Corrected the schematic for the proper orientation of the topmost
capacitor; the circuit now passes LVS.
diff --git a/netgen/comp.out b/netgen/comp.out
index 9155711..691707f 100644
--- a/netgen/comp.out
+++ b/netgen/comp.out
@@ -102,62 +102,37 @@
sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
sky130_fd_pr__pfet_g5v0d10v5 (8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
-sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (5) **Mismatc
+sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
sky130_fd_pr__res_xhigh_po_0p69 (3) |sky130_fd_pr__res_xhigh_po_0p69 (3)
sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
-Number of devices: 20 **Mismatch** |Number of devices: 22 **Mismatch**
-Number of nets: 16 **Mismatch** |Number of nets: 18 **Mismatch**
+Number of devices: 20 |Number of devices: 20
+Number of nets: 16 |Number of nets: 16
---------------------------------------------------------------------------------------
-NET mismatches: Class fragments follow (with fanout counts):
-Circuit 1: example_por |Circuit 2: example_por
+Circuits match uniquely.
+Property errors were found.
+Netlists match uniquely.
+There were property errors.
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p693 vs. sky130_fd_pr__res_xhigh_po_0p69R1:
+Property W in circuit2 has no matching property in circuit1
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p690 vs. sky130_fd_pr__res_xhigh_po_0p69R2:
+Property W in circuit2 has no matching property in circuit1
+sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0/sky130_fd_pr__res_xhigh_po_0p6918 vs. sky130_fd_pr__res_xhigh_po_0p69R3:
+Property W in circuit2 has no matching property in circuit1
----------------------------------------------------------------------------------------
-Net: vss |Net: vss
- sky130_fd_pr__cap_mim_m3_1/2 = 1 | sky130_fd_pr__cap_mim_m3_1/2 = 1
- sky130_fd_pr__cap_mim_m3_2/1 = 1 | sky130_fd_pr__cap_mim_m3_2/2 = 1
- sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 3 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 3
- sky130_fd_pr__nfet_g5v0d10v5/4 = 3 | sky130_fd_pr__nfet_g5v0d10v5/4 = 5
- sky130_fd_pr__res_xhigh_po_0p69/3 = 3 | sky130_fd_pr__res_xhigh_po_0p69/3 = 3
- sky130_fd_pr__res_xhigh_po_0p69/(1|2) = | sky130_fd_pr__res_xhigh_po_0p69/(1|2) =
- sky130_fd_sc_hvl__buf_8/VGND = 2 | sky130_fd_sc_hvl__buf_8/VGND = 2
- sky130_fd_sc_hvl__buf_8/VNB = 2 | sky130_fd_sc_hvl__buf_8/VNB = 2
- sky130_fd_sc_hvl__inv_8/VGND = 1 | sky130_fd_sc_hvl__inv_8/VGND = 1
- sky130_fd_sc_hvl__inv_8/VNB = 1 | sky130_fd_sc_hvl__inv_8/VNB = 1
- sky130_fd_sc_hvl__schmittbuf_1/VGND = 1 | sky130_fd_sc_hvl__schmittbuf_1/VGND = 1
- sky130_fd_sc_hvl__schmittbuf_1/VNB = 1 | sky130_fd_sc_hvl__schmittbuf_1/VNB = 1
- |
-Net: sky130_fd_sc_hvl__schmittbuf_1_0/A |Net: net4
- sky130_fd_pr__cap_mim_m3_2/2 = 1 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2
- sky130_fd_sc_hvl__schmittbuf_1/A = 1 | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2
- sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1 |
- sky130_fd_pr__cap_mim_m3_1/1 = 1 |
- |
-(no matching net) |Net: net1
- | sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 2
- |
-(no matching net) |Net: net11
- | sky130_fd_pr__cap_mim_m3_1/1 = 1
- | sky130_fd_pr__cap_mim_m3_2/1 = 1
- | sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1
- | sky130_fd_sc_hvl__schmittbuf_1/A = 1
----------------------------------------------------------------------------------------
-DEVICE mismatches: Class fragments follow (with node fanout counts):
+Subcircuit pins:
Circuit 1: example_por |Circuit 2: example_por
-
+-------------------------------------------|-------------------------------------------
+vdd3v3 |vdd3v3
+porb_h |porb_h
+porb_l |porb_l
+por_l |por_l
+vdd1v8 |vdd1v8
+vss |vss
---------------------------------------------------------------------------------------
-(no matching instance) |Instance: sky130_fd_pr__nfet_g5v0d10v5M5
- | (1,3) = (24,4)
- | 2 = 4
- | 4 = 24
- |
- |
-(no matching instance) |Instance: sky130_fd_pr__nfet_g5v0d10v5M2
- | (1,3) = (24,2)
- | 2 = 4
- | 4 = 24
- |
----------------------------------------------------------------------------------------
-Netlists do not match.
-Netlists do not match.
+Cell pin lists are equivalent.
+Device classes example_por and example_por are equivalent.
+Circuits match uniquely.
+Property errors were found.
+The following cells had property errors: example_por
diff --git a/xschem/example_por.sch b/xschem/example_por.sch
index 0dfa849..419c0c8 100644
--- a/xschem/example_por.sch
+++ b/xschem/example_por.sch
@@ -21,58 +21,58 @@
T {Simple power-on-reset circuit
calibrated to 500us nominal delay
no temperature compensation} 1950 -570 0 0 0.6 0.6 {}
-N 2500 -310 2500 -270 { lab=#net2}
-N 2500 -210 2500 -100 { lab=#net3}
-N 2300 -40 2300 20 { lab=#net4}
+N 2500 -310 2500 -270 { lab=#net1}
+N 2500 -210 2500 -100 { lab=#net2}
+N 2300 -40 2300 20 { lab=#net3}
N 2300 80 2300 110 { lab=vss}
N 2360 110 2500 110 { lab=vss}
N 2500 80 2500 110 { lab=vss}
-N 2400 50 2460 50 { lab=#net4}
+N 2400 50 2460 50 { lab=#net3}
N 2360 -400 2500 -400 { lab=vdd3v3}
N 2500 -400 2500 -370 { lab=vdd3v3}
N 2500 -400 2790 -400 { lab=vdd3v3}
-N 2300 -10 2370 -10 { lab=#net4}
-N 2370 -10 2370 50 { lab=#net4}
-N 2500 -290 2570 -290 { lab=#net2}
-N 2570 -340 2570 -290 { lab=#net2}
-N 2540 -340 2570 -340 { lab=#net2}
-N 2500 -190 2570 -190 { lab=#net3}
-N 2570 -240 2570 -190 { lab=#net3}
-N 2540 -240 2570 -240 { lab=#net3}
+N 2300 -10 2370 -10 { lab=#net3}
+N 2370 -10 2370 50 { lab=#net3}
+N 2500 -290 2570 -290 { lab=#net1}
+N 2570 -340 2570 -290 { lab=#net1}
+N 2540 -340 2570 -340 { lab=#net1}
+N 2500 -190 2570 -190 { lab=#net2}
+N 2570 -240 2570 -190 { lab=#net2}
+N 2540 -240 2570 -240 { lab=#net2}
N 2240 110 2360 110 { lab=vss}
N 2500 110 2630 110 { lab=vss}
N 2500 50 2630 50 { lab=vss}
N 2110 110 2240 110 { lab=vss}
N 1930 60 1930 110 { lab=vss}
-N 1930 -160 1930 0 { lab=#net6}
+N 1930 -160 1930 0 { lab=#net4}
N 1930 -400 1930 -220 { lab=vdd3v3}
N 2110 -400 2360 -400 { lab=vdd3v3}
N 1880 -190 1910 -190 { lab=vss}
N 1880 -190 1880 110 { lab=vss}
N 1880 110 1930 110 { lab=vss}
N 1880 30 1910 30 { lab=vss}
-N 2300 -310 2300 -270 { lab=#net7}
+N 2300 -310 2300 -270 { lab=#net5}
N 2300 -400 2300 -370 { lab=vdd3v3}
-N 2300 -140 2300 -100 { lab=#net5}
-N 2340 50 2400 50 { lab=#net4}
-N 2300 -210 2300 -140 { lab=#net5}
+N 2300 -140 2300 -100 { lab=#net3}
+N 2340 50 2400 50 { lab=#net3}
+N 2300 -210 2300 -140 { lab=#net3}
N 2100 80 2100 110 { lab=vss}
N 2100 110 2110 110 { lab=vss}
-N 2050 50 2060 50 { lab=#net6}
-N 2050 -70 2050 50 { lab=#net6}
-N 1930 -70 2050 -70 { lab=#net6}
+N 2050 50 2060 50 { lab=#net4}
+N 2050 -70 2050 50 { lab=#net4}
+N 1930 -70 2050 -70 { lab=#net4}
N 1930 -400 2110 -400 { lab=vdd3v3}
N 2100 -400 2100 -370 { lab=vdd3v3}
-N 2100 -310 2100 -270 { lab=#net8}
-N 2100 -210 2100 20 { lab=#net9}
+N 2100 -310 2100 -270 { lab=#net6}
+N 2100 -210 2100 20 { lab=#net7}
N 2100 50 2300 50 { lab=vss}
N 2200 50 2200 110 { lab=vss}
-N 2140 -240 2260 -240 { lab=#net9}
-N 2140 -340 2260 -340 { lab=#net8}
-N 2100 -290 2180 -290 { lab=#net8}
-N 2180 -340 2180 -290 { lab=#net8}
-N 2100 -180 2180 -180 { lab=#net9}
-N 2180 -240 2180 -180 { lab=#net9}
+N 2140 -240 2260 -240 { lab=#net7}
+N 2140 -340 2260 -340 { lab=#net6}
+N 2100 -290 2180 -290 { lab=#net6}
+N 2180 -340 2180 -290 { lab=#net6}
+N 2100 -180 2180 -180 { lab=#net7}
+N 2180 -240 2180 -180 { lab=#net7}
N 1930 -240 2100 -240 { lab=vdd3v3}
N 1930 -340 2100 -340 { lab=vdd3v3}
N 1930 110 2100 110 { lab=vss}
@@ -80,42 +80,42 @@
N 2300 -340 2500 -340 { lab=vdd3v3}
N 2400 -340 2400 -240 { lab=vdd3v3}
N 2400 -400 2400 -340 { lab=vdd3v3}
-N 2570 -240 2650 -240 { lab=#net3}
-N 2570 -340 2650 -340 { lab=#net2}
+N 2570 -240 2650 -240 { lab=#net2}
+N 2570 -340 2650 -340 { lab=#net1}
N 2690 -400 2690 -370 { lab=vdd3v3}
N 2790 -400 2790 -340 { lab=vdd3v3}
N 2690 -340 2790 -340 { lab=vdd3v3}
N 2690 -240 2790 -240 { lab=vdd3v3}
N 2790 -340 2790 -240 { lab=vdd3v3}
-N 2690 -310 2690 -270 { lab=#net10}
-N 2690 -210 2690 -150 { lab=#net11}
+N 2690 -310 2690 -270 { lab=#net8}
+N 2690 -210 2690 -150 { lab=#net9}
N 1830 30 1880 30 { lab=vss}
N 1810 60 1810 110 { lab=vss}
N 1810 110 1880 110 { lab=vss}
N 1810 -70 1810 0 { lab=vss}
N 1810 -70 1880 -70 { lab=vss}
-N 2690 -150 2690 -70 { lab=#net11}
-N 2820 -130 2820 -70 { lab=#net11}
-N 2690 -130 2820 -130 { lab=#net11}
+N 2690 -150 2690 -70 { lab=#net9}
+N 2820 -130 2820 -70 { lab=#net9}
+N 2690 -130 2820 -130 { lab=#net9}
N 2630 110 2820 110 { lab=vss}
N 2820 -10 2820 110 { lab=vss}
N 2690 -10 2690 110 { lab=vss}
-N 2820 -130 2980 -130 { lab=#net11}
-N 3060 -130 3130 -130 { lab=#net12}
-N 3090 -130 3090 60 { lab=#net12}
-N 3090 60 3130 60 { lab=#net12}
-N 3090 -40 3130 -40 { lab=#net12}
+N 2820 -130 2980 -130 { lab=#net9}
+N 3060 -130 3130 -130 { lab=#net10}
+N 3090 -130 3090 60 { lab=#net10}
+N 3090 60 3130 60 { lab=#net10}
+N 3090 -40 3130 -40 { lab=#net10}
N 3210 -130 3300 -130 { lab=porb_h}
N 3210 -40 3300 -40 { lab=porb_l}
N 3210 60 3300 60 { lab=por_l}
N 2790 -400 2840 -400 { lab=vdd3v3}
N 2820 110 2870 110 { lab=vss}
-N 2630 50 2690 50 {}
-N 2300 -100 2300 -40 {}
-N 2500 -100 2500 -30 {}
-N 2500 -30 2500 20 {}
+N 2630 50 2690 50 { lab=vss}
+N 2300 -100 2300 -40 { lab=#net3}
+N 2500 -100 2500 -30 { lab=#net2}
+N 2500 -30 2500 20 { lab=#net2}
C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X}
-C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X}
C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1
L=0.8
W=2
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
index 2d9ba11..6e8b3c8 100644
--- a/xschem/example_por_tb.sch
+++ b/xschem/example_por_tb.sch
@@ -32,5 +32,10 @@
C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
-C {devices/code.sym} 140 -270 0 0 {name=s1 only_toplevel=false value=".lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt"}
-C {devices/code.sym} 260 -270 0 0 {name=s2 only_toplevel=false value=".include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
+C {devices/code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
+C {devices/code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc"}
diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice
index 5af67cf..b58a814 100644
--- a/xschem/example_por_tb.spice
+++ b/xschem/example_por_tb.spice
@@ -1,5 +1,4 @@
**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
-.param mc_switch=0
*.opin vdd3v3
*.opin vdd1v8
*.opin porb_h
@@ -10,11 +9,11 @@
V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
**** begin user architecture code
+.param mc_switch=0
.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-
-
.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
.control
tran 1u 20m
plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
@@ -34,7 +33,7 @@
*.opin por_l
*.iopin vdd1v8
XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 net9 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
