commit 6043c956289b4a512058af52016e97088db54984
author Jorge Marin <jorge.marin.ndez@gmail.com> Fri Dec 31 16:12:11 2021 -0300
committer Jorge Marin <jorge.marin.ndez@gmail.com> Fri Dec 31 16:12:11 2021 -0300
tree d97b8548057d943f34a48c8c623416b5dc9ae876
parent 9413811347b0f50f104d2fdaa3d37589a0f21a54
parent 5e086e86a9b5ab1bb2d070a8b62e4e76046871dd

Merge branch 'main' of https://github.com/JorgeMarinN/caravel_user_project_analog into main

commited before updating README

README.md

diff --git a/README.md b/README.md
index 31e25e0..8fe1874 100644
--- a/README.md
+++ b/README.md
@@ -5,4 +5,19 @@
 
 PLL-BASED CAPACITIVE SENSOR INTERFACE
 
+This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
+
+![image](https://user-images.githubusercontent.com/93881221/147831652-41cf39a6-2140-4b39-a2b3-ab59a673443d.png)
+
+The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
+
+![image](https://user-images.githubusercontent.com/93881221/147832655-a40a443d-7c19-4a10-b0fd-b3201bb741cb.png)
+
+The characteristic plot for an average window of 10us is seen below:
+
+![image](https://user-images.githubusercontent.com/93881221/147832381-bbd27e83-ee83-4d5a-b145-8559156f3f49.png)
+
+
+
+
 Refer to [README](docs/source/index.rst) for this sample project documentation.