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foss-eda-tools / third_party / shuttle / sky130 / mpw-004 / slot-039 / 4b2dfd3bc954e017516b654341d5fbb9c06493f9
commit4b2dfd3bc954e017516b654341d5fbb9c06493f9[log] [tgz]
authorunrealismail <iyuksel@etu.edu.tr>Thu Dec 30 19:47:43 2021 +0300
committerGitHub <noreply@github.com>Thu Dec 30 19:47:43 2021 +0300
tree70cf701598079e3820aa5bc5ef7373c736bd352f
parent8b24e1c803e50474128b434cbc9387ce7f25cd6f [diff]
Update README.md
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  7. maglef/
  8. openlane/
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  11. verilog/
  12. caravel
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  15. Makefile
  16. README.md
README.md

Kasırga K0 RISC-V SoC

License UPRJ_CI Caravel Build

Table of contents

Overview

This repo contains a RISC-V based SoC (K0) that utilizes the caravel <https://github.com/efabless/caravel.git>__ chip user space. K0 is an ASIC-compatible SoC that has a RISC-V core with RV32-IM ISA and UART module @ 115200 baudrate. The repo also contains all required files to run any rv32-im tests programming through UART.

K0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga K0 using Openlane

TBA

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>__
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>__
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck <https://github.com/efabless/mpw_precheck>__