This repo contains a RISC-V based SoC (K0) that utilizes the caravel <https://github.com/efabless/caravel.git>
__ chip user space. K0 is an ASIC-compatible SoC that has a RISC-V core with RV32-IM ISA and UART module @ 115200 baudrate. The repo also contains all required files to run any rv32-im tests programming through UART.
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user_project_wrapper
.user_project_wrapper
at verilog/gl/user_project_wrapper.vuser_project_wrapper
adheres to the same pin order specified at pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>
__user_project_wrapper
adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>
__mpw-precheck <https://github.com/efabless/mpw_precheck>
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