commit	f39f35441c0b59f5e9b17a34bab389eb61dbbdfa	[log] [tgz]
author	unrealismail <iyuksel@etu.edu.tr>	Thu Dec 30 19:50:58 2021 +0300
committer	GitHub <noreply@github.com>	Thu Dec 30 19:50:58 2021 +0300
tree	c7b3dac2d799d8ae23749a68cd1346773cce8f5b
parent	4b2dfd3bc954e017516b654341d5fbb9c06493f9 [diff]

tree: c7b3dac2d799d8ae23749a68cd1346773cce8f5b

README.md

Kasırga K0 RISC-V SoC

Overview
K0 Block Diagram
Key Features
Prerequisites
Running Full Chip Simulation
Hardening the Kasirga K0 using Openlane
Checklist for Open-MPW Submission

Overview

This repo contains a RISC-V based SoC (K0) that utilizes thecaravelchip user space. K0 is an ASIC-compatible SoC that has a RISC-V core with RV32-IM ISA and UART module @ 115200 baudrate. The repo also contains all required files to run any rv32-im tests programming through UART.

K0 Block Diagram

TBA

Key Features

TBA

Prerequisites

TBA

Running Full Chip Simulation

TBA

Hardening the Kasirga K0 using Openlane

TBA

Checklist for Open-MPW Submission

✔️ The project repo adheres to the same directory structure in this repo.
✔️ The project repo contain info.yaml at the project root.
✔️ Top level macro is named user_project_wrapper.
✔️ Full Chip Simulation passes for RTL and GL (gate-level)
✔️ The hardened Macros are LVS and DRC clean
✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order
✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
✔️ XOR check passes with zero total difference.
✔️ Openlane summary reports are retained under ./signoff/
✔️ The design passes the mpw-precheck