updated verilog description
diff --git a/verilog/rtl/comparator.v b/verilog/rtl/comparator.v new file mode 100644 index 0000000..79cf28b --- /dev/null +++ b/verilog/rtl/comparator.v
@@ -0,0 +1,36 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +`timescale 1 ns / 1 ps + +// This is just a copy of simple_por.v from the Caravel project, used +// as an analog user project example. + +module comparator( +`ifdef USE_POWER_PINS + inout VDD, + inout VSS, +`endif + input VINM, + input VINP, + input VBN, + input VBP, + output VOUT +); + + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/comparator_bias.v b/verilog/rtl/comparator_bias.v new file mode 100644 index 0000000..95eb295 --- /dev/null +++ b/verilog/rtl/comparator_bias.v
@@ -0,0 +1,33 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +`timescale 1 ns / 1 ps + +// This is just a copy of simple_por.v from the Caravel project, used +// as an analog user project example. + +module comparator_bias( +`ifdef USE_POWER_PINS + inout VDD, + inout VSS, +`endif + output VBN, + output VBP +); + + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v index 94412da..6012e59 100644 --- a/verilog/rtl/user_analog_proj_example.v +++ b/verilog/rtl/user_analog_proj_example.v
@@ -140,8 +140,7 @@ // wire valid; // wire [3:0] wstrb; - wire isupply; // Independent 3.3V supply - wire io16, io15, io12, io11; + wire analog0, analog2, analog3, vbn, vbp; // WB MI A // assign valid = wbs_cyc_i && wbs_stb_i; @@ -159,61 +158,33 @@ // assign io_oeb[10:0] = 11'b1; // IO --- enable outputs on 11, 12, 15, and 16 - assign io_out[12:11] = {io12, io11}; - assign io_oeb[12:11] = {vssd1, vssd1}; + assign io_analog[0] = analog0; + assign io_analog[2] = analog2; + assign io_analog[3] = analog3; - assign io_out[16:15] = {io16, io15}; - assign io_oeb[16:15] = {vssd1, vssd1}; - // IRQ - assign irq = 3'b000; // Unused - // LA --- unused (no need to connect to anything) - // assign la_data_out = {128{1'b0}}; // Unused - - // Instantiate the POR. Connect the digital power to user area 1 - // VCCD, and connect the analog power to user area 1 VDDA. - - // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3] - // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12] - - example_por por1 ( + comparator comp1 ( `ifdef USE_POWER_PINS - .vdd3v3(vdda1), - .vdd1v8(vccd1), - .vss(vssa1), + .VDD(vdda1), + .VSS(vssa1), `endif - .porb_h(gpio_analog[3]), // 3.3V domain output - .porb_l(io11), // 1.8V domain output - .por_l(io12) // 1.8V domain output + .VINP(analog2), // 3.3V domain output + .VINM(analog3), // 1.8V domain output + .VBN(vbn), + .VBP(vbp), + .VOUT(analog0) // 1.8V domain output ); - // Instantiate 2nd POR with the analog power supply on one of the - // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same - // pad with io_clamp_high/low[0]. - `ifdef USE_POWER_PINS - assign isupply = io_analog[4]; - assign io_clamp_high[0] = isupply; - assign io_clamp_low[0] = vssa1; - // Tie off remaining clamps - assign io_clamp_high[2:1] = vssa1; - assign io_clamp_low[2:1] = vssa1; - `endif - - // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7] - // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16] - - example_por por2 ( + comparator_bias compbias1 ( `ifdef USE_POWER_PINS - .vdd3v3(isupply), - .vdd1v8(vccd1), - .vss(vssa1), + .VDD(vdda1), + .VSS(vssa1), `endif - .porb_h(gpio_analog[7]), // 3.3V domain output - .porb_l(io15), // 1.8V domain output - .por_l(io16) // 1.8V domain output + .VBN(vbn), + .VBP(vbp) ); endmodule