| commit | 58371fc1a28d00b23ef44898c2353b66d53499cf | [log] [tgz] |
|---|---|---|
| author | maherbenhouria <maher.benhouria@gmail.com> | Thu Dec 30 00:40:51 2021 -0500 |
| committer | maherbenhouria <maher.benhouria@gmail.com> | Thu Dec 30 00:40:51 2021 -0500 |
| tree | 3413ccc5e9e5c119279fcdd55922aa502ce79185 | |
| parent | c86a56e2a6655e0fafae23a415736839d0d504de [diff] |
updated includes
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v index 6012e59..c798e1e 100644 --- a/verilog/rtl/user_analog_proj_example.v +++ b/verilog/rtl/user_analog_proj_example.v
@@ -15,7 +15,8 @@ `default_nettype none -`include "example_por.v" +`include "comparator.v" +`include "comparator_bias.v" /* * I/O mapping for analog