updated includes

verilog/rtl/user_analog_proj_example.v

diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
index 6012e59..c798e1e 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -15,7 +15,8 @@
 
 `default_nettype none
 
-`include "example_por.v"
+`include "comparator.v"
+`include "comparator_bias.v"
 
 /*
  * I/O mapping for analog