changes for mpw4 made
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
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diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..cbe8fc3
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,145 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARVEL_TAG := 'rc-8'
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARVEL_TAG := 'rc-8'
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone -b $(CARVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone https://github.com/efabless/mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-precheck check-pdk check-caravel
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)"
+
+# Install PDK using OL's Docker Image
+.PHONY: pdk-nonnative
+pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks
+ docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..7141127
--- /dev/null
+++ b/README.md
@@ -0,0 +1,404 @@
+# avsd_opamp - IP Design
+
+
+This project presents the design of a Two Stage CMOS Operational Amplifier using open source SkyWater 130nm Technology
+
+  
+
+**This repository extends from the caraval wrapper for submission for tapeout
+
+# Contents
+- [Open Source Tools Used](#Open-Source-Tools-Used)
+- [Block Diagram](#Block-Diagram)
+- [Specifications](#Specifications)
+- [Installation](#Installation)
+ - [eSim Installation](#eSim-Installation)
+ - [Ngspice Installation](#Ngspice-Installation)
+ - [SkyWater PDK Installation](#SkyWater-PDK-Installation)
+ - [Magic Installation](#Magic-Installation)
+- [Clone This Project](#Clone-This-Project)
+- [Pre Layout Schematic and Simulations](#Pre-Layout-Schematic-and-Simulations)
+- [Layout Design Using Magic](#Layout-Design-Using-Magic)
+- [Post Layout Simulations](#Post-Layout-Simulations)
+- [Future Work](#Future-Work)
+- [Author](#Author)
+- [Acknowledgements](#Acknowledgements)
+
+
+# Open-Source-Tools-Used
+
+- eSim
+ - eSim (previously known as Oscad / FreeEDA) is a free/libre and open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using free/libre and open source software such as KiCad, Ngspice and GHDL. eSim is released under GPL.
+ - https://esim.fossee.in/home
+
+- Ngspice
+ - ngspice is the open source spice simulator for electric and electronic circuits.
+ - http://ngspice.sourceforge.net/
+
+- SkyWater Open Source PDK
+ - The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources, which can be used to create manufacturable designs at SkyWater’s facility.
+ - https://github.com/google/skywater-pdk
+
+- Magic
+ - Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology.
+ - http://opencircuitdesign.com/magic/
+
+# Block Diagram
+
+
+# Specifications
+
+<table align="center">
+<tr>
+ <th>Specification</th>
+ <th>Value</th>
+</tr>
+<tr>
+ <td>Differential Gain</td>
+ <td>31.55dB</td>
+</tr>
+<tr>
+ <td>CMRR</td>
+ <td>41.4dB</td>
+</tr>
+<tr>
+ <td>Gain Bandwidth Product</td>
+ <td>46MHz</td>
+</tr>
+<tr>
+ <td>Phase Margin</td>
+ <td>101.93°</td>
+</tr>
+<tr>
+ <td>Input Offset Voltage</td>
+ <td>-24.55mV</td>
+</tr>
+<tr>
+ <td>Power Dissipation at <br/>
+ 60Hz 1mV p-p sinusoid <br/>
+ with 1kΩ</td>
+ <td>17µW</td>
+</tr>
+<tr>
+ <td>Slew Rate</td>
+ <td>180 V/µs</td>
+</tr>
+</table>
+
+# Installation
+- The eSim Software is currently available for Windows 7, 8 and 10 and Ubuntu 16.04 LTS and above
+
+- The Magic Design Tool is available for Ubuntu
+- Ngspice is installed when eSim is installed, but if any other version is needed please follow the steps mentioned
+
+- The Pre-requisites for installing the following in Ubuntu are
+ - git
+ - make
+
+- Install them using
+
+ To make sure that you install the latest version of the software(that is the package information is up to date)
+ ```
+ $ sudo apt-get update
+ ```
+
+ ```
+ $ sudo apt install git
+
+ $ sudo apt install make
+ ```
+
+## eSim Installation
+Please refer to the following links for proper installation of *eSim*
+- https://static.fossee.in/esim/installation-files/Install_eSim_on_Windows.pdf
+
+- https://github.com/FOSSEE/eSim/blob/master/INSTALL
+
+## Ngspice Installation
+Please refer to the following links for proper installation of *Ngspice*
+- http://ngspice.sourceforge.net/download.html
+
+## SkyWater PDK Installation
+- In Windows
+ - Download the GitHub Repository : https://github.com/google/skywater-pdk
+
+- In Ubuntu
+In terminal, execute the following commands
+
+- To download the repository into the current working directory
+ ```
+ $ git clone git://opencircuitdesign.com/open_pdks
+ ```
+
+- Go to `open_pks` directory
+ ```
+ $ cd open_pdks
+ ```
+
+- Configure and install
+ ```
+ $ ./configure --enable-sky130-pdk
+
+ $ make
+
+ $ sudo make install
+ ```
+
+## Magic Installation
+In terminal, execute the following commands
+
+- To download the repository into the current working directory
+ ```
+ $ git clone git://opencircuitdesign.com/magic
+ ```
+
+- Go to `magic` directory
+
+ ```
+ $ cd magic
+ ```
+
+- Configure and install
+ ```
+ $ sudo ./configure
+
+ $ sudo make
+
+ $ sudo make install
+ ```
+# Clone This Project
+To Clone this repository, execute the following from terminal
+```
+$ git clone https://github.com/rohinthram/avsd_opamp
+```
+Or download and extract the files
+
+# Pre Layout Schematic and Simulations
+- Go to the directory `pre_layout/pre_layout_simulation` <br/>
+
+ ```
+ $ cd pre_layout/pre_layout_simulation
+ ```
+- Execute each and every `.cir` using `ngspice` command from terminal <br/>
+
+ ```
+ $ ngspice <file-name>
+ ```
+ - Replace `<file-name>` with file name of the analysis required
+- The necessary plot is obtained upon successful execution of the file
+
+## Differential Mode Gain
+
+```
+$ ngspice differential_gain.cir
+```
+
+
+
+
+
+## Common Mode Gain
+```
+$ ngspice common_mode_gain.cir
+```
+
+
+
+## Offset Voltage
+```
+$ ngspice offset_voltage.cir
+```
+
+
+
+## Input Noise Spectrum
+
+```
+$ ngspice input_noise_spectrum.cir
+```
+To obtain Noise Spectrum
+- Please run the following commands in the ngspice window for obtaining the plot
+
+
+- Use `setplot` to see all plots available
+
+ ```
+ ngspice-> setplot
+ ```
+
+- select the plot which has "Noise Spectral Density Curves".For example,
+ ```
+ ngspice-> setplot noise1
+ ```
+- Then plot the graph using the command
+ ```
+ ngspice-> plot inoise_spectrum
+ ```
+
+
+
+## Power Dissipation
+```
+$ ngspice power_dissipation.cir
+```
+
+
+
+## Slew Rate
+```
+$ ngspice slew_rate.cir
+```
+
+
+
+A much easier plot to see slew rate could be obtained by changing the analysis as
+```
+.tran 0.01u 2u
+```
+
+
+## Transient Analysis
+```
+$ ngspice transient.cir
+```
+
+
+
+# Layout Design Using Magic
+Copy `sky130A.tech` file and paste in the directory where we want to work with *magic*
+Or execute the following command in the terminal
+```
+cp avsd_opamp/skywater_pdk/sky130A.tech <target-destination>
+```
+
+- Magic Workspace :
+
+
+- Save the changes made using
+ ```
+ % save <file-name>
+ ```
+
+- Conversion of **.mag** file into ngspice executable
+ - Extract the **.mag** file using (from tkcon terminal)(magic terminal)
+ ```
+ % extract all
+ ```
+ - Convert **.ext** to **.spice** using
+ ```
+ % ext2spice
+ ```
+- Make necessary changes to the **.spice** file so that it can be run in `ngspice` (The modified file can be found in *post_layout/post_layout_simulations* directory)
+
+# Post Layout Simulations
+- Go to the directory `post_layout/post_layout_simulation` by executing the command from parent directory<br/>
+
+ ```
+ $ cd post_layout/post_layout_simulation
+ ```
+- Execute each and every `.cir` using `ngspice` command from terminal<br/>
+
+ ```
+ $ ngspice <file-name>
+ ```
+ - Replace `<file-name>` with file name of the analysis required
+- The necessary plot is obtained upon successful execution of the file
+
+## Differential Mode Gain
+
+```
+$ ngspice differential_gain.cir
+```
+
+
+
+
+
+## Common Mode Gain
+```
+$ ngspice common_mode_gain.cir
+```
+
+
+
+## Offset Voltage
+```
+$ ngspice offset_voltage.cir
+```
+
+
+
+## Input Noise Spectrum
+
+```
+$ ngspice input_noise_spectrum.cir
+```
+For obtaining Noise Spectrum
+- Please run the following commands in the ngspice window for obtaining the plot
+
+
+- Use `setplot` to see all plots available
+
+ ```
+ ngspice-> setplot
+ ```
+
+- select the plot which has "Noise Spectral Density Curves".For example,
+ ```
+ ngspice-> setplot noise1
+ ```
+- Then plot the graph using the command
+ ```
+ ngspice-> plot inoise_spectrum
+ ```
+
+
+
+## Power Dissipation
+```
+$ ngspice power_dissipation.cir
+```
+
+
+
+## Slew Rate
+```
+$ ngspice slew_rate.cir
+```
+
+
+
+A much easier plot to see slew rate could be obtained by changing the analysis as
+```
+.tran 0.01u 2u
+```
+
+
+## Transient Analysis
+```
+$ ngspice transient.cir
+```
+
+
+
+<blockquote>
+Note:
+<ul>
+ <li>For performing any of the simulation mentioned in this repository the <b>sky130_fd_pr</b> folder is necessary.
+ <li>All simulation given in this repository are properly linked to the <b>sky130_fd_pr</b> library. Hence files execute with no error if the <i> folders are kept as such</i>
+ <li>For any external simulation using SkyWater Models, it is a must to properly include the library
+</ul>
+</blockquote>
+
+
+# Future Work
+- The **Area** of the Operational Amplifier can be **reduced**
+- The **Gain** of the Operational Amplifier can be **increased**
+
+# Author
+- R.V.Rohinth Ram
+
+# Acknowledgements
+- Kunal Ghosh, Co-founder, VLSI System Design (VSD) Corp. Pvt. Ltd. - kunalpghosh@gmail.com
+
+---
diff --git a/caravel/Makefile b/caravel/Makefile
new file mode 100644
index 0000000..43069c9
--- /dev/null
+++ b/caravel/Makefile
@@ -0,0 +1,974 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# cannot commit files larger than 100 MB to GitHub
+FILE_SIZE_LIMIT_MB = 100
+
+# Commands to be used to compress/uncompress files
+# they must operate **in place** (otherwise, modify the target to delete the
+# intermediate file/archive)
+COMPRESS ?= gzip -n --best
+UNCOMPRESS ?= gzip -d
+ARCHIVE_EXT ?= gz
+
+# The following variables are to build static pattern rules
+
+# Needed to rebuild archives that were previously split
+SPLIT_FILES := $(shell find . -type f -name "*.$(ARCHIVE_EXT).00.split")
+SPLIT_FILES_SOURCES := $(basename $(basename $(basename $(SPLIT_FILES))))
+
+# Needed to uncompress the existing archives
+ARCHIVES := $(shell find . -type f -name "*.$(ARCHIVE_EXT)")
+ARCHIVE_SOURCES := $(basename $(ARCHIVES))
+
+# Needed to compress and split files/archives that are too large
+LARGE_FILES := $(shell find ./gds -type f -name "*.gds")
+LARGE_FILES += $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*" -not -path "./gds/*" -not -path "./openlane/*")
+LARGE_FILES_GZ := $(addsuffix .$(ARCHIVE_EXT), $(LARGE_FILES))
+LARGE_FILES_GZ_SPLIT := $(addsuffix .$(ARCHIVE_EXT).00.split, $(LARGE_FILES))
+# consider splitting existing archives
+LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES))
+
+MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+MCW ?=LITEX_VEXRISCV
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+MCW_LITE?=1
+
+ifeq ($(MCW),LITEX_VEXRISCV)
+ MCW_NAME := mcw-litex-vexriscv
+ MCW_REPO := https://github.com/efabless/caravel_mgmt_soc_litex
+ MCW_BRANCH := main
+else
+ MCW_NAME := mcw-pico
+ MCW_REPO := https://github.com/efabless/caravel_pico
+ MCW_BRANCH := main
+endif
+
+# Install caravel as submodule, (1): submodule, (0): clone
+SUBMODULE?=0
+
+# Caravel Root (Default: pwd)
+# Need to be overwritten if running the makefile from UPRJ_ROOT,
+# If caravel is sub-moduled in the user project, run export CARAVEL_ROOT=$(pwd)/caravel
+CARAVEL_ROOT ?= $(shell pwd)
+
+# User project root
+UPRJ_ROOT ?= $(shell pwd)
+
+# MANAGEMENT AREA ROOT
+MGMT_AREA_ROOT ?= $(shell pwd)/mgmt_core_wrapper
+
+# Build tasks such as make ship, make generate_fill, make set_user_id, make final run in the foreground (1) or background (0)
+FOREGROUND ?= 1
+
+# PDK setup configs
+THREADS ?= $(shell nproc)
+STD_CELL_LIBRARY ?= sky130_fd_sc_hd
+SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
+IO_LIBRARY ?= sky130_fd_io
+PRIMITIVES_LIBRARY ?= sky130_fd_pr
+SKYWATER_COMMIT ?= c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+OPEN_PDKS_COMMIT ?= 89f6ff4d9359a1ef9717b839e3e59dfdf33aaea6
+INSTALL_SRAM ?= no # = yes to enable
+
+.DEFAULT_GOAL := ship
+# We need portable GDS_FILE pointers...
+.PHONY: ship
+ship: check-env uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ @echo "Running make ship in the foreground..."
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __ship
+ @echo "Make ship completed." 2>&1 | tee -a ./signoff/build/make_ship.out
+else
+ @echo "Running make ship in the background..."
+ nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __ship >/dev/null 2>&1 &
+ tail -f signoff/build/make_ship.out
+ @echo "Make ship completed." 2>&1 | tee -a ./signoff/build/make_ship.out
+endif
+
+__ship:
+ @echo "###############################################"
+ @echo "Generating Caravel GDS (sources are in the 'gds' directory)"
+ @sleep 1
+#### Runs from the CARAVEL_ROOT mag directory
+ @echo "\
+ random seed `$(CARAVEL_ROOT)/scripts/set_user_id.py -report`; \
+ drc off; \
+ crashbackups stop; \
+ addpath hexdigits; \
+ addpath $(CARAVEL_ROOT)/mag; \
+ addpath $(UPRJ_ROOT)/mag; \
+ load user_project_wrapper; \
+ property LEFview true; \
+ property GDS_FILE $(UPRJ_ROOT)/gds/user_project_wrapper.gds; \
+ property GDS_START 0; \
+ load mgmt_core_wrapper; \
+ property LEFview true; \
+ property GDS_FILE ../mgmt_core_wrapper/gds/mgmt_core_wrapper.gds; \
+ property GDS_START 0; \
+ load $(UPRJ_ROOT)/mag/user_id_programming; \
+ load $(UPRJ_ROOT)/mag/user_id_textblock; \
+ load ../maglef/simple_por; \
+ load $(UPRJ_ROOT)/mag/caravel -dereference; \
+ select top cell; \
+ expand; \
+ cif *hier write disable; \
+ cif *array write disable; \
+ gds write $(UPRJ_ROOT)/gds/caravel.gds; \
+ quit -noprompt;" > $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl
+### Runs from CARAVEL_ROOT
+ @mkdir -p ./signoff/build
+ #@cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A MAGTYPE=mag magic -noc -dnull -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_ship.out
+ @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A MAGTYPE=mag magic -noc -dnull -rcfile ./.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_ship.out
+### @rm $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl
+
+truck: check-env uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ @echo "Running make truck in the foreground..."
+ mkdir -p ./signoff
+ mkdir -p ./build
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __truck
+ @echo "Make truck completed." 2>&1 | tee -a ./signoff/build/make_truck.out
+else
+ @echo "Running make truck in the background..."
+ mkdir -p ./signoff
+ mkdir -p ./build
+ nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __truck >/dev/null 2>&1 &
+ tail -f signoff/build/make_truck.out
+ @echo "Make truck completed." 2>&1 | tee -a ./signoff/build/make_truck.out
+endif
+
+__truck:
+ @echo "###############################################"
+ @echo "Generating Caravan GDS (sources are in the 'gds' directory)"
+ @sleep 1
+#### Runs from the CARAVEL_ROOT mag directory
+ @echo "\
+ random seed `$(CARAVEL_ROOT)/scripts/set_user_id.py -report`; \
+ drc off; \
+ crashbackups stop; \
+ addpath hexdigits; \
+ addpath $(CARAVEL_ROOT)/mag; \
+ addpath $(UPRJ_ROOT)/mag; \
+ load user_analog_project_wrapper; \
+ property LEFview true; \
+ property GDS_FILE $(UPRJ_ROOT)/gds/user_analog_project_wrapper.gds; \
+ property GDS_START 0; \
+ load mgmt_core_wrapper; \
+ property LEFview true; \
+ property GDS_FILE ../mgmt_core_wrapper/gds/mgmt_core_wrapper.gds; \
+ property GDS_START 0; \
+ load $(UPRJ_ROOT)/mag/user_id_programming; \
+ load $(UPRJ_ROOT)/mag/user_id_textblock; \
+ load ../maglef/simple_por; \
+ load $(UPRJ_ROOT)/mag/caravan -dereference; \
+ select top cell; \
+ expand; \
+ cif *hier write disable; \
+ cif *array write disable; \
+ gds write $(UPRJ_ROOT)/gds/caravan.gds; \
+ quit -noprompt;" > $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl
+### Runs from CARAVEL_ROOT
+ @mkdir -p ./signoff/build
+ #@cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A MAGTYPE=mag magic -noc -dnull -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_truck.out
+ @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/sky130A MAGTYPE=mag magic -noc -dnull -rcfile ./.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_truck.out
+### @rm $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl
+
+.PHONY: clean
+clean:
+ cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) clean
+ cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) clean
+
+
+.PHONY: verify
+verify:
+ cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \
+ $(MAKE) -j$(THREADS) all
+ cd $(CARAVEL_ROOT)/verilog/dv/wb_utests/ && \
+ $(MAKE) -j$(THREADS) all
+
+
+
+#####
+$(LARGE_FILES_GZ): %.$(ARCHIVE_EXT): %
+ @if ! [ $(suffix $<) = ".$(ARCHIVE_EXT)" ]; then\
+ $(COMPRESS) $< > /dev/null &&\
+ echo "$< -> $@";\
+ fi
+
+$(LARGE_FILES_GZ_SPLIT): %.$(ARCHIVE_EXT).00.split: %.$(ARCHIVE_EXT)
+ @if [ -n "$$(find "$<" -prune -size +$(FILE_SIZE_LIMIT_MB)M)" ]; then\
+ split $< -b $(FILE_SIZE_LIMIT_MB)M $<. -d &&\
+ rm $< &&\
+ for file in $$(ls $<.*); do mv "$$file" "$$file.split"; done &&\
+ echo -n "$< -> $$(ls $<.*.split)" | tr '\n' ' ' && echo "";\
+ fi
+
+# This target compresses all files larger than $(FILE_SIZE_LIMIT_MB) MB
+.PHONY: compress
+compress: $(LARGE_FILES_GZ) $(LARGE_FILES_GZ_SPLIT)
+ @echo "Files larger than $(FILE_SIZE_LIMIT_MB) MBytes are compressed!"
+
+
+
+#####
+$(ARCHIVE_SOURCES): %: %.$(ARCHIVE_EXT)
+ @$(UNCOMPRESS) $<
+ @echo "$< -> $@"
+
+.SECONDEXPANSION:
+$(SPLIT_FILES_SOURCES): %: $$(sort $$(wildcard %.$(ARCHIVE_EXT).*.split))
+ @cat $? > $@.$(ARCHIVE_EXT)
+ @rm $?
+ @echo "$? -> $@.$(ARCHIVE_EXT)"
+ @$(UNCOMPRESS) $@.$(ARCHIVE_EXT)
+ @echo "$@.$(ARCHIVE_EXT) -> $@"
+
+
+.PHONY: uncompress
+uncompress: $(SPLIT_FILES_SOURCES) $(ARCHIVE_SOURCES)
+ @echo "All files are uncompressed!"
+
+# Needed for targets that are run from UPRJ_ROOT for which caravel isn't submoduled.
+.PHONY: uncompress-caravel
+uncompress-caravel:
+ cd $(CARAVEL_ROOT) && \
+ $(MAKE) uncompress
+
+# Digital Wrapper
+# verify that the wrapper was respected
+xor-wrapper: uncompress uncompress-caravel
+### first erase the user's user_project_wrapper.gds
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh gds/user_project_wrapper.gds 0 0 2920 3520
+### do the same for the empty wrapper
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh $(CARAVEL_ROOT)/gds/user_project_wrapper_empty.gds 0 0 2920 3520
+ mkdir -p signoff/user_project_wrapper_xor
+### XOR the two resulting layouts
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper user_project_wrapper.xor.xml
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds \
+ user_project_wrapper gds/user_project_wrapper.xor.gds > signoff/user_project_wrapper_xor/xor.log
+ rm $(CARAVEL_ROOT)/gds/user_project_wrapper_empty_erased.gds gds/user_project_wrapper_erased.gds
+ mv gds/user_project_wrapper.xor.gds gds/user_project_wrapper.xor.xml signoff/user_project_wrapper_xor
+ python $(CARAVEL_ROOT)/utils/parse_klayout_xor_log.py \
+ -l signoff/user_project_wrapper_xor/xor.log \
+ -o signoff/user_project_wrapper_xor/total.txt
+### screenshot the result for convenience
+ sh $(CARAVEL_ROOT)/utils/scrotLayout.sh \
+ $(PDK_ROOT)/sky130A/libs.tech/klayout/sky130A.lyt \
+ signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds
+ @cat signoff/user_project_wrapper_xor/total.txt
+
+# Analog Wrapper
+# verify that the wrapper was respected
+xor-analog-wrapper: uncompress uncompress-caravel
+### first erase the user's user_project_wrapper.gds
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh gds/user_analog_project_wrapper.gds 0 0 2920 3520 -8 -8
+### do the same for the empty wrapper
+ sh $(CARAVEL_ROOT)/utils/erase_box.sh $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty.gds 0 0 2920 3520 -8 -8
+ mkdir -p signoff/user_analog_project_wrapper_xor
+### XOR the two resulting layouts
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds \
+ user_analog_project_wrapper user_analog_project_wrapper.xor.xml
+ sh $(CARAVEL_ROOT)/utils/xor.sh \
+ $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds \
+ user_analog_project_wrapper gds/user_analog_project_wrapper.xor.gds > signoff/user_analog_project_wrapper_xor/xor.log
+ rm $(CARAVEL_ROOT)/gds/user_analog_project_wrapper_empty_erased.gds gds/user_analog_project_wrapper_erased.gds
+ mv gds/user_analog_project_wrapper.xor.gds gds/user_analog_project_wrapper.xor.xml signoff/user_analog_project_wrapper_xor
+ python $(CARAVEL_ROOT)/utils/parse_klayout_xor_log.py \
+ -l signoff/user_analog_project_wrapper_xor/xor.log \
+ -o signoff/user_analog_project_wrapper_xor/total.txt
+### screenshot the result for convenience
+ sh $(CARAVEL_ROOT)/utils/scrotLayout.sh \
+ $(PDK_ROOT)/sky130A/libs.tech/klayout/sky130A.lyt \
+ signoff/user_analog_project_wrapper_xor/user_analog_project_wrapper.xor.gds
+ @cat signoff/user_analog_project_wrapper_xor/total.txt
+
+# LVS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./mag/tmp
+ echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+ addpath $(CARAVEL_ROOT)/subcells/simple_por/mag;\
+ addpath \$$PDKPATH/libs.ref/sky130_ml_xx_hd/mag;\
+ load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract unique;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && \
+ export MAGTYPE=maglef; \
+ magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./mag/*.ext
+ mv -f ./mag/extract_$*.tcl ./mag/tmp
+ mv -f ./mag/extract_$*.log ./mag/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+
+LVS_GDS_BLOCKS = $(foreach block, $(BLOCKS), lvs-gds-$(block))
+$(LVS_GDS_BLOCKS): lvs-gds-% : ./gds/%.gds ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./gds/tmp
+ echo " gds flatglob \"*_example_*\";\
+ gds flatten true;\
+ gds read ./$*.gds;\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./gds/extract_$*.tcl
+ cd gds && \
+ magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull extract_$*.tcl < /dev/null
+ mv ./gds/$*.spice ./spi/lvs
+ rm ./gds/*.ext
+ mv -f ./gds/extract_$*.tcl ./gds/tmp
+ mv -f ./gds/extract_$*.log ./gds/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ MAGIC_EXT_USE_GDS=1 sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+
+# connect-by-label is enabled here!
+LVS_MAGLEF_BLOCKS = $(foreach block, $(BLOCKS), lvs-maglef-$(block))
+$(LVS_MAGLEF_BLOCKS): lvs-maglef-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./maglef/tmp
+ echo "load $* -dereference;\
+ select top cell;\
+ foreach cell [cellname list children] {\
+ load \$$cell -dereference;\
+ property LEFview TRUE;\
+ };\
+ load $* -dereference;\
+ select top cell;\
+ extract no all;\
+ extract do local;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice $*.ext;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && export MAGTYPE=maglef; magic -noc -dnull extract_$*.tcl < /dev/null
+ mv ./mag/$*.spice ./spi/lvs
+ rm ./maglef/*.ext
+ mv -f ./mag/extract_$*.tcl ./maglef/tmp
+ mv -f ./mag/extract_$*.log ./maglef/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh $(CARAVEL_ROOT)/spi/lvs/run_lvs.sh ./spi/lvs/$*.spice ./verilog/gl/$*.v $*
+ @echo ""
+ python3 $(CARAVEL_ROOT)/scripts/count_lvs.py -f ./verilog/gl/$*.v_comp.json | tee ./spi/lvs/tmp/$*.maglef.lvs.summary.log
+ mv -f ./verilog/gl/*.out ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.json ./spi/lvs/tmp 2> /dev/null || true
+ mv -f ./verilog/gl/*.log ./spi/lvs/tmp 2> /dev/null || true
+ @echo ""
+ @echo "LVS: ./spi/lvs/$*.spice vs. ./verilog/gl/$*.v"
+ @echo "Comparison result: ./spi/lvs/tmp/$*.v_comp.out"
+ @awk '/^NET mismatches/,0' ./spi/lvs/tmp/$*.v_comp.out
+
+# DRC
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+DRC_BLOCKS = $(foreach block, $(BLOCKS), drc-$(block))
+$(DRC_BLOCKS): drc-% : ./gds/%.gds
+ echo "Running DRC on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_DRC=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull $(CARAVEL_ROOT)/gds/drc_on_gds.tcl < /dev/null
+ @echo "DRC result: ./gds/tmp/$*.drc"
+
+# Antenna
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+ANTENNA_BLOCKS = $(foreach block, $(BLOCKS), antenna-$(block))
+$(ANTENNA_BLOCKS): antenna-% : ./gds/%.gds
+ echo "Running Antenna Checks on $*"
+ mkdir -p ./gds/tmp
+ cd gds && export DESIGN_IN_ANTENNA=$* && export MAGTYPE=mag; magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull $(CARAVEL_ROOT)/gds/antenna_on_gds.tcl < /dev/null 2>&1 | tee ./tmp/$*.antenna
+ mv -f ./gds/*.ext ./gds/tmp/
+ @echo "Antenna result: ./gds/tmp/$*.antenna"
+
+# MAG2GDS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+MAG_BLOCKS = $(foreach block, $(BLOCKS), mag2gds-$(block))
+$(MAG_BLOCKS): mag2gds-% : ./mag/%.mag uncompress
+ echo "Converting mag file $* to GDS..."
+ echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
+ addpath $(CARAVEL_ROOT)/mag/primitives;\
+ drc off;\
+ gds rescale false;\
+ load $* -dereference;\
+ select top cell;\
+ expand;\
+ gds write $*.gds;\
+ exit;" > ./mag/mag2gds_$*.tcl
+ cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2gds_$*.tcl < /dev/null
+ rm ./mag/mag2gds_$*.tcl
+ mv -f ./mag/$*.gds ./gds/
+
+# MAG2LEF
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+MAG_BLOCKS = $(foreach block, $(BLOCKS), mag2lef-$(block))
+$(MAG_BLOCKS): mag2lef-% : ./mag/%.mag uncompress
+ echo "Converting mag file $* to LEF..."
+ echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
+ addpath $(CARAVEL_ROOT)/mag/primitives;\
+ drc off;\
+ load $*;\
+ lef write $*.lef;\
+ exit;" > ./mag/mag2lef_$*.tcl
+ cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2lef_$*.tcl < /dev/null
+ rm ./mag/mag2lef_$*.tcl
+ mv -f ./mag/$*.lef ./lef/
+
+# MAG2DEF
+# BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+# MAG_BLOCKS = $(foreach block, $(BLOCKS), mag2lef-$(block))
+# $(MAG_BLOCKS): mag2lef-% : ./mag/%.mag uncompress
+# echo "Converting mag file $* to DEF..."
+# echo "addpath $(CARAVEL_ROOT)/mag/hexdigits;\
+# addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag;\
+# addpath $(CARAVEL_ROOT)/mag/primitives;\
+# drc off;\
+# load $*;\
+# lef write $*.lef;\
+# exit;" > ./mag/mag2lef_$*.tcl
+# cd ./mag && magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/sky130A.magicrc -noc -dnull mag2lef_$*.tcl < /dev/null
+# rm ./mag/mag2lef_$*.tcl
+# mv -f ./mag/$*.lef ./lef/
+
+.PHONY: help
+help:
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+# RCX Extraction
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+RCX_BLOCKS = $(foreach block, $(BLOCKS), rcx-$(block))
+OPENLANE_IMAGE_NAME=efabless/openlane:2021.11.23_01.42.34
+$(RCX_BLOCKS): rcx-% : ./def/%.def check-mcw
+ echo "Running RC Extraction on $*"
+ mkdir -p ./def/tmp
+ # merge techlef and standard cell lef files
+ python3 $(OPENLANE_ROOT)/scripts/mergeLef.py -i $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/techlef/$(STD_CELL_LIBRARY).tlef $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lef/*.lef \
+ $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/techlef/$(SPECIAL_VOLTAGE_LIBRARY).tlef $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lef/*.lef \
+ $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lef/*.lef $(PDK_ROOT)/sky130A/libs.ref/$(PRIMITIVES_LIBRARY)/lef/*.lef \
+ -o ./def/tmp/merged.lef
+
+ echo "\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30_lv1v80.lib;\
+ set std_cell_lef ./def/tmp/merged.lef;\
+ set mgmt_area_lef $(MCW_ROOT)/lef/mgmt_core_wrapper.lef;\
+ if {[catch {read_lef \$$std_cell_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ foreach lef_file [glob ./lef/*.lef] {\
+ if {[catch {read_lef \$$lef_file} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ }\
+ };\
+ if {[catch {read_lef \$$mgmt_area_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ if {[catch {read_def -order_wires ./def/$*.def} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ read_sdc ./sdc/$*.sdc;\
+ set_propagated_clock [all_clocks];\
+ set rc_values \"mcon 9.249146E-3,via 4.5E-3,via2 3.368786E-3,via3 0.376635E-3,via4 0.00580E-3\";\
+ set vias_rc [split \$$rc_values ","];\
+ foreach via_rc \$$vias_rc {\
+ set layer_name [lindex \$$via_rc 0];\
+ set resistance [lindex \$$via_rc 1];\
+ set_layer_rc -via \$$layer_name -resistance \$$resistance;\
+ };\
+ set_wire_rc -signal -layer met2;\
+ set_wire_rc -clock -layer met5;\
+ define_process_corner -ext_model_index 0 X;\
+ extract_parasitics -ext_model_file ${PDK_ROOT}/sky130A/libs.tech/openlane/rcx_rules.info -corner_cnt 1 -max_res 50 -coupling_threshold 0.1 -cc_model 10 -context_depth 5;\
+ write_spef ./spef/$*.spef" > ./def/tmp/rcx_$*.tcl
+## Generate Spef file
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow -v $(PDK_ROOT):$(PDK_ROOT) -v $(PWD):/caravel -v $(MCW_ROOT):$(MCW_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) \
+ sh -c " cd /caravel; openroad -exit ./def/tmp/rcx_$*.tcl |& tee ./def/tmp/rcx_$*.log"
+## Run OpenSTA
+ echo "\
+ set std_cell_lef ./def/tmp/merged.lef;\
+ set mgmt_area_lef $(MCW_ROOT)/lef/mgmt_core_wrapper.lef;\
+ if {[catch {read_lef \$$std_cell_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ foreach lef_file [glob ./lef/*.lef] {\
+ if {[catch {read_lef \$$lef_file} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ }\
+ };\
+ if {[catch {read_lef \$$mgmt_area_lef} errmsg]} {\
+ puts stderr \$$errmsg;\
+ exit 1;\
+ };\
+ set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30_lv1v80.lib;\
+ read_def ./def/$*.def;\
+ read_spef ./spef/$*.spef;\
+ read_sdc -echo ./sdc/$*.sdc;\
+ write_sdf ./sdf/$*.sdf;\
+ report_checks -fields {capacitance slew input_pins nets fanout} -path_delay min_max -group_count 1000;\
+ report_check_types -max_slew -max_capacitance -max_fanout -violators;\
+ report_checks -to [all_outputs] -group_count 1000;\
+ report_checks -to [all_outputs] -unconstrained -group_count 1000;\
+ " > ./def/tmp/or_sta_$*.tcl
+ docker run -it -v $(OPENLANE_ROOT):/openLANE_flow -v $(PDK_ROOT):$(PDK_ROOT) -v $(PWD):/caravel -v $(MCW_ROOT):$(MCW_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) \
+ sh -c "cd /caravel; openroad -exit ./def/tmp/or_sta_$*.tcl |& tee ./def/tmp/or_sta_$*.log"
+
+
+caravel_timing: ./def/caravel.def ./sdc/caravel.sdc ./verilog/gl/caravel.v check-mcw
+ mkdir -p ./def/tmp
+## Run OpenSTA
+ echo "\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(SPECIAL_VOLTAGE_LIBRARY)/lib/$(SPECIAL_VOLTAGE_LIBRARY)__tt_025C_3v30_lv1v80.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib;\
+ read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(IO_LIBRARY)/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib;\
+ read_verilog $(MCW_ROOT)/verilog/gl/mgmt_core.v;\
+ read_verilog $(MCW_ROOT)/verilog/gl/DFFRAM.v;\
+ read_verilog $(MCW_ROOT)/verilog/gl/mgmt_core_wrapper.v;\
+ read_verilog ./verilog/gl/caravel_clocking.v;\
+ read_verilog ./verilog/gl/digital_pll.v;\
+ read_verilog ./verilog/gl/housekeeping.v;\
+ read_verilog ./verilog/gl/gpio_logic_high.v;\
+ read_verilog ./verilog/gl/gpio_control_block.v;\
+ read_verilog ./verilog/gl/gpio_defaults_block.v;\
+ read_verilog ./verilog/gl/gpio_defaults_block_0403.v;\
+ read_verilog ./verilog/gl/gpio_defaults_block_1803.v;\
+ read_verilog ./verilog/gl/mgmt_protect_hv.v;\
+ read_verilog ./verilog/gl/mprj_logic_high.v;\
+ read_verilog ./verilog/gl/mprj2_logic_high.v;\
+ read_verilog ./verilog/gl/mgmt_protect.v;\
+ read_verilog ./verilog/gl/user_id_programming.v;\
+ read_verilog ./verilog/gl/xres_buf.v;\
+ read_verilog ./verilog/gl/spare_logic_block.v;\
+ read_verilog ./verilog/gl/chip_io.v;\
+ read_verilog ./verilog/gl/caravel.v;\
+ link_design caravel;\
+ read_spef -path soc/DFFRAM_0 $(MCW_ROOT)/spef/DFFRAM.spef;\
+ read_spef -path soc/core $(MCW_ROOT)/spef/mgmt_core.spef;\
+ read_spef -path soc $(MCW_ROOT)/spef/mgmt_core_wrapper.spef;\
+ read_spef -path padframe ./spef/chip_io.spef;\
+ read_spef -path rstb_level ./spef/xres_buf.spef;\
+ read_spef -path pll ./spef/digital_pll.spef;\
+ read_spef -path housekeeping ./spef/housekeeping.spef;\
+ read_spef -path mgmt_buffers/powergood_check ./spef/mgmt_protect_hv.spef;\
+ read_spef -path mgmt_buffers/mprj_logic_high_inst ./spef/mprj_logic_high.spef;\
+ read_spef -path mgmt_buffers/mprj2_logic_high_inst ./spef/mprj2_logic_high.spef;\
+ read_spef -path mgmt_buffers ./spef/mgmt_protect.spef;\
+ read_spef -path \gpio_control_bidir_1[0] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_bidir_1[1] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_bidir_2[1] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_bidir_2[2] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[0] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[10] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[1] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[2] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[3] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[4] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[5] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[6] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[7] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[8] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1[9] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[0] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[1] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[2] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[3] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[4] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_1a[5] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[0] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[10] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[11] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[12] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[13] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[14] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[15] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[1] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[2] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[3] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[4] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[5] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[6] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[7] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[8] ./spef/gpio_control_block.spef;\
+ read_spef -path \gpio_control_in_2[9] ./spef/gpio_control_block.spef;\
+ read_spef -path gpio_defaults_block_0 ./spef/gpio_defaults_block_1803.spef;\
+ read_spef -path gpio_defaults_block_1 ./spef/gpio_defaults_block_1803.spef;\
+ read_spef -path gpio_defaults_block_2 ./spef/gpio_defaults_block_0403.spef;\
+ read_spef -path gpio_defaults_block_3 ./spef/gpio_defaults_block_0403.spef;\
+ read_spef -path gpio_defaults_block_4 ./spef/gpio_defaults_block_0403.spef;\
+ read_spef -path gpio_defaults_block_5 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_6 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_7 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_8 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_9 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_10 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_11 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_12 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_13 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_14 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_15 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_16 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_17 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_18 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_19 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_20 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_21 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_22 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_23 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_24 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_25 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_26 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_27 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_28 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_29 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_30 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_31 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_32 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_33 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_34 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_35 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_36 ./spef/gpio_defaults_block.spef;\
+ read_spef -path gpio_defaults_block_37 ./spef/gpio_defaults_block.spef;\
+ read_sdc -echo ./sdc/caravel.sdc;\
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50;\
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50;\
+ report_worst_slack -max ;\
+ report_worst_slack -min ;\
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10;\
+ " > ./def/tmp/caravel_timing.tcl
+ sta -exit ./def/tmp/caravel_timing.tcl | tee ./signoff/caravel/caravel_timing.log
+
+
+###########################################################################
+.PHONY: generate_fill
+generate_fill: check-env check-uid check-project uncompress
+ifeq ($(FOREGROUND),1)
+ @echo "Running generate_fill in the foreground..."
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __generate_fill
+ @echo "Generate fill completed." 2>&1 | tee -a ./signoff/build/generate_fill.out
+else
+ @echo "Running generate_fill in the background..."
+ @nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __generate_fill >/dev/null 2>&1 &
+ tail -f signoff/build/generate_fill.out
+ @echo "Generate fill completed." | tee -a signoff/build/generate_fill.out
+endif
+
+__generate_fill:
+ @mkdir -p ./signoff/build
+ @cp -r $(CARAVEL_ROOT)/mag/.magicrc $(shell pwd)/mag
+ python3 $(CARAVEL_ROOT)/scripts/generate_fill.py $(USER_ID) $(PROJECT) $(shell pwd) -dist 2>&1 | tee ./signoff/build/generate_fill.out
+ #python3 $(CARAVEL_ROOT)/scripts/generate_fill.py $(USER_ID) $(PROJECT) $(shell pwd) -keep 2>&1 | tee ./signoff/build/generate_fill.out
+
+
+.PHONY: final
+final: check-env check-uid check-project uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __final
+ @echo "Final build completed." 2>&1 | tee -a ./signoff/build/final_build.out
+else
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __final >/dev/null 2>&1 &
+ tail -f signoff/build/final_build.out
+ @echo "Final build completed." 2>&1 | tee -a ./signoff/build/final_build.out
+endif
+
+__final:
+ python3 $(CARAVEL_ROOT)/scripts/compositor.py $(USER_ID) $(PROJECT) $(shell pwd) $(CARAVEL_ROOT)/mag $(shell pwd)/gds -keep
+ #mv $(CARAVEL_ROOT)/mag/caravel_$(USER_ID).mag ./mag/
+ @rm -rf ./mag/tmp
+
+.PHONY: set_user_id
+set_user_id: check-env check-uid uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __set_user_id
+ @echo "Set user ID completed." 2>&1 | tee -a ./signoff/build/set_user_id.out
+else
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __set_user_id >/dev/null 2>&1 &
+ tail -f signoff/build/set_user_id.out
+ @echo "Set user ID completed." 2>&1 | tee -a ./signoff/build/set_user_id.out
+endif
+
+__set_user_id:
+ mkdir -p ./signoff/build
+ # Update info.yaml
+ # sed -r "s/^(\s*project_id\s*:\s*).*/\1${USER_ID}/" -i info.yaml
+ cp $(CARAVEL_ROOT)/gds/user_id_programming.gds ./gds/user_id_programming.gds
+ cp $(CARAVEL_ROOT)/mag/user_id_programming.mag ./mag/user_id_programming.mag
+ cp $(CARAVEL_ROOT)/mag/user_id_textblock.mag ./mag/user_id_textblock.mag
+ cp $(CARAVEL_ROOT)/verilog/rtl/caravel.v ./verilog/rtl/caravel.v
+ python3 $(CARAVEL_ROOT)/scripts/set_user_id.py $(USER_ID) $(shell pwd) 2>&1 | tee ./signoff/build/set_user_id.out
+
+.PHONY: gpio_defaults
+gpio_defaults: check-env uncompress uncompress-caravel
+ifeq ($(FOREGROUND),1)
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __gpio_defaults
+ @echo "GPIO defaults completed." 2>&1 | tee -a ./signoff/build/__gpio_defaults.out
+else
+ $(MAKE) -f $(CARAVEL_ROOT)/Makefile __gpio_defaults >/dev/null 2>&1 &
+ tail -f signoff/build/gpio_defaults.out
+ @echo "GPIO defaults completed." 2>&1 | tee -a ./signoff/build/__gpio_defaults.out
+endif
+
+__gpio_defaults:
+ mkdir -p ./signoff/build
+ mkdir -p ./verilog/gl
+ python3 $(CARAVEL_ROOT)/scripts/gen_gpio_defaults.py $(shell pwd) 2>&1 | tee ./signoff/build/gpio_defaults.out
+
+.PHONY: update_caravel
+update_caravel:
+ cd caravel/ && \
+ git checkout master && \
+ git pull
+
+###########################################################################
+
+# Install Mgmt Core Wrapper
+.PHONY: install_mcw
+install_mcw:
+ifeq ($(SUBMODULE),1)
+ @echo "Installing $(MCW_NAME) as a submodule.."
+# Convert MCW_ROOT to relative path because .gitmodules doesn't accept '/'
+ $(eval MCW_PATH := $(shell realpath --relative-to=$(shell pwd) $(MCW_ROOT)))
+ @if [ ! -d $(MCW_ROOT) ]; then git submodule add --name $(MCW_NAME) $(MCW_REPO) $(MCW_PATH); fi
+ @git submodule update --init
+ @cd $(MCW_ROOT); git checkout $(MCW_BRANCH)
+ $(MAKE) simlink
+else
+ @echo "Installing $(MCW_NAME).."
+ @git clone $(MCW_REPO) $(MCW_ROOT)
+ @cd $(MCW_ROOT); git checkout $(MCW_BRANCH)
+endif
+
+# Update Mgmt Core Wrapper
+.PHONY: update_mcw
+update_mcw: check-mcw
+ifeq ($(SUBMODULE),1)
+ @git submodule update --init --recursive
+ cd $(MCW_ROOT) && \
+ git checkout $(MCW_BRANCH) && \
+ git pull
+else
+ cd $(MCW_ROOT)/ && \
+ git checkout $(MCW_BRANCH) && \
+ git pull
+endif
+
+# Uninstall Mgmt Core Wrapper
+.PHONY: uninstall_mcw
+uninstall_mcw:
+ifeq ($(SUBMODULE),1)
+ git config -f .gitmodules --remove-section "submodule.$(MCW_NAME)"
+ git add .gitmodules
+ git submodule deinit -f $(MCW_ROOT)
+ git rm --cached $(MCW_ROOT)
+ rm -rf .git/modules/$(MCW_NAME)
+ rm -rf $(MCW_ROOT)
+else
+ rm -rf $(MCW_ROOT)/*
+endif
+
+###########################################################################
+.PHONY: pdk
+pdk: skywater-pdk skywater-library skywater-timing open_pdks build-pdk gen-sources
+
+$(PDK_ROOT)/skywater-pdk:
+ git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk
+
+.PHONY: skywater-pdk
+skywater-pdk: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git checkout main && git pull && \
+ git checkout -qf $(SKYWATER_COMMIT)
+
+.PHONY: skywater-library
+skywater-library: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ git submodule update --init libraries/$(STD_CELL_LIBRARY)/latest && \
+ git submodule update --init libraries/$(IO_LIBRARY)/latest && \
+ git submodule update --init libraries/$(SPECIAL_VOLTAGE_LIBRARY)/latest && \
+ git submodule update --init libraries/$(PRIMITIVES_LIBRARY)/latest
+
+gen-sources: $(PDK_ROOT)/sky130A
+ touch $(PDK_ROOT)/sky130A/SOURCES
+ echo -ne "skywater-pdk " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/skywater-pdk && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+ echo -ne "open_pdks " >> $(PDK_ROOT)/sky130A/SOURCES
+ cd $(PDK_ROOT)/open_pdks && git rev-parse HEAD >> $(PDK_ROOT)/sky130A/SOURCES
+
+skywater-timing: check-env $(PDK_ROOT)/skywater-pdk
+ cd $(PDK_ROOT)/skywater-pdk && \
+ $(MAKE) timing
+### OPEN_PDKS
+$(PDK_ROOT)/open_pdks:
+ git clone git://opencircuitdesign.com/open_pdks $(PDK_ROOT)/open_pdks
+
+.PHONY: open_pdks
+open_pdks: check-env $(PDK_ROOT)/open_pdks
+ cd $(PDK_ROOT)/open_pdks && \
+ git checkout master && git pull && \
+ git checkout -qf $(OPEN_PDKS_COMMIT)
+
+.PHONY: build-pdk
+build-pdk: check-env $(PDK_ROOT)/open_pdks $(PDK_ROOT)/skywater-pdk
+ [ -d $(PDK_ROOT)/sky130A ] && \
+ (echo "Warning: A sky130A build already exists under $(PDK_ROOT). It will be deleted first!" && \
+ sleep 5 && \
+ rm -rf $(PDK_ROOT)/sky130A) || \
+ true
+ cd $(PDK_ROOT)/open_pdks && \
+ ./configure --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries --with-sky130-local-path=$(PDK_ROOT) --enable-sram-sky130=$(INSTALL_SRAM) && \
+ cd sky130 && \
+ $(MAKE) veryclean && \
+ $(MAKE) && \
+ make SHARED_PDKS_PATH=$(PDK_ROOT) install && \
+ $(MAKE) clean
+
+.RECIPE: manifest
+manifest: mag/ maglef/ verilog/rtl/ Makefile
+ touch manifest && \
+ find verilog/rtl/* -type f ! -name "caravel_netlists.v" ! -name "user_*.v" ! -name "README" ! -name "defines.v" -exec shasum {} \; > manifest && \
+ shasum scripts/set_user_id.py scripts/generate_fill.py scripts/compositor.py >> manifest
+# shasum lef/user_project_wrapper_empty.lef >> manifest
+# find maglef/*.mag -type f ! -name "user_project_wrapper.mag" -exec shasum {} \; >> manifest && \
+# shasum mag/caravel.mag mag/.magicrc >> manifest
+
+.RECIPE: master_manifest
+master_manifest:
+ find verilog/rtl/* -type f -exec shasum {} \; > master_manifest && \
+ find verilog/gl/* -type f -exec shasum {} \; >> master_manifest && \
+ shasum scripts/set_user_id.py scripts/generate_fill.py scripts/compositor.py >> master_manifest && \
+ find lef/*.lef -type f -exec shasum {} \; >> master_manifest && \
+ find def/*.def -type f -exec shasum {} \; >> master_manifest && \
+ find mag/*.mag -type f -exec shasum {} \; >> master_manifest && \
+ find maglef/*.mag -type f -exec shasum {} \; >> master_manifest && \
+ find spi/lvs/*.spice -type f -exec shasum {} \; >> master_manifest && \
+ find gds/*.gds -type f -exec shasum {} \; >> master_manifest
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+check-uid:
+ifndef USER_ID
+ $(error USER_ID is undefined, please export it before running make set_user_id)
+else
+ @echo USER_ID is set to $(USER_ID)
+endif
+
+check-project:
+ifndef PROJECT
+ $(error PROJECT is undefined, please export it before running make generate_fill or make final)
+else
+ @echo PROJECT is set to $(PROJECT)
+endif
+
+check-mcw:
+ @if [ ! -d "$(MCW_ROOT)" ]; then \
+ echo "MCW Root: "$(MCW_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+# Make README.rst
+README.rst: README.src.rst docs/source/getting-started.rst docs/source/tool-versioning.rst openlane/README.src.rst docs/source/caravel-with-openlane.rst Makefile
+ pip -q install rst_include && \
+ rm -f README.rst && \
+ rst_include include README.src.rst - | \
+ sed \
+ -e's@\.\/\_static@\/docs\/source\/\_static@g' \
+ -e's@:doc:`tool-versioning`@`tool-versioning.rst <./docs/source/tool-versioning.rst>`__@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > README.rst && \
+ rst_include include openlane/README.src.rst - | \
+ sed \
+ -e's@https://github.com/efabless/caravel/blob/master/verilog@../verilog@g' \
+ -e's@:ref:`getting-started`@`README.rst <../README.rst>`__@g' \
+ -e's@https://github.com/efabless/caravel/blob/master/openlane/@./@g' \
+ -e's@.. note::@**NOTE:**@g' \
+ -e's@.. warning::@**WARNING:**@g' \
+ > openlane/README.rst
diff --git a/caravel/info.yaml b/caravel/info.yaml
new file mode 100644
index 0000000..2c889db
--- /dev/null
+++ b/caravel/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "Two Stage CMOS Operational Amplifier"
+ foundry: "SkyWater"
+ git_url: "https://github.com/rohinthram/avsd_opamp_tapeout_mpw4"
+ organization: ""
+ organization_url: ""
+ owner: "R.V.Rohinth Ram"
+ process: "SKY130"
+ project_name: "Two Stage CMOS Operational Amplifier"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Test Harness"
+ category: "Test Harness"
+ top_level_netlist: "caravel/spi/lvs/caravan.spice"
+ user_level_netlist: "netgen/user_analog_project_wrapper.spice"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/caravel/openlane/Makefile b/caravel/openlane/Makefile
new file mode 100644
index 0000000..d48367d
--- /dev/null
+++ b/caravel/openlane/Makefile
@@ -0,0 +1,92 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = $(shell find * -maxdepth 0 -type d)
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG ?= 2021.11.23_01.42.34
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+
+ @if [ -f ./$*/interactive.tcl ]; then\
+ docker run -it -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:$(PWD)/.. \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(MGMT_AREA_ROOT):$(MGMT_AREA_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
+ else\
+ docker run -it -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:$(PWD)/.. \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(MGMT_AREA_ROOT):$(MGMT_AREA_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
+ fi
+ mkdir -p ../signoff/$*/
+ cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
+ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
+ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ make openlane
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/caravel/scripts/check_density.py b/caravel/scripts/check_density.py
new file mode 100755
index 0000000..25f44ba
--- /dev/null
+++ b/caravel/scripts/check_density.py
@@ -0,0 +1,616 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# check_density.py ---
+#
+# Run density checks on the final (filled) GDS.
+#
+
+import sys
+import os
+import re
+import select
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("check_density.py [<path_to_project>] [-keep]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the check script.")
+ return 0
+
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to check_density.py.")
+ usage()
+ sys.exit(0)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ # Check for valid user path
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ if user_id_value:
+ project = 'caravel'
+ project_with_id = 'caravel_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ with open(magpath + '/check_density.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('crashbackups stop', file=ofile)
+ print('drc off', file=ofile)
+ print('snap internal', file=ofile)
+
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started reading GDS: $starttime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Read final project from .gds
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/' + project_with_id + '.gds', file=ofile)
+ print('', file=ofile)
+
+ print('set midtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Starting density checks: $midtime"', file=ofile)
+ print('', file=ofile)
+ print('flush stdout', file=ofile)
+ print('update idletasks', file=ofile)
+
+ # Get step box dimensions (700um for size and 70um for FOM step)
+ # Use 350um for stepping on other layers.
+ print('box values 0 0 0 0', file=ofile)
+ # print('box size 700um 700um', file=ofile)
+ # print('set stepbox [box values]', file=ofile)
+ # print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ # print('set stepheight [lindex $stepbox 3]', file=ofile)
+
+ print('box size 70um 70um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepsizex [lindex $stepbox 2]', file=ofile)
+ print('set stepsizey [lindex $stepbox 3]', file=ofile)
+
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+
+ # Modify the box to be inside the seal ring area (shrink 5um)
+ print('box grow c -5um', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepsizex))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepsizey))}]', file=ofile)
+ print('box size $stepsizex $stepsizey', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ print('puts stdout "XTILES: $xtiles"', file=ofile)
+ print('puts stdout "YTILES: $ytiles"', file=ofile)
+ print('', file=ofile)
+
+ # Need to know what fraction of a full tile is the last row and column
+ print('set xfrac [expr {($xtiles * $stepsizex - $fullwidth + 0.0) / $stepsizex}]', file=ofile)
+ print('set yfrac [expr {($ytiles * $stepsizey - $fullheight + 0.0) / $stepsizey}]', file=ofile)
+ print('puts stdout "XFRAC: $xfrac"', file=ofile)
+ print('puts stdout "YFRAC: $yfrac"', file=ofile)
+
+ print('cif ostyle density', file=ofile)
+
+ # Process density at steps. For efficiency, this is done in 70x70 um
+ # areas, dumped to a file, and then aggregated into the 700x700 areas.
+
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepsizex]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepsizey]', file=ofile)
+ print(' set xhi [expr $xlo + $stepsizex]', file=ofile)
+ print(' set yhi [expr $ylo + $stepsizey]', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+
+ # Flatten this area
+ print(' flatten -dobbox -nolabels tile', file=ofile)
+ print(' load tile', file=ofile)
+ print(' select top cell', file=ofile)
+
+ # Run density check for each layer
+ print(' puts stdout "Density results for tile x=$x y=$y"', file=ofile)
+
+ print(' set fdens [cif list cover fom_all]', file=ofile)
+ print(' set pdens [cif list cover poly_all]', file=ofile)
+ print(' set ldens [cif list cover li_all]', file=ofile)
+ print(' set m1dens [cif list cover m1_all]', file=ofile)
+ print(' set m2dens [cif list cover m2_all]', file=ofile)
+ print(' set m3dens [cif list cover m3_all]', file=ofile)
+ print(' set m4dens [cif list cover m4_all]', file=ofile)
+ print(' set m5dens [cif list cover m5_all]', file=ofile)
+ print(' puts stdout "FOM: $fdens"', file=ofile)
+ print(' puts stdout "POLY: $pdens"', file=ofile)
+ print(' puts stdout "LI1: $ldens"', file=ofile)
+ print(' puts stdout "MET1: $m1dens"', file=ofile)
+ print(' puts stdout "MET2: $m2dens"', file=ofile)
+ print(' puts stdout "MET3: $m3dens"', file=ofile)
+ print(' puts stdout "MET4: $m4dens"', file=ofile)
+ print(' puts stdout "MET5: $m5dens"', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+
+ print(' load ' + project_with_id, file=ofile)
+ print(' cellname delete tile', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('', file=ofile)
+
+
+ myenv = os.environ.copy()
+ # Real views are necessary for the DRC checks
+ myenv['MAGTYPE'] = 'mag'
+
+ print('Running density checks on file ' + project_with_id + '.gds', flush=True)
+
+ mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/check_density.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+
+ # Use signal to poll the process and generate any output as it arrives
+
+ dlines = []
+
+ while mproc:
+ status = mproc.poll()
+ if status != None:
+ try:
+ output = mproc.communicate(timeout=1)
+ except ValueError:
+ print('Magic forced stop, status ' + str(status))
+ sys.exit(1)
+ else:
+ outlines = output[0]
+ errlines = output[1]
+ for line in outlines.splitlines():
+ dlines.append(line)
+ print(line)
+ for line in errlines.splitlines():
+ print(line)
+ print('Magic exited with status ' + str(status))
+ if int(status) != 0:
+ sys.exit(int(status))
+ else:
+ break
+ else:
+ n = 0
+ while True:
+ n += 1
+ if n > 100:
+ n = 0
+ status = mproc.poll()
+ if status != None:
+ break
+ sresult = select.select([mproc.stdout, mproc.stderr], [], [], 0.5)[0]
+ if mproc.stdout in sresult:
+ outstring = mproc.stdout.readline().strip()
+ dlines.append(outstring)
+ print(outstring)
+ elif mproc.stderr in sresult:
+ outstring = mproc.stderr.readline().strip()
+ print(outstring)
+ else:
+ break
+
+ fomfill = []
+ polyfill = []
+ lifill = []
+ met1fill = []
+ met2fill = []
+ met3fill = []
+ met4fill = []
+ met5fill = []
+ xtiles = 0
+ ytiles = 0
+ xfrac = 0.0
+ yfrac = 0.0
+
+ for line in dlines:
+ dpair = line.split(':')
+ if len(dpair) == 2:
+ layer = dpair[0]
+ try:
+ density = float(dpair[1].strip())
+ except:
+ continue
+ if layer == 'FOM':
+ fomfill.append(density)
+ elif layer == 'POLY':
+ polyfill.append(density)
+ elif layer == 'LI1':
+ lifill.append(density)
+ elif layer == 'MET1':
+ met1fill.append(density)
+ elif layer == 'MET2':
+ met2fill.append(density)
+ elif layer == 'MET3':
+ met3fill.append(density)
+ elif layer == 'MET4':
+ met4fill.append(density)
+ elif layer == 'MET5':
+ met5fill.append(density)
+ elif layer == 'XTILES':
+ xtiles = int(dpair[1].strip())
+ elif layer == 'YTILES':
+ ytiles = int(dpair[1].strip())
+ elif layer == 'XFRAC':
+ xfrac = float(dpair[1].strip())
+ elif layer == 'YFRAC':
+ yfrac = float(dpair[1].strip())
+
+ if ytiles == 0 or xtiles == 0:
+ print('Failed to read XTILES or YTILES from output.')
+ sys.exit(1)
+
+ total_tiles = (ytiles - 9) * (xtiles - 9)
+
+ print('')
+ print('Density results (total tiles = ' + str(total_tiles) + '):')
+
+ # For FOM, step at 70um intervals (same as 70um check area)
+ fomstep = 1
+
+ # For poly, step only at 700um intervals (10 * 70um check area)
+ polystep = 10
+
+ # For all metals, step only at 350um intervals (5 * 70um check area)
+ metalstep = 5
+
+ # Full areas are 10 x 10 tiles = 100. But the right and top sides are
+ # not full tiles, so the full area must be prorated.
+
+ sideadjust = 90.0 + (10.0 * xfrac)
+ topadjust = 90.0 + (10.0 * yfrac)
+ corneradjust = 81.0 + (9.0 * xfrac) + (9.0 * yfrac) + (xfrac * yfrac)
+
+ print('')
+ print('FOM Density:')
+ for y in range(0, ytiles - 9, fomstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, fomstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ fomaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ fomaccum += sum(fomfill[base : base + 10])
+
+ fomaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ print('')
+ print('POLY Density:')
+ for y in range(0, ytiles - 9, polystep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, polystep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ polyaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ polyaccum += sum(polyfill[base : base + 10])
+
+ polyaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(polyaccum))
+
+ print('')
+ print('LI Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ liaccum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ liaccum += sum(lifill[base : base + 10])
+
+ liaccum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ print('')
+ print('MET1 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met1accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met1accum += sum(met1fill[base : base + 10])
+
+ met1accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ print('')
+ print('MET2 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met2accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met2accum += sum(met2fill[base : base + 10])
+
+ met2accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ print('')
+ print('MET3 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met3accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met3accum += sum(met3fill[base : base + 10])
+
+ met3accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ print('')
+ print('MET4 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met4accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met4accum += sum(met4fill[base : base + 10])
+
+ met4accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ print('')
+ print('MET5 Density:')
+ for y in range(0, ytiles - 9, metalstep):
+ if y == ytiles - 10:
+ atotal = topadjust
+ else:
+ atotal = 100.0
+ for x in range(0, xtiles - 9, metalstep):
+ if x == xtiles - 10:
+ if y == ytiles - 10:
+ atotal = corneradjust
+ else:
+ atotal = sideadjust
+ met5accum = 0
+ for w in range(y, y + 10):
+ base = xtiles * w + x
+ met5accum += sum(met5fill[base : base + 10])
+
+ met5accum /= atotal
+ print('Tile (' + str(x) + ', ' + str(y) + '): ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ print('')
+ print('Whole-chip density results:')
+
+ atotal = ((xtiles - 1.0) * (ytiles - 1.0)) + ((ytiles - 1.0) * xfrac) + ((xtiles - 1.0) * yfrac) + (xfrac * yfrac)
+
+ fomaccum = sum(fomfill) / atotal
+ print('')
+ print('FOM Density: ' + str(fomaccum))
+ if fomaccum < 0.33:
+ print('***Error: FOM Density < 33%')
+ elif fomaccum > 0.57:
+ print('***Error: FOM Density > 57%')
+
+ polyaccum = sum(polyfill) / atotal
+ print('')
+ print('POLY Density: ' + str(polyaccum))
+
+ liaccum = sum(lifill) / atotal
+ print('')
+ print('LI Density: ' + str(liaccum))
+ if liaccum < 0.35:
+ print('***Error: LI Density < 35%')
+ elif liaccum > 0.60:
+ print('***Error: LI Density > 60%')
+
+ met1accum = sum(met1fill) / atotal
+ print('')
+ print('MET1 Density: ' + str(met1accum))
+ if met1accum < 0.35:
+ print('***Error: MET1 Density < 35%')
+ elif met1accum > 0.60:
+ print('***Error: MET1 Density > 60%')
+
+ met2accum = sum(met2fill) / atotal
+ print('')
+ print('MET2 Density: ' + str(met2accum))
+ if met2accum < 0.35:
+ print('***Error: MET2 Density < 35%')
+ elif met2accum > 0.60:
+ print('***Error: MET2 Density > 60%')
+
+ met3accum = sum(met3fill) / atotal
+ print('')
+ print('MET3 Density: ' + str(met3accum))
+ if met3accum < 0.35:
+ print('***Error: MET3 Density < 35%')
+ elif met3accum > 0.60:
+ print('***Error: MET3 Density > 60%')
+
+ met4accum = sum(met4fill) / atotal
+ print('')
+ print('MET4 Density: ' + str(met4accum))
+ if met4accum < 0.35:
+ print('***Error: MET4 Density < 35%')
+ elif met4accum > 0.60:
+ print('***Error: MET4 Density > 60%')
+
+ met5accum = sum(met5fill) / atotal
+ print('')
+ print('MET5 Density: ' + str(met5accum))
+ if met5accum < 0.45:
+ print('***Error: MET5 Density < 45%')
+ elif met5accum > 0.76:
+ print('***Error: MET5 Density > 76%')
+
+ if not keepmode:
+ if os.path.isfile(magpath + '/check_density.tcl'):
+ os.remove(magpath + '/check_density.tcl')
+
+ print('')
+ print('Done!')
+ sys.exit(0)
diff --git a/caravel/scripts/compositor.py b/caravel/scripts/compositor.py
new file mode 100755
index 0000000..c5c0139
--- /dev/null
+++ b/caravel/scripts/compositor.py
@@ -0,0 +1,255 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# compositor.py ---
+#
+# Compose the final GDS for caravel from the caravel GDS, seal ring
+# GDS, and fill GDS.
+#
+
+import sys
+import os
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("compositor.py <user_id_value> <project> <path_to_project> <path_to_mag_dir> <path_to_gds_dir [-keep]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print(" <path_to_mag_dir> is the path to the mag directory.")
+ print(" <path_to_gds_dir> is the path to the gds directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If <path_to_mag_dir> is not given, then it is assumed to be the <path_to_project>/tmp.")
+ print(" If <path_to_gds_dir> is not given, then it is assumed to be the <path_to_project>/gds.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ return 0
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) != 5:
+ print("Wrong number of arguments given to compositor.py.")
+ usage()
+ sys.exit(0)
+
+ user_id_value = arguments[0]
+ project = arguments[1]
+ user_project_path = arguments[2]
+ mag_dir_path = arguments[3]
+ gds_dir_path = arguments[4]
+
+ # if len(arguments) > 0:
+ # user_id_value = arguments[0]
+
+ # Convert to binary
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ print("User ID not recognized")
+ usage()
+ sys.exit(1)
+
+ # if len(arguments) == 2 and user_project_path == None:
+ # user_project_path = arguments[1]
+ # mag_dir_path = user_project_path + "/mag"
+ # gds_dir_path = "../gds"
+ # if len(arguments) == 3 and user_project_path == None:
+ # user_project_path = arguments[1]
+ # mag_dir_path = arguments[2]
+ # gds_dir_path = "../gds"
+ # if len(arguments) == 4:
+ # user_project_path = arguments[1]
+ # mag_dir_path = arguments[2]
+ # gds_dir_path = arguments[3]
+ # elif len(arguments) == 3 and user_project_path != None:
+ # mag_dir_path = arguments[1]
+ # gds_dir_path = arguments[2]
+ # else:
+ # user_project_path = os.getcwd()
+ # mag_dir_path = user_project_path + "/mag"
+ # gds_dir_path = "../gds"
+
+ # Check for valid user path
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid mag path
+
+ if not os.path.isdir(mag_dir_path):
+ print('Error: Mag directory path "' + mag_dir_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid gds path
+
+ if not os.path.isdir(gds_dir_path):
+ print('Error: GDS directory path "' + gds_dir_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ # if not user_id_value:
+ # if os.path.isfile(user_project_path + '/info.yaml'):
+ # with open(user_project_path + '/info.yaml', 'r') as ifile:
+ # infolines = ifile.read().splitlines()
+ # for line in infolines:
+ # kvpair = line.split(':')
+ # if len(kvpair) == 2:
+ # key = kvpair[0].strip()
+ # value = kvpair[1].strip()
+ # if key == 'project_id':
+ # user_id_value = value.strip('"\'')
+ # break
+
+ if user_id_value:
+ # project = 'caravel'
+ # project_with_id = project + '_' + user_id_value
+ project_with_id = 'caravel_' + user_id_value
+ user_id_decimal = str(int(user_id_value, 16))
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+
+ magpath = mag_dir_path
+ rcfile = magpath + '/.magicrc'
+ # pdk_root = os.getenv("PDK_ROOT")
+ # rcfile = pdk_root + '/sky130A/libs.tech/magic/sky130A.magicrc'
+
+ gdspath = gds_dir_path
+
+ # The compositor script will create <project_with_id>.mag, but is uses
+ # "load", so the file must not already exist.
+
+ if os.path.isfile(user_project_path + '/mag/' + project_with_id + '.mag'):
+ print('Error: File ' + project_with_id + '.mag exists already! Exiting. . .')
+ sys.exit(1)
+
+ with open(user_project_path + '/mag/compose_final.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ # Set the random seed from the project ID
+ print('random seed ' + user_id_decimal, file=ofile)
+
+ # Read project from .mag but set GDS properties so that it points
+ # to the GDS file created by "make ship".
+ print('load ' + project + ' -dereference', file=ofile)
+ print('property GDS_FILE ' + gdspath + '/' + project + '.gds', file=ofile)
+ print('property GDS_START 0', file=ofile)
+ print('select top cell', file=ofile)
+ print('set bbox [box values]', file=ofile)
+
+ # Ceate a cell to represent the generated fill. There are
+ # no magic layers corresponding to the fill shape data, and
+ # it's gigabytes anyway, so we don't want to deal with any
+ # actual data. So it's just a placeholder.
+
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values {*}$bbox', file=ofile)
+ print('paint comment', file=ofile)
+ print('property GDS_FILE ' + gdspath + '/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('property GDS_START 0', file=ofile)
+ print('property FIXED_BBOX "$bbox"', file=ofile)
+
+ # Create a new project top level and place the fill cell.
+ print('load ' + project_with_id + ' -quiet', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box position 6um 6um', file=ofile)
+ print('getcell ' + project + ' child 0 0', file=ofile)
+ print('getcell ' + project_with_id + '_fill_pattern child 0 0', file=ofile)
+
+ # Move existing origin to (6um, 6um) for seal ring placement
+ # print('move origin -6um -6um', file=ofile)
+
+ # Read in abstract view of seal ring
+ print('box position 0 0', file=ofile)
+ print('getcell advSeal_6um_gen', file=ofile)
+
+ # Write out completed project as "caravel_" + the user ID
+ # print('save ' + user_project_path + '/mag/' + project_with_id, file=ofile)
+
+ # Generate final GDS
+ print('puts stdout "Writing final GDS. . . "', file=ofile)
+ print('flush stdout', file=ofile)
+ print('gds undefined allow', file=ofile)
+ print('cif *hier write disable', file=ofile)
+ print('gds write ' + gdspath + '/' + project_with_id + '.gds', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ myenv = os.environ.copy()
+ # Abstract views are appropriate for final composition
+ myenv['MAGTYPE'] = 'maglef'
+
+ print('Building final GDS file ' + project_with_id + '.gds', flush=True)
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, user_project_path + '/mag/compose_final.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ # NOTE: Until there is a "load -quiet" option in magic, loading
+ # a new cell generates an error. This code ignores the error.
+ newlines = []
+ for line in mproc.stderr.splitlines():
+ if line.endswith("_fill_pattern.mag couldn't be read"):
+ continue
+ if line.startswith("No such file or directory"):
+ continue
+ else:
+ newlines.append(line)
+
+ if len(newlines) > 0:
+ print('Error message output from magic:')
+ for line in newlines:
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ os.remove(user_project_path + '/mag/compose_final.tcl')
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/count_lvs.py b/caravel/scripts/count_lvs.py
new file mode 100755
index 0000000..2362e01
--- /dev/null
+++ b/caravel/scripts/count_lvs.py
@@ -0,0 +1,121 @@
+#!ENV_PATH python3
+#
+#---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+#---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+#---------------------------------------------------------
+
+import os
+import re
+import sys
+import json
+import argparse
+
+def count_LVS_failures(filename):
+ with open(filename, 'r') as cfile:
+ lvsdata = json.load(cfile)
+
+ # Count errors in the JSON file
+ failures = 0
+ devfail = 0
+ netfail = 0
+ pinfail = 0
+ propfail = 0
+ netdiff = 0
+ devdiff = 0
+ ncells = len(lvsdata)
+ for c in range(0, ncells):
+ cellrec = lvsdata[c]
+
+ if c == ncells - 1:
+ topcell = True
+ else:
+ topcell = False
+
+ # Most errors must only be counted for the top cell, because individual
+ # failing cells are flattened and the matching attempted again on the
+ # flattened netlist.
+
+ if topcell:
+ if 'devices' in cellrec:
+ devices = cellrec['devices']
+ devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+ devpair = list(devlist[p:p + 2] for p in range(0, len(devlist), 2))
+ for dev in devpair:
+ c1dev = dev[0]
+ c2dev = dev[1]
+ diffdevs = abs(c1dev[1] - c2dev[1])
+ failures += diffdevs
+ devdiff += diffdevs
+
+ if 'nets' in cellrec:
+ nets = cellrec['nets']
+ diffnets = abs(nets[0] - nets[1])
+ failures += diffnets
+ netdiff += diffnets
+
+ if 'badnets' in cellrec:
+ badnets = cellrec['badnets']
+ failures += len(badnets)
+ netfail += len(badnets)
+
+ if 'badelements' in cellrec:
+ badelements = cellrec['badelements']
+ failures += len(badelements)
+ devfail += len(badelements)
+
+ if 'pins' in cellrec:
+ pins = cellrec['pins']
+ pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+ pinpair = list(pinlist[p:p + 2] for p in range(0, len(pinlist), 2))
+ for pin in pinpair:
+ # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+ # and ignore case when comparing pins.
+ pin0 = re.sub('!$', '', pin[0].lower())
+ pin1 = re.sub('!$', '', pin[1].lower())
+ if pin0 != pin1:
+ # The text "(no pin)" indicates a missing pin that can be
+ # ignored because the pin in the other netlist is a no-connect
+ if pin0 != '(no pin)' and pin1 != '(no pin)':
+ failures += 1
+ pinfail += 1
+
+ # Property errors must be counted for every cell
+ if 'properties' in cellrec:
+ properties = cellrec['properties']
+ failures += len(properties)
+ propfail += len(properties)
+
+ return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+if __name__ == '__main__':
+
+ parser = argparse.ArgumentParser(description='Parses netgen lvs')
+ parser.add_argument('--file', '-f', required=True)
+ args = parser.parse_args()
+ failures = count_LVS_failures(args.file)
+
+ total = failures[0]
+ if total > 0:
+ failed = True
+ print('LVS reports:')
+ print(' net count difference = ' + str(failures[5]))
+ print(' device count difference = ' + str(failures[6]))
+ print(' unmatched nets = ' + str(failures[1]))
+ print(' unmatched devices = ' + str(failures[2]))
+ print(' unmatched pins = ' + str(failures[3]))
+ print(' property failures = ' + str(failures[4]))
+ else:
+ print('LVS reports no net, device, pin, or property mismatches.')
+
+ print('')
+ print('Total errors = ' + str(total))
+
\ No newline at end of file
diff --git a/caravel/scripts/create-caravel-diagram.py b/caravel/scripts/create-caravel-diagram.py
new file mode 100755
index 0000000..bfb4e3c
--- /dev/null
+++ b/caravel/scripts/create-caravel-diagram.py
@@ -0,0 +1,126 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+import sys
+import os
+import subprocess
+from pathlib import Path
+import argparse
+from tempfile import mkstemp
+import re
+
+
+def remove_inouts(jsonpath, replacewith='input'):
+ """Replaces inouts with either input or output statements.
+
+ Netlistsvg does not parse inout ports as for now, so they need to be
+ replaced with either input or output to produce a diagram.
+
+ Parameters
+ ----------
+ jsonpath : str
+ Path to JSON file to fix
+ replacewith : str
+ The string to replace 'inout', can be 'input' or 'output'
+ """
+ assert replacewith in ['input', 'output']
+ with open(jsonpath, 'r') as withinouts:
+ lines = withinouts.readlines()
+ with open(jsonpath, 'w') as withoutinouts:
+ for line in lines:
+ withoutinouts.write(re.sub('inout', replacewith, line))
+
+
+def main(argv):
+ parser = argparse.ArgumentParser(argv[0])
+ parser.add_argument(
+ 'verilog_rtl_dir',
+ help="Path to the project's verilog/rtl directory",
+ type=Path)
+ parser.add_argument(
+ 'output',
+ help="Path to the output SVG file",
+ type=Path)
+ parser.add_argument(
+ '--num-iopads',
+ help='Number of iopads to render',
+ type=int,
+ default=38)
+ parser.add_argument(
+ '--yosys-executable',
+ help='Path to yosys executable',
+ type=Path,
+ default='yosys')
+ parser.add_argument(
+ '--netlistsvg-executable',
+ help='Path to netlistsvg executable',
+ type=Path,
+ default='netlistsvg')
+ parser.add_argument(
+ '--inouts-as',
+ help='To what kind of IO should inout ports be replaced',
+ choices=['input', 'output'],
+ default='input'
+ )
+
+ args = parser.parse_args(argv[1:])
+
+ fd, jsonpath = mkstemp(suffix='-yosys.json')
+ os.close(fd)
+
+ yosyscommand = [
+ f'{str(args.yosys_executable)}',
+ '-p',
+ 'read_verilog pads.v defines.v; ' +
+ 'read_verilog -lib -overwrite *.v; ' +
+ f'verilog_defines -DMPRJ_IO_PADS={args.num_iopads}; ' +
+ 'read_verilog -overwrite caravel.v; ' +
+ 'hierarchy -top caravel; ' +
+ 'proc; ' +
+ 'opt; ' +
+ f'write_json {jsonpath}; '
+ ]
+
+ result = subprocess.run(
+ yosyscommand,
+ cwd=args.verilog_rtl_dir,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+
+ exitcode = 0
+ if result.returncode != 0:
+ print(f'Failed to run: {" ".join(yosyscommand)}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+ else:
+ # TODO once netlistsvg supports inout ports, this should be removed
+ remove_inouts(jsonpath, args.inouts_as)
+ command = f'{args.netlistsvg_executable} {jsonpath} -o {args.output}'
+ result = subprocess.run(
+ command.split(),
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT
+ )
+ if result.returncode != 0:
+ print(f'Failed to run: {command}', file=sys.stderr)
+ print(result.stdout.decode())
+ exitcode = result.returncode
+
+ os.unlink(jsonpath)
+ sys.exit(exitcode)
+
+
+if __name__ == '__main__':
+ sys.exit(main(sys.argv))
diff --git a/caravel/scripts/gen_gpio_defaults.py b/caravel/scripts/gen_gpio_defaults.py
new file mode 100755
index 0000000..15347e7
--- /dev/null
+++ b/caravel/scripts/gen_gpio_defaults.py
@@ -0,0 +1,427 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#----------------------------------------------------------------------
+#
+# gen_gpio_defaults.py ---
+#
+# Manipulate the magic database and GDS to create and apply defaults
+# to the GPIO control blocks based on the user's specification in the
+# user_defines.v file.
+#
+# The GPIO defaults block contains 13 bits that set the state of the
+# GPIO on power-up. GPIOs 0 to 4 in the user project area are fixed
+# and cannot be modified (to maintain access to the housekeeping SPI
+# on startup). GPIOs 5 to 37 are by default set to be an input pad
+# controlled by the user project. The file "user_defines.v" contains
+# the state specified by the user for each GPIO pad, and is what is
+# used in verilog simulation.
+#
+# This script parses the user_defines.v file to determine the state
+# of each GPIO. Then it creates as many new layouts as needed to
+# represent all unique states, modifies the caravel.mag layout
+# to replace the default layouts with the new ones as needed, and
+# generates GDS files for each of the layouts.
+#
+# gpio_defaults_block layout map:
+# Positions marked (in microns) for value = 0. For value = 1, move
+# the via 0.69um to the left. The given position is the lower left
+# corner position of the via. The via itself is 0.17um x 0.17um.
+# The values below are for the file gpio_defaults_block_1403.
+# Positions marked "Y" for "Programmed One?" are already moved to
+# the left, and so should be move 0.69um to the right if the bit
+# should be zero.
+#
+# Signal Via position (um)
+# name X Y
+#-------------------------------------------------------------------
+# gpio_defaults[0] 5.435 4.165
+# gpio_defaults[1] 6.815 3.825
+# gpio_defaults[2] 8.195 4.165
+# gpio_defaults[3] 9.575 3.825
+# gpio_defaults[4] 10.955 3.825
+# gpio_defaults[5] 12.565 3.825
+# gpio_defaults[6] 14.865 3.825
+# gpio_defaults[7] 17.165 3.825
+# gpio_defaults[8] 19.465 3.825
+# gpio_defaults[9] 21.765 3.825
+# gpio_defaults[10] 24.755 3.825
+# gpio_defaults[11] 27.055 3.825
+# gpio_defaults[12] 23.605 4.165
+#-------------------------------------------------------------------
+
+import os
+import sys
+import re
+
+def usage():
+ print('Usage:')
+ print('gen_gpio_defaults.py [<path_to_project>] [-test]')
+ print('')
+ print('where:')
+ print(' <path_to_project> is the path to the project top level directory.')
+ print('')
+ print(' If <path_to_project> is not given, then it is assumed to be the cwd.')
+ print(' The file "user_defines.v" must exist in verilog/rtl/ relative to')
+ print(' <path_to_project>.')
+ return 0
+
+if __name__ == '__main__':
+
+ # Coordinate pairs in microns for the zero position on each bit
+ via_pos = [[5.435, 4.165], [6.815, 3.825], [8.195, 4.165], [9.575, 3.825],
+ [10.955, 3.825], [12.565, 3.825], [14.865, 3.825], [17.165, 3.825],
+ [19.465, 3.825], [21.765, 3.825], [24.755, 3.825], [27.055, 3.825],
+ [23.605, 4.165]]
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ testmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 2:
+ print("Wrong number of arguments given to gen_gpio_defaults.py.")
+ usage()
+ sys.exit(0)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-test' in optionlist:
+ testmode = True
+
+ user_project_path = None
+
+ if len(arguments) == 0:
+ user_project_path = os.getcwd()
+ else:
+ user_project_path = arguments[0]
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ magpath = user_project_path + '/mag'
+ gdspath = user_project_path + '/gds'
+ vpath = user_project_path + '/verilog'
+ glpath = vpath + '/gl'
+
+ try:
+ caravel_path = os.environ['CARAVEL_ROOT']
+ except:
+ print('Warning: CARAVEL_ROOT not set; assuming the cwd.')
+ caravel_path = os.getcwd()
+
+ # Check paths
+ if not os.path.isdir(gdspath):
+ print('No directory ' + gdspath + ' found (path to GDS).')
+ sys.exit(1)
+
+ if not os.path.isdir(vpath):
+ print('No directory ' + vpath + ' found (path to verilog).')
+ sys.exit(1)
+
+ if not os.path.isdir(glpath):
+ print('No directory ' + glpath + ' found (path to gate-level verilog).')
+ sys.exit(1)
+
+ if not os.path.isdir(magpath):
+ print('No directory ' + magpath + ' found (path to magic databases).')
+ sys.exit(1)
+
+ # Parse the user defines verilog file
+ kvpairs = {}
+ user_defines_path = vpath + '/rtl/user_defines.v'
+ if not os.path.isfile(user_defines_path):
+ user_defines_path = caravel_path + '/verilog/rtl/user_defines.v'
+
+ if os.path.isfile(user_defines_path):
+ with open(user_defines_path, 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ tokens = line.split()
+ if len(tokens) >= 3:
+ if tokens[0] == '`define':
+ if tokens[2][0] == '`':
+ # If definition is nested, substitute value.
+ tokens[2] = kvpairs[tokens[2]]
+ kvpairs['`' + tokens[1]] = tokens[2]
+ else:
+ print('Error: No user_defines.v file found.')
+ sys.exit(1)
+
+ # Set additional dictionary entries for the fixed-configuration
+ # GPIOs 0 to 4. This allows the layout to have the default
+ # gpio_defaults_block layout, and this script will change it as
+ # needed.
+
+ kvpairs["`USER_CONFIG_GPIO_0_INIT"] = "13'h1803"
+ kvpairs["`USER_CONFIG_GPIO_1_INIT"] = "13'h1803"
+ kvpairs["`USER_CONFIG_GPIO_2_INIT"] = "13'h0403"
+ kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0403"
+ kvpairs["`USER_CONFIG_GPIO_4_INIT"] = "13'h0403"
+
+ # Generate zero and one coordinates for each via
+ llx_zero = []
+ lly_zero = []
+ urx_zero = []
+ ury_zero = []
+ llx_one = []
+ lly_one = []
+ urx_one = []
+ ury_one = []
+
+ zero_string = []
+ one_string = []
+
+ for i in range(0, 13):
+ llx_zero = int(via_pos[i][0] * 200)
+ lly_zero = int(via_pos[i][1] * 200)
+ urx_zero = llx_zero + 34
+ ury_zero = lly_zero + 34
+
+ llx_one = llx_zero - 138
+ lly_one = lly_zero
+ urx_one = urx_zero - 138
+ ury_one = ury_zero
+
+ zero_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_zero, lly_zero, urx_zero, ury_zero))
+ one_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_one, lly_one, urx_one, ury_one))
+
+ # Create new cells for each unique type
+ print('Step 1: Create new cells for new GPIO default vectors.')
+
+ cellsused = [None] * 38
+
+ for i in range(5, 38):
+ config_name = '`USER_CONFIG_GPIO_' + str(i) + '_INIT'
+ try:
+ config_value = kvpairs[config_name]
+ except:
+ print('No configuration specified for GPIO ' + str(i) + '; skipping.')
+ continue
+
+ try:
+ default_str = config_value[-4:]
+ binval = '{:013b}'.format(int(default_str, 16))
+ except:
+ print('Error: Default value ' + config_value + ' is not a 4-digit hex number; skipping')
+ continue
+
+ cell_name = 'gpio_defaults_block_' + default_str
+ mag_file = magpath + '/' + cell_name + '.mag'
+ cellsused[i] = cell_name
+
+ # Record which bits need to be set for this binval
+ bitflips = []
+ for j in range(0, 13):
+ if binval[12 - j] == '1':
+ bitflips.append(j)
+
+ if not os.path.isfile(mag_file):
+ # A cell with this set of defaults doesn't exist, so make it
+ # First read the 0000 cell, then write to mag_path while
+ # changing the position of vias on the "1" bits
+
+ with open(caravel_path + '/mag/gpio_defaults_block.mag', 'r') as ifile:
+ maglines = ifile.read().splitlines()
+ outlines = []
+ for magline in maglines:
+ is_flipped = False
+ for bitflip in bitflips:
+ if magline == zero_string[bitflip]:
+ is_flipped = True
+ break
+ if is_flipped:
+ outlines.append(one_string[bitflip])
+ else:
+ outlines.append(magline)
+
+ print('Creating new layout file ' + mag_file)
+ if testmode:
+ print('(Test only)')
+ else:
+ with open(mag_file, 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+ else:
+ print('Layout file ' + mag_file + ' already exists and does not need to be generated.')
+
+ gl_file = glpath + '/' + cell_name + '.v'
+
+ defrex = re.compile('[ \t]*assign[ \t]+gpio_defaults\[([0-9]+)\]')
+
+ if not os.path.isfile(gl_file):
+ # A cell with this set of defaults doesn't exist, so make it
+ # First read the default cell, then write to gl_path while
+ # changing the assignment statements at the bottom of each file.
+
+ with open(caravel_path + '/verilog/gl/gpio_defaults_block.v', 'r') as ifile:
+ vlines = ifile.read().splitlines()
+ outlines = []
+ for vline in vlines:
+ is_flipped = False
+ dmatch = defrex.match(vline)
+ if dmatch:
+ bitidx = int(dmatch.group(1))
+ if bitidx in bitflips:
+ is_flipped = True
+ if is_flipped:
+ outlines.append(re.sub('_low', '_high', vline))
+ elif 'gpio_defaults_block' in vline:
+ outlines.append(re.sub('gpio_defaults_block', cell_name, vline))
+ else:
+ outlines.append(vline)
+
+ print('Creating new gate-level verilog file ' + gl_file)
+ if testmode:
+ print('(Test only)')
+ else:
+ with open(gl_file, 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+ else:
+ print('Gate-level verilog file ' + gl_file + ' already exists and does not need to be generated.')
+
+ print('Step 2: Modify top-level layouts to use the specified defaults.')
+
+ # Create a backup of the caravan and caravel layouts
+ # if not testmode:
+ # shutil.copy(magpath + '/caravel.mag', magpath + '/caravel.mag.bak')
+ # shutil.copy(magpath + '/caravan.mag', magpath + '/caravan.mag.bak')
+
+ if testmode:
+ print('Test only: Caravel layout:')
+ with open(caravel_path + '/mag/caravel.mag', 'r') as ifile:
+ maglines = ifile.read().splitlines()
+ outlines = []
+ for magline in maglines:
+ if magline.startswith('use '):
+ tokens = magline.split()
+ instname = tokens[2]
+ if instname.startswith('gpio_defaults_block_'):
+ gpioidx = instname[20:]
+ cellname = cellsused[int(gpioidx)]
+ if cellname:
+ tokens[1] = cellname
+ outlines.append(' '.join(tokens))
+ if testmode:
+ print('Replacing line: ' + magline)
+ print('With: ' + ' '.join(tokens))
+ else:
+ outlines.append(magline)
+ else:
+ outlines.append(magline)
+
+ if not testmode:
+ with open(magpath + '/caravel.mag', 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+
+ # Do the same to the top gate-level verilog
+
+ instrex = re.compile('[ \t]*(gpio_defaults_block_?[0-9]*)[ \t]+gpio_defaults_block_([0-9]+)')
+
+ if testmode:
+ print('Test only: Caravel top gate-level verilog:')
+ with open(caravel_path + '/verilog/gl/caravel.v', 'r') as ifile:
+ vlines = ifile.read().splitlines()
+ outlines = []
+ for vline in vlines:
+ imatch = instrex.match(vline)
+ if imatch:
+ gpioname = imatch.group(1)
+ gpioidx = int(imatch.group(2))
+ cellname = cellsused[int(gpioidx)]
+ if cellname:
+ outlines.append(re.sub(gpioname, cellname, vline, 1))
+ if testmode:
+ print('Replacing line: ' + vline)
+ print('With: ' + outlines[-1])
+ else:
+ outlines.append(vline)
+ else:
+ outlines.append(vline)
+
+ if not testmode:
+ with open(glpath + '/caravel.v', 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+
+ if testmode:
+ print('Test only: Caravan layout:')
+ with open(caravel_path + '/mag/caravan.mag', 'r') as ifile:
+ maglines = ifile.read().splitlines()
+ outlines = []
+ for magline in maglines:
+ if magline.startswith('use '):
+ tokens = magline.split()
+ instname = tokens[2]
+ if instname.startswith('gpio_defaults_block_'):
+ gpioidx = instname[20:]
+ cellname = cellsused[int(gpioidx)]
+ if cellname:
+ tokens[1] = cellname
+ outlines.append(' '.join(tokens))
+ if testmode:
+ print('Replacing line: ' + magline)
+ print('With: ' + ' '.join(tokens))
+ else:
+ outlines.append(magline)
+ else:
+ outlines.append(magline)
+
+ if not testmode:
+ with open(magpath + '/caravan.mag', 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+
+ # Do the same to the top gate-level verilog
+
+ if testmode:
+ print('Test only: Caravan top gate-level verilog:')
+ with open(caravel_path + '/verilog/gl/caravan.v', 'r') as ifile:
+ vlines = ifile.read().splitlines()
+ outlines = []
+ for vline in vlines:
+ imatch = instrex.match(vline)
+ if imatch:
+ gpioname = imatch.group(1)
+ gpioidx = int(imatch.group(2))
+ cellname = cellsused[int(gpioidx)]
+ if cellname:
+ outlines.append(re.sub(gpioname, cellname, vline, 1))
+ if testmode:
+ print('Replacing line: ' + vline)
+ print('With: ' + outlines[-1])
+ else:
+ outlines.append(vline)
+ else:
+ outlines.append(vline)
+
+ if not testmode:
+ with open(glpath + '/caravan.v', 'w') as ofile:
+ for outline in outlines:
+ print(outline, file=ofile)
+
+ print('Done.')
+ sys.exit(0)
diff --git a/caravel/scripts/generate_fill.py b/caravel/scripts/generate_fill.py
new file mode 100755
index 0000000..2b0db8e
--- /dev/null
+++ b/caravel/scripts/generate_fill.py
@@ -0,0 +1,418 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# generate_fill.py ---
+#
+# Run the fill generation on a layout top level.
+#
+
+import sys
+import os
+import re
+import glob
+import subprocess
+import multiprocessing
+
+def usage():
+ print("Usage:")
+ print("generate_fill.py <user_id_value> <project> <path_to_project> [-keep] [-test] [-dist]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ print(" If '-test' is specified, then create but do not run the generation script.")
+ print(" If '-dist' is specified, then run distributed (multi-processing).")
+
+ return 0
+
+def makegds(file):
+ # Procedure for multiprocessing run only: Run the distributed processing
+ # script to load a .mag file of one flattened square area of the layout,
+ # and run the fill generator to produce a .gds file output from it.
+
+ magpath = os.path.split(file)[0]
+ filename = os.path.split(file)[1]
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill_dist.tcl',
+ filename],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+ testmode = False
+ distmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) < 3:
+ print("Wrong number of arguments given to generate_fill.py.")
+ usage()
+ sys.exit(1)
+
+ user_id_value = arguments[0]
+ project = arguments[1]
+ user_project_path = arguments[2]
+
+ try:
+ # Convert to binary
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+
+ except:
+ print("User ID not recognized")
+ usage()
+ sys.exit(1)
+
+ # if len(arguments) == 0:
+ # user_project_path = os.getcwd()
+ # elif len(arguments) == 2:
+ # user_project_path = arguments[1]
+ # elif user_project_path == None:
+ # user_project_path = arguments[0]
+ # else:
+ # user_project_path = os.getcwd()
+
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ # if not user_id_value:
+ # if os.path.isfile(user_project_path + '/info.yaml'):
+ # with open(user_project_path + '/info.yaml', 'r') as ifile:
+ # infolines = ifile.read().splitlines()
+ # for line in infolines:
+ # kvpair = line.split(':')
+ # if len(kvpair) == 2:
+ # key = kvpair[0].strip()
+ # value = kvpair[1].strip()
+ # if key == 'project_id':
+ # user_id_value = value.strip('"\'')
+ # break
+
+ if user_id_value:
+ project_with_id = 'caravel_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+ if '-test' in optionlist:
+ testmode = True
+ if '-dist' in optionlist:
+ distmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+ # pdk_root = os.getenv("PDK_ROOT")
+ # rcfile = pdk_root + '/sky130A/libs.tech/magic/sky130A.magicrc'
+
+ if not os.path.isfile(rcfile):
+ rcfile = None
+
+ topdir = user_project_path
+ gdsdir = topdir + '/gds'
+ hasgdsdir = True if os.path.isdir(gdsdir) else False
+
+ ofile = open(magpath + '/generate_fill.tcl', 'w')
+
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box size 700um 700um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ print('set stepheight [lindex $stepbox 3]', file=ofile)
+ print('', file=ofile)
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started: $starttime"', file=ofile)
+ print('', file=ofile)
+ # Read the user project from GDS, as there is not necessarily a magic database file
+ # to go along with this.
+ # print('gds read ../gds/user_project_wrapper', file=ofile)
+ # Now read the full caravel project
+ # print('load ' + project + ' -dereference', file=ofile)
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/' + project, file=ofile)
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+ if not distmode:
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepwidth))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepheight))}]', file=ofile)
+ print('box size $stepwidth $stepheight', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ # Break layout into tiles and process each separately
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' if {$xhi > $fullwidth} {set xhi $fullwidth}', file=ofile)
+ print(' if {$yhi > $fullheight} {set yhi $fullheight}', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ # The flattened area must be larger than the fill tile by >1.5um
+ print(' box grow c 1.6um', file=ofile)
+
+ # Flatten into a cell with a new name
+ print(' puts stdout "Flattening layout of tile x=$x y=$y. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' flatten -dobox -nolabels ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ # Remove any GDS_FILE reference (there should not be any?)
+ print(' property GDS_FILE ""', file=ofile)
+ # Set boundary using comment layer, to the size of the step box
+ # This corresponds to the "topbox" rule in the wafflefill(tiled) style
+ print(' select top cell', file=ofile)
+ print(' erase comment', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+
+ if not distmode:
+ print(' puts stdout "Writing GDS. . . "', file=ofile)
+
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+
+ if distmode:
+ print(' writeall force ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ else:
+ print(' gds write ' + project_with_id + '_fill_pattern_${x}_$y.gds', file=ofile)
+ # Reload project top
+ print(' load ' + project, file=ofile)
+
+ # Remove last generated cell to save memory
+ print(' cellname delete ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ if distmode:
+ print('set ofile [open fill_gen_info.txt w]', file=ofile)
+ print('puts $ofile "$stepwidth"', file=ofile)
+ print('puts $ofile "$stepheight"', file=ofile)
+ print('puts $ofile "$xtiles"', file=ofile)
+ print('puts $ofile "$ytiles"', file=ofile)
+ print('puts $ofile "$xbase"', file=ofile)
+ print('puts $ofile "$ybase"', file=ofile)
+ print('close $ofile', file=ofile)
+ print('quit -noprompt', file=ofile)
+ ofile.close()
+
+ with open(magpath + '/generate_fill_dist.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('set filename [file root [lindex $argv $argc-1]]', file=ofile)
+ print('load $filename', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('gds write [file root $filename].gds', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ ofile = open(magpath + '/generate_fill_final.tcl', 'w')
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+
+ print('set ifile [open fill_gen_info.txt r]', file=ofile)
+ print('gets $ifile stepwidth', file=ofile)
+ print('gets $ifile stepheight', file=ofile)
+ print('gets $ifile xtiles', file=ofile)
+ print('gets $ifile ytiles', file=ofile)
+ print('gets $ifile xbase', file=ofile)
+ print('gets $ifile ybase', file=ofile)
+ print('close $ifile', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+
+ # Now create simple "fake" views of all the tiles.
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y -quiet', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' property FIXED_BBOX "$xlo $ylo $xhi $yhi"', file=ofile)
+ print(' property GDS_FILE ' + project_with_id + '_fill_pattern_${x}_${y}.gds', file=ofile)
+ print(' property GDS_START 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now tile everything back together
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' box values 0 0 0 0', file=ofile)
+ print(' getcell ' + project_with_id + '_fill_pattern_${x}_$y child 0 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # And write final GDS
+ print('puts stdout "Writing final GDS"', file=ofile)
+
+ print('cif *hier write disable', file=ofile)
+ print('cif *array write disable', file=ofile)
+ if hasgdsdir:
+ print('gds write ../gds/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ else:
+ print('gds write ' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('quit -noprompt', file=ofile)
+ ofile.close()
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ if not testmode:
+ # Diagnostic
+ # print('This script will generate file ' + project_with_id + '_fill_pattern.gds')
+ print('This script will generate files ' + project_with_id + '_fill_pattern_x_y.gds')
+ print('Now generating fill patterns. This may take. . . quite. . . a while.', flush=True)
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if distmode:
+ # If using distributed mode, then run magic on each of the generated
+ # layout files
+ pool = multiprocessing.Pool()
+ magfiles = glob.glob(magpath + '/' + project_with_id + '_fill_pattern_*.mag')
+ # NOTE: Adding 'x' to the end of each filename, or else magic will
+ # try to read it from the command line as well as passing it as an
+ # argument to the script. We only want it passed as an argument.
+ magxfiles = list(item + 'x' for item in magfiles)
+ pool.map(makegds, magxfiles)
+
+ # If using distributed mode, then remove all of the temporary .mag files
+ # and then run the final generation script.
+ for file in magfiles:
+ os.remove(file)
+
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill_final.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ # Remove fill generation script
+ os.remove(magpath + '/generate_fill.tcl')
+ # Remove all individual fill tiles, leaving only the composite GDS.
+ filelist = os.listdir(magpath)
+ for file in filelist:
+ if os.path.splitext(magpath + '/' + file)[1] == '.gds':
+ if file.startswith(project_with_id + '_fill_pattern_'):
+ os.remove(magpath + '/' + file)
+
+ if distmode:
+ os.remove(magpath + '/generate_fill_dist.tcl')
+ os.remove(magpath + '/generate_fill_final.tcl')
+ os.remove(magpath + '/fill_gen_info.txt')
+ if testmode:
+ magfiles = glob.glob(magpath + '/' + project_with_id + '_fill_pattern_*.mag')
+ for file in magfiles:
+ os.remove(file)
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/generate_fill_orig.py b/caravel/scripts/generate_fill_orig.py
new file mode 100755
index 0000000..3a43a8c
--- /dev/null
+++ b/caravel/scripts/generate_fill_orig.py
@@ -0,0 +1,268 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# generate_fill_orig.py ---
+#
+# Run the fill generation on a layout top level.
+# This is the older version that does not have a "-dist" option for
+# distributed (multiprocessing) operation.
+#
+
+import sys
+import os
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("generate_fill_orig.py [<path_to_project>] [-keep] [-test]")
+ print("")
+ print("where:")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ print(" If '-keep' is specified, then keep the generation script.")
+ print(" If '-test' is specified, then create but do not run the generation script.")
+ return 0
+
+if __name__ == '__main__':
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ keepmode = False
+ testmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 1:
+ print("Wrong number of arguments given to generate_fill_orig.py.")
+ usage()
+ sys.exit(1)
+
+ if len(arguments) == 1:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid user ID
+ user_id_value = None
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ project = 'caravel'
+ if user_id_value:
+ project_with_id = project + '_' + user_id_value
+ else:
+ print('Error: No project_id found in info.yaml file.')
+ sys.exit(1)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-keep' in optionlist:
+ keepmode = True
+ if '-test' in optionlist:
+ testmode = True
+
+ magpath = user_project_path + '/mag'
+ rcfile = magpath + '/.magicrc'
+
+ if not os.path.isfile(rcfile):
+ rcfile = None
+
+ topdir = user_project_path
+ gdsdir = topdir + '/gds'
+ hasgdsdir = True if os.path.isdir(gdsdir) else False
+
+ with open(magpath + '/generate_fill.tcl', 'w') as ofile:
+ print('#!/bin/env wish', file=ofile)
+ print('drc off', file=ofile)
+ print('tech unlock *', file=ofile)
+ print('snap internal', file=ofile)
+ print('box values 0 0 0 0', file=ofile)
+ print('box size 700um 700um', file=ofile)
+ print('set stepbox [box values]', file=ofile)
+ print('set stepwidth [lindex $stepbox 2]', file=ofile)
+ print('set stepheight [lindex $stepbox 3]', file=ofile)
+ print('', file=ofile)
+ print('set starttime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Started: $starttime"', file=ofile)
+ print('', file=ofile)
+ # Read the user project from GDS, as there is not necessarily a magic database file
+ # to go along with this.
+ # print('gds read ../gds/user_project_wrapper', file=ofile)
+ # Now read the full caravel project
+ # print('load ' + project + ' -dereference', file=ofile)
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('gds read ../gds/caravel', file=ofile)
+ print('select top cell', file=ofile)
+ print('expand', file=ofile)
+ print('cif ostyle wafflefill(tiled)', file=ofile)
+ print('', file=ofile)
+ print('set fullbox [box values]', file=ofile)
+ print('set xmax [lindex $fullbox 2]', file=ofile)
+ print('set xmin [lindex $fullbox 0]', file=ofile)
+ print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)
+ print('set xtiles [expr {int(ceil(($fullwidth + 0.0) / $stepwidth))}]', file=ofile)
+ print('set ymax [lindex $fullbox 3]', file=ofile)
+ print('set ymin [lindex $fullbox 1]', file=ofile)
+ print('set fullheight [expr {$ymax - $ymin}]', file=ofile)
+ print('set ytiles [expr {int(ceil(($fullheight + 0.0) / $stepheight))}]', file=ofile)
+ print('box size $stepwidth $stepheight', file=ofile)
+ print('set xbase [lindex $fullbox 0]', file=ofile)
+ print('set ybase [lindex $fullbox 1]', file=ofile)
+ print('', file=ofile)
+
+ # Break layout into tiles and process each separately
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' if {$xhi > $fullwidth} {set xhi $fullwidth}', file=ofile)
+ print(' if {$yhi > $fullheight} {set yhi $fullheight}', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ # The flattened area must be larger than the fill tile by >1.5um
+ print(' box grow c 1.6um', file=ofile)
+
+ # Flatten into a cell with a new name
+ print(' puts stdout "Flattening layout of tile x=$x y=$y. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' flatten -dobox -nolabels ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ # Remove any GDS_FILE reference (there should not be any?)
+ print(' property GDS_FILE ""', file=ofile)
+ # Set boundary using comment layer, to the size of the step box
+ # This corresponds to the "topbox" rule in the wafflefill(tiled) style
+ print(' select top cell', file=ofile)
+ print(' erase comment', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' puts stdout "Writing GDS. . . "', file=ofile)
+ print(' flush stdout', file=ofile)
+ print(' update idletasks', file=ofile)
+ print(' gds write ' + project_with_id + '_fill_pattern_${x}_$y.gds', file=ofile)
+
+ # Reload project top
+ print(' load ' + project, file=ofile)
+
+ # Remove last generated cell to save memory
+ print(' cellname delete ' + project_with_id + '_fill_pattern_${x}_$y', file=ofile)
+
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now create simple "fake" views of all the tiles.
+ print('gds readonly true', file=ofile)
+ print('gds rescale false', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' set xlo [expr $xbase + $x * $stepwidth]', file=ofile)
+ print(' set ylo [expr $ybase + $y * $stepheight]', file=ofile)
+ print(' set xhi [expr $xlo + $stepwidth]', file=ofile)
+ print(' set yhi [expr $ylo + $stepheight]', file=ofile)
+ print(' load ' + project_with_id + '_fill_pattern_${x}_$y -quiet', file=ofile)
+ print(' box values $xlo $ylo $xhi $yhi', file=ofile)
+ print(' paint comment', file=ofile)
+ print(' property FIXED_BBOX "$xlo $ylo $xhi $yhi"', file=ofile)
+ print(' property GDS_FILE ' + project_with_id + '_fill_pattern_${x}_${y}.gds', file=ofile)
+ print(' property GDS_START 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # Now tile everything back together
+ print('load ' + project_with_id + '_fill_pattern -quiet', file=ofile)
+ print('for {set y 0} {$y < $ytiles} {incr y} {', file=ofile)
+ print(' for {set x 0} {$x < $xtiles} {incr x} {', file=ofile)
+ print(' box values 0 0 0 0', file=ofile)
+ print(' getcell ' + project_with_id + '_fill_pattern_${x}_$y child 0 0', file=ofile)
+ print(' }', file=ofile)
+ print('}', file=ofile)
+
+ # And write final GDS
+ print('puts stdout "Writing final GDS"', file=ofile)
+
+ print('cif *hier write disable', file=ofile)
+ print('cif *array write disable', file=ofile)
+ if hasgdsdir:
+ print('gds write ../gds/' + project_with_id + '_fill_pattern.gds', file=ofile)
+ else:
+ print('gds write ' + project_with_id + '_fill_pattern.gds', file=ofile)
+ print('set endtime [orig_clock format [orig_clock seconds] -format "%D %T"]', file=ofile)
+ print('puts stdout "Ended: $endtime"', file=ofile)
+ print('quit -noprompt', file=ofile)
+
+ myenv = os.environ.copy()
+ myenv['MAGTYPE'] = 'mag'
+
+ if not testmode:
+ # Diagnostic
+ # print('This script will generate file ' + project_with_id + '_fill_pattern.gds')
+ print('This script will generate files ' + project_with_id + '_fill_pattern_x_y.gds')
+ print('Now generating fill patterns. This may take. . . quite. . . a while.', flush=True)
+ mproc = subprocess.run(['magic', '-dnull', '-noconsole',
+ '-rcfile', rcfile, magpath + '/generate_fill.tcl'],
+ stdin = subprocess.DEVNULL,
+ stdout = subprocess.PIPE,
+ stderr = subprocess.PIPE,
+ cwd = magpath,
+ env = myenv,
+ universal_newlines = True)
+ if mproc.stdout:
+ for line in mproc.stdout.splitlines():
+ print(line)
+ if mproc.stderr:
+ print('Error message output from magic:')
+ for line in mproc.stderr.splitlines():
+ print(line)
+ if mproc.returncode != 0:
+ print('ERROR: Magic exited with status ' + str(mproc.returncode))
+
+ if not keepmode:
+ # Remove fill generation script
+ os.remove(magpath + '/generate_fill.tcl')
+ # Remove all individual fill tiles, leaving only the composite GDS.
+ filelist = os.listdir(magpath)
+ for file in filelist:
+ if os.path.splitext(magpath + '/' + file)[1] == '.gds':
+ if file.startswith(project + '_fill_pattern_'):
+ os.remove(magpath + '/' + file)
+
+ print('Done!')
+ exit(0)
diff --git a/caravel/scripts/make_bump_bonds.tcl b/caravel/scripts/make_bump_bonds.tcl
new file mode 100755
index 0000000..ade81d6
--- /dev/null
+++ b/caravel/scripts/make_bump_bonds.tcl
@@ -0,0 +1,702 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+#----------------------------------------------------------------------
+# Assumes running magic -T micross using the micross technology file
+# from the open_pdks installation of sky130A
+#----------------------------------------------------------------------
+# bump bond pitch is 500um. Bump diameter is set by the technology
+
+namespace path {::tcl::mathop ::tcl::mathfunc}
+
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+source $PDKPATH/libs.tech/magic/current/bump_bond_generator/bump_bond.tcl
+
+# Caravel dimensions, in microns
+set chipwidth 3588
+set chipheight 5188
+
+set halfwidth [/ $chipwidth 2]
+set halfheight [/ $chipheight 2]
+
+set columns 6
+set rows 10
+
+set bump_pitch 500
+
+set llx [- $halfwidth [* [- [/ $columns 2] 0.5] $bump_pitch]]
+set lly [- $halfheight [* [- [/ $rows 2] 0.5] $bump_pitch]]
+
+# Create a new cell
+load caravel_bump_bond -quiet
+
+# Build the bump cells
+make_bump_bond 0
+make_bump_bond 45
+
+# View the whole chip during generation. This is not strictly
+# necessary, but looks nice!
+snap internal
+box values 0 0 ${chipwidth}um ${chipheight}um
+paint glass
+view
+erase glass
+box values 0 0 0 0
+grid 250um 250um 45um 95um
+
+# Starting from the bottom left-hand corner and scanning across and up,
+# these are the orientations of the bump bond pad tapers:
+set tapers {}
+lappend tapers 180 225 270 270 270 270
+lappend tapers 180 135 225 270 0 0
+lappend tapers 180 135 135 270 315 0
+lappend tapers 180 135 135 315 315 0
+lappend tapers 135 135 0 180 315 0
+lappend tapers 180 135 0 180 315 0
+lappend tapers 180 135 180 315 315 0
+lappend tapers 180 180 135 45 315 0
+lappend tapers 135 135 135 45 45 45
+lappend tapers 90 90 90 90 45 90
+
+box values 0 0 0 0
+set t 0
+for {set y 0} {$y < $rows} {incr y} {
+ for {set x 0} {$x < $columns} {incr x} {
+ set xpos [+ $llx [* $x $bump_pitch]]
+ set ypos [+ $lly [* $y $bump_pitch]]
+ draw_bump_bond $xpos $ypos [lindex $tapers $t]
+ incr t
+ }
+}
+
+# The pad at E6 has wires exiting two sides, so put another pad down
+# at the other orientation.
+set y 4
+set x 4
+set xpos [+ $llx [* $x $bump_pitch]]
+set ypos [+ $lly [* $y $bump_pitch]]
+draw_bump_bond $xpos $ypos 180
+
+select top cell
+expand
+
+# These are the pad Y positions on the left side from bottom to top
+
+set leftpads {}
+lappend leftpads 377.5 588.5 950.5 1166.5 1382.5 1598.5 1814.5
+lappend leftpads 2030.5 2241.5 2452.5 2668.5 2884.5 3100.5
+lappend leftpads 3316.5 3532.5 3748.5 3964.5 4175.5 4386.5 4597.5 4813.5
+
+# These are the pad X positions on the top side from left to right
+
+set toppads {}
+lappend toppads 423.5 680.5 937.5 1194.5 1452.5 1704.5 1961.5 2406.5
+lappend toppads 2663.5 2915.5 3172.5
+
+# These are the pad Y positions on the right side from bottom to top
+
+set rightpads {}
+lappend rightpads 537.5 763.5 988.5 1214.5 1439.5 1664.5 1890.5
+lappend rightpads 2115.5 2336.5 2556.5 2776.5 3002.5 3227.5 3453.5
+lappend rightpads 3678.5 3903.5 4129.5 4349.5 4575.5 4795.5
+
+# These are the pad X positions on the bottom side from left to right
+
+set bottompads {}
+lappend bottompads 431.5 700.5 969.5 1243.5 1512.5 1786.5 2060.5
+lappend bottompads 2334.5 2608.5 2882.5 3151.5
+
+set leftpadx 64.6
+set rightpadx 3523.78
+set bottompady 64.6
+set toppady 5123.78
+
+set xpos $leftpadx
+for {set y 0} {$y < [llength $leftpads]} {incr y} {
+ set ypos [lindex $leftpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $toppady
+for {set x 0} {$x < [llength $toppads]} {incr x} {
+ set xpos [lindex $toppads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+set xpos $rightpadx
+for {set y 0} {$y < [llength $rightpads]} {incr y} {
+ set ypos [lindex $rightpads $y]
+ draw_pad_bond $xpos $ypos
+}
+
+set ypos $bottompady
+for {set x 0} {$x < [llength $bottompads]} {incr x} {
+ set xpos [lindex $bottompads $x]
+ draw_pad_bond $xpos $ypos
+}
+
+# Now route between the wirebond pads and the bump bond pads
+# routes start centered on the wirebond pad and align to grid points
+# on a 1/2 ball pitch, although positions do not need to be on
+# integer values. The overlaid grid starts 1/2 pitch to the left
+# and below the center of the bottom left bump bond. Grid columns
+# are numbered 0 to 12, and grid rows are numbered 0 to 20. To
+# convert to a micron unit coordinate, use the to_grid procedure
+# defined below.
+
+set gridllx [- $llx 250.0]
+set gridlly [- $lly 250.0]
+set gridpitchx 250.0
+set gridpitchy 250.0
+
+proc to_grid {x y} {
+ global gridllx gridlly
+ set coords []
+ catch {lappend coords [+ $gridllx [* 250.0 $x]]}
+ catch {lappend coords [+ $gridlly [* 250.0 $y]]}
+ return $coords
+}
+
+# Detailed routing, scanning left to right and from bottom to top.
+# (This really needs to be automated. . .)
+
+set wire_width 40.0
+
+# A10 vccd
+set coords [list $leftpadx [lindex $leftpads 0]]
+lappend coords {*}[to_grid -0.8 1]
+lappend coords {*}[to_grid 1 1]
+draw_pad_route $coords $wire_width
+
+# B10 resetb
+set coords [list [lindex $bottompads 1] $bottompady]
+lappend coords {*}[to_grid 1.9 0.2]
+lappend coords {*}[to_grid 2.2 0.2]
+lappend coords {*}[to_grid 3 1]
+draw_pad_route $coords $wire_width
+
+# C10 flash csb
+set coords [list [lindex $bottompads 4] $bottompady]
+lappend coords {*}[to_grid 5 0]
+lappend coords {*}[to_grid 5 1]
+draw_pad_route $coords $wire_width
+
+# D10 flash io0
+set coords [list [lindex $bottompads 6] $bottompady]
+lappend coords {*}[to_grid 7 0]
+lappend coords {*}[to_grid 7 1]
+draw_pad_route $coords $wire_width
+
+# E10 gpio
+set coords [list [lindex $bottompads 8] $bottompady]
+lappend coords {*}[to_grid 9 0.2]
+lappend coords {*}[to_grid 9 1]
+draw_pad_route $coords $wire_width
+
+# F10 vdda
+set coords [list [lindex $bottompads 10] $bottompady]
+lappend coords {*}[to_grid 11 0.3]
+lappend coords {*}[to_grid 11 1]
+draw_pad_route $coords $wire_width
+
+# A9 mprj_io[37]
+set coords [list $leftpadx [lindex $leftpads 2]]
+lappend coords {*}[to_grid -0.5 3]
+lappend coords {*}[to_grid 1 3]
+draw_pad_route $coords $wire_width
+
+# B9 mprj_io[36]
+set coords [list $leftpadx [lindex $leftpads 3]]
+lappend coords {*}[to_grid -0.6 4]
+lappend coords {*}[to_grid 2 4]
+lappend coords {*}[to_grid 3 3]
+draw_pad_route $coords $wire_width
+
+# C9 clock
+set coords [list [lindex $bottompads 2] $bottompady]
+lappend coords {*}[to_grid 3 0.2]
+lappend coords {*}[to_grid 3.4 0.2]
+lappend coords {*}[to_grid 3.8 0.6]
+lappend coords {*}[to_grid 3.8 1.6]
+lappend coords {*}[to_grid 4.5 2.3]
+lappend coords {*}[to_grid 4.5 2.5]
+lappend coords {*}[to_grid 5 3]
+draw_pad_route $coords $wire_width
+
+# D9 flash io1
+set coords [list [lindex $bottompads 7] $bottompady]
+lappend coords {*}[to_grid 8 0.1]
+lappend coords {*}[to_grid 8 1.3]
+lappend coords {*}[to_grid 7 2.3]
+lappend coords {*}[to_grid 7 3]
+draw_pad_route $coords $wire_width
+
+# E9 mprj_io[1]/SDO
+set coords [list $rightpadx [lindex $rightpads 1]]
+lappend coords {*}[to_grid 12.4 2.2]
+lappend coords {*}[to_grid 10.5 2.2]
+lappend coords {*}[to_grid 9.7 3]
+lappend coords {*}[to_grid 9 3]
+draw_pad_route $coords $wire_width
+
+# F9 mprj_io[2]/SDI
+set coords [list $rightpadx [lindex $rightpads 2]]
+lappend coords {*}[to_grid 12.3 3]
+lappend coords {*}[to_grid 11 3]
+draw_pad_route $coords $wire_width
+
+# A8 mprj_io[35]
+set coords [list $leftpadx [lindex $leftpads 4]]
+lappend coords {*}[to_grid -0.7 5]
+lappend coords {*}[to_grid 1 5]
+draw_pad_route $coords $wire_width
+
+# B8 mprj_io[34]
+set coords [list $leftpadx [lindex $leftpads 5]]
+lappend coords {*}[to_grid -0.7 5.8]
+lappend coords {*}[to_grid 2.2 5.8]
+lappend coords {*}[to_grid 3 5]
+draw_pad_route $coords $wire_width
+
+# C8 mprj_io[33]
+set coords [list $leftpadx [lindex $leftpads 6]]
+lappend coords {*}[to_grid -0.3 6.2]
+lappend coords {*}[to_grid 3.8 6.2]
+lappend coords {*}[to_grid 5 5]
+draw_pad_route $coords $wire_width
+
+# D8 flash clk
+set coords [list [lindex $bottompads 5] $bottompady]
+lappend coords {*}[to_grid 6 0]
+lappend coords {*}[to_grid 6 1]
+lappend coords {*}[to_grid 6.2 1.2]
+lappend coords {*}[to_grid 6.2 3.5]
+lappend coords {*}[to_grid 7 4.3]
+lappend coords {*}[to_grid 7 5]
+draw_pad_route $coords $wire_width
+
+# E8 mprj_io[3]/CSB
+set coords [list $rightpadx [lindex $rightpads 3]]
+lappend coords {*}[to_grid 12.4 4]
+lappend coords {*}[to_grid 10 4]
+lappend coords {*}[to_grid 9 5]
+draw_pad_route $coords $wire_width
+
+# F8 mrpj_io[4]/SCK
+set coords [list $rightpadx [lindex $rightpads 4]]
+lappend coords {*}[to_grid 12.5 5]
+lappend coords {*}[to_grid 11 5]
+draw_pad_route $coords $wire_width
+
+# A7 mrpj_io[32]
+set coords [list $leftpadx [lindex $leftpads 7]]
+lappend coords {*}[to_grid -0.2 7]
+lappend coords {*}[to_grid 1 7]
+draw_pad_route $coords $wire_width
+
+# B7 vssd2
+set coords [list $leftpadx [lindex $leftpads 8]]
+lappend coords {*}[to_grid -0.1 7.8]
+lappend coords {*}[to_grid 2.2 7.8]
+lappend coords {*}[to_grid 3 7]
+draw_pad_route $coords $wire_width
+
+# C7 vdda2
+set coords [list $leftpadx [lindex $leftpads 9]]
+lappend coords {*}[to_grid 0.3 8.2]
+lappend coords {*}[to_grid 2.3 8.2]
+lappend coords {*}[to_grid 2.5 8]
+lappend coords {*}[to_grid 4 8]
+lappend coords {*}[to_grid 5 7]
+draw_pad_route $coords $wire_width
+
+# D7 mrpj_io[0]/JTAG
+set coords [list $rightpadx [lindex $rightpads 0]]
+lappend coords {*}[to_grid 12.8 1.8]
+lappend coords {*}[to_grid 10.2 1.8]
+lappend coords {*}[to_grid 9.8 2.2]
+lappend coords {*}[to_grid 8.6 2.2]
+lappend coords {*}[to_grid 8.2 2.6]
+lappend coords {*}[to_grid 8.2 5.8]
+lappend coords {*}[to_grid 7 7]
+draw_pad_route $coords $wire_width
+
+# E7 mrpj_io[5]/ser_rx
+set coords [list $rightpadx [lindex $rightpads 5]]
+lappend coords {*}[to_grid 12.6 6]
+lappend coords {*}[to_grid 10 6]
+lappend coords {*}[to_grid 9 7]
+draw_pad_route $coords $wire_width
+
+# F7 mprj_io[6]/ser_tx
+set coords [list $rightpadx [lindex $rightpads 6]]
+lappend coords {*}[to_grid 12.7 7]
+lappend coords {*}[to_grid 11 7]
+draw_pad_route $coords $wire_width
+
+# A6 mprj_io[31]
+set coords [list $leftpadx [lindex $leftpads 10]]
+lappend coords {*}[to_grid -0.3 10.3]
+lappend coords {*}[to_grid 1 9]
+draw_pad_route $coords $wire_width
+
+# B6 mprj_io[30]
+set coords [list $leftpadx [lindex $leftpads 11]]
+lappend coords {*}[to_grid -0.5 10.8]
+lappend coords {*}[to_grid -0.3 10.8]
+lappend coords {*}[to_grid 0.5 10]
+lappend coords {*}[to_grid 2 10]
+lappend coords {*}[to_grid 3 9]
+draw_pad_route $coords $wire_width
+
+# C6 vssio/vssa/vssd: Connects to D6, D5, C5
+set coords [to_grid 5 9]
+lappend coords {*}[to_grid 5.65 9]
+lappend coords {*}[to_grid 5.85 9.2]
+lappend coords {*}[to_grid 6 9.2]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd
+set coords [to_grid 7 9]
+lappend coords {*}[to_grid 6.35 9]
+lappend coords {*}[to_grid 6.15 8.8]
+lappend coords {*}[to_grid 6 8.8]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 0] $bottompady]
+lappend coords {*}[to_grid 0.9 0.2]
+lappend coords {*}[to_grid 1.3 0.2]
+lappend coords {*}[to_grid 2 0.9]
+lappend coords {*}[to_grid 2 1.5]
+lappend coords {*}[to_grid 2.3 1.8]
+lappend coords {*}[to_grid 3.5 1.8]
+lappend coords {*}[to_grid 4.2 2.5]
+lappend coords {*}[to_grid 4.2 3.5]
+lappend coords {*}[to_grid 4.5 3.8]
+lappend coords {*}[to_grid 5.3 3.8]
+lappend coords {*}[to_grid 5.8 3.3]
+lappend coords {*}[to_grid 5.8 2.5]
+lappend coords {*}[to_grid 5.3 2]
+lappend coords {*}[to_grid 4.8 2]
+lappend coords {*}[to_grid 4.2 1.4]
+lappend coords {*}[to_grid 4.2 0.3]
+lappend coords {*}[list [lindex $bottompads 3] $bottompady]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $bottompads 9] $bottompady]
+lappend coords {*}[to_grid 10 0.3]
+lappend coords {*}[to_grid 10 1.4]
+lappend coords {*}[to_grid 9.6 1.8]
+lappend coords {*}[to_grid 8.5 1.8]
+lappend coords {*}[to_grid 7.8 2.5]
+lappend coords {*}[to_grid 7.8 5.5]
+lappend coords {*}[to_grid 7.3 6]
+lappend coords {*}[to_grid 6.2 6]
+draw_pad_route $coords $wire_width
+
+# D6 vssio/vssa/vssd also goes to:
+set coords [list [lindex $toppads 5] $toppady]
+lappend coords {*}[to_grid 6 19.7]
+lappend coords {*}[to_grid 6 16]
+lappend coords {*}[to_grid 5.8 15.8]
+lappend coords {*}[to_grid 5.8 12.2]
+lappend coords {*}[to_grid 6 12]
+lappend coords {*}[to_grid 6 8]
+lappend coords {*}[to_grid 6.2 7.8]
+lappend coords {*}[to_grid 6.2 4.3]
+lappend coords {*}[to_grid 5.5 3.6]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1
+set coords [list $rightpadx [lindex $rightpads 7]]
+lappend coords {*}[to_grid 12.8 8]
+lappend coords {*}[to_grid 10 8]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# E6 vssa1 also goes to
+set coords [list [lindex $toppads 9] $toppady]
+lappend coords {*}[to_grid 10 19.5]
+lappend coords {*}[to_grid 10 18.5]
+lappend coords {*}[to_grid 9.5 18]
+lappend coords {*}[to_grid 8.5 18]
+lappend coords {*}[to_grid 8 17.5]
+lappend coords {*}[to_grid 8 16.5]
+lappend coords {*}[to_grid 7.5 16]
+lappend coords {*}[to_grid 6.7 16]
+lappend coords {*}[to_grid 6.2 15.5]
+lappend coords {*}[to_grid 6.2 12.6]
+lappend coords {*}[to_grid 6.7 12]
+lappend coords {*}[to_grid 7.3 12]
+lappend coords {*}[to_grid 7.8 11.5]
+lappend coords {*}[to_grid 7.8 10.2]
+lappend coords {*}[to_grid 8 10]
+lappend coords {*}[to_grid 8 9.3]
+lappend coords {*}[to_grid 8.3 9]
+lappend coords {*}[to_grid 9 9]
+draw_pad_route $coords $wire_width
+
+# F6 vssd1
+set coords [list $rightpadx [lindex $rightpads 8]]
+lappend coords {*}[to_grid 12.9 9]
+lappend coords {*}[to_grid 11 9]
+draw_pad_route $coords $wire_width
+
+# A5 mprj_io[29]
+set coords [list $leftpadx [lindex $leftpads 12]]
+lappend coords {*}[to_grid 0.2 11]
+lappend coords {*}[to_grid 1 11]
+draw_pad_route $coords $wire_width
+
+# B5 mprj_io[28]
+set coords [list $leftpadx [lindex $leftpads 13]]
+lappend coords {*}[to_grid 0 12]
+lappend coords {*}[to_grid 2 12]
+lappend coords {*}[to_grid 3 11]
+draw_pad_route $coords $wire_width
+
+# C5 vssio/vssa/vssd : Connects to D6, C6, D5
+set coords [to_grid 5 11]
+lappend coords {*}[to_grid 5.65 11]
+lappend coords {*}[to_grid 5.85 11.2]
+lappend coords {*}[to_grid 6 11.2]
+draw_pad_route $coords $wire_width
+
+# D5 vssio/vssa/vssd : Connects to D6, C6, C5
+set coords [to_grid 7 11]
+lappend coords {*}[to_grid 6.35 11]
+lappend coords {*}[to_grid 6.15 10.8]
+lappend coords {*}[to_grid 6 10.8]
+draw_pad_route $coords $wire_width
+
+# E5 mprj_io[7]/irq
+set coords [list $rightpadx [lindex $rightpads 10]]
+lappend coords {*}[to_grid 12.4 10.2]
+lappend coords {*}[to_grid 9.8 10.2]
+lappend coords {*}[to_grid 9 11]
+draw_pad_route $coords $wire_width
+
+# F5 mprj_io[8]/flash2 csb
+set coords [list $rightpadx [lindex $rightpads 11]]
+lappend coords {*}[to_grid 12.3 11]
+lappend coords {*}[to_grid 11 11]
+draw_pad_route $coords $wire_width
+
+# A4 mprj_io[27]
+set coords [list $leftpadx [lindex $leftpads 14]]
+lappend coords {*}[to_grid -0.1 13]
+lappend coords {*}[to_grid 1 13]
+draw_pad_route $coords $wire_width
+
+# B4 mprj_io[26]
+set coords [list $leftpadx [lindex $leftpads 15]]
+lappend coords {*}[to_grid -0.2 14]
+lappend coords {*}[to_grid 2 14]
+lappend coords {*}[to_grid 3 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio
+set coords [list $leftpadx [lindex $leftpads 1]]
+lappend coords {*}[to_grid -0.8 2]
+lappend coords {*}[to_grid 1.8 2]
+lappend coords {*}[to_grid 2 2.2]
+lappend coords {*}[to_grid 3.3 2.2]
+lappend coords {*}[to_grid 3.8 2.7]
+lappend coords {*}[to_grid 3.8 3.7]
+lappend coords {*}[to_grid 4.3 4.2]
+lappend coords {*}[to_grid 5.3 4.2]
+lappend coords {*}[to_grid 5.8 4.7]
+lappend coords {*}[to_grid 5.8 7.4]
+lappend coords {*}[to_grid 5.2 8]
+lappend coords {*}[to_grid 4.7 8]
+lappend coords {*}[to_grid 4 8.7]
+lappend coords {*}[to_grid 4 13]
+draw_pad_route $coords $wire_width
+
+# C4 vddio is also:
+set coords [list $leftpadx [lindex $leftpads 18]]
+lappend coords {*}[to_grid 0.1 16.2]
+lappend coords {*}[to_grid 1.6 16.2]
+lappend coords {*}[to_grid 2 15.8]
+lappend coords {*}[to_grid 3.4 15.8]
+lappend coords {*}[to_grid 4 15.2]
+lappend coords {*}[to_grid 4 13]
+lappend coords {*}[to_grid 5 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1
+set coords [list $rightpadx [lindex $rightpads 9]]
+lappend coords {*}[to_grid 12.8 9.8]
+lappend coords {*}[to_grid 9.7 9.8]
+lappend coords {*}[to_grid 9.5 10]
+lappend coords {*}[to_grid 8.8 10]
+lappend coords {*}[to_grid 8.2 10.6]
+lappend coords {*}[to_grid 8.2 11.8]
+lappend coords {*}[to_grid 7 13]
+draw_pad_route $coords $wire_width
+
+# D4 vdda1 is also:
+set coords [list $rightpadx [lindex $rightpads 16]]
+lappend coords {*}[to_grid 12.6 15.8]
+lappend coords {*}[to_grid 8.4 15.8]
+lappend coords {*}[to_grid 8 15.4]
+lappend coords {*}[to_grid 8 12.4]
+lappend coords {*}[to_grid 7.8 12.2]
+draw_pad_route $coords $wire_width
+
+# E4 mprj_io[9]/flash2 sck
+set coords [list $rightpadx [lindex $rightpads 12]]
+lappend coords {*}[to_grid 12.4 12]
+lappend coords {*}[to_grid 10 12]
+lappend coords {*}[to_grid 9 13]
+draw_pad_route $coords $wire_width
+
+# F4 mprj_io[10]/flash2 io0
+set coords [list $rightpadx [lindex $rightpads 13]]
+lappend coords {*}[to_grid 12.5 13]
+lappend coords {*}[to_grid 11 13]
+draw_pad_route $coords $wire_width
+
+# A3 mprj_io[25]
+set coords [list $leftpadx [lindex $leftpads 16]]
+lappend coords {*}[to_grid -0.4 15]
+lappend coords {*}[to_grid 1 15]
+draw_pad_route $coords $wire_width
+
+# B3 vssa2
+set coords [list $leftpadx [lindex $leftpads 17]]
+lappend coords {*}[to_grid -0.4 15.8]
+lappend coords {*}[to_grid 0 15.8]
+lappend coords {*}[to_grid 1.3 15.8]
+lappend coords {*}[to_grid 2.2 15]
+lappend coords {*}[to_grid 3 15]
+draw_pad_route $coords $wire_width
+
+# C3 mprj_io[24]
+set coords [list $leftpadx [lindex $leftpads 20]]
+lappend coords {*}[to_grid 0 18]
+lappend coords {*}[to_grid 1.5 18]
+lappend coords {*}[to_grid 2 17.5]
+lappend coords {*}[to_grid 2 16.5]
+lappend coords {*}[to_grid 2.3 16.2]
+lappend coords {*}[to_grid 3.8 16.2]
+lappend coords {*}[to_grid 5 15]
+draw_pad_route $coords $wire_width
+
+# D3 mprj_io[13]
+set coords [list $rightpadx [lindex $rightpads 17]]
+lappend coords {*}[to_grid 12 16.2]
+lappend coords {*}[to_grid 8.2 16.2]
+lappend coords {*}[to_grid 7 15]
+draw_pad_route $coords $wire_width
+
+# E3 mprj_io[11]/flash2 io1
+set coords [list $rightpadx [lindex $rightpads 14]]
+lappend coords {*}[to_grid 12.6 14]
+lappend coords {*}[to_grid 10 14]
+lappend coords {*}[to_grid 9 15]
+draw_pad_route $coords $wire_width
+
+# F3 mprj_io[12]
+set coords [list $rightpadx [lindex $rightpads 15]]
+lappend coords {*}[to_grid 12.7 15]
+lappend coords {*}[to_grid 11 15]
+draw_pad_route $coords $wire_width
+
+# A2 vccd2
+set coords [list $leftpadx [lindex $leftpads 19]]
+lappend coords {*}[to_grid -0.4 17.5]
+lappend coords {*}[to_grid 0.5 17.5]
+lappend coords {*}[to_grid 1 17]
+draw_pad_route $coords $wire_width
+
+# B2 mprj_io[22]
+set coords [list [lindex $toppads 1] $toppady]
+lappend coords {*}[to_grid 2 19.7]
+lappend coords {*}[to_grid 2 18]
+lappend coords {*}[to_grid 3 17]
+draw_pad_route $coords $wire_width
+
+# C2 mprj_io[20]
+set coords [list [lindex $toppads 3] $toppady]
+lappend coords {*}[to_grid 4 19.7]
+lappend coords {*}[to_grid 4 18]
+lappend coords {*}[to_grid 5 17]
+draw_pad_route $coords $wire_width
+
+# D2 mprj_io[17]
+set coords [list [lindex $toppads 7] $toppady]
+lappend coords {*}[to_grid 8 19.7]
+lappend coords {*}[to_grid 8 18]
+lappend coords {*}[to_grid 7 17]
+draw_pad_route $coords $wire_width
+
+# E2 mprj_io[14]
+set coords [list $rightpadx [lindex $rightpads 19]]
+lappend coords {*}[to_grid 12.6 18.5]
+lappend coords {*}[to_grid 12 18.5]
+lappend coords {*}[to_grid 11.5 18]
+lappend coords {*}[to_grid 10 18]
+lappend coords {*}[to_grid 9 17]
+draw_pad_route $coords $wire_width
+
+# F2 vccd1
+set coords [list $rightpadx [lindex $rightpads 18]]
+lappend coords {*}[to_grid 12.5 17.5]
+lappend coords {*}[to_grid 11.5 17.5]
+lappend coords {*}[to_grid 11 17]
+draw_pad_route $coords $wire_width
+
+# A1 mprj_io[23]
+set coords [list [lindex $toppads 0] $toppady]
+lappend coords {*}[to_grid 1 19.7]
+lappend coords {*}[to_grid 1 19]
+draw_pad_route $coords $wire_width
+
+# B1 mprj_io[21]
+set coords [list [lindex $toppads 2] $toppady]
+lappend coords {*}[to_grid 3 19.7]
+lappend coords {*}[to_grid 3 19]
+draw_pad_route $coords $wire_width
+
+# C1 mprj_io[19]
+set coords [list [lindex $toppads 4] $toppady]
+lappend coords {*}[to_grid 5 19.7]
+lappend coords {*}[to_grid 5 19]
+draw_pad_route $coords $wire_width
+
+# D1 mrpj_io[18]
+set coords [list [lindex $toppads 6] $toppady]
+lappend coords {*}[to_grid 7 19.7]
+lappend coords {*}[to_grid 7 19]
+draw_pad_route $coords $wire_width
+
+# E1 mprj_io[16]
+set coords [list [lindex $toppads 8] $toppady]
+lappend coords {*}[to_grid 9.5 20]
+lappend coords {*}[to_grid 9.5 19.5]
+lappend coords {*}[to_grid 9 19]
+draw_pad_route $coords $wire_width
+
+# F1 mprj_io[15]
+set coords [list [lindex $toppads 10] $toppady]
+lappend coords {*}[to_grid 11 19.7]
+lappend coords {*}[to_grid 11 19]
+draw_pad_route $coords $wire_width
+
diff --git a/caravel/scripts/set_user_id.py b/caravel/scripts/set_user_id.py
new file mode 100755
index 0000000..562fa7c
--- /dev/null
+++ b/caravel/scripts/set_user_id.py
@@ -0,0 +1,388 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#----------------------------------------------------------------------
+#
+# set_user_id.py ---
+#
+# Manipulate the magic database, GDS, and verilog source files for the
+# user_id_programming block to set the user ID number.
+#
+# The user ID number is a 32-bit value that is passed to this routine
+# as an 8-digit hex number. If not given as an option, then the script
+# will look for the value of the key "project_id" in the info.yaml file
+# in the project top level directory
+#
+# user_id_programming layout map:
+# Positions marked (in microns) for value = 0. For value = 1, move
+# the via 0.92um to the left.
+#
+# Layout grid is 0.46um x 0.34um with half-pitch offset (0.23um, 0.17um)
+#
+# Signal Via position (um)
+# name X Y
+#--------------------------------
+# mask_rev[0] 14.49 9.35
+# mask_rev[1] 16.33 9.35
+# mask_rev[2] 10.35 20.23
+# mask_rev[3] 8.05 9.35
+# mask_rev[4] 28.29 9.35
+# mask_rev[5] 21.85 25.67
+# mask_rev[6] 8.05 20.23
+# mask_rev[7] 20.47 9.35
+# mask_rev[8] 17.25 17.85
+# mask_rev[9] 25.53 12.07
+# mask_rev[10] 22.31 20.23
+# mask_rev[11] 13.11 9.35
+# mask_rev[12] 23.69 23.29
+# mask_rev[13] 24.15 12.07
+# mask_rev[14] 13.57 17.85
+# mask_rev[15] 23.23 6.97
+# mask_rev[16] 24.15 17.85
+# mask_rev[17] 8.51 17.85
+# mask_rev[18] 23.69 20.23
+# mask_rev[19] 10.81 23.29
+# mask_rev[20] 14.95 6.97
+# mask_rev[21] 18.17 23.29
+# mask_rev[22] 21.39 17.85
+# mask_rev[23] 26.45 25.67
+# mask_rev[24] 9.89 17.85
+# mask_rev[25] 15.87 17.85
+# mask_rev[26] 26.45 17.85
+# mask_rev[27] 8.51 6.97
+# mask_rev[28] 10.81 9.35
+# mask_rev[29] 27.83 20.23
+# mask_rev[30] 16.33 23.29
+# mask_rev[31] 8.05 14.79
+#----------------------------------------------------------------------
+
+import os
+import sys
+import re
+import subprocess
+
+def usage():
+ print("Usage:")
+ print("set_user_id.py [<user_id_value>] [<path_to_project>]")
+ print("")
+ print("where:")
+ print(" <user_id_value> is a character string of eight hex digits, and")
+ print(" <path_to_project> is the path to the project top level directory.")
+ print("")
+ print(" If <user_id_value> is not given, then it must exist in the info.yaml file.")
+ print(" If <path_to_project> is not given, then it is assumed to be the cwd.")
+ return 0
+
+if __name__ == '__main__':
+
+ # Coordinate pairs in microns for the zero position on each bit
+ mask_rev = (
+ (14.49, 9.35), (16.33, 9.35), (10.35, 20.23), ( 8.05, 9.35),
+ (28.29, 9.35), (21.85, 25.67), ( 8.05, 20.23), (20.47, 9.35),
+ (17.25, 17.85), (25.53, 12.07), (22.31, 20.23), (13.11, 9.35),
+ (23.69, 23.29), (24.15, 12.07), (13.57, 17.85), (23.23, 6.97),
+ (24.15, 17.85), ( 8.51, 17.85), (23.69, 20.23), (10.81, 23.29),
+ (14.95, 6.97), (18.17, 23.29), (21.39, 17.85), (26.45, 25.67),
+ ( 9.89, 17.85), (15.87, 17.85), (26.45, 17.85), ( 8.51, 6.97),
+ (10.81, 9.35), (27.83, 20.23), (16.33, 23.29), ( 8.05, 14.79));
+
+ optionlist = []
+ arguments = []
+
+ debugmode = False
+ reportmode = False
+
+ for option in sys.argv[1:]:
+ if option.find('-', 0) == 0:
+ optionlist.append(option)
+ else:
+ arguments.append(option)
+
+ if len(arguments) > 2:
+ print("Wrong number of arguments given to set_user_id.py.")
+ usage()
+ sys.exit(0)
+
+ if '-debug' in optionlist:
+ debugmode = True
+ if '-report' in optionlist:
+ reportmode = True
+
+ user_id_value = None
+ user_project_path = None
+
+ if len(arguments) > 0:
+ user_id_value = arguments[0]
+
+ # Convert to binary
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ user_project_path = arguments[0]
+
+ if len(arguments) == 0:
+ user_project_path = os.getcwd()
+ elif len(arguments) == 2:
+ user_project_path = arguments[1]
+ elif user_project_path == None:
+ user_project_path = arguments[0]
+ else:
+ user_project_path = os.getcwd()
+
+ if not os.path.isdir(user_project_path):
+ print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
+ sys.exit(1)
+
+ # Check for valid directories
+
+ if not user_id_value:
+ if os.path.isfile(user_project_path + '/info.yaml'):
+ with open(user_project_path + '/info.yaml', 'r') as ifile:
+ infolines = ifile.read().splitlines()
+ for line in infolines:
+ kvpair = line.split(':')
+ if len(kvpair) == 2:
+ key = kvpair[0].strip()
+ value = kvpair[1].strip()
+ if key == 'project_id':
+ user_id_value = value.strip('"\'')
+ break
+
+ if not user_id_value:
+ print('Error: No project_id key:value pair found in project info.yaml.')
+ sys.exit(1)
+
+ try:
+ user_id_int = int('0x' + user_id_value, 0)
+ user_id_bits = '{0:032b}'.format(user_id_int)
+ except:
+ print('Error: Cannot parse user ID "' + user_id_value + '" as an 8-digit hex number.')
+ sys.exit(1)
+
+ else:
+ print('Error: No info.yaml file and no user ID argument given.')
+ sys.exit(1)
+
+ if reportmode:
+ print(str(user_id_int))
+ sys.exit(0)
+
+ print('Setting project user ID to: ' + user_id_value)
+
+ magpath = user_project_path + '/mag'
+ gdspath = user_project_path + '/gds'
+ vpath = user_project_path + '/verilog'
+ errors = 0
+
+ if not os.path.isdir(gdspath):
+ print('No directory ' + gdspath + ' found (path to GDS).')
+ sys.exit(1)
+
+ if not os.path.isdir(vpath):
+ print('No directory ' + vpath + ' found (path to verilog).')
+ sys.exit(1)
+
+ if not os.path.isdir(magpath):
+ print('No directory ' + magpath + ' found (path to magic databases).')
+ sys.exit(1)
+
+ print('Step 1: Modify GDS of the user_id_programming subcell')
+
+ # Bytes leading up to via position are:
+ viarec = "00 06 0d 02 00 43 00 06 0e 02 00 2c 00 2c 10 03 "
+ viabytes = bytes.fromhex(viarec)
+
+ # Check for either GDS file being gzipped
+ gdsbakgz = gdspath + '/user_id_prog_zero.gds.gz'
+ gdsfilegz = gdspath + '/user_id_programming.gds.gz'
+
+ if os.path.isfile(gdsbakgz):
+ subprocess.run(['gunzip', gdsbakgz],
+ stdout = subprocess.DEVNULL,
+ stderr = subprocess.DEVNULL)
+ zero_zipped = True
+ else:
+ zero_zipped = False
+
+ if os.path.isfile(gdsfilegz):
+ subprocess.run(['gunzip', gdsfilegz],
+ stdout = subprocess.DEVNULL,
+ stderr = subprocess.DEVNULL)
+ file_zipped = True
+ else:
+ file_zipped = False
+
+ # Read the GDS file. If a backup was made of the zero-value
+ # program, then use it.
+
+ gdsbak = gdspath + '/user_id_prog_zero.gds'
+ gdsfile = gdspath + '/user_id_programming.gds'
+
+ if os.path.isfile(gdsbak):
+ with open(gdsbak, 'rb') as ifile:
+ gdsdata = ifile.read()
+ else:
+ with open(gdsfile, 'rb') as ifile:
+ gdsdata = ifile.read()
+
+ for i in range(0,32):
+ # Ignore any zero bits.
+ if user_id_bits[i] == '0':
+ continue
+
+ coords = mask_rev[i]
+ xum = coords[0]
+ yum = coords[1]
+
+ # Contact is 0.17 x 0.17, so add and subtract 0.085 to get
+ # the corner positions.
+
+ xllum = xum - 0.085
+ yllum = yum - 0.085
+ xurum = xum + 0.085
+ yurum = yum + 0.085
+
+ # Get the 4-byte hex values for the corner coordinates
+ xllnm = round(xllum * 1000)
+ yllnm = round(yllum * 1000)
+ xllhex = '{0:08x}'.format(xllnm)
+ yllhex = '{0:08x}'.format(yllnm)
+ xurnm = round(xurum * 1000)
+ yurnm = round(yurum * 1000)
+ xurhex = '{0:08x}'.format(xurnm)
+ yurhex = '{0:08x}'.format(yurnm)
+
+ # Magic's GDS output for vias always starts at the lower left
+ # corner and goes counterclockwise, repeating the first point.
+ viaoldposdata = viarec + xllhex + yllhex + xurhex + yllhex
+ viaoldposdata += xurhex + yurhex + xllhex + yurhex + xllhex + yllhex
+
+ # For "one" bits, the X position is moved 0.92 microns to the left
+ newxllum = xllum - 0.92
+ newxurum = xurum - 0.92
+
+ # Get the 4-byte hex values for the new corner coordinates
+ newxllnm = round(newxllum * 1000)
+ newxllhex = '{0:08x}'.format(newxllnm)
+ newxurnm = round(newxurum * 1000)
+ newxurhex = '{0:08x}'.format(newxurnm)
+
+ vianewposdata = viarec + newxllhex + yllhex + newxurhex + yllhex
+ vianewposdata += newxurhex + yurhex + newxllhex + yurhex + newxllhex + yllhex
+
+ # Diagnostic
+ if debugmode:
+ print('Bit ' + str(i) + ':')
+ print('Via position ({0:3.2f}, {1:3.2f}) to ({2:3.2f}, {3:3.2f})'.format(xllum, yllum, xurum, yurum))
+ print('Old hex string = ' + viaoldposdata)
+ print('New hex string = ' + vianewposdata)
+
+ # Convert hex strings to byte arrays
+ viaoldbytedata = bytearray.fromhex(viaoldposdata)
+ vianewbytedata = bytearray.fromhex(vianewposdata)
+
+ # Replace the old data with the new
+ if viaoldbytedata not in gdsdata:
+ print('Error: via not found for bit position ' + str(i))
+ errors += 1
+ else:
+ gdsdata = gdsdata.replace(viaoldbytedata, vianewbytedata)
+
+ if errors == 0:
+ # Keep a copy of the original
+ if not os.path.isfile(gdsbak):
+ if file_zipped:
+ if os.path.isfile(gdsfilegz):
+ os.rename(gdsfilegz, gdsbakgz)
+ else:
+ os.rename(gdsfile, gdsbak)
+ subprocess.run(['gzip', gdsbak, '-n', '--best'],
+ stdout = subprocess.DEVNULL,
+ stderr = subprocess.DEVNULL)
+ else:
+ os.rename(gdsfile, gdsbak)
+
+ with open(gdsfile, 'wb') as ofile:
+ ofile.write(gdsdata)
+ if file_zipped:
+ subprocess.run(['gzip', gdsfile, '-n', '--best'],
+ stdout = subprocess.DEVNULL,
+ stderr = subprocess.DEVNULL)
+
+ print('Done!')
+
+ else:
+ print('There were errors in processing. No file written.')
+ print('Ending process.')
+ sys.exit(1)
+
+ print('Step 2: Add user project ID parameter to verilog.')
+
+ changed = False
+ with open(vpath + '/rtl/caravel.v', 'r') as ifile:
+ vlines = ifile.read().splitlines()
+ outlines = []
+ for line in vlines:
+ oline = re.sub("parameter USER_PROJECT_ID = 32'h[0-9A-F]+;",
+ "parameter USER_PROJECT_ID = 32'h" + user_id_value + ";",
+ line)
+ if oline != line:
+ changed = True
+ outlines.append(oline)
+
+ if changed:
+ with open(vpath + '/rtl/caravel.v', 'w') as ofile:
+ for line in outlines:
+ print(line, file=ofile)
+ print('Done!')
+ else:
+ print('Error: No substitutions done on verilog/rtl/caravel.v.')
+ print('Ending process.')
+ sys.exit(1)
+
+ print('Step 3: Add user project ID text to top level layout.')
+
+ with open(magpath + '/user_id_textblock.mag', 'r') as ifile:
+ maglines = ifile.read().splitlines()
+ outlines = []
+ digit = 0
+ wasseen = {}
+ for line in maglines:
+ if 'alphaX_' in line:
+ dchar = user_id_value[7 - digit].upper()
+ oline = re.sub('alpha_[0-9A-F]', 'alpha_' + dchar, line)
+ # Add path reference if cell was not previously found in the file
+ if dchar not in wasseen:
+ if 'hexdigits' not in oline:
+ oline += ' hexdigits'
+ outlines.append(oline)
+ wasseen[dchar] = True
+ digit += 1
+ else:
+ outlines.append(line)
+
+ if digit == 8:
+ with open(magpath + '/user_id_textblock.mag', 'w') as ofile:
+ for line in outlines:
+ print(line, file=ofile)
+ print('Done!')
+ elif digit == 0:
+ print('Error: No digits were replaced in the layout.')
+ else:
+ print('Error: Only ' + str(digit) + ' digits were replaced in the layout.')
+
+ sys.exit(0)
diff --git a/caravel/spi/lvs/caravan.spice b/caravel/spi/lvs/caravan.spice
new file mode 100644
index 0000000..0654ec8
--- /dev/null
+++ b/caravel/spi/lvs/caravan.spice
@@ -0,0 +1,2121 @@
+* NGSPICE file created from caravan.ext - technology: sky130A
+
+* Black-box entry subcircuit for gpio_control_block abstract view
+.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
++ gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4] gpio_defaults[5]
++ gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9] mgmt_gpio_in
++ mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en pad_gpio_ana_pol pad_gpio_ana_sel
++ pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover pad_gpio_ib_mode_sel
++ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
++ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
++ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
+.ends
+
+* Black-box entry subcircuit for digital_pll abstract view
+.subckt digital_pll VGND VPWR clockp[0] clockp[1] dco div[0] div[1] div[2] div[3]
++ div[4] enable ext_trim[0] ext_trim[10] ext_trim[11] ext_trim[12] ext_trim[13] ext_trim[14]
++ ext_trim[15] ext_trim[16] ext_trim[17] ext_trim[18] ext_trim[19] ext_trim[1] ext_trim[20]
++ ext_trim[21] ext_trim[22] ext_trim[23] ext_trim[24] ext_trim[25] ext_trim[2] ext_trim[3]
++ ext_trim[4] ext_trim[5] ext_trim[6] ext_trim[7] ext_trim[8] ext_trim[9] osc resetb
+.ends
+
+* Black-box entry subcircuit for chip_io_alt abstract view
+.subckt chip_io_alt clock clock_core por flash_clk flash_csb flash_io0 flash_io0_di_core
++ flash_io0_do_core flash_io0_ieb_core flash_io0_oeb_core flash_io1 flash_io1_di_core
++ flash_io1_do_core flash_io1_ieb_core flash_io1_oeb_core gpio gpio_in_core gpio_inenb_core
++ gpio_mode0_core gpio_mode1_core gpio_out_core gpio_outenb_core vccd_pad vdda_pad
++ vddio_pad vddio_pad2 vssa_pad vssd_pad vssio_pad vssio_pad2 mprj_io[0] mprj_io_analog_en[0]
++ mprj_io_analog_pol[0] mprj_io_analog_sel[0] mprj_io_dm[0] mprj_io_dm[1] mprj_io_dm[2]
++ mprj_io_holdover[0] mprj_io_ib_mode_sel[0] mprj_io_inp_dis[0] mprj_io_oeb[0] mprj_io_out[0]
++ mprj_io_slow_sel[0] mprj_io_vtrip_sel[0] mprj_io_in[0] mprj_io_in_3v3[0] mprj_gpio_analog[3]
++ mprj_gpio_noesd[3] mprj_io[10] mprj_io_analog_en[10] mprj_io_analog_pol[10] mprj_io_analog_sel[10]
++ mprj_io_dm[30] mprj_io_dm[31] mprj_io_dm[32] mprj_io_holdover[10] mprj_io_ib_mode_sel[10]
++ mprj_io_inp_dis[10] mprj_io_oeb[10] mprj_io_out[10] mprj_io_slow_sel[10] mprj_io_vtrip_sel[10]
++ mprj_io_in[10] mprj_io_in_3v3[10] mprj_gpio_analog[4] mprj_gpio_noesd[4] mprj_io[11]
++ mprj_io_analog_en[11] mprj_io_analog_pol[11] mprj_io_analog_sel[11] mprj_io_dm[33]
++ mprj_io_dm[34] mprj_io_dm[35] mprj_io_holdover[11] mprj_io_ib_mode_sel[11] mprj_io_inp_dis[11]
++ mprj_io_oeb[11] mprj_io_out[11] mprj_io_slow_sel[11] mprj_io_vtrip_sel[11] mprj_io_in[11]
++ mprj_io_in_3v3[11] mprj_gpio_analog[5] mprj_gpio_noesd[5] mprj_io[12] mprj_io_analog_en[12]
++ mprj_io_analog_pol[12] mprj_io_analog_sel[12] mprj_io_dm[36] mprj_io_dm[37] mprj_io_dm[38]
++ mprj_io_holdover[12] mprj_io_ib_mode_sel[12] mprj_io_inp_dis[12] mprj_io_oeb[12]
++ mprj_io_out[12] mprj_io_slow_sel[12] mprj_io_vtrip_sel[12] mprj_io_in[12] mprj_io_in_3v3[12]
++ mprj_gpio_analog[6] mprj_gpio_noesd[6] mprj_io[13] mprj_io_analog_en[13] mprj_io_analog_pol[13]
++ mprj_io_analog_sel[13] mprj_io_dm[39] mprj_io_dm[40] mprj_io_dm[41] mprj_io_holdover[13]
++ mprj_io_ib_mode_sel[13] mprj_io_inp_dis[13] mprj_io_oeb[13] mprj_io_out[13] mprj_io_slow_sel[13]
++ mprj_io_vtrip_sel[13] mprj_io_in[13] mprj_io_in_3v3[13] mprj_io[1] mprj_io_analog_en[1]
++ mprj_io_analog_pol[1] mprj_io_analog_sel[1] mprj_io_dm[3] mprj_io_dm[4] mprj_io_dm[5]
++ mprj_io_holdover[1] mprj_io_ib_mode_sel[1] mprj_io_inp_dis[1] mprj_io_oeb[1] mprj_io_out[1]
++ mprj_io_slow_sel[1] mprj_io_vtrip_sel[1] mprj_io_in[1] mprj_io_in_3v3[1] mprj_io[2]
++ mprj_io_analog_en[2] mprj_io_analog_pol[2] mprj_io_analog_sel[2] mprj_io_dm[6] mprj_io_dm[7]
++ mprj_io_dm[8] mprj_io_holdover[2] mprj_io_ib_mode_sel[2] mprj_io_inp_dis[2] mprj_io_oeb[2]
++ mprj_io_out[2] mprj_io_slow_sel[2] mprj_io_vtrip_sel[2] mprj_io_in[2] mprj_io_in_3v3[2]
++ mprj_io[3] mprj_io_analog_en[3] mprj_io_analog_pol[3] mprj_io_analog_sel[3] mprj_io_dm[10]
++ mprj_io_dm[11] mprj_io_dm[9] mprj_io_holdover[3] mprj_io_ib_mode_sel[3] mprj_io_inp_dis[3]
++ mprj_io_oeb[3] mprj_io_out[3] mprj_io_slow_sel[3] mprj_io_vtrip_sel[3] mprj_io_in[3]
++ mprj_io_in_3v3[3] mprj_io[4] mprj_io_analog_en[4] mprj_io_analog_pol[4] mprj_io_analog_sel[4]
++ mprj_io_dm[12] mprj_io_dm[13] mprj_io_dm[14] mprj_io_holdover[4] mprj_io_ib_mode_sel[4]
++ mprj_io_inp_dis[4] mprj_io_oeb[4] mprj_io_out[4] mprj_io_slow_sel[4] mprj_io_vtrip_sel[4]
++ mprj_io_in[4] mprj_io_in_3v3[4] mprj_io[5] mprj_io_analog_en[5] mprj_io_analog_pol[5]
++ mprj_io_analog_sel[5] mprj_io_dm[15] mprj_io_dm[16] mprj_io_dm[17] mprj_io_holdover[5]
++ mprj_io_ib_mode_sel[5] mprj_io_inp_dis[5] mprj_io_oeb[5] mprj_io_out[5] mprj_io_slow_sel[5]
++ mprj_io_vtrip_sel[5] mprj_io_in[5] mprj_io_in_3v3[5] mprj_io[6] mprj_io_analog_en[6]
++ mprj_io_analog_pol[6] mprj_io_analog_sel[6] mprj_io_dm[18] mprj_io_dm[19] mprj_io_dm[20]
++ mprj_io_holdover[6] mprj_io_ib_mode_sel[6] mprj_io_inp_dis[6] mprj_io_oeb[6] mprj_io_out[6]
++ mprj_io_slow_sel[6] mprj_io_vtrip_sel[6] mprj_io_in[6] mprj_io_in_3v3[6] mprj_gpio_analog[0]
++ mprj_gpio_noesd[0] mprj_io[7] mprj_io_analog_en[7] mprj_io_analog_pol[7] mprj_io_analog_sel[7]
++ mprj_io_dm[21] mprj_io_dm[22] mprj_io_dm[23] mprj_io_holdover[7] mprj_io_ib_mode_sel[7]
++ mprj_io_inp_dis[7] mprj_io_oeb[7] mprj_io_out[7] mprj_io_slow_sel[7] mprj_io_vtrip_sel[7]
++ mprj_io_in[7] mprj_io_in_3v3[7] mprj_gpio_analog[1] mprj_gpio_noesd[1] mprj_io[8]
++ mprj_io_analog_en[8] mprj_io_analog_pol[8] mprj_io_analog_sel[8] mprj_io_dm[24]
++ mprj_io_dm[25] mprj_io_dm[26] mprj_io_holdover[8] mprj_io_ib_mode_sel[8] mprj_io_inp_dis[8]
++ mprj_io_oeb[8] mprj_io_out[8] mprj_io_slow_sel[8] mprj_io_vtrip_sel[8] mprj_io_in[8]
++ mprj_io_in_3v3[8] mprj_gpio_analog[2] mprj_gpio_noesd[2] mprj_io[9] mprj_io_analog_en[9]
++ mprj_io_analog_pol[9] mprj_io_analog_sel[9] mprj_io_dm[27] mprj_io_dm[28] mprj_io_dm[29]
++ mprj_io_holdover[9] mprj_io_ib_mode_sel[9] mprj_io_inp_dis[9] mprj_io_oeb[9] mprj_io_out[9]
++ mprj_io_slow_sel[9] mprj_io_vtrip_sel[9] mprj_io_in[9] mprj_io_in_3v3[9] mprj_gpio_analog[7]
++ mprj_gpio_noesd[7] mprj_io[25] mprj_io_analog_en[14] mprj_io_analog_pol[14] mprj_io_analog_sel[14]
++ mprj_io_dm[42] mprj_io_dm[43] mprj_io_dm[44] mprj_io_holdover[14] mprj_io_ib_mode_sel[14]
++ mprj_io_inp_dis[14] mprj_io_oeb[14] mprj_io_out[14] mprj_io_slow_sel[14] mprj_io_vtrip_sel[14]
++ mprj_io_in[14] mprj_io_in_3v3[14] mprj_gpio_analog[17] mprj_gpio_noesd[17] mprj_io[35]
++ mprj_io_analog_en[24] mprj_io_analog_pol[24] mprj_io_analog_sel[24] mprj_io_dm[72]
++ mprj_io_dm[73] mprj_io_dm[74] mprj_io_holdover[24] mprj_io_ib_mode_sel[24] mprj_io_inp_dis[24]
++ mprj_io_oeb[24] mprj_io_out[24] mprj_io_slow_sel[24] mprj_io_vtrip_sel[24] mprj_io_in[24]
++ mprj_io_in_3v3[24] mprj_io[36] mprj_io_analog_en[25] mprj_io_analog_pol[25] mprj_io_analog_sel[25]
++ mprj_io_dm[75] mprj_io_dm[76] mprj_io_dm[77] mprj_io_holdover[25] mprj_io_ib_mode_sel[25]
++ mprj_io_inp_dis[25] mprj_io_oeb[25] mprj_io_out[25] mprj_io_slow_sel[25] mprj_io_vtrip_sel[25]
++ mprj_io_in[25] mprj_io_in_3v3[25] mprj_io[37] mprj_io_analog_en[26] mprj_io_analog_pol[26]
++ mprj_io_analog_sel[26] mprj_io_dm[78] mprj_io_dm[79] mprj_io_dm[80] mprj_io_holdover[26]
++ mprj_io_ib_mode_sel[26] mprj_io_inp_dis[26] mprj_io_oeb[26] mprj_io_out[26] mprj_io_slow_sel[26]
++ mprj_io_vtrip_sel[26] mprj_io_in[26] mprj_io_in_3v3[26] mprj_gpio_analog[8] mprj_gpio_noesd[8]
++ mprj_io[26] mprj_io_analog_en[15] mprj_io_analog_pol[15] mprj_io_analog_sel[15]
++ mprj_io_dm[45] mprj_io_dm[46] mprj_io_dm[47] mprj_io_holdover[15] mprj_io_ib_mode_sel[15]
++ mprj_io_inp_dis[15] mprj_io_oeb[15] mprj_io_out[15] mprj_io_slow_sel[15] mprj_io_vtrip_sel[15]
++ mprj_io_in[15] mprj_io_in_3v3[15] mprj_gpio_analog[9] mprj_gpio_noesd[9] mprj_io[27]
++ mprj_io_analog_en[16] mprj_io_analog_pol[16] mprj_io_analog_sel[16] mprj_io_dm[48]
++ mprj_io_dm[49] mprj_io_dm[50] mprj_io_holdover[16] mprj_io_ib_mode_sel[16] mprj_io_inp_dis[16]
++ mprj_io_oeb[16] mprj_io_out[16] mprj_io_slow_sel[16] mprj_io_vtrip_sel[16] mprj_io_in[16]
++ mprj_io_in_3v3[16] mprj_gpio_analog[10] mprj_gpio_noesd[10] mprj_io[28] mprj_io_analog_en[17]
++ mprj_io_analog_pol[17] mprj_io_analog_sel[17] mprj_io_dm[51] mprj_io_dm[52] mprj_io_dm[53]
++ mprj_io_holdover[17] mprj_io_ib_mode_sel[17] mprj_io_inp_dis[17] mprj_io_oeb[17]
++ mprj_io_out[17] mprj_io_slow_sel[17] mprj_io_vtrip_sel[17] mprj_io_in[17] mprj_io_in_3v3[17]
++ mprj_gpio_analog[11] mprj_gpio_noesd[11] mprj_io[29] mprj_io_analog_en[18] mprj_io_analog_pol[18]
++ mprj_io_analog_sel[18] mprj_io_dm[54] mprj_io_dm[55] mprj_io_dm[56] mprj_io_holdover[18]
++ mprj_io_ib_mode_sel[18] mprj_io_inp_dis[18] mprj_io_oeb[18] mprj_io_out[18] mprj_io_slow_sel[18]
++ mprj_io_vtrip_sel[18] mprj_io_in[18] mprj_io_in_3v3[18] mprj_gpio_analog[12] mprj_gpio_noesd[12]
++ mprj_io[30] mprj_io_analog_en[19] mprj_io_analog_pol[19] mprj_io_analog_sel[19]
++ mprj_io_dm[57] mprj_io_dm[58] mprj_io_dm[59] mprj_io_holdover[19] mprj_io_ib_mode_sel[19]
++ mprj_io_inp_dis[19] mprj_io_oeb[19] mprj_io_out[19] mprj_io_slow_sel[19] mprj_io_vtrip_sel[19]
++ mprj_io_in[19] mprj_io_in_3v3[19] mprj_gpio_analog[13] mprj_gpio_noesd[13] mprj_io[31]
++ mprj_io_analog_en[20] mprj_io_analog_pol[20] mprj_io_analog_sel[20] mprj_io_dm[60]
++ mprj_io_dm[61] mprj_io_dm[62] mprj_io_holdover[20] mprj_io_ib_mode_sel[20] mprj_io_inp_dis[20]
++ mprj_io_oeb[20] mprj_io_out[20] mprj_io_slow_sel[20] mprj_io_vtrip_sel[20] mprj_io_in[20]
++ mprj_io_in_3v3[20] mprj_gpio_analog[14] mprj_gpio_noesd[14] mprj_io[32] mprj_io_analog_en[21]
++ mprj_io_analog_pol[21] mprj_io_analog_sel[21] mprj_io_dm[63] mprj_io_dm[64] mprj_io_dm[65]
++ mprj_io_holdover[21] mprj_io_ib_mode_sel[21] mprj_io_inp_dis[21] mprj_io_oeb[21]
++ mprj_io_out[21] mprj_io_slow_sel[21] mprj_io_vtrip_sel[21] mprj_io_in[21] mprj_io_in_3v3[21]
++ mprj_gpio_analog[15] mprj_gpio_noesd[15] mprj_io[33] mprj_io_analog_en[22] mprj_io_analog_pol[22]
++ mprj_io_analog_sel[22] mprj_io_dm[66] mprj_io_dm[67] mprj_io_dm[68] mprj_io_holdover[22]
++ mprj_io_ib_mode_sel[22] mprj_io_inp_dis[22] mprj_io_oeb[22] mprj_io_out[22] mprj_io_slow_sel[22]
++ mprj_io_vtrip_sel[22] mprj_io_in[22] mprj_io_in_3v3[22] mprj_gpio_analog[16] mprj_gpio_noesd[16]
++ mprj_io[34] mprj_io_analog_en[23] mprj_io_analog_pol[23] mprj_io_analog_sel[23]
++ mprj_io_dm[69] mprj_io_dm[70] mprj_io_dm[71] mprj_io_holdover[23] mprj_io_ib_mode_sel[23]
++ mprj_io_inp_dis[23] mprj_io_oeb[23] mprj_io_out[23] mprj_io_slow_sel[23] mprj_io_vtrip_sel[23]
++ mprj_io_in[23] mprj_io_in_3v3[23] porb_h resetb resetb_core_h vdda vssa vssd mprj_analog[0]
++ mprj_io[15] mprj_analog[1] mprj_io[16] mprj_analog[2] mprj_io[17] mprj_analog[3]
++ mprj_io[14] mprj_analog[4] mprj_clamp_high[0] mprj_clamp_low[0] mprj_io[18] vccd1_pad
++ vdda1_pad vdda1_pad2 vssa1_pad vssa1_pad2 vccd1 vdda1 vssa1 vssd1 vssd1_pad mprj_analog[7]
++ mprj_io[21] mprj_analog[8] mprj_io[22] mprj_analog[9] mprj_io[23] mprj_analog[10]
++ mprj_io[24] mprj_analog[5] mprj_clamp_high[1] mprj_clamp_low[1] mprj_io[19] mprj_analog[6]
++ mprj_clamp_high[2] mprj_clamp_low[2] mprj_io[20] vccd2_pad vdda2_pad vssa2_pad vccd
++ vccd2 vdda2 vddio vssa2 vssd2 vssd2_pad vssio flash_csb_core flash_clk_ieb_core
++ flash_clk_oeb_core flash_clk_core flash_csb_oeb_core flash_csb_ieb_core
+.ends
+
+* Black-box entry subcircuit for gpio_defaults_block abstract view
+.subckt gpio_defaults_block VGND VPWR gpio_defaults[0] gpio_defaults[10] gpio_defaults[11]
++ gpio_defaults[12] gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4]
++ gpio_defaults[5] gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9]
+.ends
+
+* Black-box entry subcircuit for mgmt_core_wrapper abstract view
+.subckt mgmt_core_wrapper VGND VPWR core_clk core_rstn debug_in debug_mode debug_oeb
++ debug_out flash_clk flash_csb flash_io0_di flash_io0_do flash_io0_oeb flash_io1_di
++ flash_io1_do flash_io1_oeb flash_io2_di flash_io2_do flash_io2_oeb flash_io3_di
++ flash_io3_do flash_io3_oeb gpio_in_pad gpio_inenb_pad gpio_mode0_pad gpio_mode1_pad
++ gpio_out_pad gpio_outenb_pad hk_ack_i hk_dat_i[0] hk_dat_i[10] hk_dat_i[11] hk_dat_i[12]
++ hk_dat_i[13] hk_dat_i[14] hk_dat_i[15] hk_dat_i[16] hk_dat_i[17] hk_dat_i[18] hk_dat_i[19]
++ hk_dat_i[1] hk_dat_i[20] hk_dat_i[21] hk_dat_i[22] hk_dat_i[23] hk_dat_i[24] hk_dat_i[25]
++ hk_dat_i[26] hk_dat_i[27] hk_dat_i[28] hk_dat_i[29] hk_dat_i[2] hk_dat_i[30] hk_dat_i[31]
++ hk_dat_i[3] hk_dat_i[4] hk_dat_i[5] hk_dat_i[6] hk_dat_i[7] hk_dat_i[8] hk_dat_i[9]
++ hk_stb_o irq[0] irq[1] irq[2] irq[3] irq[4] irq[5] la_iena[0] la_iena[100] la_iena[101]
++ la_iena[102] la_iena[103] la_iena[104] la_iena[105] la_iena[106] la_iena[107] la_iena[108]
++ la_iena[109] la_iena[10] la_iena[110] la_iena[111] la_iena[112] la_iena[113] la_iena[114]
++ la_iena[115] la_iena[116] la_iena[117] la_iena[118] la_iena[119] la_iena[11] la_iena[120]
++ la_iena[121] la_iena[122] la_iena[123] la_iena[124] la_iena[125] la_iena[126] la_iena[127]
++ la_iena[12] la_iena[13] la_iena[14] la_iena[15] la_iena[16] la_iena[17] la_iena[18]
++ la_iena[19] la_iena[1] la_iena[20] la_iena[21] la_iena[22] la_iena[23] la_iena[24]
++ la_iena[25] la_iena[26] la_iena[27] la_iena[28] la_iena[29] la_iena[2] la_iena[30]
++ la_iena[31] la_iena[32] la_iena[33] la_iena[34] la_iena[35] la_iena[36] la_iena[37]
++ la_iena[38] la_iena[39] la_iena[3] la_iena[40] la_iena[41] la_iena[42] la_iena[43]
++ la_iena[44] la_iena[45] la_iena[46] la_iena[47] la_iena[48] la_iena[49] la_iena[4]
++ la_iena[50] la_iena[51] la_iena[52] la_iena[53] la_iena[54] la_iena[55] la_iena[56]
++ la_iena[57] la_iena[58] la_iena[59] la_iena[5] la_iena[60] la_iena[61] la_iena[62]
++ la_iena[63] la_iena[64] la_iena[65] la_iena[66] la_iena[67] la_iena[68] la_iena[69]
++ la_iena[6] la_iena[70] la_iena[71] la_iena[72] la_iena[73] la_iena[74] la_iena[75]
++ la_iena[76] la_iena[77] la_iena[78] la_iena[79] la_iena[7] la_iena[80] la_iena[81]
++ la_iena[82] la_iena[83] la_iena[84] la_iena[85] la_iena[86] la_iena[87] la_iena[88]
++ la_iena[89] la_iena[8] la_iena[90] la_iena[91] la_iena[92] la_iena[93] la_iena[94]
++ la_iena[95] la_iena[96] la_iena[97] la_iena[98] la_iena[99] la_iena[9] la_input[0]
++ la_input[100] la_input[101] la_input[102] la_input[103] la_input[104] la_input[105]
++ la_input[106] la_input[107] la_input[108] la_input[109] la_input[10] la_input[110]
++ la_input[111] la_input[112] la_input[113] la_input[114] la_input[115] la_input[116]
++ la_input[117] la_input[118] la_input[119] la_input[11] la_input[120] la_input[121]
++ la_input[122] la_input[123] la_input[124] la_input[125] la_input[126] la_input[127]
++ la_input[12] la_input[13] la_input[14] la_input[15] la_input[16] la_input[17] la_input[18]
++ la_input[19] la_input[1] la_input[20] la_input[21] la_input[22] la_input[23] la_input[24]
++ la_input[25] la_input[26] la_input[27] la_input[28] la_input[29] la_input[2] la_input[30]
++ la_input[31] la_input[32] la_input[33] la_input[34] la_input[35] la_input[36] la_input[37]
++ la_input[38] la_input[39] la_input[3] la_input[40] la_input[41] la_input[42] la_input[43]
++ la_input[44] la_input[45] la_input[46] la_input[47] la_input[48] la_input[49] la_input[4]
++ la_input[50] la_input[51] la_input[52] la_input[53] la_input[54] la_input[55] la_input[56]
++ la_input[57] la_input[58] la_input[59] la_input[5] la_input[60] la_input[61] la_input[62]
++ la_input[63] la_input[64] la_input[65] la_input[66] la_input[67] la_input[68] la_input[69]
++ la_input[6] la_input[70] la_input[71] la_input[72] la_input[73] la_input[74] la_input[75]
++ la_input[76] la_input[77] la_input[78] la_input[79] la_input[7] la_input[80] la_input[81]
++ la_input[82] la_input[83] la_input[84] la_input[85] la_input[86] la_input[87] la_input[88]
++ la_input[89] la_input[8] la_input[90] la_input[91] la_input[92] la_input[93] la_input[94]
++ la_input[95] la_input[96] la_input[97] la_input[98] la_input[99] la_input[9] la_oenb[0]
++ la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106]
++ la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112]
++ la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119]
++ la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125]
++ la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16]
++ la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22]
++ la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29]
++ la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35]
++ la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41]
++ la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48]
++ la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54]
++ la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60]
++ la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67]
++ la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73]
++ la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7]
++ la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86]
++ la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92]
++ la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99]
++ la_oenb[9] la_output[0] la_output[100] la_output[101] la_output[102] la_output[103]
++ la_output[104] la_output[105] la_output[106] la_output[107] la_output[108] la_output[109]
++ la_output[10] la_output[110] la_output[111] la_output[112] la_output[113] la_output[114]
++ la_output[115] la_output[116] la_output[117] la_output[118] la_output[119] la_output[11]
++ la_output[120] la_output[121] la_output[122] la_output[123] la_output[124] la_output[125]
++ la_output[126] la_output[127] la_output[12] la_output[13] la_output[14] la_output[15]
++ la_output[16] la_output[17] la_output[18] la_output[19] la_output[1] la_output[20]
++ la_output[21] la_output[22] la_output[23] la_output[24] la_output[25] la_output[26]
++ la_output[27] la_output[28] la_output[29] la_output[2] la_output[30] la_output[31]
++ la_output[32] la_output[33] la_output[34] la_output[35] la_output[36] la_output[37]
++ la_output[38] la_output[39] la_output[3] la_output[40] la_output[41] la_output[42]
++ la_output[43] la_output[44] la_output[45] la_output[46] la_output[47] la_output[48]
++ la_output[49] la_output[4] la_output[50] la_output[51] la_output[52] la_output[53]
++ la_output[54] la_output[55] la_output[56] la_output[57] la_output[58] la_output[59]
++ la_output[5] la_output[60] la_output[61] la_output[62] la_output[63] la_output[64]
++ la_output[65] la_output[66] la_output[67] la_output[68] la_output[69] la_output[6]
++ la_output[70] la_output[71] la_output[72] la_output[73] la_output[74] la_output[75]
++ la_output[76] la_output[77] la_output[78] la_output[79] la_output[7] la_output[80]
++ la_output[81] la_output[82] la_output[83] la_output[84] la_output[85] la_output[86]
++ la_output[87] la_output[88] la_output[89] la_output[8] la_output[90] la_output[91]
++ la_output[92] la_output[93] la_output[94] la_output[95] la_output[96] la_output[97]
++ la_output[98] la_output[99] la_output[9] mprj_ack_i mprj_adr_o[0] mprj_adr_o[10]
++ mprj_adr_o[11] mprj_adr_o[12] mprj_adr_o[13] mprj_adr_o[14] mprj_adr_o[15] mprj_adr_o[16]
++ mprj_adr_o[17] mprj_adr_o[18] mprj_adr_o[19] mprj_adr_o[1] mprj_adr_o[20] mprj_adr_o[21]
++ mprj_adr_o[22] mprj_adr_o[23] mprj_adr_o[24] mprj_adr_o[25] mprj_adr_o[26] mprj_adr_o[27]
++ mprj_adr_o[28] mprj_adr_o[29] mprj_adr_o[2] mprj_adr_o[30] mprj_adr_o[31] mprj_adr_o[3]
++ mprj_adr_o[4] mprj_adr_o[5] mprj_adr_o[6] mprj_adr_o[7] mprj_adr_o[8] mprj_adr_o[9]
++ mprj_cyc_o mprj_dat_i[0] mprj_dat_i[10] mprj_dat_i[11] mprj_dat_i[12] mprj_dat_i[13]
++ mprj_dat_i[14] mprj_dat_i[15] mprj_dat_i[16] mprj_dat_i[17] mprj_dat_i[18] mprj_dat_i[19]
++ mprj_dat_i[1] mprj_dat_i[20] mprj_dat_i[21] mprj_dat_i[22] mprj_dat_i[23] mprj_dat_i[24]
++ mprj_dat_i[25] mprj_dat_i[26] mprj_dat_i[27] mprj_dat_i[28] mprj_dat_i[29] mprj_dat_i[2]
++ mprj_dat_i[30] mprj_dat_i[31] mprj_dat_i[3] mprj_dat_i[4] mprj_dat_i[5] mprj_dat_i[6]
++ mprj_dat_i[7] mprj_dat_i[8] mprj_dat_i[9] mprj_dat_o[0] mprj_dat_o[10] mprj_dat_o[11]
++ mprj_dat_o[12] mprj_dat_o[13] mprj_dat_o[14] mprj_dat_o[15] mprj_dat_o[16] mprj_dat_o[17]
++ mprj_dat_o[18] mprj_dat_o[19] mprj_dat_o[1] mprj_dat_o[20] mprj_dat_o[21] mprj_dat_o[22]
++ mprj_dat_o[23] mprj_dat_o[24] mprj_dat_o[25] mprj_dat_o[26] mprj_dat_o[27] mprj_dat_o[28]
++ mprj_dat_o[29] mprj_dat_o[2] mprj_dat_o[30] mprj_dat_o[31] mprj_dat_o[3] mprj_dat_o[4]
++ mprj_dat_o[5] mprj_dat_o[6] mprj_dat_o[7] mprj_dat_o[8] mprj_dat_o[9] mprj_sel_o[0]
++ mprj_sel_o[1] mprj_sel_o[2] mprj_sel_o[3] mprj_stb_o mprj_wb_iena mprj_we_o qspi_enabled
++ ser_rx ser_tx spi_csb spi_enabled spi_sck spi_sdi spi_sdo spi_sdoenb sram_ro_addr[0]
++ sram_ro_addr[1] sram_ro_addr[2] sram_ro_addr[3] sram_ro_addr[4] sram_ro_addr[5]
++ sram_ro_addr[6] sram_ro_addr[7] sram_ro_clk sram_ro_csb sram_ro_data[0] sram_ro_data[10]
++ sram_ro_data[11] sram_ro_data[12] sram_ro_data[13] sram_ro_data[14] sram_ro_data[15]
++ sram_ro_data[16] sram_ro_data[17] sram_ro_data[18] sram_ro_data[19] sram_ro_data[1]
++ sram_ro_data[20] sram_ro_data[21] sram_ro_data[22] sram_ro_data[23] sram_ro_data[24]
++ sram_ro_data[25] sram_ro_data[26] sram_ro_data[27] sram_ro_data[28] sram_ro_data[29]
++ sram_ro_data[2] sram_ro_data[30] sram_ro_data[31] sram_ro_data[3] sram_ro_data[4]
++ sram_ro_data[5] sram_ro_data[6] sram_ro_data[7] sram_ro_data[8] sram_ro_data[9]
++ trap uart_enabled user_irq_ena[0] user_irq_ena[1] user_irq_ena[2]
+.ends
+
+* Black-box entry subcircuit for simple_por abstract view
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+.ends
+
+* Black-box entry subcircuit for caravel_clocking abstract view
+.subckt caravel_clocking VGND VPWR core_clk ext_clk ext_clk_sel ext_reset pll_clk
++ pll_clk90 resetb resetb_sync sel2[0] sel2[1] sel2[2] sel[0] sel[1] sel[2] user_clk
+.ends
+
+* Black-box entry subcircuit for user_id_programming abstract view
+.subckt user_id_programming mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13]
++ mask_rev[14] mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1]
++ mask_rev[20] mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26]
++ mask_rev[27] mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3]
++ mask_rev[4] mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for mgmt_protect abstract view
+.subckt mgmt_protect caravel_clk caravel_clk2 caravel_rstn la_data_in_core[0] la_data_in_core[100]
++ la_data_in_core[101] la_data_in_core[102] la_data_in_core[103] la_data_in_core[104]
++ la_data_in_core[105] la_data_in_core[106] la_data_in_core[107] la_data_in_core[108]
++ la_data_in_core[109] la_data_in_core[10] la_data_in_core[110] la_data_in_core[111]
++ la_data_in_core[112] la_data_in_core[113] la_data_in_core[114] la_data_in_core[115]
++ la_data_in_core[116] la_data_in_core[117] la_data_in_core[118] la_data_in_core[119]
++ la_data_in_core[11] la_data_in_core[120] la_data_in_core[121] la_data_in_core[122]
++ la_data_in_core[123] la_data_in_core[124] la_data_in_core[125] la_data_in_core[126]
++ la_data_in_core[127] la_data_in_core[12] la_data_in_core[13] la_data_in_core[14]
++ la_data_in_core[15] la_data_in_core[16] la_data_in_core[17] la_data_in_core[18]
++ la_data_in_core[19] la_data_in_core[1] la_data_in_core[20] la_data_in_core[21] la_data_in_core[22]
++ la_data_in_core[23] la_data_in_core[24] la_data_in_core[25] la_data_in_core[26]
++ la_data_in_core[27] la_data_in_core[28] la_data_in_core[29] la_data_in_core[2] la_data_in_core[30]
++ la_data_in_core[31] la_data_in_core[32] la_data_in_core[33] la_data_in_core[34]
++ la_data_in_core[35] la_data_in_core[36] la_data_in_core[37] la_data_in_core[38]
++ la_data_in_core[39] la_data_in_core[3] la_data_in_core[40] la_data_in_core[41] la_data_in_core[42]
++ la_data_in_core[43] la_data_in_core[44] la_data_in_core[45] la_data_in_core[46]
++ la_data_in_core[47] la_data_in_core[48] la_data_in_core[49] la_data_in_core[4] la_data_in_core[50]
++ la_data_in_core[51] la_data_in_core[52] la_data_in_core[53] la_data_in_core[54]
++ la_data_in_core[55] la_data_in_core[56] la_data_in_core[57] la_data_in_core[58]
++ la_data_in_core[59] la_data_in_core[5] la_data_in_core[60] la_data_in_core[61] la_data_in_core[62]
++ la_data_in_core[63] la_data_in_core[64] la_data_in_core[65] la_data_in_core[66]
++ la_data_in_core[67] la_data_in_core[68] la_data_in_core[69] la_data_in_core[6] la_data_in_core[70]
++ la_data_in_core[71] la_data_in_core[72] la_data_in_core[73] la_data_in_core[74]
++ la_data_in_core[75] la_data_in_core[76] la_data_in_core[77] la_data_in_core[78]
++ la_data_in_core[79] la_data_in_core[7] la_data_in_core[80] la_data_in_core[81] la_data_in_core[82]
++ la_data_in_core[83] la_data_in_core[84] la_data_in_core[85] la_data_in_core[86]
++ la_data_in_core[87] la_data_in_core[88] la_data_in_core[89] la_data_in_core[8] la_data_in_core[90]
++ la_data_in_core[91] la_data_in_core[92] la_data_in_core[93] la_data_in_core[94]
++ la_data_in_core[95] la_data_in_core[96] la_data_in_core[97] la_data_in_core[98]
++ la_data_in_core[99] la_data_in_core[9] la_data_in_mprj[0] la_data_in_mprj[100] la_data_in_mprj[101]
++ la_data_in_mprj[102] la_data_in_mprj[103] la_data_in_mprj[104] la_data_in_mprj[105]
++ la_data_in_mprj[106] la_data_in_mprj[107] la_data_in_mprj[108] la_data_in_mprj[109]
++ la_data_in_mprj[10] la_data_in_mprj[110] la_data_in_mprj[111] la_data_in_mprj[112]
++ la_data_in_mprj[113] la_data_in_mprj[114] la_data_in_mprj[115] la_data_in_mprj[116]
++ la_data_in_mprj[117] la_data_in_mprj[118] la_data_in_mprj[119] la_data_in_mprj[11]
++ la_data_in_mprj[120] la_data_in_mprj[121] la_data_in_mprj[122] la_data_in_mprj[123]
++ la_data_in_mprj[124] la_data_in_mprj[125] la_data_in_mprj[126] la_data_in_mprj[127]
++ la_data_in_mprj[12] la_data_in_mprj[13] la_data_in_mprj[14] la_data_in_mprj[15]
++ la_data_in_mprj[16] la_data_in_mprj[17] la_data_in_mprj[18] la_data_in_mprj[19]
++ la_data_in_mprj[1] la_data_in_mprj[20] la_data_in_mprj[21] la_data_in_mprj[22] la_data_in_mprj[23]
++ la_data_in_mprj[24] la_data_in_mprj[25] la_data_in_mprj[26] la_data_in_mprj[27]
++ la_data_in_mprj[28] la_data_in_mprj[29] la_data_in_mprj[2] la_data_in_mprj[30] la_data_in_mprj[31]
++ la_data_in_mprj[32] la_data_in_mprj[33] la_data_in_mprj[34] la_data_in_mprj[35]
++ la_data_in_mprj[36] la_data_in_mprj[37] la_data_in_mprj[38] la_data_in_mprj[39]
++ la_data_in_mprj[3] la_data_in_mprj[40] la_data_in_mprj[41] la_data_in_mprj[42] la_data_in_mprj[43]
++ la_data_in_mprj[44] la_data_in_mprj[45] la_data_in_mprj[46] la_data_in_mprj[47]
++ la_data_in_mprj[48] la_data_in_mprj[49] la_data_in_mprj[4] la_data_in_mprj[50] la_data_in_mprj[51]
++ la_data_in_mprj[52] la_data_in_mprj[53] la_data_in_mprj[54] la_data_in_mprj[55]
++ la_data_in_mprj[56] la_data_in_mprj[57] la_data_in_mprj[58] la_data_in_mprj[59]
++ la_data_in_mprj[5] la_data_in_mprj[60] la_data_in_mprj[61] la_data_in_mprj[62] la_data_in_mprj[63]
++ la_data_in_mprj[64] la_data_in_mprj[65] la_data_in_mprj[66] la_data_in_mprj[67]
++ la_data_in_mprj[68] la_data_in_mprj[69] la_data_in_mprj[6] la_data_in_mprj[70] la_data_in_mprj[71]
++ la_data_in_mprj[72] la_data_in_mprj[73] la_data_in_mprj[74] la_data_in_mprj[75]
++ la_data_in_mprj[76] la_data_in_mprj[77] la_data_in_mprj[78] la_data_in_mprj[79]
++ la_data_in_mprj[7] la_data_in_mprj[80] la_data_in_mprj[81] la_data_in_mprj[82] la_data_in_mprj[83]
++ la_data_in_mprj[84] la_data_in_mprj[85] la_data_in_mprj[86] la_data_in_mprj[87]
++ la_data_in_mprj[88] la_data_in_mprj[89] la_data_in_mprj[8] la_data_in_mprj[90] la_data_in_mprj[91]
++ la_data_in_mprj[92] la_data_in_mprj[93] la_data_in_mprj[94] la_data_in_mprj[95]
++ la_data_in_mprj[96] la_data_in_mprj[97] la_data_in_mprj[98] la_data_in_mprj[99]
++ la_data_in_mprj[9] la_data_out_core[0] la_data_out_core[100] la_data_out_core[101]
++ la_data_out_core[102] la_data_out_core[103] la_data_out_core[104] la_data_out_core[105]
++ la_data_out_core[106] la_data_out_core[107] la_data_out_core[108] la_data_out_core[109]
++ la_data_out_core[10] la_data_out_core[110] la_data_out_core[111] la_data_out_core[112]
++ la_data_out_core[113] la_data_out_core[114] la_data_out_core[115] la_data_out_core[116]
++ la_data_out_core[117] la_data_out_core[118] la_data_out_core[119] la_data_out_core[11]
++ la_data_out_core[120] la_data_out_core[121] la_data_out_core[122] la_data_out_core[123]
++ la_data_out_core[124] la_data_out_core[125] la_data_out_core[126] la_data_out_core[127]
++ la_data_out_core[12] la_data_out_core[13] la_data_out_core[14] la_data_out_core[15]
++ la_data_out_core[16] la_data_out_core[17] la_data_out_core[18] la_data_out_core[19]
++ la_data_out_core[1] la_data_out_core[20] la_data_out_core[21] la_data_out_core[22]
++ la_data_out_core[23] la_data_out_core[24] la_data_out_core[25] la_data_out_core[26]
++ la_data_out_core[27] la_data_out_core[28] la_data_out_core[29] la_data_out_core[2]
++ la_data_out_core[30] la_data_out_core[31] la_data_out_core[32] la_data_out_core[33]
++ la_data_out_core[34] la_data_out_core[35] la_data_out_core[36] la_data_out_core[37]
++ la_data_out_core[38] la_data_out_core[39] la_data_out_core[3] la_data_out_core[40]
++ la_data_out_core[41] la_data_out_core[42] la_data_out_core[43] la_data_out_core[44]
++ la_data_out_core[45] la_data_out_core[46] la_data_out_core[47] la_data_out_core[48]
++ la_data_out_core[49] la_data_out_core[4] la_data_out_core[50] la_data_out_core[51]
++ la_data_out_core[52] la_data_out_core[53] la_data_out_core[54] la_data_out_core[55]
++ la_data_out_core[56] la_data_out_core[57] la_data_out_core[58] la_data_out_core[59]
++ la_data_out_core[5] la_data_out_core[60] la_data_out_core[61] la_data_out_core[62]
++ la_data_out_core[63] la_data_out_core[64] la_data_out_core[65] la_data_out_core[66]
++ la_data_out_core[67] la_data_out_core[68] la_data_out_core[69] la_data_out_core[6]
++ la_data_out_core[70] la_data_out_core[71] la_data_out_core[72] la_data_out_core[73]
++ la_data_out_core[74] la_data_out_core[75] la_data_out_core[76] la_data_out_core[77]
++ la_data_out_core[78] la_data_out_core[79] la_data_out_core[7] la_data_out_core[80]
++ la_data_out_core[81] la_data_out_core[82] la_data_out_core[83] la_data_out_core[84]
++ la_data_out_core[85] la_data_out_core[86] la_data_out_core[87] la_data_out_core[88]
++ la_data_out_core[89] la_data_out_core[8] la_data_out_core[90] la_data_out_core[91]
++ la_data_out_core[92] la_data_out_core[93] la_data_out_core[94] la_data_out_core[95]
++ la_data_out_core[96] la_data_out_core[97] la_data_out_core[98] la_data_out_core[99]
++ la_data_out_core[9] la_data_out_mprj[0] la_data_out_mprj[100] la_data_out_mprj[101]
++ la_data_out_mprj[102] la_data_out_mprj[103] la_data_out_mprj[104] la_data_out_mprj[105]
++ la_data_out_mprj[106] la_data_out_mprj[107] la_data_out_mprj[108] la_data_out_mprj[109]
++ la_data_out_mprj[10] la_data_out_mprj[110] la_data_out_mprj[111] la_data_out_mprj[112]
++ la_data_out_mprj[113] la_data_out_mprj[114] la_data_out_mprj[115] la_data_out_mprj[116]
++ la_data_out_mprj[117] la_data_out_mprj[118] la_data_out_mprj[119] la_data_out_mprj[11]
++ la_data_out_mprj[120] la_data_out_mprj[121] la_data_out_mprj[122] la_data_out_mprj[123]
++ la_data_out_mprj[124] la_data_out_mprj[125] la_data_out_mprj[126] la_data_out_mprj[127]
++ la_data_out_mprj[12] la_data_out_mprj[13] la_data_out_mprj[14] la_data_out_mprj[15]
++ la_data_out_mprj[16] la_data_out_mprj[17] la_data_out_mprj[18] la_data_out_mprj[19]
++ la_data_out_mprj[1] la_data_out_mprj[20] la_data_out_mprj[21] la_data_out_mprj[22]
++ la_data_out_mprj[23] la_data_out_mprj[24] la_data_out_mprj[25] la_data_out_mprj[26]
++ la_data_out_mprj[27] la_data_out_mprj[28] la_data_out_mprj[29] la_data_out_mprj[2]
++ la_data_out_mprj[30] la_data_out_mprj[31] la_data_out_mprj[32] la_data_out_mprj[33]
++ la_data_out_mprj[34] la_data_out_mprj[35] la_data_out_mprj[36] la_data_out_mprj[37]
++ la_data_out_mprj[38] la_data_out_mprj[39] la_data_out_mprj[3] la_data_out_mprj[40]
++ la_data_out_mprj[41] la_data_out_mprj[42] la_data_out_mprj[43] la_data_out_mprj[44]
++ la_data_out_mprj[45] la_data_out_mprj[46] la_data_out_mprj[47] la_data_out_mprj[48]
++ la_data_out_mprj[49] la_data_out_mprj[4] la_data_out_mprj[50] la_data_out_mprj[51]
++ la_data_out_mprj[52] la_data_out_mprj[53] la_data_out_mprj[54] la_data_out_mprj[55]
++ la_data_out_mprj[56] la_data_out_mprj[57] la_data_out_mprj[58] la_data_out_mprj[59]
++ la_data_out_mprj[5] la_data_out_mprj[60] la_data_out_mprj[61] la_data_out_mprj[62]
++ la_data_out_mprj[63] la_data_out_mprj[64] la_data_out_mprj[65] la_data_out_mprj[66]
++ la_data_out_mprj[67] la_data_out_mprj[68] la_data_out_mprj[69] la_data_out_mprj[6]
++ la_data_out_mprj[70] la_data_out_mprj[71] la_data_out_mprj[72] la_data_out_mprj[73]
++ la_data_out_mprj[74] la_data_out_mprj[75] la_data_out_mprj[76] la_data_out_mprj[77]
++ la_data_out_mprj[78] la_data_out_mprj[79] la_data_out_mprj[7] la_data_out_mprj[80]
++ la_data_out_mprj[81] la_data_out_mprj[82] la_data_out_mprj[83] la_data_out_mprj[84]
++ la_data_out_mprj[85] la_data_out_mprj[86] la_data_out_mprj[87] la_data_out_mprj[88]
++ la_data_out_mprj[89] la_data_out_mprj[8] la_data_out_mprj[90] la_data_out_mprj[91]
++ la_data_out_mprj[92] la_data_out_mprj[93] la_data_out_mprj[94] la_data_out_mprj[95]
++ la_data_out_mprj[96] la_data_out_mprj[97] la_data_out_mprj[98] la_data_out_mprj[99]
++ la_data_out_mprj[9] la_iena_mprj[0] la_iena_mprj[100] la_iena_mprj[101] la_iena_mprj[102]
++ la_iena_mprj[103] la_iena_mprj[104] la_iena_mprj[105] la_iena_mprj[106] la_iena_mprj[107]
++ la_iena_mprj[108] la_iena_mprj[109] la_iena_mprj[10] la_iena_mprj[110] la_iena_mprj[111]
++ la_iena_mprj[112] la_iena_mprj[113] la_iena_mprj[114] la_iena_mprj[115] la_iena_mprj[116]
++ la_iena_mprj[117] la_iena_mprj[118] la_iena_mprj[119] la_iena_mprj[11] la_iena_mprj[120]
++ la_iena_mprj[121] la_iena_mprj[122] la_iena_mprj[123] la_iena_mprj[124] la_iena_mprj[125]
++ la_iena_mprj[126] la_iena_mprj[127] la_iena_mprj[12] la_iena_mprj[13] la_iena_mprj[14]
++ la_iena_mprj[15] la_iena_mprj[16] la_iena_mprj[17] la_iena_mprj[18] la_iena_mprj[19]
++ la_iena_mprj[1] la_iena_mprj[20] la_iena_mprj[21] la_iena_mprj[22] la_iena_mprj[23]
++ la_iena_mprj[24] la_iena_mprj[25] la_iena_mprj[26] la_iena_mprj[27] la_iena_mprj[28]
++ la_iena_mprj[29] la_iena_mprj[2] la_iena_mprj[30] la_iena_mprj[31] la_iena_mprj[32]
++ la_iena_mprj[33] la_iena_mprj[34] la_iena_mprj[35] la_iena_mprj[36] la_iena_mprj[37]
++ la_iena_mprj[38] la_iena_mprj[39] la_iena_mprj[3] la_iena_mprj[40] la_iena_mprj[41]
++ la_iena_mprj[42] la_iena_mprj[43] la_iena_mprj[44] la_iena_mprj[45] la_iena_mprj[46]
++ la_iena_mprj[47] la_iena_mprj[48] la_iena_mprj[49] la_iena_mprj[4] la_iena_mprj[50]
++ la_iena_mprj[51] la_iena_mprj[52] la_iena_mprj[53] la_iena_mprj[54] la_iena_mprj[55]
++ la_iena_mprj[56] la_iena_mprj[57] la_iena_mprj[58] la_iena_mprj[59] la_iena_mprj[5]
++ la_iena_mprj[60] la_iena_mprj[61] la_iena_mprj[62] la_iena_mprj[63] la_iena_mprj[64]
++ la_iena_mprj[65] la_iena_mprj[66] la_iena_mprj[67] la_iena_mprj[68] la_iena_mprj[69]
++ la_iena_mprj[6] la_iena_mprj[70] la_iena_mprj[71] la_iena_mprj[72] la_iena_mprj[73]
++ la_iena_mprj[74] la_iena_mprj[75] la_iena_mprj[76] la_iena_mprj[77] la_iena_mprj[78]
++ la_iena_mprj[79] la_iena_mprj[7] la_iena_mprj[80] la_iena_mprj[81] la_iena_mprj[82]
++ la_iena_mprj[83] la_iena_mprj[84] la_iena_mprj[85] la_iena_mprj[86] la_iena_mprj[87]
++ la_iena_mprj[88] la_iena_mprj[89] la_iena_mprj[8] la_iena_mprj[90] la_iena_mprj[91]
++ la_iena_mprj[92] la_iena_mprj[93] la_iena_mprj[94] la_iena_mprj[95] la_iena_mprj[96]
++ la_iena_mprj[97] la_iena_mprj[98] la_iena_mprj[99] la_iena_mprj[9] la_oenb_core[0]
++ la_oenb_core[100] la_oenb_core[101] la_oenb_core[102] la_oenb_core[103] la_oenb_core[104]
++ la_oenb_core[105] la_oenb_core[106] la_oenb_core[107] la_oenb_core[108] la_oenb_core[109]
++ la_oenb_core[10] la_oenb_core[110] la_oenb_core[111] la_oenb_core[112] la_oenb_core[113]
++ la_oenb_core[114] la_oenb_core[115] la_oenb_core[116] la_oenb_core[117] la_oenb_core[118]
++ la_oenb_core[119] la_oenb_core[11] la_oenb_core[120] la_oenb_core[121] la_oenb_core[122]
++ la_oenb_core[123] la_oenb_core[124] la_oenb_core[125] la_oenb_core[126] la_oenb_core[127]
++ la_oenb_core[12] la_oenb_core[13] la_oenb_core[14] la_oenb_core[15] la_oenb_core[16]
++ la_oenb_core[17] la_oenb_core[18] la_oenb_core[19] la_oenb_core[1] la_oenb_core[20]
++ la_oenb_core[21] la_oenb_core[22] la_oenb_core[23] la_oenb_core[24] la_oenb_core[25]
++ la_oenb_core[26] la_oenb_core[27] la_oenb_core[28] la_oenb_core[29] la_oenb_core[2]
++ la_oenb_core[30] la_oenb_core[31] la_oenb_core[32] la_oenb_core[33] la_oenb_core[34]
++ la_oenb_core[35] la_oenb_core[36] la_oenb_core[37] la_oenb_core[38] la_oenb_core[39]
++ la_oenb_core[3] la_oenb_core[40] la_oenb_core[41] la_oenb_core[42] la_oenb_core[43]
++ la_oenb_core[44] la_oenb_core[45] la_oenb_core[46] la_oenb_core[47] la_oenb_core[48]
++ la_oenb_core[49] la_oenb_core[4] la_oenb_core[50] la_oenb_core[51] la_oenb_core[52]
++ la_oenb_core[53] la_oenb_core[54] la_oenb_core[55] la_oenb_core[56] la_oenb_core[57]
++ la_oenb_core[58] la_oenb_core[59] la_oenb_core[5] la_oenb_core[60] la_oenb_core[61]
++ la_oenb_core[62] la_oenb_core[63] la_oenb_core[64] la_oenb_core[65] la_oenb_core[66]
++ la_oenb_core[67] la_oenb_core[68] la_oenb_core[69] la_oenb_core[6] la_oenb_core[70]
++ la_oenb_core[71] la_oenb_core[72] la_oenb_core[73] la_oenb_core[74] la_oenb_core[75]
++ la_oenb_core[76] la_oenb_core[77] la_oenb_core[78] la_oenb_core[79] la_oenb_core[7]
++ la_oenb_core[80] la_oenb_core[81] la_oenb_core[82] la_oenb_core[83] la_oenb_core[84]
++ la_oenb_core[85] la_oenb_core[86] la_oenb_core[87] la_oenb_core[88] la_oenb_core[89]
++ la_oenb_core[8] la_oenb_core[90] la_oenb_core[91] la_oenb_core[92] la_oenb_core[93]
++ la_oenb_core[94] la_oenb_core[95] la_oenb_core[96] la_oenb_core[97] la_oenb_core[98]
++ la_oenb_core[99] la_oenb_core[9] la_oenb_mprj[0] la_oenb_mprj[100] la_oenb_mprj[101]
++ la_oenb_mprj[102] la_oenb_mprj[103] la_oenb_mprj[104] la_oenb_mprj[105] la_oenb_mprj[106]
++ la_oenb_mprj[107] la_oenb_mprj[108] la_oenb_mprj[109] la_oenb_mprj[10] la_oenb_mprj[110]
++ la_oenb_mprj[111] la_oenb_mprj[112] la_oenb_mprj[113] la_oenb_mprj[114] la_oenb_mprj[115]
++ la_oenb_mprj[116] la_oenb_mprj[117] la_oenb_mprj[118] la_oenb_mprj[119] la_oenb_mprj[11]
++ la_oenb_mprj[120] la_oenb_mprj[121] la_oenb_mprj[122] la_oenb_mprj[123] la_oenb_mprj[124]
++ la_oenb_mprj[125] la_oenb_mprj[126] la_oenb_mprj[127] la_oenb_mprj[12] la_oenb_mprj[13]
++ la_oenb_mprj[14] la_oenb_mprj[15] la_oenb_mprj[16] la_oenb_mprj[17] la_oenb_mprj[18]
++ la_oenb_mprj[19] la_oenb_mprj[1] la_oenb_mprj[20] la_oenb_mprj[21] la_oenb_mprj[22]
++ la_oenb_mprj[23] la_oenb_mprj[24] la_oenb_mprj[25] la_oenb_mprj[26] la_oenb_mprj[27]
++ la_oenb_mprj[28] la_oenb_mprj[29] la_oenb_mprj[2] la_oenb_mprj[30] la_oenb_mprj[31]
++ la_oenb_mprj[32] la_oenb_mprj[33] la_oenb_mprj[34] la_oenb_mprj[35] la_oenb_mprj[36]
++ la_oenb_mprj[37] la_oenb_mprj[38] la_oenb_mprj[39] la_oenb_mprj[3] la_oenb_mprj[40]
++ la_oenb_mprj[41] la_oenb_mprj[42] la_oenb_mprj[43] la_oenb_mprj[44] la_oenb_mprj[45]
++ la_oenb_mprj[46] la_oenb_mprj[47] la_oenb_mprj[48] la_oenb_mprj[49] la_oenb_mprj[4]
++ la_oenb_mprj[50] la_oenb_mprj[51] la_oenb_mprj[52] la_oenb_mprj[53] la_oenb_mprj[54]
++ la_oenb_mprj[55] la_oenb_mprj[56] la_oenb_mprj[57] la_oenb_mprj[58] la_oenb_mprj[59]
++ la_oenb_mprj[5] la_oenb_mprj[60] la_oenb_mprj[61] la_oenb_mprj[62] la_oenb_mprj[63]
++ la_oenb_mprj[64] la_oenb_mprj[65] la_oenb_mprj[66] la_oenb_mprj[67] la_oenb_mprj[68]
++ la_oenb_mprj[69] la_oenb_mprj[6] la_oenb_mprj[70] la_oenb_mprj[71] la_oenb_mprj[72]
++ la_oenb_mprj[73] la_oenb_mprj[74] la_oenb_mprj[75] la_oenb_mprj[76] la_oenb_mprj[77]
++ la_oenb_mprj[78] la_oenb_mprj[79] la_oenb_mprj[7] la_oenb_mprj[80] la_oenb_mprj[81]
++ la_oenb_mprj[82] la_oenb_mprj[83] la_oenb_mprj[84] la_oenb_mprj[85] la_oenb_mprj[86]
++ la_oenb_mprj[87] la_oenb_mprj[88] la_oenb_mprj[89] la_oenb_mprj[8] la_oenb_mprj[90]
++ la_oenb_mprj[91] la_oenb_mprj[92] la_oenb_mprj[93] la_oenb_mprj[94] la_oenb_mprj[95]
++ la_oenb_mprj[96] la_oenb_mprj[97] la_oenb_mprj[98] la_oenb_mprj[99] la_oenb_mprj[9]
++ mprj_ack_i_core mprj_ack_i_user mprj_adr_o_core[0] mprj_adr_o_core[10] mprj_adr_o_core[11]
++ mprj_adr_o_core[12] mprj_adr_o_core[13] mprj_adr_o_core[14] mprj_adr_o_core[15]
++ mprj_adr_o_core[16] mprj_adr_o_core[17] mprj_adr_o_core[18] mprj_adr_o_core[19]
++ mprj_adr_o_core[1] mprj_adr_o_core[20] mprj_adr_o_core[21] mprj_adr_o_core[22] mprj_adr_o_core[23]
++ mprj_adr_o_core[24] mprj_adr_o_core[25] mprj_adr_o_core[26] mprj_adr_o_core[27]
++ mprj_adr_o_core[28] mprj_adr_o_core[29] mprj_adr_o_core[2] mprj_adr_o_core[30] mprj_adr_o_core[31]
++ mprj_adr_o_core[3] mprj_adr_o_core[4] mprj_adr_o_core[5] mprj_adr_o_core[6] mprj_adr_o_core[7]
++ mprj_adr_o_core[8] mprj_adr_o_core[9] mprj_adr_o_user[0] mprj_adr_o_user[10] mprj_adr_o_user[11]
++ mprj_adr_o_user[12] mprj_adr_o_user[13] mprj_adr_o_user[14] mprj_adr_o_user[15]
++ mprj_adr_o_user[16] mprj_adr_o_user[17] mprj_adr_o_user[18] mprj_adr_o_user[19]
++ mprj_adr_o_user[1] mprj_adr_o_user[20] mprj_adr_o_user[21] mprj_adr_o_user[22] mprj_adr_o_user[23]
++ mprj_adr_o_user[24] mprj_adr_o_user[25] mprj_adr_o_user[26] mprj_adr_o_user[27]
++ mprj_adr_o_user[28] mprj_adr_o_user[29] mprj_adr_o_user[2] mprj_adr_o_user[30] mprj_adr_o_user[31]
++ mprj_adr_o_user[3] mprj_adr_o_user[4] mprj_adr_o_user[5] mprj_adr_o_user[6] mprj_adr_o_user[7]
++ mprj_adr_o_user[8] mprj_adr_o_user[9] mprj_cyc_o_core mprj_cyc_o_user mprj_dat_i_core[0]
++ mprj_dat_i_core[10] mprj_dat_i_core[11] mprj_dat_i_core[12] mprj_dat_i_core[13]
++ mprj_dat_i_core[14] mprj_dat_i_core[15] mprj_dat_i_core[16] mprj_dat_i_core[17]
++ mprj_dat_i_core[18] mprj_dat_i_core[19] mprj_dat_i_core[1] mprj_dat_i_core[20] mprj_dat_i_core[21]
++ mprj_dat_i_core[22] mprj_dat_i_core[23] mprj_dat_i_core[24] mprj_dat_i_core[25]
++ mprj_dat_i_core[26] mprj_dat_i_core[27] mprj_dat_i_core[28] mprj_dat_i_core[29]
++ mprj_dat_i_core[2] mprj_dat_i_core[30] mprj_dat_i_core[31] mprj_dat_i_core[3] mprj_dat_i_core[4]
++ mprj_dat_i_core[5] mprj_dat_i_core[6] mprj_dat_i_core[7] mprj_dat_i_core[8] mprj_dat_i_core[9]
++ mprj_dat_i_user[0] mprj_dat_i_user[10] mprj_dat_i_user[11] mprj_dat_i_user[12] mprj_dat_i_user[13]
++ mprj_dat_i_user[14] mprj_dat_i_user[15] mprj_dat_i_user[16] mprj_dat_i_user[17]
++ mprj_dat_i_user[18] mprj_dat_i_user[19] mprj_dat_i_user[1] mprj_dat_i_user[20] mprj_dat_i_user[21]
++ mprj_dat_i_user[22] mprj_dat_i_user[23] mprj_dat_i_user[24] mprj_dat_i_user[25]
++ mprj_dat_i_user[26] mprj_dat_i_user[27] mprj_dat_i_user[28] mprj_dat_i_user[29]
++ mprj_dat_i_user[2] mprj_dat_i_user[30] mprj_dat_i_user[31] mprj_dat_i_user[3] mprj_dat_i_user[4]
++ mprj_dat_i_user[5] mprj_dat_i_user[6] mprj_dat_i_user[7] mprj_dat_i_user[8] mprj_dat_i_user[9]
++ mprj_dat_o_core[0] mprj_dat_o_core[10] mprj_dat_o_core[11] mprj_dat_o_core[12] mprj_dat_o_core[13]
++ mprj_dat_o_core[14] mprj_dat_o_core[15] mprj_dat_o_core[16] mprj_dat_o_core[17]
++ mprj_dat_o_core[18] mprj_dat_o_core[19] mprj_dat_o_core[1] mprj_dat_o_core[20] mprj_dat_o_core[21]
++ mprj_dat_o_core[22] mprj_dat_o_core[23] mprj_dat_o_core[24] mprj_dat_o_core[25]
++ mprj_dat_o_core[26] mprj_dat_o_core[27] mprj_dat_o_core[28] mprj_dat_o_core[29]
++ mprj_dat_o_core[2] mprj_dat_o_core[30] mprj_dat_o_core[31] mprj_dat_o_core[3] mprj_dat_o_core[4]
++ mprj_dat_o_core[5] mprj_dat_o_core[6] mprj_dat_o_core[7] mprj_dat_o_core[8] mprj_dat_o_core[9]
++ mprj_dat_o_user[0] mprj_dat_o_user[10] mprj_dat_o_user[11] mprj_dat_o_user[12] mprj_dat_o_user[13]
++ mprj_dat_o_user[14] mprj_dat_o_user[15] mprj_dat_o_user[16] mprj_dat_o_user[17]
++ mprj_dat_o_user[18] mprj_dat_o_user[19] mprj_dat_o_user[1] mprj_dat_o_user[20] mprj_dat_o_user[21]
++ mprj_dat_o_user[22] mprj_dat_o_user[23] mprj_dat_o_user[24] mprj_dat_o_user[25]
++ mprj_dat_o_user[26] mprj_dat_o_user[27] mprj_dat_o_user[28] mprj_dat_o_user[29]
++ mprj_dat_o_user[2] mprj_dat_o_user[30] mprj_dat_o_user[31] mprj_dat_o_user[3] mprj_dat_o_user[4]
++ mprj_dat_o_user[5] mprj_dat_o_user[6] mprj_dat_o_user[7] mprj_dat_o_user[8] mprj_dat_o_user[9]
++ mprj_iena_wb mprj_sel_o_core[0] mprj_sel_o_core[1] mprj_sel_o_core[2] mprj_sel_o_core[3]
++ mprj_sel_o_user[0] mprj_sel_o_user[1] mprj_sel_o_user[2] mprj_sel_o_user[3] mprj_stb_o_core
++ mprj_stb_o_user mprj_we_o_core mprj_we_o_user user1_vcc_powergood user1_vdd_powergood
++ user2_vcc_powergood user2_vdd_powergood user_clock user_clock2 user_irq[0] user_irq[1]
++ user_irq[2] user_irq_core[0] user_irq_core[1] user_irq_core[2] user_irq_ena[0] user_irq_ena[1]
++ user_irq_ena[2] user_reset vccd vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd vssd1 vssd2
+.ends
+
+* Black-box entry subcircuit for xres_buf abstract view
+.subckt xres_buf A X VPWR VGND LVPWR LVGND
+.ends
+
+* Black-box entry subcircuit for user_analog_project_wrapper abstract view
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+.ends
+
+* Black-box entry subcircuit for housekeeping abstract view
+.subckt housekeeping VGND VPWR debug_in debug_mode debug_oeb debug_out irq[0] irq[1]
++ irq[2] mask_rev_in[0] mask_rev_in[10] mask_rev_in[11] mask_rev_in[12] mask_rev_in[13]
++ mask_rev_in[14] mask_rev_in[15] mask_rev_in[16] mask_rev_in[17] mask_rev_in[18]
++ mask_rev_in[19] mask_rev_in[1] mask_rev_in[20] mask_rev_in[21] mask_rev_in[22] mask_rev_in[23]
++ mask_rev_in[24] mask_rev_in[25] mask_rev_in[26] mask_rev_in[27] mask_rev_in[28]
++ mask_rev_in[29] mask_rev_in[2] mask_rev_in[30] mask_rev_in[31] mask_rev_in[3] mask_rev_in[4]
++ mask_rev_in[5] mask_rev_in[6] mask_rev_in[7] mask_rev_in[8] mask_rev_in[9] mgmt_gpio_in[0]
++ mgmt_gpio_in[10] mgmt_gpio_in[11] mgmt_gpio_in[12] mgmt_gpio_in[13] mgmt_gpio_in[14]
++ mgmt_gpio_in[15] mgmt_gpio_in[16] mgmt_gpio_in[17] mgmt_gpio_in[18] mgmt_gpio_in[19]
++ mgmt_gpio_in[1] mgmt_gpio_in[20] mgmt_gpio_in[21] mgmt_gpio_in[22] mgmt_gpio_in[23]
++ mgmt_gpio_in[24] mgmt_gpio_in[25] mgmt_gpio_in[26] mgmt_gpio_in[27] mgmt_gpio_in[28]
++ mgmt_gpio_in[29] mgmt_gpio_in[2] mgmt_gpio_in[30] mgmt_gpio_in[31] mgmt_gpio_in[32]
++ mgmt_gpio_in[33] mgmt_gpio_in[34] mgmt_gpio_in[35] mgmt_gpio_in[36] mgmt_gpio_in[37]
++ mgmt_gpio_in[3] mgmt_gpio_in[4] mgmt_gpio_in[5] mgmt_gpio_in[6] mgmt_gpio_in[7]
++ mgmt_gpio_in[8] mgmt_gpio_in[9] mgmt_gpio_oeb[0] mgmt_gpio_oeb[10] mgmt_gpio_oeb[11]
++ mgmt_gpio_oeb[12] mgmt_gpio_oeb[13] mgmt_gpio_oeb[14] mgmt_gpio_oeb[15] mgmt_gpio_oeb[16]
++ mgmt_gpio_oeb[17] mgmt_gpio_oeb[18] mgmt_gpio_oeb[19] mgmt_gpio_oeb[1] mgmt_gpio_oeb[20]
++ mgmt_gpio_oeb[21] mgmt_gpio_oeb[22] mgmt_gpio_oeb[23] mgmt_gpio_oeb[24] mgmt_gpio_oeb[25]
++ mgmt_gpio_oeb[26] mgmt_gpio_oeb[27] mgmt_gpio_oeb[28] mgmt_gpio_oeb[29] mgmt_gpio_oeb[2]
++ mgmt_gpio_oeb[30] mgmt_gpio_oeb[31] mgmt_gpio_oeb[32] mgmt_gpio_oeb[33] mgmt_gpio_oeb[34]
++ mgmt_gpio_oeb[35] mgmt_gpio_oeb[36] mgmt_gpio_oeb[37] mgmt_gpio_oeb[3] mgmt_gpio_oeb[4]
++ mgmt_gpio_oeb[5] mgmt_gpio_oeb[6] mgmt_gpio_oeb[7] mgmt_gpio_oeb[8] mgmt_gpio_oeb[9]
++ mgmt_gpio_out[0] mgmt_gpio_out[10] mgmt_gpio_out[11] mgmt_gpio_out[12] mgmt_gpio_out[13]
++ mgmt_gpio_out[14] mgmt_gpio_out[15] mgmt_gpio_out[16] mgmt_gpio_out[17] mgmt_gpio_out[18]
++ mgmt_gpio_out[19] mgmt_gpio_out[1] mgmt_gpio_out[20] mgmt_gpio_out[21] mgmt_gpio_out[22]
++ mgmt_gpio_out[23] mgmt_gpio_out[24] mgmt_gpio_out[25] mgmt_gpio_out[26] mgmt_gpio_out[27]
++ mgmt_gpio_out[28] mgmt_gpio_out[29] mgmt_gpio_out[2] mgmt_gpio_out[30] mgmt_gpio_out[31]
++ mgmt_gpio_out[32] mgmt_gpio_out[33] mgmt_gpio_out[34] mgmt_gpio_out[35] mgmt_gpio_out[36]
++ mgmt_gpio_out[37] mgmt_gpio_out[3] mgmt_gpio_out[4] mgmt_gpio_out[5] mgmt_gpio_out[6]
++ mgmt_gpio_out[7] mgmt_gpio_out[8] mgmt_gpio_out[9] pad_flash_clk pad_flash_clk_oeb
++ pad_flash_csb pad_flash_csb_oeb pad_flash_io0_di pad_flash_io0_do pad_flash_io0_ieb
++ pad_flash_io0_oeb pad_flash_io1_di pad_flash_io1_do pad_flash_io1_ieb pad_flash_io1_oeb
++ pll90_sel[0] pll90_sel[1] pll90_sel[2] pll_bypass pll_dco_ena pll_div[0] pll_div[1]
++ pll_div[2] pll_div[3] pll_div[4] pll_ena pll_sel[0] pll_sel[1] pll_sel[2] pll_trim[0]
++ pll_trim[10] pll_trim[11] pll_trim[12] pll_trim[13] pll_trim[14] pll_trim[15] pll_trim[16]
++ pll_trim[17] pll_trim[18] pll_trim[19] pll_trim[1] pll_trim[20] pll_trim[21] pll_trim[22]
++ pll_trim[23] pll_trim[24] pll_trim[25] pll_trim[2] pll_trim[3] pll_trim[4] pll_trim[5]
++ pll_trim[6] pll_trim[7] pll_trim[8] pll_trim[9] porb pwr_ctrl_out[0] pwr_ctrl_out[1]
++ pwr_ctrl_out[2] pwr_ctrl_out[3] qspi_enabled reset ser_rx ser_tx serial_clock serial_data_1
++ serial_data_2 serial_load serial_resetn spi_csb spi_enabled spi_sck spi_sdi spi_sdo
++ spi_sdoenb spimemio_flash_clk spimemio_flash_csb spimemio_flash_io0_di spimemio_flash_io0_do
++ spimemio_flash_io0_oeb spimemio_flash_io1_di spimemio_flash_io1_do spimemio_flash_io1_oeb
++ spimemio_flash_io2_di spimemio_flash_io2_do spimemio_flash_io2_oeb spimemio_flash_io3_di
++ spimemio_flash_io3_do spimemio_flash_io3_oeb sram_ro_addr[0] sram_ro_addr[1] sram_ro_addr[2]
++ sram_ro_addr[3] sram_ro_addr[4] sram_ro_addr[5] sram_ro_addr[6] sram_ro_addr[7]
++ sram_ro_clk sram_ro_csb sram_ro_data[0] sram_ro_data[10] sram_ro_data[11] sram_ro_data[12]
++ sram_ro_data[13] sram_ro_data[14] sram_ro_data[15] sram_ro_data[16] sram_ro_data[17]
++ sram_ro_data[18] sram_ro_data[19] sram_ro_data[1] sram_ro_data[20] sram_ro_data[21]
++ sram_ro_data[22] sram_ro_data[23] sram_ro_data[24] sram_ro_data[25] sram_ro_data[26]
++ sram_ro_data[27] sram_ro_data[28] sram_ro_data[29] sram_ro_data[2] sram_ro_data[30]
++ sram_ro_data[31] sram_ro_data[3] sram_ro_data[4] sram_ro_data[5] sram_ro_data[6]
++ sram_ro_data[7] sram_ro_data[8] sram_ro_data[9] trap uart_enabled user_clock usr1_vcc_pwrgood
++ usr1_vdd_pwrgood usr2_vcc_pwrgood usr2_vdd_pwrgood wb_ack_o wb_adr_i[0] wb_adr_i[10]
++ wb_adr_i[11] wb_adr_i[12] wb_adr_i[13] wb_adr_i[14] wb_adr_i[15] wb_adr_i[16] wb_adr_i[17]
++ wb_adr_i[18] wb_adr_i[19] wb_adr_i[1] wb_adr_i[20] wb_adr_i[21] wb_adr_i[22] wb_adr_i[23]
++ wb_adr_i[24] wb_adr_i[25] wb_adr_i[26] wb_adr_i[27] wb_adr_i[28] wb_adr_i[29] wb_adr_i[2]
++ wb_adr_i[30] wb_adr_i[31] wb_adr_i[3] wb_adr_i[4] wb_adr_i[5] wb_adr_i[6] wb_adr_i[7]
++ wb_adr_i[8] wb_adr_i[9] wb_clk_i wb_cyc_i wb_dat_i[0] wb_dat_i[10] wb_dat_i[11]
++ wb_dat_i[12] wb_dat_i[13] wb_dat_i[14] wb_dat_i[15] wb_dat_i[16] wb_dat_i[17] wb_dat_i[18]
++ wb_dat_i[19] wb_dat_i[1] wb_dat_i[20] wb_dat_i[21] wb_dat_i[22] wb_dat_i[23] wb_dat_i[24]
++ wb_dat_i[25] wb_dat_i[26] wb_dat_i[27] wb_dat_i[28] wb_dat_i[29] wb_dat_i[2] wb_dat_i[30]
++ wb_dat_i[31] wb_dat_i[3] wb_dat_i[4] wb_dat_i[5] wb_dat_i[6] wb_dat_i[7] wb_dat_i[8]
++ wb_dat_i[9] wb_dat_o[0] wb_dat_o[10] wb_dat_o[11] wb_dat_o[12] wb_dat_o[13] wb_dat_o[14]
++ wb_dat_o[15] wb_dat_o[16] wb_dat_o[17] wb_dat_o[18] wb_dat_o[19] wb_dat_o[1] wb_dat_o[20]
++ wb_dat_o[21] wb_dat_o[22] wb_dat_o[23] wb_dat_o[24] wb_dat_o[25] wb_dat_o[26] wb_dat_o[27]
++ wb_dat_o[28] wb_dat_o[29] wb_dat_o[2] wb_dat_o[30] wb_dat_o[31] wb_dat_o[3] wb_dat_o[4]
++ wb_dat_o[5] wb_dat_o[6] wb_dat_o[7] wb_dat_o[8] wb_dat_o[9] wb_rstn_i wb_sel_i[0]
++ wb_sel_i[1] wb_sel_i[2] wb_sel_i[3] wb_stb_i wb_we_i
+.ends
+
+.subckt caravan clock flash_clk flash_csb flash_io0 flash_io1 gpio mprj_io[0] mprj_io[10]
++ mprj_io[11] mprj_io[12] mprj_io[13] mprj_io[14] mprj_io[15] mprj_io[16] mprj_io[17]
++ mprj_io[18] mprj_io[19] mprj_io[1] mprj_io[20] mprj_io[21] mprj_io[22] mprj_io[23]
++ mprj_io[24] mprj_io[25] mprj_io[26] mprj_io[27] mprj_io[28] mprj_io[29] mprj_io[2]
++ mprj_io[30] mprj_io[31] mprj_io[32] mprj_io[33] mprj_io[34] mprj_io[35] mprj_io[36]
++ mprj_io[37] mprj_io[3] mprj_io[4] mprj_io[5] mprj_io[6] mprj_io[7] mprj_io[8] mprj_io[9]
++ resetb vccd1 vccd2 vdda vdda1 vdda1_2 vdda2 vddio_2 vssa1 vssa1_2 vssa2 vssd1 vssd2
++ vssio_2 vddio vssio vssa vccd vssd
+Xgpio_control_in_2\[0\] gpio_14_defaults/gpio_defaults[0] gpio_14_defaults/gpio_defaults[10]
++ gpio_14_defaults/gpio_defaults[11] gpio_14_defaults/gpio_defaults[12] gpio_14_defaults/gpio_defaults[1]
++ gpio_14_defaults/gpio_defaults[2] gpio_14_defaults/gpio_defaults[3] gpio_14_defaults/gpio_defaults[4]
++ gpio_14_defaults/gpio_defaults[5] gpio_14_defaults/gpio_defaults[6] gpio_14_defaults/gpio_defaults[7]
++ gpio_14_defaults/gpio_defaults[8] gpio_14_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[25]
++ gpio_control_in_2\[0\]/one housekeeping/mgmt_gpio_in[25] gpio_control_in_2\[0\]/one
++ padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_in[14] padframe/mprj_io_inp_dis[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_oeb[14] padframe/mprj_io_slow_sel[14]
++ padframe/mprj_io_vtrip_sel[14] housekeeping/serial_resetn gpio_control_in_2\[1\]/resetn
++ housekeeping/serial_clock gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[0\]/serial_data_in
++ gpio_control_in_2\[0\]/serial_data_out housekeeping/serial_load gpio_control_in_2\[1\]/serial_load
++ mprj/io_in[14] mprj/io_oeb[14] mprj/io_out[14] gpio_control_in_2\[0\]/vccd gpio_control_in_2\[0\]/vccd1
++ gpio_control_in_2\[0\]/vssd gpio_control_in_2\[0\]/vssd1 gpio_control_in_2\[0\]/zero
++ gpio_control_block
+Xpll pll/VGND pll/VPWR pll/clockp[0] pll/clockp[1] pll/dco pll/div[0] pll/div[1] pll/div[2]
++ pll/div[3] pll/div[4] pll/enable pll/ext_trim[0] pll/ext_trim[10] pll/ext_trim[11]
++ pll/ext_trim[12] pll/ext_trim[13] pll/ext_trim[14] pll/ext_trim[15] pll/ext_trim[16]
++ pll/ext_trim[17] pll/ext_trim[18] pll/ext_trim[19] pll/ext_trim[1] pll/ext_trim[20]
++ pll/ext_trim[21] pll/ext_trim[22] pll/ext_trim[23] pll/ext_trim[24] pll/ext_trim[25]
++ pll/ext_trim[2] pll/ext_trim[3] pll/ext_trim[4] pll/ext_trim[5] pll/ext_trim[6]
++ pll/ext_trim[7] pll/ext_trim[8] pll/ext_trim[9] pll/osc pll/resetb digital_pll
+Xpadframe clock pll/osc por/por_l flash_clk flash_csb flash_io0 padframe/flash_io0_di_core
++ padframe/flash_io0_do_core padframe/flash_io0_ieb_core padframe/flash_io0_oeb_core
++ flash_io1 padframe/flash_io1_di_core padframe/flash_io1_do_core padframe/flash_io1_ieb_core
++ padframe/flash_io1_oeb_core gpio soc/gpio_in_pad soc/gpio_inenb_pad soc/gpio_mode0_pad
++ soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad vccd vdda vddio vddio_2
++ vssa vssd vssio vssio_2 mprj_io[0] padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0]
++ padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2]
++ padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_oeb[0] padframe/mprj_io_out[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ padframe/mprj_io_in[0] mprj/io_in_3v3[0] mprj/gpio_analog[3] mprj/gpio_noesd[3]
++ mprj_io[10] padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10]
++ padframe/mprj_io_dm[30] padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10]
++ padframe/mprj_io_in[10] mprj/io_in_3v3[10] mprj/gpio_analog[4] mprj/gpio_noesd[4]
++ mprj_io[11] padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11]
++ padframe/mprj_io_dm[33] padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11]
++ padframe/mprj_io_ib_mode_sel[11] padframe/mprj_io_inp_dis[11] padframe/mprj_io_oeb[11]
++ padframe/mprj_io_out[11] padframe/mprj_io_slow_sel[11] padframe/mprj_io_vtrip_sel[11]
++ padframe/mprj_io_in[11] mprj/io_in_3v3[11] mprj/gpio_analog[5] mprj/gpio_noesd[5]
++ mprj_io[12] padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12]
++ padframe/mprj_io_dm[36] padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12]
++ padframe/mprj_io_in[12] mprj/io_in_3v3[12] mprj/gpio_analog[6] mprj/gpio_noesd[6]
++ mprj_io[13] padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13]
++ padframe/mprj_io_dm[39] padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13]
++ padframe/mprj_io_ib_mode_sel[13] padframe/mprj_io_inp_dis[13] padframe/mprj_io_oeb[13]
++ padframe/mprj_io_out[13] padframe/mprj_io_slow_sel[13] padframe/mprj_io_vtrip_sel[13]
++ padframe/mprj_io_in[13] mprj/io_in_3v3[13] mprj_io[1] padframe/mprj_io_analog_en[1]
++ padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1] padframe/mprj_io_dm[3]
++ padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1] padframe/mprj_io_ib_mode_sel[1]
++ padframe/mprj_io_inp_dis[1] padframe/mprj_io_oeb[1] padframe/mprj_io_out[1] padframe/mprj_io_slow_sel[1]
++ padframe/mprj_io_vtrip_sel[1] padframe/mprj_io_in[1] mprj/io_in_3v3[1] mprj_io[2]
++ padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2] padframe/mprj_io_analog_sel[2]
++ padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8] padframe/mprj_io_holdover[2]
++ padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_inp_dis[2] padframe/mprj_io_oeb[2]
++ padframe/mprj_io_out[2] padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2]
++ padframe/mprj_io_in[2] mprj/io_in_3v3[2] mprj_io[3] padframe/mprj_io_analog_en[3]
++ padframe/mprj_io_analog_pol[3] padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[10]
++ padframe/mprj_io_dm[11] padframe/mprj_io_dm[9] padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3]
++ padframe/mprj_io_inp_dis[3] padframe/mprj_io_oeb[3] padframe/mprj_io_out[3] padframe/mprj_io_slow_sel[3]
++ padframe/mprj_io_vtrip_sel[3] padframe/mprj_io_in[3] mprj/io_in_3v3[3] mprj_io[4]
++ padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4] padframe/mprj_io_analog_sel[4]
++ padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14] padframe/mprj_io_holdover[4]
++ padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_inp_dis[4] padframe/mprj_io_oeb[4]
++ padframe/mprj_io_out[4] padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4]
++ padframe/mprj_io_in[4] mprj/io_in_3v3[4] mprj_io[5] padframe/mprj_io_analog_en[5]
++ padframe/mprj_io_analog_pol[5] padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15]
++ padframe/mprj_io_dm[16] padframe/mprj_io_dm[17] padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5]
++ padframe/mprj_io_inp_dis[5] padframe/mprj_io_oeb[5] padframe/mprj_io_out[5] padframe/mprj_io_slow_sel[5]
++ padframe/mprj_io_vtrip_sel[5] padframe/mprj_io_in[5] mprj/io_in_3v3[5] mprj_io[6]
++ padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6] padframe/mprj_io_analog_sel[6]
++ padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20] padframe/mprj_io_holdover[6]
++ padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_inp_dis[6] padframe/mprj_io_oeb[6]
++ padframe/mprj_io_out[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ padframe/mprj_io_in[6] mprj/io_in_3v3[6] mprj/gpio_analog[0] mprj/gpio_noesd[0]
++ mprj_io[7] padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7]
++ padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] padframe/mprj_io_holdover[7]
++ padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_inp_dis[7] padframe/mprj_io_oeb[7]
++ padframe/mprj_io_out[7] padframe/mprj_io_slow_sel[7] padframe/mprj_io_vtrip_sel[7]
++ padframe/mprj_io_in[7] mprj/io_in_3v3[7] mprj/gpio_analog[1] mprj/gpio_noesd[1]
++ mprj_io[8] padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_inp_dis[8] padframe/mprj_io_oeb[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ padframe/mprj_io_in[8] mprj/io_in_3v3[8] mprj/gpio_analog[2] mprj/gpio_noesd[2]
++ mprj_io[9] padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9]
++ padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9]
++ padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_inp_dis[9] padframe/mprj_io_oeb[9]
++ padframe/mprj_io_out[9] padframe/mprj_io_slow_sel[9] padframe/mprj_io_vtrip_sel[9]
++ padframe/mprj_io_in[9] mprj/io_in_3v3[9] mprj/gpio_analog[7] mprj/gpio_noesd[7]
++ mprj_io[25] padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14]
++ padframe/mprj_io_in[14] mprj/io_in_3v3[14] mprj/gpio_analog[17] mprj/gpio_noesd[17]
++ mprj_io[35] padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24]
++ padframe/mprj_io_dm[72] padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24]
++ padframe/mprj_io_ib_mode_sel[24] padframe/mprj_io_inp_dis[24] padframe/mprj_io_oeb[24]
++ padframe/mprj_io_out[24] padframe/mprj_io_slow_sel[24] padframe/mprj_io_vtrip_sel[24]
++ padframe/mprj_io_in[24] mprj/io_in_3v3[24] mprj_io[36] padframe/mprj_io_analog_en[25]
++ padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25] padframe/mprj_io_dm[75]
++ padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25] padframe/mprj_io_ib_mode_sel[25]
++ padframe/mprj_io_inp_dis[25] padframe/mprj_io_oeb[25] padframe/mprj_io_out[25] padframe/mprj_io_slow_sel[25]
++ padframe/mprj_io_vtrip_sel[25] padframe/mprj_io_in[25] mprj/io_in_3v3[25] mprj_io[37]
++ padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26]
++ padframe/mprj_io_dm[78] padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26]
++ padframe/mprj_io_ib_mode_sel[26] padframe/mprj_io_inp_dis[26] padframe/mprj_io_oeb[26]
++ padframe/mprj_io_out[26] padframe/mprj_io_slow_sel[26] padframe/mprj_io_vtrip_sel[26]
++ padframe/mprj_io_in[26] mprj/io_in_3v3[26] mprj/gpio_analog[8] mprj/gpio_noesd[8]
++ mprj_io[26] padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15]
++ padframe/mprj_io_dm[45] padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15]
++ padframe/mprj_io_ib_mode_sel[15] padframe/mprj_io_inp_dis[15] padframe/mprj_io_oeb[15]
++ padframe/mprj_io_out[15] padframe/mprj_io_slow_sel[15] padframe/mprj_io_vtrip_sel[15]
++ padframe/mprj_io_in[15] mprj/io_in_3v3[15] mprj/gpio_analog[9] mprj/gpio_noesd[9]
++ mprj_io[27] padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16]
++ padframe/mprj_io_in[16] mprj/io_in_3v3[16] mprj/gpio_analog[10] mprj/gpio_noesd[10]
++ mprj_io[28] padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17]
++ padframe/mprj_io_dm[51] padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17]
++ padframe/mprj_io_ib_mode_sel[17] padframe/mprj_io_inp_dis[17] padframe/mprj_io_oeb[17]
++ padframe/mprj_io_out[17] padframe/mprj_io_slow_sel[17] padframe/mprj_io_vtrip_sel[17]
++ padframe/mprj_io_in[17] mprj/io_in_3v3[17] mprj/gpio_analog[11] mprj/gpio_noesd[11]
++ mprj_io[29] padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18]
++ padframe/mprj_io_in[18] mprj/io_in_3v3[18] mprj/gpio_analog[12] mprj/gpio_noesd[12]
++ mprj_io[30] padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19]
++ padframe/mprj_io_in[19] mprj/io_in_3v3[19] mprj/gpio_analog[13] mprj/gpio_noesd[13]
++ mprj_io[31] padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20]
++ padframe/mprj_io_dm[60] padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20]
++ padframe/mprj_io_ib_mode_sel[20] padframe/mprj_io_inp_dis[20] padframe/mprj_io_oeb[20]
++ padframe/mprj_io_out[20] padframe/mprj_io_slow_sel[20] padframe/mprj_io_vtrip_sel[20]
++ padframe/mprj_io_in[20] mprj/io_in_3v3[20] mprj/gpio_analog[14] mprj/gpio_noesd[14]
++ mprj_io[32] padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21]
++ padframe/mprj_io_in[21] mprj/io_in_3v3[21] mprj/gpio_analog[15] mprj/gpio_noesd[15]
++ mprj_io[33] padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22]
++ padframe/mprj_io_dm[66] padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22]
++ padframe/mprj_io_ib_mode_sel[22] padframe/mprj_io_inp_dis[22] padframe/mprj_io_oeb[22]
++ padframe/mprj_io_out[22] padframe/mprj_io_slow_sel[22] padframe/mprj_io_vtrip_sel[22]
++ padframe/mprj_io_in[22] mprj/io_in_3v3[22] mprj/gpio_analog[16] mprj/gpio_noesd[16]
++ mprj_io[34] padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23]
++ padframe/mprj_io_in[23] mprj/io_in_3v3[23] por/porb_h resetb rstb_level/A padframe/vdda
++ padframe/vssa padframe/vssd mprj/io_analog[0] mprj_io[15] mprj/io_analog[1] mprj_io[16]
++ mprj/io_analog[2] mprj_io[17] mprj/io_analog[3] mprj_io[14] mprj/io_analog[4] mprj/io_clamp_high[0]
++ mprj/io_clamp_low[0] mprj_io[18] vccd1 vdda1 vdda1_2 vssa1 vssa1_2 padframe/vccd1
++ padframe/vdda1 padframe/vssa1 padframe/vssd1 vssd1 mprj/io_analog[7] mprj_io[21]
++ mprj/io_analog[8] mprj_io[22] mprj/io_analog[9] mprj_io[23] mprj/io_analog[10] mprj_io[24]
++ mprj/io_analog[5] mprj/io_clamp_high[1] mprj/io_clamp_low[1] mprj_io[19] mprj/io_analog[6]
++ mprj/io_clamp_high[2] mprj/io_clamp_low[2] mprj_io[20] vccd2 vdda2 vssa2 padframe/vccd
++ padframe/vccd2 padframe/vdda2 padframe/vddio padframe/vssa2 padframe/vssd2 vssd2
++ padframe/vssio padframe/flash_csb_core padframe/flash_clk_ieb_core padframe/flash_clk_oeb_core
++ padframe/flash_clk_core padframe/flash_csb_oeb_core padframe/flash_csb_ieb_core
++ chip_io_alt
+Xgpio_8_defaults gpio_8_defaults/VGND gpio_8_defaults/VPWR gpio_8_defaults/gpio_defaults[0]
++ gpio_8_defaults/gpio_defaults[10] gpio_8_defaults/gpio_defaults[11] gpio_8_defaults/gpio_defaults[12]
++ gpio_8_defaults/gpio_defaults[1] gpio_8_defaults/gpio_defaults[2] gpio_8_defaults/gpio_defaults[3]
++ gpio_8_defaults/gpio_defaults[4] gpio_8_defaults/gpio_defaults[5] gpio_8_defaults/gpio_defaults[6]
++ gpio_8_defaults/gpio_defaults[7] gpio_8_defaults/gpio_defaults[8] gpio_8_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_31_defaults gpio_31_defaults/VGND gpio_31_defaults/VPWR gpio_31_defaults/gpio_defaults[0]
++ gpio_31_defaults/gpio_defaults[10] gpio_31_defaults/gpio_defaults[11] gpio_31_defaults/gpio_defaults[12]
++ gpio_31_defaults/gpio_defaults[1] gpio_31_defaults/gpio_defaults[2] gpio_31_defaults/gpio_defaults[3]
++ gpio_31_defaults/gpio_defaults[4] gpio_31_defaults/gpio_defaults[5] gpio_31_defaults/gpio_defaults[6]
++ gpio_31_defaults/gpio_defaults[7] gpio_31_defaults/gpio_defaults[8] gpio_31_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[3\] gpio_5_defaults/gpio_defaults[0] gpio_5_defaults/gpio_defaults[10]
++ gpio_5_defaults/gpio_defaults[11] gpio_5_defaults/gpio_defaults[12] gpio_5_defaults/gpio_defaults[1]
++ gpio_5_defaults/gpio_defaults[2] gpio_5_defaults/gpio_defaults[3] gpio_5_defaults/gpio_defaults[4]
++ gpio_5_defaults/gpio_defaults[5] gpio_5_defaults/gpio_defaults[6] gpio_5_defaults/gpio_defaults[7]
++ gpio_5_defaults/gpio_defaults[8] gpio_5_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[5]
++ gpio_control_in_1a\[3\]/one housekeeping/mgmt_gpio_in[5] gpio_control_in_1a\[3\]/one
++ padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5] padframe/mprj_io_analog_sel[5]
++ padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17] padframe/mprj_io_holdover[5]
++ padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_in[5] padframe/mprj_io_inp_dis[5]
++ padframe/mprj_io_out[5] padframe/mprj_io_oeb[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_1a\[3\]/serial_data_in gpio_control_in_1a\[4\]/serial_data_in
++ gpio_control_in_2\[5\]/serial_load gpio_control_in_2\[6\]/serial_load mprj/io_in[5]
++ mprj/io_oeb[5] mprj/io_out[5] gpio_control_in_1a\[3\]/vccd gpio_control_in_1a\[3\]/vccd1
++ gpio_control_in_1a\[3\]/vssd gpio_control_in_1a\[3\]/vssd1 gpio_control_in_1a\[3\]/zero
++ gpio_control_block
+Xgpio_control_bidir_2\[0\] gpio_35_defaults/gpio_defaults[0] gpio_35_defaults/gpio_defaults[10]
++ gpio_35_defaults/gpio_defaults[11] gpio_35_defaults/gpio_defaults[12] gpio_35_defaults/gpio_defaults[1]
++ gpio_35_defaults/gpio_defaults[2] gpio_35_defaults/gpio_defaults[3] gpio_35_defaults/gpio_defaults[4]
++ gpio_35_defaults/gpio_defaults[5] gpio_35_defaults/gpio_defaults[6] gpio_35_defaults/gpio_defaults[7]
++ gpio_35_defaults/gpio_defaults[8] gpio_35_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[35]
++ housekeeping/mgmt_gpio_oeb[35] housekeeping/mgmt_gpio_out[35] gpio_control_bidir_2\[0\]/one
++ padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24]
++ padframe/mprj_io_dm[72] padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24]
++ padframe/mprj_io_ib_mode_sel[24] padframe/mprj_io_in[24] padframe/mprj_io_inp_dis[24]
++ padframe/mprj_io_out[24] padframe/mprj_io_oeb[24] padframe/mprj_io_slow_sel[24]
++ padframe/mprj_io_vtrip_sel[24] gpio_control_in_1\[2\]/resetn gpio_control_in_1\[3\]/resetn
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[3\]/serial_clock gpio_control_bidir_2\[0\]/serial_data_in
++ gpio_control_in_2\[9\]/serial_data_in gpio_control_in_1\[2\]/serial_load gpio_control_in_1\[3\]/serial_load
++ mprj/io_in[24] mprj/io_oeb[24] mprj/io_out[24] gpio_control_bidir_2\[0\]/vccd gpio_control_bidir_2\[0\]/vccd1
++ gpio_control_bidir_2\[0\]/vssd gpio_control_bidir_2\[0\]/vssd1 gpio_control_bidir_2\[0\]/zero
++ gpio_control_block
+Xgpio_234_defaults\[1\] gpio_234_defaults\[1\]/VGND gpio_234_defaults\[1\]/VPWR gpio_234_defaults\[1\]/gpio_defaults[0]
++ gpio_234_defaults\[1\]/gpio_defaults[10] gpio_234_defaults\[1\]/gpio_defaults[11]
++ gpio_234_defaults\[1\]/gpio_defaults[12] gpio_234_defaults\[1\]/gpio_defaults[1]
++ gpio_234_defaults\[1\]/gpio_defaults[2] gpio_234_defaults\[1\]/gpio_defaults[3]
++ gpio_234_defaults\[1\]/gpio_defaults[4] gpio_234_defaults\[1\]/gpio_defaults[5]
++ gpio_234_defaults\[1\]/gpio_defaults[6] gpio_234_defaults\[1\]/gpio_defaults[7]
++ gpio_234_defaults\[1\]/gpio_defaults[8] gpio_234_defaults\[1\]/gpio_defaults[9]
++ gpio_defaults_block
+Xsoc soc/VGND soc/VPWR soc/core_clk soc/core_rstn soc/debug_in soc/debug_mode soc/debug_oeb
++ soc/debug_out soc/flash_clk soc/flash_csb soc/flash_io0_di soc/flash_io0_do soc/flash_io0_oeb
++ soc/flash_io1_di soc/flash_io1_do soc/flash_io1_oeb soc/flash_io2_di soc/flash_io2_do
++ soc/flash_io2_oeb soc/flash_io3_di soc/flash_io3_do soc/flash_io3_oeb soc/gpio_in_pad
++ soc/gpio_inenb_pad soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad
++ soc/hk_ack_i soc/hk_dat_i[0] soc/hk_dat_i[10] soc/hk_dat_i[11] soc/hk_dat_i[12]
++ soc/hk_dat_i[13] soc/hk_dat_i[14] soc/hk_dat_i[15] soc/hk_dat_i[16] soc/hk_dat_i[17]
++ soc/hk_dat_i[18] soc/hk_dat_i[19] soc/hk_dat_i[1] soc/hk_dat_i[20] soc/hk_dat_i[21]
++ soc/hk_dat_i[22] soc/hk_dat_i[23] soc/hk_dat_i[24] soc/hk_dat_i[25] soc/hk_dat_i[26]
++ soc/hk_dat_i[27] soc/hk_dat_i[28] soc/hk_dat_i[29] soc/hk_dat_i[2] soc/hk_dat_i[30]
++ soc/hk_dat_i[31] soc/hk_dat_i[3] soc/hk_dat_i[4] soc/hk_dat_i[5] soc/hk_dat_i[6]
++ soc/hk_dat_i[7] soc/hk_dat_i[8] soc/hk_dat_i[9] soc/hk_stb_o soc/irq[0] soc/irq[1]
++ soc/irq[2] soc/irq[3] soc/irq[4] soc/irq[5] soc/la_iena[0] soc/la_iena[100] soc/la_iena[101]
++ soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105] soc/la_iena[106]
++ soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10] soc/la_iena[110]
++ soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114] soc/la_iena[115]
++ soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119] soc/la_iena[11]
++ soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123] soc/la_iena[124]
++ soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12] soc/la_iena[13]
++ soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17] soc/la_iena[18]
++ soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22] soc/la_iena[23]
++ soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27] soc/la_iena[28]
++ soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32] soc/la_iena[33]
++ soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37] soc/la_iena[38]
++ soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42] soc/la_iena[43]
++ soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47] soc/la_iena[48]
++ soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52] soc/la_iena[53]
++ soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57] soc/la_iena[58]
++ soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62] soc/la_iena[63]
++ soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67] soc/la_iena[68]
++ soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72] soc/la_iena[73]
++ soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77] soc/la_iena[78]
++ soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82] soc/la_iena[83]
++ soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87] soc/la_iena[88]
++ soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92] soc/la_iena[93]
++ soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97] soc/la_iena[98]
++ soc/la_iena[99] soc/la_iena[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102] soc/la_oenb[103]
++ soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107] soc/la_oenb[108]
++ soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111] soc/la_oenb[112]
++ soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116] soc/la_oenb[117]
++ soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120] soc/la_oenb[121]
++ soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125] soc/la_oenb[126]
++ soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14] soc/la_oenb[15]
++ soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19] soc/la_oenb[1] soc/la_oenb[20]
++ soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24] soc/la_oenb[25]
++ soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29] soc/la_oenb[2] soc/la_oenb[30]
++ soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34] soc/la_oenb[35]
++ soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39] soc/la_oenb[3] soc/la_oenb[40]
++ soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44] soc/la_oenb[45]
++ soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49] soc/la_oenb[4] soc/la_oenb[50]
++ soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54] soc/la_oenb[55]
++ soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59] soc/la_oenb[5] soc/la_oenb[60]
++ soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64] soc/la_oenb[65]
++ soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69] soc/la_oenb[6] soc/la_oenb[70]
++ soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74] soc/la_oenb[75]
++ soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79] soc/la_oenb[7] soc/la_oenb[80]
++ soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84] soc/la_oenb[85]
++ soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89] soc/la_oenb[8] soc/la_oenb[90]
++ soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94] soc/la_oenb[95]
++ soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99] soc/la_oenb[9] soc/la_output[0]
++ soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103] soc/la_output[104]
++ soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108] soc/la_output[109]
++ soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112] soc/la_output[113]
++ soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117] soc/la_output[118]
++ soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121] soc/la_output[122]
++ soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126] soc/la_output[127]
++ soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15] soc/la_output[16]
++ soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1] soc/la_output[20]
++ soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24] soc/la_output[25]
++ soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29] soc/la_output[2]
++ soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33] soc/la_output[34]
++ soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38] soc/la_output[39]
++ soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42] soc/la_output[43]
++ soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47] soc/la_output[48]
++ soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51] soc/la_output[52]
++ soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56] soc/la_output[57]
++ soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60] soc/la_output[61]
++ soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65] soc/la_output[66]
++ soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6] soc/la_output[70]
++ soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74] soc/la_output[75]
++ soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79] soc/la_output[7]
++ soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83] soc/la_output[84]
++ soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88] soc/la_output[89]
++ soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92] soc/la_output[93]
++ soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97] soc/la_output[98]
++ soc/la_output[99] soc/la_output[9] soc/mprj_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ soc/mprj_cyc_o soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12]
++ soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17]
++ soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21]
++ soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26]
++ soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30]
++ soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6]
++ soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/mprj_stb_o
++ soc/mprj_wb_iena soc/mprj_we_o soc/qspi_enabled soc/ser_rx soc/ser_tx soc/spi_csb
++ soc/spi_enabled soc/spi_sck soc/spi_sdi soc/spi_sdo soc/spi_sdoenb soc/sram_ro_addr[0]
++ soc/sram_ro_addr[1] soc/sram_ro_addr[2] soc/sram_ro_addr[3] soc/sram_ro_addr[4]
++ soc/sram_ro_addr[5] soc/sram_ro_addr[6] soc/sram_ro_addr[7] soc/sram_ro_clk soc/sram_ro_csb
++ soc/sram_ro_data[0] soc/sram_ro_data[10] soc/sram_ro_data[11] soc/sram_ro_data[12]
++ soc/sram_ro_data[13] soc/sram_ro_data[14] soc/sram_ro_data[15] soc/sram_ro_data[16]
++ soc/sram_ro_data[17] soc/sram_ro_data[18] soc/sram_ro_data[19] soc/sram_ro_data[1]
++ soc/sram_ro_data[20] soc/sram_ro_data[21] soc/sram_ro_data[22] soc/sram_ro_data[23]
++ soc/sram_ro_data[24] soc/sram_ro_data[25] soc/sram_ro_data[26] soc/sram_ro_data[27]
++ soc/sram_ro_data[28] soc/sram_ro_data[29] soc/sram_ro_data[2] soc/sram_ro_data[30]
++ soc/sram_ro_data[31] soc/sram_ro_data[3] soc/sram_ro_data[4] soc/sram_ro_data[5]
++ soc/sram_ro_data[6] soc/sram_ro_data[7] soc/sram_ro_data[8] soc/sram_ro_data[9]
++ soc/trap soc/uart_enabled soc/user_irq_ena[0] soc/user_irq_ena[1] soc/user_irq_ena[2]
++ mgmt_core_wrapper
+Xgpio_control_in_2\[9\] gpio_34_defaults/gpio_defaults[0] gpio_34_defaults/gpio_defaults[10]
++ gpio_34_defaults/gpio_defaults[11] gpio_34_defaults/gpio_defaults[12] gpio_34_defaults/gpio_defaults[1]
++ gpio_34_defaults/gpio_defaults[2] gpio_34_defaults/gpio_defaults[3] gpio_34_defaults/gpio_defaults[4]
++ gpio_34_defaults/gpio_defaults[5] gpio_34_defaults/gpio_defaults[6] gpio_34_defaults/gpio_defaults[7]
++ gpio_34_defaults/gpio_defaults[8] gpio_34_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[34]
++ gpio_control_in_2\[9\]/one housekeeping/mgmt_gpio_in[34] gpio_control_in_2\[9\]/one
++ padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_in[23] padframe/mprj_io_inp_dis[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_oeb[23] padframe/mprj_io_slow_sel[23]
++ padframe/mprj_io_vtrip_sel[23] gpio_control_in_2\[9\]/resetn gpio_control_in_1\[2\]/resetn
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[2\]/serial_clock gpio_control_in_2\[9\]/serial_data_in
++ gpio_control_in_2\[8\]/serial_data_in gpio_control_in_2\[9\]/serial_load gpio_control_in_1\[2\]/serial_load
++ mprj/io_in[23] mprj/io_oeb[23] mprj/io_out[23] gpio_control_in_2\[9\]/vccd gpio_control_in_2\[9\]/vccd1
++ gpio_control_in_2\[9\]/vssd gpio_control_in_2\[9\]/vssd1 gpio_control_in_2\[9\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[4\] gpio_12_defaults/gpio_defaults[0] gpio_12_defaults/gpio_defaults[10]
++ gpio_12_defaults/gpio_defaults[11] gpio_12_defaults/gpio_defaults[12] gpio_12_defaults/gpio_defaults[1]
++ gpio_12_defaults/gpio_defaults[2] gpio_12_defaults/gpio_defaults[3] gpio_12_defaults/gpio_defaults[4]
++ gpio_12_defaults/gpio_defaults[5] gpio_12_defaults/gpio_defaults[6] gpio_12_defaults/gpio_defaults[7]
++ gpio_12_defaults/gpio_defaults[8] gpio_12_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[12]
++ gpio_control_in_1\[4\]/one housekeeping/mgmt_gpio_in[12] gpio_control_in_1\[4\]/one
++ padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12]
++ padframe/mprj_io_dm[36] padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_in[12] padframe/mprj_io_inp_dis[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_oeb[12] padframe/mprj_io_slow_sel[12]
++ padframe/mprj_io_vtrip_sel[12] gpio_control_in_1\[4\]/resetn gpio_control_in_1\[5\]/resetn
++ gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[5\]/serial_clock gpio_control_in_1\[4\]/serial_data_in
++ gpio_control_in_1\[5\]/serial_data_in gpio_control_in_1\[4\]/serial_load gpio_control_in_1\[5\]/serial_load
++ mprj/io_in[12] mprj/io_oeb[12] mprj/io_out[12] gpio_control_in_1\[4\]/vccd gpio_control_in_1\[4\]/vccd1
++ gpio_control_in_1\[4\]/vssd gpio_control_in_1\[4\]/vssd1 gpio_control_in_1\[4\]/zero
++ gpio_control_block
+Xpor por/vdd3v3 por/vdd1v8 por/vss por/porb_h por/por_l por/porb_l simple_por
+Xgpio_control_in_1a\[1\] gpio_234_defaults\[1\]/gpio_defaults[0] gpio_234_defaults\[1\]/gpio_defaults[10]
++ gpio_234_defaults\[1\]/gpio_defaults[11] gpio_234_defaults\[1\]/gpio_defaults[12]
++ gpio_234_defaults\[1\]/gpio_defaults[1] gpio_234_defaults\[1\]/gpio_defaults[2]
++ gpio_234_defaults\[1\]/gpio_defaults[3] gpio_234_defaults\[1\]/gpio_defaults[4]
++ gpio_234_defaults\[1\]/gpio_defaults[5] gpio_234_defaults\[1\]/gpio_defaults[6]
++ gpio_234_defaults\[1\]/gpio_defaults[7] gpio_234_defaults\[1\]/gpio_defaults[8]
++ gpio_234_defaults\[1\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[3] gpio_control_in_1a\[1\]/one
++ housekeeping/mgmt_gpio_in[3] gpio_control_in_1a\[1\]/one padframe/mprj_io_analog_en[3]
++ padframe/mprj_io_analog_pol[3] padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[9]
++ padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3]
++ padframe/mprj_io_in[3] padframe/mprj_io_inp_dis[3] padframe/mprj_io_out[3] padframe/mprj_io_oeb[3]
++ padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3] gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[4\]/resetn gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock
++ gpio_control_in_1a\[1\]/serial_data_in gpio_control_in_1a\[2\]/serial_data_in gpio_control_in_2\[3\]/serial_load
++ gpio_control_in_2\[4\]/serial_load mprj/io_in[3] mprj/io_oeb[3] mprj/io_out[3] gpio_control_in_1a\[1\]/vccd
++ gpio_control_in_1a\[1\]/vccd1 gpio_control_in_1a\[1\]/vssd gpio_control_in_1a\[1\]/vssd1
++ gpio_control_in_1a\[1\]/zero gpio_control_block
+Xgpio_control_in_2\[7\] gpio_32_defaults/gpio_defaults[0] gpio_32_defaults/gpio_defaults[10]
++ gpio_32_defaults/gpio_defaults[11] gpio_32_defaults/gpio_defaults[12] gpio_32_defaults/gpio_defaults[1]
++ gpio_32_defaults/gpio_defaults[2] gpio_32_defaults/gpio_defaults[3] gpio_32_defaults/gpio_defaults[4]
++ gpio_32_defaults/gpio_defaults[5] gpio_32_defaults/gpio_defaults[6] gpio_32_defaults/gpio_defaults[7]
++ gpio_32_defaults/gpio_defaults[8] gpio_32_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[32]
++ gpio_control_in_2\[7\]/one housekeeping/mgmt_gpio_in[32] gpio_control_in_2\[7\]/one
++ padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_in[21] padframe/mprj_io_inp_dis[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_oeb[21] padframe/mprj_io_slow_sel[21]
++ padframe/mprj_io_vtrip_sel[21] gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[7\]/serial_data_in
++ gpio_control_in_2\[6\]/serial_data_in gpio_control_in_2\[7\]/serial_load gpio_control_in_2\[8\]/serial_load
++ mprj/io_in[21] mprj/io_oeb[21] mprj/io_out[21] gpio_control_in_2\[7\]/vccd gpio_control_in_2\[7\]/vccd1
++ gpio_control_in_2\[7\]/vssd gpio_control_in_2\[7\]/vssd1 gpio_control_in_2\[7\]/zero
++ gpio_control_block
+Xgpio_34_defaults gpio_34_defaults/VGND gpio_34_defaults/VPWR gpio_34_defaults/gpio_defaults[0]
++ gpio_34_defaults/gpio_defaults[10] gpio_34_defaults/gpio_defaults[11] gpio_34_defaults/gpio_defaults[12]
++ gpio_34_defaults/gpio_defaults[1] gpio_34_defaults/gpio_defaults[2] gpio_34_defaults/gpio_defaults[3]
++ gpio_34_defaults/gpio_defaults[4] gpio_34_defaults/gpio_defaults[5] gpio_34_defaults/gpio_defaults[6]
++ gpio_34_defaults/gpio_defaults[7] gpio_34_defaults/gpio_defaults[8] gpio_34_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xclocking clocking/VGND clocking/VPWR soc/core_clk pll/osc clocking/ext_clk_sel housekeeping/reset
++ pll/clockp[1] pll/clockp[0] pll/resetb soc/core_rstn clocking/sel2[0] clocking/sel2[1]
++ clocking/sel2[2] clocking/sel[0] clocking/sel[1] clocking/sel[2] clocking/user_clk
++ caravel_clocking
+Xgpio_28_defaults gpio_28_defaults/VGND gpio_28_defaults/VPWR gpio_28_defaults/gpio_defaults[0]
++ gpio_28_defaults/gpio_defaults[10] gpio_28_defaults/gpio_defaults[11] gpio_28_defaults/gpio_defaults[12]
++ gpio_28_defaults/gpio_defaults[1] gpio_28_defaults/gpio_defaults[2] gpio_28_defaults/gpio_defaults[3]
++ gpio_28_defaults/gpio_defaults[4] gpio_28_defaults/gpio_defaults[5] gpio_28_defaults/gpio_defaults[6]
++ gpio_28_defaults/gpio_defaults[7] gpio_28_defaults/gpio_defaults[8] gpio_28_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[2\] gpio_10_defaults/gpio_defaults[0] gpio_10_defaults/gpio_defaults[10]
++ gpio_10_defaults/gpio_defaults[11] gpio_10_defaults/gpio_defaults[12] gpio_10_defaults/gpio_defaults[1]
++ gpio_10_defaults/gpio_defaults[2] gpio_10_defaults/gpio_defaults[3] gpio_10_defaults/gpio_defaults[4]
++ gpio_10_defaults/gpio_defaults[5] gpio_10_defaults/gpio_defaults[6] gpio_10_defaults/gpio_defaults[7]
++ gpio_10_defaults/gpio_defaults[8] gpio_10_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[10]
++ gpio_control_in_1\[2\]/one housekeeping/mgmt_gpio_in[10] gpio_control_in_1\[2\]/one
++ padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10]
++ padframe/mprj_io_dm[30] padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_in[10] padframe/mprj_io_inp_dis[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_oeb[10] padframe/mprj_io_slow_sel[10]
++ padframe/mprj_io_vtrip_sel[10] gpio_control_in_1\[2\]/resetn gpio_control_in_1\[3\]/resetn
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_1\[3\]/serial_data_in gpio_control_in_1\[2\]/serial_load gpio_control_in_1\[3\]/serial_load
++ mprj/io_in[10] mprj/io_oeb[10] mprj/io_out[10] gpio_control_in_1\[2\]/vccd gpio_control_in_1\[2\]/vccd1
++ gpio_control_in_1\[2\]/vssd gpio_control_in_1\[2\]/vssd1 gpio_control_in_1\[2\]/zero
++ gpio_control_block
+Xgpio_12_defaults gpio_12_defaults/VGND gpio_12_defaults/VPWR gpio_12_defaults/gpio_defaults[0]
++ gpio_12_defaults/gpio_defaults[10] gpio_12_defaults/gpio_defaults[11] gpio_12_defaults/gpio_defaults[12]
++ gpio_12_defaults/gpio_defaults[1] gpio_12_defaults/gpio_defaults[2] gpio_12_defaults/gpio_defaults[3]
++ gpio_12_defaults/gpio_defaults[4] gpio_12_defaults/gpio_defaults[5] gpio_12_defaults/gpio_defaults[6]
++ gpio_12_defaults/gpio_defaults[7] gpio_12_defaults/gpio_defaults[8] gpio_12_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[0\] gpio_8_defaults/gpio_defaults[0] gpio_8_defaults/gpio_defaults[10]
++ gpio_8_defaults/gpio_defaults[11] gpio_8_defaults/gpio_defaults[12] gpio_8_defaults/gpio_defaults[1]
++ gpio_8_defaults/gpio_defaults[2] gpio_8_defaults/gpio_defaults[3] gpio_8_defaults/gpio_defaults[4]
++ gpio_8_defaults/gpio_defaults[5] gpio_8_defaults/gpio_defaults[6] gpio_8_defaults/gpio_defaults[7]
++ gpio_8_defaults/gpio_defaults[8] gpio_8_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[8]
++ gpio_control_in_1\[0\]/one housekeeping/mgmt_gpio_in[8] gpio_control_in_1\[0\]/one
++ padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_in[8] padframe/mprj_io_inp_dis[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_oeb[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn gpio_control_in_2\[8\]/serial_clock
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[0\]/serial_data_in gpio_control_in_1\[1\]/serial_data_in
++ gpio_control_in_2\[8\]/serial_load gpio_control_in_2\[9\]/serial_load mprj/io_in[8]
++ mprj/io_oeb[8] mprj/io_out[8] gpio_control_in_1\[0\]/vccd gpio_control_in_1\[0\]/vccd1
++ gpio_control_in_1\[0\]/vssd gpio_control_in_1\[0\]/vssd1 gpio_control_in_1\[0\]/zero
++ gpio_control_block
+Xgpio_control_in_2\[5\] gpio_30_defaults/gpio_defaults[0] gpio_30_defaults/gpio_defaults[10]
++ gpio_30_defaults/gpio_defaults[11] gpio_30_defaults/gpio_defaults[12] gpio_30_defaults/gpio_defaults[1]
++ gpio_30_defaults/gpio_defaults[2] gpio_30_defaults/gpio_defaults[3] gpio_30_defaults/gpio_defaults[4]
++ gpio_30_defaults/gpio_defaults[5] gpio_30_defaults/gpio_defaults[6] gpio_30_defaults/gpio_defaults[7]
++ gpio_30_defaults/gpio_defaults[8] gpio_30_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[30]
++ gpio_control_in_2\[5\]/one housekeeping/mgmt_gpio_in[30] gpio_control_in_2\[5\]/one
++ padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_in[19] padframe/mprj_io_inp_dis[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_oeb[19] padframe/mprj_io_slow_sel[19]
++ padframe/mprj_io_vtrip_sel[19] gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[5\]/serial_data_in
++ gpio_control_in_2\[4\]/serial_data_in gpio_control_in_2\[5\]/serial_load gpio_control_in_2\[6\]/serial_load
++ mprj/io_in[19] mprj/io_oeb[19] mprj/io_out[19] gpio_control_in_2\[5\]/vccd gpio_control_in_2\[5\]/vccd1
++ gpio_control_in_2\[5\]/vssd gpio_control_in_2\[5\]/vssd1 gpio_control_in_2\[5\]/zero
++ gpio_control_block
+Xgpio_37_defaults gpio_37_defaults/VGND gpio_37_defaults/VPWR gpio_37_defaults/gpio_defaults[0]
++ gpio_37_defaults/gpio_defaults[10] gpio_37_defaults/gpio_defaults[11] gpio_37_defaults/gpio_defaults[12]
++ gpio_37_defaults/gpio_defaults[1] gpio_37_defaults/gpio_defaults[2] gpio_37_defaults/gpio_defaults[3]
++ gpio_37_defaults/gpio_defaults[4] gpio_37_defaults/gpio_defaults[5] gpio_37_defaults/gpio_defaults[6]
++ gpio_37_defaults/gpio_defaults[7] gpio_37_defaults/gpio_defaults[8] gpio_37_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xuser_id_value user_id_value/mask_rev[0] user_id_value/mask_rev[10] user_id_value/mask_rev[11]
++ user_id_value/mask_rev[12] user_id_value/mask_rev[13] user_id_value/mask_rev[14]
++ user_id_value/mask_rev[15] user_id_value/mask_rev[16] user_id_value/mask_rev[17]
++ user_id_value/mask_rev[18] user_id_value/mask_rev[19] user_id_value/mask_rev[1]
++ user_id_value/mask_rev[20] user_id_value/mask_rev[21] user_id_value/mask_rev[22]
++ user_id_value/mask_rev[23] user_id_value/mask_rev[24] user_id_value/mask_rev[25]
++ user_id_value/mask_rev[26] user_id_value/mask_rev[27] user_id_value/mask_rev[28]
++ user_id_value/mask_rev[29] user_id_value/mask_rev[2] user_id_value/mask_rev[30]
++ user_id_value/mask_rev[31] user_id_value/mask_rev[3] user_id_value/mask_rev[4] user_id_value/mask_rev[5]
++ user_id_value/mask_rev[6] user_id_value/mask_rev[7] user_id_value/mask_rev[8] user_id_value/mask_rev[9]
++ user_id_value/VPWR user_id_value/VGND user_id_programming
+Xgpio_control_in_2\[3\] gpio_28_defaults/gpio_defaults[0] gpio_28_defaults/gpio_defaults[10]
++ gpio_28_defaults/gpio_defaults[11] gpio_28_defaults/gpio_defaults[12] gpio_28_defaults/gpio_defaults[1]
++ gpio_28_defaults/gpio_defaults[2] gpio_28_defaults/gpio_defaults[3] gpio_28_defaults/gpio_defaults[4]
++ gpio_28_defaults/gpio_defaults[5] gpio_28_defaults/gpio_defaults[6] gpio_28_defaults/gpio_defaults[7]
++ gpio_28_defaults/gpio_defaults[8] gpio_28_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[28]
++ gpio_control_in_2\[3\]/one housekeeping/mgmt_gpio_in[28] gpio_control_in_2\[3\]/one
++ padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17]
++ padframe/mprj_io_dm[51] padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17]
++ padframe/mprj_io_ib_mode_sel[17] padframe/mprj_io_in[17] padframe/mprj_io_inp_dis[17]
++ padframe/mprj_io_out[17] padframe/mprj_io_oeb[17] padframe/mprj_io_slow_sel[17]
++ padframe/mprj_io_vtrip_sel[17] gpio_control_in_2\[3\]/resetn gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[3\]/serial_data_in
++ gpio_control_in_2\[2\]/serial_data_in gpio_control_in_2\[3\]/serial_load gpio_control_in_2\[4\]/serial_load
++ mprj/io_in[17] mprj/io_oeb[17] mprj/io_out[17] gpio_control_in_2\[3\]/vccd gpio_control_in_2\[3\]/vccd1
++ gpio_control_in_2\[3\]/vssd gpio_control_in_2\[3\]/vssd1 gpio_control_in_2\[3\]/zero
++ gpio_control_block
+Xgpio_7_defaults gpio_7_defaults/VGND gpio_7_defaults/VPWR gpio_7_defaults/gpio_defaults[0]
++ gpio_7_defaults/gpio_defaults[10] gpio_7_defaults/gpio_defaults[11] gpio_7_defaults/gpio_defaults[12]
++ gpio_7_defaults/gpio_defaults[1] gpio_7_defaults/gpio_defaults[2] gpio_7_defaults/gpio_defaults[3]
++ gpio_7_defaults/gpio_defaults[4] gpio_7_defaults/gpio_defaults[5] gpio_7_defaults/gpio_defaults[6]
++ gpio_7_defaults/gpio_defaults[7] gpio_7_defaults/gpio_defaults[8] gpio_7_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_30_defaults gpio_30_defaults/VGND gpio_30_defaults/VPWR gpio_30_defaults/gpio_defaults[0]
++ gpio_30_defaults/gpio_defaults[10] gpio_30_defaults/gpio_defaults[11] gpio_30_defaults/gpio_defaults[12]
++ gpio_30_defaults/gpio_defaults[1] gpio_30_defaults/gpio_defaults[2] gpio_30_defaults/gpio_defaults[3]
++ gpio_30_defaults/gpio_defaults[4] gpio_30_defaults/gpio_defaults[5] gpio_30_defaults/gpio_defaults[6]
++ gpio_30_defaults/gpio_defaults[7] gpio_30_defaults/gpio_defaults[8] gpio_30_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_1\[0\] gpio_01_defaults\[0\]/gpio_defaults[0] gpio_01_defaults\[0\]/gpio_defaults[10]
++ gpio_01_defaults\[0\]/gpio_defaults[11] gpio_01_defaults\[0\]/gpio_defaults[12]
++ gpio_01_defaults\[0\]/gpio_defaults[1] gpio_01_defaults\[0\]/gpio_defaults[2] gpio_01_defaults\[0\]/gpio_defaults[3]
++ gpio_01_defaults\[0\]/gpio_defaults[4] gpio_01_defaults\[0\]/gpio_defaults[5] gpio_01_defaults\[0\]/gpio_defaults[6]
++ gpio_01_defaults\[0\]/gpio_defaults[7] gpio_01_defaults\[0\]/gpio_defaults[8] gpio_01_defaults\[0\]/gpio_defaults[9]
++ housekeeping/mgmt_gpio_in[0] gpio_control_bidir_1\[0\]/mgmt_gpio_oeb gpio_control_bidir_1\[0\]/mgmt_gpio_out
++ gpio_control_bidir_1\[0\]/one padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0]
++ padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2]
++ padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_in[0]
++ padframe/mprj_io_inp_dis[0] padframe/mprj_io_out[0] padframe/mprj_io_oeb[0] padframe/mprj_io_slow_sel[0]
++ padframe/mprj_io_vtrip_sel[0] housekeeping/serial_resetn gpio_control_in_2\[1\]/resetn
++ housekeeping/serial_clock gpio_control_in_2\[1\]/serial_clock housekeeping/serial_data_1
++ gpio_control_bidir_1\[1\]/serial_data_in housekeeping/serial_load gpio_control_in_2\[1\]/serial_load
++ mprj/io_in[0] mprj/io_oeb[0] mprj/io_out[0] gpio_control_bidir_1\[0\]/vccd gpio_control_bidir_1\[0\]/vccd1
++ gpio_control_bidir_1\[0\]/vssd gpio_control_bidir_1\[0\]/vssd1 gpio_control_bidir_1\[0\]/zero
++ gpio_control_block
+Xgpio_01_defaults\[1\] gpio_01_defaults\[1\]/VGND gpio_01_defaults\[1\]/VPWR gpio_01_defaults\[1\]/gpio_defaults[0]
++ gpio_01_defaults\[1\]/gpio_defaults[10] gpio_01_defaults\[1\]/gpio_defaults[11]
++ gpio_01_defaults\[1\]/gpio_defaults[12] gpio_01_defaults\[1\]/gpio_defaults[1] gpio_01_defaults\[1\]/gpio_defaults[2]
++ gpio_01_defaults\[1\]/gpio_defaults[3] gpio_01_defaults\[1\]/gpio_defaults[4] gpio_01_defaults\[1\]/gpio_defaults[5]
++ gpio_01_defaults\[1\]/gpio_defaults[6] gpio_01_defaults\[1\]/gpio_defaults[7] gpio_01_defaults\[1\]/gpio_defaults[8]
++ gpio_01_defaults\[1\]/gpio_defaults[9] gpio_defaults_block
+Xgpio_control_in_2\[1\] gpio_26_defaults/gpio_defaults[0] gpio_26_defaults/gpio_defaults[10]
++ gpio_26_defaults/gpio_defaults[11] gpio_26_defaults/gpio_defaults[12] gpio_26_defaults/gpio_defaults[1]
++ gpio_26_defaults/gpio_defaults[2] gpio_26_defaults/gpio_defaults[3] gpio_26_defaults/gpio_defaults[4]
++ gpio_26_defaults/gpio_defaults[5] gpio_26_defaults/gpio_defaults[6] gpio_26_defaults/gpio_defaults[7]
++ gpio_26_defaults/gpio_defaults[8] gpio_26_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[26]
++ gpio_control_in_2\[1\]/one housekeeping/mgmt_gpio_in[26] gpio_control_in_2\[1\]/one
++ padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15]
++ padframe/mprj_io_dm[45] padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15]
++ padframe/mprj_io_ib_mode_sel[15] padframe/mprj_io_in[15] padframe/mprj_io_inp_dis[15]
++ padframe/mprj_io_out[15] padframe/mprj_io_oeb[15] padframe/mprj_io_slow_sel[15]
++ padframe/mprj_io_vtrip_sel[15] gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[1\]/serial_data_in
++ gpio_control_in_2\[0\]/serial_data_in gpio_control_in_2\[1\]/serial_load gpio_control_in_2\[2\]/serial_load
++ mprj/io_in[15] mprj/io_oeb[15] mprj/io_out[15] gpio_control_in_2\[1\]/vccd gpio_control_in_2\[1\]/vccd1
++ gpio_control_in_2\[1\]/vssd gpio_control_in_2\[1\]/vssd1 gpio_control_in_2\[1\]/zero
++ gpio_control_block
+Xgpio_33_defaults gpio_33_defaults/VGND gpio_33_defaults/VPWR gpio_33_defaults/gpio_defaults[0]
++ gpio_33_defaults/gpio_defaults[10] gpio_33_defaults/gpio_defaults[11] gpio_33_defaults/gpio_defaults[12]
++ gpio_33_defaults/gpio_defaults[1] gpio_33_defaults/gpio_defaults[2] gpio_33_defaults/gpio_defaults[3]
++ gpio_33_defaults/gpio_defaults[4] gpio_33_defaults/gpio_defaults[5] gpio_33_defaults/gpio_defaults[6]
++ gpio_33_defaults/gpio_defaults[7] gpio_33_defaults/gpio_defaults[8] gpio_33_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[4\] gpio_6_defaults/gpio_defaults[0] gpio_6_defaults/gpio_defaults[10]
++ gpio_6_defaults/gpio_defaults[11] gpio_6_defaults/gpio_defaults[12] gpio_6_defaults/gpio_defaults[1]
++ gpio_6_defaults/gpio_defaults[2] gpio_6_defaults/gpio_defaults[3] gpio_6_defaults/gpio_defaults[4]
++ gpio_6_defaults/gpio_defaults[5] gpio_6_defaults/gpio_defaults[6] gpio_6_defaults/gpio_defaults[7]
++ gpio_6_defaults/gpio_defaults[8] gpio_6_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[6]
++ gpio_control_in_1a\[4\]/one housekeeping/mgmt_gpio_in[6] gpio_control_in_1a\[4\]/one
++ padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6] padframe/mprj_io_analog_sel[6]
++ padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20] padframe/mprj_io_holdover[6]
++ padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_in[6] padframe/mprj_io_inp_dis[6]
++ padframe/mprj_io_out[6] padframe/mprj_io_oeb[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn gpio_control_in_2\[6\]/serial_clock
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_1a\[4\]/serial_data_in gpio_control_in_1a\[5\]/serial_data_in
++ gpio_control_in_2\[6\]/serial_load gpio_control_in_2\[7\]/serial_load mprj/io_in[6]
++ mprj/io_oeb[6] mprj/io_out[6] gpio_control_in_1a\[4\]/vccd gpio_control_in_1a\[4\]/vccd1
++ gpio_control_in_1a\[4\]/vssd gpio_control_in_1a\[4\]/vssd1 gpio_control_in_1a\[4\]/zero
++ gpio_control_block
+Xgpio_234_defaults\[2\] gpio_234_defaults\[2\]/VGND gpio_234_defaults\[2\]/VPWR gpio_234_defaults\[2\]/gpio_defaults[0]
++ gpio_234_defaults\[2\]/gpio_defaults[10] gpio_234_defaults\[2\]/gpio_defaults[11]
++ gpio_234_defaults\[2\]/gpio_defaults[12] gpio_234_defaults\[2\]/gpio_defaults[1]
++ gpio_234_defaults\[2\]/gpio_defaults[2] gpio_234_defaults\[2\]/gpio_defaults[3]
++ gpio_234_defaults\[2\]/gpio_defaults[4] gpio_234_defaults\[2\]/gpio_defaults[5]
++ gpio_234_defaults\[2\]/gpio_defaults[6] gpio_234_defaults\[2\]/gpio_defaults[7]
++ gpio_234_defaults\[2\]/gpio_defaults[8] gpio_234_defaults\[2\]/gpio_defaults[9]
++ gpio_defaults_block
+Xmgmt_buffers soc/core_clk clocking/user_clk soc/core_rstn mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102]
++ mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106]
++ mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10]
++ mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113]
++ mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117]
++ mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120]
++ mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124]
++ mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12]
++ mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16]
++ mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1]
++ mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23]
++ mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27]
++ mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30]
++ mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34]
++ mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38]
++ mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41]
++ mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45]
++ mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49]
++ mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52]
++ mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56]
++ mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5]
++ mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63]
++ mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67]
++ mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70]
++ mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74]
++ mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78]
++ mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81]
++ mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85]
++ mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89]
++ mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92]
++ mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96]
++ mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9]
++ soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103]
++ soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108]
++ soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112]
++ soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117]
++ soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121]
++ soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126]
++ soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15]
++ soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1]
++ soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24]
++ soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29]
++ soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33]
++ soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38]
++ soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42]
++ soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47]
++ soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51]
++ soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56]
++ soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60]
++ soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65]
++ soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6]
++ soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74]
++ soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79]
++ soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83]
++ soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88]
++ soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92]
++ soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97]
++ soc/la_output[98] soc/la_output[99] soc/la_output[9] soc/la_iena[0] soc/la_iena[100]
++ soc/la_iena[101] soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105]
++ soc/la_iena[106] soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10]
++ soc/la_iena[110] soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114]
++ soc/la_iena[115] soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119]
++ soc/la_iena[11] soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123]
++ soc/la_iena[124] soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12]
++ soc/la_iena[13] soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17]
++ soc/la_iena[18] soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22]
++ soc/la_iena[23] soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27]
++ soc/la_iena[28] soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32]
++ soc/la_iena[33] soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37]
++ soc/la_iena[38] soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42]
++ soc/la_iena[43] soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47]
++ soc/la_iena[48] soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52]
++ soc/la_iena[53] soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57]
++ soc/la_iena[58] soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62]
++ soc/la_iena[63] soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67]
++ soc/la_iena[68] soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72]
++ soc/la_iena[73] soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77]
++ soc/la_iena[78] soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82]
++ soc/la_iena[83] soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87]
++ soc/la_iena[88] soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92]
++ soc/la_iena[93] soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97]
++ soc/la_iena[98] soc/la_iena[99] soc/la_iena[9] mprj/la_oenb[0] mprj/la_oenb[100]
++ mprj/la_oenb[101] mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105]
++ mprj/la_oenb[106] mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10]
++ mprj/la_oenb[110] mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114]
++ mprj/la_oenb[115] mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119]
++ mprj/la_oenb[11] mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123]
++ mprj/la_oenb[124] mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12]
++ mprj/la_oenb[13] mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17]
++ mprj/la_oenb[18] mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21]
++ mprj/la_oenb[22] mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26]
++ mprj/la_oenb[27] mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30]
++ mprj/la_oenb[31] mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35]
++ mprj/la_oenb[36] mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3]
++ mprj/la_oenb[40] mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44]
++ mprj/la_oenb[45] mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49]
++ mprj/la_oenb[4] mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53]
++ mprj/la_oenb[54] mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58]
++ mprj/la_oenb[59] mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62]
++ mprj/la_oenb[63] mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67]
++ mprj/la_oenb[68] mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71]
++ mprj/la_oenb[72] mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76]
++ mprj/la_oenb[77] mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80]
++ mprj/la_oenb[81] mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85]
++ mprj/la_oenb[86] mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8]
++ mprj/la_oenb[90] mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94]
++ mprj/la_oenb[95] mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99]
++ mprj/la_oenb[9] soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102]
++ soc/la_oenb[103] soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107]
++ soc/la_oenb[108] soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111]
++ soc/la_oenb[112] soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116]
++ soc/la_oenb[117] soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120]
++ soc/la_oenb[121] soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125]
++ soc/la_oenb[126] soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14]
++ soc/la_oenb[15] soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19]
++ soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24]
++ soc/la_oenb[25] soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29]
++ soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34]
++ soc/la_oenb[35] soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39]
++ soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44]
++ soc/la_oenb[45] soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49]
++ soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54]
++ soc/la_oenb[55] soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59]
++ soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64]
++ soc/la_oenb[65] soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69]
++ soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74]
++ soc/la_oenb[75] soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79]
++ soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84]
++ soc/la_oenb[85] soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89]
++ soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94]
++ soc/la_oenb[95] soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99]
++ soc/la_oenb[9] soc/mprj_ack_i mprj/wbs_ack_o soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13]
++ mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18]
++ mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22]
++ mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27]
++ mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31]
++ mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7]
++ mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] soc/mprj_cyc_o mprj/wbs_cyc_i soc/mprj_dat_i[0]
++ soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12] soc/mprj_dat_i[13] soc/mprj_dat_i[14]
++ soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17] soc/mprj_dat_i[18] soc/mprj_dat_i[19]
++ soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21] soc/mprj_dat_i[22] soc/mprj_dat_i[23]
++ soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26] soc/mprj_dat_i[27] soc/mprj_dat_i[28]
++ soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30] soc/mprj_dat_i[31] soc/mprj_dat_i[3]
++ soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6] soc/mprj_dat_i[7] soc/mprj_dat_i[8]
++ soc/mprj_dat_i[9] mprj/wbs_dat_o[0] mprj/wbs_dat_o[10] mprj/wbs_dat_o[11] mprj/wbs_dat_o[12]
++ mprj/wbs_dat_o[13] mprj/wbs_dat_o[14] mprj/wbs_dat_o[15] mprj/wbs_dat_o[16] mprj/wbs_dat_o[17]
++ mprj/wbs_dat_o[18] mprj/wbs_dat_o[19] mprj/wbs_dat_o[1] mprj/wbs_dat_o[20] mprj/wbs_dat_o[21]
++ mprj/wbs_dat_o[22] mprj/wbs_dat_o[23] mprj/wbs_dat_o[24] mprj/wbs_dat_o[25] mprj/wbs_dat_o[26]
++ mprj/wbs_dat_o[27] mprj/wbs_dat_o[28] mprj/wbs_dat_o[29] mprj/wbs_dat_o[2] mprj/wbs_dat_o[30]
++ mprj/wbs_dat_o[31] mprj/wbs_dat_o[3] mprj/wbs_dat_o[4] mprj/wbs_dat_o[5] mprj/wbs_dat_o[6]
++ mprj/wbs_dat_o[7] mprj/wbs_dat_o[8] mprj/wbs_dat_o[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] mgmt_buffers/mprj_iena_wb soc/mprj_sel_o[0]
++ soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] mprj/wbs_sel_i[0] mprj/wbs_sel_i[1]
++ mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] soc/mprj_stb_o mprj/wbs_stb_i soc/mprj_we_o
++ mprj/wbs_we_i housekeeping/usr1_vcc_pwrgood housekeeping/usr1_vdd_pwrgood housekeeping/usr2_vcc_pwrgood
++ housekeeping/usr2_vdd_pwrgood mprj/wb_clk_i mprj/user_clock2 soc/irq[0] soc/irq[1]
++ soc/irq[2] mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2] mgmt_buffers/user_irq_ena[0]
++ mgmt_buffers/user_irq_ena[1] mgmt_buffers/user_irq_ena[2] mprj/wb_rst_i mgmt_buffers/vccd
++ mgmt_buffers/vccd1 mgmt_buffers/vccd2 mgmt_buffers/vdda1 mgmt_buffers/vdda2 mgmt_buffers/vssa1
++ mgmt_buffers/vssa2 mgmt_buffers/vssd mgmt_buffers/vssd1 mgmt_buffers/vssd2 mgmt_protect
+Xrstb_level rstb_level/A pll/resetb rstb_level/VPWR rstb_level/VGND rstb_level/LVPWR
++ rstb_level/LVGND xres_buf
+Xgpio_27_defaults gpio_27_defaults/VGND gpio_27_defaults/VPWR gpio_27_defaults/gpio_defaults[0]
++ gpio_27_defaults/gpio_defaults[10] gpio_27_defaults/gpio_defaults[11] gpio_27_defaults/gpio_defaults[12]
++ gpio_27_defaults/gpio_defaults[1] gpio_27_defaults/gpio_defaults[2] gpio_27_defaults/gpio_defaults[3]
++ gpio_27_defaults/gpio_defaults[4] gpio_27_defaults/gpio_defaults[5] gpio_27_defaults/gpio_defaults[6]
++ gpio_27_defaults/gpio_defaults[7] gpio_27_defaults/gpio_defaults[8] gpio_27_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_2\[1\] gpio_36_defaults/gpio_defaults[0] gpio_36_defaults/gpio_defaults[10]
++ gpio_36_defaults/gpio_defaults[11] gpio_36_defaults/gpio_defaults[12] gpio_36_defaults/gpio_defaults[1]
++ gpio_36_defaults/gpio_defaults[2] gpio_36_defaults/gpio_defaults[3] gpio_36_defaults/gpio_defaults[4]
++ gpio_36_defaults/gpio_defaults[5] gpio_36_defaults/gpio_defaults[6] gpio_36_defaults/gpio_defaults[7]
++ gpio_36_defaults/gpio_defaults[8] gpio_36_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[36]
++ housekeeping/mgmt_gpio_oeb[36] housekeeping/mgmt_gpio_out[36] gpio_control_bidir_2\[1\]/one
++ padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25]
++ padframe/mprj_io_dm[75] padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25]
++ padframe/mprj_io_ib_mode_sel[25] padframe/mprj_io_in[25] padframe/mprj_io_inp_dis[25]
++ padframe/mprj_io_out[25] padframe/mprj_io_oeb[25] padframe/mprj_io_slow_sel[25]
++ padframe/mprj_io_vtrip_sel[25] gpio_control_in_1\[3\]/resetn gpio_control_in_1\[4\]/resetn
++ gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[4\]/serial_clock gpio_control_bidir_2\[1\]/serial_data_in
++ gpio_control_bidir_2\[0\]/serial_data_in gpio_control_in_1\[3\]/serial_load gpio_control_in_1\[4\]/serial_load
++ mprj/io_in[25] mprj/io_oeb[25] mprj/io_out[25] gpio_control_bidir_2\[1\]/vccd gpio_control_bidir_2\[1\]/vccd1
++ gpio_control_bidir_2\[1\]/vssd gpio_control_bidir_2\[1\]/vssd1 gpio_control_bidir_2\[1\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[5\] gpio_13_defaults/gpio_defaults[0] gpio_13_defaults/gpio_defaults[10]
++ gpio_13_defaults/gpio_defaults[11] gpio_13_defaults/gpio_defaults[12] gpio_13_defaults/gpio_defaults[1]
++ gpio_13_defaults/gpio_defaults[2] gpio_13_defaults/gpio_defaults[3] gpio_13_defaults/gpio_defaults[4]
++ gpio_13_defaults/gpio_defaults[5] gpio_13_defaults/gpio_defaults[6] gpio_13_defaults/gpio_defaults[7]
++ gpio_13_defaults/gpio_defaults[8] gpio_13_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[13]
++ gpio_control_in_1\[5\]/one housekeeping/mgmt_gpio_in[13] gpio_control_in_1\[5\]/one
++ padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13]
++ padframe/mprj_io_dm[39] padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13]
++ padframe/mprj_io_ib_mode_sel[13] padframe/mprj_io_in[13] padframe/mprj_io_inp_dis[13]
++ padframe/mprj_io_out[13] padframe/mprj_io_oeb[13] padframe/mprj_io_slow_sel[13]
++ padframe/mprj_io_vtrip_sel[13] gpio_control_in_1\[5\]/resetn gpio_control_in_1\[5\]/resetn_out
++ gpio_control_in_1\[5\]/serial_clock gpio_control_in_1\[5\]/serial_clock_out gpio_control_in_1\[5\]/serial_data_in
++ gpio_control_in_1\[5\]/serial_data_out gpio_control_in_1\[5\]/serial_load gpio_control_in_1\[5\]/serial_load_out
++ mprj/io_in[13] mprj/io_oeb[13] mprj/io_out[13] gpio_control_in_1\[5\]/vccd gpio_control_in_1\[5\]/vccd1
++ gpio_control_in_1\[5\]/vssd gpio_control_in_1\[5\]/vssd1 gpio_control_in_1\[5\]/zero
++ gpio_control_block
+Xgpio_11_defaults gpio_11_defaults/VGND gpio_11_defaults/VPWR gpio_11_defaults/gpio_defaults[0]
++ gpio_11_defaults/gpio_defaults[10] gpio_11_defaults/gpio_defaults[11] gpio_11_defaults/gpio_defaults[12]
++ gpio_11_defaults/gpio_defaults[1] gpio_11_defaults/gpio_defaults[2] gpio_11_defaults/gpio_defaults[3]
++ gpio_11_defaults/gpio_defaults[4] gpio_11_defaults/gpio_defaults[5] gpio_11_defaults/gpio_defaults[6]
++ gpio_11_defaults/gpio_defaults[7] gpio_11_defaults/gpio_defaults[8] gpio_11_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[2\] gpio_234_defaults\[2\]/gpio_defaults[0] gpio_234_defaults\[2\]/gpio_defaults[10]
++ gpio_234_defaults\[2\]/gpio_defaults[11] gpio_234_defaults\[2\]/gpio_defaults[12]
++ gpio_234_defaults\[2\]/gpio_defaults[1] gpio_234_defaults\[2\]/gpio_defaults[2]
++ gpio_234_defaults\[2\]/gpio_defaults[3] gpio_234_defaults\[2\]/gpio_defaults[4]
++ gpio_234_defaults\[2\]/gpio_defaults[5] gpio_234_defaults\[2\]/gpio_defaults[6]
++ gpio_234_defaults\[2\]/gpio_defaults[7] gpio_234_defaults\[2\]/gpio_defaults[8]
++ gpio_234_defaults\[2\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[4] gpio_control_in_1a\[2\]/one
++ housekeeping/mgmt_gpio_in[4] gpio_control_in_1a\[2\]/one padframe/mprj_io_analog_en[4]
++ padframe/mprj_io_analog_pol[4] padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12]
++ padframe/mprj_io_dm[13] padframe/mprj_io_dm[14] padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4]
++ padframe/mprj_io_in[4] padframe/mprj_io_inp_dis[4] padframe/mprj_io_out[4] padframe/mprj_io_oeb[4]
++ padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4] gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_1a\[2\]/serial_data_in gpio_control_in_1a\[3\]/serial_data_in gpio_control_in_2\[4\]/serial_load
++ gpio_control_in_2\[5\]/serial_load mprj/io_in[4] mprj/io_oeb[4] mprj/io_out[4] gpio_control_in_1a\[2\]/vccd
++ gpio_control_in_1a\[2\]/vccd1 gpio_control_in_1a\[2\]/vssd gpio_control_in_1a\[2\]/vssd1
++ gpio_control_in_1a\[2\]/zero gpio_control_block
+Xgpio_234_defaults\[0\] gpio_234_defaults\[0\]/VGND gpio_234_defaults\[0\]/VPWR gpio_234_defaults\[0\]/gpio_defaults[0]
++ gpio_234_defaults\[0\]/gpio_defaults[10] gpio_234_defaults\[0\]/gpio_defaults[11]
++ gpio_234_defaults\[0\]/gpio_defaults[12] gpio_234_defaults\[0\]/gpio_defaults[1]
++ gpio_234_defaults\[0\]/gpio_defaults[2] gpio_234_defaults\[0\]/gpio_defaults[3]
++ gpio_234_defaults\[0\]/gpio_defaults[4] gpio_234_defaults\[0\]/gpio_defaults[5]
++ gpio_234_defaults\[0\]/gpio_defaults[6] gpio_234_defaults\[0\]/gpio_defaults[7]
++ gpio_234_defaults\[0\]/gpio_defaults[8] gpio_234_defaults\[0\]/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_36_defaults gpio_36_defaults/VGND gpio_36_defaults/VPWR gpio_36_defaults/gpio_defaults[0]
++ gpio_36_defaults/gpio_defaults[10] gpio_36_defaults/gpio_defaults[11] gpio_36_defaults/gpio_defaults[12]
++ gpio_36_defaults/gpio_defaults[1] gpio_36_defaults/gpio_defaults[2] gpio_36_defaults/gpio_defaults[3]
++ gpio_36_defaults/gpio_defaults[4] gpio_36_defaults/gpio_defaults[5] gpio_36_defaults/gpio_defaults[6]
++ gpio_36_defaults/gpio_defaults[7] gpio_36_defaults/gpio_defaults[8] gpio_36_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[8\] gpio_33_defaults/gpio_defaults[0] gpio_33_defaults/gpio_defaults[10]
++ gpio_33_defaults/gpio_defaults[11] gpio_33_defaults/gpio_defaults[12] gpio_33_defaults/gpio_defaults[1]
++ gpio_33_defaults/gpio_defaults[2] gpio_33_defaults/gpio_defaults[3] gpio_33_defaults/gpio_defaults[4]
++ gpio_33_defaults/gpio_defaults[5] gpio_33_defaults/gpio_defaults[6] gpio_33_defaults/gpio_defaults[7]
++ gpio_33_defaults/gpio_defaults[8] gpio_33_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[33]
++ gpio_control_in_2\[8\]/one housekeeping/mgmt_gpio_in[33] gpio_control_in_2\[8\]/one
++ padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22]
++ padframe/mprj_io_dm[66] padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22]
++ padframe/mprj_io_ib_mode_sel[22] padframe/mprj_io_in[22] padframe/mprj_io_inp_dis[22]
++ padframe/mprj_io_out[22] padframe/mprj_io_oeb[22] padframe/mprj_io_slow_sel[22]
++ padframe/mprj_io_vtrip_sel[22] gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock gpio_control_in_2\[8\]/serial_data_in
++ gpio_control_in_2\[7\]/serial_data_in gpio_control_in_2\[8\]/serial_load gpio_control_in_2\[9\]/serial_load
++ mprj/io_in[22] mprj/io_oeb[22] mprj/io_out[22] gpio_control_in_2\[8\]/vccd gpio_control_in_2\[8\]/vccd1
++ gpio_control_in_2\[8\]/vssd gpio_control_in_2\[8\]/vssd1 gpio_control_in_2\[8\]/zero
++ gpio_control_block
+Xgpio_14_defaults gpio_14_defaults/VGND gpio_14_defaults/VPWR gpio_14_defaults/gpio_defaults[0]
++ gpio_14_defaults/gpio_defaults[10] gpio_14_defaults/gpio_defaults[11] gpio_14_defaults/gpio_defaults[12]
++ gpio_14_defaults/gpio_defaults[1] gpio_14_defaults/gpio_defaults[2] gpio_14_defaults/gpio_defaults[3]
++ gpio_14_defaults/gpio_defaults[4] gpio_14_defaults/gpio_defaults[5] gpio_14_defaults/gpio_defaults[6]
++ gpio_14_defaults/gpio_defaults[7] gpio_14_defaults/gpio_defaults[8] gpio_14_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[3\] gpio_11_defaults/gpio_defaults[0] gpio_11_defaults/gpio_defaults[10]
++ gpio_11_defaults/gpio_defaults[11] gpio_11_defaults/gpio_defaults[12] gpio_11_defaults/gpio_defaults[1]
++ gpio_11_defaults/gpio_defaults[2] gpio_11_defaults/gpio_defaults[3] gpio_11_defaults/gpio_defaults[4]
++ gpio_11_defaults/gpio_defaults[5] gpio_11_defaults/gpio_defaults[6] gpio_11_defaults/gpio_defaults[7]
++ gpio_11_defaults/gpio_defaults[8] gpio_11_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[11]
++ gpio_control_in_1\[3\]/one housekeeping/mgmt_gpio_in[11] gpio_control_in_1\[3\]/one
++ padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11]
++ padframe/mprj_io_dm[33] padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11]
++ padframe/mprj_io_ib_mode_sel[11] padframe/mprj_io_in[11] padframe/mprj_io_inp_dis[11]
++ padframe/mprj_io_out[11] padframe/mprj_io_oeb[11] padframe/mprj_io_slow_sel[11]
++ padframe/mprj_io_vtrip_sel[11] gpio_control_in_1\[3\]/resetn gpio_control_in_1\[4\]/resetn
++ gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[3\]/serial_data_in
++ gpio_control_in_1\[4\]/serial_data_in gpio_control_in_1\[3\]/serial_load gpio_control_in_1\[4\]/serial_load
++ mprj/io_in[11] mprj/io_oeb[11] mprj/io_out[11] gpio_control_in_1\[3\]/vccd gpio_control_in_1\[3\]/vccd1
++ gpio_control_in_1\[3\]/vssd gpio_control_in_1\[3\]/vssd1 gpio_control_in_1\[3\]/zero
++ gpio_control_block
+Xgpio_6_defaults gpio_6_defaults/VGND gpio_6_defaults/VPWR gpio_6_defaults/gpio_defaults[0]
++ gpio_6_defaults/gpio_defaults[10] gpio_6_defaults/gpio_defaults[11] gpio_6_defaults/gpio_defaults[12]
++ gpio_6_defaults/gpio_defaults[1] gpio_6_defaults/gpio_defaults[2] gpio_6_defaults/gpio_defaults[3]
++ gpio_6_defaults/gpio_defaults[4] gpio_6_defaults/gpio_defaults[5] gpio_6_defaults/gpio_defaults[6]
++ gpio_6_defaults/gpio_defaults[7] gpio_6_defaults/gpio_defaults[8] gpio_6_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[0\] gpio_234_defaults\[0\]/gpio_defaults[0] gpio_234_defaults\[0\]/gpio_defaults[10]
++ gpio_234_defaults\[0\]/gpio_defaults[11] gpio_234_defaults\[0\]/gpio_defaults[12]
++ gpio_234_defaults\[0\]/gpio_defaults[1] gpio_234_defaults\[0\]/gpio_defaults[2]
++ gpio_234_defaults\[0\]/gpio_defaults[3] gpio_234_defaults\[0\]/gpio_defaults[4]
++ gpio_234_defaults\[0\]/gpio_defaults[5] gpio_234_defaults\[0\]/gpio_defaults[6]
++ gpio_234_defaults\[0\]/gpio_defaults[7] gpio_234_defaults\[0\]/gpio_defaults[8]
++ gpio_234_defaults\[0\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[2] gpio_control_in_1a\[0\]/one
++ housekeeping/mgmt_gpio_in[2] gpio_control_in_1a\[0\]/one padframe/mprj_io_analog_en[2]
++ padframe/mprj_io_analog_pol[2] padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6]
++ padframe/mprj_io_dm[7] padframe/mprj_io_dm[8] padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2]
++ padframe/mprj_io_in[2] padframe/mprj_io_inp_dis[2] padframe/mprj_io_out[2] padframe/mprj_io_oeb[2]
++ padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2] gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[3\]/resetn gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock
++ gpio_control_in_1a\[0\]/serial_data_in gpio_control_in_1a\[1\]/serial_data_in gpio_control_in_2\[2\]/serial_load
++ gpio_control_in_2\[3\]/serial_load mprj/io_in[2] mprj/io_oeb[2] mprj/io_out[2] gpio_control_in_1a\[0\]/vccd
++ gpio_control_in_1a\[0\]/vccd1 gpio_control_in_1a\[0\]/vssd gpio_control_in_1a\[0\]/vssd1
++ gpio_control_in_1a\[0\]/zero gpio_control_block
+Xgpio_control_in_2\[6\] gpio_31_defaults/gpio_defaults[0] gpio_31_defaults/gpio_defaults[10]
++ gpio_31_defaults/gpio_defaults[11] gpio_31_defaults/gpio_defaults[12] gpio_31_defaults/gpio_defaults[1]
++ gpio_31_defaults/gpio_defaults[2] gpio_31_defaults/gpio_defaults[3] gpio_31_defaults/gpio_defaults[4]
++ gpio_31_defaults/gpio_defaults[5] gpio_31_defaults/gpio_defaults[6] gpio_31_defaults/gpio_defaults[7]
++ gpio_31_defaults/gpio_defaults[8] gpio_31_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[31]
++ gpio_control_in_2\[6\]/one housekeeping/mgmt_gpio_in[31] gpio_control_in_2\[6\]/one
++ padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20]
++ padframe/mprj_io_dm[60] padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20]
++ padframe/mprj_io_ib_mode_sel[20] padframe/mprj_io_in[20] padframe/mprj_io_inp_dis[20]
++ padframe/mprj_io_out[20] padframe/mprj_io_oeb[20] padframe/mprj_io_slow_sel[20]
++ padframe/mprj_io_vtrip_sel[20] gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[6\]/serial_data_in
++ gpio_control_in_2\[5\]/serial_data_in gpio_control_in_2\[6\]/serial_load gpio_control_in_2\[7\]/serial_load
++ mprj/io_in[20] mprj/io_oeb[20] mprj/io_out[20] gpio_control_in_2\[6\]/vccd gpio_control_in_2\[6\]/vccd1
++ gpio_control_in_2\[6\]/vssd gpio_control_in_2\[6\]/vssd1 gpio_control_in_2\[6\]/zero
++ gpio_control_block
+Xgpio_9_defaults gpio_9_defaults/VGND gpio_9_defaults/VPWR gpio_9_defaults/gpio_defaults[0]
++ gpio_9_defaults/gpio_defaults[10] gpio_9_defaults/gpio_defaults[11] gpio_9_defaults/gpio_defaults[12]
++ gpio_9_defaults/gpio_defaults[1] gpio_9_defaults/gpio_defaults[2] gpio_9_defaults/gpio_defaults[3]
++ gpio_9_defaults/gpio_defaults[4] gpio_9_defaults/gpio_defaults[5] gpio_9_defaults/gpio_defaults[6]
++ gpio_9_defaults/gpio_defaults[7] gpio_9_defaults/gpio_defaults[8] gpio_9_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[1\] gpio_9_defaults/gpio_defaults[0] gpio_9_defaults/gpio_defaults[10]
++ gpio_9_defaults/gpio_defaults[11] gpio_9_defaults/gpio_defaults[12] gpio_9_defaults/gpio_defaults[1]
++ gpio_9_defaults/gpio_defaults[2] gpio_9_defaults/gpio_defaults[3] gpio_9_defaults/gpio_defaults[4]
++ gpio_9_defaults/gpio_defaults[5] gpio_9_defaults/gpio_defaults[6] gpio_9_defaults/gpio_defaults[7]
++ gpio_9_defaults/gpio_defaults[8] gpio_9_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[9]
++ gpio_control_in_1\[1\]/one housekeeping/mgmt_gpio_in[9] gpio_control_in_1\[1\]/one
++ padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9]
++ padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9]
++ padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_in[9] padframe/mprj_io_inp_dis[9]
++ padframe/mprj_io_out[9] padframe/mprj_io_oeb[9] padframe/mprj_io_slow_sel[9] padframe/mprj_io_vtrip_sel[9]
++ gpio_control_in_2\[9\]/resetn gpio_control_in_1\[2\]/resetn gpio_control_in_2\[9\]/serial_clock
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[1\]/serial_data_in gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_2\[9\]/serial_load gpio_control_in_1\[2\]/serial_load mprj/io_in[9]
++ mprj/io_oeb[9] mprj/io_out[9] gpio_control_in_1\[1\]/vccd gpio_control_in_1\[1\]/vccd1
++ gpio_control_in_1\[1\]/vssd gpio_control_in_1\[1\]/vssd1 gpio_control_in_1\[1\]/zero
++ gpio_control_block
+Xgpio_32_defaults gpio_32_defaults/VGND gpio_32_defaults/VPWR gpio_32_defaults/gpio_defaults[0]
++ gpio_32_defaults/gpio_defaults[10] gpio_32_defaults/gpio_defaults[11] gpio_32_defaults/gpio_defaults[12]
++ gpio_32_defaults/gpio_defaults[1] gpio_32_defaults/gpio_defaults[2] gpio_32_defaults/gpio_defaults[3]
++ gpio_32_defaults/gpio_defaults[4] gpio_32_defaults/gpio_defaults[5] gpio_32_defaults/gpio_defaults[6]
++ gpio_32_defaults/gpio_defaults[7] gpio_32_defaults/gpio_defaults[8] gpio_32_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xmprj mprj/gpio_analog[0] mprj/gpio_analog[10] mprj/gpio_analog[11] mprj/gpio_analog[12]
++ mprj/gpio_analog[13] mprj/gpio_analog[14] mprj/gpio_analog[15] mprj/gpio_analog[16]
++ mprj/gpio_analog[17] mprj/gpio_analog[1] mprj/gpio_analog[2] mprj/gpio_analog[3]
++ mprj/gpio_analog[4] mprj/gpio_analog[5] mprj/gpio_analog[6] mprj/gpio_analog[7]
++ mprj/gpio_analog[8] mprj/gpio_analog[9] mprj/gpio_noesd[0] mprj/gpio_noesd[10] mprj/gpio_noesd[11]
++ mprj/gpio_noesd[12] mprj/gpio_noesd[13] mprj/gpio_noesd[14] mprj/gpio_noesd[15]
++ mprj/gpio_noesd[16] mprj/gpio_noesd[17] mprj/gpio_noesd[1] mprj/gpio_noesd[2] mprj/gpio_noesd[3]
++ mprj/gpio_noesd[4] mprj/gpio_noesd[5] mprj/gpio_noesd[6] mprj/gpio_noesd[7] mprj/gpio_noesd[8]
++ mprj/gpio_noesd[9] mprj/io_analog[0] mprj/io_analog[10] mprj/io_analog[1] mprj/io_analog[2]
++ mprj/io_analog[3] mprj/io_analog[7] mprj/io_analog[8] mprj/io_analog[9] mprj/io_analog[4]
++ mprj/io_analog[5] mprj/io_analog[6] mprj/io_clamp_high[0] mprj/io_clamp_high[1]
++ mprj/io_clamp_high[2] mprj/io_clamp_low[0] mprj/io_clamp_low[1] mprj/io_clamp_low[2]
++ mprj/io_in[0] mprj/io_in[10] mprj/io_in[11] mprj/io_in[12] mprj/io_in[13] mprj/io_in[14]
++ mprj/io_in[15] mprj/io_in[16] mprj/io_in[17] mprj/io_in[18] mprj/io_in[19] mprj/io_in[1]
++ mprj/io_in[20] mprj/io_in[21] mprj/io_in[22] mprj/io_in[23] mprj/io_in[24] mprj/io_in[25]
++ mprj/io_in[26] mprj/io_in[2] mprj/io_in[3] mprj/io_in[4] mprj/io_in[5] mprj/io_in[6]
++ mprj/io_in[7] mprj/io_in[8] mprj/io_in[9] mprj/io_in_3v3[0] mprj/io_in_3v3[10] mprj/io_in_3v3[11]
++ mprj/io_in_3v3[12] mprj/io_in_3v3[13] mprj/io_in_3v3[14] mprj/io_in_3v3[15] mprj/io_in_3v3[16]
++ mprj/io_in_3v3[17] mprj/io_in_3v3[18] mprj/io_in_3v3[19] mprj/io_in_3v3[1] mprj/io_in_3v3[20]
++ mprj/io_in_3v3[21] mprj/io_in_3v3[22] mprj/io_in_3v3[23] mprj/io_in_3v3[24] mprj/io_in_3v3[25]
++ mprj/io_in_3v3[26] mprj/io_in_3v3[2] mprj/io_in_3v3[3] mprj/io_in_3v3[4] mprj/io_in_3v3[5]
++ mprj/io_in_3v3[6] mprj/io_in_3v3[7] mprj/io_in_3v3[8] mprj/io_in_3v3[9] mprj/io_oeb[0]
++ mprj/io_oeb[10] mprj/io_oeb[11] mprj/io_oeb[12] mprj/io_oeb[13] mprj/io_oeb[14]
++ mprj/io_oeb[15] mprj/io_oeb[16] mprj/io_oeb[17] mprj/io_oeb[18] mprj/io_oeb[19]
++ mprj/io_oeb[1] mprj/io_oeb[20] mprj/io_oeb[21] mprj/io_oeb[22] mprj/io_oeb[23] mprj/io_oeb[24]
++ mprj/io_oeb[25] mprj/io_oeb[26] mprj/io_oeb[2] mprj/io_oeb[3] mprj/io_oeb[4] mprj/io_oeb[5]
++ mprj/io_oeb[6] mprj/io_oeb[7] mprj/io_oeb[8] mprj/io_oeb[9] mprj/io_out[0] mprj/io_out[10]
++ mprj/io_out[11] mprj/io_out[12] mprj/io_out[13] mprj/io_out[14] mprj/io_out[15]
++ mprj/io_out[16] mprj/io_out[17] mprj/io_out[18] mprj/io_out[19] mprj/io_out[1] mprj/io_out[20]
++ mprj/io_out[21] mprj/io_out[22] mprj/io_out[23] mprj/io_out[24] mprj/io_out[25]
++ mprj/io_out[26] mprj/io_out[2] mprj/io_out[3] mprj/io_out[4] mprj/io_out[5] mprj/io_out[6]
++ mprj/io_out[7] mprj/io_out[8] mprj/io_out[9] mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] mprj/la_data_out[0] mprj/la_data_out[100]
++ mprj/la_data_out[101] mprj/la_data_out[102] mprj/la_data_out[103] mprj/la_data_out[104]
++ mprj/la_data_out[105] mprj/la_data_out[106] mprj/la_data_out[107] mprj/la_data_out[108]
++ mprj/la_data_out[109] mprj/la_data_out[10] mprj/la_data_out[110] mprj/la_data_out[111]
++ mprj/la_data_out[112] mprj/la_data_out[113] mprj/la_data_out[114] mprj/la_data_out[115]
++ mprj/la_data_out[116] mprj/la_data_out[117] mprj/la_data_out[118] mprj/la_data_out[119]
++ mprj/la_data_out[11] mprj/la_data_out[120] mprj/la_data_out[121] mprj/la_data_out[122]
++ mprj/la_data_out[123] mprj/la_data_out[124] mprj/la_data_out[125] mprj/la_data_out[126]
++ mprj/la_data_out[127] mprj/la_data_out[12] mprj/la_data_out[13] mprj/la_data_out[14]
++ mprj/la_data_out[15] mprj/la_data_out[16] mprj/la_data_out[17] mprj/la_data_out[18]
++ mprj/la_data_out[19] mprj/la_data_out[1] mprj/la_data_out[20] mprj/la_data_out[21]
++ mprj/la_data_out[22] mprj/la_data_out[23] mprj/la_data_out[24] mprj/la_data_out[25]
++ mprj/la_data_out[26] mprj/la_data_out[27] mprj/la_data_out[28] mprj/la_data_out[29]
++ mprj/la_data_out[2] mprj/la_data_out[30] mprj/la_data_out[31] mprj/la_data_out[32]
++ mprj/la_data_out[33] mprj/la_data_out[34] mprj/la_data_out[35] mprj/la_data_out[36]
++ mprj/la_data_out[37] mprj/la_data_out[38] mprj/la_data_out[39] mprj/la_data_out[3]
++ mprj/la_data_out[40] mprj/la_data_out[41] mprj/la_data_out[42] mprj/la_data_out[43]
++ mprj/la_data_out[44] mprj/la_data_out[45] mprj/la_data_out[46] mprj/la_data_out[47]
++ mprj/la_data_out[48] mprj/la_data_out[49] mprj/la_data_out[4] mprj/la_data_out[50]
++ mprj/la_data_out[51] mprj/la_data_out[52] mprj/la_data_out[53] mprj/la_data_out[54]
++ mprj/la_data_out[55] mprj/la_data_out[56] mprj/la_data_out[57] mprj/la_data_out[58]
++ mprj/la_data_out[59] mprj/la_data_out[5] mprj/la_data_out[60] mprj/la_data_out[61]
++ mprj/la_data_out[62] mprj/la_data_out[63] mprj/la_data_out[64] mprj/la_data_out[65]
++ mprj/la_data_out[66] mprj/la_data_out[67] mprj/la_data_out[68] mprj/la_data_out[69]
++ mprj/la_data_out[6] mprj/la_data_out[70] mprj/la_data_out[71] mprj/la_data_out[72]
++ mprj/la_data_out[73] mprj/la_data_out[74] mprj/la_data_out[75] mprj/la_data_out[76]
++ mprj/la_data_out[77] mprj/la_data_out[78] mprj/la_data_out[79] mprj/la_data_out[7]
++ mprj/la_data_out[80] mprj/la_data_out[81] mprj/la_data_out[82] mprj/la_data_out[83]
++ mprj/la_data_out[84] mprj/la_data_out[85] mprj/la_data_out[86] mprj/la_data_out[87]
++ mprj/la_data_out[88] mprj/la_data_out[89] mprj/la_data_out[8] mprj/la_data_out[90]
++ mprj/la_data_out[91] mprj/la_data_out[92] mprj/la_data_out[93] mprj/la_data_out[94]
++ mprj/la_data_out[95] mprj/la_data_out[96] mprj/la_data_out[97] mprj/la_data_out[98]
++ mprj/la_data_out[99] mprj/la_data_out[9] mprj/la_oenb[0] mprj/la_oenb[100] mprj/la_oenb[101]
++ mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105] mprj/la_oenb[106]
++ mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10] mprj/la_oenb[110]
++ mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114] mprj/la_oenb[115]
++ mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119] mprj/la_oenb[11]
++ mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123] mprj/la_oenb[124]
++ mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12] mprj/la_oenb[13]
++ mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17] mprj/la_oenb[18]
++ mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21] mprj/la_oenb[22]
++ mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26] mprj/la_oenb[27]
++ mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30] mprj/la_oenb[31]
++ mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35] mprj/la_oenb[36]
++ mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3] mprj/la_oenb[40]
++ mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44] mprj/la_oenb[45]
++ mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49] mprj/la_oenb[4]
++ mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53] mprj/la_oenb[54]
++ mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58] mprj/la_oenb[59]
++ mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62] mprj/la_oenb[63]
++ mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67] mprj/la_oenb[68]
++ mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71] mprj/la_oenb[72]
++ mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76] mprj/la_oenb[77]
++ mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80] mprj/la_oenb[81]
++ mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85] mprj/la_oenb[86]
++ mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8] mprj/la_oenb[90]
++ mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94] mprj/la_oenb[95]
++ mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99] mprj/la_oenb[9]
++ mprj/user_clock2 mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2] mprj/vccd1 mprj/vccd2
++ mprj/vdda1 mprj/vdda2 mprj/vssa1 mprj/vssa2 mprj/vssd1 mprj/vssd2 mprj/wb_clk_i
++ mprj/wb_rst_i mprj/wbs_ack_o mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11]
++ mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16]
++ mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20]
++ mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25]
++ mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2]
++ mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5]
++ mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] mprj/wbs_cyc_i
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] mprj/wbs_dat_o[0] mprj/wbs_dat_o[10] mprj/wbs_dat_o[11]
++ mprj/wbs_dat_o[12] mprj/wbs_dat_o[13] mprj/wbs_dat_o[14] mprj/wbs_dat_o[15] mprj/wbs_dat_o[16]
++ mprj/wbs_dat_o[17] mprj/wbs_dat_o[18] mprj/wbs_dat_o[19] mprj/wbs_dat_o[1] mprj/wbs_dat_o[20]
++ mprj/wbs_dat_o[21] mprj/wbs_dat_o[22] mprj/wbs_dat_o[23] mprj/wbs_dat_o[24] mprj/wbs_dat_o[25]
++ mprj/wbs_dat_o[26] mprj/wbs_dat_o[27] mprj/wbs_dat_o[28] mprj/wbs_dat_o[29] mprj/wbs_dat_o[2]
++ mprj/wbs_dat_o[30] mprj/wbs_dat_o[31] mprj/wbs_dat_o[3] mprj/wbs_dat_o[4] mprj/wbs_dat_o[5]
++ mprj/wbs_dat_o[6] mprj/wbs_dat_o[7] mprj/wbs_dat_o[8] mprj/wbs_dat_o[9] mprj/wbs_sel_i[0]
++ mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] mprj/wbs_stb_i mprj/wbs_we_i
++ user_analog_project_wrapper
+Xgpio_26_defaults gpio_26_defaults/VGND gpio_26_defaults/VPWR gpio_26_defaults/gpio_defaults[0]
++ gpio_26_defaults/gpio_defaults[10] gpio_26_defaults/gpio_defaults[11] gpio_26_defaults/gpio_defaults[12]
++ gpio_26_defaults/gpio_defaults[1] gpio_26_defaults/gpio_defaults[2] gpio_26_defaults/gpio_defaults[3]
++ gpio_26_defaults/gpio_defaults[4] gpio_26_defaults/gpio_defaults[5] gpio_26_defaults/gpio_defaults[6]
++ gpio_26_defaults/gpio_defaults[7] gpio_26_defaults/gpio_defaults[8] gpio_26_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[4\] gpio_29_defaults/gpio_defaults[0] gpio_29_defaults/gpio_defaults[10]
++ gpio_29_defaults/gpio_defaults[11] gpio_29_defaults/gpio_defaults[12] gpio_29_defaults/gpio_defaults[1]
++ gpio_29_defaults/gpio_defaults[2] gpio_29_defaults/gpio_defaults[3] gpio_29_defaults/gpio_defaults[4]
++ gpio_29_defaults/gpio_defaults[5] gpio_29_defaults/gpio_defaults[6] gpio_29_defaults/gpio_defaults[7]
++ gpio_29_defaults/gpio_defaults[8] gpio_29_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[29]
++ gpio_control_in_2\[4\]/one housekeeping/mgmt_gpio_in[29] gpio_control_in_2\[4\]/one
++ padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_in[18] padframe/mprj_io_inp_dis[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_oeb[18] padframe/mprj_io_slow_sel[18]
++ padframe/mprj_io_vtrip_sel[18] gpio_control_in_2\[4\]/resetn gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[4\]/serial_data_in
++ gpio_control_in_2\[3\]/serial_data_in gpio_control_in_2\[4\]/serial_load gpio_control_in_2\[5\]/serial_load
++ mprj/io_in[18] mprj/io_oeb[18] mprj/io_out[18] gpio_control_in_2\[4\]/vccd gpio_control_in_2\[4\]/vccd1
++ gpio_control_in_2\[4\]/vssd gpio_control_in_2\[4\]/vssd1 gpio_control_in_2\[4\]/zero
++ gpio_control_block
+Xgpio_control_bidir_1\[1\] gpio_01_defaults\[1\]/gpio_defaults[0] gpio_01_defaults\[1\]/gpio_defaults[10]
++ gpio_01_defaults\[1\]/gpio_defaults[11] gpio_01_defaults\[1\]/gpio_defaults[12]
++ gpio_01_defaults\[1\]/gpio_defaults[1] gpio_01_defaults\[1\]/gpio_defaults[2] gpio_01_defaults\[1\]/gpio_defaults[3]
++ gpio_01_defaults\[1\]/gpio_defaults[4] gpio_01_defaults\[1\]/gpio_defaults[5] gpio_01_defaults\[1\]/gpio_defaults[6]
++ gpio_01_defaults\[1\]/gpio_defaults[7] gpio_01_defaults\[1\]/gpio_defaults[8] gpio_01_defaults\[1\]/gpio_defaults[9]
++ housekeeping/mgmt_gpio_in[1] gpio_control_bidir_1\[1\]/mgmt_gpio_oeb gpio_control_bidir_1\[1\]/mgmt_gpio_out
++ gpio_control_bidir_1\[1\]/one padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1]
++ padframe/mprj_io_analog_sel[1] padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5]
++ padframe/mprj_io_holdover[1] padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_in[1]
++ padframe/mprj_io_inp_dis[1] padframe/mprj_io_out[1] padframe/mprj_io_oeb[1] padframe/mprj_io_slow_sel[1]
++ padframe/mprj_io_vtrip_sel[1] gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[2\]/serial_clock gpio_control_bidir_1\[1\]/serial_data_in
++ gpio_control_in_1a\[0\]/serial_data_in gpio_control_in_2\[1\]/serial_load gpio_control_in_2\[2\]/serial_load
++ mprj/io_in[1] mprj/io_oeb[1] mprj/io_out[1] gpio_control_bidir_1\[1\]/vccd gpio_control_bidir_1\[1\]/vccd1
++ gpio_control_bidir_1\[1\]/vssd gpio_control_bidir_1\[1\]/vssd1 gpio_control_bidir_1\[1\]/zero
++ gpio_control_block
+Xgpio_10_defaults gpio_10_defaults/VGND gpio_10_defaults/VPWR gpio_10_defaults/gpio_defaults[0]
++ gpio_10_defaults/gpio_defaults[10] gpio_10_defaults/gpio_defaults[11] gpio_10_defaults/gpio_defaults[12]
++ gpio_10_defaults/gpio_defaults[1] gpio_10_defaults/gpio_defaults[2] gpio_10_defaults/gpio_defaults[3]
++ gpio_10_defaults/gpio_defaults[4] gpio_10_defaults/gpio_defaults[5] gpio_10_defaults/gpio_defaults[6]
++ gpio_10_defaults/gpio_defaults[7] gpio_10_defaults/gpio_defaults[8] gpio_10_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_35_defaults gpio_35_defaults/VGND gpio_35_defaults/VPWR gpio_35_defaults/gpio_defaults[0]
++ gpio_35_defaults/gpio_defaults[10] gpio_35_defaults/gpio_defaults[11] gpio_35_defaults/gpio_defaults[12]
++ gpio_35_defaults/gpio_defaults[1] gpio_35_defaults/gpio_defaults[2] gpio_35_defaults/gpio_defaults[3]
++ gpio_35_defaults/gpio_defaults[4] gpio_35_defaults/gpio_defaults[5] gpio_35_defaults/gpio_defaults[6]
++ gpio_35_defaults/gpio_defaults[7] gpio_35_defaults/gpio_defaults[8] gpio_35_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xhousekeeping housekeeping/VGND housekeeping/VPWR soc/debug_in soc/debug_mode soc/debug_oeb
++ soc/debug_out soc/irq[3] soc/irq[4] soc/irq[5] user_id_value/mask_rev[0] user_id_value/mask_rev[10]
++ user_id_value/mask_rev[11] user_id_value/mask_rev[12] user_id_value/mask_rev[13]
++ user_id_value/mask_rev[14] user_id_value/mask_rev[15] user_id_value/mask_rev[16]
++ user_id_value/mask_rev[17] user_id_value/mask_rev[18] user_id_value/mask_rev[19]
++ user_id_value/mask_rev[1] user_id_value/mask_rev[20] user_id_value/mask_rev[21]
++ user_id_value/mask_rev[22] user_id_value/mask_rev[23] user_id_value/mask_rev[24]
++ user_id_value/mask_rev[25] user_id_value/mask_rev[26] user_id_value/mask_rev[27]
++ user_id_value/mask_rev[28] user_id_value/mask_rev[29] user_id_value/mask_rev[2]
++ user_id_value/mask_rev[30] user_id_value/mask_rev[31] user_id_value/mask_rev[3]
++ user_id_value/mask_rev[4] user_id_value/mask_rev[5] user_id_value/mask_rev[6] user_id_value/mask_rev[7]
++ user_id_value/mask_rev[8] user_id_value/mask_rev[9] housekeeping/mgmt_gpio_in[0]
++ housekeeping/mgmt_gpio_in[10] housekeeping/mgmt_gpio_in[11] housekeeping/mgmt_gpio_in[12]
++ housekeeping/mgmt_gpio_in[13] housekeeping/mgmt_gpio_in[14] housekeeping/mgmt_gpio_in[15]
++ housekeeping/mgmt_gpio_in[16] housekeeping/mgmt_gpio_in[17] housekeeping/mgmt_gpio_in[18]
++ housekeeping/mgmt_gpio_in[19] housekeeping/mgmt_gpio_in[1] housekeeping/mgmt_gpio_in[20]
++ housekeeping/mgmt_gpio_in[21] housekeeping/mgmt_gpio_in[22] housekeeping/mgmt_gpio_in[23]
++ housekeeping/mgmt_gpio_in[24] housekeeping/mgmt_gpio_in[25] housekeeping/mgmt_gpio_in[26]
++ housekeeping/mgmt_gpio_in[27] housekeeping/mgmt_gpio_in[28] housekeeping/mgmt_gpio_in[29]
++ housekeeping/mgmt_gpio_in[2] housekeeping/mgmt_gpio_in[30] housekeeping/mgmt_gpio_in[31]
++ housekeeping/mgmt_gpio_in[32] housekeeping/mgmt_gpio_in[33] housekeeping/mgmt_gpio_in[34]
++ housekeeping/mgmt_gpio_in[35] housekeeping/mgmt_gpio_in[36] housekeeping/mgmt_gpio_in[37]
++ housekeeping/mgmt_gpio_in[3] housekeeping/mgmt_gpio_in[4] housekeeping/mgmt_gpio_in[5]
++ housekeeping/mgmt_gpio_in[6] housekeeping/mgmt_gpio_in[7] housekeeping/mgmt_gpio_in[8]
++ housekeeping/mgmt_gpio_in[9] housekeeping/mgmt_gpio_oeb[0] housekeeping/mgmt_gpio_oeb[10]
++ housekeeping/mgmt_gpio_oeb[11] housekeeping/mgmt_gpio_oeb[12] housekeeping/mgmt_gpio_oeb[13]
++ housekeeping/mgmt_gpio_oeb[14] housekeeping/mgmt_gpio_oeb[15] housekeeping/mgmt_gpio_oeb[16]
++ housekeeping/mgmt_gpio_oeb[17] housekeeping/mgmt_gpio_oeb[18] housekeeping/mgmt_gpio_oeb[19]
++ housekeeping/mgmt_gpio_oeb[1] housekeeping/mgmt_gpio_oeb[20] housekeeping/mgmt_gpio_oeb[21]
++ housekeeping/mgmt_gpio_oeb[22] housekeeping/mgmt_gpio_oeb[23] housekeeping/mgmt_gpio_oeb[24]
++ housekeeping/mgmt_gpio_oeb[25] housekeeping/mgmt_gpio_oeb[26] housekeeping/mgmt_gpio_oeb[27]
++ housekeeping/mgmt_gpio_oeb[28] housekeeping/mgmt_gpio_oeb[29] housekeeping/mgmt_gpio_oeb[2]
++ housekeeping/mgmt_gpio_oeb[30] housekeeping/mgmt_gpio_oeb[31] housekeeping/mgmt_gpio_oeb[32]
++ housekeeping/mgmt_gpio_oeb[33] housekeeping/mgmt_gpio_oeb[34] housekeeping/mgmt_gpio_oeb[35]
++ housekeeping/mgmt_gpio_oeb[36] housekeeping/mgmt_gpio_oeb[37] housekeeping/mgmt_gpio_oeb[3]
++ housekeeping/mgmt_gpio_oeb[4] housekeeping/mgmt_gpio_oeb[5] housekeeping/mgmt_gpio_oeb[6]
++ housekeeping/mgmt_gpio_oeb[7] housekeeping/mgmt_gpio_oeb[8] housekeeping/mgmt_gpio_oeb[9]
++ housekeeping/mgmt_gpio_out[0] housekeeping/mgmt_gpio_in[10] housekeeping/mgmt_gpio_in[11]
++ housekeeping/mgmt_gpio_in[12] housekeeping/mgmt_gpio_in[13] housekeeping/mgmt_gpio_in[14]
++ housekeeping/mgmt_gpio_in[15] housekeeping/mgmt_gpio_in[16] housekeeping/mgmt_gpio_in[17]
++ housekeeping/mgmt_gpio_in[18] housekeeping/mgmt_gpio_in[19] housekeeping/mgmt_gpio_out[1]
++ housekeeping/mgmt_gpio_in[20] housekeeping/mgmt_gpio_in[21] housekeeping/mgmt_gpio_in[22]
++ housekeeping/mgmt_gpio_in[23] housekeeping/mgmt_gpio_in[24] housekeeping/mgmt_gpio_in[25]
++ housekeeping/mgmt_gpio_in[26] housekeeping/mgmt_gpio_in[27] housekeeping/mgmt_gpio_in[28]
++ housekeeping/mgmt_gpio_in[29] housekeeping/mgmt_gpio_in[2] housekeeping/mgmt_gpio_in[30]
++ housekeeping/mgmt_gpio_in[31] housekeeping/mgmt_gpio_in[32] housekeeping/mgmt_gpio_in[33]
++ housekeeping/mgmt_gpio_in[34] housekeeping/mgmt_gpio_out[35] housekeeping/mgmt_gpio_out[36]
++ housekeeping/mgmt_gpio_out[37] housekeeping/mgmt_gpio_in[3] housekeeping/mgmt_gpio_in[4]
++ housekeeping/mgmt_gpio_in[5] housekeeping/mgmt_gpio_in[6] housekeeping/mgmt_gpio_in[7]
++ housekeeping/mgmt_gpio_in[8] housekeeping/mgmt_gpio_in[9] padframe/flash_clk_core
++ padframe/flash_clk_oeb_core padframe/flash_csb_core padframe/flash_csb_oeb_core
++ padframe/flash_io0_di_core padframe/flash_io0_do_core padframe/flash_io0_ieb_core
++ padframe/flash_io0_oeb_core padframe/flash_io1_di_core padframe/flash_io1_do_core
++ padframe/flash_io1_ieb_core padframe/flash_io1_oeb_core clocking/sel2[0] clocking/sel2[1]
++ clocking/sel2[2] clocking/ext_clk_sel pll/dco pll/div[0] pll/div[1] pll/div[2] pll/div[3]
++ pll/div[4] pll/enable clocking/sel[0] clocking/sel[1] clocking/sel[2] pll/ext_trim[0]
++ pll/ext_trim[10] pll/ext_trim[11] pll/ext_trim[12] pll/ext_trim[13] pll/ext_trim[14]
++ pll/ext_trim[15] pll/ext_trim[16] pll/ext_trim[17] pll/ext_trim[18] pll/ext_trim[19]
++ pll/ext_trim[1] pll/ext_trim[20] pll/ext_trim[21] pll/ext_trim[22] pll/ext_trim[23]
++ pll/ext_trim[24] pll/ext_trim[25] pll/ext_trim[2] pll/ext_trim[3] pll/ext_trim[4]
++ pll/ext_trim[5] pll/ext_trim[6] pll/ext_trim[7] pll/ext_trim[8] pll/ext_trim[9]
++ por/porb_l housekeeping/pwr_ctrl_out[0] housekeeping/pwr_ctrl_out[1] housekeeping/pwr_ctrl_out[2]
++ housekeeping/pwr_ctrl_out[3] soc/qspi_enabled housekeeping/reset soc/ser_rx soc/ser_tx
++ housekeeping/serial_clock housekeeping/serial_data_1 housekeeping/serial_data_2
++ housekeeping/serial_load housekeeping/serial_resetn soc/spi_csb soc/spi_enabled
++ soc/spi_sck soc/spi_sdi soc/spi_sdo soc/spi_sdoenb soc/flash_clk soc/flash_csb soc/flash_io0_di
++ soc/flash_io0_do soc/flash_io0_oeb soc/flash_io1_di soc/flash_io1_do soc/flash_io1_oeb
++ soc/flash_io2_di soc/flash_io2_do soc/flash_io2_oeb soc/flash_io3_di soc/flash_io3_do
++ soc/flash_io3_oeb soc/sram_ro_addr[0] soc/sram_ro_addr[1] soc/sram_ro_addr[2] soc/sram_ro_addr[3]
++ soc/sram_ro_addr[4] soc/sram_ro_addr[5] soc/sram_ro_addr[6] soc/sram_ro_addr[7]
++ soc/sram_ro_clk soc/sram_ro_csb soc/sram_ro_data[0] soc/sram_ro_data[10] soc/sram_ro_data[11]
++ soc/sram_ro_data[12] soc/sram_ro_data[13] soc/sram_ro_data[14] soc/sram_ro_data[15]
++ soc/sram_ro_data[16] soc/sram_ro_data[17] soc/sram_ro_data[18] soc/sram_ro_data[19]
++ soc/sram_ro_data[1] soc/sram_ro_data[20] soc/sram_ro_data[21] soc/sram_ro_data[22]
++ soc/sram_ro_data[23] soc/sram_ro_data[24] soc/sram_ro_data[25] soc/sram_ro_data[26]
++ soc/sram_ro_data[27] soc/sram_ro_data[28] soc/sram_ro_data[29] soc/sram_ro_data[2]
++ soc/sram_ro_data[30] soc/sram_ro_data[31] soc/sram_ro_data[3] soc/sram_ro_data[4]
++ soc/sram_ro_data[5] soc/sram_ro_data[6] soc/sram_ro_data[7] soc/sram_ro_data[8]
++ soc/sram_ro_data[9] soc/trap soc/uart_enabled housekeeping/user_clock housekeeping/usr1_vcc_pwrgood
++ housekeeping/usr1_vdd_pwrgood housekeeping/usr2_vcc_pwrgood housekeeping/usr2_vdd_pwrgood
++ soc/hk_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11] soc/mprj_adr_o[12]
++ soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16] soc/mprj_adr_o[17]
++ soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20] soc/mprj_adr_o[21]
++ soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25] soc/mprj_adr_o[26]
++ soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2] soc/mprj_adr_o[30]
++ soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5] soc/mprj_adr_o[6]
++ soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] soc/core_clk soc/mprj_cyc_o
++ soc/mprj_dat_o[0] soc/mprj_dat_o[10] soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13]
++ soc/mprj_dat_o[14] soc/mprj_dat_o[15] soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18]
++ soc/mprj_dat_o[19] soc/mprj_dat_o[1] soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22]
++ soc/mprj_dat_o[23] soc/mprj_dat_o[24] soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27]
++ soc/mprj_dat_o[28] soc/mprj_dat_o[29] soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31]
++ soc/mprj_dat_o[3] soc/mprj_dat_o[4] soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7]
++ soc/mprj_dat_o[8] soc/mprj_dat_o[9] soc/hk_dat_i[0] soc/hk_dat_i[10] soc/hk_dat_i[11]
++ soc/hk_dat_i[12] soc/hk_dat_i[13] soc/hk_dat_i[14] soc/hk_dat_i[15] soc/hk_dat_i[16]
++ soc/hk_dat_i[17] soc/hk_dat_i[18] soc/hk_dat_i[19] soc/hk_dat_i[1] soc/hk_dat_i[20]
++ soc/hk_dat_i[21] soc/hk_dat_i[22] soc/hk_dat_i[23] soc/hk_dat_i[24] soc/hk_dat_i[25]
++ soc/hk_dat_i[26] soc/hk_dat_i[27] soc/hk_dat_i[28] soc/hk_dat_i[29] soc/hk_dat_i[2]
++ soc/hk_dat_i[30] soc/hk_dat_i[31] soc/hk_dat_i[3] soc/hk_dat_i[4] soc/hk_dat_i[5]
++ soc/hk_dat_i[6] soc/hk_dat_i[7] soc/hk_dat_i[8] soc/hk_dat_i[9] soc/core_rstn soc/mprj_sel_o[0]
++ soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/hk_stb_o soc/mprj_we_o
++ housekeeping
+Xgpio_control_in_2\[2\] gpio_27_defaults/gpio_defaults[0] gpio_27_defaults/gpio_defaults[10]
++ gpio_27_defaults/gpio_defaults[11] gpio_27_defaults/gpio_defaults[12] gpio_27_defaults/gpio_defaults[1]
++ gpio_27_defaults/gpio_defaults[2] gpio_27_defaults/gpio_defaults[3] gpio_27_defaults/gpio_defaults[4]
++ gpio_27_defaults/gpio_defaults[5] gpio_27_defaults/gpio_defaults[6] gpio_27_defaults/gpio_defaults[7]
++ gpio_27_defaults/gpio_defaults[8] gpio_27_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[27]
++ gpio_control_in_2\[2\]/one housekeeping/mgmt_gpio_in[27] gpio_control_in_2\[2\]/one
++ padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_in[16] padframe/mprj_io_inp_dis[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_oeb[16] padframe/mprj_io_slow_sel[16]
++ padframe/mprj_io_vtrip_sel[16] gpio_control_in_2\[2\]/resetn gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[2\]/serial_data_in
++ gpio_control_in_2\[1\]/serial_data_in gpio_control_in_2\[2\]/serial_load gpio_control_in_2\[3\]/serial_load
++ mprj/io_in[16] mprj/io_oeb[16] mprj/io_out[16] gpio_control_in_2\[2\]/vccd gpio_control_in_2\[2\]/vccd1
++ gpio_control_in_2\[2\]/vssd gpio_control_in_2\[2\]/vssd1 gpio_control_in_2\[2\]/zero
++ gpio_control_block
+Xgpio_29_defaults gpio_29_defaults/VGND gpio_29_defaults/VPWR gpio_29_defaults/gpio_defaults[0]
++ gpio_29_defaults/gpio_defaults[10] gpio_29_defaults/gpio_defaults[11] gpio_29_defaults/gpio_defaults[12]
++ gpio_29_defaults/gpio_defaults[1] gpio_29_defaults/gpio_defaults[2] gpio_29_defaults/gpio_defaults[3]
++ gpio_29_defaults/gpio_defaults[4] gpio_29_defaults/gpio_defaults[5] gpio_29_defaults/gpio_defaults[6]
++ gpio_29_defaults/gpio_defaults[7] gpio_29_defaults/gpio_defaults[8] gpio_29_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_13_defaults gpio_13_defaults/VGND gpio_13_defaults/VPWR gpio_13_defaults/gpio_defaults[0]
++ gpio_13_defaults/gpio_defaults[10] gpio_13_defaults/gpio_defaults[11] gpio_13_defaults/gpio_defaults[12]
++ gpio_13_defaults/gpio_defaults[1] gpio_13_defaults/gpio_defaults[2] gpio_13_defaults/gpio_defaults[3]
++ gpio_13_defaults/gpio_defaults[4] gpio_13_defaults/gpio_defaults[5] gpio_13_defaults/gpio_defaults[6]
++ gpio_13_defaults/gpio_defaults[7] gpio_13_defaults/gpio_defaults[8] gpio_13_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[5\] gpio_7_defaults/gpio_defaults[0] gpio_7_defaults/gpio_defaults[10]
++ gpio_7_defaults/gpio_defaults[11] gpio_7_defaults/gpio_defaults[12] gpio_7_defaults/gpio_defaults[1]
++ gpio_7_defaults/gpio_defaults[2] gpio_7_defaults/gpio_defaults[3] gpio_7_defaults/gpio_defaults[4]
++ gpio_7_defaults/gpio_defaults[5] gpio_7_defaults/gpio_defaults[6] gpio_7_defaults/gpio_defaults[7]
++ gpio_7_defaults/gpio_defaults[8] gpio_7_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[7]
++ gpio_control_in_1a\[5\]/one housekeeping/mgmt_gpio_in[7] gpio_control_in_1a\[5\]/one
++ padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7]
++ padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] padframe/mprj_io_holdover[7]
++ padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_in[7] padframe/mprj_io_inp_dis[7]
++ padframe/mprj_io_out[7] padframe/mprj_io_oeb[7] padframe/mprj_io_slow_sel[7] padframe/mprj_io_vtrip_sel[7]
++ gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn gpio_control_in_2\[7\]/serial_clock
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_1a\[5\]/serial_data_in gpio_control_in_1\[0\]/serial_data_in
++ gpio_control_in_2\[7\]/serial_load gpio_control_in_2\[8\]/serial_load mprj/io_in[7]
++ mprj/io_oeb[7] mprj/io_out[7] gpio_control_in_1a\[5\]/vccd gpio_control_in_1a\[5\]/vccd1
++ gpio_control_in_1a\[5\]/vssd gpio_control_in_1a\[5\]/vssd1 gpio_control_in_1a\[5\]/zero
++ gpio_control_block
+Xgpio_5_defaults gpio_5_defaults/VGND gpio_5_defaults/VPWR gpio_5_defaults/gpio_defaults[0]
++ gpio_5_defaults/gpio_defaults[10] gpio_5_defaults/gpio_defaults[11] gpio_5_defaults/gpio_defaults[12]
++ gpio_5_defaults/gpio_defaults[1] gpio_5_defaults/gpio_defaults[2] gpio_5_defaults/gpio_defaults[3]
++ gpio_5_defaults/gpio_defaults[4] gpio_5_defaults/gpio_defaults[5] gpio_5_defaults/gpio_defaults[6]
++ gpio_5_defaults/gpio_defaults[7] gpio_5_defaults/gpio_defaults[8] gpio_5_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_2\[2\] gpio_37_defaults/gpio_defaults[0] gpio_37_defaults/gpio_defaults[10]
++ gpio_37_defaults/gpio_defaults[11] gpio_37_defaults/gpio_defaults[12] gpio_37_defaults/gpio_defaults[1]
++ gpio_37_defaults/gpio_defaults[2] gpio_37_defaults/gpio_defaults[3] gpio_37_defaults/gpio_defaults[4]
++ gpio_37_defaults/gpio_defaults[5] gpio_37_defaults/gpio_defaults[6] gpio_37_defaults/gpio_defaults[7]
++ gpio_37_defaults/gpio_defaults[8] gpio_37_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[37]
++ housekeeping/mgmt_gpio_oeb[37] housekeeping/mgmt_gpio_out[37] gpio_control_bidir_2\[2\]/one
++ padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26]
++ padframe/mprj_io_dm[78] padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26]
++ padframe/mprj_io_ib_mode_sel[26] padframe/mprj_io_in[26] padframe/mprj_io_inp_dis[26]
++ padframe/mprj_io_out[26] padframe/mprj_io_oeb[26] padframe/mprj_io_slow_sel[26]
++ padframe/mprj_io_vtrip_sel[26] gpio_control_in_1\[4\]/resetn gpio_control_in_1\[5\]/resetn
++ gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[5\]/serial_clock housekeeping/serial_data_2
++ gpio_control_bidir_2\[1\]/serial_data_in gpio_control_in_1\[4\]/serial_load gpio_control_in_1\[5\]/serial_load
++ mprj/io_in[26] mprj/io_oeb[26] mprj/io_out[26] gpio_control_bidir_2\[2\]/vccd gpio_control_bidir_2\[2\]/vccd1
++ gpio_control_bidir_2\[2\]/vssd gpio_control_bidir_2\[2\]/vssd1 gpio_control_bidir_2\[2\]/zero
++ gpio_control_block
+Xgpio_01_defaults\[0\] gpio_01_defaults\[0\]/VGND gpio_01_defaults\[0\]/VPWR gpio_01_defaults\[0\]/gpio_defaults[0]
++ gpio_01_defaults\[0\]/gpio_defaults[10] gpio_01_defaults\[0\]/gpio_defaults[11]
++ gpio_01_defaults\[0\]/gpio_defaults[12] gpio_01_defaults\[0\]/gpio_defaults[1] gpio_01_defaults\[0\]/gpio_defaults[2]
++ gpio_01_defaults\[0\]/gpio_defaults[3] gpio_01_defaults\[0\]/gpio_defaults[4] gpio_01_defaults\[0\]/gpio_defaults[5]
++ gpio_01_defaults\[0\]/gpio_defaults[6] gpio_01_defaults\[0\]/gpio_defaults[7] gpio_01_defaults\[0\]/gpio_defaults[8]
++ gpio_01_defaults\[0\]/gpio_defaults[9] gpio_defaults_block
+.ends
+
diff --git a/caravel/spi/lvs/caravel.spice b/caravel/spi/lvs/caravel.spice
new file mode 100644
index 0000000..0c331c5
--- /dev/null
+++ b/caravel/spi/lvs/caravel.spice
@@ -0,0 +1,2406 @@
+* NGSPICE file created from caravel.ext - technology: sky130A
+
+* Black-box entry subcircuit for gpio_control_block abstract view
+.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
++ gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4] gpio_defaults[5]
++ gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9] mgmt_gpio_in
++ mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en pad_gpio_ana_pol pad_gpio_ana_sel
++ pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover pad_gpio_ib_mode_sel
++ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
++ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
++ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
+.ends
+
+* Black-box entry subcircuit for gpio_defaults_block abstract view
+.subckt gpio_defaults_block VGND VPWR gpio_defaults[0] gpio_defaults[10] gpio_defaults[11]
++ gpio_defaults[12] gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4]
++ gpio_defaults[5] gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9]
+.ends
+
+* Black-box entry subcircuit for digital_pll abstract view
+.subckt digital_pll VGND VPWR clockp[0] clockp[1] dco div[0] div[1] div[2] div[3]
++ div[4] enable ext_trim[0] ext_trim[10] ext_trim[11] ext_trim[12] ext_trim[13] ext_trim[14]
++ ext_trim[15] ext_trim[16] ext_trim[17] ext_trim[18] ext_trim[19] ext_trim[1] ext_trim[20]
++ ext_trim[21] ext_trim[22] ext_trim[23] ext_trim[24] ext_trim[25] ext_trim[2] ext_trim[3]
++ ext_trim[4] ext_trim[5] ext_trim[6] ext_trim[7] ext_trim[8] ext_trim[9] osc resetb
+.ends
+
+* Black-box entry subcircuit for chip_io abstract view
+.subckt chip_io clock clock_core por flash_clk flash_clk_core flash_clk_ieb_core flash_clk_oeb_core
++ flash_csb flash_csb_core flash_csb_ieb_core flash_csb_oeb_core flash_io0 flash_io0_di_core
++ flash_io0_do_core flash_io0_ieb_core flash_io0_oeb_core flash_io1 flash_io1_di_core
++ flash_io1_do_core flash_io1_ieb_core flash_io1_oeb_core gpio gpio_in_core gpio_inenb_core
++ gpio_mode0_core gpio_mode1_core gpio_out_core gpio_outenb_core vccd_pad vdda_pad
++ vddio_pad vddio_pad2 vssa_pad vssd_pad vssio_pad vssio_pad2 mprj_io[0] mprj_io_analog_en[0]
++ mprj_io_analog_pol[0] mprj_io_analog_sel[0] mprj_io_dm[0] mprj_io_dm[1] mprj_io_dm[2]
++ mprj_io_holdover[0] mprj_io_ib_mode_sel[0] mprj_io_inp_dis[0] mprj_io_oeb[0] mprj_io_out[0]
++ mprj_io_slow_sel[0] mprj_io_vtrip_sel[0] mprj_io_in[0] mprj_analog_io[3] mprj_io[10]
++ mprj_io_analog_en[10] mprj_io_analog_pol[10] mprj_io_analog_sel[10] mprj_io_dm[30]
++ mprj_io_dm[31] mprj_io_dm[32] mprj_io_holdover[10] mprj_io_ib_mode_sel[10] mprj_io_inp_dis[10]
++ mprj_io_oeb[10] mprj_io_out[10] mprj_io_slow_sel[10] mprj_io_vtrip_sel[10] mprj_io_in[10]
++ mprj_analog_io[4] mprj_io[11] mprj_io_analog_en[11] mprj_io_analog_pol[11] mprj_io_analog_sel[11]
++ mprj_io_dm[33] mprj_io_dm[34] mprj_io_dm[35] mprj_io_holdover[11] mprj_io_ib_mode_sel[11]
++ mprj_io_inp_dis[11] mprj_io_oeb[11] mprj_io_out[11] mprj_io_slow_sel[11] mprj_io_vtrip_sel[11]
++ mprj_io_in[11] mprj_analog_io[5] mprj_io[12] mprj_io_analog_en[12] mprj_io_analog_pol[12]
++ mprj_io_analog_sel[12] mprj_io_dm[36] mprj_io_dm[37] mprj_io_dm[38] mprj_io_holdover[12]
++ mprj_io_ib_mode_sel[12] mprj_io_inp_dis[12] mprj_io_oeb[12] mprj_io_out[12] mprj_io_slow_sel[12]
++ mprj_io_vtrip_sel[12] mprj_io_in[12] mprj_analog_io[6] mprj_io[13] mprj_io_analog_en[13]
++ mprj_io_analog_pol[13] mprj_io_analog_sel[13] mprj_io_dm[39] mprj_io_dm[40] mprj_io_dm[41]
++ mprj_io_holdover[13] mprj_io_ib_mode_sel[13] mprj_io_inp_dis[13] mprj_io_oeb[13]
++ mprj_io_out[13] mprj_io_slow_sel[13] mprj_io_vtrip_sel[13] mprj_io_in[13] mprj_analog_io[7]
++ mprj_io[14] mprj_io_analog_en[14] mprj_io_analog_pol[14] mprj_io_analog_sel[14]
++ mprj_io_dm[42] mprj_io_dm[43] mprj_io_dm[44] mprj_io_holdover[14] mprj_io_ib_mode_sel[14]
++ mprj_io_inp_dis[14] mprj_io_oeb[14] mprj_io_out[14] mprj_io_slow_sel[14] mprj_io_vtrip_sel[14]
++ mprj_io_in[14] mprj_analog_io[8] mprj_io[15] mprj_io_analog_en[15] mprj_io_analog_pol[15]
++ mprj_io_analog_sel[15] mprj_io_dm[45] mprj_io_dm[46] mprj_io_dm[47] mprj_io_holdover[15]
++ mprj_io_ib_mode_sel[15] mprj_io_inp_dis[15] mprj_io_oeb[15] mprj_io_out[15] mprj_io_slow_sel[15]
++ mprj_io_vtrip_sel[15] mprj_io_in[15] mprj_analog_io[9] mprj_io[16] mprj_io_analog_en[16]
++ mprj_io_analog_pol[16] mprj_io_analog_sel[16] mprj_io_dm[48] mprj_io_dm[49] mprj_io_dm[50]
++ mprj_io_holdover[16] mprj_io_ib_mode_sel[16] mprj_io_inp_dis[16] mprj_io_oeb[16]
++ mprj_io_out[16] mprj_io_slow_sel[16] mprj_io_vtrip_sel[16] mprj_io_in[16] mprj_analog_io[10]
++ mprj_io[17] mprj_io_analog_en[17] mprj_io_analog_pol[17] mprj_io_analog_sel[17]
++ mprj_io_dm[51] mprj_io_dm[52] mprj_io_dm[53] mprj_io_holdover[17] mprj_io_ib_mode_sel[17]
++ mprj_io_inp_dis[17] mprj_io_oeb[17] mprj_io_out[17] mprj_io_slow_sel[17] mprj_io_vtrip_sel[17]
++ mprj_io_in[17] mprj_analog_io[11] mprj_io[18] mprj_io_analog_en[18] mprj_io_analog_pol[18]
++ mprj_io_analog_sel[18] mprj_io_dm[54] mprj_io_dm[55] mprj_io_dm[56] mprj_io_holdover[18]
++ mprj_io_ib_mode_sel[18] mprj_io_inp_dis[18] mprj_io_oeb[18] mprj_io_out[18] mprj_io_slow_sel[18]
++ mprj_io_vtrip_sel[18] mprj_io_in[18] mprj_io[1] mprj_io_analog_en[1] mprj_io_analog_pol[1]
++ mprj_io_analog_sel[1] mprj_io_dm[3] mprj_io_dm[4] mprj_io_dm[5] mprj_io_holdover[1]
++ mprj_io_ib_mode_sel[1] mprj_io_inp_dis[1] mprj_io_oeb[1] mprj_io_out[1] mprj_io_slow_sel[1]
++ mprj_io_vtrip_sel[1] mprj_io_in[1] mprj_io[2] mprj_io_analog_en[2] mprj_io_analog_pol[2]
++ mprj_io_analog_sel[2] mprj_io_dm[6] mprj_io_dm[7] mprj_io_dm[8] mprj_io_holdover[2]
++ mprj_io_ib_mode_sel[2] mprj_io_inp_dis[2] mprj_io_oeb[2] mprj_io_out[2] mprj_io_slow_sel[2]
++ mprj_io_vtrip_sel[2] mprj_io_in[2] mprj_io[3] mprj_io_analog_en[3] mprj_io_analog_pol[3]
++ mprj_io_analog_sel[3] mprj_io_dm[10] mprj_io_dm[11] mprj_io_dm[9] mprj_io_holdover[3]
++ mprj_io_ib_mode_sel[3] mprj_io_inp_dis[3] mprj_io_oeb[3] mprj_io_out[3] mprj_io_slow_sel[3]
++ mprj_io_vtrip_sel[3] mprj_io_in[3] mprj_io[4] mprj_io_analog_en[4] mprj_io_analog_pol[4]
++ mprj_io_analog_sel[4] mprj_io_dm[12] mprj_io_dm[13] mprj_io_dm[14] mprj_io_holdover[4]
++ mprj_io_ib_mode_sel[4] mprj_io_inp_dis[4] mprj_io_oeb[4] mprj_io_out[4] mprj_io_slow_sel[4]
++ mprj_io_vtrip_sel[4] mprj_io_in[4] mprj_io[5] mprj_io_analog_en[5] mprj_io_analog_pol[5]
++ mprj_io_analog_sel[5] mprj_io_dm[15] mprj_io_dm[16] mprj_io_dm[17] mprj_io_holdover[5]
++ mprj_io_ib_mode_sel[5] mprj_io_inp_dis[5] mprj_io_oeb[5] mprj_io_out[5] mprj_io_slow_sel[5]
++ mprj_io_vtrip_sel[5] mprj_io_in[5] mprj_io[6] mprj_io_analog_en[6] mprj_io_analog_pol[6]
++ mprj_io_analog_sel[6] mprj_io_dm[18] mprj_io_dm[19] mprj_io_dm[20] mprj_io_holdover[6]
++ mprj_io_ib_mode_sel[6] mprj_io_inp_dis[6] mprj_io_oeb[6] mprj_io_out[6] mprj_io_slow_sel[6]
++ mprj_io_vtrip_sel[6] mprj_io_in[6] mprj_analog_io[0] mprj_io[7] mprj_io_analog_en[7]
++ mprj_io_analog_pol[7] mprj_io_analog_sel[7] mprj_io_dm[21] mprj_io_dm[22] mprj_io_dm[23]
++ mprj_io_holdover[7] mprj_io_ib_mode_sel[7] mprj_io_inp_dis[7] mprj_io_oeb[7] mprj_io_out[7]
++ mprj_io_slow_sel[7] mprj_io_vtrip_sel[7] mprj_io_in[7] mprj_analog_io[1] mprj_io[8]
++ mprj_io_analog_en[8] mprj_io_analog_pol[8] mprj_io_analog_sel[8] mprj_io_dm[24]
++ mprj_io_dm[25] mprj_io_dm[26] mprj_io_holdover[8] mprj_io_ib_mode_sel[8] mprj_io_inp_dis[8]
++ mprj_io_oeb[8] mprj_io_out[8] mprj_io_slow_sel[8] mprj_io_vtrip_sel[8] mprj_io_in[8]
++ mprj_analog_io[2] mprj_io[9] mprj_io_analog_en[9] mprj_io_analog_pol[9] mprj_io_analog_sel[9]
++ mprj_io_dm[27] mprj_io_dm[28] mprj_io_dm[29] mprj_io_holdover[9] mprj_io_ib_mode_sel[9]
++ mprj_io_inp_dis[9] mprj_io_oeb[9] mprj_io_out[9] mprj_io_slow_sel[9] mprj_io_vtrip_sel[9]
++ mprj_io_in[9] mprj_analog_io[12] mprj_io[19] mprj_io_analog_en[19] mprj_io_analog_pol[19]
++ mprj_io_analog_sel[19] mprj_io_dm[57] mprj_io_dm[58] mprj_io_dm[59] mprj_io_holdover[19]
++ mprj_io_ib_mode_sel[19] mprj_io_inp_dis[19] mprj_io_oeb[19] mprj_io_out[19] mprj_io_slow_sel[19]
++ mprj_io_vtrip_sel[19] mprj_io_in[19] mprj_analog_io[22] mprj_io[29] mprj_io_analog_en[29]
++ mprj_io_analog_pol[29] mprj_io_analog_sel[29] mprj_io_dm[87] mprj_io_dm[88] mprj_io_dm[89]
++ mprj_io_holdover[29] mprj_io_ib_mode_sel[29] mprj_io_inp_dis[29] mprj_io_oeb[29]
++ mprj_io_out[29] mprj_io_slow_sel[29] mprj_io_vtrip_sel[29] mprj_io_in[29] mprj_analog_io[23]
++ mprj_io[30] mprj_io_analog_en[30] mprj_io_analog_pol[30] mprj_io_analog_sel[30]
++ mprj_io_dm[90] mprj_io_dm[91] mprj_io_dm[92] mprj_io_holdover[30] mprj_io_ib_mode_sel[30]
++ mprj_io_inp_dis[30] mprj_io_oeb[30] mprj_io_out[30] mprj_io_slow_sel[30] mprj_io_vtrip_sel[30]
++ mprj_io_in[30] mprj_analog_io[24] mprj_io[31] mprj_io_analog_en[31] mprj_io_analog_pol[31]
++ mprj_io_analog_sel[31] mprj_io_dm[93] mprj_io_dm[94] mprj_io_dm[95] mprj_io_holdover[31]
++ mprj_io_ib_mode_sel[31] mprj_io_inp_dis[31] mprj_io_oeb[31] mprj_io_out[31] mprj_io_slow_sel[31]
++ mprj_io_vtrip_sel[31] mprj_io_in[31] mprj_analog_io[25] mprj_io[32] mprj_io_analog_en[32]
++ mprj_io_analog_pol[32] mprj_io_analog_sel[32] mprj_io_dm[96] mprj_io_dm[97] mprj_io_dm[98]
++ mprj_io_holdover[32] mprj_io_ib_mode_sel[32] mprj_io_inp_dis[32] mprj_io_oeb[32]
++ mprj_io_out[32] mprj_io_slow_sel[32] mprj_io_vtrip_sel[32] mprj_io_in[32] mprj_analog_io[26]
++ mprj_io[33] mprj_io_analog_en[33] mprj_io_analog_pol[33] mprj_io_analog_sel[33]
++ mprj_io_dm[100] mprj_io_dm[101] mprj_io_dm[99] mprj_io_holdover[33] mprj_io_ib_mode_sel[33]
++ mprj_io_inp_dis[33] mprj_io_oeb[33] mprj_io_out[33] mprj_io_slow_sel[33] mprj_io_vtrip_sel[33]
++ mprj_io_in[33] mprj_analog_io[27] mprj_io[34] mprj_io_analog_en[34] mprj_io_analog_pol[34]
++ mprj_io_analog_sel[34] mprj_io_dm[102] mprj_io_dm[103] mprj_io_dm[104] mprj_io_holdover[34]
++ mprj_io_ib_mode_sel[34] mprj_io_inp_dis[34] mprj_io_oeb[34] mprj_io_out[34] mprj_io_slow_sel[34]
++ mprj_io_vtrip_sel[34] mprj_io_in[34] mprj_analog_io[28] mprj_io[35] mprj_io_analog_en[35]
++ mprj_io_analog_pol[35] mprj_io_analog_sel[35] mprj_io_dm[105] mprj_io_dm[106] mprj_io_dm[107]
++ mprj_io_holdover[35] mprj_io_ib_mode_sel[35] mprj_io_inp_dis[35] mprj_io_oeb[35]
++ mprj_io_out[35] mprj_io_slow_sel[35] mprj_io_vtrip_sel[35] mprj_io_in[35] mprj_io[36]
++ mprj_io_analog_en[36] mprj_io_analog_pol[36] mprj_io_analog_sel[36] mprj_io_dm[108]
++ mprj_io_dm[109] mprj_io_dm[110] mprj_io_holdover[36] mprj_io_ib_mode_sel[36] mprj_io_inp_dis[36]
++ mprj_io_oeb[36] mprj_io_out[36] mprj_io_slow_sel[36] mprj_io_vtrip_sel[36] mprj_io_in[36]
++ mprj_io[37] mprj_io_analog_en[37] mprj_io_analog_pol[37] mprj_io_analog_sel[37]
++ mprj_io_dm[111] mprj_io_dm[112] mprj_io_dm[113] mprj_io_holdover[37] mprj_io_ib_mode_sel[37]
++ mprj_io_inp_dis[37] mprj_io_oeb[37] mprj_io_out[37] mprj_io_slow_sel[37] mprj_io_vtrip_sel[37]
++ mprj_io_in[37] mprj_analog_io[13] mprj_io[20] mprj_io_analog_en[20] mprj_io_analog_pol[20]
++ mprj_io_analog_sel[20] mprj_io_dm[60] mprj_io_dm[61] mprj_io_dm[62] mprj_io_holdover[20]
++ mprj_io_ib_mode_sel[20] mprj_io_inp_dis[20] mprj_io_oeb[20] mprj_io_out[20] mprj_io_slow_sel[20]
++ mprj_io_vtrip_sel[20] mprj_io_in[20] mprj_analog_io[14] mprj_io[21] mprj_io_analog_en[21]
++ mprj_io_analog_pol[21] mprj_io_analog_sel[21] mprj_io_dm[63] mprj_io_dm[64] mprj_io_dm[65]
++ mprj_io_holdover[21] mprj_io_ib_mode_sel[21] mprj_io_inp_dis[21] mprj_io_oeb[21]
++ mprj_io_out[21] mprj_io_slow_sel[21] mprj_io_vtrip_sel[21] mprj_io_in[21] mprj_analog_io[15]
++ mprj_io[22] mprj_io_analog_en[22] mprj_io_analog_pol[22] mprj_io_analog_sel[22]
++ mprj_io_dm[66] mprj_io_dm[67] mprj_io_dm[68] mprj_io_holdover[22] mprj_io_ib_mode_sel[22]
++ mprj_io_inp_dis[22] mprj_io_oeb[22] mprj_io_out[22] mprj_io_slow_sel[22] mprj_io_vtrip_sel[22]
++ mprj_io_in[22] mprj_analog_io[16] mprj_io[23] mprj_io_analog_en[23] mprj_io_analog_pol[23]
++ mprj_io_analog_sel[23] mprj_io_dm[69] mprj_io_dm[70] mprj_io_dm[71] mprj_io_holdover[23]
++ mprj_io_ib_mode_sel[23] mprj_io_inp_dis[23] mprj_io_oeb[23] mprj_io_out[23] mprj_io_slow_sel[23]
++ mprj_io_vtrip_sel[23] mprj_io_in[23] mprj_analog_io[17] mprj_io[24] mprj_io_analog_en[24]
++ mprj_io_analog_pol[24] mprj_io_analog_sel[24] mprj_io_dm[72] mprj_io_dm[73] mprj_io_dm[74]
++ mprj_io_holdover[24] mprj_io_ib_mode_sel[24] mprj_io_inp_dis[24] mprj_io_oeb[24]
++ mprj_io_out[24] mprj_io_slow_sel[24] mprj_io_vtrip_sel[24] mprj_io_in[24] mprj_analog_io[18]
++ mprj_io[25] mprj_io_analog_en[25] mprj_io_analog_pol[25] mprj_io_analog_sel[25]
++ mprj_io_dm[75] mprj_io_dm[76] mprj_io_dm[77] mprj_io_holdover[25] mprj_io_ib_mode_sel[25]
++ mprj_io_inp_dis[25] mprj_io_oeb[25] mprj_io_out[25] mprj_io_slow_sel[25] mprj_io_vtrip_sel[25]
++ mprj_io_in[25] mprj_analog_io[19] mprj_io[26] mprj_io_analog_en[26] mprj_io_analog_pol[26]
++ mprj_io_analog_sel[26] mprj_io_dm[78] mprj_io_dm[79] mprj_io_dm[80] mprj_io_holdover[26]
++ mprj_io_ib_mode_sel[26] mprj_io_inp_dis[26] mprj_io_oeb[26] mprj_io_out[26] mprj_io_slow_sel[26]
++ mprj_io_vtrip_sel[26] mprj_io_in[26] mprj_analog_io[20] mprj_io[27] mprj_io_analog_en[27]
++ mprj_io_analog_pol[27] mprj_io_analog_sel[27] mprj_io_dm[81] mprj_io_dm[82] mprj_io_dm[83]
++ mprj_io_holdover[27] mprj_io_ib_mode_sel[27] mprj_io_inp_dis[27] mprj_io_oeb[27]
++ mprj_io_out[27] mprj_io_slow_sel[27] mprj_io_vtrip_sel[27] mprj_io_in[27] mprj_analog_io[21]
++ mprj_io[28] mprj_io_analog_en[28] mprj_io_analog_pol[28] mprj_io_analog_sel[28]
++ mprj_io_dm[84] mprj_io_dm[85] mprj_io_dm[86] mprj_io_holdover[28] mprj_io_ib_mode_sel[28]
++ mprj_io_inp_dis[28] mprj_io_oeb[28] mprj_io_out[28] mprj_io_slow_sel[28] mprj_io_vtrip_sel[28]
++ mprj_io_in[28] porb_h resetb resetb_core_h vdda vssa vssd vccd1_pad vdda1_pad vdda1_pad2
++ vssa1_pad vssa1_pad2 vccd1 vdda1 vssa1 vssd1 vssd1_pad vccd2_pad vdda2_pad vssa2_pad
++ vccd vccd2 vdda2 vddio vssa2 vssd2 vssd2_pad vssio
+.ends
+
+* Black-box entry subcircuit for mgmt_core_wrapper abstract view
+.subckt mgmt_core_wrapper VGND VPWR core_clk core_rstn debug_in debug_mode debug_oeb
++ debug_out flash_clk flash_csb flash_io0_di flash_io0_do flash_io0_oeb flash_io1_di
++ flash_io1_do flash_io1_oeb flash_io2_di flash_io2_do flash_io2_oeb flash_io3_di
++ flash_io3_do flash_io3_oeb gpio_in_pad gpio_inenb_pad gpio_mode0_pad gpio_mode1_pad
++ gpio_out_pad gpio_outenb_pad hk_ack_i hk_dat_i[0] hk_dat_i[10] hk_dat_i[11] hk_dat_i[12]
++ hk_dat_i[13] hk_dat_i[14] hk_dat_i[15] hk_dat_i[16] hk_dat_i[17] hk_dat_i[18] hk_dat_i[19]
++ hk_dat_i[1] hk_dat_i[20] hk_dat_i[21] hk_dat_i[22] hk_dat_i[23] hk_dat_i[24] hk_dat_i[25]
++ hk_dat_i[26] hk_dat_i[27] hk_dat_i[28] hk_dat_i[29] hk_dat_i[2] hk_dat_i[30] hk_dat_i[31]
++ hk_dat_i[3] hk_dat_i[4] hk_dat_i[5] hk_dat_i[6] hk_dat_i[7] hk_dat_i[8] hk_dat_i[9]
++ hk_stb_o irq[0] irq[1] irq[2] irq[3] irq[4] irq[5] la_iena[0] la_iena[100] la_iena[101]
++ la_iena[102] la_iena[103] la_iena[104] la_iena[105] la_iena[106] la_iena[107] la_iena[108]
++ la_iena[109] la_iena[10] la_iena[110] la_iena[111] la_iena[112] la_iena[113] la_iena[114]
++ la_iena[115] la_iena[116] la_iena[117] la_iena[118] la_iena[119] la_iena[11] la_iena[120]
++ la_iena[121] la_iena[122] la_iena[123] la_iena[124] la_iena[125] la_iena[126] la_iena[127]
++ la_iena[12] la_iena[13] la_iena[14] la_iena[15] la_iena[16] la_iena[17] la_iena[18]
++ la_iena[19] la_iena[1] la_iena[20] la_iena[21] la_iena[22] la_iena[23] la_iena[24]
++ la_iena[25] la_iena[26] la_iena[27] la_iena[28] la_iena[29] la_iena[2] la_iena[30]
++ la_iena[31] la_iena[32] la_iena[33] la_iena[34] la_iena[35] la_iena[36] la_iena[37]
++ la_iena[38] la_iena[39] la_iena[3] la_iena[40] la_iena[41] la_iena[42] la_iena[43]
++ la_iena[44] la_iena[45] la_iena[46] la_iena[47] la_iena[48] la_iena[49] la_iena[4]
++ la_iena[50] la_iena[51] la_iena[52] la_iena[53] la_iena[54] la_iena[55] la_iena[56]
++ la_iena[57] la_iena[58] la_iena[59] la_iena[5] la_iena[60] la_iena[61] la_iena[62]
++ la_iena[63] la_iena[64] la_iena[65] la_iena[66] la_iena[67] la_iena[68] la_iena[69]
++ la_iena[6] la_iena[70] la_iena[71] la_iena[72] la_iena[73] la_iena[74] la_iena[75]
++ la_iena[76] la_iena[77] la_iena[78] la_iena[79] la_iena[7] la_iena[80] la_iena[81]
++ la_iena[82] la_iena[83] la_iena[84] la_iena[85] la_iena[86] la_iena[87] la_iena[88]
++ la_iena[89] la_iena[8] la_iena[90] la_iena[91] la_iena[92] la_iena[93] la_iena[94]
++ la_iena[95] la_iena[96] la_iena[97] la_iena[98] la_iena[99] la_iena[9] la_input[0]
++ la_input[100] la_input[101] la_input[102] la_input[103] la_input[104] la_input[105]
++ la_input[106] la_input[107] la_input[108] la_input[109] la_input[10] la_input[110]
++ la_input[111] la_input[112] la_input[113] la_input[114] la_input[115] la_input[116]
++ la_input[117] la_input[118] la_input[119] la_input[11] la_input[120] la_input[121]
++ la_input[122] la_input[123] la_input[124] la_input[125] la_input[126] la_input[127]
++ la_input[12] la_input[13] la_input[14] la_input[15] la_input[16] la_input[17] la_input[18]
++ la_input[19] la_input[1] la_input[20] la_input[21] la_input[22] la_input[23] la_input[24]
++ la_input[25] la_input[26] la_input[27] la_input[28] la_input[29] la_input[2] la_input[30]
++ la_input[31] la_input[32] la_input[33] la_input[34] la_input[35] la_input[36] la_input[37]
++ la_input[38] la_input[39] la_input[3] la_input[40] la_input[41] la_input[42] la_input[43]
++ la_input[44] la_input[45] la_input[46] la_input[47] la_input[48] la_input[49] la_input[4]
++ la_input[50] la_input[51] la_input[52] la_input[53] la_input[54] la_input[55] la_input[56]
++ la_input[57] la_input[58] la_input[59] la_input[5] la_input[60] la_input[61] la_input[62]
++ la_input[63] la_input[64] la_input[65] la_input[66] la_input[67] la_input[68] la_input[69]
++ la_input[6] la_input[70] la_input[71] la_input[72] la_input[73] la_input[74] la_input[75]
++ la_input[76] la_input[77] la_input[78] la_input[79] la_input[7] la_input[80] la_input[81]
++ la_input[82] la_input[83] la_input[84] la_input[85] la_input[86] la_input[87] la_input[88]
++ la_input[89] la_input[8] la_input[90] la_input[91] la_input[92] la_input[93] la_input[94]
++ la_input[95] la_input[96] la_input[97] la_input[98] la_input[99] la_input[9] la_oenb[0]
++ la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106]
++ la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112]
++ la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119]
++ la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125]
++ la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16]
++ la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22]
++ la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29]
++ la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35]
++ la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41]
++ la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48]
++ la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54]
++ la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60]
++ la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67]
++ la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73]
++ la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7]
++ la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86]
++ la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92]
++ la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99]
++ la_oenb[9] la_output[0] la_output[100] la_output[101] la_output[102] la_output[103]
++ la_output[104] la_output[105] la_output[106] la_output[107] la_output[108] la_output[109]
++ la_output[10] la_output[110] la_output[111] la_output[112] la_output[113] la_output[114]
++ la_output[115] la_output[116] la_output[117] la_output[118] la_output[119] la_output[11]
++ la_output[120] la_output[121] la_output[122] la_output[123] la_output[124] la_output[125]
++ la_output[126] la_output[127] la_output[12] la_output[13] la_output[14] la_output[15]
++ la_output[16] la_output[17] la_output[18] la_output[19] la_output[1] la_output[20]
++ la_output[21] la_output[22] la_output[23] la_output[24] la_output[25] la_output[26]
++ la_output[27] la_output[28] la_output[29] la_output[2] la_output[30] la_output[31]
++ la_output[32] la_output[33] la_output[34] la_output[35] la_output[36] la_output[37]
++ la_output[38] la_output[39] la_output[3] la_output[40] la_output[41] la_output[42]
++ la_output[43] la_output[44] la_output[45] la_output[46] la_output[47] la_output[48]
++ la_output[49] la_output[4] la_output[50] la_output[51] la_output[52] la_output[53]
++ la_output[54] la_output[55] la_output[56] la_output[57] la_output[58] la_output[59]
++ la_output[5] la_output[60] la_output[61] la_output[62] la_output[63] la_output[64]
++ la_output[65] la_output[66] la_output[67] la_output[68] la_output[69] la_output[6]
++ la_output[70] la_output[71] la_output[72] la_output[73] la_output[74] la_output[75]
++ la_output[76] la_output[77] la_output[78] la_output[79] la_output[7] la_output[80]
++ la_output[81] la_output[82] la_output[83] la_output[84] la_output[85] la_output[86]
++ la_output[87] la_output[88] la_output[89] la_output[8] la_output[90] la_output[91]
++ la_output[92] la_output[93] la_output[94] la_output[95] la_output[96] la_output[97]
++ la_output[98] la_output[99] la_output[9] mprj_ack_i mprj_adr_o[0] mprj_adr_o[10]
++ mprj_adr_o[11] mprj_adr_o[12] mprj_adr_o[13] mprj_adr_o[14] mprj_adr_o[15] mprj_adr_o[16]
++ mprj_adr_o[17] mprj_adr_o[18] mprj_adr_o[19] mprj_adr_o[1] mprj_adr_o[20] mprj_adr_o[21]
++ mprj_adr_o[22] mprj_adr_o[23] mprj_adr_o[24] mprj_adr_o[25] mprj_adr_o[26] mprj_adr_o[27]
++ mprj_adr_o[28] mprj_adr_o[29] mprj_adr_o[2] mprj_adr_o[30] mprj_adr_o[31] mprj_adr_o[3]
++ mprj_adr_o[4] mprj_adr_o[5] mprj_adr_o[6] mprj_adr_o[7] mprj_adr_o[8] mprj_adr_o[9]
++ mprj_cyc_o mprj_dat_i[0] mprj_dat_i[10] mprj_dat_i[11] mprj_dat_i[12] mprj_dat_i[13]
++ mprj_dat_i[14] mprj_dat_i[15] mprj_dat_i[16] mprj_dat_i[17] mprj_dat_i[18] mprj_dat_i[19]
++ mprj_dat_i[1] mprj_dat_i[20] mprj_dat_i[21] mprj_dat_i[22] mprj_dat_i[23] mprj_dat_i[24]
++ mprj_dat_i[25] mprj_dat_i[26] mprj_dat_i[27] mprj_dat_i[28] mprj_dat_i[29] mprj_dat_i[2]
++ mprj_dat_i[30] mprj_dat_i[31] mprj_dat_i[3] mprj_dat_i[4] mprj_dat_i[5] mprj_dat_i[6]
++ mprj_dat_i[7] mprj_dat_i[8] mprj_dat_i[9] mprj_dat_o[0] mprj_dat_o[10] mprj_dat_o[11]
++ mprj_dat_o[12] mprj_dat_o[13] mprj_dat_o[14] mprj_dat_o[15] mprj_dat_o[16] mprj_dat_o[17]
++ mprj_dat_o[18] mprj_dat_o[19] mprj_dat_o[1] mprj_dat_o[20] mprj_dat_o[21] mprj_dat_o[22]
++ mprj_dat_o[23] mprj_dat_o[24] mprj_dat_o[25] mprj_dat_o[26] mprj_dat_o[27] mprj_dat_o[28]
++ mprj_dat_o[29] mprj_dat_o[2] mprj_dat_o[30] mprj_dat_o[31] mprj_dat_o[3] mprj_dat_o[4]
++ mprj_dat_o[5] mprj_dat_o[6] mprj_dat_o[7] mprj_dat_o[8] mprj_dat_o[9] mprj_sel_o[0]
++ mprj_sel_o[1] mprj_sel_o[2] mprj_sel_o[3] mprj_stb_o mprj_wb_iena mprj_we_o qspi_enabled
++ ser_rx ser_tx spi_csb spi_enabled spi_sck spi_sdi spi_sdo spi_sdoenb sram_ro_addr[0]
++ sram_ro_addr[1] sram_ro_addr[2] sram_ro_addr[3] sram_ro_addr[4] sram_ro_addr[5]
++ sram_ro_addr[6] sram_ro_addr[7] sram_ro_clk sram_ro_csb sram_ro_data[0] sram_ro_data[10]
++ sram_ro_data[11] sram_ro_data[12] sram_ro_data[13] sram_ro_data[14] sram_ro_data[15]
++ sram_ro_data[16] sram_ro_data[17] sram_ro_data[18] sram_ro_data[19] sram_ro_data[1]
++ sram_ro_data[20] sram_ro_data[21] sram_ro_data[22] sram_ro_data[23] sram_ro_data[24]
++ sram_ro_data[25] sram_ro_data[26] sram_ro_data[27] sram_ro_data[28] sram_ro_data[29]
++ sram_ro_data[2] sram_ro_data[30] sram_ro_data[31] sram_ro_data[3] sram_ro_data[4]
++ sram_ro_data[5] sram_ro_data[6] sram_ro_data[7] sram_ro_data[8] sram_ro_data[9]
++ trap uart_enabled user_irq_ena[0] user_irq_ena[1] user_irq_ena[2]
+.ends
+
+* Black-box entry subcircuit for simple_por abstract view
+.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+.ends
+
+* Black-box entry subcircuit for caravel_clocking abstract view
+.subckt caravel_clocking VGND VPWR core_clk ext_clk ext_clk_sel ext_reset pll_clk
++ pll_clk90 resetb resetb_sync sel2[0] sel2[1] sel2[2] sel[0] sel[1] sel[2] user_clk
+.ends
+
+* Black-box entry subcircuit for user_id_programming abstract view
+.subckt user_id_programming mask_rev[0] mask_rev[10] mask_rev[11] mask_rev[12] mask_rev[13]
++ mask_rev[14] mask_rev[15] mask_rev[16] mask_rev[17] mask_rev[18] mask_rev[19] mask_rev[1]
++ mask_rev[20] mask_rev[21] mask_rev[22] mask_rev[23] mask_rev[24] mask_rev[25] mask_rev[26]
++ mask_rev[27] mask_rev[28] mask_rev[29] mask_rev[2] mask_rev[30] mask_rev[31] mask_rev[3]
++ mask_rev[4] mask_rev[5] mask_rev[6] mask_rev[7] mask_rev[8] mask_rev[9] VPWR VGND
+.ends
+
+* Black-box entry subcircuit for mgmt_protect abstract view
+.subckt mgmt_protect caravel_clk caravel_clk2 caravel_rstn la_data_in_core[0] la_data_in_core[100]
++ la_data_in_core[101] la_data_in_core[102] la_data_in_core[103] la_data_in_core[104]
++ la_data_in_core[105] la_data_in_core[106] la_data_in_core[107] la_data_in_core[108]
++ la_data_in_core[109] la_data_in_core[10] la_data_in_core[110] la_data_in_core[111]
++ la_data_in_core[112] la_data_in_core[113] la_data_in_core[114] la_data_in_core[115]
++ la_data_in_core[116] la_data_in_core[117] la_data_in_core[118] la_data_in_core[119]
++ la_data_in_core[11] la_data_in_core[120] la_data_in_core[121] la_data_in_core[122]
++ la_data_in_core[123] la_data_in_core[124] la_data_in_core[125] la_data_in_core[126]
++ la_data_in_core[127] la_data_in_core[12] la_data_in_core[13] la_data_in_core[14]
++ la_data_in_core[15] la_data_in_core[16] la_data_in_core[17] la_data_in_core[18]
++ la_data_in_core[19] la_data_in_core[1] la_data_in_core[20] la_data_in_core[21] la_data_in_core[22]
++ la_data_in_core[23] la_data_in_core[24] la_data_in_core[25] la_data_in_core[26]
++ la_data_in_core[27] la_data_in_core[28] la_data_in_core[29] la_data_in_core[2] la_data_in_core[30]
++ la_data_in_core[31] la_data_in_core[32] la_data_in_core[33] la_data_in_core[34]
++ la_data_in_core[35] la_data_in_core[36] la_data_in_core[37] la_data_in_core[38]
++ la_data_in_core[39] la_data_in_core[3] la_data_in_core[40] la_data_in_core[41] la_data_in_core[42]
++ la_data_in_core[43] la_data_in_core[44] la_data_in_core[45] la_data_in_core[46]
++ la_data_in_core[47] la_data_in_core[48] la_data_in_core[49] la_data_in_core[4] la_data_in_core[50]
++ la_data_in_core[51] la_data_in_core[52] la_data_in_core[53] la_data_in_core[54]
++ la_data_in_core[55] la_data_in_core[56] la_data_in_core[57] la_data_in_core[58]
++ la_data_in_core[59] la_data_in_core[5] la_data_in_core[60] la_data_in_core[61] la_data_in_core[62]
++ la_data_in_core[63] la_data_in_core[64] la_data_in_core[65] la_data_in_core[66]
++ la_data_in_core[67] la_data_in_core[68] la_data_in_core[69] la_data_in_core[6] la_data_in_core[70]
++ la_data_in_core[71] la_data_in_core[72] la_data_in_core[73] la_data_in_core[74]
++ la_data_in_core[75] la_data_in_core[76] la_data_in_core[77] la_data_in_core[78]
++ la_data_in_core[79] la_data_in_core[7] la_data_in_core[80] la_data_in_core[81] la_data_in_core[82]
++ la_data_in_core[83] la_data_in_core[84] la_data_in_core[85] la_data_in_core[86]
++ la_data_in_core[87] la_data_in_core[88] la_data_in_core[89] la_data_in_core[8] la_data_in_core[90]
++ la_data_in_core[91] la_data_in_core[92] la_data_in_core[93] la_data_in_core[94]
++ la_data_in_core[95] la_data_in_core[96] la_data_in_core[97] la_data_in_core[98]
++ la_data_in_core[99] la_data_in_core[9] la_data_in_mprj[0] la_data_in_mprj[100] la_data_in_mprj[101]
++ la_data_in_mprj[102] la_data_in_mprj[103] la_data_in_mprj[104] la_data_in_mprj[105]
++ la_data_in_mprj[106] la_data_in_mprj[107] la_data_in_mprj[108] la_data_in_mprj[109]
++ la_data_in_mprj[10] la_data_in_mprj[110] la_data_in_mprj[111] la_data_in_mprj[112]
++ la_data_in_mprj[113] la_data_in_mprj[114] la_data_in_mprj[115] la_data_in_mprj[116]
++ la_data_in_mprj[117] la_data_in_mprj[118] la_data_in_mprj[119] la_data_in_mprj[11]
++ la_data_in_mprj[120] la_data_in_mprj[121] la_data_in_mprj[122] la_data_in_mprj[123]
++ la_data_in_mprj[124] la_data_in_mprj[125] la_data_in_mprj[126] la_data_in_mprj[127]
++ la_data_in_mprj[12] la_data_in_mprj[13] la_data_in_mprj[14] la_data_in_mprj[15]
++ la_data_in_mprj[16] la_data_in_mprj[17] la_data_in_mprj[18] la_data_in_mprj[19]
++ la_data_in_mprj[1] la_data_in_mprj[20] la_data_in_mprj[21] la_data_in_mprj[22] la_data_in_mprj[23]
++ la_data_in_mprj[24] la_data_in_mprj[25] la_data_in_mprj[26] la_data_in_mprj[27]
++ la_data_in_mprj[28] la_data_in_mprj[29] la_data_in_mprj[2] la_data_in_mprj[30] la_data_in_mprj[31]
++ la_data_in_mprj[32] la_data_in_mprj[33] la_data_in_mprj[34] la_data_in_mprj[35]
++ la_data_in_mprj[36] la_data_in_mprj[37] la_data_in_mprj[38] la_data_in_mprj[39]
++ la_data_in_mprj[3] la_data_in_mprj[40] la_data_in_mprj[41] la_data_in_mprj[42] la_data_in_mprj[43]
++ la_data_in_mprj[44] la_data_in_mprj[45] la_data_in_mprj[46] la_data_in_mprj[47]
++ la_data_in_mprj[48] la_data_in_mprj[49] la_data_in_mprj[4] la_data_in_mprj[50] la_data_in_mprj[51]
++ la_data_in_mprj[52] la_data_in_mprj[53] la_data_in_mprj[54] la_data_in_mprj[55]
++ la_data_in_mprj[56] la_data_in_mprj[57] la_data_in_mprj[58] la_data_in_mprj[59]
++ la_data_in_mprj[5] la_data_in_mprj[60] la_data_in_mprj[61] la_data_in_mprj[62] la_data_in_mprj[63]
++ la_data_in_mprj[64] la_data_in_mprj[65] la_data_in_mprj[66] la_data_in_mprj[67]
++ la_data_in_mprj[68] la_data_in_mprj[69] la_data_in_mprj[6] la_data_in_mprj[70] la_data_in_mprj[71]
++ la_data_in_mprj[72] la_data_in_mprj[73] la_data_in_mprj[74] la_data_in_mprj[75]
++ la_data_in_mprj[76] la_data_in_mprj[77] la_data_in_mprj[78] la_data_in_mprj[79]
++ la_data_in_mprj[7] la_data_in_mprj[80] la_data_in_mprj[81] la_data_in_mprj[82] la_data_in_mprj[83]
++ la_data_in_mprj[84] la_data_in_mprj[85] la_data_in_mprj[86] la_data_in_mprj[87]
++ la_data_in_mprj[88] la_data_in_mprj[89] la_data_in_mprj[8] la_data_in_mprj[90] la_data_in_mprj[91]
++ la_data_in_mprj[92] la_data_in_mprj[93] la_data_in_mprj[94] la_data_in_mprj[95]
++ la_data_in_mprj[96] la_data_in_mprj[97] la_data_in_mprj[98] la_data_in_mprj[99]
++ la_data_in_mprj[9] la_data_out_core[0] la_data_out_core[100] la_data_out_core[101]
++ la_data_out_core[102] la_data_out_core[103] la_data_out_core[104] la_data_out_core[105]
++ la_data_out_core[106] la_data_out_core[107] la_data_out_core[108] la_data_out_core[109]
++ la_data_out_core[10] la_data_out_core[110] la_data_out_core[111] la_data_out_core[112]
++ la_data_out_core[113] la_data_out_core[114] la_data_out_core[115] la_data_out_core[116]
++ la_data_out_core[117] la_data_out_core[118] la_data_out_core[119] la_data_out_core[11]
++ la_data_out_core[120] la_data_out_core[121] la_data_out_core[122] la_data_out_core[123]
++ la_data_out_core[124] la_data_out_core[125] la_data_out_core[126] la_data_out_core[127]
++ la_data_out_core[12] la_data_out_core[13] la_data_out_core[14] la_data_out_core[15]
++ la_data_out_core[16] la_data_out_core[17] la_data_out_core[18] la_data_out_core[19]
++ la_data_out_core[1] la_data_out_core[20] la_data_out_core[21] la_data_out_core[22]
++ la_data_out_core[23] la_data_out_core[24] la_data_out_core[25] la_data_out_core[26]
++ la_data_out_core[27] la_data_out_core[28] la_data_out_core[29] la_data_out_core[2]
++ la_data_out_core[30] la_data_out_core[31] la_data_out_core[32] la_data_out_core[33]
++ la_data_out_core[34] la_data_out_core[35] la_data_out_core[36] la_data_out_core[37]
++ la_data_out_core[38] la_data_out_core[39] la_data_out_core[3] la_data_out_core[40]
++ la_data_out_core[41] la_data_out_core[42] la_data_out_core[43] la_data_out_core[44]
++ la_data_out_core[45] la_data_out_core[46] la_data_out_core[47] la_data_out_core[48]
++ la_data_out_core[49] la_data_out_core[4] la_data_out_core[50] la_data_out_core[51]
++ la_data_out_core[52] la_data_out_core[53] la_data_out_core[54] la_data_out_core[55]
++ la_data_out_core[56] la_data_out_core[57] la_data_out_core[58] la_data_out_core[59]
++ la_data_out_core[5] la_data_out_core[60] la_data_out_core[61] la_data_out_core[62]
++ la_data_out_core[63] la_data_out_core[64] la_data_out_core[65] la_data_out_core[66]
++ la_data_out_core[67] la_data_out_core[68] la_data_out_core[69] la_data_out_core[6]
++ la_data_out_core[70] la_data_out_core[71] la_data_out_core[72] la_data_out_core[73]
++ la_data_out_core[74] la_data_out_core[75] la_data_out_core[76] la_data_out_core[77]
++ la_data_out_core[78] la_data_out_core[79] la_data_out_core[7] la_data_out_core[80]
++ la_data_out_core[81] la_data_out_core[82] la_data_out_core[83] la_data_out_core[84]
++ la_data_out_core[85] la_data_out_core[86] la_data_out_core[87] la_data_out_core[88]
++ la_data_out_core[89] la_data_out_core[8] la_data_out_core[90] la_data_out_core[91]
++ la_data_out_core[92] la_data_out_core[93] la_data_out_core[94] la_data_out_core[95]
++ la_data_out_core[96] la_data_out_core[97] la_data_out_core[98] la_data_out_core[99]
++ la_data_out_core[9] la_data_out_mprj[0] la_data_out_mprj[100] la_data_out_mprj[101]
++ la_data_out_mprj[102] la_data_out_mprj[103] la_data_out_mprj[104] la_data_out_mprj[105]
++ la_data_out_mprj[106] la_data_out_mprj[107] la_data_out_mprj[108] la_data_out_mprj[109]
++ la_data_out_mprj[10] la_data_out_mprj[110] la_data_out_mprj[111] la_data_out_mprj[112]
++ la_data_out_mprj[113] la_data_out_mprj[114] la_data_out_mprj[115] la_data_out_mprj[116]
++ la_data_out_mprj[117] la_data_out_mprj[118] la_data_out_mprj[119] la_data_out_mprj[11]
++ la_data_out_mprj[120] la_data_out_mprj[121] la_data_out_mprj[122] la_data_out_mprj[123]
++ la_data_out_mprj[124] la_data_out_mprj[125] la_data_out_mprj[126] la_data_out_mprj[127]
++ la_data_out_mprj[12] la_data_out_mprj[13] la_data_out_mprj[14] la_data_out_mprj[15]
++ la_data_out_mprj[16] la_data_out_mprj[17] la_data_out_mprj[18] la_data_out_mprj[19]
++ la_data_out_mprj[1] la_data_out_mprj[20] la_data_out_mprj[21] la_data_out_mprj[22]
++ la_data_out_mprj[23] la_data_out_mprj[24] la_data_out_mprj[25] la_data_out_mprj[26]
++ la_data_out_mprj[27] la_data_out_mprj[28] la_data_out_mprj[29] la_data_out_mprj[2]
++ la_data_out_mprj[30] la_data_out_mprj[31] la_data_out_mprj[32] la_data_out_mprj[33]
++ la_data_out_mprj[34] la_data_out_mprj[35] la_data_out_mprj[36] la_data_out_mprj[37]
++ la_data_out_mprj[38] la_data_out_mprj[39] la_data_out_mprj[3] la_data_out_mprj[40]
++ la_data_out_mprj[41] la_data_out_mprj[42] la_data_out_mprj[43] la_data_out_mprj[44]
++ la_data_out_mprj[45] la_data_out_mprj[46] la_data_out_mprj[47] la_data_out_mprj[48]
++ la_data_out_mprj[49] la_data_out_mprj[4] la_data_out_mprj[50] la_data_out_mprj[51]
++ la_data_out_mprj[52] la_data_out_mprj[53] la_data_out_mprj[54] la_data_out_mprj[55]
++ la_data_out_mprj[56] la_data_out_mprj[57] la_data_out_mprj[58] la_data_out_mprj[59]
++ la_data_out_mprj[5] la_data_out_mprj[60] la_data_out_mprj[61] la_data_out_mprj[62]
++ la_data_out_mprj[63] la_data_out_mprj[64] la_data_out_mprj[65] la_data_out_mprj[66]
++ la_data_out_mprj[67] la_data_out_mprj[68] la_data_out_mprj[69] la_data_out_mprj[6]
++ la_data_out_mprj[70] la_data_out_mprj[71] la_data_out_mprj[72] la_data_out_mprj[73]
++ la_data_out_mprj[74] la_data_out_mprj[75] la_data_out_mprj[76] la_data_out_mprj[77]
++ la_data_out_mprj[78] la_data_out_mprj[79] la_data_out_mprj[7] la_data_out_mprj[80]
++ la_data_out_mprj[81] la_data_out_mprj[82] la_data_out_mprj[83] la_data_out_mprj[84]
++ la_data_out_mprj[85] la_data_out_mprj[86] la_data_out_mprj[87] la_data_out_mprj[88]
++ la_data_out_mprj[89] la_data_out_mprj[8] la_data_out_mprj[90] la_data_out_mprj[91]
++ la_data_out_mprj[92] la_data_out_mprj[93] la_data_out_mprj[94] la_data_out_mprj[95]
++ la_data_out_mprj[96] la_data_out_mprj[97] la_data_out_mprj[98] la_data_out_mprj[99]
++ la_data_out_mprj[9] la_iena_mprj[0] la_iena_mprj[100] la_iena_mprj[101] la_iena_mprj[102]
++ la_iena_mprj[103] la_iena_mprj[104] la_iena_mprj[105] la_iena_mprj[106] la_iena_mprj[107]
++ la_iena_mprj[108] la_iena_mprj[109] la_iena_mprj[10] la_iena_mprj[110] la_iena_mprj[111]
++ la_iena_mprj[112] la_iena_mprj[113] la_iena_mprj[114] la_iena_mprj[115] la_iena_mprj[116]
++ la_iena_mprj[117] la_iena_mprj[118] la_iena_mprj[119] la_iena_mprj[11] la_iena_mprj[120]
++ la_iena_mprj[121] la_iena_mprj[122] la_iena_mprj[123] la_iena_mprj[124] la_iena_mprj[125]
++ la_iena_mprj[126] la_iena_mprj[127] la_iena_mprj[12] la_iena_mprj[13] la_iena_mprj[14]
++ la_iena_mprj[15] la_iena_mprj[16] la_iena_mprj[17] la_iena_mprj[18] la_iena_mprj[19]
++ la_iena_mprj[1] la_iena_mprj[20] la_iena_mprj[21] la_iena_mprj[22] la_iena_mprj[23]
++ la_iena_mprj[24] la_iena_mprj[25] la_iena_mprj[26] la_iena_mprj[27] la_iena_mprj[28]
++ la_iena_mprj[29] la_iena_mprj[2] la_iena_mprj[30] la_iena_mprj[31] la_iena_mprj[32]
++ la_iena_mprj[33] la_iena_mprj[34] la_iena_mprj[35] la_iena_mprj[36] la_iena_mprj[37]
++ la_iena_mprj[38] la_iena_mprj[39] la_iena_mprj[3] la_iena_mprj[40] la_iena_mprj[41]
++ la_iena_mprj[42] la_iena_mprj[43] la_iena_mprj[44] la_iena_mprj[45] la_iena_mprj[46]
++ la_iena_mprj[47] la_iena_mprj[48] la_iena_mprj[49] la_iena_mprj[4] la_iena_mprj[50]
++ la_iena_mprj[51] la_iena_mprj[52] la_iena_mprj[53] la_iena_mprj[54] la_iena_mprj[55]
++ la_iena_mprj[56] la_iena_mprj[57] la_iena_mprj[58] la_iena_mprj[59] la_iena_mprj[5]
++ la_iena_mprj[60] la_iena_mprj[61] la_iena_mprj[62] la_iena_mprj[63] la_iena_mprj[64]
++ la_iena_mprj[65] la_iena_mprj[66] la_iena_mprj[67] la_iena_mprj[68] la_iena_mprj[69]
++ la_iena_mprj[6] la_iena_mprj[70] la_iena_mprj[71] la_iena_mprj[72] la_iena_mprj[73]
++ la_iena_mprj[74] la_iena_mprj[75] la_iena_mprj[76] la_iena_mprj[77] la_iena_mprj[78]
++ la_iena_mprj[79] la_iena_mprj[7] la_iena_mprj[80] la_iena_mprj[81] la_iena_mprj[82]
++ la_iena_mprj[83] la_iena_mprj[84] la_iena_mprj[85] la_iena_mprj[86] la_iena_mprj[87]
++ la_iena_mprj[88] la_iena_mprj[89] la_iena_mprj[8] la_iena_mprj[90] la_iena_mprj[91]
++ la_iena_mprj[92] la_iena_mprj[93] la_iena_mprj[94] la_iena_mprj[95] la_iena_mprj[96]
++ la_iena_mprj[97] la_iena_mprj[98] la_iena_mprj[99] la_iena_mprj[9] la_oenb_core[0]
++ la_oenb_core[100] la_oenb_core[101] la_oenb_core[102] la_oenb_core[103] la_oenb_core[104]
++ la_oenb_core[105] la_oenb_core[106] la_oenb_core[107] la_oenb_core[108] la_oenb_core[109]
++ la_oenb_core[10] la_oenb_core[110] la_oenb_core[111] la_oenb_core[112] la_oenb_core[113]
++ la_oenb_core[114] la_oenb_core[115] la_oenb_core[116] la_oenb_core[117] la_oenb_core[118]
++ la_oenb_core[119] la_oenb_core[11] la_oenb_core[120] la_oenb_core[121] la_oenb_core[122]
++ la_oenb_core[123] la_oenb_core[124] la_oenb_core[125] la_oenb_core[126] la_oenb_core[127]
++ la_oenb_core[12] la_oenb_core[13] la_oenb_core[14] la_oenb_core[15] la_oenb_core[16]
++ la_oenb_core[17] la_oenb_core[18] la_oenb_core[19] la_oenb_core[1] la_oenb_core[20]
++ la_oenb_core[21] la_oenb_core[22] la_oenb_core[23] la_oenb_core[24] la_oenb_core[25]
++ la_oenb_core[26] la_oenb_core[27] la_oenb_core[28] la_oenb_core[29] la_oenb_core[2]
++ la_oenb_core[30] la_oenb_core[31] la_oenb_core[32] la_oenb_core[33] la_oenb_core[34]
++ la_oenb_core[35] la_oenb_core[36] la_oenb_core[37] la_oenb_core[38] la_oenb_core[39]
++ la_oenb_core[3] la_oenb_core[40] la_oenb_core[41] la_oenb_core[42] la_oenb_core[43]
++ la_oenb_core[44] la_oenb_core[45] la_oenb_core[46] la_oenb_core[47] la_oenb_core[48]
++ la_oenb_core[49] la_oenb_core[4] la_oenb_core[50] la_oenb_core[51] la_oenb_core[52]
++ la_oenb_core[53] la_oenb_core[54] la_oenb_core[55] la_oenb_core[56] la_oenb_core[57]
++ la_oenb_core[58] la_oenb_core[59] la_oenb_core[5] la_oenb_core[60] la_oenb_core[61]
++ la_oenb_core[62] la_oenb_core[63] la_oenb_core[64] la_oenb_core[65] la_oenb_core[66]
++ la_oenb_core[67] la_oenb_core[68] la_oenb_core[69] la_oenb_core[6] la_oenb_core[70]
++ la_oenb_core[71] la_oenb_core[72] la_oenb_core[73] la_oenb_core[74] la_oenb_core[75]
++ la_oenb_core[76] la_oenb_core[77] la_oenb_core[78] la_oenb_core[79] la_oenb_core[7]
++ la_oenb_core[80] la_oenb_core[81] la_oenb_core[82] la_oenb_core[83] la_oenb_core[84]
++ la_oenb_core[85] la_oenb_core[86] la_oenb_core[87] la_oenb_core[88] la_oenb_core[89]
++ la_oenb_core[8] la_oenb_core[90] la_oenb_core[91] la_oenb_core[92] la_oenb_core[93]
++ la_oenb_core[94] la_oenb_core[95] la_oenb_core[96] la_oenb_core[97] la_oenb_core[98]
++ la_oenb_core[99] la_oenb_core[9] la_oenb_mprj[0] la_oenb_mprj[100] la_oenb_mprj[101]
++ la_oenb_mprj[102] la_oenb_mprj[103] la_oenb_mprj[104] la_oenb_mprj[105] la_oenb_mprj[106]
++ la_oenb_mprj[107] la_oenb_mprj[108] la_oenb_mprj[109] la_oenb_mprj[10] la_oenb_mprj[110]
++ la_oenb_mprj[111] la_oenb_mprj[112] la_oenb_mprj[113] la_oenb_mprj[114] la_oenb_mprj[115]
++ la_oenb_mprj[116] la_oenb_mprj[117] la_oenb_mprj[118] la_oenb_mprj[119] la_oenb_mprj[11]
++ la_oenb_mprj[120] la_oenb_mprj[121] la_oenb_mprj[122] la_oenb_mprj[123] la_oenb_mprj[124]
++ la_oenb_mprj[125] la_oenb_mprj[126] la_oenb_mprj[127] la_oenb_mprj[12] la_oenb_mprj[13]
++ la_oenb_mprj[14] la_oenb_mprj[15] la_oenb_mprj[16] la_oenb_mprj[17] la_oenb_mprj[18]
++ la_oenb_mprj[19] la_oenb_mprj[1] la_oenb_mprj[20] la_oenb_mprj[21] la_oenb_mprj[22]
++ la_oenb_mprj[23] la_oenb_mprj[24] la_oenb_mprj[25] la_oenb_mprj[26] la_oenb_mprj[27]
++ la_oenb_mprj[28] la_oenb_mprj[29] la_oenb_mprj[2] la_oenb_mprj[30] la_oenb_mprj[31]
++ la_oenb_mprj[32] la_oenb_mprj[33] la_oenb_mprj[34] la_oenb_mprj[35] la_oenb_mprj[36]
++ la_oenb_mprj[37] la_oenb_mprj[38] la_oenb_mprj[39] la_oenb_mprj[3] la_oenb_mprj[40]
++ la_oenb_mprj[41] la_oenb_mprj[42] la_oenb_mprj[43] la_oenb_mprj[44] la_oenb_mprj[45]
++ la_oenb_mprj[46] la_oenb_mprj[47] la_oenb_mprj[48] la_oenb_mprj[49] la_oenb_mprj[4]
++ la_oenb_mprj[50] la_oenb_mprj[51] la_oenb_mprj[52] la_oenb_mprj[53] la_oenb_mprj[54]
++ la_oenb_mprj[55] la_oenb_mprj[56] la_oenb_mprj[57] la_oenb_mprj[58] la_oenb_mprj[59]
++ la_oenb_mprj[5] la_oenb_mprj[60] la_oenb_mprj[61] la_oenb_mprj[62] la_oenb_mprj[63]
++ la_oenb_mprj[64] la_oenb_mprj[65] la_oenb_mprj[66] la_oenb_mprj[67] la_oenb_mprj[68]
++ la_oenb_mprj[69] la_oenb_mprj[6] la_oenb_mprj[70] la_oenb_mprj[71] la_oenb_mprj[72]
++ la_oenb_mprj[73] la_oenb_mprj[74] la_oenb_mprj[75] la_oenb_mprj[76] la_oenb_mprj[77]
++ la_oenb_mprj[78] la_oenb_mprj[79] la_oenb_mprj[7] la_oenb_mprj[80] la_oenb_mprj[81]
++ la_oenb_mprj[82] la_oenb_mprj[83] la_oenb_mprj[84] la_oenb_mprj[85] la_oenb_mprj[86]
++ la_oenb_mprj[87] la_oenb_mprj[88] la_oenb_mprj[89] la_oenb_mprj[8] la_oenb_mprj[90]
++ la_oenb_mprj[91] la_oenb_mprj[92] la_oenb_mprj[93] la_oenb_mprj[94] la_oenb_mprj[95]
++ la_oenb_mprj[96] la_oenb_mprj[97] la_oenb_mprj[98] la_oenb_mprj[99] la_oenb_mprj[9]
++ mprj_ack_i_core mprj_ack_i_user mprj_adr_o_core[0] mprj_adr_o_core[10] mprj_adr_o_core[11]
++ mprj_adr_o_core[12] mprj_adr_o_core[13] mprj_adr_o_core[14] mprj_adr_o_core[15]
++ mprj_adr_o_core[16] mprj_adr_o_core[17] mprj_adr_o_core[18] mprj_adr_o_core[19]
++ mprj_adr_o_core[1] mprj_adr_o_core[20] mprj_adr_o_core[21] mprj_adr_o_core[22] mprj_adr_o_core[23]
++ mprj_adr_o_core[24] mprj_adr_o_core[25] mprj_adr_o_core[26] mprj_adr_o_core[27]
++ mprj_adr_o_core[28] mprj_adr_o_core[29] mprj_adr_o_core[2] mprj_adr_o_core[30] mprj_adr_o_core[31]
++ mprj_adr_o_core[3] mprj_adr_o_core[4] mprj_adr_o_core[5] mprj_adr_o_core[6] mprj_adr_o_core[7]
++ mprj_adr_o_core[8] mprj_adr_o_core[9] mprj_adr_o_user[0] mprj_adr_o_user[10] mprj_adr_o_user[11]
++ mprj_adr_o_user[12] mprj_adr_o_user[13] mprj_adr_o_user[14] mprj_adr_o_user[15]
++ mprj_adr_o_user[16] mprj_adr_o_user[17] mprj_adr_o_user[18] mprj_adr_o_user[19]
++ mprj_adr_o_user[1] mprj_adr_o_user[20] mprj_adr_o_user[21] mprj_adr_o_user[22] mprj_adr_o_user[23]
++ mprj_adr_o_user[24] mprj_adr_o_user[25] mprj_adr_o_user[26] mprj_adr_o_user[27]
++ mprj_adr_o_user[28] mprj_adr_o_user[29] mprj_adr_o_user[2] mprj_adr_o_user[30] mprj_adr_o_user[31]
++ mprj_adr_o_user[3] mprj_adr_o_user[4] mprj_adr_o_user[5] mprj_adr_o_user[6] mprj_adr_o_user[7]
++ mprj_adr_o_user[8] mprj_adr_o_user[9] mprj_cyc_o_core mprj_cyc_o_user mprj_dat_i_core[0]
++ mprj_dat_i_core[10] mprj_dat_i_core[11] mprj_dat_i_core[12] mprj_dat_i_core[13]
++ mprj_dat_i_core[14] mprj_dat_i_core[15] mprj_dat_i_core[16] mprj_dat_i_core[17]
++ mprj_dat_i_core[18] mprj_dat_i_core[19] mprj_dat_i_core[1] mprj_dat_i_core[20] mprj_dat_i_core[21]
++ mprj_dat_i_core[22] mprj_dat_i_core[23] mprj_dat_i_core[24] mprj_dat_i_core[25]
++ mprj_dat_i_core[26] mprj_dat_i_core[27] mprj_dat_i_core[28] mprj_dat_i_core[29]
++ mprj_dat_i_core[2] mprj_dat_i_core[30] mprj_dat_i_core[31] mprj_dat_i_core[3] mprj_dat_i_core[4]
++ mprj_dat_i_core[5] mprj_dat_i_core[6] mprj_dat_i_core[7] mprj_dat_i_core[8] mprj_dat_i_core[9]
++ mprj_dat_i_user[0] mprj_dat_i_user[10] mprj_dat_i_user[11] mprj_dat_i_user[12] mprj_dat_i_user[13]
++ mprj_dat_i_user[14] mprj_dat_i_user[15] mprj_dat_i_user[16] mprj_dat_i_user[17]
++ mprj_dat_i_user[18] mprj_dat_i_user[19] mprj_dat_i_user[1] mprj_dat_i_user[20] mprj_dat_i_user[21]
++ mprj_dat_i_user[22] mprj_dat_i_user[23] mprj_dat_i_user[24] mprj_dat_i_user[25]
++ mprj_dat_i_user[26] mprj_dat_i_user[27] mprj_dat_i_user[28] mprj_dat_i_user[29]
++ mprj_dat_i_user[2] mprj_dat_i_user[30] mprj_dat_i_user[31] mprj_dat_i_user[3] mprj_dat_i_user[4]
++ mprj_dat_i_user[5] mprj_dat_i_user[6] mprj_dat_i_user[7] mprj_dat_i_user[8] mprj_dat_i_user[9]
++ mprj_dat_o_core[0] mprj_dat_o_core[10] mprj_dat_o_core[11] mprj_dat_o_core[12] mprj_dat_o_core[13]
++ mprj_dat_o_core[14] mprj_dat_o_core[15] mprj_dat_o_core[16] mprj_dat_o_core[17]
++ mprj_dat_o_core[18] mprj_dat_o_core[19] mprj_dat_o_core[1] mprj_dat_o_core[20] mprj_dat_o_core[21]
++ mprj_dat_o_core[22] mprj_dat_o_core[23] mprj_dat_o_core[24] mprj_dat_o_core[25]
++ mprj_dat_o_core[26] mprj_dat_o_core[27] mprj_dat_o_core[28] mprj_dat_o_core[29]
++ mprj_dat_o_core[2] mprj_dat_o_core[30] mprj_dat_o_core[31] mprj_dat_o_core[3] mprj_dat_o_core[4]
++ mprj_dat_o_core[5] mprj_dat_o_core[6] mprj_dat_o_core[7] mprj_dat_o_core[8] mprj_dat_o_core[9]
++ mprj_dat_o_user[0] mprj_dat_o_user[10] mprj_dat_o_user[11] mprj_dat_o_user[12] mprj_dat_o_user[13]
++ mprj_dat_o_user[14] mprj_dat_o_user[15] mprj_dat_o_user[16] mprj_dat_o_user[17]
++ mprj_dat_o_user[18] mprj_dat_o_user[19] mprj_dat_o_user[1] mprj_dat_o_user[20] mprj_dat_o_user[21]
++ mprj_dat_o_user[22] mprj_dat_o_user[23] mprj_dat_o_user[24] mprj_dat_o_user[25]
++ mprj_dat_o_user[26] mprj_dat_o_user[27] mprj_dat_o_user[28] mprj_dat_o_user[29]
++ mprj_dat_o_user[2] mprj_dat_o_user[30] mprj_dat_o_user[31] mprj_dat_o_user[3] mprj_dat_o_user[4]
++ mprj_dat_o_user[5] mprj_dat_o_user[6] mprj_dat_o_user[7] mprj_dat_o_user[8] mprj_dat_o_user[9]
++ mprj_iena_wb mprj_sel_o_core[0] mprj_sel_o_core[1] mprj_sel_o_core[2] mprj_sel_o_core[3]
++ mprj_sel_o_user[0] mprj_sel_o_user[1] mprj_sel_o_user[2] mprj_sel_o_user[3] mprj_stb_o_core
++ mprj_stb_o_user mprj_we_o_core mprj_we_o_user user1_vcc_powergood user1_vdd_powergood
++ user2_vcc_powergood user2_vdd_powergood user_clock user_clock2 user_irq[0] user_irq[1]
++ user_irq[2] user_irq_core[0] user_irq_core[1] user_irq_core[2] user_irq_ena[0] user_irq_ena[1]
++ user_irq_ena[2] user_reset vccd vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd vssd1 vssd2
+.ends
+
+* Black-box entry subcircuit for xres_buf abstract view
+.subckt xres_buf A X VPWR VGND LVPWR LVGND
+.ends
+
+* Black-box entry subcircuit for user_project_wrapper abstract view
+.subckt user_project_wrapper analog_io[0] analog_io[10] analog_io[11] analog_io[12]
++ analog_io[13] analog_io[14] analog_io[15] analog_io[16] analog_io[17] analog_io[18]
++ analog_io[19] analog_io[1] analog_io[20] analog_io[21] analog_io[22] analog_io[23]
++ analog_io[24] analog_io[25] analog_io[26] analog_io[27] analog_io[28] analog_io[2]
++ analog_io[3] analog_io[4] analog_io[5] analog_io[6] analog_io[7] analog_io[8] analog_io[9]
++ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
++ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
++ io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30] io_in[31] io_in[32] io_in[33]
++ io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7]
++ io_in[8] io_in[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14]
++ io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21]
++ io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[27] io_oeb[28] io_oeb[29]
++ io_oeb[2] io_oeb[30] io_oeb[31] io_oeb[32] io_oeb[33] io_oeb[34] io_oeb[35] io_oeb[36]
++ io_oeb[37] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9]
++ io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16]
++ io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23]
++ io_out[24] io_out[25] io_out[26] io_out[27] io_out[28] io_out[29] io_out[2] io_out[30]
++ io_out[31] io_out[32] io_out[33] io_out[34] io_out[35] io_out[36] io_out[37] io_out[3]
++ io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100]
++ la_data_in[101] la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105]
++ la_data_in[106] la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110]
++ la_data_in[111] la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115]
++ la_data_in[116] la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120]
++ la_data_in[121] la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125]
++ la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15]
++ la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20]
++ la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26]
++ la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31]
++ la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37]
++ la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42]
++ la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48]
++ la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53]
++ la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59]
++ la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64]
++ la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6]
++ la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75]
++ la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80]
++ la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86]
++ la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91]
++ la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97]
++ la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101]
++ la_data_out[102] la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106]
++ la_data_out[107] la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110]
++ la_data_out[111] la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115]
++ la_data_out[116] la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11]
++ la_data_out[120] la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124]
++ la_data_out[125] la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13]
++ la_data_out[14] la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18]
++ la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23]
++ la_data_out[24] la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28]
++ la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33]
++ la_data_out[34] la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38]
++ la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43]
++ la_data_out[44] la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48]
++ la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53]
++ la_data_out[54] la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58]
++ la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63]
++ la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68]
++ la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73]
++ la_data_out[74] la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78]
++ la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83]
++ la_data_out[84] la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88]
++ la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93]
++ la_data_out[94] la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98]
++ la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102]
++ la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109]
++ la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115]
++ la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121]
++ la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12]
++ la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19]
++ la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25]
++ la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31]
++ la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38]
++ la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44]
++ la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50]
++ la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57]
++ la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63]
++ la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6]
++ la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76]
++ la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82]
++ la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89]
++ la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95]
++ la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0]
++ user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13]
++ wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19]
++ wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24]
++ wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2]
++ wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6]
++ wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11]
++ wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17]
++ wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22]
++ wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28]
++ wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4]
++ wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10]
++ wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16]
++ wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21]
++ wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27]
++ wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3]
++ wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0]
++ wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+.ends
+
+* Black-box entry subcircuit for housekeeping abstract view
+.subckt housekeeping VGND VPWR debug_in debug_mode debug_oeb debug_out irq[0] irq[1]
++ irq[2] mask_rev_in[0] mask_rev_in[10] mask_rev_in[11] mask_rev_in[12] mask_rev_in[13]
++ mask_rev_in[14] mask_rev_in[15] mask_rev_in[16] mask_rev_in[17] mask_rev_in[18]
++ mask_rev_in[19] mask_rev_in[1] mask_rev_in[20] mask_rev_in[21] mask_rev_in[22] mask_rev_in[23]
++ mask_rev_in[24] mask_rev_in[25] mask_rev_in[26] mask_rev_in[27] mask_rev_in[28]
++ mask_rev_in[29] mask_rev_in[2] mask_rev_in[30] mask_rev_in[31] mask_rev_in[3] mask_rev_in[4]
++ mask_rev_in[5] mask_rev_in[6] mask_rev_in[7] mask_rev_in[8] mask_rev_in[9] mgmt_gpio_in[0]
++ mgmt_gpio_in[10] mgmt_gpio_in[11] mgmt_gpio_in[12] mgmt_gpio_in[13] mgmt_gpio_in[14]
++ mgmt_gpio_in[15] mgmt_gpio_in[16] mgmt_gpio_in[17] mgmt_gpio_in[18] mgmt_gpio_in[19]
++ mgmt_gpio_in[1] mgmt_gpio_in[20] mgmt_gpio_in[21] mgmt_gpio_in[22] mgmt_gpio_in[23]
++ mgmt_gpio_in[24] mgmt_gpio_in[25] mgmt_gpio_in[26] mgmt_gpio_in[27] mgmt_gpio_in[28]
++ mgmt_gpio_in[29] mgmt_gpio_in[2] mgmt_gpio_in[30] mgmt_gpio_in[31] mgmt_gpio_in[32]
++ mgmt_gpio_in[33] mgmt_gpio_in[34] mgmt_gpio_in[35] mgmt_gpio_in[36] mgmt_gpio_in[37]
++ mgmt_gpio_in[3] mgmt_gpio_in[4] mgmt_gpio_in[5] mgmt_gpio_in[6] mgmt_gpio_in[7]
++ mgmt_gpio_in[8] mgmt_gpio_in[9] mgmt_gpio_oeb[0] mgmt_gpio_oeb[10] mgmt_gpio_oeb[11]
++ mgmt_gpio_oeb[12] mgmt_gpio_oeb[13] mgmt_gpio_oeb[14] mgmt_gpio_oeb[15] mgmt_gpio_oeb[16]
++ mgmt_gpio_oeb[17] mgmt_gpio_oeb[18] mgmt_gpio_oeb[19] mgmt_gpio_oeb[1] mgmt_gpio_oeb[20]
++ mgmt_gpio_oeb[21] mgmt_gpio_oeb[22] mgmt_gpio_oeb[23] mgmt_gpio_oeb[24] mgmt_gpio_oeb[25]
++ mgmt_gpio_oeb[26] mgmt_gpio_oeb[27] mgmt_gpio_oeb[28] mgmt_gpio_oeb[29] mgmt_gpio_oeb[2]
++ mgmt_gpio_oeb[30] mgmt_gpio_oeb[31] mgmt_gpio_oeb[32] mgmt_gpio_oeb[33] mgmt_gpio_oeb[34]
++ mgmt_gpio_oeb[35] mgmt_gpio_oeb[36] mgmt_gpio_oeb[37] mgmt_gpio_oeb[3] mgmt_gpio_oeb[4]
++ mgmt_gpio_oeb[5] mgmt_gpio_oeb[6] mgmt_gpio_oeb[7] mgmt_gpio_oeb[8] mgmt_gpio_oeb[9]
++ mgmt_gpio_out[0] mgmt_gpio_out[10] mgmt_gpio_out[11] mgmt_gpio_out[12] mgmt_gpio_out[13]
++ mgmt_gpio_out[14] mgmt_gpio_out[15] mgmt_gpio_out[16] mgmt_gpio_out[17] mgmt_gpio_out[18]
++ mgmt_gpio_out[19] mgmt_gpio_out[1] mgmt_gpio_out[20] mgmt_gpio_out[21] mgmt_gpio_out[22]
++ mgmt_gpio_out[23] mgmt_gpio_out[24] mgmt_gpio_out[25] mgmt_gpio_out[26] mgmt_gpio_out[27]
++ mgmt_gpio_out[28] mgmt_gpio_out[29] mgmt_gpio_out[2] mgmt_gpio_out[30] mgmt_gpio_out[31]
++ mgmt_gpio_out[32] mgmt_gpio_out[33] mgmt_gpio_out[34] mgmt_gpio_out[35] mgmt_gpio_out[36]
++ mgmt_gpio_out[37] mgmt_gpio_out[3] mgmt_gpio_out[4] mgmt_gpio_out[5] mgmt_gpio_out[6]
++ mgmt_gpio_out[7] mgmt_gpio_out[8] mgmt_gpio_out[9] pad_flash_clk pad_flash_clk_oeb
++ pad_flash_csb pad_flash_csb_oeb pad_flash_io0_di pad_flash_io0_do pad_flash_io0_ieb
++ pad_flash_io0_oeb pad_flash_io1_di pad_flash_io1_do pad_flash_io1_ieb pad_flash_io1_oeb
++ pll90_sel[0] pll90_sel[1] pll90_sel[2] pll_bypass pll_dco_ena pll_div[0] pll_div[1]
++ pll_div[2] pll_div[3] pll_div[4] pll_ena pll_sel[0] pll_sel[1] pll_sel[2] pll_trim[0]
++ pll_trim[10] pll_trim[11] pll_trim[12] pll_trim[13] pll_trim[14] pll_trim[15] pll_trim[16]
++ pll_trim[17] pll_trim[18] pll_trim[19] pll_trim[1] pll_trim[20] pll_trim[21] pll_trim[22]
++ pll_trim[23] pll_trim[24] pll_trim[25] pll_trim[2] pll_trim[3] pll_trim[4] pll_trim[5]
++ pll_trim[6] pll_trim[7] pll_trim[8] pll_trim[9] porb pwr_ctrl_out[0] pwr_ctrl_out[1]
++ pwr_ctrl_out[2] pwr_ctrl_out[3] qspi_enabled reset ser_rx ser_tx serial_clock serial_data_1
++ serial_data_2 serial_load serial_resetn spi_csb spi_enabled spi_sck spi_sdi spi_sdo
++ spi_sdoenb spimemio_flash_clk spimemio_flash_csb spimemio_flash_io0_di spimemio_flash_io0_do
++ spimemio_flash_io0_oeb spimemio_flash_io1_di spimemio_flash_io1_do spimemio_flash_io1_oeb
++ spimemio_flash_io2_di spimemio_flash_io2_do spimemio_flash_io2_oeb spimemio_flash_io3_di
++ spimemio_flash_io3_do spimemio_flash_io3_oeb sram_ro_addr[0] sram_ro_addr[1] sram_ro_addr[2]
++ sram_ro_addr[3] sram_ro_addr[4] sram_ro_addr[5] sram_ro_addr[6] sram_ro_addr[7]
++ sram_ro_clk sram_ro_csb sram_ro_data[0] sram_ro_data[10] sram_ro_data[11] sram_ro_data[12]
++ sram_ro_data[13] sram_ro_data[14] sram_ro_data[15] sram_ro_data[16] sram_ro_data[17]
++ sram_ro_data[18] sram_ro_data[19] sram_ro_data[1] sram_ro_data[20] sram_ro_data[21]
++ sram_ro_data[22] sram_ro_data[23] sram_ro_data[24] sram_ro_data[25] sram_ro_data[26]
++ sram_ro_data[27] sram_ro_data[28] sram_ro_data[29] sram_ro_data[2] sram_ro_data[30]
++ sram_ro_data[31] sram_ro_data[3] sram_ro_data[4] sram_ro_data[5] sram_ro_data[6]
++ sram_ro_data[7] sram_ro_data[8] sram_ro_data[9] trap uart_enabled user_clock usr1_vcc_pwrgood
++ usr1_vdd_pwrgood usr2_vcc_pwrgood usr2_vdd_pwrgood wb_ack_o wb_adr_i[0] wb_adr_i[10]
++ wb_adr_i[11] wb_adr_i[12] wb_adr_i[13] wb_adr_i[14] wb_adr_i[15] wb_adr_i[16] wb_adr_i[17]
++ wb_adr_i[18] wb_adr_i[19] wb_adr_i[1] wb_adr_i[20] wb_adr_i[21] wb_adr_i[22] wb_adr_i[23]
++ wb_adr_i[24] wb_adr_i[25] wb_adr_i[26] wb_adr_i[27] wb_adr_i[28] wb_adr_i[29] wb_adr_i[2]
++ wb_adr_i[30] wb_adr_i[31] wb_adr_i[3] wb_adr_i[4] wb_adr_i[5] wb_adr_i[6] wb_adr_i[7]
++ wb_adr_i[8] wb_adr_i[9] wb_clk_i wb_cyc_i wb_dat_i[0] wb_dat_i[10] wb_dat_i[11]
++ wb_dat_i[12] wb_dat_i[13] wb_dat_i[14] wb_dat_i[15] wb_dat_i[16] wb_dat_i[17] wb_dat_i[18]
++ wb_dat_i[19] wb_dat_i[1] wb_dat_i[20] wb_dat_i[21] wb_dat_i[22] wb_dat_i[23] wb_dat_i[24]
++ wb_dat_i[25] wb_dat_i[26] wb_dat_i[27] wb_dat_i[28] wb_dat_i[29] wb_dat_i[2] wb_dat_i[30]
++ wb_dat_i[31] wb_dat_i[3] wb_dat_i[4] wb_dat_i[5] wb_dat_i[6] wb_dat_i[7] wb_dat_i[8]
++ wb_dat_i[9] wb_dat_o[0] wb_dat_o[10] wb_dat_o[11] wb_dat_o[12] wb_dat_o[13] wb_dat_o[14]
++ wb_dat_o[15] wb_dat_o[16] wb_dat_o[17] wb_dat_o[18] wb_dat_o[19] wb_dat_o[1] wb_dat_o[20]
++ wb_dat_o[21] wb_dat_o[22] wb_dat_o[23] wb_dat_o[24] wb_dat_o[25] wb_dat_o[26] wb_dat_o[27]
++ wb_dat_o[28] wb_dat_o[29] wb_dat_o[2] wb_dat_o[30] wb_dat_o[31] wb_dat_o[3] wb_dat_o[4]
++ wb_dat_o[5] wb_dat_o[6] wb_dat_o[7] wb_dat_o[8] wb_dat_o[9] wb_rstn_i wb_sel_i[0]
++ wb_sel_i[1] wb_sel_i[2] wb_sel_i[3] wb_stb_i wb_we_i
+.ends
+
+.subckt caravel clock flash_clk flash_csb flash_io0 flash_io1 gpio mprj_io[0] mprj_io[10]
++ mprj_io[11] mprj_io[12] mprj_io[13] mprj_io[14] mprj_io[15] mprj_io[16] mprj_io[17]
++ mprj_io[18] mprj_io[19] mprj_io[1] mprj_io[20] mprj_io[21] mprj_io[22] mprj_io[23]
++ mprj_io[24] mprj_io[25] mprj_io[26] mprj_io[27] mprj_io[28] mprj_io[29] mprj_io[2]
++ mprj_io[30] mprj_io[31] mprj_io[32] mprj_io[33] mprj_io[34] mprj_io[35] mprj_io[36]
++ mprj_io[37] mprj_io[3] mprj_io[4] mprj_io[5] mprj_io[6] mprj_io[7] mprj_io[8] mprj_io[9]
++ resetb vccd vccd1 vccd2 vdda vdda1 vdda1_2 vdda2 vddio vddio_2 vssa vssa1 vssa1_2
++ vssa2 vssd vssd1 vssd2 vssio vssio_2
+Xgpio_control_in_2\[0\] gpio_19_defaults/gpio_defaults[0] gpio_19_defaults/gpio_defaults[10]
++ gpio_19_defaults/gpio_defaults[11] gpio_19_defaults/gpio_defaults[12] gpio_19_defaults/gpio_defaults[1]
++ gpio_19_defaults/gpio_defaults[2] gpio_19_defaults/gpio_defaults[3] gpio_19_defaults/gpio_defaults[4]
++ gpio_19_defaults/gpio_defaults[5] gpio_19_defaults/gpio_defaults[6] gpio_19_defaults/gpio_defaults[7]
++ gpio_19_defaults/gpio_defaults[8] gpio_19_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[19]
++ gpio_control_in_2\[0\]/one housekeeping/mgmt_gpio_in[19] gpio_control_in_2\[0\]/one
++ padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_in[19] padframe/mprj_io_inp_dis[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_oeb[19] padframe/mprj_io_slow_sel[19]
++ padframe/mprj_io_vtrip_sel[19] housekeeping/serial_resetn gpio_control_in_2\[1\]/resetn
++ housekeeping/serial_clock gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[0\]/serial_data_in
++ gpio_control_in_2\[0\]/serial_data_out housekeeping/serial_load gpio_control_in_2\[1\]/serial_load
++ mprj/io_in[19] mprj/io_oeb[19] mprj/io_out[19] gpio_control_in_2\[0\]/vccd gpio_control_in_2\[0\]/vccd1
++ gpio_control_in_2\[0\]/vssd gpio_control_in_2\[0\]/vssd1 gpio_control_in_2\[0\]/zero
++ gpio_control_block
+Xgpio_22_defaults gpio_22_defaults/VGND gpio_22_defaults/VPWR gpio_22_defaults/gpio_defaults[0]
++ gpio_22_defaults/gpio_defaults[10] gpio_22_defaults/gpio_defaults[11] gpio_22_defaults/gpio_defaults[12]
++ gpio_22_defaults/gpio_defaults[1] gpio_22_defaults/gpio_defaults[2] gpio_22_defaults/gpio_defaults[3]
++ gpio_22_defaults/gpio_defaults[4] gpio_22_defaults/gpio_defaults[5] gpio_22_defaults/gpio_defaults[6]
++ gpio_22_defaults/gpio_defaults[7] gpio_22_defaults/gpio_defaults[8] gpio_22_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[6\] gpio_14_defaults/gpio_defaults[0] gpio_14_defaults/gpio_defaults[2]
++ gpio_14_defaults/gpio_defaults[1] gpio_14_defaults/gpio_defaults[0] gpio_14_defaults/gpio_defaults[1]
++ gpio_14_defaults/gpio_defaults[2] gpio_14_defaults/gpio_defaults[9] gpio_14_defaults/gpio_defaults[8]
++ gpio_14_defaults/gpio_defaults[7] gpio_14_defaults/gpio_defaults[6] gpio_14_defaults/gpio_defaults[7]
++ gpio_14_defaults/gpio_defaults[8] gpio_14_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[14]
++ gpio_control_in_1\[6\]/one housekeeping/mgmt_gpio_in[14] gpio_control_in_1\[6\]/one
++ padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_in[14] padframe/mprj_io_inp_dis[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_oeb[14] padframe/mprj_io_slow_sel[14]
++ padframe/mprj_io_vtrip_sel[14] gpio_control_in_1\[6\]/resetn gpio_control_in_1\[7\]/resetn
++ gpio_control_in_1\[6\]/serial_clock gpio_control_in_1\[7\]/serial_clock gpio_control_in_1\[6\]/serial_data_in
++ gpio_control_in_1\[7\]/serial_data_in gpio_control_in_1\[6\]/serial_load gpio_control_in_1\[7\]/serial_load
++ mprj/io_in[14] mprj/io_oeb[14] mprj/io_out[14] gpio_control_in_1\[6\]/vccd gpio_control_in_1\[6\]/vccd1
++ gpio_control_in_1\[6\]/vssd gpio_control_in_1\[6\]/vssd1 gpio_control_in_1\[6\]/zero
++ gpio_control_block
+Xpll pll/VGND pll/VPWR pll/clockp[0] pll/clockp[1] pll/dco pll/div[0] pll/div[1] pll/div[2]
++ pll/div[3] pll/div[4] pll/enable pll/ext_trim[0] pll/ext_trim[10] pll/ext_trim[11]
++ pll/ext_trim[12] pll/ext_trim[13] pll/ext_trim[14] pll/ext_trim[15] pll/ext_trim[16]
++ pll/ext_trim[17] pll/ext_trim[18] pll/ext_trim[19] pll/ext_trim[1] pll/ext_trim[20]
++ pll/ext_trim[21] pll/ext_trim[22] pll/ext_trim[23] pll/ext_trim[24] pll/ext_trim[25]
++ pll/ext_trim[2] pll/ext_trim[3] pll/ext_trim[4] pll/ext_trim[5] pll/ext_trim[6]
++ pll/ext_trim[7] pll/ext_trim[8] pll/ext_trim[9] pll/osc pll/resetb digital_pll
+Xpadframe clock pll/osc por/por_l flash_clk padframe/flash_clk_core padframe/flash_clk_ieb_core
++ padframe/flash_clk_oeb_core flash_csb padframe/flash_csb_core padframe/flash_csb_ieb_core
++ padframe/flash_csb_oeb_core flash_io0 padframe/flash_io0_di_core padframe/flash_io0_do_core
++ padframe/flash_io0_ieb_core padframe/flash_io0_oeb_core flash_io1 padframe/flash_io1_di_core
++ padframe/flash_io1_do_core padframe/flash_io1_ieb_core padframe/flash_io1_oeb_core
++ gpio soc/gpio_in_pad soc/gpio_inenb_pad soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad
++ soc/gpio_outenb_pad vccd vdda vddio vddio_2 vssa vssd vssio vssio_2 mprj_io[0] padframe/mprj_io_analog_en[0]
++ padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0] padframe/mprj_io_dm[0]
++ padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0] padframe/mprj_io_ib_mode_sel[0]
++ padframe/mprj_io_inp_dis[0] padframe/mprj_io_oeb[0] padframe/mprj_io_out[0] padframe/mprj_io_slow_sel[0]
++ padframe/mprj_io_vtrip_sel[0] padframe/mprj_io_in[0] mprj/analog_io[3] mprj_io[10]
++ padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10]
++ padframe/mprj_io_dm[30] padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_inp_dis[10] padframe/mprj_io_oeb[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_slow_sel[10] padframe/mprj_io_vtrip_sel[10]
++ padframe/mprj_io_in[10] mprj/analog_io[4] mprj_io[11] padframe/mprj_io_analog_en[11]
++ padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11] padframe/mprj_io_dm[33]
++ padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11] padframe/mprj_io_ib_mode_sel[11]
++ padframe/mprj_io_inp_dis[11] padframe/mprj_io_oeb[11] padframe/mprj_io_out[11] padframe/mprj_io_slow_sel[11]
++ padframe/mprj_io_vtrip_sel[11] padframe/mprj_io_in[11] mprj/analog_io[5] mprj_io[12]
++ padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12]
++ padframe/mprj_io_dm[36] padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_inp_dis[12] padframe/mprj_io_oeb[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_slow_sel[12] padframe/mprj_io_vtrip_sel[12]
++ padframe/mprj_io_in[12] mprj/analog_io[6] mprj_io[13] padframe/mprj_io_analog_en[13]
++ padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13] padframe/mprj_io_dm[39]
++ padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13] padframe/mprj_io_ib_mode_sel[13]
++ padframe/mprj_io_inp_dis[13] padframe/mprj_io_oeb[13] padframe/mprj_io_out[13] padframe/mprj_io_slow_sel[13]
++ padframe/mprj_io_vtrip_sel[13] padframe/mprj_io_in[13] mprj/analog_io[7] mprj_io[14]
++ padframe/mprj_io_analog_en[14] padframe/mprj_io_analog_pol[14] padframe/mprj_io_analog_sel[14]
++ padframe/mprj_io_dm[42] padframe/mprj_io_dm[43] padframe/mprj_io_dm[44] padframe/mprj_io_holdover[14]
++ padframe/mprj_io_ib_mode_sel[14] padframe/mprj_io_inp_dis[14] padframe/mprj_io_oeb[14]
++ padframe/mprj_io_out[14] padframe/mprj_io_slow_sel[14] padframe/mprj_io_vtrip_sel[14]
++ padframe/mprj_io_in[14] mprj/analog_io[8] mprj_io[15] padframe/mprj_io_analog_en[15]
++ padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15] padframe/mprj_io_dm[45]
++ padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15] padframe/mprj_io_ib_mode_sel[15]
++ padframe/mprj_io_inp_dis[15] padframe/mprj_io_oeb[15] padframe/mprj_io_out[15] padframe/mprj_io_slow_sel[15]
++ padframe/mprj_io_vtrip_sel[15] padframe/mprj_io_in[15] mprj/analog_io[9] mprj_io[16]
++ padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_inp_dis[16] padframe/mprj_io_oeb[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_slow_sel[16] padframe/mprj_io_vtrip_sel[16]
++ padframe/mprj_io_in[16] mprj/analog_io[10] mprj_io[17] padframe/mprj_io_analog_en[17]
++ padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17] padframe/mprj_io_dm[51]
++ padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17] padframe/mprj_io_ib_mode_sel[17]
++ padframe/mprj_io_inp_dis[17] padframe/mprj_io_oeb[17] padframe/mprj_io_out[17] padframe/mprj_io_slow_sel[17]
++ padframe/mprj_io_vtrip_sel[17] padframe/mprj_io_in[17] mprj/analog_io[11] mprj_io[18]
++ padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_inp_dis[18] padframe/mprj_io_oeb[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_slow_sel[18] padframe/mprj_io_vtrip_sel[18]
++ padframe/mprj_io_in[18] mprj_io[1] padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1]
++ padframe/mprj_io_analog_sel[1] padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5]
++ padframe/mprj_io_holdover[1] padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_oeb[1] padframe/mprj_io_out[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ padframe/mprj_io_in[1] mprj_io[2] padframe/mprj_io_analog_en[2] padframe/mprj_io_analog_pol[2]
++ padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6] padframe/mprj_io_dm[7] padframe/mprj_io_dm[8]
++ padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2] padframe/mprj_io_inp_dis[2]
++ padframe/mprj_io_oeb[2] padframe/mprj_io_out[2] padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2]
++ padframe/mprj_io_in[2] mprj_io[3] padframe/mprj_io_analog_en[3] padframe/mprj_io_analog_pol[3]
++ padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_dm[9]
++ padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3] padframe/mprj_io_inp_dis[3]
++ padframe/mprj_io_oeb[3] padframe/mprj_io_out[3] padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3]
++ padframe/mprj_io_in[3] mprj_io[4] padframe/mprj_io_analog_en[4] padframe/mprj_io_analog_pol[4]
++ padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12] padframe/mprj_io_dm[13] padframe/mprj_io_dm[14]
++ padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4] padframe/mprj_io_inp_dis[4]
++ padframe/mprj_io_oeb[4] padframe/mprj_io_out[4] padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4]
++ padframe/mprj_io_in[4] mprj_io[5] padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5]
++ padframe/mprj_io_analog_sel[5] padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17]
++ padframe/mprj_io_holdover[5] padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_inp_dis[5]
++ padframe/mprj_io_oeb[5] padframe/mprj_io_out[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ padframe/mprj_io_in[5] mprj_io[6] padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6]
++ padframe/mprj_io_analog_sel[6] padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20]
++ padframe/mprj_io_holdover[6] padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_inp_dis[6]
++ padframe/mprj_io_oeb[6] padframe/mprj_io_out[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ padframe/mprj_io_in[6] mprj/analog_io[0] mprj_io[7] padframe/mprj_io_analog_en[7]
++ padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7] padframe/mprj_io_dm[21]
++ padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] padframe/mprj_io_holdover[7] padframe/mprj_io_ib_mode_sel[7]
++ padframe/mprj_io_inp_dis[7] padframe/mprj_io_oeb[7] padframe/mprj_io_out[7] padframe/mprj_io_slow_sel[7]
++ padframe/mprj_io_vtrip_sel[7] padframe/mprj_io_in[7] mprj/analog_io[1] mprj_io[8]
++ padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_inp_dis[8] padframe/mprj_io_oeb[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ padframe/mprj_io_in[8] mprj/analog_io[2] mprj_io[9] padframe/mprj_io_analog_en[9]
++ padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9] padframe/mprj_io_dm[27]
++ padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9] padframe/mprj_io_ib_mode_sel[9]
++ padframe/mprj_io_inp_dis[9] padframe/mprj_io_oeb[9] padframe/mprj_io_out[9] padframe/mprj_io_slow_sel[9]
++ padframe/mprj_io_vtrip_sel[9] padframe/mprj_io_in[9] mprj/analog_io[12] mprj_io[19]
++ padframe/mprj_io_analog_en[19] padframe/mprj_io_analog_pol[19] padframe/mprj_io_analog_sel[19]
++ padframe/mprj_io_dm[57] padframe/mprj_io_dm[58] padframe/mprj_io_dm[59] padframe/mprj_io_holdover[19]
++ padframe/mprj_io_ib_mode_sel[19] padframe/mprj_io_inp_dis[19] padframe/mprj_io_oeb[19]
++ padframe/mprj_io_out[19] padframe/mprj_io_slow_sel[19] padframe/mprj_io_vtrip_sel[19]
++ padframe/mprj_io_in[19] mprj/analog_io[22] mprj_io[29] padframe/mprj_io_analog_en[29]
++ padframe/mprj_io_analog_pol[29] padframe/mprj_io_analog_sel[29] padframe/mprj_io_dm[87]
++ padframe/mprj_io_dm[88] padframe/mprj_io_dm[89] padframe/mprj_io_holdover[29] padframe/mprj_io_ib_mode_sel[29]
++ padframe/mprj_io_inp_dis[29] padframe/mprj_io_oeb[29] padframe/mprj_io_out[29] padframe/mprj_io_slow_sel[29]
++ padframe/mprj_io_vtrip_sel[29] padframe/mprj_io_in[29] mprj/analog_io[23] mprj_io[30]
++ padframe/mprj_io_analog_en[30] padframe/mprj_io_analog_pol[30] padframe/mprj_io_analog_sel[30]
++ padframe/mprj_io_dm[90] padframe/mprj_io_dm[91] padframe/mprj_io_dm[92] padframe/mprj_io_holdover[30]
++ padframe/mprj_io_ib_mode_sel[30] padframe/mprj_io_inp_dis[30] padframe/mprj_io_oeb[30]
++ padframe/mprj_io_out[30] padframe/mprj_io_slow_sel[30] padframe/mprj_io_vtrip_sel[30]
++ padframe/mprj_io_in[30] mprj/analog_io[24] mprj_io[31] padframe/mprj_io_analog_en[31]
++ padframe/mprj_io_analog_pol[31] padframe/mprj_io_analog_sel[31] padframe/mprj_io_dm[93]
++ padframe/mprj_io_dm[94] padframe/mprj_io_dm[95] padframe/mprj_io_holdover[31] padframe/mprj_io_ib_mode_sel[31]
++ padframe/mprj_io_inp_dis[31] padframe/mprj_io_oeb[31] padframe/mprj_io_out[31] padframe/mprj_io_slow_sel[31]
++ padframe/mprj_io_vtrip_sel[31] padframe/mprj_io_in[31] mprj/analog_io[25] mprj_io[32]
++ padframe/mprj_io_analog_en[32] padframe/mprj_io_analog_pol[32] padframe/mprj_io_analog_sel[32]
++ padframe/mprj_io_dm[96] padframe/mprj_io_dm[97] padframe/mprj_io_dm[98] padframe/mprj_io_holdover[32]
++ padframe/mprj_io_ib_mode_sel[32] padframe/mprj_io_inp_dis[32] padframe/mprj_io_oeb[32]
++ padframe/mprj_io_out[32] padframe/mprj_io_slow_sel[32] padframe/mprj_io_vtrip_sel[32]
++ padframe/mprj_io_in[32] mprj/analog_io[26] mprj_io[33] padframe/mprj_io_analog_en[33]
++ padframe/mprj_io_analog_pol[33] padframe/mprj_io_analog_sel[33] padframe/mprj_io_dm[100]
++ padframe/mprj_io_dm[101] padframe/mprj_io_dm[99] padframe/mprj_io_holdover[33] padframe/mprj_io_ib_mode_sel[33]
++ padframe/mprj_io_inp_dis[33] padframe/mprj_io_oeb[33] padframe/mprj_io_out[33] padframe/mprj_io_slow_sel[33]
++ padframe/mprj_io_vtrip_sel[33] padframe/mprj_io_in[33] mprj/analog_io[27] mprj_io[34]
++ padframe/mprj_io_analog_en[34] padframe/mprj_io_analog_pol[34] padframe/mprj_io_analog_sel[34]
++ padframe/mprj_io_dm[102] padframe/mprj_io_dm[103] padframe/mprj_io_dm[104] padframe/mprj_io_holdover[34]
++ padframe/mprj_io_ib_mode_sel[34] padframe/mprj_io_inp_dis[34] padframe/mprj_io_oeb[34]
++ padframe/mprj_io_out[34] padframe/mprj_io_slow_sel[34] padframe/mprj_io_vtrip_sel[34]
++ padframe/mprj_io_in[34] mprj/analog_io[28] mprj_io[35] padframe/mprj_io_analog_en[35]
++ padframe/mprj_io_analog_pol[35] padframe/mprj_io_analog_sel[35] padframe/mprj_io_dm[105]
++ padframe/mprj_io_dm[106] padframe/mprj_io_dm[107] padframe/mprj_io_holdover[35]
++ padframe/mprj_io_ib_mode_sel[35] padframe/mprj_io_inp_dis[35] padframe/mprj_io_oeb[35]
++ padframe/mprj_io_out[35] padframe/mprj_io_slow_sel[35] padframe/mprj_io_vtrip_sel[35]
++ padframe/mprj_io_in[35] mprj_io[36] padframe/mprj_io_analog_en[36] padframe/mprj_io_analog_pol[36]
++ padframe/mprj_io_analog_sel[36] padframe/mprj_io_dm[108] padframe/mprj_io_dm[109]
++ padframe/mprj_io_dm[110] padframe/mprj_io_holdover[36] padframe/mprj_io_ib_mode_sel[36]
++ padframe/mprj_io_inp_dis[36] padframe/mprj_io_oeb[36] padframe/mprj_io_out[36] padframe/mprj_io_slow_sel[36]
++ padframe/mprj_io_vtrip_sel[36] padframe/mprj_io_in[36] mprj_io[37] padframe/mprj_io_analog_en[37]
++ padframe/mprj_io_analog_pol[37] padframe/mprj_io_analog_sel[37] padframe/mprj_io_dm[111]
++ padframe/mprj_io_dm[112] padframe/mprj_io_dm[113] padframe/mprj_io_holdover[37]
++ padframe/mprj_io_ib_mode_sel[37] padframe/mprj_io_inp_dis[37] padframe/mprj_io_oeb[37]
++ padframe/mprj_io_out[37] padframe/mprj_io_slow_sel[37] padframe/mprj_io_vtrip_sel[37]
++ padframe/mprj_io_in[37] mprj/analog_io[13] mprj_io[20] padframe/mprj_io_analog_en[20]
++ padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20] padframe/mprj_io_dm[60]
++ padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20] padframe/mprj_io_ib_mode_sel[20]
++ padframe/mprj_io_inp_dis[20] padframe/mprj_io_oeb[20] padframe/mprj_io_out[20] padframe/mprj_io_slow_sel[20]
++ padframe/mprj_io_vtrip_sel[20] padframe/mprj_io_in[20] mprj/analog_io[14] mprj_io[21]
++ padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_inp_dis[21] padframe/mprj_io_oeb[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_slow_sel[21] padframe/mprj_io_vtrip_sel[21]
++ padframe/mprj_io_in[21] mprj/analog_io[15] mprj_io[22] padframe/mprj_io_analog_en[22]
++ padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22] padframe/mprj_io_dm[66]
++ padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22] padframe/mprj_io_ib_mode_sel[22]
++ padframe/mprj_io_inp_dis[22] padframe/mprj_io_oeb[22] padframe/mprj_io_out[22] padframe/mprj_io_slow_sel[22]
++ padframe/mprj_io_vtrip_sel[22] padframe/mprj_io_in[22] mprj/analog_io[16] mprj_io[23]
++ padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_inp_dis[23] padframe/mprj_io_oeb[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_slow_sel[23] padframe/mprj_io_vtrip_sel[23]
++ padframe/mprj_io_in[23] mprj/analog_io[17] mprj_io[24] padframe/mprj_io_analog_en[24]
++ padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24] padframe/mprj_io_dm[72]
++ padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24] padframe/mprj_io_ib_mode_sel[24]
++ padframe/mprj_io_inp_dis[24] padframe/mprj_io_oeb[24] padframe/mprj_io_out[24] padframe/mprj_io_slow_sel[24]
++ padframe/mprj_io_vtrip_sel[24] padframe/mprj_io_in[24] mprj/analog_io[18] mprj_io[25]
++ padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25]
++ padframe/mprj_io_dm[75] padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25]
++ padframe/mprj_io_ib_mode_sel[25] padframe/mprj_io_inp_dis[25] padframe/mprj_io_oeb[25]
++ padframe/mprj_io_out[25] padframe/mprj_io_slow_sel[25] padframe/mprj_io_vtrip_sel[25]
++ padframe/mprj_io_in[25] mprj/analog_io[19] mprj_io[26] padframe/mprj_io_analog_en[26]
++ padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26] padframe/mprj_io_dm[78]
++ padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26] padframe/mprj_io_ib_mode_sel[26]
++ padframe/mprj_io_inp_dis[26] padframe/mprj_io_oeb[26] padframe/mprj_io_out[26] padframe/mprj_io_slow_sel[26]
++ padframe/mprj_io_vtrip_sel[26] padframe/mprj_io_in[26] mprj/analog_io[20] mprj_io[27]
++ padframe/mprj_io_analog_en[27] padframe/mprj_io_analog_pol[27] padframe/mprj_io_analog_sel[27]
++ padframe/mprj_io_dm[81] padframe/mprj_io_dm[82] padframe/mprj_io_dm[83] padframe/mprj_io_holdover[27]
++ padframe/mprj_io_ib_mode_sel[27] padframe/mprj_io_inp_dis[27] padframe/mprj_io_oeb[27]
++ padframe/mprj_io_out[27] padframe/mprj_io_slow_sel[27] padframe/mprj_io_vtrip_sel[27]
++ padframe/mprj_io_in[27] mprj/analog_io[21] mprj_io[28] padframe/mprj_io_analog_en[28]
++ padframe/mprj_io_analog_pol[28] padframe/mprj_io_analog_sel[28] padframe/mprj_io_dm[84]
++ padframe/mprj_io_dm[85] padframe/mprj_io_dm[86] padframe/mprj_io_holdover[28] padframe/mprj_io_ib_mode_sel[28]
++ padframe/mprj_io_inp_dis[28] padframe/mprj_io_oeb[28] padframe/mprj_io_out[28] padframe/mprj_io_slow_sel[28]
++ padframe/mprj_io_vtrip_sel[28] padframe/mprj_io_in[28] por/porb_h resetb pll/resetb
++ padframe/vdda padframe/vssa padframe/vssd vccd1 vdda1 vdda1_2 vssa1 vssa1_2 padframe/vccd1
++ padframe/vdda1 padframe/vssa1 padframe/vssd1 vssd1 vccd2 vdda2 vssa2 padframe/vccd
++ padframe/vccd2 padframe/vdda2 padframe/vddio padframe/vssa2 padframe/vssd2 vssd2
++ padframe/vssio chip_io
+Xgpio_16_defaults gpio_16_defaults/VGND gpio_16_defaults/VPWR gpio_16_defaults/gpio_defaults[0]
++ gpio_16_defaults/gpio_defaults[10] gpio_16_defaults/gpio_defaults[11] gpio_16_defaults/gpio_defaults[12]
++ gpio_16_defaults/gpio_defaults[1] gpio_16_defaults/gpio_defaults[2] gpio_16_defaults/gpio_defaults[3]
++ gpio_16_defaults/gpio_defaults[4] gpio_16_defaults/gpio_defaults[5] gpio_16_defaults/gpio_defaults[6]
++ gpio_16_defaults/gpio_defaults[7] gpio_16_defaults/gpio_defaults[8] gpio_16_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_8_defaults gpio_8_defaults/VGND gpio_8_defaults/VPWR gpio_8_defaults/gpio_defaults[0]
++ gpio_8_defaults/gpio_defaults[2] gpio_8_defaults/gpio_defaults[1] gpio_8_defaults/gpio_defaults[0]
++ gpio_8_defaults/gpio_defaults[1] gpio_8_defaults/gpio_defaults[2] gpio_8_defaults/gpio_defaults[9]
++ gpio_8_defaults/gpio_defaults[8] gpio_8_defaults/gpio_defaults[7] gpio_8_defaults/gpio_defaults[6]
++ gpio_8_defaults/gpio_defaults[7] gpio_8_defaults/gpio_defaults[8] gpio_8_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_31_defaults gpio_31_defaults/VGND gpio_31_defaults/VPWR gpio_31_defaults/gpio_defaults[0]
++ gpio_31_defaults/gpio_defaults[10] gpio_31_defaults/gpio_defaults[11] gpio_31_defaults/gpio_defaults[12]
++ gpio_31_defaults/gpio_defaults[1] gpio_31_defaults/gpio_defaults[2] gpio_31_defaults/gpio_defaults[3]
++ gpio_31_defaults/gpio_defaults[4] gpio_31_defaults/gpio_defaults[5] gpio_31_defaults/gpio_defaults[6]
++ gpio_31_defaults/gpio_defaults[7] gpio_31_defaults/gpio_defaults[8] gpio_31_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[3\] gpio_5_defaults/gpio_defaults[0] gpio_5_defaults/gpio_defaults[2]
++ gpio_5_defaults/gpio_defaults[1] gpio_5_defaults/gpio_defaults[0] gpio_5_defaults/gpio_defaults[1]
++ gpio_5_defaults/gpio_defaults[2] gpio_5_defaults/gpio_defaults[9] gpio_5_defaults/gpio_defaults[8]
++ gpio_5_defaults/gpio_defaults[7] gpio_5_defaults/gpio_defaults[6] gpio_5_defaults/gpio_defaults[7]
++ gpio_5_defaults/gpio_defaults[8] gpio_5_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[5]
++ gpio_control_in_1a\[3\]/one housekeeping/mgmt_gpio_in[5] gpio_control_in_1a\[3\]/one
++ padframe/mprj_io_analog_en[5] padframe/mprj_io_analog_pol[5] padframe/mprj_io_analog_sel[5]
++ padframe/mprj_io_dm[15] padframe/mprj_io_dm[16] padframe/mprj_io_dm[17] padframe/mprj_io_holdover[5]
++ padframe/mprj_io_ib_mode_sel[5] padframe/mprj_io_in[5] padframe/mprj_io_inp_dis[5]
++ padframe/mprj_io_out[5] padframe/mprj_io_oeb[5] padframe/mprj_io_slow_sel[5] padframe/mprj_io_vtrip_sel[5]
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_1a\[3\]/serial_data_in gpio_control_in_1a\[4\]/serial_data_in
++ gpio_control_in_2\[5\]/serial_load gpio_control_in_2\[6\]/serial_load mprj/io_in[5]
++ mprj/io_oeb[5] mprj/io_out[5] gpio_control_in_1a\[3\]/vccd gpio_control_in_1a\[3\]/vccd1
++ gpio_control_in_1a\[3\]/vssd gpio_control_in_1a\[3\]/vssd1 gpio_control_in_1a\[3\]/zero
++ gpio_control_block
+Xgpio_control_in_2\[14\] gpio_33_defaults/gpio_defaults[0] gpio_33_defaults/gpio_defaults[10]
++ gpio_33_defaults/gpio_defaults[11] gpio_33_defaults/gpio_defaults[12] gpio_33_defaults/gpio_defaults[1]
++ gpio_33_defaults/gpio_defaults[2] gpio_33_defaults/gpio_defaults[3] gpio_33_defaults/gpio_defaults[4]
++ gpio_33_defaults/gpio_defaults[5] gpio_33_defaults/gpio_defaults[6] gpio_33_defaults/gpio_defaults[7]
++ gpio_33_defaults/gpio_defaults[8] gpio_33_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[33]
++ gpio_control_in_2\[14\]/one housekeeping/mgmt_gpio_in[33] gpio_control_in_2\[14\]/one
++ padframe/mprj_io_analog_en[33] padframe/mprj_io_analog_pol[33] padframe/mprj_io_analog_sel[33]
++ padframe/mprj_io_dm[99] padframe/mprj_io_dm[100] padframe/mprj_io_dm[101] padframe/mprj_io_holdover[33]
++ padframe/mprj_io_ib_mode_sel[33] padframe/mprj_io_in[33] padframe/mprj_io_inp_dis[33]
++ padframe/mprj_io_out[33] padframe/mprj_io_oeb[33] padframe/mprj_io_slow_sel[33]
++ padframe/mprj_io_vtrip_sel[33] gpio_control_in_1\[6\]/resetn gpio_control_in_1\[7\]/resetn
++ gpio_control_in_1\[6\]/serial_clock gpio_control_in_1\[7\]/serial_clock gpio_control_in_2\[14\]/serial_data_in
++ gpio_control_in_2\[13\]/serial_data_in gpio_control_in_1\[6\]/serial_load gpio_control_in_1\[7\]/serial_load
++ mprj/io_in[33] mprj/io_oeb[33] mprj/io_out[33] gpio_control_in_2\[14\]/vccd gpio_control_in_2\[14\]/vccd1
++ gpio_control_in_2\[14\]/vssd gpio_control_in_2\[14\]/vssd1 gpio_control_in_2\[14\]/zero
++ gpio_control_block
+Xgpio_control_bidir_2\[0\] gpio_35_defaults/gpio_defaults[0] gpio_35_defaults/gpio_defaults[10]
++ gpio_35_defaults/gpio_defaults[11] gpio_35_defaults/gpio_defaults[12] gpio_35_defaults/gpio_defaults[1]
++ gpio_35_defaults/gpio_defaults[2] gpio_35_defaults/gpio_defaults[3] gpio_35_defaults/gpio_defaults[4]
++ gpio_35_defaults/gpio_defaults[5] gpio_35_defaults/gpio_defaults[6] gpio_35_defaults/gpio_defaults[7]
++ gpio_35_defaults/gpio_defaults[8] gpio_35_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[35]
++ housekeeping/mgmt_gpio_oeb[35] housekeeping/mgmt_gpio_out[35] gpio_control_bidir_2\[0\]/one
++ padframe/mprj_io_analog_en[35] padframe/mprj_io_analog_pol[35] padframe/mprj_io_analog_sel[35]
++ padframe/mprj_io_dm[105] padframe/mprj_io_dm[106] padframe/mprj_io_dm[107] padframe/mprj_io_holdover[35]
++ padframe/mprj_io_ib_mode_sel[35] padframe/mprj_io_in[35] padframe/mprj_io_inp_dis[35]
++ padframe/mprj_io_out[35] padframe/mprj_io_oeb[35] padframe/mprj_io_slow_sel[35]
++ padframe/mprj_io_vtrip_sel[35] gpio_control_in_1\[8\]/resetn gpio_control_in_1\[9\]/resetn
++ gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock gpio_control_bidir_2\[0\]/serial_data_in
++ gpio_control_in_2\[15\]/serial_data_in gpio_control_in_1\[8\]/serial_load gpio_control_in_1\[9\]/serial_load
++ mprj/io_in[35] mprj/io_oeb[35] mprj/io_out[35] gpio_control_bidir_2\[0\]/vccd gpio_control_bidir_2\[0\]/vccd1
++ gpio_control_bidir_2\[0\]/vssd gpio_control_bidir_2\[0\]/vssd1 gpio_control_bidir_2\[0\]/zero
++ gpio_control_block
+Xgpio_234_defaults\[1\] gpio_234_defaults\[1\]/VGND gpio_234_defaults\[1\]/VPWR gpio_234_defaults\[1\]/gpio_defaults[0]
++ gpio_234_defaults\[1\]/gpio_defaults[2] gpio_234_defaults\[1\]/gpio_defaults[1]
++ gpio_234_defaults\[1\]/gpio_defaults[0] gpio_234_defaults\[1\]/gpio_defaults[1]
++ gpio_234_defaults\[1\]/gpio_defaults[2] gpio_234_defaults\[1\]/gpio_defaults[9]
++ gpio_234_defaults\[1\]/gpio_defaults[8] gpio_234_defaults\[1\]/gpio_defaults[7]
++ gpio_234_defaults\[1\]/gpio_defaults[6] gpio_234_defaults\[1\]/gpio_defaults[7]
++ gpio_234_defaults\[1\]/gpio_defaults[8] gpio_234_defaults\[1\]/gpio_defaults[9]
++ gpio_defaults_block
+Xsoc soc/VGND soc/VPWR soc/core_clk soc/core_rstn soc/debug_in soc/debug_mode soc/debug_oeb
++ soc/debug_out soc/flash_clk soc/flash_csb soc/flash_io0_di soc/flash_io0_do soc/flash_io0_oeb
++ soc/flash_io1_di soc/flash_io1_do soc/flash_io1_oeb soc/flash_io2_di soc/flash_io2_do
++ soc/flash_io2_oeb soc/flash_io3_di soc/flash_io3_do soc/flash_io3_oeb soc/gpio_in_pad
++ soc/gpio_inenb_pad soc/gpio_mode0_pad soc/gpio_mode1_pad soc/gpio_out_pad soc/gpio_outenb_pad
++ soc/hk_ack_i soc/hk_dat_i[0] soc/hk_dat_i[10] soc/hk_dat_i[11] soc/hk_dat_i[12]
++ soc/hk_dat_i[13] soc/hk_dat_i[14] soc/hk_dat_i[15] soc/hk_dat_i[16] soc/hk_dat_i[17]
++ soc/hk_dat_i[18] soc/hk_dat_i[19] soc/hk_dat_i[1] soc/hk_dat_i[20] soc/hk_dat_i[21]
++ soc/hk_dat_i[22] soc/hk_dat_i[23] soc/hk_dat_i[24] soc/hk_dat_i[25] soc/hk_dat_i[26]
++ soc/hk_dat_i[27] soc/hk_dat_i[28] soc/hk_dat_i[29] soc/hk_dat_i[2] soc/hk_dat_i[30]
++ soc/hk_dat_i[31] soc/hk_dat_i[3] soc/hk_dat_i[4] soc/hk_dat_i[5] soc/hk_dat_i[6]
++ soc/hk_dat_i[7] soc/hk_dat_i[8] soc/hk_dat_i[9] soc/hk_stb_o soc/irq[0] soc/irq[1]
++ soc/irq[2] soc/irq[3] soc/irq[4] soc/irq[5] soc/la_iena[0] soc/la_iena[100] soc/la_iena[101]
++ soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105] soc/la_iena[106]
++ soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10] soc/la_iena[110]
++ soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114] soc/la_iena[115]
++ soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119] soc/la_iena[11]
++ soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123] soc/la_iena[124]
++ soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12] soc/la_iena[13]
++ soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17] soc/la_iena[18]
++ soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22] soc/la_iena[23]
++ soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27] soc/la_iena[28]
++ soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32] soc/la_iena[33]
++ soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37] soc/la_iena[38]
++ soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42] soc/la_iena[43]
++ soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47] soc/la_iena[48]
++ soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52] soc/la_iena[53]
++ soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57] soc/la_iena[58]
++ soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62] soc/la_iena[63]
++ soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67] soc/la_iena[68]
++ soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72] soc/la_iena[73]
++ soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77] soc/la_iena[78]
++ soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82] soc/la_iena[83]
++ soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87] soc/la_iena[88]
++ soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92] soc/la_iena[93]
++ soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97] soc/la_iena[98]
++ soc/la_iena[99] soc/la_iena[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102] soc/la_oenb[103]
++ soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107] soc/la_oenb[108]
++ soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111] soc/la_oenb[112]
++ soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116] soc/la_oenb[117]
++ soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120] soc/la_oenb[121]
++ soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125] soc/la_oenb[126]
++ soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14] soc/la_oenb[15]
++ soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19] soc/la_oenb[1] soc/la_oenb[20]
++ soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24] soc/la_oenb[25]
++ soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29] soc/la_oenb[2] soc/la_oenb[30]
++ soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34] soc/la_oenb[35]
++ soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39] soc/la_oenb[3] soc/la_oenb[40]
++ soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44] soc/la_oenb[45]
++ soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49] soc/la_oenb[4] soc/la_oenb[50]
++ soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54] soc/la_oenb[55]
++ soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59] soc/la_oenb[5] soc/la_oenb[60]
++ soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64] soc/la_oenb[65]
++ soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69] soc/la_oenb[6] soc/la_oenb[70]
++ soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74] soc/la_oenb[75]
++ soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79] soc/la_oenb[7] soc/la_oenb[80]
++ soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84] soc/la_oenb[85]
++ soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89] soc/la_oenb[8] soc/la_oenb[90]
++ soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94] soc/la_oenb[95]
++ soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99] soc/la_oenb[9] soc/la_output[0]
++ soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103] soc/la_output[104]
++ soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108] soc/la_output[109]
++ soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112] soc/la_output[113]
++ soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117] soc/la_output[118]
++ soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121] soc/la_output[122]
++ soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126] soc/la_output[127]
++ soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15] soc/la_output[16]
++ soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1] soc/la_output[20]
++ soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24] soc/la_output[25]
++ soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29] soc/la_output[2]
++ soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33] soc/la_output[34]
++ soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38] soc/la_output[39]
++ soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42] soc/la_output[43]
++ soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47] soc/la_output[48]
++ soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51] soc/la_output[52]
++ soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56] soc/la_output[57]
++ soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60] soc/la_output[61]
++ soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65] soc/la_output[66]
++ soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6] soc/la_output[70]
++ soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74] soc/la_output[75]
++ soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79] soc/la_output[7]
++ soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83] soc/la_output[84]
++ soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88] soc/la_output[89]
++ soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92] soc/la_output[93]
++ soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97] soc/la_output[98]
++ soc/la_output[99] soc/la_output[9] soc/mprj_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ soc/mprj_cyc_o soc/mprj_dat_i[0] soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12]
++ soc/mprj_dat_i[13] soc/mprj_dat_i[14] soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17]
++ soc/mprj_dat_i[18] soc/mprj_dat_i[19] soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21]
++ soc/mprj_dat_i[22] soc/mprj_dat_i[23] soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26]
++ soc/mprj_dat_i[27] soc/mprj_dat_i[28] soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30]
++ soc/mprj_dat_i[31] soc/mprj_dat_i[3] soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6]
++ soc/mprj_dat_i[7] soc/mprj_dat_i[8] soc/mprj_dat_i[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ soc/mprj_sel_o[0] soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/mprj_stb_o
++ soc/mprj_wb_iena soc/mprj_we_o soc/qspi_enabled soc/ser_rx soc/ser_tx soc/spi_csb
++ soc/spi_enabled soc/spi_sck soc/spi_sdi soc/spi_sdo soc/spi_sdoenb soc/sram_ro_addr[0]
++ soc/sram_ro_addr[1] soc/sram_ro_addr[2] soc/sram_ro_addr[3] soc/sram_ro_addr[4]
++ soc/sram_ro_addr[5] soc/sram_ro_addr[6] soc/sram_ro_addr[7] soc/sram_ro_clk soc/sram_ro_csb
++ soc/sram_ro_data[0] soc/sram_ro_data[10] soc/sram_ro_data[11] soc/sram_ro_data[12]
++ soc/sram_ro_data[13] soc/sram_ro_data[14] soc/sram_ro_data[15] soc/sram_ro_data[16]
++ soc/sram_ro_data[17] soc/sram_ro_data[18] soc/sram_ro_data[19] soc/sram_ro_data[1]
++ soc/sram_ro_data[20] soc/sram_ro_data[21] soc/sram_ro_data[22] soc/sram_ro_data[23]
++ soc/sram_ro_data[24] soc/sram_ro_data[25] soc/sram_ro_data[26] soc/sram_ro_data[27]
++ soc/sram_ro_data[28] soc/sram_ro_data[29] soc/sram_ro_data[2] soc/sram_ro_data[30]
++ soc/sram_ro_data[31] soc/sram_ro_data[3] soc/sram_ro_data[4] soc/sram_ro_data[5]
++ soc/sram_ro_data[6] soc/sram_ro_data[7] soc/sram_ro_data[8] soc/sram_ro_data[9]
++ soc/trap soc/uart_enabled soc/user_irq_ena[0] soc/user_irq_ena[1] soc/user_irq_ena[2]
++ mgmt_core_wrapper
+Xgpio_control_in_2\[9\] gpio_28_defaults/gpio_defaults[0] gpio_28_defaults/gpio_defaults[10]
++ gpio_28_defaults/gpio_defaults[11] gpio_28_defaults/gpio_defaults[12] gpio_28_defaults/gpio_defaults[1]
++ gpio_28_defaults/gpio_defaults[2] gpio_28_defaults/gpio_defaults[3] gpio_28_defaults/gpio_defaults[4]
++ gpio_28_defaults/gpio_defaults[5] gpio_28_defaults/gpio_defaults[6] gpio_28_defaults/gpio_defaults[7]
++ gpio_28_defaults/gpio_defaults[8] gpio_28_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[28]
++ gpio_control_in_2\[9\]/one housekeeping/mgmt_gpio_in[28] gpio_control_in_2\[9\]/one
++ padframe/mprj_io_analog_en[28] padframe/mprj_io_analog_pol[28] padframe/mprj_io_analog_sel[28]
++ padframe/mprj_io_dm[84] padframe/mprj_io_dm[85] padframe/mprj_io_dm[86] padframe/mprj_io_holdover[28]
++ padframe/mprj_io_ib_mode_sel[28] padframe/mprj_io_in[28] padframe/mprj_io_inp_dis[28]
++ padframe/mprj_io_out[28] padframe/mprj_io_oeb[28] padframe/mprj_io_slow_sel[28]
++ padframe/mprj_io_vtrip_sel[28] gpio_control_in_2\[9\]/resetn gpio_control_in_1\[2\]/resetn
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[2\]/serial_clock gpio_control_in_2\[9\]/serial_data_in
++ gpio_control_in_2\[8\]/serial_data_in gpio_control_in_2\[9\]/serial_load gpio_control_in_1\[2\]/serial_load
++ mprj/io_in[28] mprj/io_oeb[28] mprj/io_out[28] gpio_control_in_2\[9\]/vccd gpio_control_in_2\[9\]/vccd1
++ gpio_control_in_2\[9\]/vssd gpio_control_in_2\[9\]/vssd1 gpio_control_in_2\[9\]/zero
++ gpio_control_block
+Xgpio_25_defaults gpio_25_defaults/VGND gpio_25_defaults/VPWR gpio_25_defaults/gpio_defaults[0]
++ gpio_25_defaults/gpio_defaults[10] gpio_25_defaults/gpio_defaults[11] gpio_25_defaults/gpio_defaults[12]
++ gpio_25_defaults/gpio_defaults[1] gpio_25_defaults/gpio_defaults[2] gpio_25_defaults/gpio_defaults[3]
++ gpio_25_defaults/gpio_defaults[4] gpio_25_defaults/gpio_defaults[5] gpio_25_defaults/gpio_defaults[6]
++ gpio_25_defaults/gpio_defaults[7] gpio_25_defaults/gpio_defaults[8] gpio_25_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[4\] gpio_12_defaults/gpio_defaults[0] gpio_12_defaults/gpio_defaults[2]
++ gpio_12_defaults/gpio_defaults[1] gpio_12_defaults/gpio_defaults[0] gpio_12_defaults/gpio_defaults[1]
++ gpio_12_defaults/gpio_defaults[2] gpio_12_defaults/gpio_defaults[9] gpio_12_defaults/gpio_defaults[8]
++ gpio_12_defaults/gpio_defaults[7] gpio_12_defaults/gpio_defaults[6] gpio_12_defaults/gpio_defaults[7]
++ gpio_12_defaults/gpio_defaults[8] gpio_12_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[12]
++ gpio_control_in_1\[4\]/one housekeeping/mgmt_gpio_in[12] gpio_control_in_1\[4\]/one
++ padframe/mprj_io_analog_en[12] padframe/mprj_io_analog_pol[12] padframe/mprj_io_analog_sel[12]
++ padframe/mprj_io_dm[36] padframe/mprj_io_dm[37] padframe/mprj_io_dm[38] padframe/mprj_io_holdover[12]
++ padframe/mprj_io_ib_mode_sel[12] padframe/mprj_io_in[12] padframe/mprj_io_inp_dis[12]
++ padframe/mprj_io_out[12] padframe/mprj_io_oeb[12] padframe/mprj_io_slow_sel[12]
++ padframe/mprj_io_vtrip_sel[12] gpio_control_in_1\[4\]/resetn gpio_control_in_1\[5\]/resetn
++ gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[5\]/serial_clock gpio_control_in_1\[4\]/serial_data_in
++ gpio_control_in_1\[5\]/serial_data_in gpio_control_in_1\[4\]/serial_load gpio_control_in_1\[5\]/serial_load
++ mprj/io_in[12] mprj/io_oeb[12] mprj/io_out[12] gpio_control_in_1\[4\]/vccd gpio_control_in_1\[4\]/vccd1
++ gpio_control_in_1\[4\]/vssd gpio_control_in_1\[4\]/vssd1 gpio_control_in_1\[4\]/zero
++ gpio_control_block
+Xpor por/vdd3v3 por/vdd1v8 por/vss por/porb_h por/por_l por/porb_l simple_por
+Xgpio_19_defaults gpio_19_defaults/VGND gpio_19_defaults/VPWR gpio_19_defaults/gpio_defaults[0]
++ gpio_19_defaults/gpio_defaults[10] gpio_19_defaults/gpio_defaults[11] gpio_19_defaults/gpio_defaults[12]
++ gpio_19_defaults/gpio_defaults[1] gpio_19_defaults/gpio_defaults[2] gpio_19_defaults/gpio_defaults[3]
++ gpio_19_defaults/gpio_defaults[4] gpio_19_defaults/gpio_defaults[5] gpio_19_defaults/gpio_defaults[6]
++ gpio_19_defaults/gpio_defaults[7] gpio_19_defaults/gpio_defaults[8] gpio_19_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[12\] gpio_31_defaults/gpio_defaults[0] gpio_31_defaults/gpio_defaults[10]
++ gpio_31_defaults/gpio_defaults[11] gpio_31_defaults/gpio_defaults[12] gpio_31_defaults/gpio_defaults[1]
++ gpio_31_defaults/gpio_defaults[2] gpio_31_defaults/gpio_defaults[3] gpio_31_defaults/gpio_defaults[4]
++ gpio_31_defaults/gpio_defaults[5] gpio_31_defaults/gpio_defaults[6] gpio_31_defaults/gpio_defaults[7]
++ gpio_31_defaults/gpio_defaults[8] gpio_31_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[31]
++ gpio_control_in_2\[12\]/one housekeeping/mgmt_gpio_in[31] gpio_control_in_2\[12\]/one
++ padframe/mprj_io_analog_en[31] padframe/mprj_io_analog_pol[31] padframe/mprj_io_analog_sel[31]
++ padframe/mprj_io_dm[93] padframe/mprj_io_dm[94] padframe/mprj_io_dm[95] padframe/mprj_io_holdover[31]
++ padframe/mprj_io_ib_mode_sel[31] padframe/mprj_io_in[31] padframe/mprj_io_inp_dis[31]
++ padframe/mprj_io_out[31] padframe/mprj_io_oeb[31] padframe/mprj_io_slow_sel[31]
++ padframe/mprj_io_vtrip_sel[31] gpio_control_in_1\[4\]/resetn gpio_control_in_1\[5\]/resetn
++ gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[5\]/serial_clock gpio_control_in_2\[12\]/serial_data_in
++ gpio_control_in_2\[11\]/serial_data_in gpio_control_in_1\[4\]/serial_load gpio_control_in_1\[5\]/serial_load
++ mprj/io_in[31] mprj/io_oeb[31] mprj/io_out[31] gpio_control_in_2\[12\]/vccd gpio_control_in_2\[12\]/vccd1
++ gpio_control_in_2\[12\]/vssd gpio_control_in_2\[12\]/vssd1 gpio_control_in_2\[12\]/zero
++ gpio_control_block
+Xgpio_control_in_1a\[1\] gpio_234_defaults\[1\]/gpio_defaults[0] gpio_234_defaults\[1\]/gpio_defaults[2]
++ gpio_234_defaults\[1\]/gpio_defaults[1] gpio_234_defaults\[1\]/gpio_defaults[0]
++ gpio_234_defaults\[1\]/gpio_defaults[1] gpio_234_defaults\[1\]/gpio_defaults[2]
++ gpio_234_defaults\[1\]/gpio_defaults[9] gpio_234_defaults\[1\]/gpio_defaults[8]
++ gpio_234_defaults\[1\]/gpio_defaults[7] gpio_234_defaults\[1\]/gpio_defaults[6]
++ gpio_234_defaults\[1\]/gpio_defaults[7] gpio_234_defaults\[1\]/gpio_defaults[8]
++ gpio_234_defaults\[1\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[3] gpio_control_in_1a\[1\]/one
++ housekeeping/mgmt_gpio_in[3] gpio_control_in_1a\[1\]/one padframe/mprj_io_analog_en[3]
++ padframe/mprj_io_analog_pol[3] padframe/mprj_io_analog_sel[3] padframe/mprj_io_dm[9]
++ padframe/mprj_io_dm[10] padframe/mprj_io_dm[11] padframe/mprj_io_holdover[3] padframe/mprj_io_ib_mode_sel[3]
++ padframe/mprj_io_in[3] padframe/mprj_io_inp_dis[3] padframe/mprj_io_out[3] padframe/mprj_io_oeb[3]
++ padframe/mprj_io_slow_sel[3] padframe/mprj_io_vtrip_sel[3] gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[4\]/resetn gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock
++ gpio_control_in_1a\[1\]/serial_data_in gpio_control_in_1a\[2\]/serial_data_in gpio_control_in_2\[3\]/serial_load
++ gpio_control_in_2\[4\]/serial_load mprj/io_in[3] mprj/io_oeb[3] mprj/io_out[3] gpio_control_in_1a\[1\]/vccd
++ gpio_control_in_1a\[1\]/vccd1 gpio_control_in_1a\[1\]/vssd gpio_control_in_1a\[1\]/vssd1
++ gpio_control_in_1a\[1\]/zero gpio_control_block
+Xgpio_control_in_2\[7\] gpio_26_defaults/gpio_defaults[0] gpio_26_defaults/gpio_defaults[10]
++ gpio_26_defaults/gpio_defaults[11] gpio_26_defaults/gpio_defaults[12] gpio_26_defaults/gpio_defaults[1]
++ gpio_26_defaults/gpio_defaults[2] gpio_26_defaults/gpio_defaults[3] gpio_26_defaults/gpio_defaults[4]
++ gpio_26_defaults/gpio_defaults[5] gpio_26_defaults/gpio_defaults[6] gpio_26_defaults/gpio_defaults[7]
++ gpio_26_defaults/gpio_defaults[8] gpio_26_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[26]
++ gpio_control_in_2\[7\]/one housekeeping/mgmt_gpio_in[26] gpio_control_in_2\[7\]/one
++ padframe/mprj_io_analog_en[26] padframe/mprj_io_analog_pol[26] padframe/mprj_io_analog_sel[26]
++ padframe/mprj_io_dm[78] padframe/mprj_io_dm[79] padframe/mprj_io_dm[80] padframe/mprj_io_holdover[26]
++ padframe/mprj_io_ib_mode_sel[26] padframe/mprj_io_in[26] padframe/mprj_io_inp_dis[26]
++ padframe/mprj_io_out[26] padframe/mprj_io_oeb[26] padframe/mprj_io_slow_sel[26]
++ padframe/mprj_io_vtrip_sel[26] gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[7\]/serial_data_in
++ gpio_control_in_2\[6\]/serial_data_in gpio_control_in_2\[7\]/serial_load gpio_control_in_2\[8\]/serial_load
++ mprj/io_in[26] mprj/io_oeb[26] mprj/io_out[26] gpio_control_in_2\[7\]/vccd gpio_control_in_2\[7\]/vccd1
++ gpio_control_in_2\[7\]/vssd gpio_control_in_2\[7\]/vssd1 gpio_control_in_2\[7\]/zero
++ gpio_control_block
+Xgpio_34_defaults gpio_34_defaults/VGND gpio_34_defaults/VPWR gpio_34_defaults/gpio_defaults[0]
++ gpio_34_defaults/gpio_defaults[10] gpio_34_defaults/gpio_defaults[11] gpio_34_defaults/gpio_defaults[12]
++ gpio_34_defaults/gpio_defaults[1] gpio_34_defaults/gpio_defaults[2] gpio_34_defaults/gpio_defaults[3]
++ gpio_34_defaults/gpio_defaults[4] gpio_34_defaults/gpio_defaults[5] gpio_34_defaults/gpio_defaults[6]
++ gpio_34_defaults/gpio_defaults[7] gpio_34_defaults/gpio_defaults[8] gpio_34_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xclocking clocking/VGND clocking/VPWR soc/core_clk pll/osc clocking/ext_clk_sel housekeeping/reset
++ pll/clockp[1] pll/clockp[0] pll/resetb soc/core_rstn clocking/sel2[0] clocking/sel2[1]
++ clocking/sel2[2] clocking/sel[0] clocking/sel[1] clocking/sel[2] clocking/user_clk
++ caravel_clocking
+Xgpio_control_in_1\[2\] gpio_10_defaults/gpio_defaults[0] gpio_10_defaults/gpio_defaults[2]
++ gpio_10_defaults/gpio_defaults[1] gpio_10_defaults/gpio_defaults[0] gpio_10_defaults/gpio_defaults[1]
++ gpio_10_defaults/gpio_defaults[2] gpio_10_defaults/gpio_defaults[9] gpio_10_defaults/gpio_defaults[8]
++ gpio_10_defaults/gpio_defaults[7] gpio_10_defaults/gpio_defaults[6] gpio_10_defaults/gpio_defaults[7]
++ gpio_10_defaults/gpio_defaults[8] gpio_10_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[10]
++ gpio_control_in_1\[2\]/one housekeeping/mgmt_gpio_in[10] gpio_control_in_1\[2\]/one
++ padframe/mprj_io_analog_en[10] padframe/mprj_io_analog_pol[10] padframe/mprj_io_analog_sel[10]
++ padframe/mprj_io_dm[30] padframe/mprj_io_dm[31] padframe/mprj_io_dm[32] padframe/mprj_io_holdover[10]
++ padframe/mprj_io_ib_mode_sel[10] padframe/mprj_io_in[10] padframe/mprj_io_inp_dis[10]
++ padframe/mprj_io_out[10] padframe/mprj_io_oeb[10] padframe/mprj_io_slow_sel[10]
++ padframe/mprj_io_vtrip_sel[10] gpio_control_in_1\[2\]/resetn gpio_control_in_1\[3\]/resetn
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_1\[3\]/serial_data_in gpio_control_in_1\[2\]/serial_load gpio_control_in_1\[3\]/serial_load
++ mprj/io_in[10] mprj/io_oeb[10] mprj/io_out[10] gpio_control_in_1\[2\]/vccd gpio_control_in_1\[2\]/vccd1
++ gpio_control_in_1\[2\]/vssd gpio_control_in_1\[2\]/vssd1 gpio_control_in_1\[2\]/zero
++ gpio_control_block
+Xgpio_28_defaults gpio_28_defaults/VGND gpio_28_defaults/VPWR gpio_28_defaults/gpio_defaults[0]
++ gpio_28_defaults/gpio_defaults[10] gpio_28_defaults/gpio_defaults[11] gpio_28_defaults/gpio_defaults[12]
++ gpio_28_defaults/gpio_defaults[1] gpio_28_defaults/gpio_defaults[2] gpio_28_defaults/gpio_defaults[3]
++ gpio_28_defaults/gpio_defaults[4] gpio_28_defaults/gpio_defaults[5] gpio_28_defaults/gpio_defaults[6]
++ gpio_28_defaults/gpio_defaults[7] gpio_28_defaults/gpio_defaults[8] gpio_28_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_12_defaults gpio_12_defaults/VGND gpio_12_defaults/VPWR gpio_12_defaults/gpio_defaults[0]
++ gpio_12_defaults/gpio_defaults[2] gpio_12_defaults/gpio_defaults[1] gpio_12_defaults/gpio_defaults[0]
++ gpio_12_defaults/gpio_defaults[1] gpio_12_defaults/gpio_defaults[2] gpio_12_defaults/gpio_defaults[9]
++ gpio_12_defaults/gpio_defaults[8] gpio_12_defaults/gpio_defaults[7] gpio_12_defaults/gpio_defaults[6]
++ gpio_12_defaults/gpio_defaults[7] gpio_12_defaults/gpio_defaults[8] gpio_12_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[10\] gpio_29_defaults/gpio_defaults[0] gpio_29_defaults/gpio_defaults[10]
++ gpio_29_defaults/gpio_defaults[11] gpio_29_defaults/gpio_defaults[12] gpio_29_defaults/gpio_defaults[1]
++ gpio_29_defaults/gpio_defaults[2] gpio_29_defaults/gpio_defaults[3] gpio_29_defaults/gpio_defaults[4]
++ gpio_29_defaults/gpio_defaults[5] gpio_29_defaults/gpio_defaults[6] gpio_29_defaults/gpio_defaults[7]
++ gpio_29_defaults/gpio_defaults[8] gpio_29_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[29]
++ gpio_control_in_2\[10\]/one housekeeping/mgmt_gpio_in[29] gpio_control_in_2\[10\]/one
++ padframe/mprj_io_analog_en[29] padframe/mprj_io_analog_pol[29] padframe/mprj_io_analog_sel[29]
++ padframe/mprj_io_dm[87] padframe/mprj_io_dm[88] padframe/mprj_io_dm[89] padframe/mprj_io_holdover[29]
++ padframe/mprj_io_ib_mode_sel[29] padframe/mprj_io_in[29] padframe/mprj_io_inp_dis[29]
++ padframe/mprj_io_out[29] padframe/mprj_io_oeb[29] padframe/mprj_io_slow_sel[29]
++ padframe/mprj_io_vtrip_sel[29] gpio_control_in_1\[2\]/resetn gpio_control_in_1\[3\]/resetn
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[3\]/serial_clock gpio_control_in_2\[10\]/serial_data_in
++ gpio_control_in_2\[9\]/serial_data_in gpio_control_in_1\[2\]/serial_load gpio_control_in_1\[3\]/serial_load
++ mprj/io_in[29] mprj/io_oeb[29] mprj/io_out[29] gpio_control_in_2\[10\]/vccd gpio_control_in_2\[10\]/vccd1
++ gpio_control_in_2\[10\]/vssd gpio_control_in_2\[10\]/vssd1 gpio_control_in_2\[10\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[10\] gpio_18_defaults/gpio_defaults[0] gpio_18_defaults/gpio_defaults[10]
++ gpio_18_defaults/gpio_defaults[11] gpio_18_defaults/gpio_defaults[12] gpio_18_defaults/gpio_defaults[1]
++ gpio_18_defaults/gpio_defaults[2] gpio_18_defaults/gpio_defaults[3] gpio_18_defaults/gpio_defaults[4]
++ gpio_18_defaults/gpio_defaults[5] gpio_18_defaults/gpio_defaults[6] gpio_18_defaults/gpio_defaults[7]
++ gpio_18_defaults/gpio_defaults[8] gpio_18_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[18]
++ gpio_control_in_1\[10\]/one housekeeping/mgmt_gpio_in[18] gpio_control_in_1\[10\]/one
++ padframe/mprj_io_analog_en[18] padframe/mprj_io_analog_pol[18] padframe/mprj_io_analog_sel[18]
++ padframe/mprj_io_dm[54] padframe/mprj_io_dm[55] padframe/mprj_io_dm[56] padframe/mprj_io_holdover[18]
++ padframe/mprj_io_ib_mode_sel[18] padframe/mprj_io_in[18] padframe/mprj_io_inp_dis[18]
++ padframe/mprj_io_out[18] padframe/mprj_io_oeb[18] padframe/mprj_io_slow_sel[18]
++ padframe/mprj_io_vtrip_sel[18] gpio_control_in_1\[10\]/resetn gpio_control_in_1\[10\]/resetn_out
++ gpio_control_in_1\[10\]/serial_clock gpio_control_in_1\[10\]/serial_clock_out gpio_control_in_1\[9\]/serial_data_out
++ gpio_control_in_1\[10\]/serial_data_out gpio_control_in_1\[10\]/serial_load gpio_control_in_1\[10\]/serial_load_out
++ mprj/io_in[18] mprj/io_oeb[18] mprj/io_out[18] gpio_control_in_1\[10\]/vccd gpio_control_in_1\[10\]/vccd1
++ gpio_control_in_1\[10\]/vssd gpio_control_in_1\[10\]/vssd1 gpio_control_in_1\[10\]/zero
++ gpio_control_block
+Xgpio_control_in_2\[5\] gpio_24_defaults/gpio_defaults[0] gpio_24_defaults/gpio_defaults[10]
++ gpio_24_defaults/gpio_defaults[11] gpio_24_defaults/gpio_defaults[12] gpio_24_defaults/gpio_defaults[1]
++ gpio_24_defaults/gpio_defaults[2] gpio_24_defaults/gpio_defaults[3] gpio_24_defaults/gpio_defaults[4]
++ gpio_24_defaults/gpio_defaults[5] gpio_24_defaults/gpio_defaults[6] gpio_24_defaults/gpio_defaults[7]
++ gpio_24_defaults/gpio_defaults[8] gpio_24_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[24]
++ gpio_control_in_2\[5\]/one housekeeping/mgmt_gpio_in[24] gpio_control_in_2\[5\]/one
++ padframe/mprj_io_analog_en[24] padframe/mprj_io_analog_pol[24] padframe/mprj_io_analog_sel[24]
++ padframe/mprj_io_dm[72] padframe/mprj_io_dm[73] padframe/mprj_io_dm[74] padframe/mprj_io_holdover[24]
++ padframe/mprj_io_ib_mode_sel[24] padframe/mprj_io_in[24] padframe/mprj_io_inp_dis[24]
++ padframe/mprj_io_out[24] padframe/mprj_io_oeb[24] padframe/mprj_io_slow_sel[24]
++ padframe/mprj_io_vtrip_sel[24] gpio_control_in_2\[5\]/resetn gpio_control_in_2\[6\]/resetn
++ gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[5\]/serial_data_in
++ gpio_control_in_2\[4\]/serial_data_in gpio_control_in_2\[5\]/serial_load gpio_control_in_2\[6\]/serial_load
++ mprj/io_in[24] mprj/io_oeb[24] mprj/io_out[24] gpio_control_in_2\[5\]/vccd gpio_control_in_2\[5\]/vccd1
++ gpio_control_in_2\[5\]/vssd gpio_control_in_2\[5\]/vssd1 gpio_control_in_2\[5\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[0\] gpio_8_defaults/gpio_defaults[0] gpio_8_defaults/gpio_defaults[2]
++ gpio_8_defaults/gpio_defaults[1] gpio_8_defaults/gpio_defaults[0] gpio_8_defaults/gpio_defaults[1]
++ gpio_8_defaults/gpio_defaults[2] gpio_8_defaults/gpio_defaults[9] gpio_8_defaults/gpio_defaults[8]
++ gpio_8_defaults/gpio_defaults[7] gpio_8_defaults/gpio_defaults[6] gpio_8_defaults/gpio_defaults[7]
++ gpio_8_defaults/gpio_defaults[8] gpio_8_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[8]
++ gpio_control_in_1\[0\]/one housekeeping/mgmt_gpio_in[8] gpio_control_in_1\[0\]/one
++ padframe/mprj_io_analog_en[8] padframe/mprj_io_analog_pol[8] padframe/mprj_io_analog_sel[8]
++ padframe/mprj_io_dm[24] padframe/mprj_io_dm[25] padframe/mprj_io_dm[26] padframe/mprj_io_holdover[8]
++ padframe/mprj_io_ib_mode_sel[8] padframe/mprj_io_in[8] padframe/mprj_io_inp_dis[8]
++ padframe/mprj_io_out[8] padframe/mprj_io_oeb[8] padframe/mprj_io_slow_sel[8] padframe/mprj_io_vtrip_sel[8]
++ gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn gpio_control_in_2\[8\]/serial_clock
++ gpio_control_in_2\[9\]/serial_clock gpio_control_in_1\[0\]/serial_data_in gpio_control_in_1\[1\]/serial_data_in
++ gpio_control_in_2\[8\]/serial_load gpio_control_in_2\[9\]/serial_load mprj/io_in[8]
++ mprj/io_oeb[8] mprj/io_out[8] gpio_control_in_1\[0\]/vccd gpio_control_in_1\[0\]/vccd1
++ gpio_control_in_1\[0\]/vssd gpio_control_in_1\[0\]/vssd1 gpio_control_in_1\[0\]/zero
++ gpio_control_block
+Xgpio_37_defaults gpio_37_defaults/VGND gpio_37_defaults/VPWR gpio_37_defaults/gpio_defaults[0]
++ gpio_37_defaults/gpio_defaults[10] gpio_37_defaults/gpio_defaults[11] gpio_37_defaults/gpio_defaults[12]
++ gpio_37_defaults/gpio_defaults[1] gpio_37_defaults/gpio_defaults[2] gpio_37_defaults/gpio_defaults[3]
++ gpio_37_defaults/gpio_defaults[4] gpio_37_defaults/gpio_defaults[5] gpio_37_defaults/gpio_defaults[6]
++ gpio_37_defaults/gpio_defaults[7] gpio_37_defaults/gpio_defaults[8] gpio_37_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_21_defaults gpio_21_defaults/VGND gpio_21_defaults/VPWR gpio_21_defaults/gpio_defaults[0]
++ gpio_21_defaults/gpio_defaults[10] gpio_21_defaults/gpio_defaults[11] gpio_21_defaults/gpio_defaults[12]
++ gpio_21_defaults/gpio_defaults[1] gpio_21_defaults/gpio_defaults[2] gpio_21_defaults/gpio_defaults[3]
++ gpio_21_defaults/gpio_defaults[4] gpio_21_defaults/gpio_defaults[5] gpio_21_defaults/gpio_defaults[6]
++ gpio_21_defaults/gpio_defaults[7] gpio_21_defaults/gpio_defaults[8] gpio_21_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xuser_id_value user_id_value/mask_rev[0] user_id_value/mask_rev[10] user_id_value/mask_rev[11]
++ user_id_value/mask_rev[12] user_id_value/mask_rev[13] user_id_value/mask_rev[14]
++ user_id_value/mask_rev[15] user_id_value/mask_rev[16] user_id_value/mask_rev[17]
++ user_id_value/mask_rev[18] user_id_value/mask_rev[19] user_id_value/mask_rev[1]
++ user_id_value/mask_rev[20] user_id_value/mask_rev[21] user_id_value/mask_rev[22]
++ user_id_value/mask_rev[23] user_id_value/mask_rev[24] user_id_value/mask_rev[25]
++ user_id_value/mask_rev[26] user_id_value/mask_rev[27] user_id_value/mask_rev[28]
++ user_id_value/mask_rev[29] user_id_value/mask_rev[2] user_id_value/mask_rev[30]
++ user_id_value/mask_rev[31] user_id_value/mask_rev[3] user_id_value/mask_rev[4] user_id_value/mask_rev[5]
++ user_id_value/mask_rev[6] user_id_value/mask_rev[7] user_id_value/mask_rev[8] user_id_value/mask_rev[9]
++ user_id_value/VPWR user_id_value/VGND user_id_programming
+Xgpio_control_in_2\[3\] gpio_22_defaults/gpio_defaults[0] gpio_22_defaults/gpio_defaults[10]
++ gpio_22_defaults/gpio_defaults[11] gpio_22_defaults/gpio_defaults[12] gpio_22_defaults/gpio_defaults[1]
++ gpio_22_defaults/gpio_defaults[2] gpio_22_defaults/gpio_defaults[3] gpio_22_defaults/gpio_defaults[4]
++ gpio_22_defaults/gpio_defaults[5] gpio_22_defaults/gpio_defaults[6] gpio_22_defaults/gpio_defaults[7]
++ gpio_22_defaults/gpio_defaults[8] gpio_22_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[22]
++ gpio_control_in_2\[3\]/one housekeeping/mgmt_gpio_in[22] gpio_control_in_2\[3\]/one
++ padframe/mprj_io_analog_en[22] padframe/mprj_io_analog_pol[22] padframe/mprj_io_analog_sel[22]
++ padframe/mprj_io_dm[66] padframe/mprj_io_dm[67] padframe/mprj_io_dm[68] padframe/mprj_io_holdover[22]
++ padframe/mprj_io_ib_mode_sel[22] padframe/mprj_io_in[22] padframe/mprj_io_inp_dis[22]
++ padframe/mprj_io_out[22] padframe/mprj_io_oeb[22] padframe/mprj_io_slow_sel[22]
++ padframe/mprj_io_vtrip_sel[22] gpio_control_in_2\[3\]/resetn gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[3\]/serial_data_in
++ gpio_control_in_2\[2\]/serial_data_in gpio_control_in_2\[3\]/serial_load gpio_control_in_2\[4\]/serial_load
++ mprj/io_in[22] mprj/io_oeb[22] mprj/io_out[22] gpio_control_in_2\[3\]/vccd gpio_control_in_2\[3\]/vccd1
++ gpio_control_in_2\[3\]/vssd gpio_control_in_2\[3\]/vssd1 gpio_control_in_2\[3\]/zero
++ gpio_control_block
+Xgpio_7_defaults gpio_7_defaults/VGND gpio_7_defaults/VPWR gpio_7_defaults/gpio_defaults[0]
++ gpio_7_defaults/gpio_defaults[2] gpio_7_defaults/gpio_defaults[1] gpio_7_defaults/gpio_defaults[0]
++ gpio_7_defaults/gpio_defaults[1] gpio_7_defaults/gpio_defaults[2] gpio_7_defaults/gpio_defaults[9]
++ gpio_7_defaults/gpio_defaults[8] gpio_7_defaults/gpio_defaults[7] gpio_7_defaults/gpio_defaults[6]
++ gpio_7_defaults/gpio_defaults[7] gpio_7_defaults/gpio_defaults[8] gpio_7_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_15_defaults gpio_15_defaults/VGND gpio_15_defaults/VPWR gpio_15_defaults/gpio_defaults[0]
++ gpio_15_defaults/gpio_defaults[10] gpio_15_defaults/gpio_defaults[11] gpio_15_defaults/gpio_defaults[12]
++ gpio_15_defaults/gpio_defaults[1] gpio_15_defaults/gpio_defaults[2] gpio_15_defaults/gpio_defaults[3]
++ gpio_15_defaults/gpio_defaults[4] gpio_15_defaults/gpio_defaults[5] gpio_15_defaults/gpio_defaults[6]
++ gpio_15_defaults/gpio_defaults[7] gpio_15_defaults/gpio_defaults[8] gpio_15_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_30_defaults gpio_30_defaults/VGND gpio_30_defaults/VPWR gpio_30_defaults/gpio_defaults[0]
++ gpio_30_defaults/gpio_defaults[10] gpio_30_defaults/gpio_defaults[11] gpio_30_defaults/gpio_defaults[12]
++ gpio_30_defaults/gpio_defaults[1] gpio_30_defaults/gpio_defaults[2] gpio_30_defaults/gpio_defaults[3]
++ gpio_30_defaults/gpio_defaults[4] gpio_30_defaults/gpio_defaults[5] gpio_30_defaults/gpio_defaults[6]
++ gpio_30_defaults/gpio_defaults[7] gpio_30_defaults/gpio_defaults[8] gpio_30_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_1\[0\] gpio_01_defaults\[0\]/gpio_defaults[0] gpio_01_defaults\[0\]/gpio_defaults[2]
++ gpio_01_defaults\[0\]/gpio_defaults[1] gpio_01_defaults\[0\]/gpio_defaults[0] gpio_01_defaults\[0\]/gpio_defaults[1]
++ gpio_01_defaults\[0\]/gpio_defaults[2] gpio_01_defaults\[0\]/gpio_defaults[9] gpio_01_defaults\[0\]/gpio_defaults[8]
++ gpio_01_defaults\[0\]/gpio_defaults[7] gpio_01_defaults\[0\]/gpio_defaults[6] gpio_01_defaults\[0\]/gpio_defaults[7]
++ gpio_01_defaults\[0\]/gpio_defaults[8] gpio_01_defaults\[0\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[0]
++ housekeeping/mgmt_gpio_oeb[0] housekeeping/mgmt_gpio_out[0] gpio_control_bidir_1\[0\]/one
++ padframe/mprj_io_analog_en[0] padframe/mprj_io_analog_pol[0] padframe/mprj_io_analog_sel[0]
++ padframe/mprj_io_dm[0] padframe/mprj_io_dm[1] padframe/mprj_io_dm[2] padframe/mprj_io_holdover[0]
++ padframe/mprj_io_ib_mode_sel[0] padframe/mprj_io_in[0] padframe/mprj_io_inp_dis[0]
++ padframe/mprj_io_out[0] padframe/mprj_io_oeb[0] padframe/mprj_io_slow_sel[0] padframe/mprj_io_vtrip_sel[0]
++ housekeeping/serial_resetn gpio_control_in_2\[1\]/resetn housekeeping/serial_clock
++ gpio_control_in_2\[1\]/serial_clock housekeeping/serial_data_1 gpio_control_bidir_1\[1\]/serial_data_in
++ housekeeping/serial_load gpio_control_in_2\[1\]/serial_load mprj/io_in[0] mprj/io_oeb[0]
++ mprj/io_out[0] gpio_control_bidir_1\[0\]/vccd gpio_control_bidir_1\[0\]/vccd1 gpio_control_bidir_1\[0\]/vssd
++ gpio_control_bidir_1\[0\]/vssd1 gpio_control_bidir_1\[0\]/zero gpio_control_block
+Xgpio_control_in_1\[9\] gpio_17_defaults/gpio_defaults[0] gpio_17_defaults/gpio_defaults[10]
++ gpio_17_defaults/gpio_defaults[11] gpio_17_defaults/gpio_defaults[12] gpio_17_defaults/gpio_defaults[1]
++ gpio_17_defaults/gpio_defaults[2] gpio_17_defaults/gpio_defaults[3] gpio_17_defaults/gpio_defaults[4]
++ gpio_17_defaults/gpio_defaults[5] gpio_17_defaults/gpio_defaults[6] gpio_17_defaults/gpio_defaults[7]
++ gpio_17_defaults/gpio_defaults[8] gpio_17_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[17]
++ gpio_control_in_1\[9\]/one housekeeping/mgmt_gpio_in[17] gpio_control_in_1\[9\]/one
++ padframe/mprj_io_analog_en[17] padframe/mprj_io_analog_pol[17] padframe/mprj_io_analog_sel[17]
++ padframe/mprj_io_dm[51] padframe/mprj_io_dm[52] padframe/mprj_io_dm[53] padframe/mprj_io_holdover[17]
++ padframe/mprj_io_ib_mode_sel[17] padframe/mprj_io_in[17] padframe/mprj_io_inp_dis[17]
++ padframe/mprj_io_out[17] padframe/mprj_io_oeb[17] padframe/mprj_io_slow_sel[17]
++ padframe/mprj_io_vtrip_sel[17] gpio_control_in_1\[9\]/resetn gpio_control_in_1\[10\]/resetn
++ gpio_control_in_1\[9\]/serial_clock gpio_control_in_1\[10\]/serial_clock gpio_control_in_1\[9\]/serial_data_in
++ gpio_control_in_1\[9\]/serial_data_out gpio_control_in_1\[9\]/serial_load gpio_control_in_1\[10\]/serial_load
++ mprj/io_in[17] mprj/io_oeb[17] mprj/io_out[17] gpio_control_in_1\[9\]/vccd gpio_control_in_1\[9\]/vccd1
++ gpio_control_in_1\[9\]/vssd gpio_control_in_1\[9\]/vssd1 gpio_control_in_1\[9\]/zero
++ gpio_control_block
+Xgpio_01_defaults\[1\] gpio_01_defaults\[1\]/VGND gpio_01_defaults\[1\]/VPWR gpio_01_defaults\[1\]/gpio_defaults[0]
++ gpio_01_defaults\[1\]/gpio_defaults[2] gpio_01_defaults\[1\]/gpio_defaults[1] gpio_01_defaults\[1\]/gpio_defaults[0]
++ gpio_01_defaults\[1\]/gpio_defaults[1] gpio_01_defaults\[1\]/gpio_defaults[2] gpio_01_defaults\[1\]/gpio_defaults[9]
++ gpio_01_defaults\[1\]/gpio_defaults[8] gpio_01_defaults\[1\]/gpio_defaults[7] gpio_01_defaults\[1\]/gpio_defaults[6]
++ gpio_01_defaults\[1\]/gpio_defaults[7] gpio_01_defaults\[1\]/gpio_defaults[8] gpio_01_defaults\[1\]/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[1\] gpio_20_defaults/gpio_defaults[0] gpio_20_defaults/gpio_defaults[10]
++ gpio_20_defaults/gpio_defaults[11] gpio_20_defaults/gpio_defaults[12] gpio_20_defaults/gpio_defaults[1]
++ gpio_20_defaults/gpio_defaults[2] gpio_20_defaults/gpio_defaults[3] gpio_20_defaults/gpio_defaults[4]
++ gpio_20_defaults/gpio_defaults[5] gpio_20_defaults/gpio_defaults[6] gpio_20_defaults/gpio_defaults[7]
++ gpio_20_defaults/gpio_defaults[8] gpio_20_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[20]
++ gpio_control_in_2\[1\]/one housekeeping/mgmt_gpio_in[20] gpio_control_in_2\[1\]/one
++ padframe/mprj_io_analog_en[20] padframe/mprj_io_analog_pol[20] padframe/mprj_io_analog_sel[20]
++ padframe/mprj_io_dm[60] padframe/mprj_io_dm[61] padframe/mprj_io_dm[62] padframe/mprj_io_holdover[20]
++ padframe/mprj_io_ib_mode_sel[20] padframe/mprj_io_in[20] padframe/mprj_io_inp_dis[20]
++ padframe/mprj_io_out[20] padframe/mprj_io_oeb[20] padframe/mprj_io_slow_sel[20]
++ padframe/mprj_io_vtrip_sel[20] gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[1\]/serial_clock gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[1\]/serial_data_in
++ gpio_control_in_2\[0\]/serial_data_in gpio_control_in_2\[1\]/serial_load gpio_control_in_2\[2\]/serial_load
++ mprj/io_in[20] mprj/io_oeb[20] mprj/io_out[20] gpio_control_in_2\[1\]/vccd gpio_control_in_2\[1\]/vccd1
++ gpio_control_in_2\[1\]/vssd gpio_control_in_2\[1\]/vssd1 gpio_control_in_2\[1\]/zero
++ gpio_control_block
+Xgpio_24_defaults gpio_24_defaults/VGND gpio_24_defaults/VPWR gpio_24_defaults/gpio_defaults[0]
++ gpio_24_defaults/gpio_defaults[10] gpio_24_defaults/gpio_defaults[11] gpio_24_defaults/gpio_defaults[12]
++ gpio_24_defaults/gpio_defaults[1] gpio_24_defaults/gpio_defaults[2] gpio_24_defaults/gpio_defaults[3]
++ gpio_24_defaults/gpio_defaults[4] gpio_24_defaults/gpio_defaults[5] gpio_24_defaults/gpio_defaults[6]
++ gpio_24_defaults/gpio_defaults[7] gpio_24_defaults/gpio_defaults[8] gpio_24_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_18_defaults gpio_18_defaults/VGND gpio_18_defaults/VPWR gpio_18_defaults/gpio_defaults[0]
++ gpio_18_defaults/gpio_defaults[10] gpio_18_defaults/gpio_defaults[11] gpio_18_defaults/gpio_defaults[12]
++ gpio_18_defaults/gpio_defaults[1] gpio_18_defaults/gpio_defaults[2] gpio_18_defaults/gpio_defaults[3]
++ gpio_18_defaults/gpio_defaults[4] gpio_18_defaults/gpio_defaults[5] gpio_18_defaults/gpio_defaults[6]
++ gpio_18_defaults/gpio_defaults[7] gpio_18_defaults/gpio_defaults[8] gpio_18_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_33_defaults gpio_33_defaults/VGND gpio_33_defaults/VPWR gpio_33_defaults/gpio_defaults[0]
++ gpio_33_defaults/gpio_defaults[10] gpio_33_defaults/gpio_defaults[11] gpio_33_defaults/gpio_defaults[12]
++ gpio_33_defaults/gpio_defaults[1] gpio_33_defaults/gpio_defaults[2] gpio_33_defaults/gpio_defaults[3]
++ gpio_33_defaults/gpio_defaults[4] gpio_33_defaults/gpio_defaults[5] gpio_33_defaults/gpio_defaults[6]
++ gpio_33_defaults/gpio_defaults[7] gpio_33_defaults/gpio_defaults[8] gpio_33_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[7\] gpio_15_defaults/gpio_defaults[0] gpio_15_defaults/gpio_defaults[10]
++ gpio_15_defaults/gpio_defaults[11] gpio_15_defaults/gpio_defaults[12] gpio_15_defaults/gpio_defaults[1]
++ gpio_15_defaults/gpio_defaults[2] gpio_15_defaults/gpio_defaults[3] gpio_15_defaults/gpio_defaults[4]
++ gpio_15_defaults/gpio_defaults[5] gpio_15_defaults/gpio_defaults[6] gpio_15_defaults/gpio_defaults[7]
++ gpio_15_defaults/gpio_defaults[8] gpio_15_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[15]
++ gpio_control_in_1\[7\]/one housekeeping/mgmt_gpio_in[15] gpio_control_in_1\[7\]/one
++ padframe/mprj_io_analog_en[15] padframe/mprj_io_analog_pol[15] padframe/mprj_io_analog_sel[15]
++ padframe/mprj_io_dm[45] padframe/mprj_io_dm[46] padframe/mprj_io_dm[47] padframe/mprj_io_holdover[15]
++ padframe/mprj_io_ib_mode_sel[15] padframe/mprj_io_in[15] padframe/mprj_io_inp_dis[15]
++ padframe/mprj_io_out[15] padframe/mprj_io_oeb[15] padframe/mprj_io_slow_sel[15]
++ padframe/mprj_io_vtrip_sel[15] gpio_control_in_1\[7\]/resetn gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[7\]/serial_clock gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[7\]/serial_data_in
++ gpio_control_in_1\[8\]/serial_data_in gpio_control_in_1\[7\]/serial_load gpio_control_in_1\[8\]/serial_load
++ mprj/io_in[15] mprj/io_oeb[15] mprj/io_out[15] gpio_control_in_1\[7\]/vccd gpio_control_in_1\[7\]/vccd1
++ gpio_control_in_1\[7\]/vssd gpio_control_in_1\[7\]/vssd1 gpio_control_in_1\[7\]/zero
++ gpio_control_block
+Xgpio_control_in_1a\[4\] gpio_6_defaults/gpio_defaults[0] gpio_6_defaults/gpio_defaults[2]
++ gpio_6_defaults/gpio_defaults[1] gpio_6_defaults/gpio_defaults[0] gpio_6_defaults/gpio_defaults[1]
++ gpio_6_defaults/gpio_defaults[2] gpio_6_defaults/gpio_defaults[9] gpio_6_defaults/gpio_defaults[8]
++ gpio_6_defaults/gpio_defaults[7] gpio_6_defaults/gpio_defaults[6] gpio_6_defaults/gpio_defaults[7]
++ gpio_6_defaults/gpio_defaults[8] gpio_6_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[6]
++ gpio_control_in_1a\[4\]/one housekeeping/mgmt_gpio_in[6] gpio_control_in_1a\[4\]/one
++ padframe/mprj_io_analog_en[6] padframe/mprj_io_analog_pol[6] padframe/mprj_io_analog_sel[6]
++ padframe/mprj_io_dm[18] padframe/mprj_io_dm[19] padframe/mprj_io_dm[20] padframe/mprj_io_holdover[6]
++ padframe/mprj_io_ib_mode_sel[6] padframe/mprj_io_in[6] padframe/mprj_io_inp_dis[6]
++ padframe/mprj_io_out[6] padframe/mprj_io_oeb[6] padframe/mprj_io_slow_sel[6] padframe/mprj_io_vtrip_sel[6]
++ gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn gpio_control_in_2\[6\]/serial_clock
++ gpio_control_in_2\[7\]/serial_clock gpio_control_in_1a\[4\]/serial_data_in gpio_control_in_1a\[5\]/serial_data_in
++ gpio_control_in_2\[6\]/serial_load gpio_control_in_2\[7\]/serial_load mprj/io_in[6]
++ mprj/io_oeb[6] mprj/io_out[6] gpio_control_in_1a\[4\]/vccd gpio_control_in_1a\[4\]/vccd1
++ gpio_control_in_1a\[4\]/vssd gpio_control_in_1a\[4\]/vssd1 gpio_control_in_1a\[4\]/zero
++ gpio_control_block
+Xgpio_234_defaults\[2\] gpio_234_defaults\[2\]/VGND gpio_234_defaults\[2\]/VPWR gpio_234_defaults\[2\]/gpio_defaults[0]
++ gpio_234_defaults\[2\]/gpio_defaults[2] gpio_234_defaults\[2\]/gpio_defaults[1]
++ gpio_234_defaults\[2\]/gpio_defaults[0] gpio_234_defaults\[2\]/gpio_defaults[1]
++ gpio_234_defaults\[2\]/gpio_defaults[2] gpio_234_defaults\[2\]/gpio_defaults[9]
++ gpio_234_defaults\[2\]/gpio_defaults[8] gpio_234_defaults\[2\]/gpio_defaults[7]
++ gpio_234_defaults\[2\]/gpio_defaults[6] gpio_234_defaults\[2\]/gpio_defaults[7]
++ gpio_234_defaults\[2\]/gpio_defaults[8] gpio_234_defaults\[2\]/gpio_defaults[9]
++ gpio_defaults_block
+Xmgmt_buffers soc/core_clk clocking/user_clk soc/core_rstn mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] soc/la_input[0] soc/la_input[100] soc/la_input[101]
++ soc/la_input[102] soc/la_input[103] soc/la_input[104] soc/la_input[105] soc/la_input[106]
++ soc/la_input[107] soc/la_input[108] soc/la_input[109] soc/la_input[10] soc/la_input[110]
++ soc/la_input[111] soc/la_input[112] soc/la_input[113] soc/la_input[114] soc/la_input[115]
++ soc/la_input[116] soc/la_input[117] soc/la_input[118] soc/la_input[119] soc/la_input[11]
++ soc/la_input[120] soc/la_input[121] soc/la_input[122] soc/la_input[123] soc/la_input[124]
++ soc/la_input[125] soc/la_input[126] soc/la_input[127] soc/la_input[12] soc/la_input[13]
++ soc/la_input[14] soc/la_input[15] soc/la_input[16] soc/la_input[17] soc/la_input[18]
++ soc/la_input[19] soc/la_input[1] soc/la_input[20] soc/la_input[21] soc/la_input[22]
++ soc/la_input[23] soc/la_input[24] soc/la_input[25] soc/la_input[26] soc/la_input[27]
++ soc/la_input[28] soc/la_input[29] soc/la_input[2] soc/la_input[30] soc/la_input[31]
++ soc/la_input[32] soc/la_input[33] soc/la_input[34] soc/la_input[35] soc/la_input[36]
++ soc/la_input[37] soc/la_input[38] soc/la_input[39] soc/la_input[3] soc/la_input[40]
++ soc/la_input[41] soc/la_input[42] soc/la_input[43] soc/la_input[44] soc/la_input[45]
++ soc/la_input[46] soc/la_input[47] soc/la_input[48] soc/la_input[49] soc/la_input[4]
++ soc/la_input[50] soc/la_input[51] soc/la_input[52] soc/la_input[53] soc/la_input[54]
++ soc/la_input[55] soc/la_input[56] soc/la_input[57] soc/la_input[58] soc/la_input[59]
++ soc/la_input[5] soc/la_input[60] soc/la_input[61] soc/la_input[62] soc/la_input[63]
++ soc/la_input[64] soc/la_input[65] soc/la_input[66] soc/la_input[67] soc/la_input[68]
++ soc/la_input[69] soc/la_input[6] soc/la_input[70] soc/la_input[71] soc/la_input[72]
++ soc/la_input[73] soc/la_input[74] soc/la_input[75] soc/la_input[76] soc/la_input[77]
++ soc/la_input[78] soc/la_input[79] soc/la_input[7] soc/la_input[80] soc/la_input[81]
++ soc/la_input[82] soc/la_input[83] soc/la_input[84] soc/la_input[85] soc/la_input[86]
++ soc/la_input[87] soc/la_input[88] soc/la_input[89] soc/la_input[8] soc/la_input[90]
++ soc/la_input[91] soc/la_input[92] soc/la_input[93] soc/la_input[94] soc/la_input[95]
++ soc/la_input[96] soc/la_input[97] soc/la_input[98] soc/la_input[99] soc/la_input[9]
++ mprj/la_data_out[0] mprj/la_data_out[100] mprj/la_data_out[101] mprj/la_data_out[102]
++ mprj/la_data_out[103] mprj/la_data_out[104] mprj/la_data_out[105] mprj/la_data_out[106]
++ mprj/la_data_out[107] mprj/la_data_out[108] mprj/la_data_out[109] mprj/la_data_out[10]
++ mprj/la_data_out[110] mprj/la_data_out[111] mprj/la_data_out[112] mprj/la_data_out[113]
++ mprj/la_data_out[114] mprj/la_data_out[115] mprj/la_data_out[116] mprj/la_data_out[117]
++ mprj/la_data_out[118] mprj/la_data_out[119] mprj/la_data_out[11] mprj/la_data_out[120]
++ mprj/la_data_out[121] mprj/la_data_out[122] mprj/la_data_out[123] mprj/la_data_out[124]
++ mprj/la_data_out[125] mprj/la_data_out[126] mprj/la_data_out[127] mprj/la_data_out[12]
++ mprj/la_data_out[13] mprj/la_data_out[14] mprj/la_data_out[15] mprj/la_data_out[16]
++ mprj/la_data_out[17] mprj/la_data_out[18] mprj/la_data_out[19] mprj/la_data_out[1]
++ mprj/la_data_out[20] mprj/la_data_out[21] mprj/la_data_out[22] mprj/la_data_out[23]
++ mprj/la_data_out[24] mprj/la_data_out[25] mprj/la_data_out[26] mprj/la_data_out[27]
++ mprj/la_data_out[28] mprj/la_data_out[29] mprj/la_data_out[2] mprj/la_data_out[30]
++ mprj/la_data_out[31] mprj/la_data_out[32] mprj/la_data_out[33] mprj/la_data_out[34]
++ mprj/la_data_out[35] mprj/la_data_out[36] mprj/la_data_out[37] mprj/la_data_out[38]
++ mprj/la_data_out[39] mprj/la_data_out[3] mprj/la_data_out[40] mprj/la_data_out[41]
++ mprj/la_data_out[42] mprj/la_data_out[43] mprj/la_data_out[44] mprj/la_data_out[45]
++ mprj/la_data_out[46] mprj/la_data_out[47] mprj/la_data_out[48] mprj/la_data_out[49]
++ mprj/la_data_out[4] mprj/la_data_out[50] mprj/la_data_out[51] mprj/la_data_out[52]
++ mprj/la_data_out[53] mprj/la_data_out[54] mprj/la_data_out[55] mprj/la_data_out[56]
++ mprj/la_data_out[57] mprj/la_data_out[58] mprj/la_data_out[59] mprj/la_data_out[5]
++ mprj/la_data_out[60] mprj/la_data_out[61] mprj/la_data_out[62] mprj/la_data_out[63]
++ mprj/la_data_out[64] mprj/la_data_out[65] mprj/la_data_out[66] mprj/la_data_out[67]
++ mprj/la_data_out[68] mprj/la_data_out[69] mprj/la_data_out[6] mprj/la_data_out[70]
++ mprj/la_data_out[71] mprj/la_data_out[72] mprj/la_data_out[73] mprj/la_data_out[74]
++ mprj/la_data_out[75] mprj/la_data_out[76] mprj/la_data_out[77] mprj/la_data_out[78]
++ mprj/la_data_out[79] mprj/la_data_out[7] mprj/la_data_out[80] mprj/la_data_out[81]
++ mprj/la_data_out[82] mprj/la_data_out[83] mprj/la_data_out[84] mprj/la_data_out[85]
++ mprj/la_data_out[86] mprj/la_data_out[87] mprj/la_data_out[88] mprj/la_data_out[89]
++ mprj/la_data_out[8] mprj/la_data_out[90] mprj/la_data_out[91] mprj/la_data_out[92]
++ mprj/la_data_out[93] mprj/la_data_out[94] mprj/la_data_out[95] mprj/la_data_out[96]
++ mprj/la_data_out[97] mprj/la_data_out[98] mprj/la_data_out[99] mprj/la_data_out[9]
++ soc/la_output[0] soc/la_output[100] soc/la_output[101] soc/la_output[102] soc/la_output[103]
++ soc/la_output[104] soc/la_output[105] soc/la_output[106] soc/la_output[107] soc/la_output[108]
++ soc/la_output[109] soc/la_output[10] soc/la_output[110] soc/la_output[111] soc/la_output[112]
++ soc/la_output[113] soc/la_output[114] soc/la_output[115] soc/la_output[116] soc/la_output[117]
++ soc/la_output[118] soc/la_output[119] soc/la_output[11] soc/la_output[120] soc/la_output[121]
++ soc/la_output[122] soc/la_output[123] soc/la_output[124] soc/la_output[125] soc/la_output[126]
++ soc/la_output[127] soc/la_output[12] soc/la_output[13] soc/la_output[14] soc/la_output[15]
++ soc/la_output[16] soc/la_output[17] soc/la_output[18] soc/la_output[19] soc/la_output[1]
++ soc/la_output[20] soc/la_output[21] soc/la_output[22] soc/la_output[23] soc/la_output[24]
++ soc/la_output[25] soc/la_output[26] soc/la_output[27] soc/la_output[28] soc/la_output[29]
++ soc/la_output[2] soc/la_output[30] soc/la_output[31] soc/la_output[32] soc/la_output[33]
++ soc/la_output[34] soc/la_output[35] soc/la_output[36] soc/la_output[37] soc/la_output[38]
++ soc/la_output[39] soc/la_output[3] soc/la_output[40] soc/la_output[41] soc/la_output[42]
++ soc/la_output[43] soc/la_output[44] soc/la_output[45] soc/la_output[46] soc/la_output[47]
++ soc/la_output[48] soc/la_output[49] soc/la_output[4] soc/la_output[50] soc/la_output[51]
++ soc/la_output[52] soc/la_output[53] soc/la_output[54] soc/la_output[55] soc/la_output[56]
++ soc/la_output[57] soc/la_output[58] soc/la_output[59] soc/la_output[5] soc/la_output[60]
++ soc/la_output[61] soc/la_output[62] soc/la_output[63] soc/la_output[64] soc/la_output[65]
++ soc/la_output[66] soc/la_output[67] soc/la_output[68] soc/la_output[69] soc/la_output[6]
++ soc/la_output[70] soc/la_output[71] soc/la_output[72] soc/la_output[73] soc/la_output[74]
++ soc/la_output[75] soc/la_output[76] soc/la_output[77] soc/la_output[78] soc/la_output[79]
++ soc/la_output[7] soc/la_output[80] soc/la_output[81] soc/la_output[82] soc/la_output[83]
++ soc/la_output[84] soc/la_output[85] soc/la_output[86] soc/la_output[87] soc/la_output[88]
++ soc/la_output[89] soc/la_output[8] soc/la_output[90] soc/la_output[91] soc/la_output[92]
++ soc/la_output[93] soc/la_output[94] soc/la_output[95] soc/la_output[96] soc/la_output[97]
++ soc/la_output[98] soc/la_output[99] soc/la_output[9] soc/la_iena[0] soc/la_iena[100]
++ soc/la_iena[101] soc/la_iena[102] soc/la_iena[103] soc/la_iena[104] soc/la_iena[105]
++ soc/la_iena[106] soc/la_iena[107] soc/la_iena[108] soc/la_iena[109] soc/la_iena[10]
++ soc/la_iena[110] soc/la_iena[111] soc/la_iena[112] soc/la_iena[113] soc/la_iena[114]
++ soc/la_iena[115] soc/la_iena[116] soc/la_iena[117] soc/la_iena[118] soc/la_iena[119]
++ soc/la_iena[11] soc/la_iena[120] soc/la_iena[121] soc/la_iena[122] soc/la_iena[123]
++ soc/la_iena[124] soc/la_iena[125] soc/la_iena[126] soc/la_iena[127] soc/la_iena[12]
++ soc/la_iena[13] soc/la_iena[14] soc/la_iena[15] soc/la_iena[16] soc/la_iena[17]
++ soc/la_iena[18] soc/la_iena[19] soc/la_iena[1] soc/la_iena[20] soc/la_iena[21] soc/la_iena[22]
++ soc/la_iena[23] soc/la_iena[24] soc/la_iena[25] soc/la_iena[26] soc/la_iena[27]
++ soc/la_iena[28] soc/la_iena[29] soc/la_iena[2] soc/la_iena[30] soc/la_iena[31] soc/la_iena[32]
++ soc/la_iena[33] soc/la_iena[34] soc/la_iena[35] soc/la_iena[36] soc/la_iena[37]
++ soc/la_iena[38] soc/la_iena[39] soc/la_iena[3] soc/la_iena[40] soc/la_iena[41] soc/la_iena[42]
++ soc/la_iena[43] soc/la_iena[44] soc/la_iena[45] soc/la_iena[46] soc/la_iena[47]
++ soc/la_iena[48] soc/la_iena[49] soc/la_iena[4] soc/la_iena[50] soc/la_iena[51] soc/la_iena[52]
++ soc/la_iena[53] soc/la_iena[54] soc/la_iena[55] soc/la_iena[56] soc/la_iena[57]
++ soc/la_iena[58] soc/la_iena[59] soc/la_iena[5] soc/la_iena[60] soc/la_iena[61] soc/la_iena[62]
++ soc/la_iena[63] soc/la_iena[64] soc/la_iena[65] soc/la_iena[66] soc/la_iena[67]
++ soc/la_iena[68] soc/la_iena[69] soc/la_iena[6] soc/la_iena[70] soc/la_iena[71] soc/la_iena[72]
++ soc/la_iena[73] soc/la_iena[74] soc/la_iena[75] soc/la_iena[76] soc/la_iena[77]
++ soc/la_iena[78] soc/la_iena[79] soc/la_iena[7] soc/la_iena[80] soc/la_iena[81] soc/la_iena[82]
++ soc/la_iena[83] soc/la_iena[84] soc/la_iena[85] soc/la_iena[86] soc/la_iena[87]
++ soc/la_iena[88] soc/la_iena[89] soc/la_iena[8] soc/la_iena[90] soc/la_iena[91] soc/la_iena[92]
++ soc/la_iena[93] soc/la_iena[94] soc/la_iena[95] soc/la_iena[96] soc/la_iena[97]
++ soc/la_iena[98] soc/la_iena[99] soc/la_iena[9] mprj/la_oenb[0] mprj/la_oenb[100]
++ mprj/la_oenb[101] mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105]
++ mprj/la_oenb[106] mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10]
++ mprj/la_oenb[110] mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114]
++ mprj/la_oenb[115] mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119]
++ mprj/la_oenb[11] mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123]
++ mprj/la_oenb[124] mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12]
++ mprj/la_oenb[13] mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17]
++ mprj/la_oenb[18] mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21]
++ mprj/la_oenb[22] mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26]
++ mprj/la_oenb[27] mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30]
++ mprj/la_oenb[31] mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35]
++ mprj/la_oenb[36] mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3]
++ mprj/la_oenb[40] mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44]
++ mprj/la_oenb[45] mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49]
++ mprj/la_oenb[4] mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53]
++ mprj/la_oenb[54] mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58]
++ mprj/la_oenb[59] mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62]
++ mprj/la_oenb[63] mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67]
++ mprj/la_oenb[68] mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71]
++ mprj/la_oenb[72] mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76]
++ mprj/la_oenb[77] mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80]
++ mprj/la_oenb[81] mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85]
++ mprj/la_oenb[86] mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8]
++ mprj/la_oenb[90] mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94]
++ mprj/la_oenb[95] mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99]
++ mprj/la_oenb[9] soc/la_oenb[0] soc/la_oenb[100] soc/la_oenb[101] soc/la_oenb[102]
++ soc/la_oenb[103] soc/la_oenb[104] soc/la_oenb[105] soc/la_oenb[106] soc/la_oenb[107]
++ soc/la_oenb[108] soc/la_oenb[109] soc/la_oenb[10] soc/la_oenb[110] soc/la_oenb[111]
++ soc/la_oenb[112] soc/la_oenb[113] soc/la_oenb[114] soc/la_oenb[115] soc/la_oenb[116]
++ soc/la_oenb[117] soc/la_oenb[118] soc/la_oenb[119] soc/la_oenb[11] soc/la_oenb[120]
++ soc/la_oenb[121] soc/la_oenb[122] soc/la_oenb[123] soc/la_oenb[124] soc/la_oenb[125]
++ soc/la_oenb[126] soc/la_oenb[127] soc/la_oenb[12] soc/la_oenb[13] soc/la_oenb[14]
++ soc/la_oenb[15] soc/la_oenb[16] soc/la_oenb[17] soc/la_oenb[18] soc/la_oenb[19]
++ soc/la_oenb[1] soc/la_oenb[20] soc/la_oenb[21] soc/la_oenb[22] soc/la_oenb[23] soc/la_oenb[24]
++ soc/la_oenb[25] soc/la_oenb[26] soc/la_oenb[27] soc/la_oenb[28] soc/la_oenb[29]
++ soc/la_oenb[2] soc/la_oenb[30] soc/la_oenb[31] soc/la_oenb[32] soc/la_oenb[33] soc/la_oenb[34]
++ soc/la_oenb[35] soc/la_oenb[36] soc/la_oenb[37] soc/la_oenb[38] soc/la_oenb[39]
++ soc/la_oenb[3] soc/la_oenb[40] soc/la_oenb[41] soc/la_oenb[42] soc/la_oenb[43] soc/la_oenb[44]
++ soc/la_oenb[45] soc/la_oenb[46] soc/la_oenb[47] soc/la_oenb[48] soc/la_oenb[49]
++ soc/la_oenb[4] soc/la_oenb[50] soc/la_oenb[51] soc/la_oenb[52] soc/la_oenb[53] soc/la_oenb[54]
++ soc/la_oenb[55] soc/la_oenb[56] soc/la_oenb[57] soc/la_oenb[58] soc/la_oenb[59]
++ soc/la_oenb[5] soc/la_oenb[60] soc/la_oenb[61] soc/la_oenb[62] soc/la_oenb[63] soc/la_oenb[64]
++ soc/la_oenb[65] soc/la_oenb[66] soc/la_oenb[67] soc/la_oenb[68] soc/la_oenb[69]
++ soc/la_oenb[6] soc/la_oenb[70] soc/la_oenb[71] soc/la_oenb[72] soc/la_oenb[73] soc/la_oenb[74]
++ soc/la_oenb[75] soc/la_oenb[76] soc/la_oenb[77] soc/la_oenb[78] soc/la_oenb[79]
++ soc/la_oenb[7] soc/la_oenb[80] soc/la_oenb[81] soc/la_oenb[82] soc/la_oenb[83] soc/la_oenb[84]
++ soc/la_oenb[85] soc/la_oenb[86] soc/la_oenb[87] soc/la_oenb[88] soc/la_oenb[89]
++ soc/la_oenb[8] soc/la_oenb[90] soc/la_oenb[91] soc/la_oenb[92] soc/la_oenb[93] soc/la_oenb[94]
++ soc/la_oenb[95] soc/la_oenb[96] soc/la_oenb[97] soc/la_oenb[98] soc/la_oenb[99]
++ soc/la_oenb[9] soc/mprj_ack_i mprj/wbs_ack_o soc/mprj_adr_o[0] soc/mprj_adr_o[10]
++ soc/mprj_adr_o[11] soc/mprj_adr_o[12] soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15]
++ soc/mprj_adr_o[16] soc/mprj_adr_o[17] soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1]
++ soc/mprj_adr_o[20] soc/mprj_adr_o[21] soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24]
++ soc/mprj_adr_o[25] soc/mprj_adr_o[26] soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29]
++ soc/mprj_adr_o[2] soc/mprj_adr_o[30] soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4]
++ soc/mprj_adr_o[5] soc/mprj_adr_o[6] soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9]
++ mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11] mprj/wbs_adr_i[12] mprj/wbs_adr_i[13]
++ mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16] mprj/wbs_adr_i[17] mprj/wbs_adr_i[18]
++ mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20] mprj/wbs_adr_i[21] mprj/wbs_adr_i[22]
++ mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25] mprj/wbs_adr_i[26] mprj/wbs_adr_i[27]
++ mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2] mprj/wbs_adr_i[30] mprj/wbs_adr_i[31]
++ mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5] mprj/wbs_adr_i[6] mprj/wbs_adr_i[7]
++ mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] soc/mprj_cyc_o mprj/wbs_cyc_i soc/mprj_dat_i[0]
++ soc/mprj_dat_i[10] soc/mprj_dat_i[11] soc/mprj_dat_i[12] soc/mprj_dat_i[13] soc/mprj_dat_i[14]
++ soc/mprj_dat_i[15] soc/mprj_dat_i[16] soc/mprj_dat_i[17] soc/mprj_dat_i[18] soc/mprj_dat_i[19]
++ soc/mprj_dat_i[1] soc/mprj_dat_i[20] soc/mprj_dat_i[21] soc/mprj_dat_i[22] soc/mprj_dat_i[23]
++ soc/mprj_dat_i[24] soc/mprj_dat_i[25] soc/mprj_dat_i[26] soc/mprj_dat_i[27] soc/mprj_dat_i[28]
++ soc/mprj_dat_i[29] soc/mprj_dat_i[2] soc/mprj_dat_i[30] soc/mprj_dat_i[31] soc/mprj_dat_i[3]
++ soc/mprj_dat_i[4] soc/mprj_dat_i[5] soc/mprj_dat_i[6] soc/mprj_dat_i[7] soc/mprj_dat_i[8]
++ soc/mprj_dat_i[9] mprj/wbs_dat_o[0] mprj/wbs_dat_o[10] mprj/wbs_dat_o[11] mprj/wbs_dat_o[12]
++ mprj/wbs_dat_o[13] mprj/wbs_dat_o[14] mprj/wbs_dat_o[15] mprj/wbs_dat_o[16] mprj/wbs_dat_o[17]
++ mprj/wbs_dat_o[18] mprj/wbs_dat_o[19] mprj/wbs_dat_o[1] mprj/wbs_dat_o[20] mprj/wbs_dat_o[21]
++ mprj/wbs_dat_o[22] mprj/wbs_dat_o[23] mprj/wbs_dat_o[24] mprj/wbs_dat_o[25] mprj/wbs_dat_o[26]
++ mprj/wbs_dat_o[27] mprj/wbs_dat_o[28] mprj/wbs_dat_o[29] mprj/wbs_dat_o[2] mprj/wbs_dat_o[30]
++ mprj/wbs_dat_o[31] mprj/wbs_dat_o[3] mprj/wbs_dat_o[4] mprj/wbs_dat_o[5] mprj/wbs_dat_o[6]
++ mprj/wbs_dat_o[7] mprj/wbs_dat_o[8] mprj/wbs_dat_o[9] soc/mprj_dat_o[0] soc/mprj_dat_o[10]
++ soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13] soc/mprj_dat_o[14] soc/mprj_dat_o[15]
++ soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18] soc/mprj_dat_o[19] soc/mprj_dat_o[1]
++ soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22] soc/mprj_dat_o[23] soc/mprj_dat_o[24]
++ soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27] soc/mprj_dat_o[28] soc/mprj_dat_o[29]
++ soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31] soc/mprj_dat_o[3] soc/mprj_dat_o[4]
++ soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7] soc/mprj_dat_o[8] soc/mprj_dat_o[9]
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] soc/mprj_wb_iena soc/mprj_sel_o[0] soc/mprj_sel_o[1]
++ soc/mprj_sel_o[2] soc/mprj_sel_o[3] mprj/wbs_sel_i[0] mprj/wbs_sel_i[1] mprj/wbs_sel_i[2]
++ mprj/wbs_sel_i[3] soc/mprj_stb_o mprj/wbs_stb_i soc/mprj_we_o mprj/wbs_we_i housekeeping/usr1_vcc_pwrgood
++ housekeeping/usr1_vdd_pwrgood housekeeping/usr2_vcc_pwrgood housekeeping/usr2_vdd_pwrgood
++ mprj/wb_clk_i mprj/user_clock2 soc/irq[0] soc/irq[1] soc/irq[2] mprj/user_irq[0]
++ mprj/user_irq[1] mprj/user_irq[2] soc/user_irq_ena[0] soc/user_irq_ena[1] soc/user_irq_ena[2]
++ mprj/wb_rst_i mgmt_buffers/vccd mgmt_buffers/vccd1 mgmt_buffers/vccd2 mgmt_buffers/vdda1
++ mgmt_buffers/vdda2 mgmt_buffers/vssa1 mgmt_buffers/vssa2 mgmt_buffers/vssd mgmt_buffers/vssd1
++ mgmt_buffers/vssd2 mgmt_protect
+Xrstb_level pll/resetb rstb_level/X rstb_level/VPWR rstb_level/VGND rstb_level/LVPWR
++ rstb_level/LVGND xres_buf
+Xgpio_27_defaults gpio_27_defaults/VGND gpio_27_defaults/VPWR gpio_27_defaults/gpio_defaults[0]
++ gpio_27_defaults/gpio_defaults[10] gpio_27_defaults/gpio_defaults[11] gpio_27_defaults/gpio_defaults[12]
++ gpio_27_defaults/gpio_defaults[1] gpio_27_defaults/gpio_defaults[2] gpio_27_defaults/gpio_defaults[3]
++ gpio_27_defaults/gpio_defaults[4] gpio_27_defaults/gpio_defaults[5] gpio_27_defaults/gpio_defaults[6]
++ gpio_27_defaults/gpio_defaults[7] gpio_27_defaults/gpio_defaults[8] gpio_27_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[15\] gpio_34_defaults/gpio_defaults[0] gpio_34_defaults/gpio_defaults[10]
++ gpio_34_defaults/gpio_defaults[11] gpio_34_defaults/gpio_defaults[12] gpio_34_defaults/gpio_defaults[1]
++ gpio_34_defaults/gpio_defaults[2] gpio_34_defaults/gpio_defaults[3] gpio_34_defaults/gpio_defaults[4]
++ gpio_34_defaults/gpio_defaults[5] gpio_34_defaults/gpio_defaults[6] gpio_34_defaults/gpio_defaults[7]
++ gpio_34_defaults/gpio_defaults[8] gpio_34_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[34]
++ gpio_control_in_2\[15\]/one housekeeping/mgmt_gpio_in[34] gpio_control_in_2\[15\]/one
++ padframe/mprj_io_analog_en[34] padframe/mprj_io_analog_pol[34] padframe/mprj_io_analog_sel[34]
++ padframe/mprj_io_dm[102] padframe/mprj_io_dm[103] padframe/mprj_io_dm[104] padframe/mprj_io_holdover[34]
++ padframe/mprj_io_ib_mode_sel[34] padframe/mprj_io_in[34] padframe/mprj_io_inp_dis[34]
++ padframe/mprj_io_out[34] padframe/mprj_io_oeb[34] padframe/mprj_io_slow_sel[34]
++ padframe/mprj_io_vtrip_sel[34] gpio_control_in_1\[7\]/resetn gpio_control_in_1\[8\]/resetn
++ gpio_control_in_1\[7\]/serial_clock gpio_control_in_1\[8\]/serial_clock gpio_control_in_2\[15\]/serial_data_in
++ gpio_control_in_2\[14\]/serial_data_in gpio_control_in_1\[7\]/serial_load gpio_control_in_1\[8\]/serial_load
++ mprj/io_in[34] mprj/io_oeb[34] mprj/io_out[34] gpio_control_in_2\[15\]/vccd gpio_control_in_2\[15\]/vccd1
++ gpio_control_in_2\[15\]/vssd gpio_control_in_2\[15\]/vssd1 gpio_control_in_2\[15\]/zero
++ gpio_control_block
+Xgpio_control_bidir_2\[1\] gpio_36_defaults/gpio_defaults[0] gpio_36_defaults/gpio_defaults[10]
++ gpio_36_defaults/gpio_defaults[11] gpio_36_defaults/gpio_defaults[12] gpio_36_defaults/gpio_defaults[1]
++ gpio_36_defaults/gpio_defaults[2] gpio_36_defaults/gpio_defaults[3] gpio_36_defaults/gpio_defaults[4]
++ gpio_36_defaults/gpio_defaults[5] gpio_36_defaults/gpio_defaults[6] gpio_36_defaults/gpio_defaults[7]
++ gpio_36_defaults/gpio_defaults[8] gpio_36_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[36]
++ housekeeping/mgmt_gpio_oeb[36] housekeeping/mgmt_gpio_out[36] gpio_control_bidir_2\[1\]/one
++ padframe/mprj_io_analog_en[36] padframe/mprj_io_analog_pol[36] padframe/mprj_io_analog_sel[36]
++ padframe/mprj_io_dm[108] padframe/mprj_io_dm[109] padframe/mprj_io_dm[110] padframe/mprj_io_holdover[36]
++ padframe/mprj_io_ib_mode_sel[36] padframe/mprj_io_in[36] padframe/mprj_io_inp_dis[36]
++ padframe/mprj_io_out[36] padframe/mprj_io_oeb[36] padframe/mprj_io_slow_sel[36]
++ padframe/mprj_io_vtrip_sel[36] gpio_control_in_1\[9\]/resetn gpio_control_in_1\[10\]/resetn
++ gpio_control_in_1\[9\]/serial_clock gpio_control_in_1\[10\]/serial_clock gpio_control_bidir_2\[1\]/serial_data_in
++ gpio_control_bidir_2\[0\]/serial_data_in gpio_control_in_1\[9\]/serial_load gpio_control_in_1\[10\]/serial_load
++ mprj/io_in[36] mprj/io_oeb[36] mprj/io_out[36] gpio_control_bidir_2\[1\]/vccd gpio_control_bidir_2\[1\]/vccd1
++ gpio_control_bidir_2\[1\]/vssd gpio_control_bidir_2\[1\]/vssd1 gpio_control_bidir_2\[1\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[5\] gpio_13_defaults/gpio_defaults[0] gpio_13_defaults/gpio_defaults[2]
++ gpio_13_defaults/gpio_defaults[1] gpio_13_defaults/gpio_defaults[0] gpio_13_defaults/gpio_defaults[1]
++ gpio_13_defaults/gpio_defaults[2] gpio_13_defaults/gpio_defaults[9] gpio_13_defaults/gpio_defaults[8]
++ gpio_13_defaults/gpio_defaults[7] gpio_13_defaults/gpio_defaults[6] gpio_13_defaults/gpio_defaults[7]
++ gpio_13_defaults/gpio_defaults[8] gpio_13_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[13]
++ gpio_control_in_1\[5\]/one housekeeping/mgmt_gpio_in[13] gpio_control_in_1\[5\]/one
++ padframe/mprj_io_analog_en[13] padframe/mprj_io_analog_pol[13] padframe/mprj_io_analog_sel[13]
++ padframe/mprj_io_dm[39] padframe/mprj_io_dm[40] padframe/mprj_io_dm[41] padframe/mprj_io_holdover[13]
++ padframe/mprj_io_ib_mode_sel[13] padframe/mprj_io_in[13] padframe/mprj_io_inp_dis[13]
++ padframe/mprj_io_out[13] padframe/mprj_io_oeb[13] padframe/mprj_io_slow_sel[13]
++ padframe/mprj_io_vtrip_sel[13] gpio_control_in_1\[5\]/resetn gpio_control_in_1\[6\]/resetn
++ gpio_control_in_1\[5\]/serial_clock gpio_control_in_1\[6\]/serial_clock gpio_control_in_1\[5\]/serial_data_in
++ gpio_control_in_1\[6\]/serial_data_in gpio_control_in_1\[5\]/serial_load gpio_control_in_1\[6\]/serial_load
++ mprj/io_in[13] mprj/io_oeb[13] mprj/io_out[13] gpio_control_in_1\[5\]/vccd gpio_control_in_1\[5\]/vccd1
++ gpio_control_in_1\[5\]/vssd gpio_control_in_1\[5\]/vssd1 gpio_control_in_1\[5\]/zero
++ gpio_control_block
+Xgpio_11_defaults gpio_11_defaults/VGND gpio_11_defaults/VPWR gpio_11_defaults/gpio_defaults[0]
++ gpio_11_defaults/gpio_defaults[2] gpio_11_defaults/gpio_defaults[1] gpio_11_defaults/gpio_defaults[0]
++ gpio_11_defaults/gpio_defaults[1] gpio_11_defaults/gpio_defaults[2] gpio_11_defaults/gpio_defaults[9]
++ gpio_11_defaults/gpio_defaults[8] gpio_11_defaults/gpio_defaults[7] gpio_11_defaults/gpio_defaults[6]
++ gpio_11_defaults/gpio_defaults[7] gpio_11_defaults/gpio_defaults[8] gpio_11_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[13\] gpio_32_defaults/gpio_defaults[0] gpio_32_defaults/gpio_defaults[10]
++ gpio_32_defaults/gpio_defaults[11] gpio_32_defaults/gpio_defaults[12] gpio_32_defaults/gpio_defaults[1]
++ gpio_32_defaults/gpio_defaults[2] gpio_32_defaults/gpio_defaults[3] gpio_32_defaults/gpio_defaults[4]
++ gpio_32_defaults/gpio_defaults[5] gpio_32_defaults/gpio_defaults[6] gpio_32_defaults/gpio_defaults[7]
++ gpio_32_defaults/gpio_defaults[8] gpio_32_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[32]
++ gpio_control_in_2\[13\]/one housekeeping/mgmt_gpio_in[32] gpio_control_in_2\[13\]/one
++ padframe/mprj_io_analog_en[32] padframe/mprj_io_analog_pol[32] padframe/mprj_io_analog_sel[32]
++ padframe/mprj_io_dm[96] padframe/mprj_io_dm[97] padframe/mprj_io_dm[98] padframe/mprj_io_holdover[32]
++ padframe/mprj_io_ib_mode_sel[32] padframe/mprj_io_in[32] padframe/mprj_io_inp_dis[32]
++ padframe/mprj_io_out[32] padframe/mprj_io_oeb[32] padframe/mprj_io_slow_sel[32]
++ padframe/mprj_io_vtrip_sel[32] gpio_control_in_1\[5\]/resetn gpio_control_in_1\[6\]/resetn
++ gpio_control_in_1\[5\]/serial_clock gpio_control_in_1\[6\]/serial_clock gpio_control_in_2\[13\]/serial_data_in
++ gpio_control_in_2\[12\]/serial_data_in gpio_control_in_1\[5\]/serial_load gpio_control_in_1\[6\]/serial_load
++ mprj/io_in[32] mprj/io_oeb[32] mprj/io_out[32] gpio_control_in_2\[13\]/vccd gpio_control_in_2\[13\]/vccd1
++ gpio_control_in_2\[13\]/vssd gpio_control_in_2\[13\]/vssd1 gpio_control_in_2\[13\]/zero
++ gpio_control_block
+Xgpio_control_in_1a\[2\] gpio_234_defaults\[2\]/gpio_defaults[0] gpio_234_defaults\[2\]/gpio_defaults[2]
++ gpio_234_defaults\[2\]/gpio_defaults[1] gpio_234_defaults\[2\]/gpio_defaults[0]
++ gpio_234_defaults\[2\]/gpio_defaults[1] gpio_234_defaults\[2\]/gpio_defaults[2]
++ gpio_234_defaults\[2\]/gpio_defaults[9] gpio_234_defaults\[2\]/gpio_defaults[8]
++ gpio_234_defaults\[2\]/gpio_defaults[7] gpio_234_defaults\[2\]/gpio_defaults[6]
++ gpio_234_defaults\[2\]/gpio_defaults[7] gpio_234_defaults\[2\]/gpio_defaults[8]
++ gpio_234_defaults\[2\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[4] gpio_control_in_1a\[2\]/one
++ housekeeping/mgmt_gpio_in[4] gpio_control_in_1a\[2\]/one padframe/mprj_io_analog_en[4]
++ padframe/mprj_io_analog_pol[4] padframe/mprj_io_analog_sel[4] padframe/mprj_io_dm[12]
++ padframe/mprj_io_dm[13] padframe/mprj_io_dm[14] padframe/mprj_io_holdover[4] padframe/mprj_io_ib_mode_sel[4]
++ padframe/mprj_io_in[4] padframe/mprj_io_inp_dis[4] padframe/mprj_io_out[4] padframe/mprj_io_oeb[4]
++ padframe/mprj_io_slow_sel[4] padframe/mprj_io_vtrip_sel[4] gpio_control_in_2\[4\]/resetn
++ gpio_control_in_2\[5\]/resetn gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock
++ gpio_control_in_1a\[2\]/serial_data_in gpio_control_in_1a\[3\]/serial_data_in gpio_control_in_2\[4\]/serial_load
++ gpio_control_in_2\[5\]/serial_load mprj/io_in[4] mprj/io_oeb[4] mprj/io_out[4] gpio_control_in_1a\[2\]/vccd
++ gpio_control_in_1a\[2\]/vccd1 gpio_control_in_1a\[2\]/vssd gpio_control_in_1a\[2\]/vssd1
++ gpio_control_in_1a\[2\]/zero gpio_control_block
+Xgpio_234_defaults\[0\] gpio_234_defaults\[0\]/VGND gpio_234_defaults\[0\]/VPWR gpio_234_defaults\[0\]/gpio_defaults[0]
++ gpio_234_defaults\[0\]/gpio_defaults[2] gpio_234_defaults\[0\]/gpio_defaults[1]
++ gpio_234_defaults\[0\]/gpio_defaults[0] gpio_234_defaults\[0\]/gpio_defaults[1]
++ gpio_234_defaults\[0\]/gpio_defaults[2] gpio_234_defaults\[0\]/gpio_defaults[9]
++ gpio_234_defaults\[0\]/gpio_defaults[8] gpio_234_defaults\[0\]/gpio_defaults[7]
++ gpio_234_defaults\[0\]/gpio_defaults[6] gpio_234_defaults\[0\]/gpio_defaults[7]
++ gpio_234_defaults\[0\]/gpio_defaults[8] gpio_234_defaults\[0\]/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_36_defaults gpio_36_defaults/VGND gpio_36_defaults/VPWR gpio_36_defaults/gpio_defaults[0]
++ gpio_36_defaults/gpio_defaults[10] gpio_36_defaults/gpio_defaults[11] gpio_36_defaults/gpio_defaults[12]
++ gpio_36_defaults/gpio_defaults[1] gpio_36_defaults/gpio_defaults[2] gpio_36_defaults/gpio_defaults[3]
++ gpio_36_defaults/gpio_defaults[4] gpio_36_defaults/gpio_defaults[5] gpio_36_defaults/gpio_defaults[6]
++ gpio_36_defaults/gpio_defaults[7] gpio_36_defaults/gpio_defaults[8] gpio_36_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_20_defaults gpio_20_defaults/VGND gpio_20_defaults/VPWR gpio_20_defaults/gpio_defaults[0]
++ gpio_20_defaults/gpio_defaults[10] gpio_20_defaults/gpio_defaults[11] gpio_20_defaults/gpio_defaults[12]
++ gpio_20_defaults/gpio_defaults[1] gpio_20_defaults/gpio_defaults[2] gpio_20_defaults/gpio_defaults[3]
++ gpio_20_defaults/gpio_defaults[4] gpio_20_defaults/gpio_defaults[5] gpio_20_defaults/gpio_defaults[6]
++ gpio_20_defaults/gpio_defaults[7] gpio_20_defaults/gpio_defaults[8] gpio_20_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[8\] gpio_27_defaults/gpio_defaults[0] gpio_27_defaults/gpio_defaults[10]
++ gpio_27_defaults/gpio_defaults[11] gpio_27_defaults/gpio_defaults[12] gpio_27_defaults/gpio_defaults[1]
++ gpio_27_defaults/gpio_defaults[2] gpio_27_defaults/gpio_defaults[3] gpio_27_defaults/gpio_defaults[4]
++ gpio_27_defaults/gpio_defaults[5] gpio_27_defaults/gpio_defaults[6] gpio_27_defaults/gpio_defaults[7]
++ gpio_27_defaults/gpio_defaults[8] gpio_27_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[27]
++ gpio_control_in_2\[8\]/one housekeeping/mgmt_gpio_in[27] gpio_control_in_2\[8\]/one
++ padframe/mprj_io_analog_en[27] padframe/mprj_io_analog_pol[27] padframe/mprj_io_analog_sel[27]
++ padframe/mprj_io_dm[81] padframe/mprj_io_dm[82] padframe/mprj_io_dm[83] padframe/mprj_io_holdover[27]
++ padframe/mprj_io_ib_mode_sel[27] padframe/mprj_io_in[27] padframe/mprj_io_inp_dis[27]
++ padframe/mprj_io_out[27] padframe/mprj_io_oeb[27] padframe/mprj_io_slow_sel[27]
++ padframe/mprj_io_vtrip_sel[27] gpio_control_in_2\[8\]/resetn gpio_control_in_2\[9\]/resetn
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_2\[9\]/serial_clock gpio_control_in_2\[8\]/serial_data_in
++ gpio_control_in_2\[7\]/serial_data_in gpio_control_in_2\[8\]/serial_load gpio_control_in_2\[9\]/serial_load
++ mprj/io_in[27] mprj/io_oeb[27] mprj/io_out[27] gpio_control_in_2\[8\]/vccd gpio_control_in_2\[8\]/vccd1
++ gpio_control_in_2\[8\]/vssd gpio_control_in_2\[8\]/vssd1 gpio_control_in_2\[8\]/zero
++ gpio_control_block
+Xgpio_14_defaults gpio_14_defaults/VGND gpio_14_defaults/VPWR gpio_14_defaults/gpio_defaults[0]
++ gpio_14_defaults/gpio_defaults[2] gpio_14_defaults/gpio_defaults[1] gpio_14_defaults/gpio_defaults[0]
++ gpio_14_defaults/gpio_defaults[1] gpio_14_defaults/gpio_defaults[2] gpio_14_defaults/gpio_defaults[9]
++ gpio_14_defaults/gpio_defaults[8] gpio_14_defaults/gpio_defaults[7] gpio_14_defaults/gpio_defaults[6]
++ gpio_14_defaults/gpio_defaults[7] gpio_14_defaults/gpio_defaults[8] gpio_14_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[3\] gpio_11_defaults/gpio_defaults[0] gpio_11_defaults/gpio_defaults[2]
++ gpio_11_defaults/gpio_defaults[1] gpio_11_defaults/gpio_defaults[0] gpio_11_defaults/gpio_defaults[1]
++ gpio_11_defaults/gpio_defaults[2] gpio_11_defaults/gpio_defaults[9] gpio_11_defaults/gpio_defaults[8]
++ gpio_11_defaults/gpio_defaults[7] gpio_11_defaults/gpio_defaults[6] gpio_11_defaults/gpio_defaults[7]
++ gpio_11_defaults/gpio_defaults[8] gpio_11_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[11]
++ gpio_control_in_1\[3\]/one housekeeping/mgmt_gpio_in[11] gpio_control_in_1\[3\]/one
++ padframe/mprj_io_analog_en[11] padframe/mprj_io_analog_pol[11] padframe/mprj_io_analog_sel[11]
++ padframe/mprj_io_dm[33] padframe/mprj_io_dm[34] padframe/mprj_io_dm[35] padframe/mprj_io_holdover[11]
++ padframe/mprj_io_ib_mode_sel[11] padframe/mprj_io_in[11] padframe/mprj_io_inp_dis[11]
++ padframe/mprj_io_out[11] padframe/mprj_io_oeb[11] padframe/mprj_io_slow_sel[11]
++ padframe/mprj_io_vtrip_sel[11] gpio_control_in_1\[3\]/resetn gpio_control_in_1\[4\]/resetn
++ gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[4\]/serial_clock gpio_control_in_1\[3\]/serial_data_in
++ gpio_control_in_1\[4\]/serial_data_in gpio_control_in_1\[3\]/serial_load gpio_control_in_1\[4\]/serial_load
++ mprj/io_in[11] mprj/io_oeb[11] mprj/io_out[11] gpio_control_in_1\[3\]/vccd gpio_control_in_1\[3\]/vccd1
++ gpio_control_in_1\[3\]/vssd gpio_control_in_1\[3\]/vssd1 gpio_control_in_1\[3\]/zero
++ gpio_control_block
+Xgpio_6_defaults gpio_6_defaults/VGND gpio_6_defaults/VPWR gpio_6_defaults/gpio_defaults[0]
++ gpio_6_defaults/gpio_defaults[2] gpio_6_defaults/gpio_defaults[1] gpio_6_defaults/gpio_defaults[0]
++ gpio_6_defaults/gpio_defaults[1] gpio_6_defaults/gpio_defaults[2] gpio_6_defaults/gpio_defaults[9]
++ gpio_6_defaults/gpio_defaults[8] gpio_6_defaults/gpio_defaults[7] gpio_6_defaults/gpio_defaults[6]
++ gpio_6_defaults/gpio_defaults[7] gpio_6_defaults/gpio_defaults[8] gpio_6_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[11\] gpio_30_defaults/gpio_defaults[0] gpio_30_defaults/gpio_defaults[10]
++ gpio_30_defaults/gpio_defaults[11] gpio_30_defaults/gpio_defaults[12] gpio_30_defaults/gpio_defaults[1]
++ gpio_30_defaults/gpio_defaults[2] gpio_30_defaults/gpio_defaults[3] gpio_30_defaults/gpio_defaults[4]
++ gpio_30_defaults/gpio_defaults[5] gpio_30_defaults/gpio_defaults[6] gpio_30_defaults/gpio_defaults[7]
++ gpio_30_defaults/gpio_defaults[8] gpio_30_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[30]
++ gpio_control_in_2\[11\]/one housekeeping/mgmt_gpio_in[30] gpio_control_in_2\[11\]/one
++ padframe/mprj_io_analog_en[30] padframe/mprj_io_analog_pol[30] padframe/mprj_io_analog_sel[30]
++ padframe/mprj_io_dm[90] padframe/mprj_io_dm[91] padframe/mprj_io_dm[92] padframe/mprj_io_holdover[30]
++ padframe/mprj_io_ib_mode_sel[30] padframe/mprj_io_in[30] padframe/mprj_io_inp_dis[30]
++ padframe/mprj_io_out[30] padframe/mprj_io_oeb[30] padframe/mprj_io_slow_sel[30]
++ padframe/mprj_io_vtrip_sel[30] gpio_control_in_1\[3\]/resetn gpio_control_in_1\[4\]/resetn
++ gpio_control_in_1\[3\]/serial_clock gpio_control_in_1\[4\]/serial_clock gpio_control_in_2\[11\]/serial_data_in
++ gpio_control_in_2\[10\]/serial_data_in gpio_control_in_1\[3\]/serial_load gpio_control_in_1\[4\]/serial_load
++ mprj/io_in[30] mprj/io_oeb[30] mprj/io_out[30] gpio_control_in_2\[11\]/vccd gpio_control_in_2\[11\]/vccd1
++ gpio_control_in_2\[11\]/vssd gpio_control_in_2\[11\]/vssd1 gpio_control_in_2\[11\]/zero
++ gpio_control_block
+Xgpio_control_in_1a\[0\] gpio_234_defaults\[0\]/gpio_defaults[0] gpio_234_defaults\[0\]/gpio_defaults[2]
++ gpio_234_defaults\[0\]/gpio_defaults[1] gpio_234_defaults\[0\]/gpio_defaults[0]
++ gpio_234_defaults\[0\]/gpio_defaults[1] gpio_234_defaults\[0\]/gpio_defaults[2]
++ gpio_234_defaults\[0\]/gpio_defaults[9] gpio_234_defaults\[0\]/gpio_defaults[8]
++ gpio_234_defaults\[0\]/gpio_defaults[7] gpio_234_defaults\[0\]/gpio_defaults[6]
++ gpio_234_defaults\[0\]/gpio_defaults[7] gpio_234_defaults\[0\]/gpio_defaults[8]
++ gpio_234_defaults\[0\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[2] gpio_control_in_1a\[0\]/one
++ housekeeping/mgmt_gpio_in[2] gpio_control_in_1a\[0\]/one padframe/mprj_io_analog_en[2]
++ padframe/mprj_io_analog_pol[2] padframe/mprj_io_analog_sel[2] padframe/mprj_io_dm[6]
++ padframe/mprj_io_dm[7] padframe/mprj_io_dm[8] padframe/mprj_io_holdover[2] padframe/mprj_io_ib_mode_sel[2]
++ padframe/mprj_io_in[2] padframe/mprj_io_inp_dis[2] padframe/mprj_io_out[2] padframe/mprj_io_oeb[2]
++ padframe/mprj_io_slow_sel[2] padframe/mprj_io_vtrip_sel[2] gpio_control_in_2\[2\]/resetn
++ gpio_control_in_2\[3\]/resetn gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock
++ gpio_control_in_1a\[0\]/serial_data_in gpio_control_in_1a\[1\]/serial_data_in gpio_control_in_2\[2\]/serial_load
++ gpio_control_in_2\[3\]/serial_load mprj/io_in[2] mprj/io_oeb[2] mprj/io_out[2] gpio_control_in_1a\[0\]/vccd
++ gpio_control_in_1a\[0\]/vccd1 gpio_control_in_1a\[0\]/vssd gpio_control_in_1a\[0\]/vssd1
++ gpio_control_in_1a\[0\]/zero gpio_control_block
+Xgpio_23_defaults gpio_23_defaults/VGND gpio_23_defaults/VPWR gpio_23_defaults/gpio_defaults[0]
++ gpio_23_defaults/gpio_defaults[10] gpio_23_defaults/gpio_defaults[11] gpio_23_defaults/gpio_defaults[12]
++ gpio_23_defaults/gpio_defaults[1] gpio_23_defaults/gpio_defaults[2] gpio_23_defaults/gpio_defaults[3]
++ gpio_23_defaults/gpio_defaults[4] gpio_23_defaults/gpio_defaults[5] gpio_23_defaults/gpio_defaults[6]
++ gpio_23_defaults/gpio_defaults[7] gpio_23_defaults/gpio_defaults[8] gpio_23_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_2\[6\] gpio_25_defaults/gpio_defaults[0] gpio_25_defaults/gpio_defaults[10]
++ gpio_25_defaults/gpio_defaults[11] gpio_25_defaults/gpio_defaults[12] gpio_25_defaults/gpio_defaults[1]
++ gpio_25_defaults/gpio_defaults[2] gpio_25_defaults/gpio_defaults[3] gpio_25_defaults/gpio_defaults[4]
++ gpio_25_defaults/gpio_defaults[5] gpio_25_defaults/gpio_defaults[6] gpio_25_defaults/gpio_defaults[7]
++ gpio_25_defaults/gpio_defaults[8] gpio_25_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[25]
++ gpio_control_in_2\[6\]/one housekeeping/mgmt_gpio_in[25] gpio_control_in_2\[6\]/one
++ padframe/mprj_io_analog_en[25] padframe/mprj_io_analog_pol[25] padframe/mprj_io_analog_sel[25]
++ padframe/mprj_io_dm[75] padframe/mprj_io_dm[76] padframe/mprj_io_dm[77] padframe/mprj_io_holdover[25]
++ padframe/mprj_io_ib_mode_sel[25] padframe/mprj_io_in[25] padframe/mprj_io_inp_dis[25]
++ padframe/mprj_io_out[25] padframe/mprj_io_oeb[25] padframe/mprj_io_slow_sel[25]
++ padframe/mprj_io_vtrip_sel[25] gpio_control_in_2\[6\]/resetn gpio_control_in_2\[7\]/resetn
++ gpio_control_in_2\[6\]/serial_clock gpio_control_in_2\[7\]/serial_clock gpio_control_in_2\[6\]/serial_data_in
++ gpio_control_in_2\[5\]/serial_data_in gpio_control_in_2\[6\]/serial_load gpio_control_in_2\[7\]/serial_load
++ mprj/io_in[25] mprj/io_oeb[25] mprj/io_out[25] gpio_control_in_2\[6\]/vccd gpio_control_in_2\[6\]/vccd1
++ gpio_control_in_2\[6\]/vssd gpio_control_in_2\[6\]/vssd1 gpio_control_in_2\[6\]/zero
++ gpio_control_block
+Xgpio_9_defaults gpio_9_defaults/VGND gpio_9_defaults/VPWR gpio_9_defaults/gpio_defaults[0]
++ gpio_9_defaults/gpio_defaults[2] gpio_9_defaults/gpio_defaults[1] gpio_9_defaults/gpio_defaults[0]
++ gpio_9_defaults/gpio_defaults[1] gpio_9_defaults/gpio_defaults[2] gpio_9_defaults/gpio_defaults[9]
++ gpio_9_defaults/gpio_defaults[8] gpio_9_defaults/gpio_defaults[7] gpio_9_defaults/gpio_defaults[6]
++ gpio_9_defaults/gpio_defaults[7] gpio_9_defaults/gpio_defaults[8] gpio_9_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1\[1\] gpio_9_defaults/gpio_defaults[0] gpio_9_defaults/gpio_defaults[2]
++ gpio_9_defaults/gpio_defaults[1] gpio_9_defaults/gpio_defaults[0] gpio_9_defaults/gpio_defaults[1]
++ gpio_9_defaults/gpio_defaults[2] gpio_9_defaults/gpio_defaults[9] gpio_9_defaults/gpio_defaults[8]
++ gpio_9_defaults/gpio_defaults[7] gpio_9_defaults/gpio_defaults[6] gpio_9_defaults/gpio_defaults[7]
++ gpio_9_defaults/gpio_defaults[8] gpio_9_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[9]
++ gpio_control_in_1\[1\]/one housekeeping/mgmt_gpio_in[9] gpio_control_in_1\[1\]/one
++ padframe/mprj_io_analog_en[9] padframe/mprj_io_analog_pol[9] padframe/mprj_io_analog_sel[9]
++ padframe/mprj_io_dm[27] padframe/mprj_io_dm[28] padframe/mprj_io_dm[29] padframe/mprj_io_holdover[9]
++ padframe/mprj_io_ib_mode_sel[9] padframe/mprj_io_in[9] padframe/mprj_io_inp_dis[9]
++ padframe/mprj_io_out[9] padframe/mprj_io_oeb[9] padframe/mprj_io_slow_sel[9] padframe/mprj_io_vtrip_sel[9]
++ gpio_control_in_2\[9\]/resetn gpio_control_in_1\[2\]/resetn gpio_control_in_2\[9\]/serial_clock
++ gpio_control_in_1\[2\]/serial_clock gpio_control_in_1\[1\]/serial_data_in gpio_control_in_1\[2\]/serial_data_in
++ gpio_control_in_2\[9\]/serial_load gpio_control_in_1\[2\]/serial_load mprj/io_in[9]
++ mprj/io_oeb[9] mprj/io_out[9] gpio_control_in_1\[1\]/vccd gpio_control_in_1\[1\]/vccd1
++ gpio_control_in_1\[1\]/vssd gpio_control_in_1\[1\]/vssd1 gpio_control_in_1\[1\]/zero
++ gpio_control_block
+Xgpio_17_defaults gpio_17_defaults/VGND gpio_17_defaults/VPWR gpio_17_defaults/gpio_defaults[0]
++ gpio_17_defaults/gpio_defaults[10] gpio_17_defaults/gpio_defaults[11] gpio_17_defaults/gpio_defaults[12]
++ gpio_17_defaults/gpio_defaults[1] gpio_17_defaults/gpio_defaults[2] gpio_17_defaults/gpio_defaults[3]
++ gpio_17_defaults/gpio_defaults[4] gpio_17_defaults/gpio_defaults[5] gpio_17_defaults/gpio_defaults[6]
++ gpio_17_defaults/gpio_defaults[7] gpio_17_defaults/gpio_defaults[8] gpio_17_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_32_defaults gpio_32_defaults/VGND gpio_32_defaults/VPWR gpio_32_defaults/gpio_defaults[0]
++ gpio_32_defaults/gpio_defaults[10] gpio_32_defaults/gpio_defaults[11] gpio_32_defaults/gpio_defaults[12]
++ gpio_32_defaults/gpio_defaults[1] gpio_32_defaults/gpio_defaults[2] gpio_32_defaults/gpio_defaults[3]
++ gpio_32_defaults/gpio_defaults[4] gpio_32_defaults/gpio_defaults[5] gpio_32_defaults/gpio_defaults[6]
++ gpio_32_defaults/gpio_defaults[7] gpio_32_defaults/gpio_defaults[8] gpio_32_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xmprj mprj/analog_io[0] mprj/analog_io[10] mprj/analog_io[11] mprj/analog_io[12] mprj/analog_io[13]
++ mprj/analog_io[14] mprj/analog_io[15] mprj/analog_io[16] mprj/analog_io[17] mprj/analog_io[18]
++ mprj/analog_io[19] mprj/analog_io[1] mprj/analog_io[20] mprj/analog_io[21] mprj/analog_io[22]
++ mprj/analog_io[23] mprj/analog_io[24] mprj/analog_io[25] mprj/analog_io[26] mprj/analog_io[27]
++ mprj/analog_io[28] mprj/analog_io[2] mprj/analog_io[3] mprj/analog_io[4] mprj/analog_io[5]
++ mprj/analog_io[6] mprj/analog_io[7] mprj/analog_io[8] mprj/analog_io[9] mprj/io_in[0]
++ mprj/io_in[10] mprj/io_in[11] mprj/io_in[12] mprj/io_in[13] mprj/io_in[14] mprj/io_in[15]
++ mprj/io_in[16] mprj/io_in[17] mprj/io_in[18] mprj/io_in[19] mprj/io_in[1] mprj/io_in[20]
++ mprj/io_in[21] mprj/io_in[22] mprj/io_in[23] mprj/io_in[24] mprj/io_in[25] mprj/io_in[26]
++ mprj/io_in[27] mprj/io_in[28] mprj/io_in[29] mprj/io_in[2] mprj/io_in[30] mprj/io_in[31]
++ mprj/io_in[32] mprj/io_in[33] mprj/io_in[34] mprj/io_in[35] mprj/io_in[36] mprj/io_in[37]
++ mprj/io_in[3] mprj/io_in[4] mprj/io_in[5] mprj/io_in[6] mprj/io_in[7] mprj/io_in[8]
++ mprj/io_in[9] mprj/io_oeb[0] mprj/io_oeb[10] mprj/io_oeb[11] mprj/io_oeb[12] mprj/io_oeb[13]
++ mprj/io_oeb[14] mprj/io_oeb[15] mprj/io_oeb[16] mprj/io_oeb[17] mprj/io_oeb[18]
++ mprj/io_oeb[19] mprj/io_oeb[1] mprj/io_oeb[20] mprj/io_oeb[21] mprj/io_oeb[22] mprj/io_oeb[23]
++ mprj/io_oeb[24] mprj/io_oeb[25] mprj/io_oeb[26] mprj/io_oeb[27] mprj/io_oeb[28]
++ mprj/io_oeb[29] mprj/io_oeb[2] mprj/io_oeb[30] mprj/io_oeb[31] mprj/io_oeb[32] mprj/io_oeb[33]
++ mprj/io_oeb[34] mprj/io_oeb[35] mprj/io_oeb[36] mprj/io_oeb[37] mprj/io_oeb[3] mprj/io_oeb[4]
++ mprj/io_oeb[5] mprj/io_oeb[6] mprj/io_oeb[7] mprj/io_oeb[8] mprj/io_oeb[9] mprj/io_out[0]
++ mprj/io_out[10] mprj/io_out[11] mprj/io_out[12] mprj/io_out[13] mprj/io_out[14]
++ mprj/io_out[15] mprj/io_out[16] mprj/io_out[17] mprj/io_out[18] mprj/io_out[19]
++ mprj/io_out[1] mprj/io_out[20] mprj/io_out[21] mprj/io_out[22] mprj/io_out[23] mprj/io_out[24]
++ mprj/io_out[25] mprj/io_out[26] mprj/io_out[27] mprj/io_out[28] mprj/io_out[29]
++ mprj/io_out[2] mprj/io_out[30] mprj/io_out[31] mprj/io_out[32] mprj/io_out[33] mprj/io_out[34]
++ mprj/io_out[35] mprj/io_out[36] mprj/io_out[37] mprj/io_out[3] mprj/io_out[4] mprj/io_out[5]
++ mprj/io_out[6] mprj/io_out[7] mprj/io_out[8] mprj/io_out[9] mprj/la_data_in[0] mprj/la_data_in[100]
++ mprj/la_data_in[101] mprj/la_data_in[102] mprj/la_data_in[103] mprj/la_data_in[104]
++ mprj/la_data_in[105] mprj/la_data_in[106] mprj/la_data_in[107] mprj/la_data_in[108]
++ mprj/la_data_in[109] mprj/la_data_in[10] mprj/la_data_in[110] mprj/la_data_in[111]
++ mprj/la_data_in[112] mprj/la_data_in[113] mprj/la_data_in[114] mprj/la_data_in[115]
++ mprj/la_data_in[116] mprj/la_data_in[117] mprj/la_data_in[118] mprj/la_data_in[119]
++ mprj/la_data_in[11] mprj/la_data_in[120] mprj/la_data_in[121] mprj/la_data_in[122]
++ mprj/la_data_in[123] mprj/la_data_in[124] mprj/la_data_in[125] mprj/la_data_in[126]
++ mprj/la_data_in[127] mprj/la_data_in[12] mprj/la_data_in[13] mprj/la_data_in[14]
++ mprj/la_data_in[15] mprj/la_data_in[16] mprj/la_data_in[17] mprj/la_data_in[18]
++ mprj/la_data_in[19] mprj/la_data_in[1] mprj/la_data_in[20] mprj/la_data_in[21] mprj/la_data_in[22]
++ mprj/la_data_in[23] mprj/la_data_in[24] mprj/la_data_in[25] mprj/la_data_in[26]
++ mprj/la_data_in[27] mprj/la_data_in[28] mprj/la_data_in[29] mprj/la_data_in[2] mprj/la_data_in[30]
++ mprj/la_data_in[31] mprj/la_data_in[32] mprj/la_data_in[33] mprj/la_data_in[34]
++ mprj/la_data_in[35] mprj/la_data_in[36] mprj/la_data_in[37] mprj/la_data_in[38]
++ mprj/la_data_in[39] mprj/la_data_in[3] mprj/la_data_in[40] mprj/la_data_in[41] mprj/la_data_in[42]
++ mprj/la_data_in[43] mprj/la_data_in[44] mprj/la_data_in[45] mprj/la_data_in[46]
++ mprj/la_data_in[47] mprj/la_data_in[48] mprj/la_data_in[49] mprj/la_data_in[4] mprj/la_data_in[50]
++ mprj/la_data_in[51] mprj/la_data_in[52] mprj/la_data_in[53] mprj/la_data_in[54]
++ mprj/la_data_in[55] mprj/la_data_in[56] mprj/la_data_in[57] mprj/la_data_in[58]
++ mprj/la_data_in[59] mprj/la_data_in[5] mprj/la_data_in[60] mprj/la_data_in[61] mprj/la_data_in[62]
++ mprj/la_data_in[63] mprj/la_data_in[64] mprj/la_data_in[65] mprj/la_data_in[66]
++ mprj/la_data_in[67] mprj/la_data_in[68] mprj/la_data_in[69] mprj/la_data_in[6] mprj/la_data_in[70]
++ mprj/la_data_in[71] mprj/la_data_in[72] mprj/la_data_in[73] mprj/la_data_in[74]
++ mprj/la_data_in[75] mprj/la_data_in[76] mprj/la_data_in[77] mprj/la_data_in[78]
++ mprj/la_data_in[79] mprj/la_data_in[7] mprj/la_data_in[80] mprj/la_data_in[81] mprj/la_data_in[82]
++ mprj/la_data_in[83] mprj/la_data_in[84] mprj/la_data_in[85] mprj/la_data_in[86]
++ mprj/la_data_in[87] mprj/la_data_in[88] mprj/la_data_in[89] mprj/la_data_in[8] mprj/la_data_in[90]
++ mprj/la_data_in[91] mprj/la_data_in[92] mprj/la_data_in[93] mprj/la_data_in[94]
++ mprj/la_data_in[95] mprj/la_data_in[96] mprj/la_data_in[97] mprj/la_data_in[98]
++ mprj/la_data_in[99] mprj/la_data_in[9] mprj/la_data_out[0] mprj/la_data_out[100]
++ mprj/la_data_out[101] mprj/la_data_out[102] mprj/la_data_out[103] mprj/la_data_out[104]
++ mprj/la_data_out[105] mprj/la_data_out[106] mprj/la_data_out[107] mprj/la_data_out[108]
++ mprj/la_data_out[109] mprj/la_data_out[10] mprj/la_data_out[110] mprj/la_data_out[111]
++ mprj/la_data_out[112] mprj/la_data_out[113] mprj/la_data_out[114] mprj/la_data_out[115]
++ mprj/la_data_out[116] mprj/la_data_out[117] mprj/la_data_out[118] mprj/la_data_out[119]
++ mprj/la_data_out[11] mprj/la_data_out[120] mprj/la_data_out[121] mprj/la_data_out[122]
++ mprj/la_data_out[123] mprj/la_data_out[124] mprj/la_data_out[125] mprj/la_data_out[126]
++ mprj/la_data_out[127] mprj/la_data_out[12] mprj/la_data_out[13] mprj/la_data_out[14]
++ mprj/la_data_out[15] mprj/la_data_out[16] mprj/la_data_out[17] mprj/la_data_out[18]
++ mprj/la_data_out[19] mprj/la_data_out[1] mprj/la_data_out[20] mprj/la_data_out[21]
++ mprj/la_data_out[22] mprj/la_data_out[23] mprj/la_data_out[24] mprj/la_data_out[25]
++ mprj/la_data_out[26] mprj/la_data_out[27] mprj/la_data_out[28] mprj/la_data_out[29]
++ mprj/la_data_out[2] mprj/la_data_out[30] mprj/la_data_out[31] mprj/la_data_out[32]
++ mprj/la_data_out[33] mprj/la_data_out[34] mprj/la_data_out[35] mprj/la_data_out[36]
++ mprj/la_data_out[37] mprj/la_data_out[38] mprj/la_data_out[39] mprj/la_data_out[3]
++ mprj/la_data_out[40] mprj/la_data_out[41] mprj/la_data_out[42] mprj/la_data_out[43]
++ mprj/la_data_out[44] mprj/la_data_out[45] mprj/la_data_out[46] mprj/la_data_out[47]
++ mprj/la_data_out[48] mprj/la_data_out[49] mprj/la_data_out[4] mprj/la_data_out[50]
++ mprj/la_data_out[51] mprj/la_data_out[52] mprj/la_data_out[53] mprj/la_data_out[54]
++ mprj/la_data_out[55] mprj/la_data_out[56] mprj/la_data_out[57] mprj/la_data_out[58]
++ mprj/la_data_out[59] mprj/la_data_out[5] mprj/la_data_out[60] mprj/la_data_out[61]
++ mprj/la_data_out[62] mprj/la_data_out[63] mprj/la_data_out[64] mprj/la_data_out[65]
++ mprj/la_data_out[66] mprj/la_data_out[67] mprj/la_data_out[68] mprj/la_data_out[69]
++ mprj/la_data_out[6] mprj/la_data_out[70] mprj/la_data_out[71] mprj/la_data_out[72]
++ mprj/la_data_out[73] mprj/la_data_out[74] mprj/la_data_out[75] mprj/la_data_out[76]
++ mprj/la_data_out[77] mprj/la_data_out[78] mprj/la_data_out[79] mprj/la_data_out[7]
++ mprj/la_data_out[80] mprj/la_data_out[81] mprj/la_data_out[82] mprj/la_data_out[83]
++ mprj/la_data_out[84] mprj/la_data_out[85] mprj/la_data_out[86] mprj/la_data_out[87]
++ mprj/la_data_out[88] mprj/la_data_out[89] mprj/la_data_out[8] mprj/la_data_out[90]
++ mprj/la_data_out[91] mprj/la_data_out[92] mprj/la_data_out[93] mprj/la_data_out[94]
++ mprj/la_data_out[95] mprj/la_data_out[96] mprj/la_data_out[97] mprj/la_data_out[98]
++ mprj/la_data_out[99] mprj/la_data_out[9] mprj/la_oenb[0] mprj/la_oenb[100] mprj/la_oenb[101]
++ mprj/la_oenb[102] mprj/la_oenb[103] mprj/la_oenb[104] mprj/la_oenb[105] mprj/la_oenb[106]
++ mprj/la_oenb[107] mprj/la_oenb[108] mprj/la_oenb[109] mprj/la_oenb[10] mprj/la_oenb[110]
++ mprj/la_oenb[111] mprj/la_oenb[112] mprj/la_oenb[113] mprj/la_oenb[114] mprj/la_oenb[115]
++ mprj/la_oenb[116] mprj/la_oenb[117] mprj/la_oenb[118] mprj/la_oenb[119] mprj/la_oenb[11]
++ mprj/la_oenb[120] mprj/la_oenb[121] mprj/la_oenb[122] mprj/la_oenb[123] mprj/la_oenb[124]
++ mprj/la_oenb[125] mprj/la_oenb[126] mprj/la_oenb[127] mprj/la_oenb[12] mprj/la_oenb[13]
++ mprj/la_oenb[14] mprj/la_oenb[15] mprj/la_oenb[16] mprj/la_oenb[17] mprj/la_oenb[18]
++ mprj/la_oenb[19] mprj/la_oenb[1] mprj/la_oenb[20] mprj/la_oenb[21] mprj/la_oenb[22]
++ mprj/la_oenb[23] mprj/la_oenb[24] mprj/la_oenb[25] mprj/la_oenb[26] mprj/la_oenb[27]
++ mprj/la_oenb[28] mprj/la_oenb[29] mprj/la_oenb[2] mprj/la_oenb[30] mprj/la_oenb[31]
++ mprj/la_oenb[32] mprj/la_oenb[33] mprj/la_oenb[34] mprj/la_oenb[35] mprj/la_oenb[36]
++ mprj/la_oenb[37] mprj/la_oenb[38] mprj/la_oenb[39] mprj/la_oenb[3] mprj/la_oenb[40]
++ mprj/la_oenb[41] mprj/la_oenb[42] mprj/la_oenb[43] mprj/la_oenb[44] mprj/la_oenb[45]
++ mprj/la_oenb[46] mprj/la_oenb[47] mprj/la_oenb[48] mprj/la_oenb[49] mprj/la_oenb[4]
++ mprj/la_oenb[50] mprj/la_oenb[51] mprj/la_oenb[52] mprj/la_oenb[53] mprj/la_oenb[54]
++ mprj/la_oenb[55] mprj/la_oenb[56] mprj/la_oenb[57] mprj/la_oenb[58] mprj/la_oenb[59]
++ mprj/la_oenb[5] mprj/la_oenb[60] mprj/la_oenb[61] mprj/la_oenb[62] mprj/la_oenb[63]
++ mprj/la_oenb[64] mprj/la_oenb[65] mprj/la_oenb[66] mprj/la_oenb[67] mprj/la_oenb[68]
++ mprj/la_oenb[69] mprj/la_oenb[6] mprj/la_oenb[70] mprj/la_oenb[71] mprj/la_oenb[72]
++ mprj/la_oenb[73] mprj/la_oenb[74] mprj/la_oenb[75] mprj/la_oenb[76] mprj/la_oenb[77]
++ mprj/la_oenb[78] mprj/la_oenb[79] mprj/la_oenb[7] mprj/la_oenb[80] mprj/la_oenb[81]
++ mprj/la_oenb[82] mprj/la_oenb[83] mprj/la_oenb[84] mprj/la_oenb[85] mprj/la_oenb[86]
++ mprj/la_oenb[87] mprj/la_oenb[88] mprj/la_oenb[89] mprj/la_oenb[8] mprj/la_oenb[90]
++ mprj/la_oenb[91] mprj/la_oenb[92] mprj/la_oenb[93] mprj/la_oenb[94] mprj/la_oenb[95]
++ mprj/la_oenb[96] mprj/la_oenb[97] mprj/la_oenb[98] mprj/la_oenb[99] mprj/la_oenb[9]
++ mprj/user_clock2 mprj/user_irq[0] mprj/user_irq[1] mprj/user_irq[2] mprj/vccd1 mprj/vccd2
++ mprj/vdda1 mprj/vdda2 mprj/vssa1 mprj/vssa2 mprj/vssd1 mprj/vssd2 mprj/wb_clk_i
++ mprj/wb_rst_i mprj/wbs_ack_o mprj/wbs_adr_i[0] mprj/wbs_adr_i[10] mprj/wbs_adr_i[11]
++ mprj/wbs_adr_i[12] mprj/wbs_adr_i[13] mprj/wbs_adr_i[14] mprj/wbs_adr_i[15] mprj/wbs_adr_i[16]
++ mprj/wbs_adr_i[17] mprj/wbs_adr_i[18] mprj/wbs_adr_i[19] mprj/wbs_adr_i[1] mprj/wbs_adr_i[20]
++ mprj/wbs_adr_i[21] mprj/wbs_adr_i[22] mprj/wbs_adr_i[23] mprj/wbs_adr_i[24] mprj/wbs_adr_i[25]
++ mprj/wbs_adr_i[26] mprj/wbs_adr_i[27] mprj/wbs_adr_i[28] mprj/wbs_adr_i[29] mprj/wbs_adr_i[2]
++ mprj/wbs_adr_i[30] mprj/wbs_adr_i[31] mprj/wbs_adr_i[3] mprj/wbs_adr_i[4] mprj/wbs_adr_i[5]
++ mprj/wbs_adr_i[6] mprj/wbs_adr_i[7] mprj/wbs_adr_i[8] mprj/wbs_adr_i[9] mprj/wbs_cyc_i
++ mprj/wbs_dat_i[0] mprj/wbs_dat_i[10] mprj/wbs_dat_i[11] mprj/wbs_dat_i[12] mprj/wbs_dat_i[13]
++ mprj/wbs_dat_i[14] mprj/wbs_dat_i[15] mprj/wbs_dat_i[16] mprj/wbs_dat_i[17] mprj/wbs_dat_i[18]
++ mprj/wbs_dat_i[19] mprj/wbs_dat_i[1] mprj/wbs_dat_i[20] mprj/wbs_dat_i[21] mprj/wbs_dat_i[22]
++ mprj/wbs_dat_i[23] mprj/wbs_dat_i[24] mprj/wbs_dat_i[25] mprj/wbs_dat_i[26] mprj/wbs_dat_i[27]
++ mprj/wbs_dat_i[28] mprj/wbs_dat_i[29] mprj/wbs_dat_i[2] mprj/wbs_dat_i[30] mprj/wbs_dat_i[31]
++ mprj/wbs_dat_i[3] mprj/wbs_dat_i[4] mprj/wbs_dat_i[5] mprj/wbs_dat_i[6] mprj/wbs_dat_i[7]
++ mprj/wbs_dat_i[8] mprj/wbs_dat_i[9] mprj/wbs_dat_o[0] mprj/wbs_dat_o[10] mprj/wbs_dat_o[11]
++ mprj/wbs_dat_o[12] mprj/wbs_dat_o[13] mprj/wbs_dat_o[14] mprj/wbs_dat_o[15] mprj/wbs_dat_o[16]
++ mprj/wbs_dat_o[17] mprj/wbs_dat_o[18] mprj/wbs_dat_o[19] mprj/wbs_dat_o[1] mprj/wbs_dat_o[20]
++ mprj/wbs_dat_o[21] mprj/wbs_dat_o[22] mprj/wbs_dat_o[23] mprj/wbs_dat_o[24] mprj/wbs_dat_o[25]
++ mprj/wbs_dat_o[26] mprj/wbs_dat_o[27] mprj/wbs_dat_o[28] mprj/wbs_dat_o[29] mprj/wbs_dat_o[2]
++ mprj/wbs_dat_o[30] mprj/wbs_dat_o[31] mprj/wbs_dat_o[3] mprj/wbs_dat_o[4] mprj/wbs_dat_o[5]
++ mprj/wbs_dat_o[6] mprj/wbs_dat_o[7] mprj/wbs_dat_o[8] mprj/wbs_dat_o[9] mprj/wbs_sel_i[0]
++ mprj/wbs_sel_i[1] mprj/wbs_sel_i[2] mprj/wbs_sel_i[3] mprj/wbs_stb_i mprj/wbs_we_i
++ user_project_wrapper
+Xgpio_control_in_2\[4\] gpio_23_defaults/gpio_defaults[0] gpio_23_defaults/gpio_defaults[10]
++ gpio_23_defaults/gpio_defaults[11] gpio_23_defaults/gpio_defaults[12] gpio_23_defaults/gpio_defaults[1]
++ gpio_23_defaults/gpio_defaults[2] gpio_23_defaults/gpio_defaults[3] gpio_23_defaults/gpio_defaults[4]
++ gpio_23_defaults/gpio_defaults[5] gpio_23_defaults/gpio_defaults[6] gpio_23_defaults/gpio_defaults[7]
++ gpio_23_defaults/gpio_defaults[8] gpio_23_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[23]
++ gpio_control_in_2\[4\]/one housekeeping/mgmt_gpio_in[23] gpio_control_in_2\[4\]/one
++ padframe/mprj_io_analog_en[23] padframe/mprj_io_analog_pol[23] padframe/mprj_io_analog_sel[23]
++ padframe/mprj_io_dm[69] padframe/mprj_io_dm[70] padframe/mprj_io_dm[71] padframe/mprj_io_holdover[23]
++ padframe/mprj_io_ib_mode_sel[23] padframe/mprj_io_in[23] padframe/mprj_io_inp_dis[23]
++ padframe/mprj_io_out[23] padframe/mprj_io_oeb[23] padframe/mprj_io_slow_sel[23]
++ padframe/mprj_io_vtrip_sel[23] gpio_control_in_2\[4\]/resetn gpio_control_in_2\[5\]/resetn
++ gpio_control_in_2\[4\]/serial_clock gpio_control_in_2\[5\]/serial_clock gpio_control_in_2\[4\]/serial_data_in
++ gpio_control_in_2\[3\]/serial_data_in gpio_control_in_2\[4\]/serial_load gpio_control_in_2\[5\]/serial_load
++ mprj/io_in[23] mprj/io_oeb[23] mprj/io_out[23] gpio_control_in_2\[4\]/vccd gpio_control_in_2\[4\]/vccd1
++ gpio_control_in_2\[4\]/vssd gpio_control_in_2\[4\]/vssd1 gpio_control_in_2\[4\]/zero
++ gpio_control_block
+Xgpio_26_defaults gpio_26_defaults/VGND gpio_26_defaults/VPWR gpio_26_defaults/gpio_defaults[0]
++ gpio_26_defaults/gpio_defaults[10] gpio_26_defaults/gpio_defaults[11] gpio_26_defaults/gpio_defaults[12]
++ gpio_26_defaults/gpio_defaults[1] gpio_26_defaults/gpio_defaults[2] gpio_26_defaults/gpio_defaults[3]
++ gpio_26_defaults/gpio_defaults[4] gpio_26_defaults/gpio_defaults[5] gpio_26_defaults/gpio_defaults[6]
++ gpio_26_defaults/gpio_defaults[7] gpio_26_defaults/gpio_defaults[8] gpio_26_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_1\[1\] gpio_01_defaults\[1\]/gpio_defaults[0] gpio_01_defaults\[1\]/gpio_defaults[2]
++ gpio_01_defaults\[1\]/gpio_defaults[1] gpio_01_defaults\[1\]/gpio_defaults[0] gpio_01_defaults\[1\]/gpio_defaults[1]
++ gpio_01_defaults\[1\]/gpio_defaults[2] gpio_01_defaults\[1\]/gpio_defaults[9] gpio_01_defaults\[1\]/gpio_defaults[8]
++ gpio_01_defaults\[1\]/gpio_defaults[7] gpio_01_defaults\[1\]/gpio_defaults[6] gpio_01_defaults\[1\]/gpio_defaults[7]
++ gpio_01_defaults\[1\]/gpio_defaults[8] gpio_01_defaults\[1\]/gpio_defaults[9] housekeeping/mgmt_gpio_in[1]
++ housekeeping/mgmt_gpio_oeb[1] housekeeping/mgmt_gpio_out[1] gpio_control_bidir_1\[1\]/one
++ padframe/mprj_io_analog_en[1] padframe/mprj_io_analog_pol[1] padframe/mprj_io_analog_sel[1]
++ padframe/mprj_io_dm[3] padframe/mprj_io_dm[4] padframe/mprj_io_dm[5] padframe/mprj_io_holdover[1]
++ padframe/mprj_io_ib_mode_sel[1] padframe/mprj_io_in[1] padframe/mprj_io_inp_dis[1]
++ padframe/mprj_io_out[1] padframe/mprj_io_oeb[1] padframe/mprj_io_slow_sel[1] padframe/mprj_io_vtrip_sel[1]
++ gpio_control_in_2\[1\]/resetn gpio_control_in_2\[2\]/resetn gpio_control_in_2\[1\]/serial_clock
++ gpio_control_in_2\[2\]/serial_clock gpio_control_bidir_1\[1\]/serial_data_in gpio_control_in_1a\[0\]/serial_data_in
++ gpio_control_in_2\[1\]/serial_load gpio_control_in_2\[2\]/serial_load mprj/io_in[1]
++ mprj/io_oeb[1] mprj/io_out[1] gpio_control_bidir_1\[1\]/vccd gpio_control_bidir_1\[1\]/vccd1
++ gpio_control_bidir_1\[1\]/vssd gpio_control_bidir_1\[1\]/vssd1 gpio_control_bidir_1\[1\]/zero
++ gpio_control_block
+Xgpio_10_defaults gpio_10_defaults/VGND gpio_10_defaults/VPWR gpio_10_defaults/gpio_defaults[0]
++ gpio_10_defaults/gpio_defaults[2] gpio_10_defaults/gpio_defaults[1] gpio_10_defaults/gpio_defaults[0]
++ gpio_10_defaults/gpio_defaults[1] gpio_10_defaults/gpio_defaults[2] gpio_10_defaults/gpio_defaults[9]
++ gpio_10_defaults/gpio_defaults[8] gpio_10_defaults/gpio_defaults[7] gpio_10_defaults/gpio_defaults[6]
++ gpio_10_defaults/gpio_defaults[7] gpio_10_defaults/gpio_defaults[8] gpio_10_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_35_defaults gpio_35_defaults/VGND gpio_35_defaults/VPWR gpio_35_defaults/gpio_defaults[0]
++ gpio_35_defaults/gpio_defaults[10] gpio_35_defaults/gpio_defaults[11] gpio_35_defaults/gpio_defaults[12]
++ gpio_35_defaults/gpio_defaults[1] gpio_35_defaults/gpio_defaults[2] gpio_35_defaults/gpio_defaults[3]
++ gpio_35_defaults/gpio_defaults[4] gpio_35_defaults/gpio_defaults[5] gpio_35_defaults/gpio_defaults[6]
++ gpio_35_defaults/gpio_defaults[7] gpio_35_defaults/gpio_defaults[8] gpio_35_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xhousekeeping housekeeping/VGND housekeeping/VPWR soc/debug_in soc/debug_mode soc/debug_oeb
++ soc/debug_out soc/irq[3] soc/irq[4] soc/irq[5] user_id_value/mask_rev[0] user_id_value/mask_rev[10]
++ user_id_value/mask_rev[11] user_id_value/mask_rev[12] user_id_value/mask_rev[13]
++ user_id_value/mask_rev[14] user_id_value/mask_rev[15] user_id_value/mask_rev[16]
++ user_id_value/mask_rev[17] user_id_value/mask_rev[18] user_id_value/mask_rev[19]
++ user_id_value/mask_rev[1] user_id_value/mask_rev[20] user_id_value/mask_rev[21]
++ user_id_value/mask_rev[22] user_id_value/mask_rev[23] user_id_value/mask_rev[24]
++ user_id_value/mask_rev[25] user_id_value/mask_rev[26] user_id_value/mask_rev[27]
++ user_id_value/mask_rev[28] user_id_value/mask_rev[29] user_id_value/mask_rev[2]
++ user_id_value/mask_rev[30] user_id_value/mask_rev[31] user_id_value/mask_rev[3]
++ user_id_value/mask_rev[4] user_id_value/mask_rev[5] user_id_value/mask_rev[6] user_id_value/mask_rev[7]
++ user_id_value/mask_rev[8] user_id_value/mask_rev[9] housekeeping/mgmt_gpio_in[0]
++ housekeeping/mgmt_gpio_in[10] housekeeping/mgmt_gpio_in[11] housekeeping/mgmt_gpio_in[12]
++ housekeeping/mgmt_gpio_in[13] housekeeping/mgmt_gpio_in[14] housekeeping/mgmt_gpio_in[15]
++ housekeeping/mgmt_gpio_in[16] housekeeping/mgmt_gpio_in[17] housekeeping/mgmt_gpio_in[18]
++ housekeeping/mgmt_gpio_in[19] housekeeping/mgmt_gpio_in[1] housekeeping/mgmt_gpio_in[20]
++ housekeeping/mgmt_gpio_in[21] housekeeping/mgmt_gpio_in[22] housekeeping/mgmt_gpio_in[23]
++ housekeeping/mgmt_gpio_in[24] housekeeping/mgmt_gpio_in[25] housekeeping/mgmt_gpio_in[26]
++ housekeeping/mgmt_gpio_in[27] housekeeping/mgmt_gpio_in[28] housekeeping/mgmt_gpio_in[29]
++ housekeeping/mgmt_gpio_in[2] housekeeping/mgmt_gpio_in[30] housekeeping/mgmt_gpio_in[31]
++ housekeeping/mgmt_gpio_in[32] housekeeping/mgmt_gpio_in[33] housekeeping/mgmt_gpio_in[34]
++ housekeeping/mgmt_gpio_in[35] housekeeping/mgmt_gpio_in[36] housekeeping/mgmt_gpio_in[37]
++ housekeeping/mgmt_gpio_in[3] housekeeping/mgmt_gpio_in[4] housekeeping/mgmt_gpio_in[5]
++ housekeeping/mgmt_gpio_in[6] housekeeping/mgmt_gpio_in[7] housekeeping/mgmt_gpio_in[8]
++ housekeeping/mgmt_gpio_in[9] housekeeping/mgmt_gpio_oeb[0] housekeeping/mgmt_gpio_oeb[10]
++ housekeeping/mgmt_gpio_oeb[11] housekeeping/mgmt_gpio_oeb[12] housekeeping/mgmt_gpio_oeb[13]
++ housekeeping/mgmt_gpio_oeb[14] housekeeping/mgmt_gpio_oeb[15] housekeeping/mgmt_gpio_oeb[16]
++ housekeeping/mgmt_gpio_oeb[17] housekeeping/mgmt_gpio_oeb[18] housekeeping/mgmt_gpio_oeb[19]
++ housekeeping/mgmt_gpio_oeb[1] housekeeping/mgmt_gpio_oeb[20] housekeeping/mgmt_gpio_oeb[21]
++ housekeeping/mgmt_gpio_oeb[22] housekeeping/mgmt_gpio_oeb[23] housekeeping/mgmt_gpio_oeb[24]
++ housekeeping/mgmt_gpio_oeb[25] housekeeping/mgmt_gpio_oeb[26] housekeeping/mgmt_gpio_oeb[27]
++ housekeeping/mgmt_gpio_oeb[28] housekeeping/mgmt_gpio_oeb[29] housekeeping/mgmt_gpio_oeb[2]
++ housekeeping/mgmt_gpio_oeb[30] housekeeping/mgmt_gpio_oeb[31] housekeeping/mgmt_gpio_oeb[32]
++ housekeeping/mgmt_gpio_oeb[33] housekeeping/mgmt_gpio_oeb[34] housekeeping/mgmt_gpio_oeb[35]
++ housekeeping/mgmt_gpio_oeb[36] housekeeping/mgmt_gpio_oeb[37] housekeeping/mgmt_gpio_oeb[3]
++ housekeeping/mgmt_gpio_oeb[4] housekeeping/mgmt_gpio_oeb[5] housekeeping/mgmt_gpio_oeb[6]
++ housekeeping/mgmt_gpio_oeb[7] housekeeping/mgmt_gpio_oeb[8] housekeeping/mgmt_gpio_oeb[9]
++ housekeeping/mgmt_gpio_out[0] housekeeping/mgmt_gpio_in[10] housekeeping/mgmt_gpio_in[11]
++ housekeeping/mgmt_gpio_in[12] housekeeping/mgmt_gpio_in[13] housekeeping/mgmt_gpio_in[14]
++ housekeeping/mgmt_gpio_in[15] housekeeping/mgmt_gpio_in[16] housekeeping/mgmt_gpio_in[17]
++ housekeeping/mgmt_gpio_in[18] housekeeping/mgmt_gpio_in[19] housekeeping/mgmt_gpio_out[1]
++ housekeeping/mgmt_gpio_in[20] housekeeping/mgmt_gpio_in[21] housekeeping/mgmt_gpio_in[22]
++ housekeeping/mgmt_gpio_in[23] housekeeping/mgmt_gpio_in[24] housekeeping/mgmt_gpio_in[25]
++ housekeeping/mgmt_gpio_in[26] housekeeping/mgmt_gpio_in[27] housekeeping/mgmt_gpio_in[28]
++ housekeeping/mgmt_gpio_in[29] housekeeping/mgmt_gpio_in[2] housekeeping/mgmt_gpio_in[30]
++ housekeeping/mgmt_gpio_in[31] housekeeping/mgmt_gpio_in[32] housekeeping/mgmt_gpio_in[33]
++ housekeeping/mgmt_gpio_in[34] housekeeping/mgmt_gpio_out[35] housekeeping/mgmt_gpio_out[36]
++ housekeeping/mgmt_gpio_out[37] housekeeping/mgmt_gpio_in[3] housekeeping/mgmt_gpio_in[4]
++ housekeeping/mgmt_gpio_in[5] housekeeping/mgmt_gpio_in[6] housekeeping/mgmt_gpio_in[7]
++ housekeeping/mgmt_gpio_in[8] housekeeping/mgmt_gpio_in[9] padframe/flash_clk_core
++ padframe/flash_clk_oeb_core padframe/flash_csb_core padframe/flash_csb_oeb_core
++ padframe/flash_io0_di_core padframe/flash_io0_do_core padframe/flash_io0_ieb_core
++ padframe/flash_io0_oeb_core padframe/flash_io1_di_core padframe/flash_io1_do_core
++ padframe/flash_io1_ieb_core padframe/flash_io1_oeb_core clocking/sel2[0] clocking/sel2[1]
++ clocking/sel2[2] clocking/ext_clk_sel pll/dco pll/div[0] pll/div[1] pll/div[2] pll/div[3]
++ pll/div[4] pll/enable clocking/sel[0] clocking/sel[1] clocking/sel[2] pll/ext_trim[0]
++ pll/ext_trim[10] pll/ext_trim[11] pll/ext_trim[12] pll/ext_trim[13] pll/ext_trim[14]
++ pll/ext_trim[15] pll/ext_trim[16] pll/ext_trim[17] pll/ext_trim[18] pll/ext_trim[19]
++ pll/ext_trim[1] pll/ext_trim[20] pll/ext_trim[21] pll/ext_trim[22] pll/ext_trim[23]
++ pll/ext_trim[24] pll/ext_trim[25] pll/ext_trim[2] pll/ext_trim[3] pll/ext_trim[4]
++ pll/ext_trim[5] pll/ext_trim[6] pll/ext_trim[7] pll/ext_trim[8] pll/ext_trim[9]
++ por/porb_l housekeeping/pwr_ctrl_out[0] housekeeping/pwr_ctrl_out[1] housekeeping/pwr_ctrl_out[2]
++ housekeeping/pwr_ctrl_out[3] soc/qspi_enabled housekeeping/reset soc/ser_rx soc/ser_tx
++ housekeeping/serial_clock housekeeping/serial_data_1 housekeeping/serial_data_2
++ housekeeping/serial_load housekeeping/serial_resetn soc/spi_csb soc/spi_enabled
++ soc/spi_sck soc/spi_sdi soc/spi_sdo soc/spi_sdoenb soc/flash_clk soc/flash_csb soc/flash_io0_di
++ soc/flash_io0_do soc/flash_io0_oeb soc/flash_io1_di soc/flash_io1_do soc/flash_io1_oeb
++ soc/flash_io2_di soc/flash_io2_do soc/flash_io2_oeb soc/flash_io3_di soc/flash_io3_do
++ soc/flash_io3_oeb soc/sram_ro_addr[0] soc/sram_ro_addr[1] soc/sram_ro_addr[2] soc/sram_ro_addr[3]
++ soc/sram_ro_addr[4] soc/sram_ro_addr[5] soc/sram_ro_addr[6] soc/sram_ro_addr[7]
++ soc/sram_ro_clk soc/sram_ro_csb soc/sram_ro_data[0] soc/sram_ro_data[10] soc/sram_ro_data[11]
++ soc/sram_ro_data[12] soc/sram_ro_data[13] soc/sram_ro_data[14] soc/sram_ro_data[15]
++ soc/sram_ro_data[16] soc/sram_ro_data[17] soc/sram_ro_data[18] soc/sram_ro_data[19]
++ soc/sram_ro_data[1] soc/sram_ro_data[20] soc/sram_ro_data[21] soc/sram_ro_data[22]
++ soc/sram_ro_data[23] soc/sram_ro_data[24] soc/sram_ro_data[25] soc/sram_ro_data[26]
++ soc/sram_ro_data[27] soc/sram_ro_data[28] soc/sram_ro_data[29] soc/sram_ro_data[2]
++ soc/sram_ro_data[30] soc/sram_ro_data[31] soc/sram_ro_data[3] soc/sram_ro_data[4]
++ soc/sram_ro_data[5] soc/sram_ro_data[6] soc/sram_ro_data[7] soc/sram_ro_data[8]
++ soc/sram_ro_data[9] soc/trap soc/uart_enabled housekeeping/user_clock housekeeping/usr1_vcc_pwrgood
++ housekeeping/usr1_vdd_pwrgood housekeeping/usr2_vcc_pwrgood housekeeping/usr2_vdd_pwrgood
++ soc/hk_ack_i soc/mprj_adr_o[0] soc/mprj_adr_o[10] soc/mprj_adr_o[11] soc/mprj_adr_o[12]
++ soc/mprj_adr_o[13] soc/mprj_adr_o[14] soc/mprj_adr_o[15] soc/mprj_adr_o[16] soc/mprj_adr_o[17]
++ soc/mprj_adr_o[18] soc/mprj_adr_o[19] soc/mprj_adr_o[1] soc/mprj_adr_o[20] soc/mprj_adr_o[21]
++ soc/mprj_adr_o[22] soc/mprj_adr_o[23] soc/mprj_adr_o[24] soc/mprj_adr_o[25] soc/mprj_adr_o[26]
++ soc/mprj_adr_o[27] soc/mprj_adr_o[28] soc/mprj_adr_o[29] soc/mprj_adr_o[2] soc/mprj_adr_o[30]
++ soc/mprj_adr_o[31] soc/mprj_adr_o[3] soc/mprj_adr_o[4] soc/mprj_adr_o[5] soc/mprj_adr_o[6]
++ soc/mprj_adr_o[7] soc/mprj_adr_o[8] soc/mprj_adr_o[9] soc/core_clk soc/mprj_cyc_o
++ soc/mprj_dat_o[0] soc/mprj_dat_o[10] soc/mprj_dat_o[11] soc/mprj_dat_o[12] soc/mprj_dat_o[13]
++ soc/mprj_dat_o[14] soc/mprj_dat_o[15] soc/mprj_dat_o[16] soc/mprj_dat_o[17] soc/mprj_dat_o[18]
++ soc/mprj_dat_o[19] soc/mprj_dat_o[1] soc/mprj_dat_o[20] soc/mprj_dat_o[21] soc/mprj_dat_o[22]
++ soc/mprj_dat_o[23] soc/mprj_dat_o[24] soc/mprj_dat_o[25] soc/mprj_dat_o[26] soc/mprj_dat_o[27]
++ soc/mprj_dat_o[28] soc/mprj_dat_o[29] soc/mprj_dat_o[2] soc/mprj_dat_o[30] soc/mprj_dat_o[31]
++ soc/mprj_dat_o[3] soc/mprj_dat_o[4] soc/mprj_dat_o[5] soc/mprj_dat_o[6] soc/mprj_dat_o[7]
++ soc/mprj_dat_o[8] soc/mprj_dat_o[9] soc/hk_dat_i[0] soc/hk_dat_i[10] soc/hk_dat_i[11]
++ soc/hk_dat_i[12] soc/hk_dat_i[13] soc/hk_dat_i[14] soc/hk_dat_i[15] soc/hk_dat_i[16]
++ soc/hk_dat_i[17] soc/hk_dat_i[18] soc/hk_dat_i[19] soc/hk_dat_i[1] soc/hk_dat_i[20]
++ soc/hk_dat_i[21] soc/hk_dat_i[22] soc/hk_dat_i[23] soc/hk_dat_i[24] soc/hk_dat_i[25]
++ soc/hk_dat_i[26] soc/hk_dat_i[27] soc/hk_dat_i[28] soc/hk_dat_i[29] soc/hk_dat_i[2]
++ soc/hk_dat_i[30] soc/hk_dat_i[31] soc/hk_dat_i[3] soc/hk_dat_i[4] soc/hk_dat_i[5]
++ soc/hk_dat_i[6] soc/hk_dat_i[7] soc/hk_dat_i[8] soc/hk_dat_i[9] soc/core_rstn soc/mprj_sel_o[0]
++ soc/mprj_sel_o[1] soc/mprj_sel_o[2] soc/mprj_sel_o[3] soc/hk_stb_o soc/mprj_we_o
++ housekeeping
+Xgpio_control_in_2\[2\] gpio_21_defaults/gpio_defaults[0] gpio_21_defaults/gpio_defaults[10]
++ gpio_21_defaults/gpio_defaults[11] gpio_21_defaults/gpio_defaults[12] gpio_21_defaults/gpio_defaults[1]
++ gpio_21_defaults/gpio_defaults[2] gpio_21_defaults/gpio_defaults[3] gpio_21_defaults/gpio_defaults[4]
++ gpio_21_defaults/gpio_defaults[5] gpio_21_defaults/gpio_defaults[6] gpio_21_defaults/gpio_defaults[7]
++ gpio_21_defaults/gpio_defaults[8] gpio_21_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[21]
++ gpio_control_in_2\[2\]/one housekeeping/mgmt_gpio_in[21] gpio_control_in_2\[2\]/one
++ padframe/mprj_io_analog_en[21] padframe/mprj_io_analog_pol[21] padframe/mprj_io_analog_sel[21]
++ padframe/mprj_io_dm[63] padframe/mprj_io_dm[64] padframe/mprj_io_dm[65] padframe/mprj_io_holdover[21]
++ padframe/mprj_io_ib_mode_sel[21] padframe/mprj_io_in[21] padframe/mprj_io_inp_dis[21]
++ padframe/mprj_io_out[21] padframe/mprj_io_oeb[21] padframe/mprj_io_slow_sel[21]
++ padframe/mprj_io_vtrip_sel[21] gpio_control_in_2\[2\]/resetn gpio_control_in_2\[3\]/resetn
++ gpio_control_in_2\[2\]/serial_clock gpio_control_in_2\[3\]/serial_clock gpio_control_in_2\[2\]/serial_data_in
++ gpio_control_in_2\[1\]/serial_data_in gpio_control_in_2\[2\]/serial_load gpio_control_in_2\[3\]/serial_load
++ mprj/io_in[21] mprj/io_oeb[21] mprj/io_out[21] gpio_control_in_2\[2\]/vccd gpio_control_in_2\[2\]/vccd1
++ gpio_control_in_2\[2\]/vssd gpio_control_in_2\[2\]/vssd1 gpio_control_in_2\[2\]/zero
++ gpio_control_block
+Xgpio_control_in_1\[8\] gpio_16_defaults/gpio_defaults[0] gpio_16_defaults/gpio_defaults[10]
++ gpio_16_defaults/gpio_defaults[11] gpio_16_defaults/gpio_defaults[12] gpio_16_defaults/gpio_defaults[1]
++ gpio_16_defaults/gpio_defaults[2] gpio_16_defaults/gpio_defaults[3] gpio_16_defaults/gpio_defaults[4]
++ gpio_16_defaults/gpio_defaults[5] gpio_16_defaults/gpio_defaults[6] gpio_16_defaults/gpio_defaults[7]
++ gpio_16_defaults/gpio_defaults[8] gpio_16_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[16]
++ gpio_control_in_1\[8\]/one housekeeping/mgmt_gpio_in[16] gpio_control_in_1\[8\]/one
++ padframe/mprj_io_analog_en[16] padframe/mprj_io_analog_pol[16] padframe/mprj_io_analog_sel[16]
++ padframe/mprj_io_dm[48] padframe/mprj_io_dm[49] padframe/mprj_io_dm[50] padframe/mprj_io_holdover[16]
++ padframe/mprj_io_ib_mode_sel[16] padframe/mprj_io_in[16] padframe/mprj_io_inp_dis[16]
++ padframe/mprj_io_out[16] padframe/mprj_io_oeb[16] padframe/mprj_io_slow_sel[16]
++ padframe/mprj_io_vtrip_sel[16] gpio_control_in_1\[8\]/resetn gpio_control_in_1\[9\]/resetn
++ gpio_control_in_1\[8\]/serial_clock gpio_control_in_1\[9\]/serial_clock gpio_control_in_1\[8\]/serial_data_in
++ gpio_control_in_1\[9\]/serial_data_in gpio_control_in_1\[8\]/serial_load gpio_control_in_1\[9\]/serial_load
++ mprj/io_in[16] mprj/io_oeb[16] mprj/io_out[16] gpio_control_in_1\[8\]/vccd gpio_control_in_1\[8\]/vccd1
++ gpio_control_in_1\[8\]/vssd gpio_control_in_1\[8\]/vssd1 gpio_control_in_1\[8\]/zero
++ gpio_control_block
+Xgpio_29_defaults gpio_29_defaults/VGND gpio_29_defaults/VPWR gpio_29_defaults/gpio_defaults[0]
++ gpio_29_defaults/gpio_defaults[10] gpio_29_defaults/gpio_defaults[11] gpio_29_defaults/gpio_defaults[12]
++ gpio_29_defaults/gpio_defaults[1] gpio_29_defaults/gpio_defaults[2] gpio_29_defaults/gpio_defaults[3]
++ gpio_29_defaults/gpio_defaults[4] gpio_29_defaults/gpio_defaults[5] gpio_29_defaults/gpio_defaults[6]
++ gpio_29_defaults/gpio_defaults[7] gpio_29_defaults/gpio_defaults[8] gpio_29_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_13_defaults gpio_13_defaults/VGND gpio_13_defaults/VPWR gpio_13_defaults/gpio_defaults[0]
++ gpio_13_defaults/gpio_defaults[2] gpio_13_defaults/gpio_defaults[1] gpio_13_defaults/gpio_defaults[0]
++ gpio_13_defaults/gpio_defaults[1] gpio_13_defaults/gpio_defaults[2] gpio_13_defaults/gpio_defaults[9]
++ gpio_13_defaults/gpio_defaults[8] gpio_13_defaults/gpio_defaults[7] gpio_13_defaults/gpio_defaults[6]
++ gpio_13_defaults/gpio_defaults[7] gpio_13_defaults/gpio_defaults[8] gpio_13_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_in_1a\[5\] gpio_7_defaults/gpio_defaults[0] gpio_7_defaults/gpio_defaults[2]
++ gpio_7_defaults/gpio_defaults[1] gpio_7_defaults/gpio_defaults[0] gpio_7_defaults/gpio_defaults[1]
++ gpio_7_defaults/gpio_defaults[2] gpio_7_defaults/gpio_defaults[9] gpio_7_defaults/gpio_defaults[8]
++ gpio_7_defaults/gpio_defaults[7] gpio_7_defaults/gpio_defaults[6] gpio_7_defaults/gpio_defaults[7]
++ gpio_7_defaults/gpio_defaults[8] gpio_7_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[7]
++ gpio_control_in_1a\[5\]/one housekeeping/mgmt_gpio_in[7] gpio_control_in_1a\[5\]/one
++ padframe/mprj_io_analog_en[7] padframe/mprj_io_analog_pol[7] padframe/mprj_io_analog_sel[7]
++ padframe/mprj_io_dm[21] padframe/mprj_io_dm[22] padframe/mprj_io_dm[23] padframe/mprj_io_holdover[7]
++ padframe/mprj_io_ib_mode_sel[7] padframe/mprj_io_in[7] padframe/mprj_io_inp_dis[7]
++ padframe/mprj_io_out[7] padframe/mprj_io_oeb[7] padframe/mprj_io_slow_sel[7] padframe/mprj_io_vtrip_sel[7]
++ gpio_control_in_2\[7\]/resetn gpio_control_in_2\[8\]/resetn gpio_control_in_2\[7\]/serial_clock
++ gpio_control_in_2\[8\]/serial_clock gpio_control_in_1a\[5\]/serial_data_in gpio_control_in_1\[0\]/serial_data_in
++ gpio_control_in_2\[7\]/serial_load gpio_control_in_2\[8\]/serial_load mprj/io_in[7]
++ mprj/io_oeb[7] mprj/io_out[7] gpio_control_in_1a\[5\]/vccd gpio_control_in_1a\[5\]/vccd1
++ gpio_control_in_1a\[5\]/vssd gpio_control_in_1a\[5\]/vssd1 gpio_control_in_1a\[5\]/zero
++ gpio_control_block
+Xgpio_5_defaults gpio_5_defaults/VGND gpio_5_defaults/VPWR gpio_5_defaults/gpio_defaults[0]
++ gpio_5_defaults/gpio_defaults[2] gpio_5_defaults/gpio_defaults[1] gpio_5_defaults/gpio_defaults[0]
++ gpio_5_defaults/gpio_defaults[1] gpio_5_defaults/gpio_defaults[2] gpio_5_defaults/gpio_defaults[9]
++ gpio_5_defaults/gpio_defaults[8] gpio_5_defaults/gpio_defaults[7] gpio_5_defaults/gpio_defaults[6]
++ gpio_5_defaults/gpio_defaults[7] gpio_5_defaults/gpio_defaults[8] gpio_5_defaults/gpio_defaults[9]
++ gpio_defaults_block
+Xgpio_control_bidir_2\[2\] gpio_37_defaults/gpio_defaults[0] gpio_37_defaults/gpio_defaults[10]
++ gpio_37_defaults/gpio_defaults[11] gpio_37_defaults/gpio_defaults[12] gpio_37_defaults/gpio_defaults[1]
++ gpio_37_defaults/gpio_defaults[2] gpio_37_defaults/gpio_defaults[3] gpio_37_defaults/gpio_defaults[4]
++ gpio_37_defaults/gpio_defaults[5] gpio_37_defaults/gpio_defaults[6] gpio_37_defaults/gpio_defaults[7]
++ gpio_37_defaults/gpio_defaults[8] gpio_37_defaults/gpio_defaults[9] housekeeping/mgmt_gpio_in[37]
++ housekeeping/mgmt_gpio_oeb[37] housekeeping/mgmt_gpio_out[37] gpio_control_bidir_2\[2\]/one
++ padframe/mprj_io_analog_en[37] padframe/mprj_io_analog_pol[37] padframe/mprj_io_analog_sel[37]
++ padframe/mprj_io_dm[111] padframe/mprj_io_dm[112] padframe/mprj_io_dm[113] padframe/mprj_io_holdover[37]
++ padframe/mprj_io_ib_mode_sel[37] padframe/mprj_io_in[37] padframe/mprj_io_inp_dis[37]
++ padframe/mprj_io_out[37] padframe/mprj_io_oeb[37] padframe/mprj_io_slow_sel[37]
++ padframe/mprj_io_vtrip_sel[37] gpio_control_in_1\[10\]/resetn gpio_control_in_1\[10\]/resetn_out
++ gpio_control_in_1\[10\]/serial_clock gpio_control_in_1\[10\]/serial_clock_out housekeeping/serial_data_2
++ gpio_control_bidir_2\[1\]/serial_data_in gpio_control_in_1\[10\]/serial_load gpio_control_in_1\[10\]/serial_load_out
++ mprj/io_in[37] mprj/io_oeb[37] mprj/io_out[37] gpio_control_bidir_2\[2\]/vccd gpio_control_bidir_2\[2\]/vccd1
++ gpio_control_bidir_2\[2\]/vssd gpio_control_bidir_2\[2\]/vssd1 gpio_control_bidir_2\[2\]/zero
++ gpio_control_block
+Xgpio_01_defaults\[0\] gpio_01_defaults\[0\]/VGND gpio_01_defaults\[0\]/VPWR gpio_01_defaults\[0\]/gpio_defaults[0]
++ gpio_01_defaults\[0\]/gpio_defaults[2] gpio_01_defaults\[0\]/gpio_defaults[1] gpio_01_defaults\[0\]/gpio_defaults[0]
++ gpio_01_defaults\[0\]/gpio_defaults[1] gpio_01_defaults\[0\]/gpio_defaults[2] gpio_01_defaults\[0\]/gpio_defaults[9]
++ gpio_01_defaults\[0\]/gpio_defaults[8] gpio_01_defaults\[0\]/gpio_defaults[7] gpio_01_defaults\[0\]/gpio_defaults[6]
++ gpio_01_defaults\[0\]/gpio_defaults[7] gpio_01_defaults\[0\]/gpio_defaults[8] gpio_01_defaults\[0\]/gpio_defaults[9]
++ gpio_defaults_block
+.ends
+
diff --git a/caravel/verilog/dv/caravel/defs.h b/caravel/verilog/dv/caravel/defs.h
new file mode 100644
index 0000000..b80c639
--- /dev/null
+++ b/caravel/verilog/dv/caravel/defs.h
@@ -0,0 +1,234 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _CARAVEL_H_
+#define _CARAVEL_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_oenb (*(volatile uint32_t*)0x25000010)
+#define reg_la1_oenb (*(volatile uint32_t*)0x25000014)
+#define reg_la2_oenb (*(volatile uint32_t*)0x25000018)
+#define reg_la3_oenb (*(volatile uint32_t*)0x2500001c)
+
+#define reg_la0_iena (*(volatile uint32_t*)0x25000020)
+#define reg_la1_iena (*(volatile uint32_t*)0x25000024)
+#define reg_la2_iena (*(volatile uint32_t*)0x25000028)
+#define reg_la3_iena (*(volatile uint32_t*)0x2500002c)
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_irq (*(volatile uint32_t*)0x26100014)
+#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x2600003c)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x2600004c)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x2600005c)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x2600006c)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x2600007c)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000088)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x2600008c)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x260000a0)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b4)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b8)
+
+// Housekeeping
+#define reg_hkspi_status (*(volatile uint32_t*)0x26100000)
+#define reg_hkspi_chip_id (*(volatile uint32_t*)0x26100004)
+#define reg_hkspi_user_id (*(volatile uint32_t*)0x26100008)
+#define reg_hkspi_pll_ena (*(volatile uint32_t*)0x2610000c)
+#define reg_hkspi_pll_bypass (*(volatile uint32_t*)0x26100010)
+#define reg_hkspi_irq (*(volatile uint32_t*)0x26100014)
+#define reg_hkspi_reset (*(volatile uint32_t*)0x26100018)
+#define reg_hkspi_trap (*(volatile uint32_t*)0x26100028)
+#define reg_hkspi_pll_trim (*(volatile uint32_t*)0x2610001c)
+#define reg_hkspi_pll_source (*(volatile uint32_t*)0x26100020)
+#define reg_hkspi_pll_divider (*(volatile uint32_t*)0x26100024)
+#define reg_hkspi_disable (*(volatile uint32_t*)0x26200010)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0 0x00000001
+#define FLASH_BITBANG_IO1 0x00000002
+#define FLASH_BITBANG_CLK 0x00000010
+#define FLASH_BITBANG_CSB 0x00000020
+#define FLASH_BITBANG_OEB0 0x00000100
+#define FLASH_BITBANG_OEB1 0x00000200
+#define FLASH_ENABLE 0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE 0x01
+#define TIMER_ONESHOT 0x02
+#define TIMER_UPCOUNT 0x04
+#define TIMER_CHAIN 0x08
+#define TIMER_IRQ_ENABLE 0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK 0x00ff
+#define SPI_MASTER_MLB 0x0100
+#define SPI_MASTER_INV_CSB 0x0200
+#define SPI_MASTER_INV_CLK 0x0400
+#define SPI_MASTER_MODE_1 0x0800
+#define SPI_MASTER_STREAM 0x1000
+#define SPI_MASTER_ENABLE 0x2000
+#define SPI_MASTER_IRQ_ENABLE 0x4000
+#define SPI_HOUSEKEEPING_CONN 0x8000
+
+// System Area (0x2620_0000)
+#define reg_power_good (*(volatile uint32_t*)0x26200000)
+#define reg_clk_out_dest (*(volatile uint32_t*)0x26200004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x26200004)
+#define reg_irq_source (*(volatile uint32_t*)0x2620000C)
+
+// Management protection (0x2f00_0000)
+#define reg_irq_enable (*(volatile uint32_t*)0x2f000000)
+#define reg_wb_enable (*(volatile uint32_t*)0x2f000004)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+#define TRAP_MONITOR 0x04
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE 0x0001
+#define OUTPUT_DISABLE 0x0002
+#define HOLD_OVERRIDE 0x0004
+#define INPUT_DISABLE 0x0008
+#define MODE_SELECT 0x0010
+#define ANALOG_ENABLE 0x0020
+#define ANALOG_SELECT 0x0040
+#define ANALOG_POLARITY 0x0080
+#define SLOW_SLEW_MODE 0x0100
+#define TRIPPOINT_SEL 0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802
+#define GPIO_MODE_USER_STD_ANALOG 0x000a
+
+// --------------------------------------------------------
+#endif
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/Makefile
new file mode 100644
index 0000000..3d355f3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/Makefile
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_mgmt gpio mem uart perf hkspi sysctrl mprj_ctrl mprj_bitbang pass_thru timer timer2 pll storage qspi caravan irq user_pass_thru spi_master sram_exec hkspi_power
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile
new file mode 100644
index 0000000..8e9f4bf
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = caravan
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/README b/caravel/verilog/dv/caravel/mgmt_soc/caravan/README
new file mode 100644
index 0000000..a39b365
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/README
@@ -0,0 +1,27 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravan
+basic testbench
+------------------------------------------------
+
+This testbench exercises the basic use of the Caravan analog project
+harness, which is equivalent to the Caravel chip with 11 GPIOs
+removed from the top of the padframe and replaced with straight-through
+connections to pads.
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
new file mode 100644
index 0000000..feca129
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Caravan GPIO Test
+ *
+ * This is mainly a test of the digital I/O surrounding the analog
+ * pinouts on the caravan chip to make sure that they are connected
+ * properly after the middle GPIO pads and serial loader blocks are
+ * clipped out from the caravel design.
+ *
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* GPIO 14 to 24 have been replaced by analog and should be set */
+ /* to mode output to keep the input from floating. */
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0a000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xaa000000;
+
+ while (1) {
+ int x = (reg_mprj_datal & 0x3f80) >> 7;
+ reg_mprj_datal = (x+1) << 25;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
new file mode 100644
index 0000000..1b32be2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -0,0 +1,214 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+
+module caravan_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("caravan.vcd");
+ $dumpvars(0, caravan_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [6:0] checkbits_hi; // Upper 7 valid GPIO bits
+ wire [7:0] checkbits_lo; // Lower 6 valid GPIO bits (read)
+
+ reg [7:0] setbits_lo; // Lower 6 valid GPIO bits (write)
+
+ assign mprj_io[13:7] = setbits_lo;
+ assign checkbits_lo = mprj_io[13:7];
+ assign checkbits_hi = mprj_io[31:25];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ setbits_lo <= {7{1'bz}};
+ wait(checkbits_hi == 7'h50);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h30;
+ wait(checkbits_hi == 7'h05);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h0f;
+ wait(checkbits_hi == 7'h55);
+ repeat (1000) @(posedge clock);
+ setbits_lo <= 7'h00;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h01;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h03;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 7'h50); // 1st pull test
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Started");
+ `else
+ $display("Monitor: Test GPIO (RTL) Started");
+ `endif
+ wait(checkbits_lo == 7'h30); // (1st pull test result)
+ $display("Monitor: Check 1 seen");
+ wait(checkbits_hi == 7'h05); // 2nd pull test
+ $display("Monitor: Check 2 seen");
+ wait(checkbits_lo == 7'h0F); // (2nd pull test result)
+ $display("Monitor: Check 3 seen");
+ wait(checkbits_hi == 7'h55); // loopback test
+ $display("Monitor: Check 4 seen");
+ wait(checkbits_lo == 7'h00); // 1st value set
+ $display("Monitor: Check 5 seen");
+ wait(checkbits_hi == 7'h01); // 1st loopback read
+ $display("Monitor: Check 6 seen");
+ wait(checkbits_lo == 7'h01); // 2nd value set
+ $display("Monitor: Check 7 seen");
+ wait(checkbits_hi == 7'h02); // 2nd loopback read
+ $display("Monitor: Check 8 seen");
+ wait(checkbits_lo == 7'h03); // 3rd value set
+ $display("Monitor: Check 9 seen");
+ wait(checkbits_hi == 7'h04); // 3rd loopback read
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(mprj_io) begin
+ #1 $display("GPIO state = %b (%d - %d)", mprj_io,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("caravan.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile
new file mode 100644
index 0000000..1d067ac
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/README b/caravel/verilog/dv/caravel/mgmt_soc/gpio/README
new file mode 100644
index 0000000..baadc1f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/README
@@ -0,0 +1,44 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio testbench
+------------------------------------------------
+
+This testbench exercises the fundamental use of the Caravel
+management SoC to drive the I/O in the user area as general
+purpose I/O on startup.
+
+On startup, all GPIO are configured as input to the management
+region (so as to be high impedence to the external world) and
+decoupled from the user project area.
+
+To configure any GPIO as output, the appropriate memory-mapped
+location for the I/O must be properly configured. Since the
+I/O configuration is stored in two places, in the SoC, but
+also locally at each I/O pad, the "transfer" bit must be
+applied, which initiates a transfer of the configuration data
+around the padframe.
+
+The testbench takes 16 pins from the user area and checks
+functionality by applying input values on 8 of these pins from
+the testbench verilog, detecting them in the C program, then
+copying the values to the other 8 pins, and detecting those
+values in the testbench verilog.
+
+If any of that does not work, then the testbench will fail.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
new file mode 100644
index 0000000..73dd397
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xab000000;
+
+ while (1){
+ int x = (reg_mprj_datal & 0xff0000) >> 16;
+ reg_mprj_datal = (x+1) << 24;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
new file mode 100644
index 0000000..a6bd94d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -0,0 +1,196 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("gpio.vcd");
+ $dumpvars(0, gpio_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ checkbits_lo <= {8{1'bz}};
+ wait(checkbits_hi == 8'hA0);
+ checkbits_lo <= 8'hF0;
+ wait(checkbits_hi == 8'h0B);
+ checkbits_lo <= 8'h0F;
+ wait(checkbits_hi == 8'hAB);
+ checkbits_lo <= 8'h0;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h1;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h3;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 8'hA0);
+ wait(checkbits[7:0] == 8'hF0);
+ wait(checkbits_hi == 8'h0B);
+ wait(checkbits[7:0] == 8'h0F);
+ wait(checkbits_hi == 8'hAB);
+ wait(checkbits[7:0] == 8'h00);
+ wait(checkbits_hi == 8'h01);
+ wait(checkbits[7:0] == 8'h01);
+ wait(checkbits_hi == 8'h02);
+ wait(checkbits[7:0] == 8'h03);
+ wait(checkbits_hi == 8'h04);
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile
new file mode 100644
index 0000000..183307b
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio_mgmt
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c
new file mode 100644
index 0000000..3a3265c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Management SoC GPIO Pin Test
+ * Tests writing to the GPIO pin.
+ */
+
+void main()
+{
+ int i;
+
+ reg_gpio_data = 0;
+ reg_gpio_ena = 0;
+ reg_gpio_pu = 0;
+ reg_gpio_pd = 0;
+
+ for (i = 0; i < 10; i++) {
+ /* Fast blink for simulation */
+ reg_gpio_data = 1;
+ reg_gpio_data = 0;
+ }
+
+ while (1) {
+ /* Slow blink for demonstration board */
+ for (i = 0; i < 30000; i++) {
+ reg_gpio_data = 1;
+ }
+ for (i = 0; i < 30000; i++) {
+ reg_gpio_data = 0;
+ }
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v
new file mode 100644
index 0000000..b181dc3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v
@@ -0,0 +1,200 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_mgmt_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("gpio_mgmt.vcd");
+ $dumpvars(0, gpio_mgmt_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mgmt GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mgmt GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Monitor
+ initial begin
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ $display("Blink.");
+ wait(gpio == 1'b1);
+ wait(gpio == 1'b0);
+ `ifdef GL
+ $display("Monitor: Test Mgmt GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test Mgmt GPIO (RTL) Passed");
+ `endif
+ #2000;
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("Mgmt GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("gpio_mgmt.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
new file mode 100644
index 0000000..7ee89e9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = hkspi
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
new file mode 100644
index 0000000..3bfac32
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed, to show that the
+ // processor is interrupted only when the reset is applied
+ // through the SPI.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test message
+ print("\n");
+ print(" ____ _ ____ ____\n");
+ print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
+ print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+ print(" | __/| | (_| (_) |__) | (_) | |___\n");
+ print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
new file mode 100644
index 0000000..364c251
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -0,0 +1,431 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ StriVe housekeeping SPI testbench.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("hkspi.vcd");
+ $dumpvars(0, hkspi_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ // Delay, then bring chip out of reset
+ #1000;
+ RSTB <= 1'b1;
+ #2000;
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+
+ // Toggle external reset
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h01); // Data = 0x01 (apply external reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h00); // Data = 0x00 (release external reset)
+ end_csb();
+
+ // Read all registers (0 to 18)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h00); // Address (register 3 = product ID)
+ read_byte(tbdata);
+
+ $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+ if(tbdata !== 8'h56) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 3 = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
+ if(tbdata !== 8'h02) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+ if(tbdata !== 8'hef) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+ if(tbdata !== 8'h03) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+ if(tbdata !== 8'h12) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("hkspi.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/Makefile
new file mode 100644
index 0000000..ffe9fd6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = hkspi_power
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power.c b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power.c
new file mode 100644
index 0000000..3bfac32
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed, to show that the
+ // processor is interrupted only when the reset is applied
+ // through the SPI.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test message
+ print("\n");
+ print(" ____ _ ____ ____\n");
+ print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
+ print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+ print(" | __/| | (_| (_) |__) | (_) | |___\n");
+ print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
+
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power_tb.v
new file mode 100644
index 0000000..a00b4f4
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/hkspi_power/hkspi_power_tb.v
@@ -0,0 +1,430 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping SPI testbench with the user project powered
+ * down. The same as testbench "hkspi" but with user power set to
+ * zero.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_power_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("hkspi_power.vcd");
+ $dumpvars(0, hkspi_power_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ // Delay, then bring chip out of reset
+ #1000;
+ RSTB <= 1'b1;
+ #2000;
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+
+ // Toggle external reset
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h01); // Data = 0x01 (apply external reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 7 = external reset)
+ write_byte(8'h00); // Data = 0x00 (release external reset)
+ end_csb();
+
+ // Read all registers (0 to 18)
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h00); // Address (register 3 = product ID)
+ read_byte(tbdata);
+
+ $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+ if(tbdata !== 8'h56) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 3 = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
+ if(tbdata !== 8'h02) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+ if(tbdata !== 8'hef) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+ if(tbdata !== 8'h03) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+ if(tbdata !== 8'h12) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VSS), // User power supplies grounded
+ .vdda2 (VSS), // for this testbench.
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VSS),
+ .vccd2 (VSS),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("hkspi_power.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile
new file mode 100644
index 0000000..7737cba
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = irq
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+%.elf: %.c sections.lds start.S check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ start.S $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/README b/caravel/verilog/dv/caravel/mgmt_soc/irq/README
new file mode 100644
index 0000000..99d3cf9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/README
@@ -0,0 +1,32 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+irq testbench
+------------------------------------------------
+
+This testbench demonstrates how to use the interrupts on the
+picoRV32. It uses the internal picoRV32 counter to set up an
+interval timer. At each timer expiration, an interrupt is
+generated, and the assembler code in start.S runs and captures
+data from a routine emulating a Digilent PMOD MIC-3 microphone
+module. Data are accumulated in a ring buffer reserved in the
+top of memory. The main loop of the program queries the
+current ring buffer position, reads the data there, and
+displays the value on the GPIO (upper 16 of the lower 32 GPIO
+channels).
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S b/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S
new file mode 100644
index 0000000..e3d1e2d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S
@@ -0,0 +1,116 @@
+/*
+ * SPDX-FileCopyrightText: 2015 Clifford Wolf
+ * PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+#define regnum_q0 0
+#define regnum_q1 1
+#define regnum_q2 2
+#define regnum_q3 3
+
+#define regnum_x0 0
+#define regnum_x1 1
+#define regnum_x2 2
+#define regnum_x3 3
+#define regnum_x4 4
+#define regnum_x5 5
+#define regnum_x6 6
+#define regnum_x7 7
+#define regnum_x8 8
+#define regnum_x9 9
+#define regnum_x10 10
+#define regnum_x11 11
+#define regnum_x12 12
+#define regnum_x13 13
+#define regnum_x14 14
+#define regnum_x15 15
+#define regnum_x16 16
+#define regnum_x17 17
+#define regnum_x18 18
+#define regnum_x19 19
+#define regnum_x20 20
+#define regnum_x21 21
+#define regnum_x22 22
+#define regnum_x23 23
+#define regnum_x24 24
+#define regnum_x25 25
+#define regnum_x26 26
+#define regnum_x27 27
+#define regnum_x28 28
+#define regnum_x29 29
+#define regnum_x30 30
+#define regnum_x31 31
+
+#define regnum_zero 0
+#define regnum_ra 1
+#define regnum_sp 2
+#define regnum_gp 3
+#define regnum_tp 4
+#define regnum_t0 5
+#define regnum_t1 6
+#define regnum_t2 7
+#define regnum_s0 8
+#define regnum_s1 9
+#define regnum_a0 10
+#define regnum_a1 11
+#define regnum_a2 12
+#define regnum_a3 13
+#define regnum_a4 14
+#define regnum_a5 15
+#define regnum_a6 16
+#define regnum_a7 17
+#define regnum_s2 18
+#define regnum_s3 19
+#define regnum_s4 20
+#define regnum_s5 21
+#define regnum_s6 22
+#define regnum_s7 23
+#define regnum_s8 24
+#define regnum_s9 25
+#define regnum_s10 26
+#define regnum_s11 27
+#define regnum_t3 28
+#define regnum_t4 29
+#define regnum_t5 30
+#define regnum_t6 31
+
+// x8 is s0 and also fp
+#define regnum_fp 8
+
+#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
+.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
+
+#define picorv32_getq_insn(_rd, _qs) \
+r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_setq_insn(_qd, _rs) \
+r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
+
+#define picorv32_retirq_insn() \
+r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
+
+#define picorv32_maskirq_insn(_rd, _rs) \
+r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_waitirq_insn(_rd) \
+r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_timer_insn(_rd, _rs) \
+r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c
new file mode 100755
index 0000000..61dfcdd
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// -------------------------------------------------------------------------
+// Test IRQ callback
+// -------------------------------------------------------------------------
+
+uint16_t flag;
+
+void irq_callback()
+{
+ /* If this routine is called, then the test passes the 1st stage */
+ reg_mprj_datah = 0xa; // Signal end of test 1st stage
+ reg_mprj_datal = 0x20000;
+ flag = 1;
+ return;
+}
+
+void main()
+{
+ uint16_t data;
+ int i;
+
+ // Configure GPIO upper bits to assert the test code
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply the GPIO configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datah = 0x5; // Signal start of test
+ reg_mprj_datal = 0;
+ flag = 0;
+
+ // Loop, waiting for the interrupt to change reg_mprj_datah
+
+ while (flag == 0) {
+ reg_mprj_datal = 0x10000;
+ }
+ reg_mprj_datal = 0x40000;
+ reg_mprj_datah = 0xc; // Signal end of test
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v
new file mode 100755
index 0000000..0e03d6d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v
@@ -0,0 +1,172 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * Caravel - A full example SoC using PicoRV32 in SkyWater sky130
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2021 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module irq_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("irq.vcd");
+ $dumpvars(0, irq_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (12) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test IRQ (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test IRQ (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [3:0] status;
+ wire [3:0] checkbits;
+
+ assign checkbits = mprj_io[19:16];
+ assign status = mprj_io[35:32];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Monitor
+ initial begin
+ wait(status == 4'h5);
+ `ifdef GL
+ $display("Monitor: Test IRQ (GL) Started");
+ `else
+ $display("Monitor: Test IRQ (RTL) Started");
+ `endif
+ wait(status == 4'ha);
+ wait(status == 4'hc);
+ `ifdef GL
+ $display("Monitor: Test IRQ (GL) Passed");
+ `else
+ $display("Monitor: Test IRQ (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits, status) begin
+ #1 $display("GPIO state = %b (%b)", checkbits, status);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("irq.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds b/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds
new file mode 100755
index 0000000..c328222
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds
@@ -0,0 +1,83 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+/*
+ *-------------------------------------------------------------------------
+ * Note: This is like the default sections.lds file for Caravel, but moves
+ * the start of SRAM used by the compiler to address 0x80 to make room for
+ * memory used by the firmware routines defined in the local start.S file.
+ *-------------------------------------------------------------------------
+ */
+
+MEMORY {
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000080, LENGTH = 0x0380 /* 256 words (1 KB) */
+}
+
+SECTIONS {
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.srodata) /* .srodata sections (constants, strings, etc.) */
+ *(.srodata*) /* .srodata*sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } >FLASH
+
+ /* Initialized data section */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(4);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ /* Define the start of the heap */
+ .heap :
+ {
+ . = ALIGN(4);
+ _heap_start = .;
+ } >RAM
+}
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S b/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S
new file mode 100755
index 0000000..7c1c8a5
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/irq/start.S
@@ -0,0 +1,195 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*-----------------------------------------------*/
+/* Start code that enables and handles an IRQ */
+/*-----------------------------------------------*/
+
+#undef ENABLE_FASTIRQ
+
+#include "custom_ops.S"
+
+.section .text
+.global irq
+
+reset_vec:
+ j start
+
+/* Interrupt handler @ 0x10000004 */
+/* Requires defining a routine called irq_callback in the C code */
+
+.balign 4
+irq_vec:
+ sw gp, 0*4+0x10(zero)
+ sw t0, 1*4+0x10(zero)
+ sw t1, 2*4+0x10(zero)
+ sw t2, 3*4+0x10(zero)
+ sw t4, 4*4+0x10(zero)
+ sw t5, 5*4+0x10(zero)
+
+ call irq_callback
+
+ lw gp, 0*4+0x10(zero)
+ lw t0, 1*4+0x10(zero)
+ lw t1, 2*4+0x10(zero)
+ lw t2, 3*4+0x10(zero)
+ lw t4, 4*4+0x10(zero)
+ lw t5, 5*4+0x10(zero)
+
+ picorv32_retirq_insn()
+
+irq_regs:
+ .fill 32,8
+
+
+/* Main program */
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# Write these instructions to memory location zero and following:
+# lui t4, 0x10000 = 10000eb7
+# addi t4, t4, 4 = 0e91
+# jalr t4, 0 = 000e80e7
+#
+# These three instructions jump to 0x10000004, which is the location
+# of the interrupt handler. For a fast interrupt handler, the whole
+# handler should be moved into SRAM.
+
+li t4, 0x10000eb7
+sw t4, 0(zero)
+li t4, 0x80e70e91
+sw t4, 4(zero)
+li t4, 0x000e
+sw t4, 8(zero)
+
+# Enable the timer IRQ only
+li t4, 0xfff0
+picorv32_maskirq_insn(t4, t4)
+
+# Set the picorv32 32-bit counter/timer to trigger one interrupt.
+
+li t4, 0x1200
+picorv32_timer_insn(t4, t4)
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li t0, 0x02000000
+
+# Set CS high, IO0 is output
+li t1, 0x120
+sh t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+beqz a1, flashio_worker_L3
+li t5, 8
+lbu t2, 0(a0)
+flashio_worker_L2:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+lbu t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or t2, t2, t4
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L2
+sb t2, 0(a0)
+addi a0, a0, 1
+addi a1, a1, -1
+j flashio_worker_L1
+flashio_worker_L3:
+
+# Back to MEMIO mode
+li t1, 0x80
+sb t1, 3(t0)
+
+ret
+flashio_worker_end:
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile
new file mode 100644
index 0000000..59e93ff
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c
new file mode 100644
index 0000000..a3b6fcc
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Memory Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[10];
+unsigned short shorts[10];
+unsigned char bytes[10];
+
+void main()
+{
+ int i;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Word R/W
+ for (i=0; i<10; i++)
+ ints[i] = i*5000 + 10000;
+
+ for (i=0; i<10; i++)
+ if ((i*5000+10000) != ints[i])
+ reg_mprj_datal = 0xAB400000;
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Half Word R/W
+ reg_mprj_datal = 0xA0200000;
+ for (i=0; i<10; i++)
+ shorts[i] = i*500 + 100;
+
+ for(i=0; i<10; i++)
+ if((i*500+100) != shorts[i])
+ reg_mprj_datal = 0xAB200000;
+
+ reg_mprj_datal = 0xAB210000;
+
+ // Test byte R/W
+ reg_mprj_datal = 0xA0100000;
+ for(i=0; i<10; i++)
+ bytes[i] = i*5 + 10;
+
+ for(i=0; i<10; i++)
+ if((i*5+10) != bytes[i])
+ reg_mprj_datal = 0xAB100000;
+
+ reg_mprj_datal = 0xAB110000;
+}
\ No newline at end of file
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
new file mode 100644
index 0000000..4aa244a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -0,0 +1,203 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mem_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mem.vcd");
+ $dumpvars(0, mem_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test MEM (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test MEM (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ $display("Mem Test (word rw) started");
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ $display("Mem Test (short rw) started");
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA010) begin
+ $display("Mem Test (byte rw) started");
+ end
+ else if(checkbits == 16'hAB10) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB11) begin
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] passed");
+ `endif
+ $finish;
+ end
+
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mem.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/Makefile
new file mode 100644
index 0000000..229dde9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_bitbang
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang.c b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang.c
new file mode 100644
index 0000000..f53288f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang.c
@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * User Project IO Control by Bit-bang Method Test
+ */
+
+void main()
+{
+ /* This program does nothing but apply output bits to all */
+ /* GPIOs. Configuring the GPIOs is done by the verilog */
+ /* testbench through the housekeeping SPI. */
+
+ /* However, the internal config must match the controller */
+ /* config for the management SoC to apply output. */
+
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_datal = 0xffffffff;
+ reg_mprj_datah = 0x0000003f;
+
+ return;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang_tb.v
new file mode 100644
index 0000000..519b538
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang_tb.v
@@ -0,0 +1,489 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ Testbench of GPIO configuration through bit-bang method
+ using the StriVe housekeeping SPI.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_bitbang_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task bitbang_one_clock;
+ begin
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+ end
+ endtask
+
+ task bitbang_load;
+ begin
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h0e);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+ end
+ endtask
+
+ task bitbang_thirteen_clocks;
+ begin
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ bitbang_one_clock();
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("mprj_bitbang.vcd");
+ $dumpvars(0, mprj_bitbang_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ // Delay, then bring chip out of reset
+ #1000;
+ RSTB <= 1'b1;
+ #2000;
+
+ // Give 100us for the startup code to complete and the GPIO output
+ // value set.
+ #100000;
+
+ // NOTE: The SPI takes precedence over the wishbone back-door
+ // access and the GPIO lines will not get set from the program
+ // while CSB is held low. The C program keeps attempting a
+ // write and should succeed after the following code finishes
+ // and CSB is raised.
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h13); // Address (register 19 = GPIO bit-bang control)
+ write_byte(8'h66); // Data = 0x01 (enable bit-bang mode)
+ end_csb();
+
+ // Clock 12 times. Set data when clock is zero.
+ // (NOTE: Bits moved up by 1 compared to previous caravel version.
+ // the testbench was updated by bit shifting all the data up by 1.)
+ // Bits: (0 = serial xfer)
+ // 1 = bit-bang enable
+ // 2 = bit-bang resetn
+ // 3 = bit-bang load
+ // 4 = bit-bang clock
+ // 5 = bit-bang data user 1
+ // 6 = bit-bang data user 2
+
+ // Apply data 0x1809 (management standard output) to
+ // first block of user 1 and user 2 (GPIO 0 and 37)
+ // bits 0, 1, 9, and 12 are "1" (data go in backwards)
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h76); // bit 0
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h66);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h76); // bit 1
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 2
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 3
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 4
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 5
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 6
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 7
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 8
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h66);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h76); // bit 9
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 10
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h16); // bit 11
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h66);
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h76); // bit 12
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80);
+ write_byte(8'h13);
+ write_byte(8'h06);
+ end_csb();
+
+
+ // Toggle GPIO external control enable and clock forward 2 registers
+ // This moves ahead of the bidirectional registers at the front.
+ bitbang_thirteen_clocks();
+ bitbang_thirteen_clocks();
+ bitbang_load();
+
+ // There is no point in resetting bit bang mode because at
+ // this point the SPI pins just got disabled by loading zeros.
+
+ #10000;
+
+ // Timeout condition
+ `ifdef GL
+ $display("Monitor: Test GPIO bit-bang (GL) Failed");
+ `else
+ $display("Monitor: Test GPIO bit-bang (RTL) Failed");
+ `endif
+
+ $finish;
+ end
+
+ initial begin
+ // Wait for channel 35 to go high
+ wait(mprj_io[35] == 1'b1);
+
+ `ifdef GL
+ $display("Monitor: Test GPIO bit-bang (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO bit-bang (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mprj_bitbang.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..e1b13b6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..1d7a140
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * User Project IO Control Test
+ */
+
+void main()
+{
+ /* All GPIO pins are configured to be output */
+ /* The lower 28 bits are connected to the user */
+ /* project to output the counter result, and the */
+ /* upper 4 bits are connected to the management */
+ /* SoC to apply values that can be flagged by the */
+ /* testbench for specific benchmark tests. */
+
+ /* GPIOs 31 to 16 are connected to the management SoC */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* GPIOs 27 to 0 are connected to the user area */
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0x50000000;
+
+ // Write to IO Control
+ reg_mprj_io_0 = 0x004F;
+ if (reg_mprj_io_0 != 0x004F)
+ reg_mprj_datal = 0x60000000;
+ else
+ reg_mprj_datal = 0x70000000;
+
+ // Write to IO Control
+ reg_mprj_io_1 = 0x005F;
+ if (reg_mprj_io_1 != 0x005F)
+ reg_mprj_datal = 0x80000000;
+ else
+ reg_mprj_datal = 0x90000000;
+
+ // Write to IO Control
+ reg_mprj_io_2 = 0x006F;
+ if (reg_mprj_io_2 != 0x006F)
+ reg_mprj_datal = 0xA0000000;
+ else
+ reg_mprj_datal = 0xb0000000;
+
+ // Write to IO Control (NOTE: Only 13 bits are valid)
+ reg_mprj_io_3 = 0xF0F5;
+ if (reg_mprj_io_3 != 0x10F5)
+ reg_mprj_datal = 0xc0000000;
+ else
+ reg_mprj_datal = 0xd0000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..6ddfca3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,176 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mprj_ctrl_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] user_io;
+ wire SDO;
+
+ wire [3:0] checkbits;
+
+ assign checkbits = user_io[31:28];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_ctrl.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test User Project (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test User Project (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 4'h5) begin
+ $display("User Project control Test started");
+ end else if(checkbits == 4'h6) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: IO control R/W failed (check 6)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h7) begin
+ $display("Monitor: IO control R/W passed (check 7)");
+ end else if(checkbits == 4'h8) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 8)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'h9) begin
+ $display("Monitor: power control R/W passed (check 9)");
+ end else if(checkbits == 4'ha) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 10)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hb) begin
+ $display("Monitor: power control R/W passed (check 11)");
+ end else if(checkbits == 4'hc) begin
+ $display("%c[1;31m",27);
+ $display("Monitor: power control R/W failed (check 12)");
+ $display("%c[0m",27);
+ $finish;
+ end else if(checkbits == 4'hd) begin
+
+ $display("Monitor: power control R/W passed (check 13)");
+ `ifdef GL
+ $display("Monitor: User Project control (GL) test passed.");
+ `else
+ $display("Monitor: User Project control (RTL) test passed.");
+ `endif
+ $finish;
+ end
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(gpio) begin
+ #1 $display("GPIO state = %b ", gpio);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign user_io[3] = 1'b1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (user_io),
+ .flash_csb (flash_csb),
+ .flash_clk (flash_clk),
+ .flash_io0 (flash_io0),
+ .flash_io1 (flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("mprj_ctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
new file mode 100644
index 0000000..fbe5db6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pass_thru
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c
new file mode 100644
index 0000000..33a981d
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed. to show that the
+ // processor is halted while the SPI is accessing the
+ // flash SPI in pass-through mode.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test in progress
+ reg_mprj_datal = 0xa5000000;
+
+ // Test message
+ print("Test message\n");
+
+ // End test
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
new file mode 100644
index 0000000..00c9e6a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -0,0 +1,351 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module pass_thru_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("pass_thru.vcd");
+ $dumpvars(0, pass_thru_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ #2000;
+
+ RSTB <= 1'b1;
+
+ // Wait on start of program execution
+ wait(checkbits == 16'hA000);
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ // Now write a command directly to the SPI flash.
+ start_csb();
+ write_byte(8'hc4); // Pass-thru mode
+ write_byte(8'h03); // Command 03 (read values w/3-byte address
+ write_byte(8'h00); // Address is next three bytes (0x000000)
+ write_byte(8'h00);
+ write_byte(8'h00);
+
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ // Wait for processor to restart
+ wait(checkbits == 16'hA000);
+
+ // Read product ID register again
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pass_thru.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile
new file mode 100644
index 0000000..8e4c979
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = perf
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c
new file mode 100644
index 0000000..5a17ba2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c
@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Performance Test
+ It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[50];
+unsigned short shorts[50];
+unsigned char bytes[50];
+
+int main()
+{
+ int i;
+ int sum = 0;
+
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0;
+
+ // start test
+ reg_mprj_datal = 0xA0000000;
+
+ for (i=0; i<100; i++)
+ sum += (sum + i);
+
+ reg_mprj_datal = 0xAB000000;
+
+ return sum;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
new file mode 100644
index 0000000..25798ec
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -0,0 +1,159 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module perf_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ reg [31:0] kcycles;
+
+ initial begin
+ $dumpfile("perf.vcd");
+ $dumpvars(0, perf_tb);
+
+ kcycles = 0;
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ kcycles <= kcycles + 1;
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Performance (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Performance (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ //#1 $display("GPIO state = %X ", gpio);
+ if(checkbits == 16'hA000) begin
+ kcycles = 0;
+ $display("Performance Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ //$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
+ `ifdef GL
+ $display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+ `else
+ $display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("perf.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile
new file mode 100644
index 0000000..25874c1
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -0,0 +1,93 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pll
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c
new file mode 100644
index 0000000..978b53e
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * PLL Test (self-switching)
+ * - Switches PLL bypass in housekeeping
+ * - Changes PLL divider in housekeeping
+ *
+ */
+void main()
+{
+ int i;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Monitor pins must be set to output */
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+
+ /*
+ *-------------------------------------------------------------
+ * Register 2610_000c reg_hkspi_pll_ena
+ * SPI address 0x08 = PLL enables
+ * bit 0 = PLL enable, bit 1 = DCO enable
+ *
+ * Register 2610_0010 reg_hkspi_pll_bypass
+ * SPI address 0x09 = PLL bypass
+ * bit 0 = PLL bypass
+ *
+ * Register 2610_0020 reg_hkspi_pll_source
+ * SPI address 0x11 = PLL source
+ * bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
+ *
+ * Register 2610_0024 reg_hkspi_pll_divider
+ * SPI address 0x12 = PLL divider
+ * bits 0-4 = feedback divider
+ *
+ * Register 2620_0004 reg_clk_out_dest
+ * SPI address 0x1b = Output redirect
+ * bit 0 = trap to mprj_io[13]
+ * bit 1 = clk to mprj_io[14]
+ * bit 2 = clk2 to mprj_io[15]
+ *-------------------------------------------------------------
+ */
+
+ // Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
+ // reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
+
+ // Write checkpoint for clock counting (PLL bypassed)
+ reg_mprj_datal = 0xA0400000;
+ reg_clk_out_dest = 0x6;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0410000;
+
+ // Set PLL enable, no DCO mode
+ reg_hkspi_pll_ena = 0x1;
+
+ // Set PLL output divider to 0x03
+ reg_hkspi_pll_source = 0x3;
+
+ // Write checkpoint for clock counting (PLL bypassed)
+ reg_mprj_datal = 0xA0420000;
+ reg_clk_out_dest = 0x6;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0430000;
+
+ // Disable PLL bypass
+ reg_hkspi_pll_bypass = 0x0;
+
+ // Write checkpoint for clock counting
+ reg_mprj_datal = 0xA0440000;
+ reg_clk_out_dest = 0x6;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0450000;
+
+ // Write 0x03 to feedback divider (was 0x04)
+ reg_hkspi_pll_divider = 0x3;
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0460000;
+ reg_clk_out_dest = 0x6;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0470000;
+
+ // Write 0x04 to PLL output divider
+ reg_hkspi_pll_source = 0x4;
+
+ // Write checkpoint
+ reg_mprj_datal = 0xA0480000;
+ reg_clk_out_dest = 0x6;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0490000;
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
new file mode 100644
index 0000000..6d662c3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -0,0 +1,209 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module pll_tb;
+ reg clock;
+ reg power1;
+ reg power2;
+ reg RSTB;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ integer ccount;
+ integer ucount;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ // User clock monitoring
+ always @(posedge mprj_io[15]) begin
+ ucount = ucount + 1;
+ end
+
+ // Core clock monitoring
+ always @(posedge mprj_io[14]) begin
+ ccount = ccount + 1;
+ end
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("pll.vcd");
+ $dumpvars(0, pll_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test PLL (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+ $display("Monitor: Test 1 PLL (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA041);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 129 || ccount != 129) begin
+ $display("Monitor: Test PLL Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA042);
+ $display("Monitor: Test 2 PLL (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA043);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 193 || ccount != 193) begin
+ $display("Monitor: Test PLL Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA044);
+ $display("Monitor: Test 3 PLL (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA045);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 385 || ccount != 129) begin
+ $display("Monitor: Test PLL Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA046);
+ $display("Monitor: Test 4 PLL (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA047);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 385 || ccount != 129) begin
+ $display("Monitor: Test PLL Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA048);
+ $display("Monitor: Test 5 PLL (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA049);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 513 || ccount != 129) begin
+ $display("Monitor: Test PLL Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA090);
+
+ $display("Monitor: Test PLL (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("pll.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile
new file mode 100644
index 0000000..96fd19f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = qspi
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/README b/caravel/verilog/dv/caravel/mgmt_soc/qspi/README
new file mode 100644
index 0000000..4b3644a
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/README
@@ -0,0 +1,28 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+qspi testbench
+------------------------------------------------
+
+This testbench is mainly a copy of the gpio testbench and uses the
+same checks for pass/fail status. The difference is that the startup
+C code puts the SPI flash into QSPI/DDR/CRM modes for fastest access
+and enables the GPIO channels 36 and 37 to work as the flash IO2 and
+IO3 channels. If the channel and spimemio setup works correctly,
+then the testbench simulation will pass.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c
new file mode 100644
index 0000000..597e45f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c
@@ -0,0 +1,132 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set SPI flash latency to 8 for use with the spiflash.v
+ * module (note that spiflash.v does not have configuration
+ * registers emulated, so the external flash cannot be
+ * changed from its default of 8).
+ */
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now the flash SPI controller can be put in qspi/ddr/crm mode */
+ /* First run DSPI + CRM */
+ reg_spictrl = 0x80580000; // DSPI + CRM
+
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now run QSPI + CRM */
+ reg_spictrl = 0x80380000; // QSPI + CRM
+
+ reg_mprj_datal = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Now run QSPI + DDR + CRM */
+ reg_spictrl = 0x80780000; // QSPI + DDR + CRM
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xab000000;
+
+ while (1){
+ int x = (reg_mprj_datal & 0xff0000) >> 16;
+ reg_mprj_datal = (x+1) << 24;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
new file mode 100644
index 0000000..d8683b9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
@@ -0,0 +1,205 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module qspi_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("qspi.vcd");
+ $dumpvars(0, qspi_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [35:0] mprj_io; // Most of these are no-connects
+ wire [15:0] checkbits;
+ reg [7:0] checkbits_lo;
+ wire [7:0] checkbits_hi;
+
+ assign mprj_io[23:16] = checkbits_lo;
+ assign checkbits = mprj_io[31:16];
+ assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ checkbits_lo <= {8{1'bz}};
+ wait(checkbits_hi == 8'hA0);
+ checkbits_lo <= 8'hF0;
+ wait(checkbits_hi == 8'h0B);
+ checkbits_lo <= 8'h0F;
+ wait(checkbits_hi == 8'hAB);
+ checkbits_lo <= 8'h0;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h1;
+ repeat (1000) @(posedge clock);
+ checkbits_lo <= 8'h3;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 8'hA0);
+ `ifdef GL
+ $display("Monitor: Test QSPI (GL) Started");
+ `else
+ $display("Monitor: Test QSPI (RTL) Started");
+ `endif
+ wait(checkbits[7:0] == 8'hF0);
+ wait(checkbits_hi == 8'h0B);
+ wait(checkbits[7:0] == 8'h0F);
+ wait(checkbits_hi == 8'hAB);
+ wait(checkbits[7:0] == 8'h00);
+ wait(checkbits_hi == 8'h01);
+ wait(checkbits[7:0] == 8'h01);
+ wait(checkbits_hi == 8'h02);
+ wait(checkbits[7:0] == 8'h03);
+ wait(checkbits_hi == 8'h04);
+ `ifdef GL
+ $display("Monitor: Test QSPI (GL) Passed");
+ `else
+ $display("Monitor: Test QSPI (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b (%d - %d)", checkbits,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+ // flash_io2 = mgmt_gpio_io[36] (inout)
+ // flash_io3 = mgmt_gpio_io[37] (inout)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io ({flash_io3, flash_io2, mprj_io}),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("qspi.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(flash_io2),
+ .io3(flash_io3)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/spi_master/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/Makefile
new file mode 100644
index 0000000..5e25756
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = spi_master
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master.c b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master.c
new file mode 100644
index 0000000..8f21417
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master.c
@@ -0,0 +1,184 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * SPI master Test
+ * - Enables SPI master
+ * - Uses SPI master to talk to external SPI module
+ */
+void main()
+{
+ int i;
+ uint32_t value;
+
+ reg_mprj_datal = 0;
+
+ // For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
+ // should be outputs.
+
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Configure next 8 bits for writing the SPI value read on GPIO
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Enable SPI master
+ // SPI master configuration bits:
+ // bits 7-0: Clock prescaler value (default 2)
+ // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
+ // bit 9: CSB sense (0 = inverted, 1 = noninverted)
+ // bit 10: SCK sense (0 = noninverted, 1 = inverted)
+ // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
+ // bit 12: stream (1 = CSB ends transmission)
+ // bit 13: enable (1 = enabled)
+ // bit 14: IRQ enable (1 = enabled)
+ // bit 15: (unused)
+
+ reg_spimaster_config = 0x2002; // Enable, prescaler = 2,
+
+ // Apply stream read (0x40 + 0x03) and read back one byte
+
+ reg_spimaster_config = 0x3002; // Apply stream mode
+
+ reg_spimaster_data = 0xff; // Write 0xff (reset)
+ reg_spimaster_config = 0x2102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x3002; // Apply stream mode
+ reg_spimaster_data = 0xab; // Write 0xab (wakeup)
+ reg_spimaster_config = 0x2102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x3002; // Apply stream mode
+ reg_spimaster_data = 0x03; // Write 0x03 (read mode)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address high byte)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address middle byte)
+ reg_spimaster_data = 0x04; // Write 0x00 (start address low byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0410000 | (value << 8); // 0x93
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0420000 | (value << 8); // 0x01
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0430000 | (value << 8); // 0x00
+
+ reg_spimaster_config = 0x2102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x3002; // Apply stream mode
+ reg_spimaster_data = 0x03; // Write 0x03 (read mode)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address low byte)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address middle byte)
+ reg_spimaster_data = 0x08; // Write 0x08 (start address high byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0440000 | (value << 8); // 0x13
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0450000 | (value << 8); // 0x02
+
+ reg_spimaster_config = 0x2102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x3002; // Apply stream mode
+ reg_spimaster_data = 0x03; // Write 0x03 (read mode)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address high byte)
+ reg_spimaster_data = 0x00; // Write 0x00 (start address middle byte)
+ reg_spimaster_data = 0xa0; // Write 0xa0 (start address low byte)
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0460000 | (value << 8); // 0x63
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0470000 | (value << 8); // 0x57
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0480000 | (value << 8); // 0xb5
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA0490000 | (value << 8); // 0x00
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04a0000 | (value << 8); // 0x23
+
+ reg_spimaster_data = 0x00; // Write 0x00 for read
+ value = reg_spimaster_data; // Read back byte
+ // Write checkpoint
+ reg_mprj_datal = 0xA04b0000 | (value << 8); // 0x20
+
+ reg_spimaster_config = 0x2102; // Release CSB (ends stream mode)
+ reg_spimaster_config = 0x0002; // Disable the SPI master
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master_tb.v
new file mode 100644
index 0000000..e11e6cf
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/spi_master/spi_master_tb.v
@@ -0,0 +1,236 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module spi_master_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("spi_master.vcd");
+ $dumpvars(0, spi_master_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test SPI Master (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test SPI Master (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+ `ifdef GL
+ $display("Monitor: Test SPI Master (GL) Started");
+ `else
+ $display("Monitor: Test SPI Master (RTL) Started");
+ `endif
+ wait(checkbits == 16'hA041);
+ $display(" SPI value = 0x%x (should be 0x93)", spivalue);
+ if(spivalue !== 32'h93) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA042);
+ $display(" SPI value = 0x%x (should be 0x01)", spivalue);
+ if(spivalue !== 32'h01) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA043);
+ $display(" SPI value = 0x%x (should be 0x00)", spivalue);
+ if(spivalue !== 32'h00) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA044);
+ $display(" SPI value = 0x%x (should be 0x13)", spivalue);
+ if(spivalue !== 32'h13) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA045);
+ $display(" SPI value = 0x%x (should be 0x02)", spivalue);
+ if(spivalue !== 32'h02) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA046);
+ $display(" SPI value = 0x%x (should be 0x63)", spivalue);
+ if(spivalue !== 32'h63) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA047);
+ $display(" SPI value = 0x%x (should be 0x57)", spivalue);
+ if(spivalue !== 32'h57) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA048);
+ $display(" SPI value = 0x%x (should be 0xb5)", spivalue);
+ if(spivalue !== 32'hb5) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA049);
+ $display(" SPI value = 0x%x (should be 0x00)", spivalue);
+ if(spivalue !== 32'h00) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04a);
+ $display(" SPI value = 0x%x (should be 0x23)", spivalue);
+ if(spivalue !== 32'h23) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+ wait(checkbits == 16'hA04b);
+ $display(" SPI value = 0x%x (should be 0x20)", spivalue);
+ if(spivalue !== 32'h20) begin
+ $display("Monitor: Test SPI Master Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA090);
+ `ifdef GL
+ $display("Monitor: Test SPI Master (GL) Passed");
+ `else
+ $display("Monitor: Test SPI Master (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Keep CSB high
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("spi_master.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ /* Instantiate a 2nd SPI flash so the SPI master can talk to it */
+
+ spiflash #(
+ .FILENAME("spi_master.hex")
+ ) test_spi (
+ .csb(mprj_io[33]),
+ .clk(mprj_io[32]),
+ .io0(mprj_io[35]),
+ .io1(mprj_io[34]),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/Makefile
new file mode 100644
index 0000000..5e951a2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = sram_exec
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/README b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/README
new file mode 100644
index 0000000..ad92671
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/README
@@ -0,0 +1,24 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+sram_exec testbench
+------------------------------------------------
+
+This testbench demonstrates how to copy a portion of a program from
+flash memory into SRAM and to run it from there.
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec.c b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec.c
new file mode 100755
index 0000000..ac64d83
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec.c
@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// -------------------------------------------------------------------------
+// Test copying code into SRAM and running it from there.
+// -------------------------------------------------------------------------
+
+void test_function()
+{
+ int i;
+ reg_mprj_datah = 0xa; // Signal middle of test
+ for (i = 0; i < 10; i++) {
+ reg_mprj_datal = i << 16;
+ }
+ return;
+}
+
+void main()
+{
+ uint16_t func[&main - &test_function];
+ uint16_t *src_ptr;
+ uint16_t *dst_ptr;
+
+ // Copy test routine from flash into SRAM
+ // Configure GPIO upper bits to assert the test code
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply the GPIO configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datah = 0x5; // Signal start of test
+ reg_mprj_datal = 0;
+
+ src_ptr = &test_function;
+ dst_ptr = func;
+
+ while (src_ptr != &main)
+ *(dst_ptr++) = *(src_ptr++);
+
+ // Call the routine in SRAM
+
+ ((void(*)())func)();
+
+ reg_mprj_datal = 0x40000;
+ reg_mprj_datah = 0xc; // Signal end of test
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec_tb.v
new file mode 100755
index 0000000..dc9eff4
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sram_exec/sram_exec_tb.v
@@ -0,0 +1,177 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * Caravel - A full example SoC using PicoRV32 in SkyWater sky130
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2021 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module sram_exec_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("sram_exec.vcd");
+ $dumpvars(0, sram_exec_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (60) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test SRAM exec (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test SRAM exec (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [3:0] status;
+ wire [3:0] checkbits;
+
+ assign checkbits = mprj_io[19:16];
+ assign status = mprj_io[35:32];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Monitor
+ initial begin
+ wait(status == 4'h5);
+ `ifdef GL
+ $display("Monitor: Test SRAM exec (GL) Started");
+ `else
+ $display("Monitor: Test SRAM exec (RTL) Started");
+ `endif
+ wait(status == 4'ha);
+ `ifdef GL
+ $display("Monitor: Test SRAM exec (GL) called SRAM routine");
+ `else
+ $display("Monitor: Test SRAM exec (RTL) called SRAM routine");
+ `endif
+ wait(status == 4'hc);
+ `ifdef GL
+ $display("Monitor: Test SRAM exec (GL) Passed");
+ `else
+ $display("Monitor: Test SRAM exec (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits, status) begin
+ #1 $display("GPIO state = %b (%b)", checkbits, status);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("sram_exec.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile
new file mode 100644
index 0000000..21eff79
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c
new file mode 100644
index 0000000..5d738b9
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ Storage area Test
+ It uses GPIO to flag the success or failure of the test
+*/
+
+void main()
+{
+ int i;
+ volatile uint32_t* ram_addr;
+ /* Upper 16 user area pins are configured to be GPIO output */
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // start test
+ reg_mprj_datal = 0xA0400000;
+
+ // Test Management R/W block0
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=0; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB400000;
+ }
+
+ reg_mprj_datal = 0xAB410000;
+
+ // Test Management R/W block0 > 1K address
+ reg_mprj_datal = 0xA0200000;
+ for (i=256; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ *ram_addr = i*5000 + 10000;
+ }
+
+ for (i=256; i<10; i++){
+ ram_addr = ®_rw_block0 + i;
+ if ((i*5000+10000) != *ram_addr)
+ reg_mprj_datal = 0xAB200000;
+ }
+
+ reg_mprj_datal = 0xAB210000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
new file mode 100644
index 0000000..0adee87
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -0,0 +1,190 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module storage_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ assign checkbits = mprj_io[31:16];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("storage.vcd");
+ $dumpvars(0, storage_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (100) begin
+ repeat (1000) @(posedge clock);
+ //$display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Storage (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Storage (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA040) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block0 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB40) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB41) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed");
+ `endif
+ end
+ else if(checkbits == 16'hA020) begin
+ `ifdef GL
+ $display("Mem Test storage MGMT block1 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+ `endif
+ end
+ else if(checkbits == 16'hAB20) begin
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+ else if(checkbits == 16'hAB21) begin
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VSS = 1'b0;
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("storage.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
new file mode 100644
index 0000000..8bfb5c6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = sysctrl
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
new file mode 100644
index 0000000..f55bc3f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * System control test
+ * - Sets GPIO to monitor the core and user clocks
+ *
+ * This test is basically just the first part of the
+ * PLL test, with the PLL bypassed. Unlike the PLL
+ * test, it can be run on a gate-level netlist.
+ *
+ */
+void main()
+{
+ int i;
+
+ reg_mprj_datal = 0;
+
+ // Configure upper 16 bits of user GPIO for generating testbench
+ // checkpoints.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Monitor pins must be set to output */
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+
+ /*
+ *-------------------------------------------------------------
+ * Register 2620_0004 reg_clk_out_dest
+ * SPI address 0x1b = Output redirect
+ * bit 0 = trap to mprj_io[13]
+ * bit 1 = clk to mprj_io[14]
+ * bit 2 = clk2 to mprj_io[15]
+ *-------------------------------------------------------------
+ */
+
+ // Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
+ // reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
+
+ // Write checkpoint for making sure nothing is counted when monitoring is off
+ reg_mprj_datal = 0xA0400000;
+ reg_clk_out_dest = 0x0;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0410000;
+
+ // Write checkpoint for core clock counting (PLL bypassed)
+ reg_mprj_datal = 0xA0420000;
+ reg_clk_out_dest = 0x2;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0430000;
+
+ // Write checkpoint for user clock counting (PLL bypassed)
+ reg_mprj_datal = 0xA0440000;
+ reg_clk_out_dest = 0x4;
+ reg_clk_out_dest = 0x0;
+ reg_mprj_datal = 0xA0450000;
+
+ // End test
+ reg_mprj_datal = 0xA0900000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
new file mode 100644
index 0000000..26d279c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -0,0 +1,187 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module sysctrl_tb;
+ reg clock;
+ reg power1;
+ reg power2;
+ reg RSTB;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [7:0] spivalue;
+ wire [37:0] mprj_io;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire SDO;
+
+ integer ccount;
+ integer ucount;
+
+ assign checkbits = mprj_io[31:16];
+ assign spivalue = mprj_io[15:8];
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10 clock <= (clock === 1'b0);
+
+ // User clock monitoring
+ always @(posedge mprj_io[15]) begin
+ ucount = ucount + 1;
+ end
+
+ // Core clock monitoring
+ always @(posedge mprj_io[14]) begin
+ ccount = ccount + 1;
+ end
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("sysctrl.vcd");
+ $dumpvars(0, sysctrl_tb);
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits == 16'hA040);
+ $display("Monitor: Test 1 Sysctrl (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA041);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 0 || ccount != 0) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA042);
+ $display("Monitor: Test 1 Sysctrl (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA043);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 129 || ccount != 0) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA044);
+ $display("Monitor: Test 2 Sysctrl (RTL) Started");
+ ucount = 0;
+ ccount = 0;
+ wait(checkbits == 16'hA045);
+ $display("Monitor: ucount = %d ccount = %d", ucount, ccount);
+ if (ucount !== 0 || ccount != 129) begin
+ $display("Monitor: Test Sysctrl Failed");
+ $finish;
+ end
+
+ wait(checkbits == 16'hA090);
+
+ $display("Monitor: Test Sysctrl (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("GPIO state = %b ", checkbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("sysctrl.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile
new file mode 100644
index 0000000..fc03d06
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+.SUFFIXES:
+
+PATTERN = timer
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c
new file mode 100644
index 0000000..e01ed7f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer Test
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer0_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer0_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer0_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer0_value = 0x00000011;
+ reg_timer0_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000101; // Set value (will be reset)
+ reg_timer0_config = 2; /* Disabled, one-shot, count up */
+ reg_timer0_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer0_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x05;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
new file mode 100644
index 0000000..3865bf3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -0,0 +1,201 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer_tb;
+
+ reg RSTB;
+ reg clock;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer.vcd");
+ $dumpvars(0, timer_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (50) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Started");
+ `else
+ $display("Monitor: Test Timer (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== ((32'h0f) | (3'b100))) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Passed");
+ `else
+ $display("Monitor: Test Timer (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile
new file mode 100644
index 0000000..9c408bc
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+.SUFFIXES:
+
+PATTERN = timer2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
new file mode 100644
index 0000000..6d598ac
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Timer2 Test --- This runs the same testbench as the
+ * other timer, on the 2nd counter/timer module instance.
+ */
+
+void main()
+{
+ int i;
+ uint32_t value;
+
+ /* Initialize output data vector to zero */
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datal = 0x00000000;
+
+ /* Apply all 38 bits to management standard output. */
+
+ /* The lower 32 will be used to output the count value */
+ /* from the timer. The top 5 bits will be used to mark */
+ /* specific checkpoints for the testbench simulation. */
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Present start marker (see testbench verilog) */
+ reg_mprj_datah = 0x0a;
+
+ /* Configure timer for a single-shot countdown */
+ reg_timer1_value = 0xdcba9876;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 3; /* Enabled, one-shot, down count */
+
+ for (i = 0; i < 8; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_timer1_config = 0; /* Disabled */
+
+ reg_mprj_datah = 0x01; /* Check value in testbench */
+
+ reg_timer1_value = 0x00000011;
+ reg_timer1_config = 7; /* Enabled, one-shot, count up */
+
+ for (i = 0; i < 3; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x02; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000101; // Set value (will be reset)
+ reg_timer1_config = 2; /* Disabled, one-shot, count up */
+ reg_timer1_config = 5; /* Enabled, continuous, count down */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x03; /* Check value in testbench */
+
+ reg_timer1_data = 0x00000145; // Force new value
+
+ reg_mprj_datah = 0x04; /* Check value in testbench */
+
+ for (i = 0; i < 5; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x05; /* Check value in testbench */
+
+ /* Now, set up chained 64 bit timer. Check count-up */
+ /* value and count-down value crossing the 32-bit */
+ /* boundary. */
+
+ /* First disable both counters, and set the "chained" */
+ /* property so that enable/disable will be synchronized */
+
+ reg_timer1_config = 8; /* Disabled, chained */
+ reg_timer0_config = 8; /* Disabled, chained */
+
+ /* Configure timer for a chained single-shot countdown. */
+ /* Count start = 0x0000000100001000, end = 0x0 */
+
+ reg_timer1_value = 0x00000055;
+ reg_timer0_value = 0x00001000;
+
+ /* Timer configuration bits: */
+ /* 0 = timer enable (1 = enabled, 0 = disabled) */
+ /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
+ /* 2 = up/down (1 = count up, 0 = count down) */
+ /* 3 = chain (1 = enabled, 0 = disabled) */
+ /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
+
+ reg_timer1_config = 11; /* Enabled, one-shot, down count, chained */
+ reg_timer0_config = 11; /* Enabled, one-shot, down count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x06; /* Check value in testbench */
+
+ // Skip to the end. . .
+ reg_timer1_data = 0x00000000;
+ reg_timer0_data = 0x00000200;
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x07; /* Check value in testbench */
+
+ reg_timer1_config = 14; /* Disabled, one-shot, up count, chained */
+ reg_timer0_config = 14; /* Disabled, one-shot, up count, chained */
+
+ reg_timer1_value = 0x00000002;
+ reg_timer0_value = 0x00000000;
+
+ reg_timer1_config = 15; /* Enabled, one-shot, up count, chained */
+ reg_timer0_config = 15; /* Enabled, one-shot, up count, chained */
+
+ for (i = 0; i < 1; i++) {
+ value = reg_timer0_data;
+ reg_mprj_datal = value; // Put count value on GPIO
+ }
+
+ reg_mprj_datah = 0x08; /* Check value in testbench */
+
+ // Skip to the end. . .
+ /* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
+
+ reg_timer1_data = 0x00000001; // Set value (will be reset)
+ reg_timer0_data = 0xffffff00; // Set value (will be reset)
+
+ for (i = 0; i < 4; i++) {
+ value = reg_timer1_data;
+ reg_mprj_datal = value; // Put timer1 count value on GPIO
+ }
+
+ /* Present end marker (see testbench verilog) */
+ reg_mprj_datah = 0x10;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
new file mode 100644
index 0000000..a53e216
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -0,0 +1,229 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer2_tb;
+
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("timer2.vcd");
+ $dumpvars(0, timer2_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (60) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [5:0] checkbits;
+ wire [31:0] countbits;
+
+ assign checkbits = mprj_io[37:32];
+ assign countbits = mprj_io[31:0];
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ // Monitor
+ initial begin
+ wait(checkbits == 6'h0a);
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Started");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Started");
+ `endif
+ /* Add checks here */
+ wait(checkbits == 6'h01);
+ $display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+ if(countbits !== 32'hdcba7cfb) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h02);
+ $display(" countbits = 0x%x (should be 0x19)", countbits);
+ if(countbits !== 32'h19) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h03);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h04);
+ $display(" countbits = %x (should be 0x0f)", countbits);
+ if(countbits !== 32'h0f) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+ wait(checkbits == 6'h05);
+ $display(" countbits = %x (should be 0x12bc)", countbits);
+ if(countbits !== 32'h12bc) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h06);
+ $display(" countbits = %x (should be 0x005d)", countbits);
+ if(countbits !== 32'h005d) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h07);
+ $display(" countbits = %x (should be 0x0008)", countbits);
+ if(countbits !== 32'h0008) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h08);
+ $display(" countbits = %x (should be 0x0259)", countbits);
+ if(countbits !== 32'h0259) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ wait(checkbits == 6'h10);
+ $display(" countbits = %x (should be 0x000a)", countbits);
+ if(countbits !== 32'h000a) begin
+ $display("Monitor: Test Timer2 (RTL) Failed");
+ $finish;
+ end
+
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Passed");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ #1 $display("Timer state = %b (%d)", countbits, countbits);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("timer2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile
new file mode 100644
index 0000000..024a956
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c
new file mode 100644
index 0000000..13cee0f
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+void main()
+{
+ int j;
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set clock to 64 kbaud and enable the UART. It is important to do this
+ // before applying the configuration, or else the Tx line initializes as
+ // zero, which indicates the start of a byte to the receiver.
+
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Now, apply the configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // This should appear at the output, received by the testbench UART.
+ // (Makes simulation time long.)
+ print("Monitor: Test UART (RTL) passed\n");
+
+ // Allow transmission to complete before signalling that the program
+ // has ended.
+ for (j = 0; j < 20; j++);
+ reg_mprj_datal = 0xab000000;
+}
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
new file mode 100644
index 0000000..d8bbd35
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -0,0 +1,150 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module uart_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire uart_tx;
+ wire SDO;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("uart.vcd");
+ $dumpvars(0, uart_tb);
+
+ $display("Wait for UART o/p");
+ repeat (150) begin
+ repeat (10000) @(posedge clock);
+ // Diagnostic. . . interrupts output pattern.
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ always @(checkbits) begin
+ if(checkbits == 16'hA000) begin
+ $display("UART Test started");
+ end
+ else if(checkbits == 16'hAB00) begin
+ `ifdef GL
+ $display("UART Test (GL) passed");
+ `else
+ $display("UART Test (RTL) passed");
+ `endif
+ $finish;
+ end
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("uart.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile
new file mode 100644
index 0000000..1659de5
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile
@@ -0,0 +1,91 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = user_pass_thru
+
+# Path to management SoC wrapper repository
+MGMT_CORE_PATH ?= ~/gits/caravel_pico
+ifeq ($(SIM),RTL)
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
+else
+ MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
+endif
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README
new file mode 100644
index 0000000..e4072d6
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README
@@ -0,0 +1,14 @@
+------------------------------------
+user_pass_thru test bench
+------------------------------------
+
+This test bench exercises the pass-thru mode to the GPIO pins
+that are reserved for use by a user project for connecting to
+an SPI flash. The pass-thru mode allows the SPI flash to be
+programmed using the housekeeping SPI.
+
+The testbench is essentially the same as the pass_thru test
+bench, but using the pins specified for the secondary SPI
+flash. Note that the testbench does not define a controller
+on the user side to access the SPI flash (which would be a
+useful thing to add to the testbench).
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c
new file mode 100644
index 0000000..011102c
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+ // This program is just to keep the processor busy while the
+ // housekeeping SPI is being accessed. to show that the
+ // processor is halted while the SPI is accessing the
+ // flash SPI in pass-through mode.
+
+ // Configure I/O: High 16 bits of user area used for a 16-bit
+ // word to write and be detected by the testbench verilog.
+ // Only serial Tx line is used in this testbench. It connects
+ // to mprj_io[6]. Since all lines of the chip are input or
+ // high impedence on startup, the I/O has to be configured
+ // for output
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Management needs to apply output on these pads to access the user area SPI flash
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Apply configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Start test
+ reg_mprj_datal = 0xa0000000;
+
+ // Set clock to 64 kbaud and enable the UART
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ // Test in progress
+ reg_mprj_datal = 0xa5000000;
+
+ // Test message
+ print("Test message\n");
+
+ // End test
+ reg_mprj_datal = 0xab000000;
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v
new file mode 100644
index 0000000..b7532b8
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v
@@ -0,0 +1,399 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ * StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module user_pass_thru_tb;
+ reg clock;
+ reg SDI, CSB, SCK, RSTB;
+ reg power1, power2;
+
+ wire gpio;
+ wire [15:0] checkbits;
+ wire [37:0] mprj_io;
+ wire uart_tx;
+ wire uart_rx;
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire flash_io2;
+ wire flash_io3;
+
+ wire user_csb;
+ wire user_clk;
+ wire user_io0;
+ wire user_io1;
+
+ wire SDO;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ // The main testbench is here. Put the housekeeping SPI into
+ // pass-thru mode and read several bytes from the flash SPI.
+
+ // First define tasks for SPI functions
+
+ task start_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b0;
+ #50;
+ end
+ endtask
+
+ task end_csb;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ CSB <= 1'b1;
+ #50;
+ end
+ endtask
+
+ task write_byte;
+ input [7:0] odata;
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_byte;
+ output [7:0] idata;
+ begin
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ task read_write_byte
+ (input [7:0] odata,
+ output [7:0] idata);
+ begin
+ SCK <= 1'b0;
+ for (i=7; i >= 0; i--) begin
+ #50;
+ SDI <= odata[i];
+ idata[i] = SDO;
+ #50;
+ SCK <= 1'b1;
+ #100;
+ SCK <= 1'b0;
+ end
+ end
+ endtask
+
+ integer i;
+
+ // Now drive the digital signals on the housekeeping SPI
+ reg [7:0] tbdata;
+
+ initial begin
+ $dumpfile("user_pass_thru.vcd");
+ $dumpvars(0, user_pass_thru_tb);
+
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
+ RSTB <= 1'b0;
+
+ #2000;
+
+ RSTB <= 1'b1;
+
+ // Wait on start of program execution
+ wait(checkbits == 16'hA000);
+
+ // First do a normal read from the housekeeping SPI to
+ // make sure the housekeeping SPI works.
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ // The SPI flash may need to be reset.
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'hff); // SPI flash command ff
+ end_csb();
+
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'hab); // SPI flash command ab
+ end_csb();
+
+ start_csb();
+ write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+ write_byte(8'h03); // Command 03 (read values w/3-byte address)
+ write_byte(8'h00); // Address is next three bytes (0x000000)
+ write_byte(8'h00);
+ write_byte(8'h00);
+
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+ read_byte(tbdata);
+ $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ end_csb();
+
+ // Reset processor
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 11 = reset)
+ write_byte(8'h01); // Data (value 1 = apply reset)
+ end_csb();
+
+ start_csb();
+ write_byte(8'h80); // Write stream command
+ write_byte(8'h0b); // Address (register 11 = reset)
+ write_byte(8'h00); // Data (value 1 = apply reset)
+ end_csb();
+
+ // Wait for processor to restart
+ wait(checkbits == 16'hA000);
+
+ // Read product ID register again
+
+ start_csb();
+ write_byte(8'h40); // Read stream command
+ write_byte(8'h03); // Address (register 3 = product ID)
+ read_byte(tbdata);
+ end_csb();
+ #10;
+ $display("Read data = 0x%02x (should be 0x11)", tbdata);
+ if(tbdata !== 8'h11) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
+
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
+ #10000;
+ $finish;
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ wire hk_sck;
+ wire hk_csb;
+ wire hk_sdi;
+
+ assign hk_sck = SCK;
+ assign hk_csb = CSB;
+ assign hk_sdi = SDI;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[5] = uart_rx;
+ assign mprj_io[4] = hk_sck;
+ assign mprj_io[3] = hk_csb;
+ assign mprj_io[2] = hk_sdi;
+ assign SDO = mprj_io[1];
+
+ assign user_csb = mprj_io[8];
+ assign user_clk = mprj_io[9];
+ assign user_io0 = mprj_io[10];
+ assign mprj_io[11] = user_io1;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("user_pass_thru.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Use the same flash; this is just to put known data in memory that can be
+ // checked by reading it back through a pass-through command.
+ spiflash #(
+ .FILENAME("user_pass_thru.hex")
+ ) secondary (
+ .csb(user_csb),
+ .clk(user_clk),
+ .io0(user_io0),
+ .io1(user_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/dv/caravel/sections.lds b/caravel/verilog/dv/caravel/sections.lds
new file mode 100644
index 0000000..2d8c048
--- /dev/null
+++ b/caravel/verilog/dv/caravel/sections.lds
@@ -0,0 +1,75 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+MEMORY {
+ FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 256 words (1 KB) */
+}
+
+SECTIONS {
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.srodata) /* .srodata sections (constants, strings, etc.) */
+ *(.srodata*) /* .srodata*sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ _etext = .; /* define a global symbol at end of code */
+ _sidata = _etext; /* This is used by the startup to initialize data */
+ } >FLASH
+
+ /* Initialized data section */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ _ram_start = .;
+ . = ALIGN(4);
+ *(.data)
+ *(.data*)
+ *(.sdata)
+ *(.sdata*)
+ . = ALIGN(4);
+ _edata = .;
+ } >RAM
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(.sbss)
+ *(.sbss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+
+ /* Define the start of the heap */
+ .heap :
+ {
+ . = ALIGN(4);
+ _heap_start = .;
+ } >RAM
+}
diff --git a/caravel/verilog/dv/caravel/spiflash.v b/caravel/verilog/dv/caravel/spiflash.v
new file mode 100644
index 0000000..6aa29ba
--- /dev/null
+++ b/caravel/verilog/dv/caravel/spiflash.v
@@ -0,0 +1,447 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+// AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+// Cypress S25FL064L http://www.cypress.com/file/316661/download
+// Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+ parameter FILENAME = "firmware.hex"
+)(
+ input csb,
+ input clk,
+ inout io0, // MOSI
+ inout io1, // MISO
+ inout io2,
+ inout io3
+);
+ localparam verbose = 0;
+ localparam integer latency = 8;
+
+ reg [7:0] buffer;
+ reg [3:0] reset_count = 0;
+ reg [3:0] reset_monitor = 0;
+ integer bitcount = 0;
+ integer bytecount = 0;
+ integer dummycount = 0;
+
+ reg [7:0] spi_cmd;
+ reg [7:0] xip_cmd = 0;
+ reg [23:0] spi_addr;
+
+ reg [7:0] spi_in;
+ reg [7:0] spi_out;
+ reg spi_io_vld;
+
+ reg powered_up = 0;
+
+ localparam [3:0] mode_spi = 1;
+ localparam [3:0] mode_dspi_rd = 2;
+ localparam [3:0] mode_dspi_wr = 3;
+ localparam [3:0] mode_qspi_rd = 4;
+ localparam [3:0] mode_qspi_wr = 5;
+ localparam [3:0] mode_qspi_ddr_rd = 6;
+ localparam [3:0] mode_qspi_ddr_wr = 7;
+
+ reg [3:0] mode = 0;
+ reg [3:0] next_mode = 0;
+
+ reg io0_oe = 0;
+ reg io1_oe = 0;
+ reg io2_oe = 0;
+ reg io3_oe = 0;
+
+ reg io0_dout = 0;
+ reg io1_dout = 0;
+ reg io2_dout = 0;
+ reg io3_dout = 0;
+
+ assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+ assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+ assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+ assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+ wire io0_delayed;
+ wire io1_delayed;
+ wire io2_delayed;
+ wire io3_delayed;
+
+ assign #1 io0_delayed = io0;
+ assign #1 io1_delayed = io1;
+ assign #1 io2_delayed = io2;
+ assign #1 io3_delayed = io3;
+
+ // 16 MB (128Mb) Flash
+ reg [7:0] memory [0:16*1024*1024-1];
+
+ initial begin
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ $display("Reading %s", FILENAME);
+ $readmemh(FILENAME, memory);
+ $display("%s loaded into memory", FILENAME);
+ $display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+ memory[1048576], memory[1048577], memory[1048578],
+ memory[1048579], memory[1048580]);
+ end
+
+ task spi_action;
+ begin
+ spi_in = buffer;
+
+ if (bytecount == 1) begin
+ spi_cmd = buffer;
+
+ if (spi_cmd == 8'h ab)
+ powered_up = 1;
+
+ if (spi_cmd == 8'h b9)
+ powered_up = 0;
+
+ if (spi_cmd == 8'h ff)
+ xip_cmd = 0;
+ end
+
+ if (powered_up && spi_cmd == 'h 03) begin
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount >= 4) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h bb) begin
+ if (bytecount == 1)
+ mode = mode_dspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_dspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h eb) begin
+ if (bytecount == 1)
+ mode = mode_qspi_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ if (powered_up && spi_cmd == 'h ed) begin
+ if (bytecount == 1)
+ next_mode = mode_qspi_ddr_rd;
+
+ if (bytecount == 2)
+ spi_addr[23:16] = buffer;
+
+ if (bytecount == 3)
+ spi_addr[15:8] = buffer;
+
+ if (bytecount == 4)
+ spi_addr[7:0] = buffer;
+
+ if (bytecount == 5) begin
+ xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+ mode = mode_qspi_ddr_wr;
+ dummycount = latency;
+ end
+
+ if (bytecount >= 5) begin
+ buffer = memory[spi_addr];
+ spi_addr = spi_addr + 1;
+ end
+ end
+
+ spi_out = buffer;
+ spi_io_vld = 1;
+
+ if (verbose) begin
+ if (bytecount == 1)
+ $write("<SPI-START>");
+ $write("<SPI:%02x:%02x>", spi_in, spi_out);
+ end
+
+ end
+ endtask
+
+ task ddr_rd_edge;
+ begin
+ buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ task ddr_wr_edge;
+ begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+
+ buffer = {buffer, 4'h 0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ endtask
+
+ always @(csb) begin
+ if (csb) begin
+ if (verbose) begin
+ $display("");
+ $fflush;
+ end
+ buffer = 0;
+ bitcount = 0;
+ bytecount = 0;
+ mode = mode_spi;
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+
+ // Handle MBR. If in XIP continuous mode, the following
+ // 8 clock cycles are normally not expected to be a command.
+ // If followed by CSB high, however, if the address bits
+ // are consistent with io0 == 1 for 8 clk cycles, then an
+ // MBR has been issued and the system must exit XIP
+ // continuous mode.
+ if (xip_cmd == 8'hbb || xip_cmd == 8'heb
+ || xip_cmd == 8'hed) begin
+ if (reset_count == 4'h8 && reset_monitor == 4'h8) begin
+ xip_cmd = 8'h00;
+ spi_cmd = 8'h03;
+ end
+ end
+ end else
+ if (xip_cmd) begin
+ buffer = xip_cmd;
+ bitcount = 0;
+ bytecount = 1;
+ spi_action;
+ end
+ end
+
+ always @(posedge clk or posedge csb) begin
+ if (csb == 1'b1) begin
+ reset_count = 0;
+ reset_monitor = 0;
+ end else begin
+ if (reset_count < 4'h9) begin
+ reset_count = reset_count + 1;
+ if (io0_delayed == 1'b1) begin
+ reset_monitor = reset_monitor + 1;
+ end
+ end
+ end
+ end
+
+ always @(csb, clk) begin
+ spi_io_vld = 0;
+ if (!csb && !clk) begin
+ if (dummycount > 0) begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end else
+ case (mode)
+ mode_spi: begin
+ io0_oe = 0;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io1_dout = buffer[7];
+ end
+ mode_dspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_dspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 0;
+ io3_oe = 0;
+ io0_dout = buffer[6];
+ io1_dout = buffer[7];
+ end
+ mode_qspi_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ if (next_mode) begin
+ case (next_mode)
+ mode_qspi_ddr_rd: begin
+ io0_oe = 0;
+ io1_oe = 0;
+ io2_oe = 0;
+ io3_oe = 0;
+ end
+ mode_qspi_ddr_wr: begin
+ io0_oe = 1;
+ io1_oe = 1;
+ io2_oe = 1;
+ io3_oe = 1;
+ io0_dout = buffer[4];
+ io1_dout = buffer[5];
+ io2_dout = buffer[6];
+ io3_dout = buffer[7];
+ end
+ endcase
+ mode = next_mode;
+ next_mode = 0;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ if (!csb) begin
+ if (dummycount > 0) begin
+ dummycount = dummycount - 1;
+ end else
+ case (mode)
+ mode_spi: begin
+ buffer = {buffer, io0};
+ bitcount = bitcount + 1;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_dspi_rd, mode_dspi_wr: begin
+ buffer = {buffer, io1, io0};
+ bitcount = bitcount + 2;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_rd, mode_qspi_wr: begin
+ buffer = {buffer, io3, io2, io1, io0};
+ bitcount = bitcount + 4;
+ if (bitcount == 8) begin
+ bitcount = 0;
+ bytecount = bytecount + 1;
+ spi_action;
+ end
+ end
+ mode_qspi_ddr_rd: begin
+ ddr_rd_edge;
+ end
+ mode_qspi_ddr_wr: begin
+ ddr_wr_edge;
+ end
+ endcase
+ end
+ end
+endmodule
diff --git a/caravel/verilog/dv/caravel/start.s b/caravel/verilog/dv/caravel/start.s
new file mode 100644
index 0000000..287cba2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/start.s
@@ -0,0 +1,174 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li t0, 0x28000000
+
+# Set CS high, IO0 is output
+li t1, 0x120
+sh t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li t5, 32
+# Load t2 from address a0 (4 bytes)
+lw t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb t4, 0(t0)
+ori t4, t4, 0x10
+sb t4, 0(t0)
+lbu t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw t2, 0(a0)
+addi a0, a0, 4
+lw t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li t1, 0x80
+sb t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+
diff --git a/caravel/verilog/dv/caravel/stub.c b/caravel/verilog/dv/caravel/stub.c
new file mode 100644
index 0000000..575cfc3
--- /dev/null
+++ b/caravel/verilog/dv/caravel/stub.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+void putchar(char c)
+{
+ if (c == '\n')
+ putchar('\r');
+ reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+ while (*p)
+ putchar(*(p++));
+}
\ No newline at end of file
diff --git a/caravel/verilog/dv/caravel/tbuart.v b/caravel/verilog/dv/caravel/tbuart.v
new file mode 100644
index 0000000..bac9480
--- /dev/null
+++ b/caravel/verilog/dv/caravel/tbuart.v
@@ -0,0 +1,93 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ * PicoSoC - A simple example SoC using PicoRV32
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud */
+/* and accepting ASCII characters for display. */
+
+/* To do: Match a known UART 3.3V 16x2 LCD display. However, it */
+/* should be possible on a testing system to interface to the UART */
+/* pins on a Raspberry Pi, also running at 3.3V. */
+
+module tbuart (
+ input ser_rx
+);
+ reg [3:0] recv_state;
+ reg [2:0] recv_divcnt;
+ reg [7:0] recv_pattern;
+ reg [8*50-1:0] recv_buf_data; // 50 characters. Increase as needed for tests.
+
+ reg clk;
+
+ initial begin
+ clk <= 1'b0;
+ recv_state <= 0;
+ recv_divcnt <= 0;
+ recv_pattern <= 0;
+ recv_buf_data <= 0;
+ end
+
+ // NOTE: Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+ // bit ~= 64 kbaud. Not tuned to any particular UART. Most run at
+ // 9600 baud default and will bounce up to higher baud rates when
+ // passed specific command words.
+
+ always #1500 clk <= (clk === 1'b0);
+
+ always @(posedge clk) begin
+ recv_divcnt <= recv_divcnt + 1;
+ case (recv_state)
+ 0: begin
+ if (!ser_rx)
+ recv_state <= 1;
+ recv_divcnt <= 0;
+ end
+ 1: begin
+ if (2*recv_divcnt > 3'd3) begin
+ recv_state <= 2;
+ recv_divcnt <= 0;
+ end
+ end
+ 10: begin
+ if (recv_divcnt > 3'd3) begin
+ // 0x0a = '\n'
+ if (recv_pattern == 8'h0a) begin
+ $display("output: %s", recv_buf_data);
+ end else begin
+ recv_buf_data <= {recv_buf_data, recv_pattern};
+ end
+ recv_state <= 0;
+ end
+ end
+ default: begin
+ if (recv_divcnt > 3'd3) begin
+ recv_pattern <= {ser_rx, recv_pattern[7:1]};
+ recv_state <= recv_state + 1;
+ recv_divcnt <= 0;
+ end
+ end
+ endcase
+ end
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/Makefile b/caravel/verilog/dv/wb_utests/Makefile
new file mode 100644
index 0000000..1c95476
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mgmt_protect chip_io mprj_ctrl sysctrl_wb
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/chip_io/Makefile b/caravel/verilog/dv/wb_utests/chip_io/Makefile
new file mode 100644
index 0000000..4bd731a
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/Makefile
@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = chip_io
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+ifeq ($(SIM),SPLIT_BUS)
+ iverilog -Ttyp -DFUNCTIONAL -DSPLIT_BUS -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+ifeq ($(SIM),GL)
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v b/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v
new file mode 100644
index 0000000..62a1cb2
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v
@@ -0,0 +1,4218 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module chip_io(vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, \mprj_io[0] , \mprj_io[1] , \mprj_io[2] , \mprj_io[3] , \mprj_io[4] , \mprj_io[5] , \mprj_io[6] , \mprj_io[7] , \mprj_io[8] , \mprj_io[9] , \mprj_io[10] , \mprj_io[11] , \mprj_io[12] , \mprj_io[13] , \mprj_io[14] , \mprj_io[15] , \mprj_io[16] , \mprj_io[17] , \mprj_io[18] , \mprj_io[19] , \mprj_io[20] , \mprj_io[21] , \mprj_io[22] , \mprj_io[23] , \mprj_io[24] , \mprj_io[25] , \mprj_io[26] , \mprj_io[27] , \mprj_io[28] , \mprj_io[29] , \mprj_io[30] , \mprj_io[31] , \mprj_io[32] , \mprj_io[33] , \mprj_io[34] , \mprj_io[35] , \mprj_io[36] , \mprj_io[37] , \mprj_io_out[0] , \mprj_io_out[1] , \mprj_io_out[2] , \mprj_io_out[3] , \mprj_io_out[4] , \mprj_io_out[5] , \mprj_io_out[6] , \mprj_io_out[7] , \mprj_io_out[8] , \mprj_io_out[9] , \mprj_io_out[10] , \mprj_io_out[11] , \mprj_io_out[12] , \mprj_io_out[13] , \mprj_io_out[14] , \mprj_io_out[15] , \mprj_io_out[16] , \mprj_io_out[17] , \mprj_io_out[18] , \mprj_io_out[19] , \mprj_io_out[20] , \mprj_io_out[21] , \mprj_io_out[22] , \mprj_io_out[23] , \mprj_io_out[24] , \mprj_io_out[25] , \mprj_io_out[26] , \mprj_io_out[27] , \mprj_io_out[28] , \mprj_io_out[29] , \mprj_io_out[30] , \mprj_io_out[31] , \mprj_io_out[32] , \mprj_io_out[33] , \mprj_io_out[34] , \mprj_io_out[35] , \mprj_io_out[36] , \mprj_io_out[37] , \mprj_io_oeb[0] , \mprj_io_oeb[1] , \mprj_io_oeb[2] , \mprj_io_oeb[3] , \mprj_io_oeb[4] , \mprj_io_oeb[5] , \mprj_io_oeb[6] , \mprj_io_oeb[7] , \mprj_io_oeb[8] , \mprj_io_oeb[9] , \mprj_io_oeb[10] , \mprj_io_oeb[11] , \mprj_io_oeb[12] , \mprj_io_oeb[13] , \mprj_io_oeb[14] , \mprj_io_oeb[15] , \mprj_io_oeb[16] , \mprj_io_oeb[17] , \mprj_io_oeb[18] , \mprj_io_oeb[19] , \mprj_io_oeb[20] , \mprj_io_oeb[21] , \mprj_io_oeb[22] , \mprj_io_oeb[23] , \mprj_io_oeb[24] , \mprj_io_oeb[25] , \mprj_io_oeb[26] , \mprj_io_oeb[27] , \mprj_io_oeb[28] , \mprj_io_oeb[29] , \mprj_io_oeb[30] , \mprj_io_oeb[31] , \mprj_io_oeb[32] , \mprj_io_oeb[33] , \mprj_io_oeb[34] , \mprj_io_oeb[35] , \mprj_io_oeb[36] , \mprj_io_oeb[37] , \mprj_io_hldh_n[0] , \mprj_io_hldh_n[1] , \mprj_io_hldh_n[2] , \mprj_io_hldh_n[3] , \mprj_io_hldh_n[4] , \mprj_io_hldh_n[5] , \mprj_io_hldh_n[6] , \mprj_io_hldh_n[7] , \mprj_io_hldh_n[8] , \mprj_io_hldh_n[9] , \mprj_io_hldh_n[10] , \mprj_io_hldh_n[11] , \mprj_io_hldh_n[12] , \mprj_io_hldh_n[13] , \mprj_io_hldh_n[14] , \mprj_io_hldh_n[15] , \mprj_io_hldh_n[16] , \mprj_io_hldh_n[17] , \mprj_io_hldh_n[18] , \mprj_io_hldh_n[19] , \mprj_io_hldh_n[20] , \mprj_io_hldh_n[21] , \mprj_io_hldh_n[22] , \mprj_io_hldh_n[23] , \mprj_io_hldh_n[24] , \mprj_io_hldh_n[25] , \mprj_io_hldh_n[26] , \mprj_io_hldh_n[27] , \mprj_io_hldh_n[28] , \mprj_io_hldh_n[29] , \mprj_io_hldh_n[30] , \mprj_io_hldh_n[31] , \mprj_io_hldh_n[32] , \mprj_io_hldh_n[33] , \mprj_io_hldh_n[34] , \mprj_io_hldh_n[35] , \mprj_io_hldh_n[36] , \mprj_io_hldh_n[37] , \mprj_io_enh[0] , \mprj_io_enh[1] , \mprj_io_enh[2] , \mprj_io_enh[3] , \mprj_io_enh[4] , \mprj_io_enh[5] , \mprj_io_enh[6] , \mprj_io_enh[7] , \mprj_io_enh[8] , \mprj_io_enh[9] , \mprj_io_enh[10] , \mprj_io_enh[11] , \mprj_io_enh[12] , \mprj_io_enh[13] , \mprj_io_enh[14] , \mprj_io_enh[15] , \mprj_io_enh[16] , \mprj_io_enh[17] , \mprj_io_enh[18] , \mprj_io_enh[19] , \mprj_io_enh[20] , \mprj_io_enh[21] , \mprj_io_enh[22] , \mprj_io_enh[23] , \mprj_io_enh[24] , \mprj_io_enh[25] , \mprj_io_enh[26] , \mprj_io_enh[27] , \mprj_io_enh[28] , \mprj_io_enh[29] , \mprj_io_enh[30] , \mprj_io_enh[31] , \mprj_io_enh[32] , \mprj_io_enh[33] , \mprj_io_enh[34] , \mprj_io_enh[35] , \mprj_io_enh[36] , \mprj_io_enh[37] , \mprj_io_inp_dis[0] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[37] , \mprj_io_ib_mode_sel[0] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[37] , \mprj_io_vtrip_sel[0] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[37] , \mprj_io_slow_sel[0] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[37] , \mprj_io_holdover[0] , \mprj_io_holdover[1] , \mprj_io_holdover[2] , \mprj_io_holdover[3] , \mprj_io_holdover[4] , \mprj_io_holdover[5] , \mprj_io_holdover[6] , \mprj_io_holdover[7] , \mprj_io_holdover[8] , \mprj_io_holdover[9] , \mprj_io_holdover[10] , \mprj_io_holdover[11] , \mprj_io_holdover[12] , \mprj_io_holdover[13] , \mprj_io_holdover[14] , \mprj_io_holdover[15] , \mprj_io_holdover[16] , \mprj_io_holdover[17] , \mprj_io_holdover[18] , \mprj_io_holdover[19] , \mprj_io_holdover[20] , \mprj_io_holdover[21] , \mprj_io_holdover[22] , \mprj_io_holdover[23] , \mprj_io_holdover[24] , \mprj_io_holdover[25] , \mprj_io_holdover[26] , \mprj_io_holdover[27] , \mprj_io_holdover[28] , \mprj_io_holdover[29] , \mprj_io_holdover[30] , \mprj_io_holdover[31] , \mprj_io_holdover[32] , \mprj_io_holdover[33] , \mprj_io_holdover[34] , \mprj_io_holdover[35] , \mprj_io_holdover[36] , \mprj_io_holdover[37] , \mprj_io_analog_en[0] , \mprj_io_analog_en[1] , \mprj_io_analog_en[2] , \mprj_io_analog_en[3] , \mprj_io_analog_en[4] , \mprj_io_analog_en[5] , \mprj_io_analog_en[6] , \mprj_io_analog_en[7] , \mprj_io_analog_en[8] , \mprj_io_analog_en[9] , \mprj_io_analog_en[10] , \mprj_io_analog_en[11] , \mprj_io_analog_en[12] , \mprj_io_analog_en[13] , \mprj_io_analog_en[14] , \mprj_io_analog_en[15] , \mprj_io_analog_en[16] , \mprj_io_analog_en[17] , \mprj_io_analog_en[18] , \mprj_io_analog_en[19] , \mprj_io_analog_en[20] , \mprj_io_analog_en[21] , \mprj_io_analog_en[22] , \mprj_io_analog_en[23] , \mprj_io_analog_en[24] , \mprj_io_analog_en[25] , \mprj_io_analog_en[26] , \mprj_io_analog_en[27] , \mprj_io_analog_en[28] , \mprj_io_analog_en[29] , \mprj_io_analog_en[30] , \mprj_io_analog_en[31] , \mprj_io_analog_en[32] , \mprj_io_analog_en[33] , \mprj_io_analog_en[34] , \mprj_io_analog_en[35] , \mprj_io_analog_en[36] , \mprj_io_analog_en[37] , \mprj_io_analog_sel[0] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[37] , \mprj_io_analog_pol[0] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[37] , \mprj_io_dm[0] , \mprj_io_dm[1] , \mprj_io_dm[2] , \mprj_io_dm[3] , \mprj_io_dm[4] , \mprj_io_dm[5] , \mprj_io_dm[6] , \mprj_io_dm[7] , \mprj_io_dm[8] , \mprj_io_dm[9] , \mprj_io_dm[10] , \mprj_io_dm[11] , \mprj_io_dm[12] , \mprj_io_dm[13] , \mprj_io_dm[14] , \mprj_io_dm[15] , \mprj_io_dm[16] , \mprj_io_dm[17] , \mprj_io_dm[18] , \mprj_io_dm[19] , \mprj_io_dm[20] , \mprj_io_dm[21] , \mprj_io_dm[22] , \mprj_io_dm[23] , \mprj_io_dm[24] , \mprj_io_dm[25] , \mprj_io_dm[26] , \mprj_io_dm[27] , \mprj_io_dm[28] , \mprj_io_dm[29] , \mprj_io_dm[30] , \mprj_io_dm[31] , \mprj_io_dm[32] , \mprj_io_dm[33] , \mprj_io_dm[34] , \mprj_io_dm[35] , \mprj_io_dm[36] , \mprj_io_dm[37] , \mprj_io_dm[38] , \mprj_io_dm[39] , \mprj_io_dm[40] , \mprj_io_dm[41] , \mprj_io_dm[42] , \mprj_io_dm[43] , \mprj_io_dm[44] , \mprj_io_dm[45] , \mprj_io_dm[46] , \mprj_io_dm[47] , \mprj_io_dm[48] , \mprj_io_dm[49] , \mprj_io_dm[50] , \mprj_io_dm[51] , \mprj_io_dm[52] , \mprj_io_dm[53] , \mprj_io_dm[54] , \mprj_io_dm[55] , \mprj_io_dm[56] , \mprj_io_dm[57] , \mprj_io_dm[58] , \mprj_io_dm[59] , \mprj_io_dm[60] , \mprj_io_dm[61] , \mprj_io_dm[62] , \mprj_io_dm[63] , \mprj_io_dm[64] , \mprj_io_dm[65] , \mprj_io_dm[66] , \mprj_io_dm[67] , \mprj_io_dm[68] , \mprj_io_dm[69] , \mprj_io_dm[70] , \mprj_io_dm[71] , \mprj_io_dm[72] , \mprj_io_dm[73] , \mprj_io_dm[74] , \mprj_io_dm[75] , \mprj_io_dm[76] , \mprj_io_dm[77] , \mprj_io_dm[78] , \mprj_io_dm[79] , \mprj_io_dm[80] , \mprj_io_dm[81] , \mprj_io_dm[82] , \mprj_io_dm[83] , \mprj_io_dm[84] , \mprj_io_dm[85] , \mprj_io_dm[86] , \mprj_io_dm[87] , \mprj_io_dm[88] , \mprj_io_dm[89] , \mprj_io_dm[90] , \mprj_io_dm[91] , \mprj_io_dm[92] , \mprj_io_dm[93] , \mprj_io_dm[94] , \mprj_io_dm[95] , \mprj_io_dm[96] , \mprj_io_dm[97] , \mprj_io_dm[98] , \mprj_io_dm[99] , \mprj_io_dm[100] , \mprj_io_dm[101] , \mprj_io_dm[102] , \mprj_io_dm[103] , \mprj_io_dm[104] , \mprj_io_dm[105] , \mprj_io_dm[106] , \mprj_io_dm[107] , \mprj_io_dm[108] , \mprj_io_dm[109] , \mprj_io_dm[110] , \mprj_io_dm[111] , \mprj_io_dm[112] , \mprj_io_dm[113] , \mprj_io_in[0] , \mprj_io_in[1] , \mprj_io_in[2] , \mprj_io_in[3] , \mprj_io_in[4] , \mprj_io_in[5] , \mprj_io_in[6] , \mprj_io_in[7] , \mprj_io_in[8] , \mprj_io_in[9] , \mprj_io_in[10] , \mprj_io_in[11] , \mprj_io_in[12] , \mprj_io_in[13] , \mprj_io_in[14] , \mprj_io_in[15] , \mprj_io_in[16] , \mprj_io_in[17] , \mprj_io_in[18] , \mprj_io_in[19] , \mprj_io_in[20] , \mprj_io_in[21] , \mprj_io_in[22] , \mprj_io_in[23] , \mprj_io_in[24] , \mprj_io_in[25] , \mprj_io_in[26] , \mprj_io_in[27] , \mprj_io_in[28] , \mprj_io_in[29] , \mprj_io_in[30] , \mprj_io_in[31] , \mprj_io_in[32] , \mprj_io_in[33] , \mprj_io_in[34] , \mprj_io_in[35] , \mprj_io_in[36] , \mprj_io_in[37] , \mprj_analog_io[0] , \mprj_analog_io[1] , \mprj_analog_io[2] , \mprj_analog_io[3] , \mprj_analog_io[4] , \mprj_analog_io[5] , \mprj_analog_io[6] , \mprj_analog_io[7] , \mprj_analog_io[8] , \mprj_analog_io[9] , \mprj_analog_io[10] , \mprj_analog_io[11] , \mprj_analog_io[12] , \mprj_analog_io[13] , \mprj_analog_io[14] , \mprj_analog_io[15] , \mprj_analog_io[16] , \mprj_analog_io[17] , \mprj_analog_io[18] , \mprj_analog_io[19] , \mprj_analog_io[20] , \mprj_analog_io[21] , \mprj_analog_io[22] , \mprj_analog_io[23] , \mprj_analog_io[24] , \mprj_analog_io[25] , \mprj_analog_io[26] , \mprj_analog_io[27] , \mprj_analog_io[28] , \mprj_analog_io[29] , \mprj_analog_io[30] );
+ wire analog_a;
+ wire analog_b;
+ input clock;
+ output clock_core;
+ wire \dm_all[0] ;
+ wire \dm_all[1] ;
+ wire \dm_all[2] ;
+ output flash_clk;
+ input flash_clk_core;
+ input flash_clk_ieb_core;
+ input flash_clk_oeb_core;
+ output flash_csb;
+ input flash_csb_core;
+ input flash_csb_ieb_core;
+ input flash_csb_oeb_core;
+ inout flash_io0;
+ output flash_io0_di_core;
+ input flash_io0_do_core;
+ input flash_io0_ieb_core;
+ wire \flash_io0_mode[0] ;
+ wire \flash_io0_mode[1] ;
+ wire \flash_io0_mode[2] ;
+ input flash_io0_oeb_core;
+ inout flash_io1;
+ output flash_io1_di_core;
+ input flash_io1_do_core;
+ input flash_io1_ieb_core;
+ wire \flash_io1_mode[0] ;
+ wire \flash_io1_mode[1] ;
+ wire \flash_io1_mode[2] ;
+ input flash_io1_oeb_core;
+ inout gpio;
+ output gpio_in_core;
+ input gpio_inenb_core;
+ input gpio_mode0_core;
+ input gpio_mode1_core;
+ input gpio_out_core;
+ input gpio_outenb_core;
+ wire loop_clock;
+ wire loop_flash_clk;
+ wire loop_flash_csb;
+ wire loop_flash_io0;
+ wire loop_flash_io1;
+ wire loop_gpio;
+ inout \mprj_analog_io[0] ;
+ inout \mprj_analog_io[10] ;
+ inout \mprj_analog_io[11] ;
+ inout \mprj_analog_io[12] ;
+ inout \mprj_analog_io[13] ;
+ inout \mprj_analog_io[14] ;
+ inout \mprj_analog_io[15] ;
+ inout \mprj_analog_io[16] ;
+ inout \mprj_analog_io[17] ;
+ inout \mprj_analog_io[18] ;
+ inout \mprj_analog_io[19] ;
+ inout \mprj_analog_io[1] ;
+ inout \mprj_analog_io[20] ;
+ inout \mprj_analog_io[21] ;
+ inout \mprj_analog_io[22] ;
+ inout \mprj_analog_io[23] ;
+ inout \mprj_analog_io[24] ;
+ inout \mprj_analog_io[25] ;
+ inout \mprj_analog_io[26] ;
+ inout \mprj_analog_io[27] ;
+ inout \mprj_analog_io[28] ;
+ inout \mprj_analog_io[29] ;
+ inout \mprj_analog_io[2] ;
+ inout \mprj_analog_io[30] ;
+ inout \mprj_analog_io[3] ;
+ inout \mprj_analog_io[4] ;
+ inout \mprj_analog_io[5] ;
+ inout \mprj_analog_io[6] ;
+ inout \mprj_analog_io[7] ;
+ inout \mprj_analog_io[8] ;
+ inout \mprj_analog_io[9] ;
+ inout \mprj_io[0] ;
+ inout \mprj_io[10] ;
+ inout \mprj_io[11] ;
+ inout \mprj_io[12] ;
+ inout \mprj_io[13] ;
+ inout \mprj_io[14] ;
+ inout \mprj_io[15] ;
+ inout \mprj_io[16] ;
+ inout \mprj_io[17] ;
+ inout \mprj_io[18] ;
+ inout \mprj_io[19] ;
+ inout \mprj_io[1] ;
+ inout \mprj_io[20] ;
+ inout \mprj_io[21] ;
+ inout \mprj_io[22] ;
+ inout \mprj_io[23] ;
+ inout \mprj_io[24] ;
+ inout \mprj_io[25] ;
+ inout \mprj_io[26] ;
+ inout \mprj_io[27] ;
+ inout \mprj_io[28] ;
+ inout \mprj_io[29] ;
+ inout \mprj_io[2] ;
+ inout \mprj_io[30] ;
+ inout \mprj_io[31] ;
+ inout \mprj_io[32] ;
+ inout \mprj_io[33] ;
+ inout \mprj_io[34] ;
+ inout \mprj_io[35] ;
+ inout \mprj_io[36] ;
+ inout \mprj_io[37] ;
+ inout \mprj_io[3] ;
+ inout \mprj_io[4] ;
+ inout \mprj_io[5] ;
+ inout \mprj_io[6] ;
+ inout \mprj_io[7] ;
+ inout \mprj_io[8] ;
+ inout \mprj_io[9] ;
+ input \mprj_io_analog_en[0] ;
+ input \mprj_io_analog_en[10] ;
+ input \mprj_io_analog_en[11] ;
+ input \mprj_io_analog_en[12] ;
+ input \mprj_io_analog_en[13] ;
+ input \mprj_io_analog_en[14] ;
+ input \mprj_io_analog_en[15] ;
+ input \mprj_io_analog_en[16] ;
+ input \mprj_io_analog_en[17] ;
+ input \mprj_io_analog_en[18] ;
+ input \mprj_io_analog_en[19] ;
+ input \mprj_io_analog_en[1] ;
+ input \mprj_io_analog_en[20] ;
+ input \mprj_io_analog_en[21] ;
+ input \mprj_io_analog_en[22] ;
+ input \mprj_io_analog_en[23] ;
+ input \mprj_io_analog_en[24] ;
+ input \mprj_io_analog_en[25] ;
+ input \mprj_io_analog_en[26] ;
+ input \mprj_io_analog_en[27] ;
+ input \mprj_io_analog_en[28] ;
+ input \mprj_io_analog_en[29] ;
+ input \mprj_io_analog_en[2] ;
+ input \mprj_io_analog_en[30] ;
+ input \mprj_io_analog_en[31] ;
+ input \mprj_io_analog_en[32] ;
+ input \mprj_io_analog_en[33] ;
+ input \mprj_io_analog_en[34] ;
+ input \mprj_io_analog_en[35] ;
+ input \mprj_io_analog_en[36] ;
+ input \mprj_io_analog_en[37] ;
+ input \mprj_io_analog_en[3] ;
+ input \mprj_io_analog_en[4] ;
+ input \mprj_io_analog_en[5] ;
+ input \mprj_io_analog_en[6] ;
+ input \mprj_io_analog_en[7] ;
+ input \mprj_io_analog_en[8] ;
+ input \mprj_io_analog_en[9] ;
+ input \mprj_io_analog_pol[0] ;
+ input \mprj_io_analog_pol[10] ;
+ input \mprj_io_analog_pol[11] ;
+ input \mprj_io_analog_pol[12] ;
+ input \mprj_io_analog_pol[13] ;
+ input \mprj_io_analog_pol[14] ;
+ input \mprj_io_analog_pol[15] ;
+ input \mprj_io_analog_pol[16] ;
+ input \mprj_io_analog_pol[17] ;
+ input \mprj_io_analog_pol[18] ;
+ input \mprj_io_analog_pol[19] ;
+ input \mprj_io_analog_pol[1] ;
+ input \mprj_io_analog_pol[20] ;
+ input \mprj_io_analog_pol[21] ;
+ input \mprj_io_analog_pol[22] ;
+ input \mprj_io_analog_pol[23] ;
+ input \mprj_io_analog_pol[24] ;
+ input \mprj_io_analog_pol[25] ;
+ input \mprj_io_analog_pol[26] ;
+ input \mprj_io_analog_pol[27] ;
+ input \mprj_io_analog_pol[28] ;
+ input \mprj_io_analog_pol[29] ;
+ input \mprj_io_analog_pol[2] ;
+ input \mprj_io_analog_pol[30] ;
+ input \mprj_io_analog_pol[31] ;
+ input \mprj_io_analog_pol[32] ;
+ input \mprj_io_analog_pol[33] ;
+ input \mprj_io_analog_pol[34] ;
+ input \mprj_io_analog_pol[35] ;
+ input \mprj_io_analog_pol[36] ;
+ input \mprj_io_analog_pol[37] ;
+ input \mprj_io_analog_pol[3] ;
+ input \mprj_io_analog_pol[4] ;
+ input \mprj_io_analog_pol[5] ;
+ input \mprj_io_analog_pol[6] ;
+ input \mprj_io_analog_pol[7] ;
+ input \mprj_io_analog_pol[8] ;
+ input \mprj_io_analog_pol[9] ;
+ input \mprj_io_analog_sel[0] ;
+ input \mprj_io_analog_sel[10] ;
+ input \mprj_io_analog_sel[11] ;
+ input \mprj_io_analog_sel[12] ;
+ input \mprj_io_analog_sel[13] ;
+ input \mprj_io_analog_sel[14] ;
+ input \mprj_io_analog_sel[15] ;
+ input \mprj_io_analog_sel[16] ;
+ input \mprj_io_analog_sel[17] ;
+ input \mprj_io_analog_sel[18] ;
+ input \mprj_io_analog_sel[19] ;
+ input \mprj_io_analog_sel[1] ;
+ input \mprj_io_analog_sel[20] ;
+ input \mprj_io_analog_sel[21] ;
+ input \mprj_io_analog_sel[22] ;
+ input \mprj_io_analog_sel[23] ;
+ input \mprj_io_analog_sel[24] ;
+ input \mprj_io_analog_sel[25] ;
+ input \mprj_io_analog_sel[26] ;
+ input \mprj_io_analog_sel[27] ;
+ input \mprj_io_analog_sel[28] ;
+ input \mprj_io_analog_sel[29] ;
+ input \mprj_io_analog_sel[2] ;
+ input \mprj_io_analog_sel[30] ;
+ input \mprj_io_analog_sel[31] ;
+ input \mprj_io_analog_sel[32] ;
+ input \mprj_io_analog_sel[33] ;
+ input \mprj_io_analog_sel[34] ;
+ input \mprj_io_analog_sel[35] ;
+ input \mprj_io_analog_sel[36] ;
+ input \mprj_io_analog_sel[37] ;
+ input \mprj_io_analog_sel[3] ;
+ input \mprj_io_analog_sel[4] ;
+ input \mprj_io_analog_sel[5] ;
+ input \mprj_io_analog_sel[6] ;
+ input \mprj_io_analog_sel[7] ;
+ input \mprj_io_analog_sel[8] ;
+ input \mprj_io_analog_sel[9] ;
+ input \mprj_io_dm[0] ;
+ input \mprj_io_dm[100] ;
+ input \mprj_io_dm[101] ;
+ input \mprj_io_dm[102] ;
+ input \mprj_io_dm[103] ;
+ input \mprj_io_dm[104] ;
+ input \mprj_io_dm[105] ;
+ input \mprj_io_dm[106] ;
+ input \mprj_io_dm[107] ;
+ input \mprj_io_dm[108] ;
+ input \mprj_io_dm[109] ;
+ input \mprj_io_dm[10] ;
+ input \mprj_io_dm[110] ;
+ input \mprj_io_dm[111] ;
+ input \mprj_io_dm[112] ;
+ input \mprj_io_dm[113] ;
+ input \mprj_io_dm[11] ;
+ input \mprj_io_dm[12] ;
+ input \mprj_io_dm[13] ;
+ input \mprj_io_dm[14] ;
+ input \mprj_io_dm[15] ;
+ input \mprj_io_dm[16] ;
+ input \mprj_io_dm[17] ;
+ input \mprj_io_dm[18] ;
+ input \mprj_io_dm[19] ;
+ input \mprj_io_dm[1] ;
+ input \mprj_io_dm[20] ;
+ input \mprj_io_dm[21] ;
+ input \mprj_io_dm[22] ;
+ input \mprj_io_dm[23] ;
+ input \mprj_io_dm[24] ;
+ input \mprj_io_dm[25] ;
+ input \mprj_io_dm[26] ;
+ input \mprj_io_dm[27] ;
+ input \mprj_io_dm[28] ;
+ input \mprj_io_dm[29] ;
+ input \mprj_io_dm[2] ;
+ input \mprj_io_dm[30] ;
+ input \mprj_io_dm[31] ;
+ input \mprj_io_dm[32] ;
+ input \mprj_io_dm[33] ;
+ input \mprj_io_dm[34] ;
+ input \mprj_io_dm[35] ;
+ input \mprj_io_dm[36] ;
+ input \mprj_io_dm[37] ;
+ input \mprj_io_dm[38] ;
+ input \mprj_io_dm[39] ;
+ input \mprj_io_dm[3] ;
+ input \mprj_io_dm[40] ;
+ input \mprj_io_dm[41] ;
+ input \mprj_io_dm[42] ;
+ input \mprj_io_dm[43] ;
+ input \mprj_io_dm[44] ;
+ input \mprj_io_dm[45] ;
+ input \mprj_io_dm[46] ;
+ input \mprj_io_dm[47] ;
+ input \mprj_io_dm[48] ;
+ input \mprj_io_dm[49] ;
+ input \mprj_io_dm[4] ;
+ input \mprj_io_dm[50] ;
+ input \mprj_io_dm[51] ;
+ input \mprj_io_dm[52] ;
+ input \mprj_io_dm[53] ;
+ input \mprj_io_dm[54] ;
+ input \mprj_io_dm[55] ;
+ input \mprj_io_dm[56] ;
+ input \mprj_io_dm[57] ;
+ input \mprj_io_dm[58] ;
+ input \mprj_io_dm[59] ;
+ input \mprj_io_dm[5] ;
+ input \mprj_io_dm[60] ;
+ input \mprj_io_dm[61] ;
+ input \mprj_io_dm[62] ;
+ input \mprj_io_dm[63] ;
+ input \mprj_io_dm[64] ;
+ input \mprj_io_dm[65] ;
+ input \mprj_io_dm[66] ;
+ input \mprj_io_dm[67] ;
+ input \mprj_io_dm[68] ;
+ input \mprj_io_dm[69] ;
+ input \mprj_io_dm[6] ;
+ input \mprj_io_dm[70] ;
+ input \mprj_io_dm[71] ;
+ input \mprj_io_dm[72] ;
+ input \mprj_io_dm[73] ;
+ input \mprj_io_dm[74] ;
+ input \mprj_io_dm[75] ;
+ input \mprj_io_dm[76] ;
+ input \mprj_io_dm[77] ;
+ input \mprj_io_dm[78] ;
+ input \mprj_io_dm[79] ;
+ input \mprj_io_dm[7] ;
+ input \mprj_io_dm[80] ;
+ input \mprj_io_dm[81] ;
+ input \mprj_io_dm[82] ;
+ input \mprj_io_dm[83] ;
+ input \mprj_io_dm[84] ;
+ input \mprj_io_dm[85] ;
+ input \mprj_io_dm[86] ;
+ input \mprj_io_dm[87] ;
+ input \mprj_io_dm[88] ;
+ input \mprj_io_dm[89] ;
+ input \mprj_io_dm[8] ;
+ input \mprj_io_dm[90] ;
+ input \mprj_io_dm[91] ;
+ input \mprj_io_dm[92] ;
+ input \mprj_io_dm[93] ;
+ input \mprj_io_dm[94] ;
+ input \mprj_io_dm[95] ;
+ input \mprj_io_dm[96] ;
+ input \mprj_io_dm[97] ;
+ input \mprj_io_dm[98] ;
+ input \mprj_io_dm[99] ;
+ input \mprj_io_dm[9] ;
+ input \mprj_io_enh[0] ;
+ input \mprj_io_enh[10] ;
+ input \mprj_io_enh[11] ;
+ input \mprj_io_enh[12] ;
+ input \mprj_io_enh[13] ;
+ input \mprj_io_enh[14] ;
+ input \mprj_io_enh[15] ;
+ input \mprj_io_enh[16] ;
+ input \mprj_io_enh[17] ;
+ input \mprj_io_enh[18] ;
+ input \mprj_io_enh[19] ;
+ input \mprj_io_enh[1] ;
+ input \mprj_io_enh[20] ;
+ input \mprj_io_enh[21] ;
+ input \mprj_io_enh[22] ;
+ input \mprj_io_enh[23] ;
+ input \mprj_io_enh[24] ;
+ input \mprj_io_enh[25] ;
+ input \mprj_io_enh[26] ;
+ input \mprj_io_enh[27] ;
+ input \mprj_io_enh[28] ;
+ input \mprj_io_enh[29] ;
+ input \mprj_io_enh[2] ;
+ input \mprj_io_enh[30] ;
+ input \mprj_io_enh[31] ;
+ input \mprj_io_enh[32] ;
+ input \mprj_io_enh[33] ;
+ input \mprj_io_enh[34] ;
+ input \mprj_io_enh[35] ;
+ input \mprj_io_enh[36] ;
+ input \mprj_io_enh[37] ;
+ input \mprj_io_enh[3] ;
+ input \mprj_io_enh[4] ;
+ input \mprj_io_enh[5] ;
+ input \mprj_io_enh[6] ;
+ input \mprj_io_enh[7] ;
+ input \mprj_io_enh[8] ;
+ input \mprj_io_enh[9] ;
+ input \mprj_io_hldh_n[0] ;
+ input \mprj_io_hldh_n[10] ;
+ input \mprj_io_hldh_n[11] ;
+ input \mprj_io_hldh_n[12] ;
+ input \mprj_io_hldh_n[13] ;
+ input \mprj_io_hldh_n[14] ;
+ input \mprj_io_hldh_n[15] ;
+ input \mprj_io_hldh_n[16] ;
+ input \mprj_io_hldh_n[17] ;
+ input \mprj_io_hldh_n[18] ;
+ input \mprj_io_hldh_n[19] ;
+ input \mprj_io_hldh_n[1] ;
+ input \mprj_io_hldh_n[20] ;
+ input \mprj_io_hldh_n[21] ;
+ input \mprj_io_hldh_n[22] ;
+ input \mprj_io_hldh_n[23] ;
+ input \mprj_io_hldh_n[24] ;
+ input \mprj_io_hldh_n[25] ;
+ input \mprj_io_hldh_n[26] ;
+ input \mprj_io_hldh_n[27] ;
+ input \mprj_io_hldh_n[28] ;
+ input \mprj_io_hldh_n[29] ;
+ input \mprj_io_hldh_n[2] ;
+ input \mprj_io_hldh_n[30] ;
+ input \mprj_io_hldh_n[31] ;
+ input \mprj_io_hldh_n[32] ;
+ input \mprj_io_hldh_n[33] ;
+ input \mprj_io_hldh_n[34] ;
+ input \mprj_io_hldh_n[35] ;
+ input \mprj_io_hldh_n[36] ;
+ input \mprj_io_hldh_n[37] ;
+ input \mprj_io_hldh_n[3] ;
+ input \mprj_io_hldh_n[4] ;
+ input \mprj_io_hldh_n[5] ;
+ input \mprj_io_hldh_n[6] ;
+ input \mprj_io_hldh_n[7] ;
+ input \mprj_io_hldh_n[8] ;
+ input \mprj_io_hldh_n[9] ;
+ input \mprj_io_holdover[0] ;
+ input \mprj_io_holdover[10] ;
+ input \mprj_io_holdover[11] ;
+ input \mprj_io_holdover[12] ;
+ input \mprj_io_holdover[13] ;
+ input \mprj_io_holdover[14] ;
+ input \mprj_io_holdover[15] ;
+ input \mprj_io_holdover[16] ;
+ input \mprj_io_holdover[17] ;
+ input \mprj_io_holdover[18] ;
+ input \mprj_io_holdover[19] ;
+ input \mprj_io_holdover[1] ;
+ input \mprj_io_holdover[20] ;
+ input \mprj_io_holdover[21] ;
+ input \mprj_io_holdover[22] ;
+ input \mprj_io_holdover[23] ;
+ input \mprj_io_holdover[24] ;
+ input \mprj_io_holdover[25] ;
+ input \mprj_io_holdover[26] ;
+ input \mprj_io_holdover[27] ;
+ input \mprj_io_holdover[28] ;
+ input \mprj_io_holdover[29] ;
+ input \mprj_io_holdover[2] ;
+ input \mprj_io_holdover[30] ;
+ input \mprj_io_holdover[31] ;
+ input \mprj_io_holdover[32] ;
+ input \mprj_io_holdover[33] ;
+ input \mprj_io_holdover[34] ;
+ input \mprj_io_holdover[35] ;
+ input \mprj_io_holdover[36] ;
+ input \mprj_io_holdover[37] ;
+ input \mprj_io_holdover[3] ;
+ input \mprj_io_holdover[4] ;
+ input \mprj_io_holdover[5] ;
+ input \mprj_io_holdover[6] ;
+ input \mprj_io_holdover[7] ;
+ input \mprj_io_holdover[8] ;
+ input \mprj_io_holdover[9] ;
+ input \mprj_io_ib_mode_sel[0] ;
+ input \mprj_io_ib_mode_sel[10] ;
+ input \mprj_io_ib_mode_sel[11] ;
+ input \mprj_io_ib_mode_sel[12] ;
+ input \mprj_io_ib_mode_sel[13] ;
+ input \mprj_io_ib_mode_sel[14] ;
+ input \mprj_io_ib_mode_sel[15] ;
+ input \mprj_io_ib_mode_sel[16] ;
+ input \mprj_io_ib_mode_sel[17] ;
+ input \mprj_io_ib_mode_sel[18] ;
+ input \mprj_io_ib_mode_sel[19] ;
+ input \mprj_io_ib_mode_sel[1] ;
+ input \mprj_io_ib_mode_sel[20] ;
+ input \mprj_io_ib_mode_sel[21] ;
+ input \mprj_io_ib_mode_sel[22] ;
+ input \mprj_io_ib_mode_sel[23] ;
+ input \mprj_io_ib_mode_sel[24] ;
+ input \mprj_io_ib_mode_sel[25] ;
+ input \mprj_io_ib_mode_sel[26] ;
+ input \mprj_io_ib_mode_sel[27] ;
+ input \mprj_io_ib_mode_sel[28] ;
+ input \mprj_io_ib_mode_sel[29] ;
+ input \mprj_io_ib_mode_sel[2] ;
+ input \mprj_io_ib_mode_sel[30] ;
+ input \mprj_io_ib_mode_sel[31] ;
+ input \mprj_io_ib_mode_sel[32] ;
+ input \mprj_io_ib_mode_sel[33] ;
+ input \mprj_io_ib_mode_sel[34] ;
+ input \mprj_io_ib_mode_sel[35] ;
+ input \mprj_io_ib_mode_sel[36] ;
+ input \mprj_io_ib_mode_sel[37] ;
+ input \mprj_io_ib_mode_sel[3] ;
+ input \mprj_io_ib_mode_sel[4] ;
+ input \mprj_io_ib_mode_sel[5] ;
+ input \mprj_io_ib_mode_sel[6] ;
+ input \mprj_io_ib_mode_sel[7] ;
+ input \mprj_io_ib_mode_sel[8] ;
+ input \mprj_io_ib_mode_sel[9] ;
+ output \mprj_io_in[0] ;
+ output \mprj_io_in[10] ;
+ output \mprj_io_in[11] ;
+ output \mprj_io_in[12] ;
+ output \mprj_io_in[13] ;
+ output \mprj_io_in[14] ;
+ output \mprj_io_in[15] ;
+ output \mprj_io_in[16] ;
+ output \mprj_io_in[17] ;
+ output \mprj_io_in[18] ;
+ output \mprj_io_in[19] ;
+ output \mprj_io_in[1] ;
+ output \mprj_io_in[20] ;
+ output \mprj_io_in[21] ;
+ output \mprj_io_in[22] ;
+ output \mprj_io_in[23] ;
+ output \mprj_io_in[24] ;
+ output \mprj_io_in[25] ;
+ output \mprj_io_in[26] ;
+ output \mprj_io_in[27] ;
+ output \mprj_io_in[28] ;
+ output \mprj_io_in[29] ;
+ output \mprj_io_in[2] ;
+ output \mprj_io_in[30] ;
+ output \mprj_io_in[31] ;
+ output \mprj_io_in[32] ;
+ output \mprj_io_in[33] ;
+ output \mprj_io_in[34] ;
+ output \mprj_io_in[35] ;
+ output \mprj_io_in[36] ;
+ output \mprj_io_in[37] ;
+ output \mprj_io_in[3] ;
+ output \mprj_io_in[4] ;
+ output \mprj_io_in[5] ;
+ output \mprj_io_in[6] ;
+ output \mprj_io_in[7] ;
+ output \mprj_io_in[8] ;
+ output \mprj_io_in[9] ;
+ input \mprj_io_inp_dis[0] ;
+ input \mprj_io_inp_dis[10] ;
+ input \mprj_io_inp_dis[11] ;
+ input \mprj_io_inp_dis[12] ;
+ input \mprj_io_inp_dis[13] ;
+ input \mprj_io_inp_dis[14] ;
+ input \mprj_io_inp_dis[15] ;
+ input \mprj_io_inp_dis[16] ;
+ input \mprj_io_inp_dis[17] ;
+ input \mprj_io_inp_dis[18] ;
+ input \mprj_io_inp_dis[19] ;
+ input \mprj_io_inp_dis[1] ;
+ input \mprj_io_inp_dis[20] ;
+ input \mprj_io_inp_dis[21] ;
+ input \mprj_io_inp_dis[22] ;
+ input \mprj_io_inp_dis[23] ;
+ input \mprj_io_inp_dis[24] ;
+ input \mprj_io_inp_dis[25] ;
+ input \mprj_io_inp_dis[26] ;
+ input \mprj_io_inp_dis[27] ;
+ input \mprj_io_inp_dis[28] ;
+ input \mprj_io_inp_dis[29] ;
+ input \mprj_io_inp_dis[2] ;
+ input \mprj_io_inp_dis[30] ;
+ input \mprj_io_inp_dis[31] ;
+ input \mprj_io_inp_dis[32] ;
+ input \mprj_io_inp_dis[33] ;
+ input \mprj_io_inp_dis[34] ;
+ input \mprj_io_inp_dis[35] ;
+ input \mprj_io_inp_dis[36] ;
+ input \mprj_io_inp_dis[37] ;
+ input \mprj_io_inp_dis[3] ;
+ input \mprj_io_inp_dis[4] ;
+ input \mprj_io_inp_dis[5] ;
+ input \mprj_io_inp_dis[6] ;
+ input \mprj_io_inp_dis[7] ;
+ input \mprj_io_inp_dis[8] ;
+ input \mprj_io_inp_dis[9] ;
+ input \mprj_io_oeb[0] ;
+ input \mprj_io_oeb[10] ;
+ input \mprj_io_oeb[11] ;
+ input \mprj_io_oeb[12] ;
+ input \mprj_io_oeb[13] ;
+ input \mprj_io_oeb[14] ;
+ input \mprj_io_oeb[15] ;
+ input \mprj_io_oeb[16] ;
+ input \mprj_io_oeb[17] ;
+ input \mprj_io_oeb[18] ;
+ input \mprj_io_oeb[19] ;
+ input \mprj_io_oeb[1] ;
+ input \mprj_io_oeb[20] ;
+ input \mprj_io_oeb[21] ;
+ input \mprj_io_oeb[22] ;
+ input \mprj_io_oeb[23] ;
+ input \mprj_io_oeb[24] ;
+ input \mprj_io_oeb[25] ;
+ input \mprj_io_oeb[26] ;
+ input \mprj_io_oeb[27] ;
+ input \mprj_io_oeb[28] ;
+ input \mprj_io_oeb[29] ;
+ input \mprj_io_oeb[2] ;
+ input \mprj_io_oeb[30] ;
+ input \mprj_io_oeb[31] ;
+ input \mprj_io_oeb[32] ;
+ input \mprj_io_oeb[33] ;
+ input \mprj_io_oeb[34] ;
+ input \mprj_io_oeb[35] ;
+ input \mprj_io_oeb[36] ;
+ input \mprj_io_oeb[37] ;
+ input \mprj_io_oeb[3] ;
+ input \mprj_io_oeb[4] ;
+ input \mprj_io_oeb[5] ;
+ input \mprj_io_oeb[6] ;
+ input \mprj_io_oeb[7] ;
+ input \mprj_io_oeb[8] ;
+ input \mprj_io_oeb[9] ;
+ input \mprj_io_out[0] ;
+ input \mprj_io_out[10] ;
+ input \mprj_io_out[11] ;
+ input \mprj_io_out[12] ;
+ input \mprj_io_out[13] ;
+ input \mprj_io_out[14] ;
+ input \mprj_io_out[15] ;
+ input \mprj_io_out[16] ;
+ input \mprj_io_out[17] ;
+ input \mprj_io_out[18] ;
+ input \mprj_io_out[19] ;
+ input \mprj_io_out[1] ;
+ input \mprj_io_out[20] ;
+ input \mprj_io_out[21] ;
+ input \mprj_io_out[22] ;
+ input \mprj_io_out[23] ;
+ input \mprj_io_out[24] ;
+ input \mprj_io_out[25] ;
+ input \mprj_io_out[26] ;
+ input \mprj_io_out[27] ;
+ input \mprj_io_out[28] ;
+ input \mprj_io_out[29] ;
+ input \mprj_io_out[2] ;
+ input \mprj_io_out[30] ;
+ input \mprj_io_out[31] ;
+ input \mprj_io_out[32] ;
+ input \mprj_io_out[33] ;
+ input \mprj_io_out[34] ;
+ input \mprj_io_out[35] ;
+ input \mprj_io_out[36] ;
+ input \mprj_io_out[37] ;
+ input \mprj_io_out[3] ;
+ input \mprj_io_out[4] ;
+ input \mprj_io_out[5] ;
+ input \mprj_io_out[6] ;
+ input \mprj_io_out[7] ;
+ input \mprj_io_out[8] ;
+ input \mprj_io_out[9] ;
+ input \mprj_io_slow_sel[0] ;
+ input \mprj_io_slow_sel[10] ;
+ input \mprj_io_slow_sel[11] ;
+ input \mprj_io_slow_sel[12] ;
+ input \mprj_io_slow_sel[13] ;
+ input \mprj_io_slow_sel[14] ;
+ input \mprj_io_slow_sel[15] ;
+ input \mprj_io_slow_sel[16] ;
+ input \mprj_io_slow_sel[17] ;
+ input \mprj_io_slow_sel[18] ;
+ input \mprj_io_slow_sel[19] ;
+ input \mprj_io_slow_sel[1] ;
+ input \mprj_io_slow_sel[20] ;
+ input \mprj_io_slow_sel[21] ;
+ input \mprj_io_slow_sel[22] ;
+ input \mprj_io_slow_sel[23] ;
+ input \mprj_io_slow_sel[24] ;
+ input \mprj_io_slow_sel[25] ;
+ input \mprj_io_slow_sel[26] ;
+ input \mprj_io_slow_sel[27] ;
+ input \mprj_io_slow_sel[28] ;
+ input \mprj_io_slow_sel[29] ;
+ input \mprj_io_slow_sel[2] ;
+ input \mprj_io_slow_sel[30] ;
+ input \mprj_io_slow_sel[31] ;
+ input \mprj_io_slow_sel[32] ;
+ input \mprj_io_slow_sel[33] ;
+ input \mprj_io_slow_sel[34] ;
+ input \mprj_io_slow_sel[35] ;
+ input \mprj_io_slow_sel[36] ;
+ input \mprj_io_slow_sel[37] ;
+ input \mprj_io_slow_sel[3] ;
+ input \mprj_io_slow_sel[4] ;
+ input \mprj_io_slow_sel[5] ;
+ input \mprj_io_slow_sel[6] ;
+ input \mprj_io_slow_sel[7] ;
+ input \mprj_io_slow_sel[8] ;
+ input \mprj_io_slow_sel[9] ;
+ input \mprj_io_vtrip_sel[0] ;
+ input \mprj_io_vtrip_sel[10] ;
+ input \mprj_io_vtrip_sel[11] ;
+ input \mprj_io_vtrip_sel[12] ;
+ input \mprj_io_vtrip_sel[13] ;
+ input \mprj_io_vtrip_sel[14] ;
+ input \mprj_io_vtrip_sel[15] ;
+ input \mprj_io_vtrip_sel[16] ;
+ input \mprj_io_vtrip_sel[17] ;
+ input \mprj_io_vtrip_sel[18] ;
+ input \mprj_io_vtrip_sel[19] ;
+ input \mprj_io_vtrip_sel[1] ;
+ input \mprj_io_vtrip_sel[20] ;
+ input \mprj_io_vtrip_sel[21] ;
+ input \mprj_io_vtrip_sel[22] ;
+ input \mprj_io_vtrip_sel[23] ;
+ input \mprj_io_vtrip_sel[24] ;
+ input \mprj_io_vtrip_sel[25] ;
+ input \mprj_io_vtrip_sel[26] ;
+ input \mprj_io_vtrip_sel[27] ;
+ input \mprj_io_vtrip_sel[28] ;
+ input \mprj_io_vtrip_sel[29] ;
+ input \mprj_io_vtrip_sel[2] ;
+ input \mprj_io_vtrip_sel[30] ;
+ input \mprj_io_vtrip_sel[31] ;
+ input \mprj_io_vtrip_sel[32] ;
+ input \mprj_io_vtrip_sel[33] ;
+ input \mprj_io_vtrip_sel[34] ;
+ input \mprj_io_vtrip_sel[35] ;
+ input \mprj_io_vtrip_sel[36] ;
+ input \mprj_io_vtrip_sel[37] ;
+ input \mprj_io_vtrip_sel[3] ;
+ input \mprj_io_vtrip_sel[4] ;
+ input \mprj_io_vtrip_sel[5] ;
+ input \mprj_io_vtrip_sel[6] ;
+ input \mprj_io_vtrip_sel[7] ;
+ input \mprj_io_vtrip_sel[8] ;
+ input \mprj_io_vtrip_sel[9] ;
+ wire \mprj_pads.analog_a ;
+ wire \mprj_pads.analog_b ;
+ wire \mprj_pads.analog_en[0] ;
+ wire \mprj_pads.analog_en[10] ;
+ wire \mprj_pads.analog_en[11] ;
+ wire \mprj_pads.analog_en[12] ;
+ wire \mprj_pads.analog_en[13] ;
+ wire \mprj_pads.analog_en[14] ;
+ wire \mprj_pads.analog_en[15] ;
+ wire \mprj_pads.analog_en[16] ;
+ wire \mprj_pads.analog_en[17] ;
+ wire \mprj_pads.analog_en[18] ;
+ wire \mprj_pads.analog_en[19] ;
+ wire \mprj_pads.analog_en[1] ;
+ wire \mprj_pads.analog_en[20] ;
+ wire \mprj_pads.analog_en[21] ;
+ wire \mprj_pads.analog_en[22] ;
+ wire \mprj_pads.analog_en[23] ;
+ wire \mprj_pads.analog_en[24] ;
+ wire \mprj_pads.analog_en[25] ;
+ wire \mprj_pads.analog_en[26] ;
+ wire \mprj_pads.analog_en[27] ;
+ wire \mprj_pads.analog_en[28] ;
+ wire \mprj_pads.analog_en[29] ;
+ wire \mprj_pads.analog_en[2] ;
+ wire \mprj_pads.analog_en[30] ;
+ wire \mprj_pads.analog_en[31] ;
+ wire \mprj_pads.analog_en[32] ;
+ wire \mprj_pads.analog_en[33] ;
+ wire \mprj_pads.analog_en[34] ;
+ wire \mprj_pads.analog_en[35] ;
+ wire \mprj_pads.analog_en[36] ;
+ wire \mprj_pads.analog_en[37] ;
+ wire \mprj_pads.analog_en[3] ;
+ wire \mprj_pads.analog_en[4] ;
+ wire \mprj_pads.analog_en[5] ;
+ wire \mprj_pads.analog_en[6] ;
+ wire \mprj_pads.analog_en[7] ;
+ wire \mprj_pads.analog_en[8] ;
+ wire \mprj_pads.analog_en[9] ;
+ wire \mprj_pads.analog_io[0] ;
+ wire \mprj_pads.analog_io[10] ;
+ wire \mprj_pads.analog_io[11] ;
+ wire \mprj_pads.analog_io[12] ;
+ wire \mprj_pads.analog_io[13] ;
+ wire \mprj_pads.analog_io[14] ;
+ wire \mprj_pads.analog_io[15] ;
+ wire \mprj_pads.analog_io[16] ;
+ wire \mprj_pads.analog_io[17] ;
+ wire \mprj_pads.analog_io[18] ;
+ wire \mprj_pads.analog_io[19] ;
+ wire \mprj_pads.analog_io[1] ;
+ wire \mprj_pads.analog_io[20] ;
+ wire \mprj_pads.analog_io[21] ;
+ wire \mprj_pads.analog_io[22] ;
+ wire \mprj_pads.analog_io[23] ;
+ wire \mprj_pads.analog_io[24] ;
+ wire \mprj_pads.analog_io[25] ;
+ wire \mprj_pads.analog_io[26] ;
+ wire \mprj_pads.analog_io[27] ;
+ wire \mprj_pads.analog_io[28] ;
+ wire \mprj_pads.analog_io[29] ;
+ wire \mprj_pads.analog_io[2] ;
+ wire \mprj_pads.analog_io[30] ;
+ wire \mprj_pads.analog_io[3] ;
+ wire \mprj_pads.analog_io[4] ;
+ wire \mprj_pads.analog_io[5] ;
+ wire \mprj_pads.analog_io[6] ;
+ wire \mprj_pads.analog_io[7] ;
+ wire \mprj_pads.analog_io[8] ;
+ wire \mprj_pads.analog_io[9] ;
+ wire \mprj_pads.analog_pol[0] ;
+ wire \mprj_pads.analog_pol[10] ;
+ wire \mprj_pads.analog_pol[11] ;
+ wire \mprj_pads.analog_pol[12] ;
+ wire \mprj_pads.analog_pol[13] ;
+ wire \mprj_pads.analog_pol[14] ;
+ wire \mprj_pads.analog_pol[15] ;
+ wire \mprj_pads.analog_pol[16] ;
+ wire \mprj_pads.analog_pol[17] ;
+ wire \mprj_pads.analog_pol[18] ;
+ wire \mprj_pads.analog_pol[19] ;
+ wire \mprj_pads.analog_pol[1] ;
+ wire \mprj_pads.analog_pol[20] ;
+ wire \mprj_pads.analog_pol[21] ;
+ wire \mprj_pads.analog_pol[22] ;
+ wire \mprj_pads.analog_pol[23] ;
+ wire \mprj_pads.analog_pol[24] ;
+ wire \mprj_pads.analog_pol[25] ;
+ wire \mprj_pads.analog_pol[26] ;
+ wire \mprj_pads.analog_pol[27] ;
+ wire \mprj_pads.analog_pol[28] ;
+ wire \mprj_pads.analog_pol[29] ;
+ wire \mprj_pads.analog_pol[2] ;
+ wire \mprj_pads.analog_pol[30] ;
+ wire \mprj_pads.analog_pol[31] ;
+ wire \mprj_pads.analog_pol[32] ;
+ wire \mprj_pads.analog_pol[33] ;
+ wire \mprj_pads.analog_pol[34] ;
+ wire \mprj_pads.analog_pol[35] ;
+ wire \mprj_pads.analog_pol[36] ;
+ wire \mprj_pads.analog_pol[37] ;
+ wire \mprj_pads.analog_pol[3] ;
+ wire \mprj_pads.analog_pol[4] ;
+ wire \mprj_pads.analog_pol[5] ;
+ wire \mprj_pads.analog_pol[6] ;
+ wire \mprj_pads.analog_pol[7] ;
+ wire \mprj_pads.analog_pol[8] ;
+ wire \mprj_pads.analog_pol[9] ;
+ wire \mprj_pads.analog_sel[0] ;
+ wire \mprj_pads.analog_sel[10] ;
+ wire \mprj_pads.analog_sel[11] ;
+ wire \mprj_pads.analog_sel[12] ;
+ wire \mprj_pads.analog_sel[13] ;
+ wire \mprj_pads.analog_sel[14] ;
+ wire \mprj_pads.analog_sel[15] ;
+ wire \mprj_pads.analog_sel[16] ;
+ wire \mprj_pads.analog_sel[17] ;
+ wire \mprj_pads.analog_sel[18] ;
+ wire \mprj_pads.analog_sel[19] ;
+ wire \mprj_pads.analog_sel[1] ;
+ wire \mprj_pads.analog_sel[20] ;
+ wire \mprj_pads.analog_sel[21] ;
+ wire \mprj_pads.analog_sel[22] ;
+ wire \mprj_pads.analog_sel[23] ;
+ wire \mprj_pads.analog_sel[24] ;
+ wire \mprj_pads.analog_sel[25] ;
+ wire \mprj_pads.analog_sel[26] ;
+ wire \mprj_pads.analog_sel[27] ;
+ wire \mprj_pads.analog_sel[28] ;
+ wire \mprj_pads.analog_sel[29] ;
+ wire \mprj_pads.analog_sel[2] ;
+ wire \mprj_pads.analog_sel[30] ;
+ wire \mprj_pads.analog_sel[31] ;
+ wire \mprj_pads.analog_sel[32] ;
+ wire \mprj_pads.analog_sel[33] ;
+ wire \mprj_pads.analog_sel[34] ;
+ wire \mprj_pads.analog_sel[35] ;
+ wire \mprj_pads.analog_sel[36] ;
+ wire \mprj_pads.analog_sel[37] ;
+ wire \mprj_pads.analog_sel[3] ;
+ wire \mprj_pads.analog_sel[4] ;
+ wire \mprj_pads.analog_sel[5] ;
+ wire \mprj_pads.analog_sel[6] ;
+ wire \mprj_pads.analog_sel[7] ;
+ wire \mprj_pads.analog_sel[8] ;
+ wire \mprj_pads.analog_sel[9] ;
+ wire \mprj_pads.dm[0] ;
+ wire \mprj_pads.dm[100] ;
+ wire \mprj_pads.dm[101] ;
+ wire \mprj_pads.dm[102] ;
+ wire \mprj_pads.dm[103] ;
+ wire \mprj_pads.dm[104] ;
+ wire \mprj_pads.dm[105] ;
+ wire \mprj_pads.dm[106] ;
+ wire \mprj_pads.dm[107] ;
+ wire \mprj_pads.dm[108] ;
+ wire \mprj_pads.dm[109] ;
+ wire \mprj_pads.dm[10] ;
+ wire \mprj_pads.dm[110] ;
+ wire \mprj_pads.dm[111] ;
+ wire \mprj_pads.dm[112] ;
+ wire \mprj_pads.dm[113] ;
+ wire \mprj_pads.dm[11] ;
+ wire \mprj_pads.dm[12] ;
+ wire \mprj_pads.dm[13] ;
+ wire \mprj_pads.dm[14] ;
+ wire \mprj_pads.dm[15] ;
+ wire \mprj_pads.dm[16] ;
+ wire \mprj_pads.dm[17] ;
+ wire \mprj_pads.dm[18] ;
+ wire \mprj_pads.dm[19] ;
+ wire \mprj_pads.dm[1] ;
+ wire \mprj_pads.dm[20] ;
+ wire \mprj_pads.dm[21] ;
+ wire \mprj_pads.dm[22] ;
+ wire \mprj_pads.dm[23] ;
+ wire \mprj_pads.dm[24] ;
+ wire \mprj_pads.dm[25] ;
+ wire \mprj_pads.dm[26] ;
+ wire \mprj_pads.dm[27] ;
+ wire \mprj_pads.dm[28] ;
+ wire \mprj_pads.dm[29] ;
+ wire \mprj_pads.dm[2] ;
+ wire \mprj_pads.dm[30] ;
+ wire \mprj_pads.dm[31] ;
+ wire \mprj_pads.dm[32] ;
+ wire \mprj_pads.dm[33] ;
+ wire \mprj_pads.dm[34] ;
+ wire \mprj_pads.dm[35] ;
+ wire \mprj_pads.dm[36] ;
+ wire \mprj_pads.dm[37] ;
+ wire \mprj_pads.dm[38] ;
+ wire \mprj_pads.dm[39] ;
+ wire \mprj_pads.dm[3] ;
+ wire \mprj_pads.dm[40] ;
+ wire \mprj_pads.dm[41] ;
+ wire \mprj_pads.dm[42] ;
+ wire \mprj_pads.dm[43] ;
+ wire \mprj_pads.dm[44] ;
+ wire \mprj_pads.dm[45] ;
+ wire \mprj_pads.dm[46] ;
+ wire \mprj_pads.dm[47] ;
+ wire \mprj_pads.dm[48] ;
+ wire \mprj_pads.dm[49] ;
+ wire \mprj_pads.dm[4] ;
+ wire \mprj_pads.dm[50] ;
+ wire \mprj_pads.dm[51] ;
+ wire \mprj_pads.dm[52] ;
+ wire \mprj_pads.dm[53] ;
+ wire \mprj_pads.dm[54] ;
+ wire \mprj_pads.dm[55] ;
+ wire \mprj_pads.dm[56] ;
+ wire \mprj_pads.dm[57] ;
+ wire \mprj_pads.dm[58] ;
+ wire \mprj_pads.dm[59] ;
+ wire \mprj_pads.dm[5] ;
+ wire \mprj_pads.dm[60] ;
+ wire \mprj_pads.dm[61] ;
+ wire \mprj_pads.dm[62] ;
+ wire \mprj_pads.dm[63] ;
+ wire \mprj_pads.dm[64] ;
+ wire \mprj_pads.dm[65] ;
+ wire \mprj_pads.dm[66] ;
+ wire \mprj_pads.dm[67] ;
+ wire \mprj_pads.dm[68] ;
+ wire \mprj_pads.dm[69] ;
+ wire \mprj_pads.dm[6] ;
+ wire \mprj_pads.dm[70] ;
+ wire \mprj_pads.dm[71] ;
+ wire \mprj_pads.dm[72] ;
+ wire \mprj_pads.dm[73] ;
+ wire \mprj_pads.dm[74] ;
+ wire \mprj_pads.dm[75] ;
+ wire \mprj_pads.dm[76] ;
+ wire \mprj_pads.dm[77] ;
+ wire \mprj_pads.dm[78] ;
+ wire \mprj_pads.dm[79] ;
+ wire \mprj_pads.dm[7] ;
+ wire \mprj_pads.dm[80] ;
+ wire \mprj_pads.dm[81] ;
+ wire \mprj_pads.dm[82] ;
+ wire \mprj_pads.dm[83] ;
+ wire \mprj_pads.dm[84] ;
+ wire \mprj_pads.dm[85] ;
+ wire \mprj_pads.dm[86] ;
+ wire \mprj_pads.dm[87] ;
+ wire \mprj_pads.dm[88] ;
+ wire \mprj_pads.dm[89] ;
+ wire \mprj_pads.dm[8] ;
+ wire \mprj_pads.dm[90] ;
+ wire \mprj_pads.dm[91] ;
+ wire \mprj_pads.dm[92] ;
+ wire \mprj_pads.dm[93] ;
+ wire \mprj_pads.dm[94] ;
+ wire \mprj_pads.dm[95] ;
+ wire \mprj_pads.dm[96] ;
+ wire \mprj_pads.dm[97] ;
+ wire \mprj_pads.dm[98] ;
+ wire \mprj_pads.dm[99] ;
+ wire \mprj_pads.dm[9] ;
+ wire \mprj_pads.enh[0] ;
+ wire \mprj_pads.enh[10] ;
+ wire \mprj_pads.enh[11] ;
+ wire \mprj_pads.enh[12] ;
+ wire \mprj_pads.enh[13] ;
+ wire \mprj_pads.enh[14] ;
+ wire \mprj_pads.enh[15] ;
+ wire \mprj_pads.enh[16] ;
+ wire \mprj_pads.enh[17] ;
+ wire \mprj_pads.enh[18] ;
+ wire \mprj_pads.enh[19] ;
+ wire \mprj_pads.enh[1] ;
+ wire \mprj_pads.enh[20] ;
+ wire \mprj_pads.enh[21] ;
+ wire \mprj_pads.enh[22] ;
+ wire \mprj_pads.enh[23] ;
+ wire \mprj_pads.enh[24] ;
+ wire \mprj_pads.enh[25] ;
+ wire \mprj_pads.enh[26] ;
+ wire \mprj_pads.enh[27] ;
+ wire \mprj_pads.enh[28] ;
+ wire \mprj_pads.enh[29] ;
+ wire \mprj_pads.enh[2] ;
+ wire \mprj_pads.enh[30] ;
+ wire \mprj_pads.enh[31] ;
+ wire \mprj_pads.enh[32] ;
+ wire \mprj_pads.enh[33] ;
+ wire \mprj_pads.enh[34] ;
+ wire \mprj_pads.enh[35] ;
+ wire \mprj_pads.enh[36] ;
+ wire \mprj_pads.enh[37] ;
+ wire \mprj_pads.enh[3] ;
+ wire \mprj_pads.enh[4] ;
+ wire \mprj_pads.enh[5] ;
+ wire \mprj_pads.enh[6] ;
+ wire \mprj_pads.enh[7] ;
+ wire \mprj_pads.enh[8] ;
+ wire \mprj_pads.enh[9] ;
+ wire \mprj_pads.hldh_n[0] ;
+ wire \mprj_pads.hldh_n[10] ;
+ wire \mprj_pads.hldh_n[11] ;
+ wire \mprj_pads.hldh_n[12] ;
+ wire \mprj_pads.hldh_n[13] ;
+ wire \mprj_pads.hldh_n[14] ;
+ wire \mprj_pads.hldh_n[15] ;
+ wire \mprj_pads.hldh_n[16] ;
+ wire \mprj_pads.hldh_n[17] ;
+ wire \mprj_pads.hldh_n[18] ;
+ wire \mprj_pads.hldh_n[19] ;
+ wire \mprj_pads.hldh_n[1] ;
+ wire \mprj_pads.hldh_n[20] ;
+ wire \mprj_pads.hldh_n[21] ;
+ wire \mprj_pads.hldh_n[22] ;
+ wire \mprj_pads.hldh_n[23] ;
+ wire \mprj_pads.hldh_n[24] ;
+ wire \mprj_pads.hldh_n[25] ;
+ wire \mprj_pads.hldh_n[26] ;
+ wire \mprj_pads.hldh_n[27] ;
+ wire \mprj_pads.hldh_n[28] ;
+ wire \mprj_pads.hldh_n[29] ;
+ wire \mprj_pads.hldh_n[2] ;
+ wire \mprj_pads.hldh_n[30] ;
+ wire \mprj_pads.hldh_n[31] ;
+ wire \mprj_pads.hldh_n[32] ;
+ wire \mprj_pads.hldh_n[33] ;
+ wire \mprj_pads.hldh_n[34] ;
+ wire \mprj_pads.hldh_n[35] ;
+ wire \mprj_pads.hldh_n[36] ;
+ wire \mprj_pads.hldh_n[37] ;
+ wire \mprj_pads.hldh_n[3] ;
+ wire \mprj_pads.hldh_n[4] ;
+ wire \mprj_pads.hldh_n[5] ;
+ wire \mprj_pads.hldh_n[6] ;
+ wire \mprj_pads.hldh_n[7] ;
+ wire \mprj_pads.hldh_n[8] ;
+ wire \mprj_pads.hldh_n[9] ;
+ wire \mprj_pads.holdover[0] ;
+ wire \mprj_pads.holdover[10] ;
+ wire \mprj_pads.holdover[11] ;
+ wire \mprj_pads.holdover[12] ;
+ wire \mprj_pads.holdover[13] ;
+ wire \mprj_pads.holdover[14] ;
+ wire \mprj_pads.holdover[15] ;
+ wire \mprj_pads.holdover[16] ;
+ wire \mprj_pads.holdover[17] ;
+ wire \mprj_pads.holdover[18] ;
+ wire \mprj_pads.holdover[19] ;
+ wire \mprj_pads.holdover[1] ;
+ wire \mprj_pads.holdover[20] ;
+ wire \mprj_pads.holdover[21] ;
+ wire \mprj_pads.holdover[22] ;
+ wire \mprj_pads.holdover[23] ;
+ wire \mprj_pads.holdover[24] ;
+ wire \mprj_pads.holdover[25] ;
+ wire \mprj_pads.holdover[26] ;
+ wire \mprj_pads.holdover[27] ;
+ wire \mprj_pads.holdover[28] ;
+ wire \mprj_pads.holdover[29] ;
+ wire \mprj_pads.holdover[2] ;
+ wire \mprj_pads.holdover[30] ;
+ wire \mprj_pads.holdover[31] ;
+ wire \mprj_pads.holdover[32] ;
+ wire \mprj_pads.holdover[33] ;
+ wire \mprj_pads.holdover[34] ;
+ wire \mprj_pads.holdover[35] ;
+ wire \mprj_pads.holdover[36] ;
+ wire \mprj_pads.holdover[37] ;
+ wire \mprj_pads.holdover[3] ;
+ wire \mprj_pads.holdover[4] ;
+ wire \mprj_pads.holdover[5] ;
+ wire \mprj_pads.holdover[6] ;
+ wire \mprj_pads.holdover[7] ;
+ wire \mprj_pads.holdover[8] ;
+ wire \mprj_pads.holdover[9] ;
+ wire \mprj_pads.ib_mode_sel[0] ;
+ wire \mprj_pads.ib_mode_sel[10] ;
+ wire \mprj_pads.ib_mode_sel[11] ;
+ wire \mprj_pads.ib_mode_sel[12] ;
+ wire \mprj_pads.ib_mode_sel[13] ;
+ wire \mprj_pads.ib_mode_sel[14] ;
+ wire \mprj_pads.ib_mode_sel[15] ;
+ wire \mprj_pads.ib_mode_sel[16] ;
+ wire \mprj_pads.ib_mode_sel[17] ;
+ wire \mprj_pads.ib_mode_sel[18] ;
+ wire \mprj_pads.ib_mode_sel[19] ;
+ wire \mprj_pads.ib_mode_sel[1] ;
+ wire \mprj_pads.ib_mode_sel[20] ;
+ wire \mprj_pads.ib_mode_sel[21] ;
+ wire \mprj_pads.ib_mode_sel[22] ;
+ wire \mprj_pads.ib_mode_sel[23] ;
+ wire \mprj_pads.ib_mode_sel[24] ;
+ wire \mprj_pads.ib_mode_sel[25] ;
+ wire \mprj_pads.ib_mode_sel[26] ;
+ wire \mprj_pads.ib_mode_sel[27] ;
+ wire \mprj_pads.ib_mode_sel[28] ;
+ wire \mprj_pads.ib_mode_sel[29] ;
+ wire \mprj_pads.ib_mode_sel[2] ;
+ wire \mprj_pads.ib_mode_sel[30] ;
+ wire \mprj_pads.ib_mode_sel[31] ;
+ wire \mprj_pads.ib_mode_sel[32] ;
+ wire \mprj_pads.ib_mode_sel[33] ;
+ wire \mprj_pads.ib_mode_sel[34] ;
+ wire \mprj_pads.ib_mode_sel[35] ;
+ wire \mprj_pads.ib_mode_sel[36] ;
+ wire \mprj_pads.ib_mode_sel[37] ;
+ wire \mprj_pads.ib_mode_sel[3] ;
+ wire \mprj_pads.ib_mode_sel[4] ;
+ wire \mprj_pads.ib_mode_sel[5] ;
+ wire \mprj_pads.ib_mode_sel[6] ;
+ wire \mprj_pads.ib_mode_sel[7] ;
+ wire \mprj_pads.ib_mode_sel[8] ;
+ wire \mprj_pads.ib_mode_sel[9] ;
+ wire \mprj_pads.inp_dis[0] ;
+ wire \mprj_pads.inp_dis[10] ;
+ wire \mprj_pads.inp_dis[11] ;
+ wire \mprj_pads.inp_dis[12] ;
+ wire \mprj_pads.inp_dis[13] ;
+ wire \mprj_pads.inp_dis[14] ;
+ wire \mprj_pads.inp_dis[15] ;
+ wire \mprj_pads.inp_dis[16] ;
+ wire \mprj_pads.inp_dis[17] ;
+ wire \mprj_pads.inp_dis[18] ;
+ wire \mprj_pads.inp_dis[19] ;
+ wire \mprj_pads.inp_dis[1] ;
+ wire \mprj_pads.inp_dis[20] ;
+ wire \mprj_pads.inp_dis[21] ;
+ wire \mprj_pads.inp_dis[22] ;
+ wire \mprj_pads.inp_dis[23] ;
+ wire \mprj_pads.inp_dis[24] ;
+ wire \mprj_pads.inp_dis[25] ;
+ wire \mprj_pads.inp_dis[26] ;
+ wire \mprj_pads.inp_dis[27] ;
+ wire \mprj_pads.inp_dis[28] ;
+ wire \mprj_pads.inp_dis[29] ;
+ wire \mprj_pads.inp_dis[2] ;
+ wire \mprj_pads.inp_dis[30] ;
+ wire \mprj_pads.inp_dis[31] ;
+ wire \mprj_pads.inp_dis[32] ;
+ wire \mprj_pads.inp_dis[33] ;
+ wire \mprj_pads.inp_dis[34] ;
+ wire \mprj_pads.inp_dis[35] ;
+ wire \mprj_pads.inp_dis[36] ;
+ wire \mprj_pads.inp_dis[37] ;
+ wire \mprj_pads.inp_dis[3] ;
+ wire \mprj_pads.inp_dis[4] ;
+ wire \mprj_pads.inp_dis[5] ;
+ wire \mprj_pads.inp_dis[6] ;
+ wire \mprj_pads.inp_dis[7] ;
+ wire \mprj_pads.inp_dis[8] ;
+ wire \mprj_pads.inp_dis[9] ;
+ wire \mprj_pads.io[0] ;
+ wire \mprj_pads.io[10] ;
+ wire \mprj_pads.io[11] ;
+ wire \mprj_pads.io[12] ;
+ wire \mprj_pads.io[13] ;
+ wire \mprj_pads.io[14] ;
+ wire \mprj_pads.io[15] ;
+ wire \mprj_pads.io[16] ;
+ wire \mprj_pads.io[17] ;
+ wire \mprj_pads.io[18] ;
+ wire \mprj_pads.io[19] ;
+ wire \mprj_pads.io[1] ;
+ wire \mprj_pads.io[20] ;
+ wire \mprj_pads.io[21] ;
+ wire \mprj_pads.io[22] ;
+ wire \mprj_pads.io[23] ;
+ wire \mprj_pads.io[24] ;
+ wire \mprj_pads.io[25] ;
+ wire \mprj_pads.io[26] ;
+ wire \mprj_pads.io[27] ;
+ wire \mprj_pads.io[28] ;
+ wire \mprj_pads.io[29] ;
+ wire \mprj_pads.io[2] ;
+ wire \mprj_pads.io[30] ;
+ wire \mprj_pads.io[31] ;
+ wire \mprj_pads.io[32] ;
+ wire \mprj_pads.io[33] ;
+ wire \mprj_pads.io[34] ;
+ wire \mprj_pads.io[35] ;
+ wire \mprj_pads.io[36] ;
+ wire \mprj_pads.io[37] ;
+ wire \mprj_pads.io[3] ;
+ wire \mprj_pads.io[4] ;
+ wire \mprj_pads.io[5] ;
+ wire \mprj_pads.io[6] ;
+ wire \mprj_pads.io[7] ;
+ wire \mprj_pads.io[8] ;
+ wire \mprj_pads.io[9] ;
+ wire \mprj_pads.io_in[0] ;
+ wire \mprj_pads.io_in[10] ;
+ wire \mprj_pads.io_in[11] ;
+ wire \mprj_pads.io_in[12] ;
+ wire \mprj_pads.io_in[13] ;
+ wire \mprj_pads.io_in[14] ;
+ wire \mprj_pads.io_in[15] ;
+ wire \mprj_pads.io_in[16] ;
+ wire \mprj_pads.io_in[17] ;
+ wire \mprj_pads.io_in[18] ;
+ wire \mprj_pads.io_in[19] ;
+ wire \mprj_pads.io_in[1] ;
+ wire \mprj_pads.io_in[20] ;
+ wire \mprj_pads.io_in[21] ;
+ wire \mprj_pads.io_in[22] ;
+ wire \mprj_pads.io_in[23] ;
+ wire \mprj_pads.io_in[24] ;
+ wire \mprj_pads.io_in[25] ;
+ wire \mprj_pads.io_in[26] ;
+ wire \mprj_pads.io_in[27] ;
+ wire \mprj_pads.io_in[28] ;
+ wire \mprj_pads.io_in[29] ;
+ wire \mprj_pads.io_in[2] ;
+ wire \mprj_pads.io_in[30] ;
+ wire \mprj_pads.io_in[31] ;
+ wire \mprj_pads.io_in[32] ;
+ wire \mprj_pads.io_in[33] ;
+ wire \mprj_pads.io_in[34] ;
+ wire \mprj_pads.io_in[35] ;
+ wire \mprj_pads.io_in[36] ;
+ wire \mprj_pads.io_in[37] ;
+ wire \mprj_pads.io_in[3] ;
+ wire \mprj_pads.io_in[4] ;
+ wire \mprj_pads.io_in[5] ;
+ wire \mprj_pads.io_in[6] ;
+ wire \mprj_pads.io_in[7] ;
+ wire \mprj_pads.io_in[8] ;
+ wire \mprj_pads.io_in[9] ;
+ wire \mprj_pads.io_out[0] ;
+ wire \mprj_pads.io_out[10] ;
+ wire \mprj_pads.io_out[11] ;
+ wire \mprj_pads.io_out[12] ;
+ wire \mprj_pads.io_out[13] ;
+ wire \mprj_pads.io_out[14] ;
+ wire \mprj_pads.io_out[15] ;
+ wire \mprj_pads.io_out[16] ;
+ wire \mprj_pads.io_out[17] ;
+ wire \mprj_pads.io_out[18] ;
+ wire \mprj_pads.io_out[19] ;
+ wire \mprj_pads.io_out[1] ;
+ wire \mprj_pads.io_out[20] ;
+ wire \mprj_pads.io_out[21] ;
+ wire \mprj_pads.io_out[22] ;
+ wire \mprj_pads.io_out[23] ;
+ wire \mprj_pads.io_out[24] ;
+ wire \mprj_pads.io_out[25] ;
+ wire \mprj_pads.io_out[26] ;
+ wire \mprj_pads.io_out[27] ;
+ wire \mprj_pads.io_out[28] ;
+ wire \mprj_pads.io_out[29] ;
+ wire \mprj_pads.io_out[2] ;
+ wire \mprj_pads.io_out[30] ;
+ wire \mprj_pads.io_out[31] ;
+ wire \mprj_pads.io_out[32] ;
+ wire \mprj_pads.io_out[33] ;
+ wire \mprj_pads.io_out[34] ;
+ wire \mprj_pads.io_out[35] ;
+ wire \mprj_pads.io_out[36] ;
+ wire \mprj_pads.io_out[37] ;
+ wire \mprj_pads.io_out[3] ;
+ wire \mprj_pads.io_out[4] ;
+ wire \mprj_pads.io_out[5] ;
+ wire \mprj_pads.io_out[6] ;
+ wire \mprj_pads.io_out[7] ;
+ wire \mprj_pads.io_out[8] ;
+ wire \mprj_pads.io_out[9] ;
+ wire \mprj_pads.loop1_io[0] ;
+ wire \mprj_pads.loop1_io[10] ;
+ wire \mprj_pads.loop1_io[11] ;
+ wire \mprj_pads.loop1_io[12] ;
+ wire \mprj_pads.loop1_io[13] ;
+ wire \mprj_pads.loop1_io[14] ;
+ wire \mprj_pads.loop1_io[15] ;
+ wire \mprj_pads.loop1_io[16] ;
+ wire \mprj_pads.loop1_io[17] ;
+ wire \mprj_pads.loop1_io[18] ;
+ wire \mprj_pads.loop1_io[19] ;
+ wire \mprj_pads.loop1_io[1] ;
+ wire \mprj_pads.loop1_io[20] ;
+ wire \mprj_pads.loop1_io[21] ;
+ wire \mprj_pads.loop1_io[22] ;
+ wire \mprj_pads.loop1_io[23] ;
+ wire \mprj_pads.loop1_io[24] ;
+ wire \mprj_pads.loop1_io[25] ;
+ wire \mprj_pads.loop1_io[26] ;
+ wire \mprj_pads.loop1_io[27] ;
+ wire \mprj_pads.loop1_io[28] ;
+ wire \mprj_pads.loop1_io[29] ;
+ wire \mprj_pads.loop1_io[2] ;
+ wire \mprj_pads.loop1_io[30] ;
+ wire \mprj_pads.loop1_io[31] ;
+ wire \mprj_pads.loop1_io[32] ;
+ wire \mprj_pads.loop1_io[33] ;
+ wire \mprj_pads.loop1_io[34] ;
+ wire \mprj_pads.loop1_io[35] ;
+ wire \mprj_pads.loop1_io[36] ;
+ wire \mprj_pads.loop1_io[37] ;
+ wire \mprj_pads.loop1_io[3] ;
+ wire \mprj_pads.loop1_io[4] ;
+ wire \mprj_pads.loop1_io[5] ;
+ wire \mprj_pads.loop1_io[6] ;
+ wire \mprj_pads.loop1_io[7] ;
+ wire \mprj_pads.loop1_io[8] ;
+ wire \mprj_pads.loop1_io[9] ;
+ wire \mprj_pads.no_connect[0] ;
+ wire \mprj_pads.no_connect[1] ;
+ wire \mprj_pads.no_connect[2] ;
+ wire \mprj_pads.no_connect[3] ;
+ wire \mprj_pads.no_connect[4] ;
+ wire \mprj_pads.no_connect[5] ;
+ wire \mprj_pads.no_connect[6] ;
+ wire \mprj_pads.oeb[0] ;
+ wire \mprj_pads.oeb[10] ;
+ wire \mprj_pads.oeb[11] ;
+ wire \mprj_pads.oeb[12] ;
+ wire \mprj_pads.oeb[13] ;
+ wire \mprj_pads.oeb[14] ;
+ wire \mprj_pads.oeb[15] ;
+ wire \mprj_pads.oeb[16] ;
+ wire \mprj_pads.oeb[17] ;
+ wire \mprj_pads.oeb[18] ;
+ wire \mprj_pads.oeb[19] ;
+ wire \mprj_pads.oeb[1] ;
+ wire \mprj_pads.oeb[20] ;
+ wire \mprj_pads.oeb[21] ;
+ wire \mprj_pads.oeb[22] ;
+ wire \mprj_pads.oeb[23] ;
+ wire \mprj_pads.oeb[24] ;
+ wire \mprj_pads.oeb[25] ;
+ wire \mprj_pads.oeb[26] ;
+ wire \mprj_pads.oeb[27] ;
+ wire \mprj_pads.oeb[28] ;
+ wire \mprj_pads.oeb[29] ;
+ wire \mprj_pads.oeb[2] ;
+ wire \mprj_pads.oeb[30] ;
+ wire \mprj_pads.oeb[31] ;
+ wire \mprj_pads.oeb[32] ;
+ wire \mprj_pads.oeb[33] ;
+ wire \mprj_pads.oeb[34] ;
+ wire \mprj_pads.oeb[35] ;
+ wire \mprj_pads.oeb[36] ;
+ wire \mprj_pads.oeb[37] ;
+ wire \mprj_pads.oeb[3] ;
+ wire \mprj_pads.oeb[4] ;
+ wire \mprj_pads.oeb[5] ;
+ wire \mprj_pads.oeb[6] ;
+ wire \mprj_pads.oeb[7] ;
+ wire \mprj_pads.oeb[8] ;
+ wire \mprj_pads.oeb[9] ;
+ wire \mprj_pads.porb_h ;
+ wire \mprj_pads.slow_sel[0] ;
+ wire \mprj_pads.slow_sel[10] ;
+ wire \mprj_pads.slow_sel[11] ;
+ wire \mprj_pads.slow_sel[12] ;
+ wire \mprj_pads.slow_sel[13] ;
+ wire \mprj_pads.slow_sel[14] ;
+ wire \mprj_pads.slow_sel[15] ;
+ wire \mprj_pads.slow_sel[16] ;
+ wire \mprj_pads.slow_sel[17] ;
+ wire \mprj_pads.slow_sel[18] ;
+ wire \mprj_pads.slow_sel[19] ;
+ wire \mprj_pads.slow_sel[1] ;
+ wire \mprj_pads.slow_sel[20] ;
+ wire \mprj_pads.slow_sel[21] ;
+ wire \mprj_pads.slow_sel[22] ;
+ wire \mprj_pads.slow_sel[23] ;
+ wire \mprj_pads.slow_sel[24] ;
+ wire \mprj_pads.slow_sel[25] ;
+ wire \mprj_pads.slow_sel[26] ;
+ wire \mprj_pads.slow_sel[27] ;
+ wire \mprj_pads.slow_sel[28] ;
+ wire \mprj_pads.slow_sel[29] ;
+ wire \mprj_pads.slow_sel[2] ;
+ wire \mprj_pads.slow_sel[30] ;
+ wire \mprj_pads.slow_sel[31] ;
+ wire \mprj_pads.slow_sel[32] ;
+ wire \mprj_pads.slow_sel[33] ;
+ wire \mprj_pads.slow_sel[34] ;
+ wire \mprj_pads.slow_sel[35] ;
+ wire \mprj_pads.slow_sel[36] ;
+ wire \mprj_pads.slow_sel[37] ;
+ wire \mprj_pads.slow_sel[3] ;
+ wire \mprj_pads.slow_sel[4] ;
+ wire \mprj_pads.slow_sel[5] ;
+ wire \mprj_pads.slow_sel[6] ;
+ wire \mprj_pads.slow_sel[7] ;
+ wire \mprj_pads.slow_sel[8] ;
+ wire \mprj_pads.slow_sel[9] ;
+ wire \mprj_pads.vccd ;
+ wire \mprj_pads.vccd1 ;
+ wire \mprj_pads.vccd2 ;
+ wire \mprj_pads.vdda ;
+ wire \mprj_pads.vdda1 ;
+ wire \mprj_pads.vdda2 ;
+ wire \mprj_pads.vddio ;
+ wire \mprj_pads.vddio_q ;
+ wire \mprj_pads.vssa ;
+ wire \mprj_pads.vssa1 ;
+ wire \mprj_pads.vssa2 ;
+ wire \mprj_pads.vssd ;
+ wire \mprj_pads.vssd1 ;
+ wire \mprj_pads.vssd2 ;
+ wire \mprj_pads.vssio ;
+ wire \mprj_pads.vssio_q ;
+ wire \mprj_pads.vtrip_sel[0] ;
+ wire \mprj_pads.vtrip_sel[10] ;
+ wire \mprj_pads.vtrip_sel[11] ;
+ wire \mprj_pads.vtrip_sel[12] ;
+ wire \mprj_pads.vtrip_sel[13] ;
+ wire \mprj_pads.vtrip_sel[14] ;
+ wire \mprj_pads.vtrip_sel[15] ;
+ wire \mprj_pads.vtrip_sel[16] ;
+ wire \mprj_pads.vtrip_sel[17] ;
+ wire \mprj_pads.vtrip_sel[18] ;
+ wire \mprj_pads.vtrip_sel[19] ;
+ wire \mprj_pads.vtrip_sel[1] ;
+ wire \mprj_pads.vtrip_sel[20] ;
+ wire \mprj_pads.vtrip_sel[21] ;
+ wire \mprj_pads.vtrip_sel[22] ;
+ wire \mprj_pads.vtrip_sel[23] ;
+ wire \mprj_pads.vtrip_sel[24] ;
+ wire \mprj_pads.vtrip_sel[25] ;
+ wire \mprj_pads.vtrip_sel[26] ;
+ wire \mprj_pads.vtrip_sel[27] ;
+ wire \mprj_pads.vtrip_sel[28] ;
+ wire \mprj_pads.vtrip_sel[29] ;
+ wire \mprj_pads.vtrip_sel[2] ;
+ wire \mprj_pads.vtrip_sel[30] ;
+ wire \mprj_pads.vtrip_sel[31] ;
+ wire \mprj_pads.vtrip_sel[32] ;
+ wire \mprj_pads.vtrip_sel[33] ;
+ wire \mprj_pads.vtrip_sel[34] ;
+ wire \mprj_pads.vtrip_sel[35] ;
+ wire \mprj_pads.vtrip_sel[36] ;
+ wire \mprj_pads.vtrip_sel[37] ;
+ wire \mprj_pads.vtrip_sel[3] ;
+ wire \mprj_pads.vtrip_sel[4] ;
+ wire \mprj_pads.vtrip_sel[5] ;
+ wire \mprj_pads.vtrip_sel[6] ;
+ wire \mprj_pads.vtrip_sel[7] ;
+ wire \mprj_pads.vtrip_sel[8] ;
+ wire \mprj_pads.vtrip_sel[9] ;
+ input por;
+ input porb_h;
+ input resetb;
+ output resetb_core_h;
+ inout vccd;
+ inout vccd1;
+ inout vccd2;
+ inout vdda;
+ inout vdda1;
+ inout vdda2;
+ inout vddio;
+ wire vddio_q;
+ inout vssa;
+ inout vssa1;
+ inout vssa2;
+ inout vssd;
+ inout vssd1;
+ inout vssd2;
+ inout vssio;
+ wire vssio_q;
+ wire xresloop;
+ sky130_ef_io__gpiov2_pad_wrapped clock_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vssd, vssd, vccd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_clock),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(clock_core),
+ .INP_DIS(por),
+ .IN_H(),
+ .OE_N(vccd),
+ .OUT(vssd),
+ .PAD(clock),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_clock),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_clk_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_clk),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(flash_clk_ieb_core),
+ .IN_H(),
+ .OE_N(flash_clk_oeb_core),
+ .OUT(flash_clk_core),
+ .PAD(flash_clk),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_clk),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_csb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_csb),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(flash_csb_ieb_core),
+ .IN_H(),
+ .OE_N(flash_csb_oeb_core),
+ .OUT(flash_csb_core),
+ .PAD(flash_csb),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_csb),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io0_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io0),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io0_di_core),
+ .INP_DIS(flash_io0_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io0_oeb_core),
+ .OUT(flash_io0_do_core),
+ .PAD(flash_io0),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io0),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io1_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io1),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io1_di_core),
+ .INP_DIS(flash_io1_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io1_oeb_core),
+ .OUT(flash_io1_do_core),
+ .PAD(flash_io1),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io1),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped gpio_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ gpio_mode1_core, gpio_mode1_core, gpio_mode0_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_gpio),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(gpio_in_core),
+ .INP_DIS(gpio_inenb_core),
+ .IN_H(),
+ .OE_N(gpio_outenb_core),
+ .OUT(gpio_out_core),
+ .PAD(gpio),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_gpio),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[0] ),
+ .ANALOG_POL(\mprj_io_analog_pol[0] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[0] ),
+ .DM({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .ENABLE_H(\mprj_io_enh[0] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[0] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[0] ),
+ .HLD_OVR(\mprj_io_holdover[0] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[0] ),
+ .IN(\mprj_pads.io_in[0] ),
+ .INP_DIS(\mprj_io_inp_dis[0] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[0] ),
+ .OUT(\mprj_io_out[0] ),
+ .PAD(\mprj_io[0] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[0] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[0] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[0] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[10] ),
+ .ANALOG_POL(\mprj_io_analog_pol[10] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[10] ),
+ .DM({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] }),
+ .ENABLE_H(\mprj_io_enh[10] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[10] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[10] ),
+ .HLD_OVR(\mprj_io_holdover[10] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[10] ),
+ .IN(\mprj_pads.io_in[10] ),
+ .INP_DIS(\mprj_io_inp_dis[10] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[10] ),
+ .OUT(\mprj_io_out[10] ),
+ .PAD(\mprj_io[10] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[10] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[10] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[10] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[11] ),
+ .ANALOG_POL(\mprj_io_analog_pol[11] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[11] ),
+ .DM({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] }),
+ .ENABLE_H(\mprj_io_enh[11] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[11] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[11] ),
+ .HLD_OVR(\mprj_io_holdover[11] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[11] ),
+ .IN(\mprj_pads.io_in[11] ),
+ .INP_DIS(\mprj_io_inp_dis[11] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[11] ),
+ .OUT(\mprj_io_out[11] ),
+ .PAD(\mprj_io[11] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[11] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[11] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[11] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[12] ),
+ .ANALOG_POL(\mprj_io_analog_pol[12] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[12] ),
+ .DM({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] }),
+ .ENABLE_H(\mprj_io_enh[12] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[12] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[12] ),
+ .HLD_OVR(\mprj_io_holdover[12] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[12] ),
+ .IN(\mprj_pads.io_in[12] ),
+ .INP_DIS(\mprj_io_inp_dis[12] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[12] ),
+ .OUT(\mprj_io_out[12] ),
+ .PAD(\mprj_io[12] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[12] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[12] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[12] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[13] ),
+ .ANALOG_POL(\mprj_io_analog_pol[13] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[13] ),
+ .DM({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] }),
+ .ENABLE_H(\mprj_io_enh[13] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[13] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[13] ),
+ .HLD_OVR(\mprj_io_holdover[13] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[13] ),
+ .IN(\mprj_pads.io_in[13] ),
+ .INP_DIS(\mprj_io_inp_dis[13] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[13] ),
+ .OUT(\mprj_io_out[13] ),
+ .PAD(\mprj_io[13] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[13] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[13] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[13] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[14] ),
+ .ANALOG_POL(\mprj_io_analog_pol[14] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[14] ),
+ .DM({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] }),
+ .ENABLE_H(\mprj_io_enh[14] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[14] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[14] ),
+ .HLD_OVR(\mprj_io_holdover[14] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[14] ),
+ .IN(\mprj_pads.io_in[14] ),
+ .INP_DIS(\mprj_io_inp_dis[14] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[14] ),
+ .OUT(\mprj_io_out[14] ),
+ .PAD(\mprj_io[14] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[7] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[14] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[14] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[14] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[15] ),
+ .ANALOG_POL(\mprj_io_analog_pol[15] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[15] ),
+ .DM({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] }),
+ .ENABLE_H(\mprj_io_enh[15] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[15] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[15] ),
+ .HLD_OVR(\mprj_io_holdover[15] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[15] ),
+ .IN(\mprj_pads.io_in[15] ),
+ .INP_DIS(\mprj_io_inp_dis[15] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[15] ),
+ .OUT(\mprj_io_out[15] ),
+ .PAD(\mprj_io[15] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[8] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[15] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[15] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[15] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[16] ),
+ .ANALOG_POL(\mprj_io_analog_pol[16] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[16] ),
+ .DM({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] }),
+ .ENABLE_H(\mprj_io_enh[16] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[16] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[16] ),
+ .HLD_OVR(\mprj_io_holdover[16] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[16] ),
+ .IN(\mprj_pads.io_in[16] ),
+ .INP_DIS(\mprj_io_inp_dis[16] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[16] ),
+ .OUT(\mprj_io_out[16] ),
+ .PAD(\mprj_io[16] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[9] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[16] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[16] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[16] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[17] ),
+ .ANALOG_POL(\mprj_io_analog_pol[17] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[17] ),
+ .DM({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] }),
+ .ENABLE_H(\mprj_io_enh[17] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[17] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[17] ),
+ .HLD_OVR(\mprj_io_holdover[17] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[17] ),
+ .IN(\mprj_pads.io_in[17] ),
+ .INP_DIS(\mprj_io_inp_dis[17] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[17] ),
+ .OUT(\mprj_io_out[17] ),
+ .PAD(\mprj_io[17] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[10] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[17] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[17] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[17] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[1] ),
+ .ANALOG_POL(\mprj_io_analog_pol[1] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[1] ),
+ .DM({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] }),
+ .ENABLE_H(\mprj_io_enh[1] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[1] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[1] ),
+ .HLD_OVR(\mprj_io_holdover[1] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[1] ),
+ .IN(\mprj_pads.io_in[1] ),
+ .INP_DIS(\mprj_io_inp_dis[1] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[1] ),
+ .OUT(\mprj_io_out[1] ),
+ .PAD(\mprj_io[1] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[1] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[1] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[1] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[2] ),
+ .ANALOG_POL(\mprj_io_analog_pol[2] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[2] ),
+ .DM({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] }),
+ .ENABLE_H(\mprj_io_enh[2] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[2] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[2] ),
+ .HLD_OVR(\mprj_io_holdover[2] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[2] ),
+ .IN(\mprj_pads.io_in[2] ),
+ .INP_DIS(\mprj_io_inp_dis[2] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[2] ),
+ .OUT(\mprj_io_out[2] ),
+ .PAD(\mprj_io[2] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[2] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[2] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[2] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[3] ),
+ .ANALOG_POL(\mprj_io_analog_pol[3] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[3] ),
+ .DM({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] }),
+ .ENABLE_H(\mprj_io_enh[3] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[3] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[3] ),
+ .HLD_OVR(\mprj_io_holdover[3] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[3] ),
+ .IN(\mprj_pads.io_in[3] ),
+ .INP_DIS(\mprj_io_inp_dis[3] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[3] ),
+ .OUT(\mprj_io_out[3] ),
+ .PAD(\mprj_io[3] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[3] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[3] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[3] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[4] ),
+ .ANALOG_POL(\mprj_io_analog_pol[4] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[4] ),
+ .DM({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] }),
+ .ENABLE_H(\mprj_io_enh[4] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[4] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[4] ),
+ .HLD_OVR(\mprj_io_holdover[4] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[4] ),
+ .IN(\mprj_pads.io_in[4] ),
+ .INP_DIS(\mprj_io_inp_dis[4] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[4] ),
+ .OUT(\mprj_io_out[4] ),
+ .PAD(\mprj_io[4] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[4] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[4] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[4] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[5] ),
+ .ANALOG_POL(\mprj_io_analog_pol[5] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[5] ),
+ .DM({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] }),
+ .ENABLE_H(\mprj_io_enh[5] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[5] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[5] ),
+ .HLD_OVR(\mprj_io_holdover[5] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[5] ),
+ .IN(\mprj_pads.io_in[5] ),
+ .INP_DIS(\mprj_io_inp_dis[5] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[5] ),
+ .OUT(\mprj_io_out[5] ),
+ .PAD(\mprj_io[5] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[5] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[5] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[5] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[6] ),
+ .ANALOG_POL(\mprj_io_analog_pol[6] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[6] ),
+ .DM({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] }),
+ .ENABLE_H(\mprj_io_enh[6] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[6] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[6] ),
+ .HLD_OVR(\mprj_io_holdover[6] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[6] ),
+ .IN(\mprj_pads.io_in[6] ),
+ .INP_DIS(\mprj_io_inp_dis[6] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[6] ),
+ .OUT(\mprj_io_out[6] ),
+ .PAD(\mprj_io[6] ),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[6] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[6] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[6] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[7] ),
+ .ANALOG_POL(\mprj_io_analog_pol[7] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[7] ),
+ .DM({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] }),
+ .ENABLE_H(\mprj_io_enh[7] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[7] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[7] ),
+ .HLD_OVR(\mprj_io_holdover[7] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[7] ),
+ .IN(\mprj_pads.io_in[7] ),
+ .INP_DIS(\mprj_io_inp_dis[7] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[7] ),
+ .OUT(\mprj_io_out[7] ),
+ .PAD(\mprj_io[7] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[7] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[7] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[7] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[8] ),
+ .ANALOG_POL(\mprj_io_analog_pol[8] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[8] ),
+ .DM({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] }),
+ .ENABLE_H(\mprj_io_enh[8] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[8] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[8] ),
+ .HLD_OVR(\mprj_io_holdover[8] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[8] ),
+ .IN(\mprj_pads.io_in[8] ),
+ .INP_DIS(\mprj_io_inp_dis[8] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[8] ),
+ .OUT(\mprj_io_out[8] ),
+ .PAD(\mprj_io[8] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[8] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[8] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[8] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[9] ),
+ .ANALOG_POL(\mprj_io_analog_pol[9] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[9] ),
+ .DM({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] }),
+ .ENABLE_H(\mprj_io_enh[9] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[9] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[9] ),
+ .HLD_OVR(\mprj_io_holdover[9] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[9] ),
+ .IN(\mprj_pads.io_in[9] ),
+ .INP_DIS(\mprj_io_inp_dis[9] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[9] ),
+ .OUT(\mprj_io_out[9] ),
+ .PAD(\mprj_io[9] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[9] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[9] ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[9] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[18] ),
+ .ANALOG_POL(\mprj_io_analog_pol[18] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[18] ),
+ .DM({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] }),
+ .ENABLE_H(\mprj_io_enh[18] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[18] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[18] ),
+ .HLD_OVR(\mprj_io_holdover[18] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[18] ),
+ .IN(\mprj_pads.io_in[18] ),
+ .INP_DIS(\mprj_io_inp_dis[18] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[18] ),
+ .OUT(\mprj_io_out[18] ),
+ .PAD(\mprj_io[18] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[11] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[18] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[18] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[18] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[28] ),
+ .ANALOG_POL(\mprj_io_analog_pol[28] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[28] ),
+ .DM({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] }),
+ .ENABLE_H(\mprj_io_enh[28] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[28] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[28] ),
+ .HLD_OVR(\mprj_io_holdover[28] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[28] ),
+ .IN(\mprj_pads.io_in[28] ),
+ .INP_DIS(\mprj_io_inp_dis[28] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[28] ),
+ .OUT(\mprj_io_out[28] ),
+ .PAD(\mprj_io[28] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[21] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[28] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[28] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[28] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[29] ),
+ .ANALOG_POL(\mprj_io_analog_pol[29] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[29] ),
+ .DM({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] }),
+ .ENABLE_H(\mprj_io_enh[29] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[29] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[29] ),
+ .HLD_OVR(\mprj_io_holdover[29] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[29] ),
+ .IN(\mprj_pads.io_in[29] ),
+ .INP_DIS(\mprj_io_inp_dis[29] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[29] ),
+ .OUT(\mprj_io_out[29] ),
+ .PAD(\mprj_io[29] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[22] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[29] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[29] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[29] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[30] ),
+ .ANALOG_POL(\mprj_io_analog_pol[30] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[30] ),
+ .DM({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] }),
+ .ENABLE_H(\mprj_io_enh[30] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[30] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[30] ),
+ .HLD_OVR(\mprj_io_holdover[30] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[30] ),
+ .IN(\mprj_pads.io_in[30] ),
+ .INP_DIS(\mprj_io_inp_dis[30] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[30] ),
+ .OUT(\mprj_io_out[30] ),
+ .PAD(\mprj_io[30] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[23] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[30] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[30] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[30] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[31] ),
+ .ANALOG_POL(\mprj_io_analog_pol[31] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[31] ),
+ .DM({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] }),
+ .ENABLE_H(\mprj_io_enh[31] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[31] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[31] ),
+ .HLD_OVR(\mprj_io_holdover[31] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[31] ),
+ .IN(\mprj_pads.io_in[31] ),
+ .INP_DIS(\mprj_io_inp_dis[31] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[31] ),
+ .OUT(\mprj_io_out[31] ),
+ .PAD(\mprj_io[31] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[24] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[31] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[31] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[31] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[32] ),
+ .ANALOG_POL(\mprj_io_analog_pol[32] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[32] ),
+ .DM({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] }),
+ .ENABLE_H(\mprj_io_enh[32] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[32] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[32] ),
+ .HLD_OVR(\mprj_io_holdover[32] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[32] ),
+ .IN(\mprj_pads.io_in[32] ),
+ .INP_DIS(\mprj_io_inp_dis[32] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[32] ),
+ .OUT(\mprj_io_out[32] ),
+ .PAD(\mprj_io[32] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[25] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[32] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[32] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[32] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[33] ),
+ .ANALOG_POL(\mprj_io_analog_pol[33] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[33] ),
+ .DM({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] }),
+ .ENABLE_H(\mprj_io_enh[33] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[33] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[33] ),
+ .HLD_OVR(\mprj_io_holdover[33] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[33] ),
+ .IN(\mprj_pads.io_in[33] ),
+ .INP_DIS(\mprj_io_inp_dis[33] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[33] ),
+ .OUT(\mprj_io_out[33] ),
+ .PAD(\mprj_io[33] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[26] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[33] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[33] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[33] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[34] ),
+ .ANALOG_POL(\mprj_io_analog_pol[34] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[34] ),
+ .DM({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] }),
+ .ENABLE_H(\mprj_io_enh[34] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[34] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[34] ),
+ .HLD_OVR(\mprj_io_holdover[34] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[34] ),
+ .IN(\mprj_pads.io_in[34] ),
+ .INP_DIS(\mprj_io_inp_dis[34] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[34] ),
+ .OUT(\mprj_io_out[34] ),
+ .PAD(\mprj_io[34] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[27] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[34] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[34] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[34] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[35] ),
+ .ANALOG_POL(\mprj_io_analog_pol[35] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[35] ),
+ .DM({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] }),
+ .ENABLE_H(\mprj_io_enh[35] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[35] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[35] ),
+ .HLD_OVR(\mprj_io_holdover[35] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[35] ),
+ .IN(\mprj_pads.io_in[35] ),
+ .INP_DIS(\mprj_io_inp_dis[35] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[35] ),
+ .OUT(\mprj_io_out[35] ),
+ .PAD(\mprj_io[35] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[28] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[35] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[35] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[35] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[18] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[36] ),
+ .ANALOG_POL(\mprj_io_analog_pol[36] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[36] ),
+ .DM({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] }),
+ .ENABLE_H(\mprj_io_enh[36] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[36] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[36] ),
+ .HLD_OVR(\mprj_io_holdover[36] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[36] ),
+ .IN(\mprj_pads.io_in[36] ),
+ .INP_DIS(\mprj_io_inp_dis[36] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[36] ),
+ .OUT(\mprj_io_out[36] ),
+ .PAD(\mprj_io[36] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[29] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[36] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[36] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[36] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[19] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[37] ),
+ .ANALOG_POL(\mprj_io_analog_pol[37] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[37] ),
+ .DM({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] }),
+ .ENABLE_H(\mprj_io_enh[37] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[37] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[37] ),
+ .HLD_OVR(\mprj_io_holdover[37] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[37] ),
+ .IN(\mprj_pads.io_in[37] ),
+ .INP_DIS(\mprj_io_inp_dis[37] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[37] ),
+ .OUT(\mprj_io_out[37] ),
+ .PAD(\mprj_io[37] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[30] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[37] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[37] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[37] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[19] ),
+ .ANALOG_POL(\mprj_io_analog_pol[19] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[19] ),
+ .DM({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] }),
+ .ENABLE_H(\mprj_io_enh[19] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[19] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[19] ),
+ .HLD_OVR(\mprj_io_holdover[19] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[19] ),
+ .IN(\mprj_pads.io_in[19] ),
+ .INP_DIS(\mprj_io_inp_dis[19] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[19] ),
+ .OUT(\mprj_io_out[19] ),
+ .PAD(\mprj_io[19] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[12] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[19] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[19] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[19] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[20] ),
+ .ANALOG_POL(\mprj_io_analog_pol[20] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[20] ),
+ .DM({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] }),
+ .ENABLE_H(\mprj_io_enh[20] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[20] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[20] ),
+ .HLD_OVR(\mprj_io_holdover[20] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[20] ),
+ .IN(\mprj_pads.io_in[20] ),
+ .INP_DIS(\mprj_io_inp_dis[20] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[20] ),
+ .OUT(\mprj_io_out[20] ),
+ .PAD(\mprj_io[20] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[13] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[20] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[20] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[20] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[21] ),
+ .ANALOG_POL(\mprj_io_analog_pol[21] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[21] ),
+ .DM({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] }),
+ .ENABLE_H(\mprj_io_enh[21] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[21] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[21] ),
+ .HLD_OVR(\mprj_io_holdover[21] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[21] ),
+ .IN(\mprj_pads.io_in[21] ),
+ .INP_DIS(\mprj_io_inp_dis[21] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[21] ),
+ .OUT(\mprj_io_out[21] ),
+ .PAD(\mprj_io[21] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[14] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[21] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[21] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[21] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[22] ),
+ .ANALOG_POL(\mprj_io_analog_pol[22] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[22] ),
+ .DM({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] }),
+ .ENABLE_H(\mprj_io_enh[22] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[22] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[22] ),
+ .HLD_OVR(\mprj_io_holdover[22] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[22] ),
+ .IN(\mprj_pads.io_in[22] ),
+ .INP_DIS(\mprj_io_inp_dis[22] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[22] ),
+ .OUT(\mprj_io_out[22] ),
+ .PAD(\mprj_io[22] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[15] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[22] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[22] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[22] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[23] ),
+ .ANALOG_POL(\mprj_io_analog_pol[23] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[23] ),
+ .DM({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] }),
+ .ENABLE_H(\mprj_io_enh[23] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[23] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[23] ),
+ .HLD_OVR(\mprj_io_holdover[23] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[23] ),
+ .IN(\mprj_pads.io_in[23] ),
+ .INP_DIS(\mprj_io_inp_dis[23] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[23] ),
+ .OUT(\mprj_io_out[23] ),
+ .PAD(\mprj_io[23] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[16] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[23] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[23] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[23] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[24] ),
+ .ANALOG_POL(\mprj_io_analog_pol[24] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[24] ),
+ .DM({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] }),
+ .ENABLE_H(\mprj_io_enh[24] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[24] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[24] ),
+ .HLD_OVR(\mprj_io_holdover[24] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[24] ),
+ .IN(\mprj_pads.io_in[24] ),
+ .INP_DIS(\mprj_io_inp_dis[24] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[24] ),
+ .OUT(\mprj_io_out[24] ),
+ .PAD(\mprj_io[24] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[17] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[24] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[24] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[24] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[25] ),
+ .ANALOG_POL(\mprj_io_analog_pol[25] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[25] ),
+ .DM({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] }),
+ .ENABLE_H(\mprj_io_enh[25] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[25] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[25] ),
+ .HLD_OVR(\mprj_io_holdover[25] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[25] ),
+ .IN(\mprj_pads.io_in[25] ),
+ .INP_DIS(\mprj_io_inp_dis[25] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[25] ),
+ .OUT(\mprj_io_out[25] ),
+ .PAD(\mprj_io[25] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[18] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[25] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[25] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[25] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[26] ),
+ .ANALOG_POL(\mprj_io_analog_pol[26] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[26] ),
+ .DM({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] }),
+ .ENABLE_H(\mprj_io_enh[26] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[26] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[26] ),
+ .HLD_OVR(\mprj_io_holdover[26] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[26] ),
+ .IN(\mprj_pads.io_in[26] ),
+ .INP_DIS(\mprj_io_inp_dis[26] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[26] ),
+ .OUT(\mprj_io_out[26] ),
+ .PAD(\mprj_io[26] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[19] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[26] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[26] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[26] )
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(\mprj_io_analog_en[27] ),
+ .ANALOG_POL(\mprj_io_analog_pol[27] ),
+ .ANALOG_SEL(\mprj_io_analog_sel[27] ),
+ .DM({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] }),
+ .ENABLE_H(\mprj_io_enh[27] ),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[27] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(\mprj_io_hldh_n[27] ),
+ .HLD_OVR(\mprj_io_holdover[27] ),
+ .IB_MODE_SEL(\mprj_io_ib_mode_sel[27] ),
+ .IN(\mprj_pads.io_in[27] ),
+ .INP_DIS(\mprj_io_inp_dis[27] ),
+ .IN_H(),
+ .OE_N(\mprj_io_oeb[27] ),
+ .OUT(\mprj_io_out[27] ),
+ .PAD(\mprj_io[27] ),
+ .PAD_A_ESD_0_H(\mprj_analog_io[20] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(\mprj_io_slow_sel[27] ),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[27] ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(\mprj_io_vtrip_sel[27] )
+ );
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DISABLE_PULLUP_H(vssio),
+ .ENABLE_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .EN_VDDIO_SIG_H(vssio),
+ .FILT_IN_H(vssio),
+ .INP_SEL_H(vssio),
+ .PAD(resetb),
+ .PAD_A_ESD_H(xresloop),
+ .PULLUP_H(vssio),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .TIE_WEAK_HI_H(xresloop),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .XRES_H_N(resetb_core_h)
+ );
+ sky130_ef_io__corner_pad user1_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad user2_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclmap_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ assign \mprj_pads.slow_sel[19] = \mprj_io_slow_sel[19] ;
+ assign \mprj_pads.slow_sel[18] = \mprj_io_slow_sel[18] ;
+ assign \mprj_pads.slow_sel[17] = \mprj_io_slow_sel[17] ;
+ assign \mprj_pads.slow_sel[16] = \mprj_io_slow_sel[16] ;
+ assign \mprj_pads.slow_sel[15] = \mprj_io_slow_sel[15] ;
+ assign \mprj_pads.slow_sel[14] = \mprj_io_slow_sel[14] ;
+ assign \mprj_pads.slow_sel[13] = \mprj_io_slow_sel[13] ;
+ assign \mprj_pads.slow_sel[12] = \mprj_io_slow_sel[12] ;
+ assign \mprj_pads.slow_sel[11] = \mprj_io_slow_sel[11] ;
+ assign \mprj_pads.slow_sel[10] = \mprj_io_slow_sel[10] ;
+ assign \mprj_pads.slow_sel[9] = \mprj_io_slow_sel[9] ;
+ assign \mprj_pads.slow_sel[8] = \mprj_io_slow_sel[8] ;
+ assign \mprj_pads.slow_sel[7] = \mprj_io_slow_sel[7] ;
+ assign \mprj_pads.slow_sel[6] = \mprj_io_slow_sel[6] ;
+ assign \mprj_pads.slow_sel[5] = \mprj_io_slow_sel[5] ;
+ assign \mprj_pads.slow_sel[4] = \mprj_io_slow_sel[4] ;
+ assign \mprj_pads.slow_sel[3] = \mprj_io_slow_sel[3] ;
+ assign \mprj_pads.slow_sel[2] = \mprj_io_slow_sel[2] ;
+ assign \mprj_pads.slow_sel[1] = \mprj_io_slow_sel[1] ;
+ assign \mprj_pads.slow_sel[0] = \mprj_io_slow_sel[0] ;
+ assign \mprj_pads.enh[37] = \mprj_io_enh[37] ;
+ assign \mprj_pads.enh[36] = \mprj_io_enh[36] ;
+ assign \mprj_pads.enh[35] = \mprj_io_enh[35] ;
+ assign \mprj_pads.enh[34] = \mprj_io_enh[34] ;
+ assign \mprj_pads.enh[33] = \mprj_io_enh[33] ;
+ assign \mprj_pads.enh[32] = \mprj_io_enh[32] ;
+ assign \mprj_pads.enh[31] = \mprj_io_enh[31] ;
+ assign \mprj_pads.enh[30] = \mprj_io_enh[30] ;
+ assign \mprj_pads.enh[29] = \mprj_io_enh[29] ;
+ assign \mprj_pads.enh[28] = \mprj_io_enh[28] ;
+ assign \mprj_pads.enh[27] = \mprj_io_enh[27] ;
+ assign \mprj_pads.enh[26] = \mprj_io_enh[26] ;
+ assign \mprj_pads.enh[25] = \mprj_io_enh[25] ;
+ assign \mprj_pads.enh[24] = \mprj_io_enh[24] ;
+ assign \mprj_pads.enh[23] = \mprj_io_enh[23] ;
+ assign \mprj_pads.enh[22] = \mprj_io_enh[22] ;
+ assign \mprj_pads.enh[21] = \mprj_io_enh[21] ;
+ assign \mprj_pads.enh[20] = \mprj_io_enh[20] ;
+ assign \mprj_pads.enh[19] = \mprj_io_enh[19] ;
+ assign \mprj_pads.enh[18] = \mprj_io_enh[18] ;
+ assign \mprj_pads.enh[17] = \mprj_io_enh[17] ;
+ assign \mprj_pads.enh[16] = \mprj_io_enh[16] ;
+ assign \mprj_pads.enh[15] = \mprj_io_enh[15] ;
+ assign \mprj_pads.enh[14] = \mprj_io_enh[14] ;
+ assign \mprj_pads.enh[13] = \mprj_io_enh[13] ;
+ assign \mprj_pads.enh[12] = \mprj_io_enh[12] ;
+ assign \mprj_pads.enh[11] = \mprj_io_enh[11] ;
+ assign \mprj_pads.enh[10] = \mprj_io_enh[10] ;
+ assign \mprj_pads.enh[9] = \mprj_io_enh[9] ;
+ assign \mprj_pads.enh[8] = \mprj_io_enh[8] ;
+ assign \mprj_pads.enh[7] = \mprj_io_enh[7] ;
+ assign \mprj_pads.enh[6] = \mprj_io_enh[6] ;
+ assign \mprj_pads.enh[5] = \mprj_io_enh[5] ;
+ assign \mprj_pads.enh[4] = \mprj_io_enh[4] ;
+ assign \mprj_pads.enh[3] = \mprj_io_enh[3] ;
+ assign \mprj_pads.enh[2] = \mprj_io_enh[2] ;
+ assign \mprj_pads.enh[1] = \mprj_io_enh[1] ;
+ assign \mprj_pads.enh[0] = \mprj_io_enh[0] ;
+ assign \mprj_pads.hldh_n[37] = \mprj_io_hldh_n[37] ;
+ assign \mprj_pads.hldh_n[36] = \mprj_io_hldh_n[36] ;
+ assign \mprj_pads.hldh_n[35] = \mprj_io_hldh_n[35] ;
+ assign \mprj_pads.hldh_n[34] = \mprj_io_hldh_n[34] ;
+ assign \mprj_pads.hldh_n[33] = \mprj_io_hldh_n[33] ;
+ assign \mprj_pads.hldh_n[32] = \mprj_io_hldh_n[32] ;
+ assign \mprj_pads.hldh_n[31] = \mprj_io_hldh_n[31] ;
+ assign \mprj_pads.hldh_n[30] = \mprj_io_hldh_n[30] ;
+ assign \mprj_pads.hldh_n[29] = \mprj_io_hldh_n[29] ;
+ assign \mprj_pads.hldh_n[28] = \mprj_io_hldh_n[28] ;
+ assign \mprj_pads.hldh_n[27] = \mprj_io_hldh_n[27] ;
+ assign \mprj_pads.hldh_n[26] = \mprj_io_hldh_n[26] ;
+ assign \mprj_pads.hldh_n[25] = \mprj_io_hldh_n[25] ;
+ assign \mprj_pads.hldh_n[24] = \mprj_io_hldh_n[24] ;
+ assign \mprj_pads.hldh_n[23] = \mprj_io_hldh_n[23] ;
+ assign \mprj_pads.hldh_n[22] = \mprj_io_hldh_n[22] ;
+ assign \mprj_pads.hldh_n[21] = \mprj_io_hldh_n[21] ;
+ assign \mprj_pads.hldh_n[20] = \mprj_io_hldh_n[20] ;
+ assign \mprj_pads.hldh_n[19] = \mprj_io_hldh_n[19] ;
+ assign \mprj_pads.hldh_n[18] = \mprj_io_hldh_n[18] ;
+ assign \mprj_pads.hldh_n[17] = \mprj_io_hldh_n[17] ;
+ assign \mprj_pads.hldh_n[16] = \mprj_io_hldh_n[16] ;
+ assign \mprj_pads.hldh_n[15] = \mprj_io_hldh_n[15] ;
+ assign \mprj_pads.hldh_n[14] = \mprj_io_hldh_n[14] ;
+ assign \mprj_pads.hldh_n[13] = \mprj_io_hldh_n[13] ;
+ assign \mprj_pads.hldh_n[12] = \mprj_io_hldh_n[12] ;
+ assign \mprj_pads.hldh_n[11] = \mprj_io_hldh_n[11] ;
+ assign \mprj_pads.hldh_n[10] = \mprj_io_hldh_n[10] ;
+ assign \mprj_pads.hldh_n[9] = \mprj_io_hldh_n[9] ;
+ assign \mprj_pads.hldh_n[8] = \mprj_io_hldh_n[8] ;
+ assign \mprj_pads.hldh_n[7] = \mprj_io_hldh_n[7] ;
+ assign \mprj_pads.hldh_n[6] = \mprj_io_hldh_n[6] ;
+ assign \mprj_pads.hldh_n[5] = \mprj_io_hldh_n[5] ;
+ assign \mprj_pads.hldh_n[4] = \mprj_io_hldh_n[4] ;
+ assign \mprj_pads.hldh_n[3] = \mprj_io_hldh_n[3] ;
+ assign \mprj_pads.hldh_n[2] = \mprj_io_hldh_n[2] ;
+ assign \mprj_pads.hldh_n[1] = \mprj_io_hldh_n[1] ;
+ assign \mprj_pads.hldh_n[0] = \mprj_io_hldh_n[0] ;
+ assign \mprj_pads.io[37] = \mprj_io[37] ;
+ assign \mprj_pads.io[36] = \mprj_io[36] ;
+ assign \mprj_pads.io[35] = \mprj_io[35] ;
+ assign \mprj_pads.io[34] = \mprj_io[34] ;
+ assign \mprj_pads.io[33] = \mprj_io[33] ;
+ assign \mprj_pads.io[32] = \mprj_io[32] ;
+ assign \mprj_pads.io[31] = \mprj_io[31] ;
+ assign \mprj_pads.io[30] = \mprj_io[30] ;
+ assign \mprj_pads.io[29] = \mprj_io[29] ;
+ assign \mprj_pads.io[28] = \mprj_io[28] ;
+ assign \mprj_pads.io[27] = \mprj_io[27] ;
+ assign \mprj_pads.io[26] = \mprj_io[26] ;
+ assign \mprj_pads.io[25] = \mprj_io[25] ;
+ assign \mprj_pads.io[24] = \mprj_io[24] ;
+ assign \mprj_pads.io[23] = \mprj_io[23] ;
+ assign \mprj_pads.io[22] = \mprj_io[22] ;
+ assign \mprj_pads.io[21] = \mprj_io[21] ;
+ assign \mprj_pads.io[20] = \mprj_io[20] ;
+ assign \mprj_pads.io[19] = \mprj_io[19] ;
+ assign \mprj_pads.io[18] = \mprj_io[18] ;
+ assign \mprj_pads.io[17] = \mprj_io[17] ;
+ assign \mprj_pads.io[16] = \mprj_io[16] ;
+ assign \mprj_pads.io[15] = \mprj_io[15] ;
+ assign \mprj_pads.io[14] = \mprj_io[14] ;
+ assign \mprj_pads.io[13] = \mprj_io[13] ;
+ assign \mprj_pads.io[12] = \mprj_io[12] ;
+ assign \mprj_pads.io[11] = \mprj_io[11] ;
+ assign \mprj_pads.io[10] = \mprj_io[10] ;
+ assign \mprj_pads.io[9] = \mprj_io[9] ;
+ assign \mprj_pads.io[8] = \mprj_io[8] ;
+ assign \mprj_pads.io[7] = \mprj_io[7] ;
+ assign \mprj_pads.io[6] = \mprj_io[6] ;
+ assign \mprj_pads.io[5] = \mprj_io[5] ;
+ assign \mprj_pads.io[4] = \mprj_io[4] ;
+ assign \mprj_pads.io[3] = \mprj_io[3] ;
+ assign \mprj_pads.io[2] = \mprj_io[2] ;
+ assign \mprj_pads.io[1] = \mprj_io[1] ;
+ assign \mprj_pads.io[0] = \mprj_io[0] ;
+ assign \mprj_pads.analog_io[30] = \mprj_analog_io[30] ;
+ assign \mprj_pads.analog_io[29] = \mprj_analog_io[29] ;
+ assign \mprj_pads.analog_io[28] = \mprj_analog_io[28] ;
+ assign \mprj_pads.analog_io[27] = \mprj_analog_io[27] ;
+ assign \mprj_pads.analog_io[26] = \mprj_analog_io[26] ;
+ assign \mprj_pads.analog_io[25] = \mprj_analog_io[25] ;
+ assign \mprj_pads.analog_io[24] = \mprj_analog_io[24] ;
+ assign \mprj_pads.analog_io[23] = \mprj_analog_io[23] ;
+ assign \mprj_pads.analog_io[22] = \mprj_analog_io[22] ;
+ assign \mprj_pads.analog_io[21] = \mprj_analog_io[21] ;
+ assign \mprj_pads.analog_io[20] = \mprj_analog_io[20] ;
+ assign \mprj_pads.analog_io[19] = \mprj_analog_io[19] ;
+ assign \mprj_pads.analog_io[18] = \mprj_analog_io[18] ;
+ assign \mprj_pads.analog_io[17] = \mprj_analog_io[17] ;
+ assign \mprj_pads.analog_io[16] = \mprj_analog_io[16] ;
+ assign \mprj_pads.analog_io[15] = \mprj_analog_io[15] ;
+ assign \mprj_pads.analog_io[14] = \mprj_analog_io[14] ;
+ assign \mprj_pads.analog_io[13] = \mprj_analog_io[13] ;
+ assign \mprj_pads.analog_io[12] = \mprj_analog_io[12] ;
+ assign \mprj_pads.analog_io[11] = \mprj_analog_io[11] ;
+ assign \mprj_pads.analog_io[10] = \mprj_analog_io[10] ;
+ assign \mprj_pads.analog_io[9] = \mprj_analog_io[9] ;
+ assign \mprj_pads.analog_io[8] = \mprj_analog_io[8] ;
+ assign \mprj_pads.analog_io[7] = \mprj_analog_io[7] ;
+ assign \mprj_pads.analog_io[6] = \mprj_analog_io[6] ;
+ assign \mprj_pads.analog_io[5] = \mprj_analog_io[5] ;
+ assign \mprj_pads.analog_io[4] = \mprj_analog_io[4] ;
+ assign \mprj_pads.analog_io[3] = \mprj_analog_io[3] ;
+ assign \mprj_pads.analog_io[2] = \mprj_analog_io[2] ;
+ assign \mprj_pads.analog_io[1] = \mprj_analog_io[1] ;
+ assign \mprj_pads.analog_io[0] = \mprj_analog_io[0] ;
+ assign \flash_io1_mode[2] = flash_io1_ieb_core;
+ assign \flash_io1_mode[1] = flash_io1_ieb_core;
+ assign \flash_io1_mode[0] = flash_io1_oeb_core;
+ assign \dm_all[2] = gpio_mode1_core;
+ assign \dm_all[1] = gpio_mode1_core;
+ assign \dm_all[0] = gpio_mode0_core;
+ assign \mprj_pads.analog_sel[37] = \mprj_io_analog_sel[37] ;
+ assign \mprj_pads.analog_sel[36] = \mprj_io_analog_sel[36] ;
+ assign \mprj_pads.analog_sel[35] = \mprj_io_analog_sel[35] ;
+ assign \mprj_pads.analog_sel[34] = \mprj_io_analog_sel[34] ;
+ assign \mprj_pads.analog_sel[33] = \mprj_io_analog_sel[33] ;
+ assign \mprj_pads.analog_sel[32] = \mprj_io_analog_sel[32] ;
+ assign \mprj_pads.analog_sel[31] = \mprj_io_analog_sel[31] ;
+ assign \mprj_pads.analog_sel[30] = \mprj_io_analog_sel[30] ;
+ assign \mprj_pads.analog_sel[29] = \mprj_io_analog_sel[29] ;
+ assign \mprj_pads.analog_sel[28] = \mprj_io_analog_sel[28] ;
+ assign \mprj_pads.analog_sel[27] = \mprj_io_analog_sel[27] ;
+ assign \mprj_pads.analog_sel[26] = \mprj_io_analog_sel[26] ;
+ assign \mprj_pads.analog_sel[25] = \mprj_io_analog_sel[25] ;
+ assign \mprj_pads.analog_sel[24] = \mprj_io_analog_sel[24] ;
+ assign \mprj_pads.analog_sel[23] = \mprj_io_analog_sel[23] ;
+ assign \mprj_pads.analog_sel[22] = \mprj_io_analog_sel[22] ;
+ assign \mprj_pads.analog_sel[21] = \mprj_io_analog_sel[21] ;
+ assign \mprj_pads.analog_sel[20] = \mprj_io_analog_sel[20] ;
+ assign \mprj_pads.analog_sel[19] = \mprj_io_analog_sel[19] ;
+ assign \mprj_pads.analog_sel[18] = \mprj_io_analog_sel[18] ;
+ assign \mprj_pads.analog_sel[17] = \mprj_io_analog_sel[17] ;
+ assign \mprj_pads.analog_sel[16] = \mprj_io_analog_sel[16] ;
+ assign \mprj_pads.analog_sel[15] = \mprj_io_analog_sel[15] ;
+ assign \mprj_pads.analog_sel[14] = \mprj_io_analog_sel[14] ;
+ assign \mprj_pads.analog_sel[13] = \mprj_io_analog_sel[13] ;
+ assign \mprj_pads.analog_sel[12] = \mprj_io_analog_sel[12] ;
+ assign \mprj_pads.analog_sel[11] = \mprj_io_analog_sel[11] ;
+ assign \mprj_pads.analog_sel[10] = \mprj_io_analog_sel[10] ;
+ assign \mprj_pads.analog_sel[9] = \mprj_io_analog_sel[9] ;
+ assign \mprj_pads.analog_sel[8] = \mprj_io_analog_sel[8] ;
+ assign \mprj_pads.analog_sel[7] = \mprj_io_analog_sel[7] ;
+ assign \mprj_pads.analog_sel[6] = \mprj_io_analog_sel[6] ;
+ assign \mprj_pads.analog_sel[5] = \mprj_io_analog_sel[5] ;
+ assign \mprj_pads.analog_sel[4] = \mprj_io_analog_sel[4] ;
+ assign \mprj_pads.analog_sel[3] = \mprj_io_analog_sel[3] ;
+ assign \mprj_pads.analog_sel[2] = \mprj_io_analog_sel[2] ;
+ assign \mprj_pads.analog_sel[1] = \mprj_io_analog_sel[1] ;
+ assign \mprj_pads.analog_sel[0] = \mprj_io_analog_sel[0] ;
+ assign \mprj_pads.vtrip_sel[37] = \mprj_io_vtrip_sel[37] ;
+ assign \mprj_pads.vtrip_sel[36] = \mprj_io_vtrip_sel[36] ;
+ assign \mprj_pads.vtrip_sel[35] = \mprj_io_vtrip_sel[35] ;
+ assign \mprj_pads.vtrip_sel[34] = \mprj_io_vtrip_sel[34] ;
+ assign \mprj_pads.vtrip_sel[33] = \mprj_io_vtrip_sel[33] ;
+ assign \mprj_pads.vtrip_sel[32] = \mprj_io_vtrip_sel[32] ;
+ assign \mprj_pads.vtrip_sel[31] = \mprj_io_vtrip_sel[31] ;
+ assign \mprj_pads.vtrip_sel[30] = \mprj_io_vtrip_sel[30] ;
+ assign \mprj_pads.vtrip_sel[29] = \mprj_io_vtrip_sel[29] ;
+ assign \mprj_pads.vtrip_sel[28] = \mprj_io_vtrip_sel[28] ;
+ assign \mprj_pads.vtrip_sel[27] = \mprj_io_vtrip_sel[27] ;
+ assign \mprj_pads.vtrip_sel[26] = \mprj_io_vtrip_sel[26] ;
+ assign \mprj_pads.vtrip_sel[25] = \mprj_io_vtrip_sel[25] ;
+ assign \mprj_pads.vtrip_sel[24] = \mprj_io_vtrip_sel[24] ;
+ assign \mprj_pads.vtrip_sel[23] = \mprj_io_vtrip_sel[23] ;
+ assign \mprj_pads.vtrip_sel[22] = \mprj_io_vtrip_sel[22] ;
+ assign \mprj_pads.vtrip_sel[21] = \mprj_io_vtrip_sel[21] ;
+ assign \mprj_pads.vtrip_sel[20] = \mprj_io_vtrip_sel[20] ;
+ assign \mprj_pads.vtrip_sel[19] = \mprj_io_vtrip_sel[19] ;
+ assign \mprj_pads.vtrip_sel[18] = \mprj_io_vtrip_sel[18] ;
+ assign \mprj_pads.vtrip_sel[17] = \mprj_io_vtrip_sel[17] ;
+ assign \mprj_pads.vtrip_sel[16] = \mprj_io_vtrip_sel[16] ;
+ assign \mprj_pads.vtrip_sel[15] = \mprj_io_vtrip_sel[15] ;
+ assign \mprj_pads.vtrip_sel[14] = \mprj_io_vtrip_sel[14] ;
+ assign \mprj_pads.vtrip_sel[13] = \mprj_io_vtrip_sel[13] ;
+ assign \mprj_pads.vtrip_sel[12] = \mprj_io_vtrip_sel[12] ;
+ assign \mprj_pads.vtrip_sel[11] = \mprj_io_vtrip_sel[11] ;
+ assign \mprj_pads.vtrip_sel[10] = \mprj_io_vtrip_sel[10] ;
+ assign \mprj_pads.vtrip_sel[9] = \mprj_io_vtrip_sel[9] ;
+ assign \mprj_pads.vtrip_sel[8] = \mprj_io_vtrip_sel[8] ;
+ assign \mprj_pads.vtrip_sel[7] = \mprj_io_vtrip_sel[7] ;
+ assign \mprj_pads.vtrip_sel[6] = \mprj_io_vtrip_sel[6] ;
+ assign \mprj_pads.vtrip_sel[5] = \mprj_io_vtrip_sel[5] ;
+ assign \mprj_pads.vtrip_sel[4] = \mprj_io_vtrip_sel[4] ;
+ assign \mprj_pads.vtrip_sel[3] = \mprj_io_vtrip_sel[3] ;
+ assign \mprj_pads.vtrip_sel[2] = \mprj_io_vtrip_sel[2] ;
+ assign \mprj_pads.vtrip_sel[1] = \mprj_io_vtrip_sel[1] ;
+ assign \mprj_pads.vtrip_sel[0] = \mprj_io_vtrip_sel[0] ;
+ assign \mprj_pads.analog_pol[37] = \mprj_io_analog_pol[37] ;
+ assign \mprj_pads.analog_pol[36] = \mprj_io_analog_pol[36] ;
+ assign \mprj_pads.analog_pol[35] = \mprj_io_analog_pol[35] ;
+ assign \mprj_pads.analog_pol[34] = \mprj_io_analog_pol[34] ;
+ assign \mprj_pads.analog_pol[33] = \mprj_io_analog_pol[33] ;
+ assign \mprj_pads.analog_pol[32] = \mprj_io_analog_pol[32] ;
+ assign \mprj_pads.analog_pol[31] = \mprj_io_analog_pol[31] ;
+ assign \mprj_pads.analog_pol[30] = \mprj_io_analog_pol[30] ;
+ assign \mprj_pads.analog_pol[29] = \mprj_io_analog_pol[29] ;
+ assign \mprj_pads.analog_pol[28] = \mprj_io_analog_pol[28] ;
+ assign \mprj_pads.analog_pol[27] = \mprj_io_analog_pol[27] ;
+ assign \mprj_pads.analog_pol[26] = \mprj_io_analog_pol[26] ;
+ assign \mprj_pads.analog_pol[25] = \mprj_io_analog_pol[25] ;
+ assign \mprj_pads.analog_pol[24] = \mprj_io_analog_pol[24] ;
+ assign \mprj_pads.analog_pol[23] = \mprj_io_analog_pol[23] ;
+ assign \mprj_pads.analog_pol[22] = \mprj_io_analog_pol[22] ;
+ assign \mprj_pads.analog_pol[21] = \mprj_io_analog_pol[21] ;
+ assign \mprj_pads.analog_pol[20] = \mprj_io_analog_pol[20] ;
+ assign \mprj_pads.analog_pol[19] = \mprj_io_analog_pol[19] ;
+ assign \mprj_pads.analog_pol[18] = \mprj_io_analog_pol[18] ;
+ assign \mprj_pads.analog_pol[17] = \mprj_io_analog_pol[17] ;
+ assign \mprj_pads.analog_pol[16] = \mprj_io_analog_pol[16] ;
+ assign \mprj_pads.analog_pol[15] = \mprj_io_analog_pol[15] ;
+ assign \mprj_pads.analog_pol[14] = \mprj_io_analog_pol[14] ;
+ assign \mprj_pads.analog_pol[13] = \mprj_io_analog_pol[13] ;
+ assign \mprj_pads.analog_pol[12] = \mprj_io_analog_pol[12] ;
+ assign \mprj_pads.analog_pol[11] = \mprj_io_analog_pol[11] ;
+ assign \mprj_pads.analog_pol[10] = \mprj_io_analog_pol[10] ;
+ assign \mprj_pads.analog_pol[9] = \mprj_io_analog_pol[9] ;
+ assign \mprj_pads.analog_pol[8] = \mprj_io_analog_pol[8] ;
+ assign \mprj_pads.analog_pol[7] = \mprj_io_analog_pol[7] ;
+ assign \mprj_pads.analog_pol[6] = \mprj_io_analog_pol[6] ;
+ assign \mprj_pads.analog_pol[5] = \mprj_io_analog_pol[5] ;
+ assign \mprj_pads.analog_pol[4] = \mprj_io_analog_pol[4] ;
+ assign \mprj_pads.analog_pol[3] = \mprj_io_analog_pol[3] ;
+ assign \mprj_pads.analog_pol[2] = \mprj_io_analog_pol[2] ;
+ assign \mprj_pads.analog_pol[1] = \mprj_io_analog_pol[1] ;
+ assign \mprj_pads.analog_pol[0] = \mprj_io_analog_pol[0] ;
+ assign \mprj_pads.oeb[37] = \mprj_io_oeb[37] ;
+ assign \mprj_pads.oeb[36] = \mprj_io_oeb[36] ;
+ assign \mprj_pads.oeb[35] = \mprj_io_oeb[35] ;
+ assign \mprj_pads.oeb[34] = \mprj_io_oeb[34] ;
+ assign \mprj_pads.oeb[33] = \mprj_io_oeb[33] ;
+ assign \mprj_pads.oeb[32] = \mprj_io_oeb[32] ;
+ assign \mprj_pads.oeb[31] = \mprj_io_oeb[31] ;
+ assign \mprj_pads.oeb[30] = \mprj_io_oeb[30] ;
+ assign \mprj_pads.oeb[29] = \mprj_io_oeb[29] ;
+ assign \mprj_pads.oeb[28] = \mprj_io_oeb[28] ;
+ assign \mprj_pads.oeb[27] = \mprj_io_oeb[27] ;
+ assign \mprj_pads.oeb[26] = \mprj_io_oeb[26] ;
+ assign \mprj_pads.oeb[25] = \mprj_io_oeb[25] ;
+ assign \mprj_pads.oeb[24] = \mprj_io_oeb[24] ;
+ assign \mprj_pads.oeb[23] = \mprj_io_oeb[23] ;
+ assign \mprj_pads.oeb[22] = \mprj_io_oeb[22] ;
+ assign \mprj_pads.oeb[21] = \mprj_io_oeb[21] ;
+ assign \mprj_pads.oeb[20] = \mprj_io_oeb[20] ;
+ assign \mprj_pads.oeb[19] = \mprj_io_oeb[19] ;
+ assign \mprj_pads.oeb[18] = \mprj_io_oeb[18] ;
+ assign \mprj_pads.oeb[17] = \mprj_io_oeb[17] ;
+ assign \mprj_pads.oeb[16] = \mprj_io_oeb[16] ;
+ assign \mprj_pads.oeb[15] = \mprj_io_oeb[15] ;
+ assign \mprj_pads.oeb[14] = \mprj_io_oeb[14] ;
+ assign \mprj_pads.oeb[13] = \mprj_io_oeb[13] ;
+ assign \mprj_pads.oeb[12] = \mprj_io_oeb[12] ;
+ assign \mprj_pads.oeb[11] = \mprj_io_oeb[11] ;
+ assign \mprj_pads.oeb[10] = \mprj_io_oeb[10] ;
+ assign \mprj_pads.oeb[9] = \mprj_io_oeb[9] ;
+ assign \mprj_pads.oeb[8] = \mprj_io_oeb[8] ;
+ assign \mprj_pads.oeb[7] = \mprj_io_oeb[7] ;
+ assign \mprj_pads.oeb[6] = \mprj_io_oeb[6] ;
+ assign \mprj_pads.oeb[5] = \mprj_io_oeb[5] ;
+ assign \mprj_pads.oeb[4] = \mprj_io_oeb[4] ;
+ assign \mprj_pads.oeb[3] = \mprj_io_oeb[3] ;
+ assign \mprj_pads.oeb[2] = \mprj_io_oeb[2] ;
+ assign \mprj_pads.oeb[1] = \mprj_io_oeb[1] ;
+ assign \mprj_pads.oeb[0] = \mprj_io_oeb[0] ;
+ assign \mprj_pads.analog_en[37] = \mprj_io_analog_en[37] ;
+ assign \mprj_pads.analog_en[36] = \mprj_io_analog_en[36] ;
+ assign \mprj_pads.analog_en[35] = \mprj_io_analog_en[35] ;
+ assign \mprj_pads.analog_en[34] = \mprj_io_analog_en[34] ;
+ assign \mprj_pads.analog_en[33] = \mprj_io_analog_en[33] ;
+ assign \mprj_pads.analog_en[32] = \mprj_io_analog_en[32] ;
+ assign \mprj_pads.analog_en[31] = \mprj_io_analog_en[31] ;
+ assign \mprj_pads.analog_en[30] = \mprj_io_analog_en[30] ;
+ assign \mprj_pads.analog_en[29] = \mprj_io_analog_en[29] ;
+ assign \mprj_pads.analog_en[28] = \mprj_io_analog_en[28] ;
+ assign \mprj_pads.analog_en[27] = \mprj_io_analog_en[27] ;
+ assign \mprj_pads.analog_en[26] = \mprj_io_analog_en[26] ;
+ assign \mprj_pads.analog_en[25] = \mprj_io_analog_en[25] ;
+ assign \mprj_pads.analog_en[24] = \mprj_io_analog_en[24] ;
+ assign \mprj_pads.analog_en[23] = \mprj_io_analog_en[23] ;
+ assign \mprj_pads.analog_en[22] = \mprj_io_analog_en[22] ;
+ assign \mprj_pads.analog_en[21] = \mprj_io_analog_en[21] ;
+ assign \mprj_pads.analog_en[20] = \mprj_io_analog_en[20] ;
+ assign \mprj_pads.analog_en[19] = \mprj_io_analog_en[19] ;
+ assign \mprj_pads.analog_en[18] = \mprj_io_analog_en[18] ;
+ assign \mprj_pads.analog_en[17] = \mprj_io_analog_en[17] ;
+ assign \mprj_pads.analog_en[16] = \mprj_io_analog_en[16] ;
+ assign \mprj_pads.analog_en[15] = \mprj_io_analog_en[15] ;
+ assign \mprj_pads.analog_en[14] = \mprj_io_analog_en[14] ;
+ assign \mprj_pads.analog_en[13] = \mprj_io_analog_en[13] ;
+ assign \mprj_pads.analog_en[12] = \mprj_io_analog_en[12] ;
+ assign \mprj_pads.analog_en[11] = \mprj_io_analog_en[11] ;
+ assign \mprj_pads.analog_en[10] = \mprj_io_analog_en[10] ;
+ assign \mprj_pads.analog_en[9] = \mprj_io_analog_en[9] ;
+ assign \mprj_pads.analog_en[8] = \mprj_io_analog_en[8] ;
+ assign \mprj_pads.analog_en[7] = \mprj_io_analog_en[7] ;
+ assign \mprj_pads.analog_en[6] = \mprj_io_analog_en[6] ;
+ assign \mprj_pads.analog_en[5] = \mprj_io_analog_en[5] ;
+ assign \mprj_pads.analog_en[4] = \mprj_io_analog_en[4] ;
+ assign \mprj_pads.analog_en[3] = \mprj_io_analog_en[3] ;
+ assign \mprj_pads.analog_en[2] = \mprj_io_analog_en[2] ;
+ assign \mprj_pads.analog_en[1] = \mprj_io_analog_en[1] ;
+ assign \mprj_pads.analog_en[0] = \mprj_io_analog_en[0] ;
+ assign \mprj_pads.dm[113] = \mprj_io_dm[113] ;
+ assign \mprj_pads.dm[112] = \mprj_io_dm[112] ;
+ assign \mprj_pads.dm[111] = \mprj_io_dm[111] ;
+ assign \mprj_pads.dm[110] = \mprj_io_dm[110] ;
+ assign \mprj_pads.dm[109] = \mprj_io_dm[109] ;
+ assign \mprj_pads.dm[108] = \mprj_io_dm[108] ;
+ assign \mprj_pads.dm[107] = \mprj_io_dm[107] ;
+ assign \mprj_pads.dm[106] = \mprj_io_dm[106] ;
+ assign \mprj_pads.dm[105] = \mprj_io_dm[105] ;
+ assign \mprj_pads.dm[104] = \mprj_io_dm[104] ;
+ assign \mprj_pads.dm[103] = \mprj_io_dm[103] ;
+ assign \mprj_pads.dm[102] = \mprj_io_dm[102] ;
+ assign \mprj_pads.dm[101] = \mprj_io_dm[101] ;
+ assign \mprj_pads.dm[100] = \mprj_io_dm[100] ;
+ assign \mprj_pads.dm[99] = \mprj_io_dm[99] ;
+ assign \mprj_pads.dm[98] = \mprj_io_dm[98] ;
+ assign \mprj_pads.dm[97] = \mprj_io_dm[97] ;
+ assign \mprj_pads.dm[96] = \mprj_io_dm[96] ;
+ assign \mprj_pads.dm[95] = \mprj_io_dm[95] ;
+ assign \mprj_pads.dm[94] = \mprj_io_dm[94] ;
+ assign \mprj_pads.dm[93] = \mprj_io_dm[93] ;
+ assign \mprj_pads.dm[92] = \mprj_io_dm[92] ;
+ assign \mprj_pads.dm[91] = \mprj_io_dm[91] ;
+ assign \mprj_pads.dm[90] = \mprj_io_dm[90] ;
+ assign \mprj_pads.dm[89] = \mprj_io_dm[89] ;
+ assign \mprj_pads.dm[88] = \mprj_io_dm[88] ;
+ assign \mprj_pads.dm[87] = \mprj_io_dm[87] ;
+ assign \mprj_pads.dm[86] = \mprj_io_dm[86] ;
+ assign \mprj_pads.dm[85] = \mprj_io_dm[85] ;
+ assign \mprj_pads.dm[84] = \mprj_io_dm[84] ;
+ assign \mprj_pads.dm[83] = \mprj_io_dm[83] ;
+ assign \mprj_pads.dm[82] = \mprj_io_dm[82] ;
+ assign \mprj_pads.dm[81] = \mprj_io_dm[81] ;
+ assign \mprj_pads.dm[80] = \mprj_io_dm[80] ;
+ assign \mprj_pads.dm[79] = \mprj_io_dm[79] ;
+ assign \mprj_pads.dm[78] = \mprj_io_dm[78] ;
+ assign \mprj_pads.dm[77] = \mprj_io_dm[77] ;
+ assign \mprj_pads.dm[76] = \mprj_io_dm[76] ;
+ assign \mprj_pads.dm[75] = \mprj_io_dm[75] ;
+ assign \mprj_pads.dm[74] = \mprj_io_dm[74] ;
+ assign \mprj_pads.dm[73] = \mprj_io_dm[73] ;
+ assign \mprj_pads.dm[72] = \mprj_io_dm[72] ;
+ assign \mprj_pads.dm[71] = \mprj_io_dm[71] ;
+ assign \mprj_pads.dm[70] = \mprj_io_dm[70] ;
+ assign \mprj_pads.dm[69] = \mprj_io_dm[69] ;
+ assign \mprj_pads.dm[68] = \mprj_io_dm[68] ;
+ assign \mprj_pads.dm[67] = \mprj_io_dm[67] ;
+ assign \mprj_pads.dm[66] = \mprj_io_dm[66] ;
+ assign \mprj_pads.dm[65] = \mprj_io_dm[65] ;
+ assign \mprj_pads.dm[64] = \mprj_io_dm[64] ;
+ assign \mprj_pads.dm[63] = \mprj_io_dm[63] ;
+ assign \mprj_pads.dm[62] = \mprj_io_dm[62] ;
+ assign \mprj_pads.dm[61] = \mprj_io_dm[61] ;
+ assign \mprj_pads.dm[60] = \mprj_io_dm[60] ;
+ assign \mprj_pads.dm[59] = \mprj_io_dm[59] ;
+ assign \mprj_pads.dm[58] = \mprj_io_dm[58] ;
+ assign \mprj_pads.dm[57] = \mprj_io_dm[57] ;
+ assign \mprj_pads.dm[56] = \mprj_io_dm[56] ;
+ assign \mprj_pads.dm[55] = \mprj_io_dm[55] ;
+ assign \mprj_pads.dm[54] = \mprj_io_dm[54] ;
+ assign \mprj_pads.dm[53] = \mprj_io_dm[53] ;
+ assign \mprj_pads.dm[52] = \mprj_io_dm[52] ;
+ assign \mprj_pads.dm[51] = \mprj_io_dm[51] ;
+ assign \mprj_pads.dm[50] = \mprj_io_dm[50] ;
+ assign \mprj_pads.dm[49] = \mprj_io_dm[49] ;
+ assign \mprj_pads.dm[48] = \mprj_io_dm[48] ;
+ assign \mprj_pads.dm[47] = \mprj_io_dm[47] ;
+ assign \mprj_pads.dm[46] = \mprj_io_dm[46] ;
+ assign \mprj_pads.dm[45] = \mprj_io_dm[45] ;
+ assign \mprj_pads.dm[44] = \mprj_io_dm[44] ;
+ assign \mprj_pads.dm[43] = \mprj_io_dm[43] ;
+ assign \mprj_pads.dm[42] = \mprj_io_dm[42] ;
+ assign \mprj_pads.dm[41] = \mprj_io_dm[41] ;
+ assign \mprj_pads.dm[40] = \mprj_io_dm[40] ;
+ assign \mprj_pads.dm[39] = \mprj_io_dm[39] ;
+ assign \mprj_pads.dm[38] = \mprj_io_dm[38] ;
+ assign \mprj_pads.dm[37] = \mprj_io_dm[37] ;
+ assign \mprj_pads.dm[36] = \mprj_io_dm[36] ;
+ assign \mprj_pads.dm[35] = \mprj_io_dm[35] ;
+ assign \mprj_pads.dm[34] = \mprj_io_dm[34] ;
+ assign \mprj_pads.dm[33] = \mprj_io_dm[33] ;
+ assign \mprj_pads.dm[32] = \mprj_io_dm[32] ;
+ assign \mprj_pads.dm[31] = \mprj_io_dm[31] ;
+ assign \mprj_pads.dm[30] = \mprj_io_dm[30] ;
+ assign \mprj_pads.dm[29] = \mprj_io_dm[29] ;
+ assign \mprj_pads.dm[28] = \mprj_io_dm[28] ;
+ assign \mprj_pads.dm[27] = \mprj_io_dm[27] ;
+ assign \mprj_pads.dm[26] = \mprj_io_dm[26] ;
+ assign \mprj_pads.dm[25] = \mprj_io_dm[25] ;
+ assign \mprj_pads.dm[24] = \mprj_io_dm[24] ;
+ assign \mprj_pads.dm[23] = \mprj_io_dm[23] ;
+ assign \mprj_pads.dm[22] = \mprj_io_dm[22] ;
+ assign \mprj_pads.dm[21] = \mprj_io_dm[21] ;
+ assign \mprj_pads.dm[20] = \mprj_io_dm[20] ;
+ assign \mprj_pads.dm[19] = \mprj_io_dm[19] ;
+ assign \mprj_pads.dm[18] = \mprj_io_dm[18] ;
+ assign \mprj_pads.dm[17] = \mprj_io_dm[17] ;
+ assign \mprj_pads.dm[16] = \mprj_io_dm[16] ;
+ assign \mprj_pads.dm[15] = \mprj_io_dm[15] ;
+ assign \mprj_pads.dm[14] = \mprj_io_dm[14] ;
+ assign \mprj_pads.dm[13] = \mprj_io_dm[13] ;
+ assign \mprj_pads.dm[12] = \mprj_io_dm[12] ;
+ assign \mprj_pads.dm[11] = \mprj_io_dm[11] ;
+ assign \mprj_pads.dm[10] = \mprj_io_dm[10] ;
+ assign \mprj_pads.dm[9] = \mprj_io_dm[9] ;
+ assign \mprj_pads.dm[8] = \mprj_io_dm[8] ;
+ assign \mprj_pads.dm[7] = \mprj_io_dm[7] ;
+ assign \mprj_pads.dm[6] = \mprj_io_dm[6] ;
+ assign \mprj_pads.dm[5] = \mprj_io_dm[5] ;
+ assign \mprj_pads.dm[4] = \mprj_io_dm[4] ;
+ assign \mprj_pads.dm[3] = \mprj_io_dm[3] ;
+ assign \mprj_pads.dm[2] = \mprj_io_dm[2] ;
+ assign \mprj_pads.dm[1] = \mprj_io_dm[1] ;
+ assign \mprj_pads.dm[0] = \mprj_io_dm[0] ;
+ assign \mprj_pads.inp_dis[37] = \mprj_io_inp_dis[37] ;
+ assign \mprj_pads.inp_dis[36] = \mprj_io_inp_dis[36] ;
+ assign \mprj_pads.inp_dis[35] = \mprj_io_inp_dis[35] ;
+ assign \mprj_pads.inp_dis[34] = \mprj_io_inp_dis[34] ;
+ assign \mprj_pads.inp_dis[33] = \mprj_io_inp_dis[33] ;
+ assign \mprj_pads.inp_dis[32] = \mprj_io_inp_dis[32] ;
+ assign \mprj_pads.inp_dis[31] = \mprj_io_inp_dis[31] ;
+ assign \mprj_pads.inp_dis[30] = \mprj_io_inp_dis[30] ;
+ assign \mprj_pads.inp_dis[29] = \mprj_io_inp_dis[29] ;
+ assign \mprj_pads.inp_dis[28] = \mprj_io_inp_dis[28] ;
+ assign \mprj_pads.inp_dis[27] = \mprj_io_inp_dis[27] ;
+ assign \mprj_pads.inp_dis[26] = \mprj_io_inp_dis[26] ;
+ assign \mprj_pads.inp_dis[25] = \mprj_io_inp_dis[25] ;
+ assign \mprj_pads.inp_dis[24] = \mprj_io_inp_dis[24] ;
+ assign \mprj_pads.inp_dis[23] = \mprj_io_inp_dis[23] ;
+ assign \mprj_pads.inp_dis[22] = \mprj_io_inp_dis[22] ;
+ assign \mprj_pads.inp_dis[21] = \mprj_io_inp_dis[21] ;
+ assign \mprj_pads.inp_dis[20] = \mprj_io_inp_dis[20] ;
+ assign \mprj_pads.inp_dis[19] = \mprj_io_inp_dis[19] ;
+ assign \mprj_pads.inp_dis[18] = \mprj_io_inp_dis[18] ;
+ assign \mprj_pads.inp_dis[17] = \mprj_io_inp_dis[17] ;
+ assign \mprj_pads.inp_dis[16] = \mprj_io_inp_dis[16] ;
+ assign \mprj_pads.inp_dis[15] = \mprj_io_inp_dis[15] ;
+ assign \mprj_pads.inp_dis[14] = \mprj_io_inp_dis[14] ;
+ assign \mprj_pads.inp_dis[13] = \mprj_io_inp_dis[13] ;
+ assign \mprj_pads.inp_dis[12] = \mprj_io_inp_dis[12] ;
+ assign \mprj_pads.inp_dis[11] = \mprj_io_inp_dis[11] ;
+ assign \mprj_pads.inp_dis[10] = \mprj_io_inp_dis[10] ;
+ assign \mprj_pads.inp_dis[9] = \mprj_io_inp_dis[9] ;
+ assign \mprj_pads.inp_dis[8] = \mprj_io_inp_dis[8] ;
+ assign \mprj_pads.inp_dis[7] = \mprj_io_inp_dis[7] ;
+ assign \mprj_pads.inp_dis[6] = \mprj_io_inp_dis[6] ;
+ assign \mprj_pads.inp_dis[5] = \mprj_io_inp_dis[5] ;
+ assign \mprj_pads.inp_dis[4] = \mprj_io_inp_dis[4] ;
+ assign \mprj_pads.inp_dis[3] = \mprj_io_inp_dis[3] ;
+ assign \mprj_pads.inp_dis[2] = \mprj_io_inp_dis[2] ;
+ assign \mprj_pads.inp_dis[1] = \mprj_io_inp_dis[1] ;
+ assign \mprj_pads.inp_dis[0] = \mprj_io_inp_dis[0] ;
+ assign \mprj_pads.io_out[37] = \mprj_io_out[37] ;
+ assign \mprj_pads.io_out[36] = \mprj_io_out[36] ;
+ assign \mprj_pads.io_out[35] = \mprj_io_out[35] ;
+ assign \mprj_pads.io_out[34] = \mprj_io_out[34] ;
+ assign \mprj_pads.io_out[33] = \mprj_io_out[33] ;
+ assign \mprj_pads.io_out[32] = \mprj_io_out[32] ;
+ assign \mprj_pads.io_out[31] = \mprj_io_out[31] ;
+ assign \mprj_pads.io_out[30] = \mprj_io_out[30] ;
+ assign \mprj_pads.io_out[29] = \mprj_io_out[29] ;
+ assign \mprj_pads.io_out[28] = \mprj_io_out[28] ;
+ assign \mprj_pads.io_out[27] = \mprj_io_out[27] ;
+ assign \mprj_pads.io_out[26] = \mprj_io_out[26] ;
+ assign \mprj_pads.io_out[25] = \mprj_io_out[25] ;
+ assign \mprj_pads.io_out[24] = \mprj_io_out[24] ;
+ assign \mprj_pads.io_out[23] = \mprj_io_out[23] ;
+ assign \mprj_pads.io_out[22] = \mprj_io_out[22] ;
+ assign \mprj_pads.io_out[21] = \mprj_io_out[21] ;
+ assign \mprj_pads.io_out[20] = \mprj_io_out[20] ;
+ assign \mprj_pads.io_out[19] = \mprj_io_out[19] ;
+ assign \mprj_pads.io_out[18] = \mprj_io_out[18] ;
+ assign \mprj_pads.io_out[17] = \mprj_io_out[17] ;
+ assign \mprj_pads.io_out[16] = \mprj_io_out[16] ;
+ assign \mprj_pads.io_out[15] = \mprj_io_out[15] ;
+ assign \mprj_pads.io_out[14] = \mprj_io_out[14] ;
+ assign \mprj_pads.io_out[13] = \mprj_io_out[13] ;
+ assign \mprj_pads.io_out[12] = \mprj_io_out[12] ;
+ assign \mprj_pads.io_out[11] = \mprj_io_out[11] ;
+ assign \mprj_pads.io_out[10] = \mprj_io_out[10] ;
+ assign \mprj_pads.io_out[9] = \mprj_io_out[9] ;
+ assign \mprj_pads.io_out[8] = \mprj_io_out[8] ;
+ assign \mprj_pads.io_out[7] = \mprj_io_out[7] ;
+ assign \mprj_pads.io_out[6] = \mprj_io_out[6] ;
+ assign \mprj_pads.io_out[5] = \mprj_io_out[5] ;
+ assign \mprj_pads.io_out[4] = \mprj_io_out[4] ;
+ assign \mprj_pads.io_out[3] = \mprj_io_out[3] ;
+ assign \mprj_pads.io_out[2] = \mprj_io_out[2] ;
+ assign \mprj_pads.io_out[1] = \mprj_io_out[1] ;
+ assign \mprj_pads.io_out[0] = \mprj_io_out[0] ;
+ assign \mprj_pads.holdover[37] = \mprj_io_holdover[37] ;
+ assign \mprj_pads.holdover[36] = \mprj_io_holdover[36] ;
+ assign \mprj_pads.holdover[35] = \mprj_io_holdover[35] ;
+ assign \mprj_pads.holdover[34] = \mprj_io_holdover[34] ;
+ assign \mprj_pads.holdover[33] = \mprj_io_holdover[33] ;
+ assign \mprj_pads.holdover[32] = \mprj_io_holdover[32] ;
+ assign \mprj_pads.holdover[31] = \mprj_io_holdover[31] ;
+ assign \mprj_pads.holdover[30] = \mprj_io_holdover[30] ;
+ assign \mprj_pads.holdover[29] = \mprj_io_holdover[29] ;
+ assign \mprj_pads.holdover[28] = \mprj_io_holdover[28] ;
+ assign \mprj_pads.holdover[27] = \mprj_io_holdover[27] ;
+ assign \mprj_pads.holdover[26] = \mprj_io_holdover[26] ;
+ assign \mprj_pads.holdover[25] = \mprj_io_holdover[25] ;
+ assign \mprj_pads.holdover[24] = \mprj_io_holdover[24] ;
+ assign \mprj_pads.holdover[23] = \mprj_io_holdover[23] ;
+ assign \mprj_pads.holdover[22] = \mprj_io_holdover[22] ;
+ assign \mprj_pads.holdover[21] = \mprj_io_holdover[21] ;
+ assign \mprj_pads.holdover[20] = \mprj_io_holdover[20] ;
+ assign \mprj_pads.holdover[19] = \mprj_io_holdover[19] ;
+ assign \mprj_pads.holdover[18] = \mprj_io_holdover[18] ;
+ assign \mprj_pads.holdover[17] = \mprj_io_holdover[17] ;
+ assign \mprj_pads.holdover[16] = \mprj_io_holdover[16] ;
+ assign \mprj_pads.holdover[15] = \mprj_io_holdover[15] ;
+ assign \mprj_pads.holdover[14] = \mprj_io_holdover[14] ;
+ assign \mprj_pads.holdover[13] = \mprj_io_holdover[13] ;
+ assign \mprj_pads.holdover[12] = \mprj_io_holdover[12] ;
+ assign \mprj_pads.holdover[11] = \mprj_io_holdover[11] ;
+ assign \mprj_pads.holdover[10] = \mprj_io_holdover[10] ;
+ assign \mprj_pads.holdover[9] = \mprj_io_holdover[9] ;
+ assign \mprj_pads.holdover[8] = \mprj_io_holdover[8] ;
+ assign \mprj_pads.holdover[7] = \mprj_io_holdover[7] ;
+ assign \mprj_pads.holdover[6] = \mprj_io_holdover[6] ;
+ assign \mprj_pads.holdover[5] = \mprj_io_holdover[5] ;
+ assign \mprj_pads.holdover[4] = \mprj_io_holdover[4] ;
+ assign \mprj_pads.holdover[3] = \mprj_io_holdover[3] ;
+ assign \mprj_pads.holdover[2] = \mprj_io_holdover[2] ;
+ assign \mprj_pads.holdover[1] = \mprj_io_holdover[1] ;
+ assign \mprj_pads.holdover[0] = \mprj_io_holdover[0] ;
+ assign \mprj_pads.ib_mode_sel[37] = \mprj_io_ib_mode_sel[37] ;
+ assign \mprj_pads.ib_mode_sel[36] = \mprj_io_ib_mode_sel[36] ;
+ assign \mprj_pads.ib_mode_sel[35] = \mprj_io_ib_mode_sel[35] ;
+ assign \mprj_pads.ib_mode_sel[34] = \mprj_io_ib_mode_sel[34] ;
+ assign \mprj_pads.ib_mode_sel[33] = \mprj_io_ib_mode_sel[33] ;
+ assign \mprj_pads.ib_mode_sel[32] = \mprj_io_ib_mode_sel[32] ;
+ assign \mprj_pads.ib_mode_sel[31] = \mprj_io_ib_mode_sel[31] ;
+ assign \mprj_pads.ib_mode_sel[30] = \mprj_io_ib_mode_sel[30] ;
+ assign \mprj_pads.ib_mode_sel[29] = \mprj_io_ib_mode_sel[29] ;
+ assign \mprj_pads.ib_mode_sel[28] = \mprj_io_ib_mode_sel[28] ;
+ assign \mprj_pads.ib_mode_sel[27] = \mprj_io_ib_mode_sel[27] ;
+ assign \mprj_pads.ib_mode_sel[26] = \mprj_io_ib_mode_sel[26] ;
+ assign \mprj_pads.ib_mode_sel[25] = \mprj_io_ib_mode_sel[25] ;
+ assign \mprj_pads.ib_mode_sel[24] = \mprj_io_ib_mode_sel[24] ;
+ assign \mprj_pads.ib_mode_sel[23] = \mprj_io_ib_mode_sel[23] ;
+ assign \mprj_pads.ib_mode_sel[22] = \mprj_io_ib_mode_sel[22] ;
+ assign \mprj_pads.ib_mode_sel[21] = \mprj_io_ib_mode_sel[21] ;
+ assign \mprj_pads.ib_mode_sel[20] = \mprj_io_ib_mode_sel[20] ;
+ assign \mprj_pads.ib_mode_sel[19] = \mprj_io_ib_mode_sel[19] ;
+ assign \mprj_pads.ib_mode_sel[18] = \mprj_io_ib_mode_sel[18] ;
+ assign \mprj_pads.ib_mode_sel[17] = \mprj_io_ib_mode_sel[17] ;
+ assign \mprj_pads.ib_mode_sel[16] = \mprj_io_ib_mode_sel[16] ;
+ assign \mprj_pads.ib_mode_sel[15] = \mprj_io_ib_mode_sel[15] ;
+ assign \mprj_pads.ib_mode_sel[14] = \mprj_io_ib_mode_sel[14] ;
+ assign \mprj_pads.ib_mode_sel[13] = \mprj_io_ib_mode_sel[13] ;
+ assign \mprj_pads.ib_mode_sel[12] = \mprj_io_ib_mode_sel[12] ;
+ assign \mprj_pads.ib_mode_sel[11] = \mprj_io_ib_mode_sel[11] ;
+ assign \mprj_pads.ib_mode_sel[10] = \mprj_io_ib_mode_sel[10] ;
+ assign \mprj_pads.ib_mode_sel[9] = \mprj_io_ib_mode_sel[9] ;
+ assign \mprj_pads.ib_mode_sel[8] = \mprj_io_ib_mode_sel[8] ;
+ assign \mprj_pads.ib_mode_sel[7] = \mprj_io_ib_mode_sel[7] ;
+ assign \mprj_pads.ib_mode_sel[6] = \mprj_io_ib_mode_sel[6] ;
+ assign \mprj_pads.ib_mode_sel[5] = \mprj_io_ib_mode_sel[5] ;
+ assign \mprj_pads.ib_mode_sel[4] = \mprj_io_ib_mode_sel[4] ;
+ assign \mprj_pads.ib_mode_sel[3] = \mprj_io_ib_mode_sel[3] ;
+ assign \mprj_pads.ib_mode_sel[2] = \mprj_io_ib_mode_sel[2] ;
+ assign \mprj_pads.ib_mode_sel[1] = \mprj_io_ib_mode_sel[1] ;
+ assign \mprj_pads.ib_mode_sel[0] = \mprj_io_ib_mode_sel[0] ;
+ assign \mprj_pads.vddio = vddio;
+ assign \mprj_pads.vssio = vssio;
+ assign \mprj_pads.vccd = vccd;
+ assign \mprj_pads.vssd = vssd;
+ assign \mprj_pads.vdda1 = vdda1;
+ assign \mprj_pads.vdda2 = vdda2;
+ assign \mprj_pads.vssa1 = vssa1;
+ assign \mprj_pads.vssa2 = vssa2;
+ assign \mprj_pads.vccd1 = vccd1;
+ assign \mprj_pads.vccd2 = vccd2;
+ assign \mprj_pads.vssd1 = vssd1;
+ assign \mprj_pads.vssd2 = vssd2;
+ assign \mprj_pads.porb_h = porb_h;
+ assign \mprj_pads.slow_sel[36] = \mprj_io_slow_sel[36] ;
+ assign \mprj_pads.slow_sel[23] = \mprj_io_slow_sel[23] ;
+ assign \mprj_pads.slow_sel[28] = \mprj_io_slow_sel[28] ;
+ assign \mprj_pads.slow_sel[37] = \mprj_io_slow_sel[37] ;
+ assign \flash_io0_mode[0] = flash_io0_oeb_core;
+ assign \mprj_pads.slow_sel[24] = \mprj_io_slow_sel[24] ;
+ assign \mprj_pads.slow_sel[21] = \mprj_io_slow_sel[21] ;
+ assign \mprj_pads.slow_sel[31] = \mprj_io_slow_sel[31] ;
+ assign \flash_io0_mode[1] = flash_io0_ieb_core;
+ assign \mprj_pads.slow_sel[22] = \mprj_io_slow_sel[22] ;
+ assign \mprj_pads.slow_sel[27] = \mprj_io_slow_sel[27] ;
+ assign \mprj_pads.slow_sel[32] = \mprj_io_slow_sel[32] ;
+ assign \mprj_pads.slow_sel[30] = \mprj_io_slow_sel[30] ;
+ assign \mprj_pads.slow_sel[26] = \mprj_io_slow_sel[26] ;
+ assign \mprj_pads.slow_sel[29] = \mprj_io_slow_sel[29] ;
+ assign \mprj_pads.slow_sel[35] = \mprj_io_slow_sel[35] ;
+ assign \mprj_pads.slow_sel[25] = \mprj_io_slow_sel[25] ;
+ assign \mprj_pads.slow_sel[20] = \mprj_io_slow_sel[20] ;
+ assign \mprj_pads.slow_sel[34] = \mprj_io_slow_sel[34] ;
+ assign \flash_io0_mode[2] = flash_io0_ieb_core;
+ assign \mprj_pads.slow_sel[33] = \mprj_io_slow_sel[33] ;
+ assign vssio_q = \mprj_pads.vssio_q ;
+ assign vddio_q = \mprj_pads.vddio_q ;
+ assign analog_b = \mprj_pads.analog_b ;
+ assign analog_a = \mprj_pads.analog_a ;
+ assign { \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0] } =
+ { \mprj_pads.io_in[37] , \mprj_pads.io_in[36] , \mprj_pads.io_in[35] , \mprj_pads.io_in[34] , \mprj_pads.io_in[33] , \mprj_pads.io_in[32] , \mprj_pads.io_in[31] , \mprj_pads.io_in[30] , \mprj_pads.io_in[29] , \mprj_pads.io_in[28] , \mprj_pads.io_in[27] , \mprj_pads.io_in[26] , \mprj_pads.io_in[25] , \mprj_pads.io_in[24] , \mprj_pads.io_in[23] , \mprj_pads.io_in[22] , \mprj_pads.io_in[21] , \mprj_pads.io_in[20] , \mprj_pads.io_in[19] , \mprj_pads.io_in[18] , \mprj_pads.io_in[17] , \mprj_pads.io_in[16] , \mprj_pads.io_in[15] , \mprj_pads.io_in[14] , \mprj_pads.io_in[13] , \mprj_pads.io_in[12] , \mprj_pads.io_in[11] , \mprj_pads.io_in[10] , \mprj_pads.io_in[9] , \mprj_pads.io_in[8] , \mprj_pads.io_in[7] , \mprj_pads.io_in[6] , \mprj_pads.io_in[5] , \mprj_pads.io_in[4] , \mprj_pads.io_in[3] , \mprj_pads.io_in[2] , \mprj_pads.io_in[1] , \mprj_pads.io_in[0] };
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v
new file mode 100644
index 0000000..400c5ab
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v
@@ -0,0 +1,377 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
+
+`include "defines.v"
+
+`ifdef GL
+ `include "gl/chip_io.v"
+`else
+ `ifdef SPLIT_BUS
+ `include "ports.v"
+ `include "chip_io_split.v"
+ `else
+ `include "pads.v"
+ `include "mprj_io.v"
+ `include "chip_io.v"
+ `endif
+`endif
+
+module chip_io_tb;
+
+ wire clock_core;
+ reg clock;
+
+ wire rstb_h;
+ reg RSTB;
+
+ reg porb_h;
+ wire por_l;
+
+ wire gpio;
+ reg gpio_out_core;
+ reg gpio_inenb_core;
+ reg gpio_outenb_core;
+
+ wire flash_csb;
+ reg flash_csb_core;
+ reg flash_csb_ieb_core;
+ reg flash_csb_oeb_core;
+
+ wire flash_clk;
+ reg flash_clk_core;
+ reg flash_clk_ieb_core;
+ reg flash_clk_oeb_core;
+
+ wire flash_io0;
+ wire flash_io0_di_core;
+ reg flash_io0_do_core;
+ reg flash_io0_ieb_core;
+ reg flash_io0_oeb_core;
+
+ wire flash_io1;
+ wire flash_io1_di_core;
+ reg flash_io1_do_core;
+ reg flash_io1_ieb_core;
+ reg flash_io1_oeb_core;
+
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+
+ wire [`MPRJ_IO_PADS-1:0] mprj_io;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ reg [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-10:0] mprj_analog_io;
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ porb_h = 0;
+ flash_csb_core = 0;
+ flash_csb_ieb_core = 1;
+ flash_csb_oeb_core = 0;
+ flash_clk_ieb_core = 1;
+ flash_clk_oeb_core = 0;
+ mprj_io_ib_mode_sel = {38{1'b0}};
+ mprj_io_vtrip_sel = {38{1'b0}};
+ mprj_io_slow_sel = {38{1'b0}};
+ mprj_io_holdover = {38{1'b0}};
+ mprj_io_analog_en = {38{1'b0}};
+ mprj_io_analog_sel = {38{1'b0}};
+ mprj_io_analog_pol = {38{1'b0}};
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ reg power1, power2;
+
+ initial begin
+ RSTB <= 1'b0;
+ porb_h <= 1'b0;
+ #500;
+ porb_h <= 1'b1;
+ #500;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ initial begin
+ $dumpfile("chip_io.vcd");
+ $dumpvars(0, chip_io_tb);
+ #(`SIM_TIME);
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Management Protect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [2:0] dm_all;
+ reg gpio_bit;
+
+ assign gpio = gpio_bit;
+ assign gpio_mode0_core = dm_all[0];
+ assign gpio_mode1_core = dm_all[1];
+
+ reg flash_io0_bit;
+ reg flash_io1_bit;
+
+ assign flash_io0 = flash_io0_bit;
+ assign flash_io1 = flash_io1_bit;
+
+ reg [`MPRJ_IO_PADS-1:0] mprj_io_bits;
+
+ assign mprj_io = mprj_io_bits;
+
+ initial begin
+ wait(RSTB == 1'b1); // wait for reset
+ #25;
+ // Clock & Reset Pads
+ if (clock !== clock_core) begin
+ $display("Error: Clock Pad Test Failed."); $finish;
+ end
+ if (RSTB !== rstb_h) begin
+ $display("Error: Reset Pad Test Failed."); $finish;
+ end
+
+ // Management GPIO Pad
+ gpio_bit = 1'b1;
+ gpio_out_core = 1'b0;
+ gpio_inenb_core = 1'b0;
+ gpio_outenb_core = 1'b1;
+ dm_all = 3'b001; // input-only
+ #25;
+ if (gpio_in_core !== gpio) begin
+ $display("Error: GPIO Pad Input Test Failed."); $finish;
+ end
+
+ gpio_bit = 1'bz;
+ gpio_out_core = 1'b1;
+ gpio_inenb_core = 1'b1;
+ gpio_outenb_core = 1'b0;
+ dm_all = 3'b110; // output-only
+ #25;
+ if (gpio_out_core !== gpio) begin
+ $display("Error: GPIO Pad Output Test Failed."); $finish;
+ end
+
+ // Flash Output Pads
+ flash_csb_core = 1'b1; // CSB Pad
+ #25;
+ if (flash_csb !== flash_csb_core) begin
+ $display("Error: Flash CSB Pad Test Failed."); $finish;
+ end
+
+ flash_clk_core = 1'b1; // CLK Pad
+ #25;
+ if (flash_clk !== flash_clk_core) begin
+ $display("Error: Flash CLK Pad Test Failed."); $finish;
+ end
+
+ // Flash Inout Pads
+ flash_io0_bit = 1'b1;
+ flash_io0_ieb_core = 1'b0; // Input
+ flash_io0_oeb_core = 1'b1;
+ #25;
+ if (flash_io0_di_core !== flash_io0_bit) begin
+ $display("Error: Flash io0 Pad Input Test Failed."); $finish;
+ end
+
+ flash_io0_bit = 1'bz;
+ flash_io0_do_core = 1'b1;
+ flash_io0_ieb_core = 1'b1;
+ flash_io0_oeb_core = 1'b0; // Output
+ #25
+ if (flash_io0 !== flash_io0_do_core) begin
+ $display("Error: Flash io0 Pad Output Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Outputs
+ mprj_io_bits = {38{1'bz}};
+ mprj_io_out = {6'b10101, 32'hF0F0};
+ mprj_io_oeb = {38{1'b0}};
+ mprj_io_inp_dis = {38{1'b1}};
+ mprj_io_dm = {38*3{3'b110}};
+
+ #25;
+ if (mprj_io !== mprj_io_out) begin
+ $display("Error: User Project Pads Output Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Inputs
+ mprj_io_bits = {6'b01010, 32'hFF0F};
+ mprj_io_out = {38{1'b0}};
+ mprj_io_oeb = {38{1'b1}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38*3{3'b001}};
+
+ #25;
+ if (mprj_io_in !== mprj_io_bits) begin
+ $display("Error: User Project Pads Input Test Failed."); $finish;
+ end
+
+ // User Project Pads - All Bidirectional
+ mprj_io_bits = {6'b01010, 32'hF00F}; // drive input signal
+ mprj_io_out = {38{1'bz}};
+ mprj_io_oeb = {38{1'b1}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38{3'b110}};
+
+ #25;
+ if (mprj_io_in !== mprj_io_bits) begin
+ $display("Error: User Project Pads Bidirectional Test Failed."); $finish;
+ end
+
+ mprj_io_bits = {38{1'bz}};
+ mprj_io_out = {6'b01110, 32'h0FF0}; // drive output signal
+ mprj_io_oeb = {38{1'b0}};
+ mprj_io_inp_dis = {38{1'b0}};
+ mprj_io_dm = {38{3'b110}};
+
+ #25;
+ if (mprj_io !== mprj_io_out) begin
+ $display("Error: User Project Pads Output Test Failed."); $finish;
+ end
+ $display("Success");
+ $display("Monitor: Chip IO Test Passed.");
+ #2000;
+ $finish;
+ end
+
+ assign por_l = ~porb_h;
+
+ chip_io uut (
+ // Package Pins
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+
+ .gpio(gpio),
+ .clock(clock),
+ .resetb(RSTB),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_core),
+ .flash_clk_core(flash_clk_core),
+ .flash_csb_oeb_core(flash_csb_oeb_core),
+ .flash_clk_oeb_core(flash_clk_oeb_core),
+ .flash_io0_oeb_core(flash_io0_oeb_core),
+ .flash_io1_oeb_core(flash_io1_oeb_core),
+ .flash_csb_ieb_core(flash_csb_ieb_core),
+ .flash_clk_ieb_core(flash_clk_ieb_core),
+ .flash_io0_ieb_core(flash_io0_ieb_core),
+ .flash_io1_ieb_core(flash_io1_ieb_core),
+ .flash_io0_do_core(flash_io0_do_core),
+ .flash_io1_do_core(flash_io1_do_core),
+ .flash_io0_di_core(flash_io0_di_core),
+ .flash_io1_di_core(flash_io1_di_core),
+ `ifdef SPLIT_BUS
+ `MPRJ_IO,
+ `MPRJ_IO_IN,
+ `MPRJ_IO_OUT,
+ `MPRJ_IO_OEB,
+ `MPRJ_IO_INP_DIS,
+ `MPRJ_IO_IB_MODE_SEL,
+ `MPRJ_IO_VTRIP_SEL,
+ `MPRJ_IO_SLOW_SEL,
+ `MPRJ_IO_HOLDOVER,
+ `MPRJ_IO_ANALOG_EN,
+ `MPRJ_IO_ANALOG_SEL,
+ `MPRJ_IO_ANALOG_POL,
+ `MPRJ_IO_DM,
+ `MPRJ_IO_ANALOG
+ `else
+ .mprj_io(mprj_io),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(mprj_analog_io)
+`endif
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/chip_io/ports.v b/caravel/verilog/dv/wb_utests/chip_io/ports.v
new file mode 100644
index 0000000..6516802
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/chip_io/ports.v
@@ -0,0 +1,727 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`define MPRJ_IO \
+.\mprj_io[0] (mprj_io[0]),\
+.\mprj_io[1] (mprj_io[1]),\
+.\mprj_io[2] (mprj_io[2]),\
+.\mprj_io[3] (mprj_io[3]),\
+.\mprj_io[4] (mprj_io[4]),\
+.\mprj_io[5] (mprj_io[5]),\
+.\mprj_io[6] (mprj_io[6]),\
+.\mprj_io[7] (mprj_io[7]),\
+.\mprj_io[8] (mprj_io[8]),\
+.\mprj_io[9] (mprj_io[9]),\
+.\mprj_io[10] (mprj_io[10]),\
+.\mprj_io[11] (mprj_io[11]),\
+.\mprj_io[12] (mprj_io[12]),\
+.\mprj_io[13] (mprj_io[13]),\
+.\mprj_io[14] (mprj_io[14]),\
+.\mprj_io[15] (mprj_io[15]),\
+.\mprj_io[16] (mprj_io[16]),\
+.\mprj_io[17] (mprj_io[17]),\
+.\mprj_io[18] (mprj_io[18]),\
+.\mprj_io[19] (mprj_io[19]),\
+.\mprj_io[20] (mprj_io[20]),\
+.\mprj_io[21] (mprj_io[21]),\
+.\mprj_io[22] (mprj_io[22]),\
+.\mprj_io[23] (mprj_io[23]),\
+.\mprj_io[24] (mprj_io[24]),\
+.\mprj_io[25] (mprj_io[25]),\
+.\mprj_io[26] (mprj_io[26]),\
+.\mprj_io[27] (mprj_io[27]),\
+.\mprj_io[28] (mprj_io[28]),\
+.\mprj_io[29] (mprj_io[29]),\
+.\mprj_io[30] (mprj_io[30]),\
+.\mprj_io[31] (mprj_io[31]),\
+.\mprj_io[32] (mprj_io[32]),\
+.\mprj_io[33] (mprj_io[33]),\
+.\mprj_io[34] (mprj_io[34]),\
+.\mprj_io[35] (mprj_io[35]),\
+.\mprj_io[36] (mprj_io[36]),\
+.\mprj_io[37] (mprj_io[37])
+
+`define MPRJ_IO_IN \
+.\mprj_io_in[0] (mprj_io_in[0]),\
+.\mprj_io_in[1] (mprj_io_in[1]),\
+.\mprj_io_in[2] (mprj_io_in[2]),\
+.\mprj_io_in[3] (mprj_io_in[3]),\
+.\mprj_io_in[4] (mprj_io_in[4]),\
+.\mprj_io_in[5] (mprj_io_in[5]),\
+.\mprj_io_in[6] (mprj_io_in[6]),\
+.\mprj_io_in[7] (mprj_io_in[7]),\
+.\mprj_io_in[8] (mprj_io_in[8]),\
+.\mprj_io_in[9] (mprj_io_in[9]),\
+.\mprj_io_in[10] (mprj_io_in[10]),\
+.\mprj_io_in[11] (mprj_io_in[11]),\
+.\mprj_io_in[12] (mprj_io_in[12]),\
+.\mprj_io_in[13] (mprj_io_in[13]),\
+.\mprj_io_in[14] (mprj_io_in[14]),\
+.\mprj_io_in[15] (mprj_io_in[15]),\
+.\mprj_io_in[16] (mprj_io_in[16]),\
+.\mprj_io_in[17] (mprj_io_in[17]),\
+.\mprj_io_in[18] (mprj_io_in[18]),\
+.\mprj_io_in[19] (mprj_io_in[19]),\
+.\mprj_io_in[20] (mprj_io_in[20]),\
+.\mprj_io_in[21] (mprj_io_in[21]),\
+.\mprj_io_in[22] (mprj_io_in[22]),\
+.\mprj_io_in[23] (mprj_io_in[23]),\
+.\mprj_io_in[24] (mprj_io_in[24]),\
+.\mprj_io_in[25] (mprj_io_in[25]),\
+.\mprj_io_in[26] (mprj_io_in[26]),\
+.\mprj_io_in[27] (mprj_io_in[27]),\
+.\mprj_io_in[28] (mprj_io_in[28]),\
+.\mprj_io_in[29] (mprj_io_in[29]),\
+.\mprj_io_in[30] (mprj_io_in[30]),\
+.\mprj_io_in[31] (mprj_io_in[31]),\
+.\mprj_io_in[32] (mprj_io_in[32]),\
+.\mprj_io_in[33] (mprj_io_in[33]),\
+.\mprj_io_in[34] (mprj_io_in[34]),\
+.\mprj_io_in[35] (mprj_io_in[35]),\
+.\mprj_io_in[36] (mprj_io_in[36]),\
+.\mprj_io_in[37] (mprj_io_in[37])
+
+
+`define MPRJ_IO_OUT \
+.\mprj_io_out[0] (mprj_io_out[0]),\
+.\mprj_io_out[1] (mprj_io_out[1]),\
+.\mprj_io_out[2] (mprj_io_out[2]),\
+.\mprj_io_out[3] (mprj_io_out[3]),\
+.\mprj_io_out[4] (mprj_io_out[4]),\
+.\mprj_io_out[5] (mprj_io_out[5]),\
+.\mprj_io_out[6] (mprj_io_out[6]),\
+.\mprj_io_out[7] (mprj_io_out[7]),\
+.\mprj_io_out[8] (mprj_io_out[8]),\
+.\mprj_io_out[9] (mprj_io_out[9]),\
+.\mprj_io_out[10] (mprj_io_out[10]),\
+.\mprj_io_out[11] (mprj_io_out[11]),\
+.\mprj_io_out[12] (mprj_io_out[12]),\
+.\mprj_io_out[13] (mprj_io_out[13]),\
+.\mprj_io_out[14] (mprj_io_out[14]),\
+.\mprj_io_out[15] (mprj_io_out[15]),\
+.\mprj_io_out[16] (mprj_io_out[16]),\
+.\mprj_io_out[17] (mprj_io_out[17]),\
+.\mprj_io_out[18] (mprj_io_out[18]),\
+.\mprj_io_out[19] (mprj_io_out[19]),\
+.\mprj_io_out[20] (mprj_io_out[20]),\
+.\mprj_io_out[21] (mprj_io_out[21]),\
+.\mprj_io_out[22] (mprj_io_out[22]),\
+.\mprj_io_out[23] (mprj_io_out[23]),\
+.\mprj_io_out[24] (mprj_io_out[24]),\
+.\mprj_io_out[25] (mprj_io_out[25]),\
+.\mprj_io_out[26] (mprj_io_out[26]),\
+.\mprj_io_out[27] (mprj_io_out[27]),\
+.\mprj_io_out[28] (mprj_io_out[28]),\
+.\mprj_io_out[29] (mprj_io_out[29]),\
+.\mprj_io_out[30] (mprj_io_out[30]),\
+.\mprj_io_out[31] (mprj_io_out[31]),\
+.\mprj_io_out[32] (mprj_io_out[32]),\
+.\mprj_io_out[33] (mprj_io_out[33]),\
+.\mprj_io_out[34] (mprj_io_out[34]),\
+.\mprj_io_out[35] (mprj_io_out[35]),\
+.\mprj_io_out[36] (mprj_io_out[36]),\
+.\mprj_io_out[37] (mprj_io_out[37])
+
+`define MPRJ_IO_OEB \
+.\mprj_io_oeb[0] (mprj_io_oeb[0]),\
+.\mprj_io_oeb[1] (mprj_io_oeb[1]),\
+.\mprj_io_oeb[2] (mprj_io_oeb[2]),\
+.\mprj_io_oeb[3] (mprj_io_oeb[3]),\
+.\mprj_io_oeb[4] (mprj_io_oeb[4]),\
+.\mprj_io_oeb[5] (mprj_io_oeb[5]),\
+.\mprj_io_oeb[6] (mprj_io_oeb[6]),\
+.\mprj_io_oeb[7] (mprj_io_oeb[7]),\
+.\mprj_io_oeb[8] (mprj_io_oeb[8]),\
+.\mprj_io_oeb[9] (mprj_io_oeb[9]),\
+.\mprj_io_oeb[10] (mprj_io_oeb[10]),\
+.\mprj_io_oeb[11] (mprj_io_oeb[11]),\
+.\mprj_io_oeb[12] (mprj_io_oeb[12]),\
+.\mprj_io_oeb[13] (mprj_io_oeb[13]),\
+.\mprj_io_oeb[14] (mprj_io_oeb[14]),\
+.\mprj_io_oeb[15] (mprj_io_oeb[15]),\
+.\mprj_io_oeb[16] (mprj_io_oeb[16]),\
+.\mprj_io_oeb[17] (mprj_io_oeb[17]),\
+.\mprj_io_oeb[18] (mprj_io_oeb[18]),\
+.\mprj_io_oeb[19] (mprj_io_oeb[19]),\
+.\mprj_io_oeb[20] (mprj_io_oeb[20]),\
+.\mprj_io_oeb[21] (mprj_io_oeb[21]),\
+.\mprj_io_oeb[22] (mprj_io_oeb[22]),\
+.\mprj_io_oeb[23] (mprj_io_oeb[23]),\
+.\mprj_io_oeb[24] (mprj_io_oeb[24]),\
+.\mprj_io_oeb[25] (mprj_io_oeb[25]),\
+.\mprj_io_oeb[26] (mprj_io_oeb[26]),\
+.\mprj_io_oeb[27] (mprj_io_oeb[27]),\
+.\mprj_io_oeb[28] (mprj_io_oeb[28]),\
+.\mprj_io_oeb[29] (mprj_io_oeb[29]),\
+.\mprj_io_oeb[30] (mprj_io_oeb[30]),\
+.\mprj_io_oeb[31] (mprj_io_oeb[31]),\
+.\mprj_io_oeb[32] (mprj_io_oeb[32]),\
+.\mprj_io_oeb[33] (mprj_io_oeb[33]),\
+.\mprj_io_oeb[34] (mprj_io_oeb[34]),\
+.\mprj_io_oeb[35] (mprj_io_oeb[35]),\
+.\mprj_io_oeb[36] (mprj_io_oeb[36]),\
+.\mprj_io_oeb[37] (mprj_io_oeb[37])
+
+`define MPRJ_IO_HLDH_N \
+.\mprj_io_hldh_n[0] (mprj_io_hldh_n[0]),\
+.\mprj_io_hldh_n[1] (mprj_io_hldh_n[1]),\
+.\mprj_io_hldh_n[2] (mprj_io_hldh_n[2]),\
+.\mprj_io_hldh_n[3] (mprj_io_hldh_n[3]),\
+.\mprj_io_hldh_n[4] (mprj_io_hldh_n[4]),\
+.\mprj_io_hldh_n[5] (mprj_io_hldh_n[5]),\
+.\mprj_io_hldh_n[6] (mprj_io_hldh_n[6]),\
+.\mprj_io_hldh_n[7] (mprj_io_hldh_n[7]),\
+.\mprj_io_hldh_n[8] (mprj_io_hldh_n[8]),\
+.\mprj_io_hldh_n[9] (mprj_io_hldh_n[9]),\
+.\mprj_io_hldh_n[10] (mprj_io_hldh_n[10]),\
+.\mprj_io_hldh_n[11] (mprj_io_hldh_n[11]),\
+.\mprj_io_hldh_n[12] (mprj_io_hldh_n[12]),\
+.\mprj_io_hldh_n[13] (mprj_io_hldh_n[13]),\
+.\mprj_io_hldh_n[14] (mprj_io_hldh_n[14]),\
+.\mprj_io_hldh_n[15] (mprj_io_hldh_n[15]),\
+.\mprj_io_hldh_n[16] (mprj_io_hldh_n[16]),\
+.\mprj_io_hldh_n[17] (mprj_io_hldh_n[17]),\
+.\mprj_io_hldh_n[18] (mprj_io_hldh_n[18]),\
+.\mprj_io_hldh_n[19] (mprj_io_hldh_n[19]),\
+.\mprj_io_hldh_n[20] (mprj_io_hldh_n[20]),\
+.\mprj_io_hldh_n[21] (mprj_io_hldh_n[21]),\
+.\mprj_io_hldh_n[22] (mprj_io_hldh_n[22]),\
+.\mprj_io_hldh_n[23] (mprj_io_hldh_n[23]),\
+.\mprj_io_hldh_n[24] (mprj_io_hldh_n[24]),\
+.\mprj_io_hldh_n[25] (mprj_io_hldh_n[25]),\
+.\mprj_io_hldh_n[26] (mprj_io_hldh_n[26]),\
+.\mprj_io_hldh_n[27] (mprj_io_hldh_n[27]),\
+.\mprj_io_hldh_n[28] (mprj_io_hldh_n[28]),\
+.\mprj_io_hldh_n[29] (mprj_io_hldh_n[29]),\
+.\mprj_io_hldh_n[30] (mprj_io_hldh_n[30]),\
+.\mprj_io_hldh_n[31] (mprj_io_hldh_n[31]),\
+.\mprj_io_hldh_n[32] (mprj_io_hldh_n[32]),\
+.\mprj_io_hldh_n[33] (mprj_io_hldh_n[33]),\
+.\mprj_io_hldh_n[34] (mprj_io_hldh_n[34]),\
+.\mprj_io_hldh_n[35] (mprj_io_hldh_n[35]),\
+.\mprj_io_hldh_n[36] (mprj_io_hldh_n[36]),\
+.\mprj_io_hldh_n[37] (mprj_io_hldh_n[37])
+
+`define MPRJ_IO_ENH \
+.\mprj_io_enh[0] (mprj_io_enh[0]),\
+.\mprj_io_enh[1] (mprj_io_enh[1]),\
+.\mprj_io_enh[2] (mprj_io_enh[2]),\
+.\mprj_io_enh[3] (mprj_io_enh[3]),\
+.\mprj_io_enh[4] (mprj_io_enh[4]),\
+.\mprj_io_enh[5] (mprj_io_enh[5]),\
+.\mprj_io_enh[6] (mprj_io_enh[6]),\
+.\mprj_io_enh[7] (mprj_io_enh[7]),\
+.\mprj_io_enh[8] (mprj_io_enh[8]),\
+.\mprj_io_enh[9] (mprj_io_enh[9]),\
+.\mprj_io_enh[10] (mprj_io_enh[10]),\
+.\mprj_io_enh[11] (mprj_io_enh[11]),\
+.\mprj_io_enh[12] (mprj_io_enh[12]),\
+.\mprj_io_enh[13] (mprj_io_enh[13]),\
+.\mprj_io_enh[14] (mprj_io_enh[14]),\
+.\mprj_io_enh[15] (mprj_io_enh[15]),\
+.\mprj_io_enh[16] (mprj_io_enh[16]),\
+.\mprj_io_enh[17] (mprj_io_enh[17]),\
+.\mprj_io_enh[18] (mprj_io_enh[18]),\
+.\mprj_io_enh[19] (mprj_io_enh[19]),\
+.\mprj_io_enh[20] (mprj_io_enh[20]),\
+.\mprj_io_enh[21] (mprj_io_enh[21]),\
+.\mprj_io_enh[22] (mprj_io_enh[22]),\
+.\mprj_io_enh[23] (mprj_io_enh[23]),\
+.\mprj_io_enh[24] (mprj_io_enh[24]),\
+.\mprj_io_enh[25] (mprj_io_enh[25]),\
+.\mprj_io_enh[26] (mprj_io_enh[26]),\
+.\mprj_io_enh[27] (mprj_io_enh[27]),\
+.\mprj_io_enh[28] (mprj_io_enh[28]),\
+.\mprj_io_enh[29] (mprj_io_enh[29]),\
+.\mprj_io_enh[30] (mprj_io_enh[30]),\
+.\mprj_io_enh[31] (mprj_io_enh[31]),\
+.\mprj_io_enh[32] (mprj_io_enh[32]),\
+.\mprj_io_enh[33] (mprj_io_enh[33]),\
+.\mprj_io_enh[34] (mprj_io_enh[34]),\
+.\mprj_io_enh[35] (mprj_io_enh[35]),\
+.\mprj_io_enh[36] (mprj_io_enh[36]),\
+.\mprj_io_enh[37] (mprj_io_enh[37])
+
+`define MPRJ_IO_INP_DIS \
+.\mprj_io_inp_dis[0] (mprj_io_inp_dis[0]),\
+.\mprj_io_inp_dis[1] (mprj_io_inp_dis[1]),\
+.\mprj_io_inp_dis[2] (mprj_io_inp_dis[2]),\
+.\mprj_io_inp_dis[3] (mprj_io_inp_dis[3]),\
+.\mprj_io_inp_dis[4] (mprj_io_inp_dis[4]),\
+.\mprj_io_inp_dis[5] (mprj_io_inp_dis[5]),\
+.\mprj_io_inp_dis[6] (mprj_io_inp_dis[6]),\
+.\mprj_io_inp_dis[7] (mprj_io_inp_dis[7]),\
+.\mprj_io_inp_dis[8] (mprj_io_inp_dis[8]),\
+.\mprj_io_inp_dis[9] (mprj_io_inp_dis[9]),\
+.\mprj_io_inp_dis[10] (mprj_io_inp_dis[10]),\
+.\mprj_io_inp_dis[11] (mprj_io_inp_dis[11]),\
+.\mprj_io_inp_dis[12] (mprj_io_inp_dis[12]),\
+.\mprj_io_inp_dis[13] (mprj_io_inp_dis[13]),\
+.\mprj_io_inp_dis[14] (mprj_io_inp_dis[14]),\
+.\mprj_io_inp_dis[15] (mprj_io_inp_dis[15]),\
+.\mprj_io_inp_dis[16] (mprj_io_inp_dis[16]),\
+.\mprj_io_inp_dis[17] (mprj_io_inp_dis[17]),\
+.\mprj_io_inp_dis[18] (mprj_io_inp_dis[18]),\
+.\mprj_io_inp_dis[19] (mprj_io_inp_dis[19]),\
+.\mprj_io_inp_dis[20] (mprj_io_inp_dis[20]),\
+.\mprj_io_inp_dis[21] (mprj_io_inp_dis[21]),\
+.\mprj_io_inp_dis[22] (mprj_io_inp_dis[22]),\
+.\mprj_io_inp_dis[23] (mprj_io_inp_dis[23]),\
+.\mprj_io_inp_dis[24] (mprj_io_inp_dis[24]),\
+.\mprj_io_inp_dis[25] (mprj_io_inp_dis[25]),\
+.\mprj_io_inp_dis[26] (mprj_io_inp_dis[26]),\
+.\mprj_io_inp_dis[27] (mprj_io_inp_dis[27]),\
+.\mprj_io_inp_dis[28] (mprj_io_inp_dis[28]),\
+.\mprj_io_inp_dis[29] (mprj_io_inp_dis[29]),\
+.\mprj_io_inp_dis[30] (mprj_io_inp_dis[30]),\
+.\mprj_io_inp_dis[31] (mprj_io_inp_dis[31]),\
+.\mprj_io_inp_dis[32] (mprj_io_inp_dis[32]),\
+.\mprj_io_inp_dis[33] (mprj_io_inp_dis[33]),\
+.\mprj_io_inp_dis[34] (mprj_io_inp_dis[34]),\
+.\mprj_io_inp_dis[35] (mprj_io_inp_dis[35]),\
+.\mprj_io_inp_dis[36] (mprj_io_inp_dis[36]),\
+.\mprj_io_inp_dis[37] (mprj_io_inp_dis[37])
+
+`define MPRJ_IO_IB_MODE_SEL \
+.\mprj_io_ib_mode_sel[0] (mprj_io_ib_mode_sel[0]),\
+.\mprj_io_ib_mode_sel[1] (mprj_io_ib_mode_sel[1]),\
+.\mprj_io_ib_mode_sel[2] (mprj_io_ib_mode_sel[2]),\
+.\mprj_io_ib_mode_sel[3] (mprj_io_ib_mode_sel[3]),\
+.\mprj_io_ib_mode_sel[4] (mprj_io_ib_mode_sel[4]),\
+.\mprj_io_ib_mode_sel[5] (mprj_io_ib_mode_sel[5]),\
+.\mprj_io_ib_mode_sel[6] (mprj_io_ib_mode_sel[6]),\
+.\mprj_io_ib_mode_sel[7] (mprj_io_ib_mode_sel[7]),\
+.\mprj_io_ib_mode_sel[8] (mprj_io_ib_mode_sel[8]),\
+.\mprj_io_ib_mode_sel[9] (mprj_io_ib_mode_sel[9]),\
+.\mprj_io_ib_mode_sel[10] (mprj_io_ib_mode_sel[10]),\
+.\mprj_io_ib_mode_sel[11] (mprj_io_ib_mode_sel[11]),\
+.\mprj_io_ib_mode_sel[12] (mprj_io_ib_mode_sel[12]),\
+.\mprj_io_ib_mode_sel[13] (mprj_io_ib_mode_sel[13]),\
+.\mprj_io_ib_mode_sel[14] (mprj_io_ib_mode_sel[14]),\
+.\mprj_io_ib_mode_sel[15] (mprj_io_ib_mode_sel[15]),\
+.\mprj_io_ib_mode_sel[16] (mprj_io_ib_mode_sel[16]),\
+.\mprj_io_ib_mode_sel[17] (mprj_io_ib_mode_sel[17]),\
+.\mprj_io_ib_mode_sel[18] (mprj_io_ib_mode_sel[18]),\
+.\mprj_io_ib_mode_sel[19] (mprj_io_ib_mode_sel[19]),\
+.\mprj_io_ib_mode_sel[20] (mprj_io_ib_mode_sel[20]),\
+.\mprj_io_ib_mode_sel[21] (mprj_io_ib_mode_sel[21]),\
+.\mprj_io_ib_mode_sel[22] (mprj_io_ib_mode_sel[22]),\
+.\mprj_io_ib_mode_sel[23] (mprj_io_ib_mode_sel[23]),\
+.\mprj_io_ib_mode_sel[24] (mprj_io_ib_mode_sel[24]),\
+.\mprj_io_ib_mode_sel[25] (mprj_io_ib_mode_sel[25]),\
+.\mprj_io_ib_mode_sel[26] (mprj_io_ib_mode_sel[26]),\
+.\mprj_io_ib_mode_sel[27] (mprj_io_ib_mode_sel[27]),\
+.\mprj_io_ib_mode_sel[28] (mprj_io_ib_mode_sel[28]),\
+.\mprj_io_ib_mode_sel[29] (mprj_io_ib_mode_sel[29]),\
+.\mprj_io_ib_mode_sel[30] (mprj_io_ib_mode_sel[30]),\
+.\mprj_io_ib_mode_sel[31] (mprj_io_ib_mode_sel[31]),\
+.\mprj_io_ib_mode_sel[32] (mprj_io_ib_mode_sel[32]),\
+.\mprj_io_ib_mode_sel[33] (mprj_io_ib_mode_sel[33]),\
+.\mprj_io_ib_mode_sel[34] (mprj_io_ib_mode_sel[34]),\
+.\mprj_io_ib_mode_sel[35] (mprj_io_ib_mode_sel[35]),\
+.\mprj_io_ib_mode_sel[36] (mprj_io_ib_mode_sel[36]),\
+.\mprj_io_ib_mode_sel[37] (mprj_io_ib_mode_sel[37])
+
+`define MPRJ_IO_VTRIP_SEL \
+.\mprj_io_vtrip_sel[0] (mprj_io_vtrip_sel[0]),\
+.\mprj_io_vtrip_sel[1] (mprj_io_vtrip_sel[1]),\
+.\mprj_io_vtrip_sel[2] (mprj_io_vtrip_sel[2]),\
+.\mprj_io_vtrip_sel[3] (mprj_io_vtrip_sel[3]),\
+.\mprj_io_vtrip_sel[4] (mprj_io_vtrip_sel[4]),\
+.\mprj_io_vtrip_sel[5] (mprj_io_vtrip_sel[5]),\
+.\mprj_io_vtrip_sel[6] (mprj_io_vtrip_sel[6]),\
+.\mprj_io_vtrip_sel[7] (mprj_io_vtrip_sel[7]),\
+.\mprj_io_vtrip_sel[8] (mprj_io_vtrip_sel[8]),\
+.\mprj_io_vtrip_sel[9] (mprj_io_vtrip_sel[9]),\
+.\mprj_io_vtrip_sel[10] (mprj_io_vtrip_sel[10]),\
+.\mprj_io_vtrip_sel[11] (mprj_io_vtrip_sel[11]),\
+.\mprj_io_vtrip_sel[12] (mprj_io_vtrip_sel[12]),\
+.\mprj_io_vtrip_sel[13] (mprj_io_vtrip_sel[13]),\
+.\mprj_io_vtrip_sel[14] (mprj_io_vtrip_sel[14]),\
+.\mprj_io_vtrip_sel[15] (mprj_io_vtrip_sel[15]),\
+.\mprj_io_vtrip_sel[16] (mprj_io_vtrip_sel[16]),\
+.\mprj_io_vtrip_sel[17] (mprj_io_vtrip_sel[17]),\
+.\mprj_io_vtrip_sel[18] (mprj_io_vtrip_sel[18]),\
+.\mprj_io_vtrip_sel[19] (mprj_io_vtrip_sel[19]),\
+.\mprj_io_vtrip_sel[20] (mprj_io_vtrip_sel[20]),\
+.\mprj_io_vtrip_sel[21] (mprj_io_vtrip_sel[21]),\
+.\mprj_io_vtrip_sel[22] (mprj_io_vtrip_sel[22]),\
+.\mprj_io_vtrip_sel[23] (mprj_io_vtrip_sel[23]),\
+.\mprj_io_vtrip_sel[24] (mprj_io_vtrip_sel[24]),\
+.\mprj_io_vtrip_sel[25] (mprj_io_vtrip_sel[25]),\
+.\mprj_io_vtrip_sel[26] (mprj_io_vtrip_sel[26]),\
+.\mprj_io_vtrip_sel[27] (mprj_io_vtrip_sel[27]),\
+.\mprj_io_vtrip_sel[28] (mprj_io_vtrip_sel[28]),\
+.\mprj_io_vtrip_sel[29] (mprj_io_vtrip_sel[29]),\
+.\mprj_io_vtrip_sel[30] (mprj_io_vtrip_sel[30]),\
+.\mprj_io_vtrip_sel[31] (mprj_io_vtrip_sel[31]),\
+.\mprj_io_vtrip_sel[32] (mprj_io_vtrip_sel[32]),\
+.\mprj_io_vtrip_sel[33] (mprj_io_vtrip_sel[33]),\
+.\mprj_io_vtrip_sel[34] (mprj_io_vtrip_sel[34]),\
+.\mprj_io_vtrip_sel[35] (mprj_io_vtrip_sel[35]),\
+.\mprj_io_vtrip_sel[36] (mprj_io_vtrip_sel[36]),\
+.\mprj_io_vtrip_sel[37] (mprj_io_vtrip_sel[37])
+
+
+`define MPRJ_IO_SLOW_SEL \
+.\mprj_io_slow_sel[0] (mprj_io_slow_sel[0]),\
+.\mprj_io_slow_sel[1] (mprj_io_slow_sel[1]),\
+.\mprj_io_slow_sel[2] (mprj_io_slow_sel[2]),\
+.\mprj_io_slow_sel[3] (mprj_io_slow_sel[3]),\
+.\mprj_io_slow_sel[4] (mprj_io_slow_sel[4]),\
+.\mprj_io_slow_sel[5] (mprj_io_slow_sel[5]),\
+.\mprj_io_slow_sel[6] (mprj_io_slow_sel[6]),\
+.\mprj_io_slow_sel[7] (mprj_io_slow_sel[7]),\
+.\mprj_io_slow_sel[8] (mprj_io_slow_sel[8]),\
+.\mprj_io_slow_sel[9] (mprj_io_slow_sel[9]),\
+.\mprj_io_slow_sel[10] (mprj_io_slow_sel[10]),\
+.\mprj_io_slow_sel[11] (mprj_io_slow_sel[11]),\
+.\mprj_io_slow_sel[12] (mprj_io_slow_sel[12]),\
+.\mprj_io_slow_sel[13] (mprj_io_slow_sel[13]),\
+.\mprj_io_slow_sel[14] (mprj_io_slow_sel[14]),\
+.\mprj_io_slow_sel[15] (mprj_io_slow_sel[15]),\
+.\mprj_io_slow_sel[16] (mprj_io_slow_sel[16]),\
+.\mprj_io_slow_sel[17] (mprj_io_slow_sel[17]),\
+.\mprj_io_slow_sel[18] (mprj_io_slow_sel[18]),\
+.\mprj_io_slow_sel[19] (mprj_io_slow_sel[19]),\
+.\mprj_io_slow_sel[20] (mprj_io_slow_sel[20]),\
+.\mprj_io_slow_sel[21] (mprj_io_slow_sel[21]),\
+.\mprj_io_slow_sel[22] (mprj_io_slow_sel[22]),\
+.\mprj_io_slow_sel[23] (mprj_io_slow_sel[23]),\
+.\mprj_io_slow_sel[24] (mprj_io_slow_sel[24]),\
+.\mprj_io_slow_sel[25] (mprj_io_slow_sel[25]),\
+.\mprj_io_slow_sel[26] (mprj_io_slow_sel[26]),\
+.\mprj_io_slow_sel[27] (mprj_io_slow_sel[27]),\
+.\mprj_io_slow_sel[28] (mprj_io_slow_sel[28]),\
+.\mprj_io_slow_sel[29] (mprj_io_slow_sel[29]),\
+.\mprj_io_slow_sel[30] (mprj_io_slow_sel[30]),\
+.\mprj_io_slow_sel[31] (mprj_io_slow_sel[31]),\
+.\mprj_io_slow_sel[32] (mprj_io_slow_sel[32]),\
+.\mprj_io_slow_sel[33] (mprj_io_slow_sel[33]),\
+.\mprj_io_slow_sel[34] (mprj_io_slow_sel[34]),\
+.\mprj_io_slow_sel[35] (mprj_io_slow_sel[35]),\
+.\mprj_io_slow_sel[36] (mprj_io_slow_sel[36]),\
+.\mprj_io_slow_sel[37] (mprj_io_slow_sel[37])
+
+
+`define MPRJ_IO_HOLDOVER \
+.\mprj_io_holdover[0] (mprj_io_holdover[0]),\
+.\mprj_io_holdover[1] (mprj_io_holdover[1]),\
+.\mprj_io_holdover[2] (mprj_io_holdover[2]),\
+.\mprj_io_holdover[3] (mprj_io_holdover[3]),\
+.\mprj_io_holdover[4] (mprj_io_holdover[4]),\
+.\mprj_io_holdover[5] (mprj_io_holdover[5]),\
+.\mprj_io_holdover[6] (mprj_io_holdover[6]),\
+.\mprj_io_holdover[7] (mprj_io_holdover[7]),\
+.\mprj_io_holdover[8] (mprj_io_holdover[8]),\
+.\mprj_io_holdover[9] (mprj_io_holdover[9]),\
+.\mprj_io_holdover[10] (mprj_io_holdover[10]),\
+.\mprj_io_holdover[11] (mprj_io_holdover[11]),\
+.\mprj_io_holdover[12] (mprj_io_holdover[12]),\
+.\mprj_io_holdover[13] (mprj_io_holdover[13]),\
+.\mprj_io_holdover[14] (mprj_io_holdover[14]),\
+.\mprj_io_holdover[15] (mprj_io_holdover[15]),\
+.\mprj_io_holdover[16] (mprj_io_holdover[16]),\
+.\mprj_io_holdover[17] (mprj_io_holdover[17]),\
+.\mprj_io_holdover[18] (mprj_io_holdover[18]),\
+.\mprj_io_holdover[19] (mprj_io_holdover[19]),\
+.\mprj_io_holdover[20] (mprj_io_holdover[20]),\
+.\mprj_io_holdover[21] (mprj_io_holdover[21]),\
+.\mprj_io_holdover[22] (mprj_io_holdover[22]),\
+.\mprj_io_holdover[23] (mprj_io_holdover[23]),\
+.\mprj_io_holdover[24] (mprj_io_holdover[24]),\
+.\mprj_io_holdover[25] (mprj_io_holdover[25]),\
+.\mprj_io_holdover[26] (mprj_io_holdover[26]),\
+.\mprj_io_holdover[27] (mprj_io_holdover[27]),\
+.\mprj_io_holdover[28] (mprj_io_holdover[28]),\
+.\mprj_io_holdover[29] (mprj_io_holdover[29]),\
+.\mprj_io_holdover[30] (mprj_io_holdover[30]),\
+.\mprj_io_holdover[31] (mprj_io_holdover[31]),\
+.\mprj_io_holdover[32] (mprj_io_holdover[32]),\
+.\mprj_io_holdover[33] (mprj_io_holdover[33]),\
+.\mprj_io_holdover[34] (mprj_io_holdover[34]),\
+.\mprj_io_holdover[35] (mprj_io_holdover[35]),\
+.\mprj_io_holdover[36] (mprj_io_holdover[36]),\
+.\mprj_io_holdover[37] (mprj_io_holdover[37])
+
+`define MPRJ_IO_ANALOG_EN \
+.\mprj_io_analog_en[0] (mprj_io_analog_en[0]),\
+.\mprj_io_analog_en[1] (mprj_io_analog_en[1]),\
+.\mprj_io_analog_en[2] (mprj_io_analog_en[2]),\
+.\mprj_io_analog_en[3] (mprj_io_analog_en[3]),\
+.\mprj_io_analog_en[4] (mprj_io_analog_en[4]),\
+.\mprj_io_analog_en[5] (mprj_io_analog_en[5]),\
+.\mprj_io_analog_en[6] (mprj_io_analog_en[6]),\
+.\mprj_io_analog_en[7] (mprj_io_analog_en[7]),\
+.\mprj_io_analog_en[8] (mprj_io_analog_en[8]),\
+.\mprj_io_analog_en[9] (mprj_io_analog_en[9]),\
+.\mprj_io_analog_en[10] (mprj_io_analog_en[10]),\
+.\mprj_io_analog_en[11] (mprj_io_analog_en[11]),\
+.\mprj_io_analog_en[12] (mprj_io_analog_en[12]),\
+.\mprj_io_analog_en[13] (mprj_io_analog_en[13]),\
+.\mprj_io_analog_en[14] (mprj_io_analog_en[14]),\
+.\mprj_io_analog_en[15] (mprj_io_analog_en[15]),\
+.\mprj_io_analog_en[16] (mprj_io_analog_en[16]),\
+.\mprj_io_analog_en[17] (mprj_io_analog_en[17]),\
+.\mprj_io_analog_en[18] (mprj_io_analog_en[18]),\
+.\mprj_io_analog_en[19] (mprj_io_analog_en[19]),\
+.\mprj_io_analog_en[20] (mprj_io_analog_en[20]),\
+.\mprj_io_analog_en[21] (mprj_io_analog_en[21]),\
+.\mprj_io_analog_en[22] (mprj_io_analog_en[22]),\
+.\mprj_io_analog_en[23] (mprj_io_analog_en[23]),\
+.\mprj_io_analog_en[24] (mprj_io_analog_en[24]),\
+.\mprj_io_analog_en[25] (mprj_io_analog_en[25]),\
+.\mprj_io_analog_en[26] (mprj_io_analog_en[26]),\
+.\mprj_io_analog_en[27] (mprj_io_analog_en[27]),\
+.\mprj_io_analog_en[28] (mprj_io_analog_en[28]),\
+.\mprj_io_analog_en[29] (mprj_io_analog_en[29]),\
+.\mprj_io_analog_en[30] (mprj_io_analog_en[30]),\
+.\mprj_io_analog_en[31] (mprj_io_analog_en[31]),\
+.\mprj_io_analog_en[32] (mprj_io_analog_en[32]),\
+.\mprj_io_analog_en[33] (mprj_io_analog_en[33]),\
+.\mprj_io_analog_en[34] (mprj_io_analog_en[34]),\
+.\mprj_io_analog_en[35] (mprj_io_analog_en[35]),\
+.\mprj_io_analog_en[36] (mprj_io_analog_en[36]),\
+.\mprj_io_analog_en[37] (mprj_io_analog_en[37])
+
+`define MPRJ_IO_ANALOG_SEL \
+.\mprj_io_analog_sel[0] (mprj_io_analog_sel[0]),\
+.\mprj_io_analog_sel[1] (mprj_io_analog_sel[1]),\
+.\mprj_io_analog_sel[2] (mprj_io_analog_sel[2]),\
+.\mprj_io_analog_sel[3] (mprj_io_analog_sel[3]),\
+.\mprj_io_analog_sel[4] (mprj_io_analog_sel[4]),\
+.\mprj_io_analog_sel[5] (mprj_io_analog_sel[5]),\
+.\mprj_io_analog_sel[6] (mprj_io_analog_sel[6]),\
+.\mprj_io_analog_sel[7] (mprj_io_analog_sel[7]),\
+.\mprj_io_analog_sel[8] (mprj_io_analog_sel[8]),\
+.\mprj_io_analog_sel[9] (mprj_io_analog_sel[9]),\
+.\mprj_io_analog_sel[10] (mprj_io_analog_sel[10]),\
+.\mprj_io_analog_sel[11] (mprj_io_analog_sel[11]),\
+.\mprj_io_analog_sel[12] (mprj_io_analog_sel[12]),\
+.\mprj_io_analog_sel[13] (mprj_io_analog_sel[13]),\
+.\mprj_io_analog_sel[14] (mprj_io_analog_sel[14]),\
+.\mprj_io_analog_sel[15] (mprj_io_analog_sel[15]),\
+.\mprj_io_analog_sel[16] (mprj_io_analog_sel[16]),\
+.\mprj_io_analog_sel[17] (mprj_io_analog_sel[17]),\
+.\mprj_io_analog_sel[18] (mprj_io_analog_sel[18]),\
+.\mprj_io_analog_sel[19] (mprj_io_analog_sel[19]),\
+.\mprj_io_analog_sel[20] (mprj_io_analog_sel[20]),\
+.\mprj_io_analog_sel[21] (mprj_io_analog_sel[21]),\
+.\mprj_io_analog_sel[22] (mprj_io_analog_sel[22]),\
+.\mprj_io_analog_sel[23] (mprj_io_analog_sel[23]),\
+.\mprj_io_analog_sel[24] (mprj_io_analog_sel[24]),\
+.\mprj_io_analog_sel[25] (mprj_io_analog_sel[25]),\
+.\mprj_io_analog_sel[26] (mprj_io_analog_sel[26]),\
+.\mprj_io_analog_sel[27] (mprj_io_analog_sel[27]),\
+.\mprj_io_analog_sel[28] (mprj_io_analog_sel[28]),\
+.\mprj_io_analog_sel[29] (mprj_io_analog_sel[29]),\
+.\mprj_io_analog_sel[30] (mprj_io_analog_sel[30]),\
+.\mprj_io_analog_sel[31] (mprj_io_analog_sel[31]),\
+.\mprj_io_analog_sel[32] (mprj_io_analog_sel[32]),\
+.\mprj_io_analog_sel[33] (mprj_io_analog_sel[33]),\
+.\mprj_io_analog_sel[34] (mprj_io_analog_sel[34]),\
+.\mprj_io_analog_sel[35] (mprj_io_analog_sel[35]),\
+.\mprj_io_analog_sel[36] (mprj_io_analog_sel[36]),\
+.\mprj_io_analog_sel[37] (mprj_io_analog_sel[37])
+
+
+`define MPRJ_IO_ANALOG_POL \
+.\mprj_io_analog_pol[0] (mprj_io_analog_pol[0]),\
+.\mprj_io_analog_pol[1] (mprj_io_analog_pol[1]),\
+.\mprj_io_analog_pol[2] (mprj_io_analog_pol[2]),\
+.\mprj_io_analog_pol[3] (mprj_io_analog_pol[3]),\
+.\mprj_io_analog_pol[4] (mprj_io_analog_pol[4]),\
+.\mprj_io_analog_pol[5] (mprj_io_analog_pol[5]),\
+.\mprj_io_analog_pol[6] (mprj_io_analog_pol[6]),\
+.\mprj_io_analog_pol[7] (mprj_io_analog_pol[7]),\
+.\mprj_io_analog_pol[8] (mprj_io_analog_pol[8]),\
+.\mprj_io_analog_pol[9] (mprj_io_analog_pol[9]),\
+.\mprj_io_analog_pol[10] (mprj_io_analog_pol[10]),\
+.\mprj_io_analog_pol[11] (mprj_io_analog_pol[11]),\
+.\mprj_io_analog_pol[12] (mprj_io_analog_pol[12]),\
+.\mprj_io_analog_pol[13] (mprj_io_analog_pol[13]),\
+.\mprj_io_analog_pol[14] (mprj_io_analog_pol[14]),\
+.\mprj_io_analog_pol[15] (mprj_io_analog_pol[15]),\
+.\mprj_io_analog_pol[16] (mprj_io_analog_pol[16]),\
+.\mprj_io_analog_pol[17] (mprj_io_analog_pol[17]),\
+.\mprj_io_analog_pol[18] (mprj_io_analog_pol[18]),\
+.\mprj_io_analog_pol[19] (mprj_io_analog_pol[19]),\
+.\mprj_io_analog_pol[20] (mprj_io_analog_pol[20]),\
+.\mprj_io_analog_pol[21] (mprj_io_analog_pol[21]),\
+.\mprj_io_analog_pol[22] (mprj_io_analog_pol[22]),\
+.\mprj_io_analog_pol[23] (mprj_io_analog_pol[23]),\
+.\mprj_io_analog_pol[24] (mprj_io_analog_pol[24]),\
+.\mprj_io_analog_pol[25] (mprj_io_analog_pol[25]),\
+.\mprj_io_analog_pol[26] (mprj_io_analog_pol[26]),\
+.\mprj_io_analog_pol[27] (mprj_io_analog_pol[27]),\
+.\mprj_io_analog_pol[28] (mprj_io_analog_pol[28]),\
+.\mprj_io_analog_pol[29] (mprj_io_analog_pol[29]),\
+.\mprj_io_analog_pol[30] (mprj_io_analog_pol[30]),\
+.\mprj_io_analog_pol[31] (mprj_io_analog_pol[31]),\
+.\mprj_io_analog_pol[32] (mprj_io_analog_pol[32]),\
+.\mprj_io_analog_pol[33] (mprj_io_analog_pol[33]),\
+.\mprj_io_analog_pol[34] (mprj_io_analog_pol[34]),\
+.\mprj_io_analog_pol[35] (mprj_io_analog_pol[35]),\
+.\mprj_io_analog_pol[36] (mprj_io_analog_pol[36]),\
+.\mprj_io_analog_pol[37] (mprj_io_analog_pol[37])
+
+`define MPRJ_IO_DM \
+.\mprj_io_dm[0] (mprj_io_dm[0]),\
+.\mprj_io_dm[1] (mprj_io_dm[1]),\
+.\mprj_io_dm[2] (mprj_io_dm[2]),\
+.\mprj_io_dm[3] (mprj_io_dm[3]),\
+.\mprj_io_dm[4] (mprj_io_dm[4]),\
+.\mprj_io_dm[5] (mprj_io_dm[5]),\
+.\mprj_io_dm[6] (mprj_io_dm[6]),\
+.\mprj_io_dm[7] (mprj_io_dm[7]),\
+.\mprj_io_dm[8] (mprj_io_dm[8]),\
+.\mprj_io_dm[9] (mprj_io_dm[9]),\
+.\mprj_io_dm[10] (mprj_io_dm[10]),\
+.\mprj_io_dm[11] (mprj_io_dm[11]),\
+.\mprj_io_dm[12] (mprj_io_dm[12]),\
+.\mprj_io_dm[13] (mprj_io_dm[13]),\
+.\mprj_io_dm[14] (mprj_io_dm[14]),\
+.\mprj_io_dm[15] (mprj_io_dm[15]),\
+.\mprj_io_dm[16] (mprj_io_dm[16]),\
+.\mprj_io_dm[17] (mprj_io_dm[17]),\
+.\mprj_io_dm[18] (mprj_io_dm[18]),\
+.\mprj_io_dm[19] (mprj_io_dm[19]),\
+.\mprj_io_dm[20] (mprj_io_dm[20]),\
+.\mprj_io_dm[21] (mprj_io_dm[21]),\
+.\mprj_io_dm[22] (mprj_io_dm[22]),\
+.\mprj_io_dm[23] (mprj_io_dm[23]),\
+.\mprj_io_dm[24] (mprj_io_dm[24]),\
+.\mprj_io_dm[25] (mprj_io_dm[25]),\
+.\mprj_io_dm[26] (mprj_io_dm[26]),\
+.\mprj_io_dm[27] (mprj_io_dm[27]),\
+.\mprj_io_dm[28] (mprj_io_dm[28]),\
+.\mprj_io_dm[29] (mprj_io_dm[29]),\
+.\mprj_io_dm[30] (mprj_io_dm[30]),\
+.\mprj_io_dm[31] (mprj_io_dm[31]),\
+.\mprj_io_dm[32] (mprj_io_dm[32]),\
+.\mprj_io_dm[33] (mprj_io_dm[33]),\
+.\mprj_io_dm[34] (mprj_io_dm[34]),\
+.\mprj_io_dm[35] (mprj_io_dm[35]),\
+.\mprj_io_dm[36] (mprj_io_dm[36]),\
+.\mprj_io_dm[37] (mprj_io_dm[37]),\
+.\mprj_io_dm[38] (mprj_io_dm[38]),\
+.\mprj_io_dm[39] (mprj_io_dm[39]),\
+.\mprj_io_dm[40] (mprj_io_dm[40]),\
+.\mprj_io_dm[41] (mprj_io_dm[41]),\
+.\mprj_io_dm[42] (mprj_io_dm[42]),\
+.\mprj_io_dm[43] (mprj_io_dm[43]),\
+.\mprj_io_dm[44] (mprj_io_dm[44]),\
+.\mprj_io_dm[45] (mprj_io_dm[45]),\
+.\mprj_io_dm[46] (mprj_io_dm[46]),\
+.\mprj_io_dm[47] (mprj_io_dm[47]),\
+.\mprj_io_dm[48] (mprj_io_dm[48]),\
+.\mprj_io_dm[49] (mprj_io_dm[49]),\
+.\mprj_io_dm[50] (mprj_io_dm[50]),\
+.\mprj_io_dm[51] (mprj_io_dm[51]),\
+.\mprj_io_dm[52] (mprj_io_dm[52]),\
+.\mprj_io_dm[53] (mprj_io_dm[53]),\
+.\mprj_io_dm[54] (mprj_io_dm[54]),\
+.\mprj_io_dm[55] (mprj_io_dm[55]),\
+.\mprj_io_dm[56] (mprj_io_dm[56]),\
+.\mprj_io_dm[57] (mprj_io_dm[57]),\
+.\mprj_io_dm[58] (mprj_io_dm[58]),\
+.\mprj_io_dm[59] (mprj_io_dm[59]),\
+.\mprj_io_dm[60] (mprj_io_dm[60]),\
+.\mprj_io_dm[61] (mprj_io_dm[61]),\
+.\mprj_io_dm[62] (mprj_io_dm[62]),\
+.\mprj_io_dm[63] (mprj_io_dm[63]),\
+.\mprj_io_dm[64] (mprj_io_dm[64]),\
+.\mprj_io_dm[65] (mprj_io_dm[65]),\
+.\mprj_io_dm[66] (mprj_io_dm[66]),\
+.\mprj_io_dm[67] (mprj_io_dm[67]),\
+.\mprj_io_dm[68] (mprj_io_dm[68]),\
+.\mprj_io_dm[69] (mprj_io_dm[69]),\
+.\mprj_io_dm[70] (mprj_io_dm[70]),\
+.\mprj_io_dm[71] (mprj_io_dm[71]),\
+.\mprj_io_dm[72] (mprj_io_dm[72]),\
+.\mprj_io_dm[73] (mprj_io_dm[73]),\
+.\mprj_io_dm[74] (mprj_io_dm[74]),\
+.\mprj_io_dm[75] (mprj_io_dm[75]),\
+.\mprj_io_dm[76] (mprj_io_dm[76]),\
+.\mprj_io_dm[77] (mprj_io_dm[77]),\
+.\mprj_io_dm[78] (mprj_io_dm[78]),\
+.\mprj_io_dm[79] (mprj_io_dm[79]),\
+.\mprj_io_dm[80] (mprj_io_dm[80]),\
+.\mprj_io_dm[81] (mprj_io_dm[81]),\
+.\mprj_io_dm[82] (mprj_io_dm[82]),\
+.\mprj_io_dm[83] (mprj_io_dm[83]),\
+.\mprj_io_dm[84] (mprj_io_dm[84]),\
+.\mprj_io_dm[85] (mprj_io_dm[85]),\
+.\mprj_io_dm[86] (mprj_io_dm[86]),\
+.\mprj_io_dm[87] (mprj_io_dm[87]),\
+.\mprj_io_dm[88] (mprj_io_dm[88]),\
+.\mprj_io_dm[89] (mprj_io_dm[89]),\
+.\mprj_io_dm[90] (mprj_io_dm[90]),\
+.\mprj_io_dm[91] (mprj_io_dm[91]),\
+.\mprj_io_dm[92] (mprj_io_dm[92]),\
+.\mprj_io_dm[93] (mprj_io_dm[93]),\
+.\mprj_io_dm[94] (mprj_io_dm[94]),\
+.\mprj_io_dm[95] (mprj_io_dm[95]),\
+.\mprj_io_dm[96] (mprj_io_dm[96]),\
+.\mprj_io_dm[97] (mprj_io_dm[97]),\
+.\mprj_io_dm[98] (mprj_io_dm[98]),\
+.\mprj_io_dm[99] (mprj_io_dm[99]),\
+.\mprj_io_dm[100] (mprj_io_dm[100]),\
+.\mprj_io_dm[101] (mprj_io_dm[101]),\
+.\mprj_io_dm[102] (mprj_io_dm[102]),\
+.\mprj_io_dm[103] (mprj_io_dm[103]),\
+.\mprj_io_dm[104] (mprj_io_dm[104]),\
+.\mprj_io_dm[105] (mprj_io_dm[105]),\
+.\mprj_io_dm[106] (mprj_io_dm[106]),\
+.\mprj_io_dm[107] (mprj_io_dm[107]),\
+.\mprj_io_dm[108] (mprj_io_dm[108]),\
+.\mprj_io_dm[109] (mprj_io_dm[109]),\
+.\mprj_io_dm[110] (mprj_io_dm[110]),\
+.\mprj_io_dm[111] (mprj_io_dm[111]),\
+.\mprj_io_dm[112] (mprj_io_dm[112]),\
+.\mprj_io_dm[113] (mprj_io_dm[113])
+
+`define MPRJ_IO_ANALOG \
+.\mprj_analog_io[0] (mprj_analog_io[0]),\
+.\mprj_analog_io[1] (mprj_analog_io[1]),\
+.\mprj_analog_io[2] (mprj_analog_io[2]),\
+.\mprj_analog_io[3] (mprj_analog_io[3]),\
+.\mprj_analog_io[4] (mprj_analog_io[4]),\
+.\mprj_analog_io[5] (mprj_analog_io[5]),\
+.\mprj_analog_io[6] (mprj_analog_io[6]),\
+.\mprj_analog_io[7] (mprj_analog_io[7]),\
+.\mprj_analog_io[8] (mprj_analog_io[8]),\
+.\mprj_analog_io[9] (mprj_analog_io[9]),\
+.\mprj_analog_io[10] (mprj_analog_io[10]),\
+.\mprj_analog_io[11] (mprj_analog_io[11]),\
+.\mprj_analog_io[12] (mprj_analog_io[12]),\
+.\mprj_analog_io[13] (mprj_analog_io[13]),\
+.\mprj_analog_io[14] (mprj_analog_io[14]),\
+.\mprj_analog_io[15] (mprj_analog_io[15]),\
+.\mprj_analog_io[16] (mprj_analog_io[16]),\
+.\mprj_analog_io[17] (mprj_analog_io[17]),\
+.\mprj_analog_io[18] (mprj_analog_io[18]),\
+.\mprj_analog_io[19] (mprj_analog_io[19]),\
+.\mprj_analog_io[20] (mprj_analog_io[20]),\
+.\mprj_analog_io[21] (mprj_analog_io[21]),\
+.\mprj_analog_io[22] (mprj_analog_io[22]),\
+.\mprj_analog_io[23] (mprj_analog_io[23]),\
+.\mprj_analog_io[24] (mprj_analog_io[24]),\
+.\mprj_analog_io[25] (mprj_analog_io[25]),\
+.\mprj_analog_io[26] (mprj_analog_io[26]),\
+.\mprj_analog_io[27] (mprj_analog_io[27]),\
+.\mprj_analog_io[28] (mprj_analog_io[28]),\
+.\mprj_analog_io[29] (mprj_analog_io[29]),\
+.\mprj_analog_io[30] (mprj_analog_io[30])
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile b/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile
new file mode 100644
index 0000000..7dd7866
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mgmt_protect/Makefile
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = mgmt_protect
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp check-env
+ vvp $<
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+ rm -f *.vvp *.vcd
+
+.PHONY: clean all
diff --git a/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
new file mode 100644
index 0000000..accae33
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -0,0 +1,263 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`include "defines.v"
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+`else
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+`endif
+
+module mgmt_protect_tb;
+
+ reg caravel_clk;
+ reg caravel_clk2;
+ reg caravel_rstn;
+
+ reg mprj_cyc_o_core;
+ reg mprj_stb_o_core;
+ reg mprj_we_o_core;
+ reg [31:0] mprj_adr_o_core;
+ reg [31:0] mprj_dat_o_core;
+ reg [3:0] mprj_sel_o_core;
+
+ wire [127:0] la_data_in_mprj;
+ reg [127:0] la_data_out_mprj;
+ reg [127:0] la_oenb_mprj;
+ reg [127:0] la_iena_mprj;
+
+ reg [127:0] la_data_out_core;
+ wire [127:0] la_data_in_core;
+ wire [127:0] la_oenb_core;
+
+ wire user_clock;
+ wire user_clock2;
+ wire user_reset;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire user1_vcc_powergood;
+ wire user2_vcc_powergood;
+ wire user1_vdd_powergood;
+ wire user2_vdd_powergood;
+
+ always #12.5 caravel_clk <= (caravel_clk === 1'b0);
+ always #12.5 caravel_clk2 <= (caravel_clk2 === 1'b0);
+
+ initial begin
+ caravel_clk = 0;
+ caravel_clk2 = 0;
+ caravel_rstn = 0;
+
+ mprj_cyc_o_core = 0;
+ mprj_stb_o_core = 0;
+ mprj_we_o_core = 0;
+ mprj_adr_o_core = 0;
+ mprj_dat_o_core = 0;
+ mprj_sel_o_core = 0;
+
+ la_data_out_mprj = 0;
+ la_oenb_mprj = 0;
+ la_data_out_core = 0;
+ end
+
+ reg USER_VDD3V3;
+ reg USER_VDD1V8;
+ reg VDD3V3;
+ reg VDD1V8;
+
+ wire VCCD; // Management/Common 1.8V power
+ wire VSSD; // Common digital ground
+
+ wire VCCD1; // User area 1 1.8V power
+ wire VSSD1; // User area 1 digital ground
+ wire VCCD2; // User area 2 1.8V power
+ wire VSSD2; // User area 2 digital ground
+
+ wire VDDA1; // User area 1 3.3V power
+ wire VSSA1; // User area 1 analog ground
+ wire VDDA2; // User area 2 3.3V power
+ wire VSSA2; // User area 2 analog ground
+
+ assign VCCD = VDD1V8;
+ assign VSSD = 1'b0;
+
+ assign VCCD1 = USER_VDD1V8;
+ assign VSSD1 = 1'b0;
+
+ assign VCCD2 = USER_VDD1V8;
+ assign VSSD2 = 1'b0;
+
+ assign VDDA1 = USER_VDD3V3;
+ assign VSSA1 = 1'b0;
+
+ assign VDDA2 = USER_VDD3V3;
+ assign VSSA2 = 1'b0;
+
+ initial begin // Power-up sequence
+ VDD1V8 <= 1'b0;
+ USER_VDD3V3 <= 1'b0;
+ USER_VDD1V8 <= 1'b0;
+ #200;
+ VDD1V8 <= 1'b1;
+ #200;
+ USER_VDD3V3 <= 1'b1;
+ #200;
+ USER_VDD1V8 <= 1'b1;
+ end
+
+ initial begin
+ $dumpfile("mgmt_protect.vcd");
+ $dumpvars(0, mgmt_protect_tb);
+ #(`SIM_TIME);
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Management Protect Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ initial begin
+ caravel_rstn = 1'b1;
+ mprj_cyc_o_core = 1'b1;
+ mprj_stb_o_core = 1'b1;
+ mprj_we_o_core = 1'b1;
+ mprj_sel_o_core = 4'b1010;
+ mprj_adr_o_core = 32'hF0F0;
+ mprj_dat_o_core = 32'h0F0F;
+ la_data_out_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
+ la_oenb_mprj = 128'h0000_0000_0000_0000;
+ la_data_out_core = 128'h0F0F_FFFF_F0F0_FFFF;
+ la_iena_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
+
+ wait(user1_vdd_powergood === 1'b1);
+ wait(user2_vdd_powergood === 1'b1);
+ wait(user1_vcc_powergood === 1'b1);
+ wait(user2_vcc_powergood === 1'b1);
+ #25;
+ if (user_reset !== ~caravel_rstn) begin
+ $display("Monitor: Error on user_reset. "); $finish;
+ end
+ if (mprj_cyc_o_user !== mprj_cyc_o_core) begin
+ $display("Monitor: Error on mprj_cyc_o_user. "); $finish;
+ end
+ if (mprj_stb_o_user !== mprj_stb_o_core) begin
+ $display("Monitor: Error on mprj_stb_o_user. "); $finish;
+ end
+ if (mprj_we_o_user !== mprj_we_o_core) begin
+ $display("Monitor: Error on mprj_we_o_user. "); $finish;
+ end
+ if (mprj_sel_o_user !== mprj_sel_o_core) begin
+ $display("Monitor: Error on mprj_sel_o_user. "); $finish;
+ end
+ if (mprj_adr_o_user !== mprj_adr_o_core) begin
+ $display("Monitor: Error on mprj_adr_o_user. "); $finish;
+ end
+ if (la_data_in_core !== la_data_out_mprj) begin
+ $display("%0h", la_data_in_core);
+ $display("Monitor: Error on la_data_in_core. "); $finish;
+ end
+ if (la_oenb_core !== la_oenb_mprj) begin
+ $display("Monitor: Error on la_oenb_core. "); $finish;
+ end
+ if (la_data_in_mprj !== la_data_out_core) begin
+ $display("%0h , %0h", la_data_in_mprj, la_data_out_core);
+ $display("Monitor: Error on la_data_in_mprj. "); $finish;
+ end
+ $display ("Success!");
+ $display ("Monitor: Test Management Protect Passed");
+ $finish;
+ end
+
+ mgmt_protect uut (
+ `ifdef USE_POWER_PINS
+ .vccd(VCCD),
+ .vssd(VSSD),
+ .vccd1(VCCD1),
+ .vssd1(VSSD1),
+ .vccd2(VCCD2),
+ .vssd2(VSSD2),
+ .vdda1(VDDA1),
+ .vssa1(VSSA1),
+ .vdda2(VDDA2),
+ .vssa2(VSSA2),
+ `endif
+
+ .caravel_clk (caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core (mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+
+ .la_data_out_core(la_data_out_core),
+ .la_data_in_core (la_data_in_core),
+ .la_oenb_core(la_oenb_core),
+
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_iena_mprj(la_iena_mprj),
+
+ .user_clock (user_clock),
+ .user_clock2(user_clock2),
+ .user_reset (user_reset),
+
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user (mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+
+ .user1_vcc_powergood(user1_vcc_powergood),
+ .user2_vcc_powergood(user2_vcc_powergood),
+ .user1_vdd_powergood(user1_vdd_powergood),
+ .user2_vdd_powergood(user2_vdd_powergood)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile b/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile
new file mode 100644
index 0000000..f354018
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile
@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file
diff --git a/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..5f656f0
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,168 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+`include "housekeeping_spi.v"
+`include "housekeeping.v"
+
+module mprj_ctrl_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ reg porb;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ // Mega Project Control Registers
+ wire [31:0] mprj_ctrl = uut.GPIO_BASE_ADR | 8'h24;
+ wire [31:0] pwr_ctrl = uut.GPIO_BASE_ADR | 8'h04;
+
+ initial begin
+ $dumpfile("mprj_ctrl_tb.vcd");
+ $dumpvars(0, mprj_ctrl_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ reg [31:0] data;
+
+ initial begin
+ // Reset Operation
+ porb = 0;
+ wb_rst_i = 1;
+ #2;
+ porb = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
+ data = $urandom_range(0, 2**(7));
+ write(mprj_ctrl+i*4, data);
+ #20;
+ read(mprj_ctrl+i*4);
+ #20;
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from IO-CTRL Failed.");
+ $finish;
+ end
+ end
+
+ data = $urandom_range(0, 2**(`MPRJ_PWR_PADS-2));
+ write(pwr_ctrl, data);
+ #20;
+ read(pwr_ctrl);
+ #20;
+ if (wb_dat_o !== data) begin
+ $display("Monitor: R/W from POWER-CTRL Failed.");
+ $finish;
+ end
+
+
+ $display("Success!");
+ $display ("Monitor: Test Mega-Project Control Passed");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Read Cycle Ended.");
+ end
+ endtask
+
+ housekeeping uut(
+ .porb(porb),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
diff --git a/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile b/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile
new file mode 100644
index 0000000..89aa77b
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile
@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = sysctrl_wb
+
+all: ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ iverilog -I ../../../rtl \
+ $< -o $@
+
+%.vcd: %.vvp
+ vvp $<
+
+clean:
+ rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+
diff --git a/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
new file mode 100644
index 0000000..a4c9a17
--- /dev/null
+++ b/caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -0,0 +1,173 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+
+`include "housekeeping_spi.v"
+`include "housekeeping.v"
+
+module sysctrl_wb_tb;
+
+ reg wb_clk_i;
+ reg wb_rst_i;
+
+ reg wb_stb_i;
+ reg wb_cyc_i;
+ reg wb_we_i;
+ reg [3:0] wb_sel_i;
+ reg [31:0] wb_dat_i;
+ reg [31:0] wb_adr_i;
+
+ reg porb;
+
+ wire wb_ack_o;
+ wire [31:0] wb_dat_o;
+
+ initial begin
+ wb_clk_i = 0;
+ wb_rst_i = 0;
+ wb_stb_i = 0;
+ wb_cyc_i = 0;
+ wb_sel_i = 0;
+ wb_we_i = 0;
+ wb_dat_i = 0;
+ wb_adr_i = 0;
+ end
+
+ always #1 wb_clk_i = ~wb_clk_i;
+
+ initial begin
+ $dumpfile("sysctrl_wb_tb.vcd");
+ $dumpvars(0, sysctrl_wb_tb);
+ repeat (50) begin
+ repeat (1000) @(posedge wb_clk_i);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test System Control Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ integer i;
+
+ // System Control Default Register Addresses
+ wire [31:0] clk_out_adr = uut.SYS_BASE_ADR | 8'h04;
+ wire [31:0] irq_src_adr = uut.SYS_BASE_ADR | 8'h0c;
+
+ reg clk1_output_dest;
+ reg [1:0] clk2_output_dest;
+ reg [2:0] trap_output_dest;
+ reg irq_7_inputsrc;
+ reg [1:0] irq_8_inputsrc;
+
+ initial begin
+ // Reset Operation
+ porb = 0;
+ wb_rst_i = 1;
+ #2;
+ porb = 1;
+ #2;
+ wb_rst_i = 0;
+ #2;
+
+ clk1_output_dest = 1'b1;
+ clk2_output_dest = 2'b10;
+ trap_output_dest = 3'b100;
+ irq_7_inputsrc = 1'b1;
+ irq_8_inputsrc = 2'b10;
+
+ // Write to System Control Registers
+ write(clk_out_adr, clk2_output_dest);
+ #20;
+ write(irq_src_adr, irq_7_inputsrc);
+ #20;
+ read(clk_out_adr);
+ if (wb_dat_o !== clk2_output_dest) begin
+ $display("Error reading CLK1 output destination register.");
+ $finish;
+ end
+
+ #20;
+ read(irq_src_adr);
+ if (wb_dat_o !== irq_7_inputsrc) begin
+ $display("Error reading IRQ7 input source register.");
+ $finish;
+ end
+
+ $display("Success!");
+ $display ("Monitor: Test System Control Passed!");
+ $finish;
+ end
+
+ task write;
+ input [32:0] addr;
+ input [32:0] data;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_sel_i = 4'hF;
+ wb_we_i = 1;
+ wb_adr_i = addr;
+ wb_dat_i = data;
+ $display("Monitor: Write Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Write Cycle Ended.");
+ end
+ endtask
+
+ task read;
+ input [32:0] addr;
+ begin
+ @(posedge wb_clk_i) begin
+ wb_stb_i = 1;
+ wb_cyc_i = 1;
+ wb_we_i = 0;
+ wb_adr_i = addr;
+ $display("Monitor: Read Cycle Started.");
+ end
+ // Wait for an ACK
+ wait(wb_ack_o == 1);
+ wait(wb_ack_o == 0);
+ wb_cyc_i = 0;
+ wb_stb_i = 0;
+ $display("Monitor: Read Cycle Ended.");
+ end
+ endtask
+
+ housekeeping uut(
+ .porb(porb),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_sel_i(wb_sel_i),
+ .wb_we_i(wb_we_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_ack_o(wb_ack_o),
+ .wb_dat_o(wb_dat_o)
+ );
+
+endmodule
diff --git a/caravel/verilog/gl/__user_analog_project_wrapper.v b/caravel/verilog/gl/__user_analog_project_wrapper.v
new file mode 100644
index 0000000..6360f0b
--- /dev/null
+++ b/caravel/verilog/gl/__user_analog_project_wrapper.v
@@ -0,0 +1,124 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+// Dummy assignment so that we can take it through the openlane flow
+assign io_out = io_in;
+
+endmodule // user_analog_project_wrapper
diff --git a/caravel/verilog/gl/__user_project_wrapper.v b/caravel/verilog/gl/__user_project_wrapper.v
new file mode 100644
index 0000000..763c2bf
--- /dev/null
+++ b/caravel/verilog/gl/__user_project_wrapper.v
@@ -0,0 +1,91 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+
+// Dummy assignments so that we can take it through the openlane flow
+`ifdef SIM
+// Needed for running GL simulation
+assign io_out = 0;
+assign io_oeb = 0;
+`else
+assign io_out = io_in;
+`endif
+
+endmodule // user_project_wrapper
diff --git a/caravel/verilog/gl/caravan.v b/caravel/verilog/gl/caravan.v
new file mode 100644
index 0000000..c037c1f
--- /dev/null
+++ b/caravel/verilog/gl/caravan.v
@@ -0,0 +1,4306 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+ input clock;
+ wire clock_core;
+ wire debug_in;
+ wire debug_mode;
+ wire debug_oeb;
+ wire debug_out;
+ wire ext_clk_sel;
+ wire ext_reset;
+ output flash_clk;
+ wire flash_clk_core;
+ wire flash_clk_frame;
+ wire flash_clk_ieb;
+ wire flash_clk_ieb_core;
+ wire flash_clk_oeb;
+ wire flash_clk_oeb_core;
+ output flash_csb;
+ wire flash_csb_core;
+ wire flash_csb_frame;
+ wire flash_csb_ieb;
+ wire flash_csb_ieb_core;
+ wire flash_csb_oeb;
+ wire flash_csb_oeb_core;
+ output flash_io0;
+ wire flash_io0_di;
+ wire flash_io0_di_core;
+ wire flash_io0_do;
+ wire flash_io0_do_core;
+ wire flash_io0_ieb;
+ wire flash_io0_ieb_core;
+ wire flash_io0_oeb;
+ wire flash_io0_oeb_core;
+ output flash_io1;
+ wire flash_io1_di;
+ wire flash_io1_di_core;
+ wire flash_io1_do;
+ wire flash_io1_do_core;
+ wire flash_io1_ieb;
+ wire flash_io1_ieb_core;
+ wire flash_io1_oeb;
+ wire flash_io1_oeb_core;
+ wire flash_io2_di_core;
+ wire flash_io2_do_core;
+ wire flash_io2_ieb_core;
+ wire flash_io2_oeb_core;
+ wire flash_io3_di_core;
+ wire flash_io3_do_core;
+ wire flash_io3_ieb_core;
+ wire flash_io3_oeb_core;
+ inout gpio;
+ wire \gpio_clock_1[0] ;
+ wire \gpio_clock_1[10] ;
+ wire \gpio_clock_1[11] ;
+ wire \gpio_clock_1[12] ;
+ wire \gpio_clock_1[13] ;
+ wire \gpio_clock_1[14] ;
+ wire \gpio_clock_1[15] ;
+ wire \gpio_clock_1[16] ;
+ wire \gpio_clock_1[17] ;
+ wire \gpio_clock_1[18] ;
+ wire \gpio_clock_1[1] ;
+ wire \gpio_clock_1[2] ;
+ wire \gpio_clock_1[3] ;
+ wire \gpio_clock_1[4] ;
+ wire \gpio_clock_1[5] ;
+ wire \gpio_clock_1[6] ;
+ wire \gpio_clock_1[7] ;
+ wire \gpio_clock_1[8] ;
+ wire \gpio_clock_1[9] ;
+ wire \gpio_clock_1_shifted[0] ;
+ wire \gpio_clock_1_shifted[10] ;
+ wire \gpio_clock_1_shifted[11] ;
+ wire \gpio_clock_1_shifted[12] ;
+ wire \gpio_clock_1_shifted[13] ;
+ wire \gpio_clock_1_shifted[1] ;
+ wire \gpio_clock_1_shifted[2] ;
+ wire \gpio_clock_1_shifted[3] ;
+ wire \gpio_clock_1_shifted[4] ;
+ wire \gpio_clock_1_shifted[5] ;
+ wire \gpio_clock_1_shifted[6] ;
+ wire \gpio_clock_1_shifted[7] ;
+ wire \gpio_clock_1_shifted[8] ;
+ wire \gpio_clock_1_shifted[9] ;
+ wire \gpio_clock_2[0] ;
+ wire \gpio_clock_2[10] ;
+ wire \gpio_clock_2[11] ;
+ wire \gpio_clock_2[12] ;
+ wire \gpio_clock_2[13] ;
+ wire \gpio_clock_2[14] ;
+ wire \gpio_clock_2[15] ;
+ wire \gpio_clock_2[16] ;
+ wire \gpio_clock_2[17] ;
+ wire \gpio_clock_2[18] ;
+ wire \gpio_clock_2[1] ;
+ wire \gpio_clock_2[2] ;
+ wire \gpio_clock_2[3] ;
+ wire \gpio_clock_2[4] ;
+ wire \gpio_clock_2[5] ;
+ wire \gpio_clock_2[6] ;
+ wire \gpio_clock_2[7] ;
+ wire \gpio_clock_2[8] ;
+ wire \gpio_clock_2[9] ;
+ wire \gpio_clock_2_shifted[0] ;
+ wire \gpio_clock_2_shifted[10] ;
+ wire \gpio_clock_2_shifted[11] ;
+ wire \gpio_clock_2_shifted[12] ;
+ wire \gpio_clock_2_shifted[1] ;
+ wire \gpio_clock_2_shifted[2] ;
+ wire \gpio_clock_2_shifted[3] ;
+ wire \gpio_clock_2_shifted[4] ;
+ wire \gpio_clock_2_shifted[5] ;
+ wire \gpio_clock_2_shifted[6] ;
+ wire \gpio_clock_2_shifted[7] ;
+ wire \gpio_clock_2_shifted[8] ;
+ wire \gpio_clock_2_shifted[9] ;
+ wire \gpio_defaults[0] ;
+ wire \gpio_defaults[100] ;
+ wire \gpio_defaults[101] ;
+ wire \gpio_defaults[102] ;
+ wire \gpio_defaults[103] ;
+ wire \gpio_defaults[104] ;
+ wire \gpio_defaults[105] ;
+ wire \gpio_defaults[106] ;
+ wire \gpio_defaults[107] ;
+ wire \gpio_defaults[108] ;
+ wire \gpio_defaults[109] ;
+ wire \gpio_defaults[10] ;
+ wire \gpio_defaults[110] ;
+ wire \gpio_defaults[111] ;
+ wire \gpio_defaults[112] ;
+ wire \gpio_defaults[113] ;
+ wire \gpio_defaults[114] ;
+ wire \gpio_defaults[115] ;
+ wire \gpio_defaults[116] ;
+ wire \gpio_defaults[117] ;
+ wire \gpio_defaults[118] ;
+ wire \gpio_defaults[119] ;
+ wire \gpio_defaults[11] ;
+ wire \gpio_defaults[120] ;
+ wire \gpio_defaults[121] ;
+ wire \gpio_defaults[122] ;
+ wire \gpio_defaults[123] ;
+ wire \gpio_defaults[124] ;
+ wire \gpio_defaults[125] ;
+ wire \gpio_defaults[126] ;
+ wire \gpio_defaults[127] ;
+ wire \gpio_defaults[128] ;
+ wire \gpio_defaults[129] ;
+ wire \gpio_defaults[12] ;
+ wire \gpio_defaults[130] ;
+ wire \gpio_defaults[131] ;
+ wire \gpio_defaults[132] ;
+ wire \gpio_defaults[133] ;
+ wire \gpio_defaults[134] ;
+ wire \gpio_defaults[135] ;
+ wire \gpio_defaults[136] ;
+ wire \gpio_defaults[137] ;
+ wire \gpio_defaults[138] ;
+ wire \gpio_defaults[139] ;
+ wire \gpio_defaults[13] ;
+ wire \gpio_defaults[140] ;
+ wire \gpio_defaults[141] ;
+ wire \gpio_defaults[142] ;
+ wire \gpio_defaults[143] ;
+ wire \gpio_defaults[144] ;
+ wire \gpio_defaults[145] ;
+ wire \gpio_defaults[146] ;
+ wire \gpio_defaults[147] ;
+ wire \gpio_defaults[148] ;
+ wire \gpio_defaults[149] ;
+ wire \gpio_defaults[14] ;
+ wire \gpio_defaults[150] ;
+ wire \gpio_defaults[151] ;
+ wire \gpio_defaults[152] ;
+ wire \gpio_defaults[153] ;
+ wire \gpio_defaults[154] ;
+ wire \gpio_defaults[155] ;
+ wire \gpio_defaults[156] ;
+ wire \gpio_defaults[157] ;
+ wire \gpio_defaults[158] ;
+ wire \gpio_defaults[159] ;
+ wire \gpio_defaults[15] ;
+ wire \gpio_defaults[160] ;
+ wire \gpio_defaults[161] ;
+ wire \gpio_defaults[162] ;
+ wire \gpio_defaults[163] ;
+ wire \gpio_defaults[164] ;
+ wire \gpio_defaults[165] ;
+ wire \gpio_defaults[166] ;
+ wire \gpio_defaults[167] ;
+ wire \gpio_defaults[168] ;
+ wire \gpio_defaults[169] ;
+ wire \gpio_defaults[16] ;
+ wire \gpio_defaults[170] ;
+ wire \gpio_defaults[171] ;
+ wire \gpio_defaults[172] ;
+ wire \gpio_defaults[173] ;
+ wire \gpio_defaults[174] ;
+ wire \gpio_defaults[175] ;
+ wire \gpio_defaults[176] ;
+ wire \gpio_defaults[177] ;
+ wire \gpio_defaults[178] ;
+ wire \gpio_defaults[179] ;
+ wire \gpio_defaults[17] ;
+ wire \gpio_defaults[180] ;
+ wire \gpio_defaults[181] ;
+ wire \gpio_defaults[182] ;
+ wire \gpio_defaults[183] ;
+ wire \gpio_defaults[184] ;
+ wire \gpio_defaults[185] ;
+ wire \gpio_defaults[186] ;
+ wire \gpio_defaults[187] ;
+ wire \gpio_defaults[188] ;
+ wire \gpio_defaults[189] ;
+ wire \gpio_defaults[18] ;
+ wire \gpio_defaults[190] ;
+ wire \gpio_defaults[191] ;
+ wire \gpio_defaults[192] ;
+ wire \gpio_defaults[193] ;
+ wire \gpio_defaults[194] ;
+ wire \gpio_defaults[195] ;
+ wire \gpio_defaults[196] ;
+ wire \gpio_defaults[197] ;
+ wire \gpio_defaults[198] ;
+ wire \gpio_defaults[199] ;
+ wire \gpio_defaults[19] ;
+ wire \gpio_defaults[1] ;
+ wire \gpio_defaults[200] ;
+ wire \gpio_defaults[201] ;
+ wire \gpio_defaults[202] ;
+ wire \gpio_defaults[203] ;
+ wire \gpio_defaults[204] ;
+ wire \gpio_defaults[205] ;
+ wire \gpio_defaults[206] ;
+ wire \gpio_defaults[207] ;
+ wire \gpio_defaults[208] ;
+ wire \gpio_defaults[209] ;
+ wire \gpio_defaults[20] ;
+ wire \gpio_defaults[210] ;
+ wire \gpio_defaults[211] ;
+ wire \gpio_defaults[212] ;
+ wire \gpio_defaults[213] ;
+ wire \gpio_defaults[214] ;
+ wire \gpio_defaults[215] ;
+ wire \gpio_defaults[216] ;
+ wire \gpio_defaults[217] ;
+ wire \gpio_defaults[218] ;
+ wire \gpio_defaults[219] ;
+ wire \gpio_defaults[21] ;
+ wire \gpio_defaults[220] ;
+ wire \gpio_defaults[221] ;
+ wire \gpio_defaults[222] ;
+ wire \gpio_defaults[223] ;
+ wire \gpio_defaults[224] ;
+ wire \gpio_defaults[225] ;
+ wire \gpio_defaults[226] ;
+ wire \gpio_defaults[227] ;
+ wire \gpio_defaults[228] ;
+ wire \gpio_defaults[229] ;
+ wire \gpio_defaults[22] ;
+ wire \gpio_defaults[230] ;
+ wire \gpio_defaults[231] ;
+ wire \gpio_defaults[232] ;
+ wire \gpio_defaults[233] ;
+ wire \gpio_defaults[234] ;
+ wire \gpio_defaults[235] ;
+ wire \gpio_defaults[236] ;
+ wire \gpio_defaults[237] ;
+ wire \gpio_defaults[238] ;
+ wire \gpio_defaults[239] ;
+ wire \gpio_defaults[23] ;
+ wire \gpio_defaults[240] ;
+ wire \gpio_defaults[241] ;
+ wire \gpio_defaults[242] ;
+ wire \gpio_defaults[243] ;
+ wire \gpio_defaults[244] ;
+ wire \gpio_defaults[245] ;
+ wire \gpio_defaults[246] ;
+ wire \gpio_defaults[247] ;
+ wire \gpio_defaults[248] ;
+ wire \gpio_defaults[249] ;
+ wire \gpio_defaults[24] ;
+ wire \gpio_defaults[250] ;
+ wire \gpio_defaults[251] ;
+ wire \gpio_defaults[252] ;
+ wire \gpio_defaults[253] ;
+ wire \gpio_defaults[254] ;
+ wire \gpio_defaults[255] ;
+ wire \gpio_defaults[256] ;
+ wire \gpio_defaults[257] ;
+ wire \gpio_defaults[258] ;
+ wire \gpio_defaults[259] ;
+ wire \gpio_defaults[25] ;
+ wire \gpio_defaults[260] ;
+ wire \gpio_defaults[261] ;
+ wire \gpio_defaults[262] ;
+ wire \gpio_defaults[263] ;
+ wire \gpio_defaults[264] ;
+ wire \gpio_defaults[265] ;
+ wire \gpio_defaults[266] ;
+ wire \gpio_defaults[267] ;
+ wire \gpio_defaults[268] ;
+ wire \gpio_defaults[269] ;
+ wire \gpio_defaults[26] ;
+ wire \gpio_defaults[270] ;
+ wire \gpio_defaults[271] ;
+ wire \gpio_defaults[272] ;
+ wire \gpio_defaults[273] ;
+ wire \gpio_defaults[274] ;
+ wire \gpio_defaults[275] ;
+ wire \gpio_defaults[276] ;
+ wire \gpio_defaults[277] ;
+ wire \gpio_defaults[278] ;
+ wire \gpio_defaults[279] ;
+ wire \gpio_defaults[27] ;
+ wire \gpio_defaults[280] ;
+ wire \gpio_defaults[281] ;
+ wire \gpio_defaults[282] ;
+ wire \gpio_defaults[283] ;
+ wire \gpio_defaults[284] ;
+ wire \gpio_defaults[285] ;
+ wire \gpio_defaults[286] ;
+ wire \gpio_defaults[287] ;
+ wire \gpio_defaults[288] ;
+ wire \gpio_defaults[289] ;
+ wire \gpio_defaults[28] ;
+ wire \gpio_defaults[290] ;
+ wire \gpio_defaults[291] ;
+ wire \gpio_defaults[292] ;
+ wire \gpio_defaults[293] ;
+ wire \gpio_defaults[294] ;
+ wire \gpio_defaults[295] ;
+ wire \gpio_defaults[296] ;
+ wire \gpio_defaults[297] ;
+ wire \gpio_defaults[298] ;
+ wire \gpio_defaults[299] ;
+ wire \gpio_defaults[29] ;
+ wire \gpio_defaults[2] ;
+ wire \gpio_defaults[300] ;
+ wire \gpio_defaults[301] ;
+ wire \gpio_defaults[302] ;
+ wire \gpio_defaults[303] ;
+ wire \gpio_defaults[304] ;
+ wire \gpio_defaults[305] ;
+ wire \gpio_defaults[306] ;
+ wire \gpio_defaults[307] ;
+ wire \gpio_defaults[308] ;
+ wire \gpio_defaults[309] ;
+ wire \gpio_defaults[30] ;
+ wire \gpio_defaults[310] ;
+ wire \gpio_defaults[311] ;
+ wire \gpio_defaults[312] ;
+ wire \gpio_defaults[313] ;
+ wire \gpio_defaults[314] ;
+ wire \gpio_defaults[315] ;
+ wire \gpio_defaults[316] ;
+ wire \gpio_defaults[317] ;
+ wire \gpio_defaults[318] ;
+ wire \gpio_defaults[319] ;
+ wire \gpio_defaults[31] ;
+ wire \gpio_defaults[320] ;
+ wire \gpio_defaults[321] ;
+ wire \gpio_defaults[322] ;
+ wire \gpio_defaults[323] ;
+ wire \gpio_defaults[324] ;
+ wire \gpio_defaults[325] ;
+ wire \gpio_defaults[326] ;
+ wire \gpio_defaults[327] ;
+ wire \gpio_defaults[328] ;
+ wire \gpio_defaults[329] ;
+ wire \gpio_defaults[32] ;
+ wire \gpio_defaults[330] ;
+ wire \gpio_defaults[331] ;
+ wire \gpio_defaults[332] ;
+ wire \gpio_defaults[333] ;
+ wire \gpio_defaults[334] ;
+ wire \gpio_defaults[335] ;
+ wire \gpio_defaults[336] ;
+ wire \gpio_defaults[337] ;
+ wire \gpio_defaults[338] ;
+ wire \gpio_defaults[339] ;
+ wire \gpio_defaults[33] ;
+ wire \gpio_defaults[340] ;
+ wire \gpio_defaults[341] ;
+ wire \gpio_defaults[342] ;
+ wire \gpio_defaults[343] ;
+ wire \gpio_defaults[344] ;
+ wire \gpio_defaults[345] ;
+ wire \gpio_defaults[346] ;
+ wire \gpio_defaults[347] ;
+ wire \gpio_defaults[348] ;
+ wire \gpio_defaults[349] ;
+ wire \gpio_defaults[34] ;
+ wire \gpio_defaults[350] ;
+ wire \gpio_defaults[35] ;
+ wire \gpio_defaults[36] ;
+ wire \gpio_defaults[37] ;
+ wire \gpio_defaults[38] ;
+ wire \gpio_defaults[39] ;
+ wire \gpio_defaults[3] ;
+ wire \gpio_defaults[40] ;
+ wire \gpio_defaults[41] ;
+ wire \gpio_defaults[42] ;
+ wire \gpio_defaults[43] ;
+ wire \gpio_defaults[44] ;
+ wire \gpio_defaults[45] ;
+ wire \gpio_defaults[46] ;
+ wire \gpio_defaults[47] ;
+ wire \gpio_defaults[48] ;
+ wire \gpio_defaults[49] ;
+ wire \gpio_defaults[4] ;
+ wire \gpio_defaults[50] ;
+ wire \gpio_defaults[51] ;
+ wire \gpio_defaults[52] ;
+ wire \gpio_defaults[53] ;
+ wire \gpio_defaults[54] ;
+ wire \gpio_defaults[55] ;
+ wire \gpio_defaults[56] ;
+ wire \gpio_defaults[57] ;
+ wire \gpio_defaults[58] ;
+ wire \gpio_defaults[59] ;
+ wire \gpio_defaults[5] ;
+ wire \gpio_defaults[60] ;
+ wire \gpio_defaults[61] ;
+ wire \gpio_defaults[62] ;
+ wire \gpio_defaults[63] ;
+ wire \gpio_defaults[64] ;
+ wire \gpio_defaults[65] ;
+ wire \gpio_defaults[66] ;
+ wire \gpio_defaults[67] ;
+ wire \gpio_defaults[68] ;
+ wire \gpio_defaults[69] ;
+ wire \gpio_defaults[6] ;
+ wire \gpio_defaults[70] ;
+ wire \gpio_defaults[71] ;
+ wire \gpio_defaults[72] ;
+ wire \gpio_defaults[73] ;
+ wire \gpio_defaults[74] ;
+ wire \gpio_defaults[75] ;
+ wire \gpio_defaults[76] ;
+ wire \gpio_defaults[77] ;
+ wire \gpio_defaults[78] ;
+ wire \gpio_defaults[79] ;
+ wire \gpio_defaults[7] ;
+ wire \gpio_defaults[80] ;
+ wire \gpio_defaults[81] ;
+ wire \gpio_defaults[82] ;
+ wire \gpio_defaults[83] ;
+ wire \gpio_defaults[84] ;
+ wire \gpio_defaults[85] ;
+ wire \gpio_defaults[86] ;
+ wire \gpio_defaults[87] ;
+ wire \gpio_defaults[88] ;
+ wire \gpio_defaults[89] ;
+ wire \gpio_defaults[8] ;
+ wire \gpio_defaults[90] ;
+ wire \gpio_defaults[91] ;
+ wire \gpio_defaults[92] ;
+ wire \gpio_defaults[93] ;
+ wire \gpio_defaults[94] ;
+ wire \gpio_defaults[95] ;
+ wire \gpio_defaults[96] ;
+ wire \gpio_defaults[97] ;
+ wire \gpio_defaults[98] ;
+ wire \gpio_defaults[99] ;
+ wire \gpio_defaults[9] ;
+ wire gpio_in_core;
+ wire gpio_inenb_core;
+ wire \gpio_load_1[0] ;
+ wire \gpio_load_1[10] ;
+ wire \gpio_load_1[11] ;
+ wire \gpio_load_1[12] ;
+ wire \gpio_load_1[13] ;
+ wire \gpio_load_1[14] ;
+ wire \gpio_load_1[15] ;
+ wire \gpio_load_1[16] ;
+ wire \gpio_load_1[17] ;
+ wire \gpio_load_1[18] ;
+ wire \gpio_load_1[1] ;
+ wire \gpio_load_1[2] ;
+ wire \gpio_load_1[3] ;
+ wire \gpio_load_1[4] ;
+ wire \gpio_load_1[5] ;
+ wire \gpio_load_1[6] ;
+ wire \gpio_load_1[7] ;
+ wire \gpio_load_1[8] ;
+ wire \gpio_load_1[9] ;
+ wire \gpio_load_1_shifted[0] ;
+ wire \gpio_load_1_shifted[10] ;
+ wire \gpio_load_1_shifted[11] ;
+ wire \gpio_load_1_shifted[12] ;
+ wire \gpio_load_1_shifted[13] ;
+ wire \gpio_load_1_shifted[1] ;
+ wire \gpio_load_1_shifted[2] ;
+ wire \gpio_load_1_shifted[3] ;
+ wire \gpio_load_1_shifted[4] ;
+ wire \gpio_load_1_shifted[5] ;
+ wire \gpio_load_1_shifted[6] ;
+ wire \gpio_load_1_shifted[7] ;
+ wire \gpio_load_1_shifted[8] ;
+ wire \gpio_load_1_shifted[9] ;
+ wire \gpio_load_2[0] ;
+ wire \gpio_load_2[10] ;
+ wire \gpio_load_2[11] ;
+ wire \gpio_load_2[12] ;
+ wire \gpio_load_2[13] ;
+ wire \gpio_load_2[14] ;
+ wire \gpio_load_2[15] ;
+ wire \gpio_load_2[16] ;
+ wire \gpio_load_2[17] ;
+ wire \gpio_load_2[18] ;
+ wire \gpio_load_2[1] ;
+ wire \gpio_load_2[2] ;
+ wire \gpio_load_2[3] ;
+ wire \gpio_load_2[4] ;
+ wire \gpio_load_2[5] ;
+ wire \gpio_load_2[6] ;
+ wire \gpio_load_2[7] ;
+ wire \gpio_load_2[8] ;
+ wire \gpio_load_2[9] ;
+ wire \gpio_load_2_shifted[0] ;
+ wire \gpio_load_2_shifted[10] ;
+ wire \gpio_load_2_shifted[11] ;
+ wire \gpio_load_2_shifted[12] ;
+ wire \gpio_load_2_shifted[1] ;
+ wire \gpio_load_2_shifted[2] ;
+ wire \gpio_load_2_shifted[3] ;
+ wire \gpio_load_2_shifted[4] ;
+ wire \gpio_load_2_shifted[5] ;
+ wire \gpio_load_2_shifted[6] ;
+ wire \gpio_load_2_shifted[7] ;
+ wire \gpio_load_2_shifted[8] ;
+ wire \gpio_load_2_shifted[9] ;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_out_core;
+ wire gpio_outenb_core;
+ wire \gpio_resetn_1[0] ;
+ wire \gpio_resetn_1[10] ;
+ wire \gpio_resetn_1[11] ;
+ wire \gpio_resetn_1[12] ;
+ wire \gpio_resetn_1[13] ;
+ wire \gpio_resetn_1[14] ;
+ wire \gpio_resetn_1[15] ;
+ wire \gpio_resetn_1[16] ;
+ wire \gpio_resetn_1[17] ;
+ wire \gpio_resetn_1[18] ;
+ wire \gpio_resetn_1[1] ;
+ wire \gpio_resetn_1[2] ;
+ wire \gpio_resetn_1[3] ;
+ wire \gpio_resetn_1[4] ;
+ wire \gpio_resetn_1[5] ;
+ wire \gpio_resetn_1[6] ;
+ wire \gpio_resetn_1[7] ;
+ wire \gpio_resetn_1[8] ;
+ wire \gpio_resetn_1[9] ;
+ wire \gpio_resetn_1_shifted[0] ;
+ wire \gpio_resetn_1_shifted[10] ;
+ wire \gpio_resetn_1_shifted[11] ;
+ wire \gpio_resetn_1_shifted[12] ;
+ wire \gpio_resetn_1_shifted[13] ;
+ wire \gpio_resetn_1_shifted[1] ;
+ wire \gpio_resetn_1_shifted[2] ;
+ wire \gpio_resetn_1_shifted[3] ;
+ wire \gpio_resetn_1_shifted[4] ;
+ wire \gpio_resetn_1_shifted[5] ;
+ wire \gpio_resetn_1_shifted[6] ;
+ wire \gpio_resetn_1_shifted[7] ;
+ wire \gpio_resetn_1_shifted[8] ;
+ wire \gpio_resetn_1_shifted[9] ;
+ wire \gpio_resetn_2[0] ;
+ wire \gpio_resetn_2[10] ;
+ wire \gpio_resetn_2[11] ;
+ wire \gpio_resetn_2[12] ;
+ wire \gpio_resetn_2[13] ;
+ wire \gpio_resetn_2[14] ;
+ wire \gpio_resetn_2[15] ;
+ wire \gpio_resetn_2[16] ;
+ wire \gpio_resetn_2[17] ;
+ wire \gpio_resetn_2[18] ;
+ wire \gpio_resetn_2[1] ;
+ wire \gpio_resetn_2[2] ;
+ wire \gpio_resetn_2[3] ;
+ wire \gpio_resetn_2[4] ;
+ wire \gpio_resetn_2[5] ;
+ wire \gpio_resetn_2[6] ;
+ wire \gpio_resetn_2[7] ;
+ wire \gpio_resetn_2[8] ;
+ wire \gpio_resetn_2[9] ;
+ wire \gpio_resetn_2_shifted[0] ;
+ wire \gpio_resetn_2_shifted[10] ;
+ wire \gpio_resetn_2_shifted[11] ;
+ wire \gpio_resetn_2_shifted[12] ;
+ wire \gpio_resetn_2_shifted[1] ;
+ wire \gpio_resetn_2_shifted[2] ;
+ wire \gpio_resetn_2_shifted[3] ;
+ wire \gpio_resetn_2_shifted[4] ;
+ wire \gpio_resetn_2_shifted[5] ;
+ wire \gpio_resetn_2_shifted[6] ;
+ wire \gpio_resetn_2_shifted[7] ;
+ wire \gpio_resetn_2_shifted[8] ;
+ wire \gpio_resetn_2_shifted[9] ;
+ wire \gpio_serial_link_1[0] ;
+ wire \gpio_serial_link_1[10] ;
+ wire \gpio_serial_link_1[11] ;
+ wire \gpio_serial_link_1[12] ;
+ wire \gpio_serial_link_1[13] ;
+ wire \gpio_serial_link_1[1] ;
+ wire \gpio_serial_link_1[2] ;
+ wire \gpio_serial_link_1[3] ;
+ wire \gpio_serial_link_1[4] ;
+ wire \gpio_serial_link_1[5] ;
+ wire \gpio_serial_link_1[6] ;
+ wire \gpio_serial_link_1[7] ;
+ wire \gpio_serial_link_1[8] ;
+ wire \gpio_serial_link_1[9] ;
+ wire \gpio_serial_link_1_shifted[0] ;
+ wire \gpio_serial_link_1_shifted[10] ;
+ wire \gpio_serial_link_1_shifted[11] ;
+ wire \gpio_serial_link_1_shifted[12] ;
+ wire \gpio_serial_link_1_shifted[13] ;
+ wire \gpio_serial_link_1_shifted[1] ;
+ wire \gpio_serial_link_1_shifted[2] ;
+ wire \gpio_serial_link_1_shifted[3] ;
+ wire \gpio_serial_link_1_shifted[4] ;
+ wire \gpio_serial_link_1_shifted[5] ;
+ wire \gpio_serial_link_1_shifted[6] ;
+ wire \gpio_serial_link_1_shifted[7] ;
+ wire \gpio_serial_link_1_shifted[8] ;
+ wire \gpio_serial_link_1_shifted[9] ;
+ wire \gpio_serial_link_2[0] ;
+ wire \gpio_serial_link_2[10] ;
+ wire \gpio_serial_link_2[11] ;
+ wire \gpio_serial_link_2[12] ;
+ wire \gpio_serial_link_2[1] ;
+ wire \gpio_serial_link_2[2] ;
+ wire \gpio_serial_link_2[3] ;
+ wire \gpio_serial_link_2[4] ;
+ wire \gpio_serial_link_2[5] ;
+ wire \gpio_serial_link_2[6] ;
+ wire \gpio_serial_link_2[7] ;
+ wire \gpio_serial_link_2[8] ;
+ wire \gpio_serial_link_2[9] ;
+ wire \gpio_serial_link_2_shifted[0] ;
+ wire \gpio_serial_link_2_shifted[10] ;
+ wire \gpio_serial_link_2_shifted[11] ;
+ wire \gpio_serial_link_2_shifted[12] ;
+ wire \gpio_serial_link_2_shifted[1] ;
+ wire \gpio_serial_link_2_shifted[2] ;
+ wire \gpio_serial_link_2_shifted[3] ;
+ wire \gpio_serial_link_2_shifted[4] ;
+ wire \gpio_serial_link_2_shifted[5] ;
+ wire \gpio_serial_link_2_shifted[6] ;
+ wire \gpio_serial_link_2_shifted[7] ;
+ wire \gpio_serial_link_2_shifted[8] ;
+ wire \gpio_serial_link_2_shifted[9] ;
+ wire hk_ack_i;
+ wire \hk_dat_i[0] ;
+ wire \hk_dat_i[10] ;
+ wire \hk_dat_i[11] ;
+ wire \hk_dat_i[12] ;
+ wire \hk_dat_i[13] ;
+ wire \hk_dat_i[14] ;
+ wire \hk_dat_i[15] ;
+ wire \hk_dat_i[16] ;
+ wire \hk_dat_i[17] ;
+ wire \hk_dat_i[18] ;
+ wire \hk_dat_i[19] ;
+ wire \hk_dat_i[1] ;
+ wire \hk_dat_i[20] ;
+ wire \hk_dat_i[21] ;
+ wire \hk_dat_i[22] ;
+ wire \hk_dat_i[23] ;
+ wire \hk_dat_i[24] ;
+ wire \hk_dat_i[25] ;
+ wire \hk_dat_i[26] ;
+ wire \hk_dat_i[27] ;
+ wire \hk_dat_i[28] ;
+ wire \hk_dat_i[29] ;
+ wire \hk_dat_i[2] ;
+ wire \hk_dat_i[30] ;
+ wire \hk_dat_i[31] ;
+ wire \hk_dat_i[3] ;
+ wire \hk_dat_i[4] ;
+ wire \hk_dat_i[5] ;
+ wire \hk_dat_i[6] ;
+ wire \hk_dat_i[7] ;
+ wire \hk_dat_i[8] ;
+ wire \hk_dat_i[9] ;
+ wire hk_stb_o;
+ wire hk_cyc_o;
+ wire \hkspi_sram_addr[0] ;
+ wire \hkspi_sram_addr[1] ;
+ wire \hkspi_sram_addr[2] ;
+ wire \hkspi_sram_addr[3] ;
+ wire \hkspi_sram_addr[4] ;
+ wire \hkspi_sram_addr[5] ;
+ wire \hkspi_sram_addr[6] ;
+ wire \hkspi_sram_addr[7] ;
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire \hkspi_sram_data[0] ;
+ wire \hkspi_sram_data[10] ;
+ wire \hkspi_sram_data[11] ;
+ wire \hkspi_sram_data[12] ;
+ wire \hkspi_sram_data[13] ;
+ wire \hkspi_sram_data[14] ;
+ wire \hkspi_sram_data[15] ;
+ wire \hkspi_sram_data[16] ;
+ wire \hkspi_sram_data[17] ;
+ wire \hkspi_sram_data[18] ;
+ wire \hkspi_sram_data[19] ;
+ wire \hkspi_sram_data[1] ;
+ wire \hkspi_sram_data[20] ;
+ wire \hkspi_sram_data[21] ;
+ wire \hkspi_sram_data[22] ;
+ wire \hkspi_sram_data[23] ;
+ wire \hkspi_sram_data[24] ;
+ wire \hkspi_sram_data[25] ;
+ wire \hkspi_sram_data[26] ;
+ wire \hkspi_sram_data[27] ;
+ wire \hkspi_sram_data[28] ;
+ wire \hkspi_sram_data[29] ;
+ wire \hkspi_sram_data[2] ;
+ wire \hkspi_sram_data[30] ;
+ wire \hkspi_sram_data[31] ;
+ wire \hkspi_sram_data[3] ;
+ wire \hkspi_sram_data[4] ;
+ wire \hkspi_sram_data[5] ;
+ wire \hkspi_sram_data[6] ;
+ wire \hkspi_sram_data[7] ;
+ wire \hkspi_sram_data[8] ;
+ wire \hkspi_sram_data[9] ;
+ wire \irq_spi[0] ;
+ wire \irq_spi[1] ;
+ wire \irq_spi[2] ;
+ wire jtag_out;
+ wire jtag_outenb;
+ wire \la_data_in_mprj[0] ;
+ wire \la_data_in_mprj[100] ;
+ wire \la_data_in_mprj[101] ;
+ wire \la_data_in_mprj[102] ;
+ wire \la_data_in_mprj[103] ;
+ wire \la_data_in_mprj[104] ;
+ wire \la_data_in_mprj[105] ;
+ wire \la_data_in_mprj[106] ;
+ wire \la_data_in_mprj[107] ;
+ wire \la_data_in_mprj[108] ;
+ wire \la_data_in_mprj[109] ;
+ wire \la_data_in_mprj[10] ;
+ wire \la_data_in_mprj[110] ;
+ wire \la_data_in_mprj[111] ;
+ wire \la_data_in_mprj[112] ;
+ wire \la_data_in_mprj[113] ;
+ wire \la_data_in_mprj[114] ;
+ wire \la_data_in_mprj[115] ;
+ wire \la_data_in_mprj[116] ;
+ wire \la_data_in_mprj[117] ;
+ wire \la_data_in_mprj[118] ;
+ wire \la_data_in_mprj[119] ;
+ wire \la_data_in_mprj[11] ;
+ wire \la_data_in_mprj[120] ;
+ wire \la_data_in_mprj[121] ;
+ wire \la_data_in_mprj[122] ;
+ wire \la_data_in_mprj[123] ;
+ wire \la_data_in_mprj[124] ;
+ wire \la_data_in_mprj[125] ;
+ wire \la_data_in_mprj[126] ;
+ wire \la_data_in_mprj[127] ;
+ wire \la_data_in_mprj[12] ;
+ wire \la_data_in_mprj[13] ;
+ wire \la_data_in_mprj[14] ;
+ wire \la_data_in_mprj[15] ;
+ wire \la_data_in_mprj[16] ;
+ wire \la_data_in_mprj[17] ;
+ wire \la_data_in_mprj[18] ;
+ wire \la_data_in_mprj[19] ;
+ wire \la_data_in_mprj[1] ;
+ wire \la_data_in_mprj[20] ;
+ wire \la_data_in_mprj[21] ;
+ wire \la_data_in_mprj[22] ;
+ wire \la_data_in_mprj[23] ;
+ wire \la_data_in_mprj[24] ;
+ wire \la_data_in_mprj[25] ;
+ wire \la_data_in_mprj[26] ;
+ wire \la_data_in_mprj[27] ;
+ wire \la_data_in_mprj[28] ;
+ wire \la_data_in_mprj[29] ;
+ wire \la_data_in_mprj[2] ;
+ wire \la_data_in_mprj[30] ;
+ wire \la_data_in_mprj[31] ;
+ wire \la_data_in_mprj[32] ;
+ wire \la_data_in_mprj[33] ;
+ wire \la_data_in_mprj[34] ;
+ wire \la_data_in_mprj[35] ;
+ wire \la_data_in_mprj[36] ;
+ wire \la_data_in_mprj[37] ;
+ wire \la_data_in_mprj[38] ;
+ wire \la_data_in_mprj[39] ;
+ wire \la_data_in_mprj[3] ;
+ wire \la_data_in_mprj[40] ;
+ wire \la_data_in_mprj[41] ;
+ wire \la_data_in_mprj[42] ;
+ wire \la_data_in_mprj[43] ;
+ wire \la_data_in_mprj[44] ;
+ wire \la_data_in_mprj[45] ;
+ wire \la_data_in_mprj[46] ;
+ wire \la_data_in_mprj[47] ;
+ wire \la_data_in_mprj[48] ;
+ wire \la_data_in_mprj[49] ;
+ wire \la_data_in_mprj[4] ;
+ wire \la_data_in_mprj[50] ;
+ wire \la_data_in_mprj[51] ;
+ wire \la_data_in_mprj[52] ;
+ wire \la_data_in_mprj[53] ;
+ wire \la_data_in_mprj[54] ;
+ wire \la_data_in_mprj[55] ;
+ wire \la_data_in_mprj[56] ;
+ wire \la_data_in_mprj[57] ;
+ wire \la_data_in_mprj[58] ;
+ wire \la_data_in_mprj[59] ;
+ wire \la_data_in_mprj[5] ;
+ wire \la_data_in_mprj[60] ;
+ wire \la_data_in_mprj[61] ;
+ wire \la_data_in_mprj[62] ;
+ wire \la_data_in_mprj[63] ;
+ wire \la_data_in_mprj[64] ;
+ wire \la_data_in_mprj[65] ;
+ wire \la_data_in_mprj[66] ;
+ wire \la_data_in_mprj[67] ;
+ wire \la_data_in_mprj[68] ;
+ wire \la_data_in_mprj[69] ;
+ wire \la_data_in_mprj[6] ;
+ wire \la_data_in_mprj[70] ;
+ wire \la_data_in_mprj[71] ;
+ wire \la_data_in_mprj[72] ;
+ wire \la_data_in_mprj[73] ;
+ wire \la_data_in_mprj[74] ;
+ wire \la_data_in_mprj[75] ;
+ wire \la_data_in_mprj[76] ;
+ wire \la_data_in_mprj[77] ;
+ wire \la_data_in_mprj[78] ;
+ wire \la_data_in_mprj[79] ;
+ wire \la_data_in_mprj[7] ;
+ wire \la_data_in_mprj[80] ;
+ wire \la_data_in_mprj[81] ;
+ wire \la_data_in_mprj[82] ;
+ wire \la_data_in_mprj[83] ;
+ wire \la_data_in_mprj[84] ;
+ wire \la_data_in_mprj[85] ;
+ wire \la_data_in_mprj[86] ;
+ wire \la_data_in_mprj[87] ;
+ wire \la_data_in_mprj[88] ;
+ wire \la_data_in_mprj[89] ;
+ wire \la_data_in_mprj[8] ;
+ wire \la_data_in_mprj[90] ;
+ wire \la_data_in_mprj[91] ;
+ wire \la_data_in_mprj[92] ;
+ wire \la_data_in_mprj[93] ;
+ wire \la_data_in_mprj[94] ;
+ wire \la_data_in_mprj[95] ;
+ wire \la_data_in_mprj[96] ;
+ wire \la_data_in_mprj[97] ;
+ wire \la_data_in_mprj[98] ;
+ wire \la_data_in_mprj[99] ;
+ wire \la_data_in_mprj[9] ;
+ wire \la_data_in_user[0] ;
+ wire \la_data_in_user[100] ;
+ wire \la_data_in_user[101] ;
+ wire \la_data_in_user[102] ;
+ wire \la_data_in_user[103] ;
+ wire \la_data_in_user[104] ;
+ wire \la_data_in_user[105] ;
+ wire \la_data_in_user[106] ;
+ wire \la_data_in_user[107] ;
+ wire \la_data_in_user[108] ;
+ wire \la_data_in_user[109] ;
+ wire \la_data_in_user[10] ;
+ wire \la_data_in_user[110] ;
+ wire \la_data_in_user[111] ;
+ wire \la_data_in_user[112] ;
+ wire \la_data_in_user[113] ;
+ wire \la_data_in_user[114] ;
+ wire \la_data_in_user[115] ;
+ wire \la_data_in_user[116] ;
+ wire \la_data_in_user[117] ;
+ wire \la_data_in_user[118] ;
+ wire \la_data_in_user[119] ;
+ wire \la_data_in_user[11] ;
+ wire \la_data_in_user[120] ;
+ wire \la_data_in_user[121] ;
+ wire \la_data_in_user[122] ;
+ wire \la_data_in_user[123] ;
+ wire \la_data_in_user[124] ;
+ wire \la_data_in_user[125] ;
+ wire \la_data_in_user[126] ;
+ wire \la_data_in_user[127] ;
+ wire \la_data_in_user[12] ;
+ wire \la_data_in_user[13] ;
+ wire \la_data_in_user[14] ;
+ wire \la_data_in_user[15] ;
+ wire \la_data_in_user[16] ;
+ wire \la_data_in_user[17] ;
+ wire \la_data_in_user[18] ;
+ wire \la_data_in_user[19] ;
+ wire \la_data_in_user[1] ;
+ wire \la_data_in_user[20] ;
+ wire \la_data_in_user[21] ;
+ wire \la_data_in_user[22] ;
+ wire \la_data_in_user[23] ;
+ wire \la_data_in_user[24] ;
+ wire \la_data_in_user[25] ;
+ wire \la_data_in_user[26] ;
+ wire \la_data_in_user[27] ;
+ wire \la_data_in_user[28] ;
+ wire \la_data_in_user[29] ;
+ wire \la_data_in_user[2] ;
+ wire \la_data_in_user[30] ;
+ wire \la_data_in_user[31] ;
+ wire \la_data_in_user[32] ;
+ wire \la_data_in_user[33] ;
+ wire \la_data_in_user[34] ;
+ wire \la_data_in_user[35] ;
+ wire \la_data_in_user[36] ;
+ wire \la_data_in_user[37] ;
+ wire \la_data_in_user[38] ;
+ wire \la_data_in_user[39] ;
+ wire \la_data_in_user[3] ;
+ wire \la_data_in_user[40] ;
+ wire \la_data_in_user[41] ;
+ wire \la_data_in_user[42] ;
+ wire \la_data_in_user[43] ;
+ wire \la_data_in_user[44] ;
+ wire \la_data_in_user[45] ;
+ wire \la_data_in_user[46] ;
+ wire \la_data_in_user[47] ;
+ wire \la_data_in_user[48] ;
+ wire \la_data_in_user[49] ;
+ wire \la_data_in_user[4] ;
+ wire \la_data_in_user[50] ;
+ wire \la_data_in_user[51] ;
+ wire \la_data_in_user[52] ;
+ wire \la_data_in_user[53] ;
+ wire \la_data_in_user[54] ;
+ wire \la_data_in_user[55] ;
+ wire \la_data_in_user[56] ;
+ wire \la_data_in_user[57] ;
+ wire \la_data_in_user[58] ;
+ wire \la_data_in_user[59] ;
+ wire \la_data_in_user[5] ;
+ wire \la_data_in_user[60] ;
+ wire \la_data_in_user[61] ;
+ wire \la_data_in_user[62] ;
+ wire \la_data_in_user[63] ;
+ wire \la_data_in_user[64] ;
+ wire \la_data_in_user[65] ;
+ wire \la_data_in_user[66] ;
+ wire \la_data_in_user[67] ;
+ wire \la_data_in_user[68] ;
+ wire \la_data_in_user[69] ;
+ wire \la_data_in_user[6] ;
+ wire \la_data_in_user[70] ;
+ wire \la_data_in_user[71] ;
+ wire \la_data_in_user[72] ;
+ wire \la_data_in_user[73] ;
+ wire \la_data_in_user[74] ;
+ wire \la_data_in_user[75] ;
+ wire \la_data_in_user[76] ;
+ wire \la_data_in_user[77] ;
+ wire \la_data_in_user[78] ;
+ wire \la_data_in_user[79] ;
+ wire \la_data_in_user[7] ;
+ wire \la_data_in_user[80] ;
+ wire \la_data_in_user[81] ;
+ wire \la_data_in_user[82] ;
+ wire \la_data_in_user[83] ;
+ wire \la_data_in_user[84] ;
+ wire \la_data_in_user[85] ;
+ wire \la_data_in_user[86] ;
+ wire \la_data_in_user[87] ;
+ wire \la_data_in_user[88] ;
+ wire \la_data_in_user[89] ;
+ wire \la_data_in_user[8] ;
+ wire \la_data_in_user[90] ;
+ wire \la_data_in_user[91] ;
+ wire \la_data_in_user[92] ;
+ wire \la_data_in_user[93] ;
+ wire \la_data_in_user[94] ;
+ wire \la_data_in_user[95] ;
+ wire \la_data_in_user[96] ;
+ wire \la_data_in_user[97] ;
+ wire \la_data_in_user[98] ;
+ wire \la_data_in_user[99] ;
+ wire \la_data_in_user[9] ;
+ wire \la_data_out_mprj[0] ;
+ wire \la_data_out_mprj[100] ;
+ wire \la_data_out_mprj[101] ;
+ wire \la_data_out_mprj[102] ;
+ wire \la_data_out_mprj[103] ;
+ wire \la_data_out_mprj[104] ;
+ wire \la_data_out_mprj[105] ;
+ wire \la_data_out_mprj[106] ;
+ wire \la_data_out_mprj[107] ;
+ wire \la_data_out_mprj[108] ;
+ wire \la_data_out_mprj[109] ;
+ wire \la_data_out_mprj[10] ;
+ wire \la_data_out_mprj[110] ;
+ wire \la_data_out_mprj[111] ;
+ wire \la_data_out_mprj[112] ;
+ wire \la_data_out_mprj[113] ;
+ wire \la_data_out_mprj[114] ;
+ wire \la_data_out_mprj[115] ;
+ wire \la_data_out_mprj[116] ;
+ wire \la_data_out_mprj[117] ;
+ wire \la_data_out_mprj[118] ;
+ wire \la_data_out_mprj[119] ;
+ wire \la_data_out_mprj[11] ;
+ wire \la_data_out_mprj[120] ;
+ wire \la_data_out_mprj[121] ;
+ wire \la_data_out_mprj[122] ;
+ wire \la_data_out_mprj[123] ;
+ wire \la_data_out_mprj[124] ;
+ wire \la_data_out_mprj[125] ;
+ wire \la_data_out_mprj[126] ;
+ wire \la_data_out_mprj[127] ;
+ wire \la_data_out_mprj[12] ;
+ wire \la_data_out_mprj[13] ;
+ wire \la_data_out_mprj[14] ;
+ wire \la_data_out_mprj[15] ;
+ wire \la_data_out_mprj[16] ;
+ wire \la_data_out_mprj[17] ;
+ wire \la_data_out_mprj[18] ;
+ wire \la_data_out_mprj[19] ;
+ wire \la_data_out_mprj[1] ;
+ wire \la_data_out_mprj[20] ;
+ wire \la_data_out_mprj[21] ;
+ wire \la_data_out_mprj[22] ;
+ wire \la_data_out_mprj[23] ;
+ wire \la_data_out_mprj[24] ;
+ wire \la_data_out_mprj[25] ;
+ wire \la_data_out_mprj[26] ;
+ wire \la_data_out_mprj[27] ;
+ wire \la_data_out_mprj[28] ;
+ wire \la_data_out_mprj[29] ;
+ wire \la_data_out_mprj[2] ;
+ wire \la_data_out_mprj[30] ;
+ wire \la_data_out_mprj[31] ;
+ wire \la_data_out_mprj[32] ;
+ wire \la_data_out_mprj[33] ;
+ wire \la_data_out_mprj[34] ;
+ wire \la_data_out_mprj[35] ;
+ wire \la_data_out_mprj[36] ;
+ wire \la_data_out_mprj[37] ;
+ wire \la_data_out_mprj[38] ;
+ wire \la_data_out_mprj[39] ;
+ wire \la_data_out_mprj[3] ;
+ wire \la_data_out_mprj[40] ;
+ wire \la_data_out_mprj[41] ;
+ wire \la_data_out_mprj[42] ;
+ wire \la_data_out_mprj[43] ;
+ wire \la_data_out_mprj[44] ;
+ wire \la_data_out_mprj[45] ;
+ wire \la_data_out_mprj[46] ;
+ wire \la_data_out_mprj[47] ;
+ wire \la_data_out_mprj[48] ;
+ wire \la_data_out_mprj[49] ;
+ wire \la_data_out_mprj[4] ;
+ wire \la_data_out_mprj[50] ;
+ wire \la_data_out_mprj[51] ;
+ wire \la_data_out_mprj[52] ;
+ wire \la_data_out_mprj[53] ;
+ wire \la_data_out_mprj[54] ;
+ wire \la_data_out_mprj[55] ;
+ wire \la_data_out_mprj[56] ;
+ wire \la_data_out_mprj[57] ;
+ wire \la_data_out_mprj[58] ;
+ wire \la_data_out_mprj[59] ;
+ wire \la_data_out_mprj[5] ;
+ wire \la_data_out_mprj[60] ;
+ wire \la_data_out_mprj[61] ;
+ wire \la_data_out_mprj[62] ;
+ wire \la_data_out_mprj[63] ;
+ wire \la_data_out_mprj[64] ;
+ wire \la_data_out_mprj[65] ;
+ wire \la_data_out_mprj[66] ;
+ wire \la_data_out_mprj[67] ;
+ wire \la_data_out_mprj[68] ;
+ wire \la_data_out_mprj[69] ;
+ wire \la_data_out_mprj[6] ;
+ wire \la_data_out_mprj[70] ;
+ wire \la_data_out_mprj[71] ;
+ wire \la_data_out_mprj[72] ;
+ wire \la_data_out_mprj[73] ;
+ wire \la_data_out_mprj[74] ;
+ wire \la_data_out_mprj[75] ;
+ wire \la_data_out_mprj[76] ;
+ wire \la_data_out_mprj[77] ;
+ wire \la_data_out_mprj[78] ;
+ wire \la_data_out_mprj[79] ;
+ wire \la_data_out_mprj[7] ;
+ wire \la_data_out_mprj[80] ;
+ wire \la_data_out_mprj[81] ;
+ wire \la_data_out_mprj[82] ;
+ wire \la_data_out_mprj[83] ;
+ wire \la_data_out_mprj[84] ;
+ wire \la_data_out_mprj[85] ;
+ wire \la_data_out_mprj[86] ;
+ wire \la_data_out_mprj[87] ;
+ wire \la_data_out_mprj[88] ;
+ wire \la_data_out_mprj[89] ;
+ wire \la_data_out_mprj[8] ;
+ wire \la_data_out_mprj[90] ;
+ wire \la_data_out_mprj[91] ;
+ wire \la_data_out_mprj[92] ;
+ wire \la_data_out_mprj[93] ;
+ wire \la_data_out_mprj[94] ;
+ wire \la_data_out_mprj[95] ;
+ wire \la_data_out_mprj[96] ;
+ wire \la_data_out_mprj[97] ;
+ wire \la_data_out_mprj[98] ;
+ wire \la_data_out_mprj[99] ;
+ wire \la_data_out_mprj[9] ;
+ wire \la_data_out_user[0] ;
+ wire \la_data_out_user[100] ;
+ wire \la_data_out_user[101] ;
+ wire \la_data_out_user[102] ;
+ wire \la_data_out_user[103] ;
+ wire \la_data_out_user[104] ;
+ wire \la_data_out_user[105] ;
+ wire \la_data_out_user[106] ;
+ wire \la_data_out_user[107] ;
+ wire \la_data_out_user[108] ;
+ wire \la_data_out_user[109] ;
+ wire \la_data_out_user[10] ;
+ wire \la_data_out_user[110] ;
+ wire \la_data_out_user[111] ;
+ wire \la_data_out_user[112] ;
+ wire \la_data_out_user[113] ;
+ wire \la_data_out_user[114] ;
+ wire \la_data_out_user[115] ;
+ wire \la_data_out_user[116] ;
+ wire \la_data_out_user[117] ;
+ wire \la_data_out_user[118] ;
+ wire \la_data_out_user[119] ;
+ wire \la_data_out_user[11] ;
+ wire \la_data_out_user[120] ;
+ wire \la_data_out_user[121] ;
+ wire \la_data_out_user[122] ;
+ wire \la_data_out_user[123] ;
+ wire \la_data_out_user[124] ;
+ wire \la_data_out_user[125] ;
+ wire \la_data_out_user[126] ;
+ wire \la_data_out_user[127] ;
+ wire \la_data_out_user[12] ;
+ wire \la_data_out_user[13] ;
+ wire \la_data_out_user[14] ;
+ wire \la_data_out_user[15] ;
+ wire \la_data_out_user[16] ;
+ wire \la_data_out_user[17] ;
+ wire \la_data_out_user[18] ;
+ wire \la_data_out_user[19] ;
+ wire \la_data_out_user[1] ;
+ wire \la_data_out_user[20] ;
+ wire \la_data_out_user[21] ;
+ wire \la_data_out_user[22] ;
+ wire \la_data_out_user[23] ;
+ wire \la_data_out_user[24] ;
+ wire \la_data_out_user[25] ;
+ wire \la_data_out_user[26] ;
+ wire \la_data_out_user[27] ;
+ wire \la_data_out_user[28] ;
+ wire \la_data_out_user[29] ;
+ wire \la_data_out_user[2] ;
+ wire \la_data_out_user[30] ;
+ wire \la_data_out_user[31] ;
+ wire \la_data_out_user[32] ;
+ wire \la_data_out_user[33] ;
+ wire \la_data_out_user[34] ;
+ wire \la_data_out_user[35] ;
+ wire \la_data_out_user[36] ;
+ wire \la_data_out_user[37] ;
+ wire \la_data_out_user[38] ;
+ wire \la_data_out_user[39] ;
+ wire \la_data_out_user[3] ;
+ wire \la_data_out_user[40] ;
+ wire \la_data_out_user[41] ;
+ wire \la_data_out_user[42] ;
+ wire \la_data_out_user[43] ;
+ wire \la_data_out_user[44] ;
+ wire \la_data_out_user[45] ;
+ wire \la_data_out_user[46] ;
+ wire \la_data_out_user[47] ;
+ wire \la_data_out_user[48] ;
+ wire \la_data_out_user[49] ;
+ wire \la_data_out_user[4] ;
+ wire \la_data_out_user[50] ;
+ wire \la_data_out_user[51] ;
+ wire \la_data_out_user[52] ;
+ wire \la_data_out_user[53] ;
+ wire \la_data_out_user[54] ;
+ wire \la_data_out_user[55] ;
+ wire \la_data_out_user[56] ;
+ wire \la_data_out_user[57] ;
+ wire \la_data_out_user[58] ;
+ wire \la_data_out_user[59] ;
+ wire \la_data_out_user[5] ;
+ wire \la_data_out_user[60] ;
+ wire \la_data_out_user[61] ;
+ wire \la_data_out_user[62] ;
+ wire \la_data_out_user[63] ;
+ wire \la_data_out_user[64] ;
+ wire \la_data_out_user[65] ;
+ wire \la_data_out_user[66] ;
+ wire \la_data_out_user[67] ;
+ wire \la_data_out_user[68] ;
+ wire \la_data_out_user[69] ;
+ wire \la_data_out_user[6] ;
+ wire \la_data_out_user[70] ;
+ wire \la_data_out_user[71] ;
+ wire \la_data_out_user[72] ;
+ wire \la_data_out_user[73] ;
+ wire \la_data_out_user[74] ;
+ wire \la_data_out_user[75] ;
+ wire \la_data_out_user[76] ;
+ wire \la_data_out_user[77] ;
+ wire \la_data_out_user[78] ;
+ wire \la_data_out_user[79] ;
+ wire \la_data_out_user[7] ;
+ wire \la_data_out_user[80] ;
+ wire \la_data_out_user[81] ;
+ wire \la_data_out_user[82] ;
+ wire \la_data_out_user[83] ;
+ wire \la_data_out_user[84] ;
+ wire \la_data_out_user[85] ;
+ wire \la_data_out_user[86] ;
+ wire \la_data_out_user[87] ;
+ wire \la_data_out_user[88] ;
+ wire \la_data_out_user[89] ;
+ wire \la_data_out_user[8] ;
+ wire \la_data_out_user[90] ;
+ wire \la_data_out_user[91] ;
+ wire \la_data_out_user[92] ;
+ wire \la_data_out_user[93] ;
+ wire \la_data_out_user[94] ;
+ wire \la_data_out_user[95] ;
+ wire \la_data_out_user[96] ;
+ wire \la_data_out_user[97] ;
+ wire \la_data_out_user[98] ;
+ wire \la_data_out_user[99] ;
+ wire \la_data_out_user[9] ;
+ wire \la_iena_mprj[0] ;
+ wire \la_iena_mprj[100] ;
+ wire \la_iena_mprj[101] ;
+ wire \la_iena_mprj[102] ;
+ wire \la_iena_mprj[103] ;
+ wire \la_iena_mprj[104] ;
+ wire \la_iena_mprj[105] ;
+ wire \la_iena_mprj[106] ;
+ wire \la_iena_mprj[107] ;
+ wire \la_iena_mprj[108] ;
+ wire \la_iena_mprj[109] ;
+ wire \la_iena_mprj[10] ;
+ wire \la_iena_mprj[110] ;
+ wire \la_iena_mprj[111] ;
+ wire \la_iena_mprj[112] ;
+ wire \la_iena_mprj[113] ;
+ wire \la_iena_mprj[114] ;
+ wire \la_iena_mprj[115] ;
+ wire \la_iena_mprj[116] ;
+ wire \la_iena_mprj[117] ;
+ wire \la_iena_mprj[118] ;
+ wire \la_iena_mprj[119] ;
+ wire \la_iena_mprj[11] ;
+ wire \la_iena_mprj[120] ;
+ wire \la_iena_mprj[121] ;
+ wire \la_iena_mprj[122] ;
+ wire \la_iena_mprj[123] ;
+ wire \la_iena_mprj[124] ;
+ wire \la_iena_mprj[125] ;
+ wire \la_iena_mprj[126] ;
+ wire \la_iena_mprj[127] ;
+ wire \la_iena_mprj[12] ;
+ wire \la_iena_mprj[13] ;
+ wire \la_iena_mprj[14] ;
+ wire \la_iena_mprj[15] ;
+ wire \la_iena_mprj[16] ;
+ wire \la_iena_mprj[17] ;
+ wire \la_iena_mprj[18] ;
+ wire \la_iena_mprj[19] ;
+ wire \la_iena_mprj[1] ;
+ wire \la_iena_mprj[20] ;
+ wire \la_iena_mprj[21] ;
+ wire \la_iena_mprj[22] ;
+ wire \la_iena_mprj[23] ;
+ wire \la_iena_mprj[24] ;
+ wire \la_iena_mprj[25] ;
+ wire \la_iena_mprj[26] ;
+ wire \la_iena_mprj[27] ;
+ wire \la_iena_mprj[28] ;
+ wire \la_iena_mprj[29] ;
+ wire \la_iena_mprj[2] ;
+ wire \la_iena_mprj[30] ;
+ wire \la_iena_mprj[31] ;
+ wire \la_iena_mprj[32] ;
+ wire \la_iena_mprj[33] ;
+ wire \la_iena_mprj[34] ;
+ wire \la_iena_mprj[35] ;
+ wire \la_iena_mprj[36] ;
+ wire \la_iena_mprj[37] ;
+ wire \la_iena_mprj[38] ;
+ wire \la_iena_mprj[39] ;
+ wire \la_iena_mprj[3] ;
+ wire \la_iena_mprj[40] ;
+ wire \la_iena_mprj[41] ;
+ wire \la_iena_mprj[42] ;
+ wire \la_iena_mprj[43] ;
+ wire \la_iena_mprj[44] ;
+ wire \la_iena_mprj[45] ;
+ wire \la_iena_mprj[46] ;
+ wire \la_iena_mprj[47] ;
+ wire \la_iena_mprj[48] ;
+ wire \la_iena_mprj[49] ;
+ wire \la_iena_mprj[4] ;
+ wire \la_iena_mprj[50] ;
+ wire \la_iena_mprj[51] ;
+ wire \la_iena_mprj[52] ;
+ wire \la_iena_mprj[53] ;
+ wire \la_iena_mprj[54] ;
+ wire \la_iena_mprj[55] ;
+ wire \la_iena_mprj[56] ;
+ wire \la_iena_mprj[57] ;
+ wire \la_iena_mprj[58] ;
+ wire \la_iena_mprj[59] ;
+ wire \la_iena_mprj[5] ;
+ wire \la_iena_mprj[60] ;
+ wire \la_iena_mprj[61] ;
+ wire \la_iena_mprj[62] ;
+ wire \la_iena_mprj[63] ;
+ wire \la_iena_mprj[64] ;
+ wire \la_iena_mprj[65] ;
+ wire \la_iena_mprj[66] ;
+ wire \la_iena_mprj[67] ;
+ wire \la_iena_mprj[68] ;
+ wire \la_iena_mprj[69] ;
+ wire \la_iena_mprj[6] ;
+ wire \la_iena_mprj[70] ;
+ wire \la_iena_mprj[71] ;
+ wire \la_iena_mprj[72] ;
+ wire \la_iena_mprj[73] ;
+ wire \la_iena_mprj[74] ;
+ wire \la_iena_mprj[75] ;
+ wire \la_iena_mprj[76] ;
+ wire \la_iena_mprj[77] ;
+ wire \la_iena_mprj[78] ;
+ wire \la_iena_mprj[79] ;
+ wire \la_iena_mprj[7] ;
+ wire \la_iena_mprj[80] ;
+ wire \la_iena_mprj[81] ;
+ wire \la_iena_mprj[82] ;
+ wire \la_iena_mprj[83] ;
+ wire \la_iena_mprj[84] ;
+ wire \la_iena_mprj[85] ;
+ wire \la_iena_mprj[86] ;
+ wire \la_iena_mprj[87] ;
+ wire \la_iena_mprj[88] ;
+ wire \la_iena_mprj[89] ;
+ wire \la_iena_mprj[8] ;
+ wire \la_iena_mprj[90] ;
+ wire \la_iena_mprj[91] ;
+ wire \la_iena_mprj[92] ;
+ wire \la_iena_mprj[93] ;
+ wire \la_iena_mprj[94] ;
+ wire \la_iena_mprj[95] ;
+ wire \la_iena_mprj[96] ;
+ wire \la_iena_mprj[97] ;
+ wire \la_iena_mprj[98] ;
+ wire \la_iena_mprj[99] ;
+ wire \la_iena_mprj[9] ;
+ wire \la_oenb_mprj[0] ;
+ wire \la_oenb_mprj[100] ;
+ wire \la_oenb_mprj[101] ;
+ wire \la_oenb_mprj[102] ;
+ wire \la_oenb_mprj[103] ;
+ wire \la_oenb_mprj[104] ;
+ wire \la_oenb_mprj[105] ;
+ wire \la_oenb_mprj[106] ;
+ wire \la_oenb_mprj[107] ;
+ wire \la_oenb_mprj[108] ;
+ wire \la_oenb_mprj[109] ;
+ wire \la_oenb_mprj[10] ;
+ wire \la_oenb_mprj[110] ;
+ wire \la_oenb_mprj[111] ;
+ wire \la_oenb_mprj[112] ;
+ wire \la_oenb_mprj[113] ;
+ wire \la_oenb_mprj[114] ;
+ wire \la_oenb_mprj[115] ;
+ wire \la_oenb_mprj[116] ;
+ wire \la_oenb_mprj[117] ;
+ wire \la_oenb_mprj[118] ;
+ wire \la_oenb_mprj[119] ;
+ wire \la_oenb_mprj[11] ;
+ wire \la_oenb_mprj[120] ;
+ wire \la_oenb_mprj[121] ;
+ wire \la_oenb_mprj[122] ;
+ wire \la_oenb_mprj[123] ;
+ wire \la_oenb_mprj[124] ;
+ wire \la_oenb_mprj[125] ;
+ wire \la_oenb_mprj[126] ;
+ wire \la_oenb_mprj[127] ;
+ wire \la_oenb_mprj[12] ;
+ wire \la_oenb_mprj[13] ;
+ wire \la_oenb_mprj[14] ;
+ wire \la_oenb_mprj[15] ;
+ wire \la_oenb_mprj[16] ;
+ wire \la_oenb_mprj[17] ;
+ wire \la_oenb_mprj[18] ;
+ wire \la_oenb_mprj[19] ;
+ wire \la_oenb_mprj[1] ;
+ wire \la_oenb_mprj[20] ;
+ wire \la_oenb_mprj[21] ;
+ wire \la_oenb_mprj[22] ;
+ wire \la_oenb_mprj[23] ;
+ wire \la_oenb_mprj[24] ;
+ wire \la_oenb_mprj[25] ;
+ wire \la_oenb_mprj[26] ;
+ wire \la_oenb_mprj[27] ;
+ wire \la_oenb_mprj[28] ;
+ wire \la_oenb_mprj[29] ;
+ wire \la_oenb_mprj[2] ;
+ wire \la_oenb_mprj[30] ;
+ wire \la_oenb_mprj[31] ;
+ wire \la_oenb_mprj[32] ;
+ wire \la_oenb_mprj[33] ;
+ wire \la_oenb_mprj[34] ;
+ wire \la_oenb_mprj[35] ;
+ wire \la_oenb_mprj[36] ;
+ wire \la_oenb_mprj[37] ;
+ wire \la_oenb_mprj[38] ;
+ wire \la_oenb_mprj[39] ;
+ wire \la_oenb_mprj[3] ;
+ wire \la_oenb_mprj[40] ;
+ wire \la_oenb_mprj[41] ;
+ wire \la_oenb_mprj[42] ;
+ wire \la_oenb_mprj[43] ;
+ wire \la_oenb_mprj[44] ;
+ wire \la_oenb_mprj[45] ;
+ wire \la_oenb_mprj[46] ;
+ wire \la_oenb_mprj[47] ;
+ wire \la_oenb_mprj[48] ;
+ wire \la_oenb_mprj[49] ;
+ wire \la_oenb_mprj[4] ;
+ wire \la_oenb_mprj[50] ;
+ wire \la_oenb_mprj[51] ;
+ wire \la_oenb_mprj[52] ;
+ wire \la_oenb_mprj[53] ;
+ wire \la_oenb_mprj[54] ;
+ wire \la_oenb_mprj[55] ;
+ wire \la_oenb_mprj[56] ;
+ wire \la_oenb_mprj[57] ;
+ wire \la_oenb_mprj[58] ;
+ wire \la_oenb_mprj[59] ;
+ wire \la_oenb_mprj[5] ;
+ wire \la_oenb_mprj[60] ;
+ wire \la_oenb_mprj[61] ;
+ wire \la_oenb_mprj[62] ;
+ wire \la_oenb_mprj[63] ;
+ wire \la_oenb_mprj[64] ;
+ wire \la_oenb_mprj[65] ;
+ wire \la_oenb_mprj[66] ;
+ wire \la_oenb_mprj[67] ;
+ wire \la_oenb_mprj[68] ;
+ wire \la_oenb_mprj[69] ;
+ wire \la_oenb_mprj[6] ;
+ wire \la_oenb_mprj[70] ;
+ wire \la_oenb_mprj[71] ;
+ wire \la_oenb_mprj[72] ;
+ wire \la_oenb_mprj[73] ;
+ wire \la_oenb_mprj[74] ;
+ wire \la_oenb_mprj[75] ;
+ wire \la_oenb_mprj[76] ;
+ wire \la_oenb_mprj[77] ;
+ wire \la_oenb_mprj[78] ;
+ wire \la_oenb_mprj[79] ;
+ wire \la_oenb_mprj[7] ;
+ wire \la_oenb_mprj[80] ;
+ wire \la_oenb_mprj[81] ;
+ wire \la_oenb_mprj[82] ;
+ wire \la_oenb_mprj[83] ;
+ wire \la_oenb_mprj[84] ;
+ wire \la_oenb_mprj[85] ;
+ wire \la_oenb_mprj[86] ;
+ wire \la_oenb_mprj[87] ;
+ wire \la_oenb_mprj[88] ;
+ wire \la_oenb_mprj[89] ;
+ wire \la_oenb_mprj[8] ;
+ wire \la_oenb_mprj[90] ;
+ wire \la_oenb_mprj[91] ;
+ wire \la_oenb_mprj[92] ;
+ wire \la_oenb_mprj[93] ;
+ wire \la_oenb_mprj[94] ;
+ wire \la_oenb_mprj[95] ;
+ wire \la_oenb_mprj[96] ;
+ wire \la_oenb_mprj[97] ;
+ wire \la_oenb_mprj[98] ;
+ wire \la_oenb_mprj[99] ;
+ wire \la_oenb_mprj[9] ;
+ wire \la_oenb_user[0] ;
+ wire \la_oenb_user[100] ;
+ wire \la_oenb_user[101] ;
+ wire \la_oenb_user[102] ;
+ wire \la_oenb_user[103] ;
+ wire \la_oenb_user[104] ;
+ wire \la_oenb_user[105] ;
+ wire \la_oenb_user[106] ;
+ wire \la_oenb_user[107] ;
+ wire \la_oenb_user[108] ;
+ wire \la_oenb_user[109] ;
+ wire \la_oenb_user[10] ;
+ wire \la_oenb_user[110] ;
+ wire \la_oenb_user[111] ;
+ wire \la_oenb_user[112] ;
+ wire \la_oenb_user[113] ;
+ wire \la_oenb_user[114] ;
+ wire \la_oenb_user[115] ;
+ wire \la_oenb_user[116] ;
+ wire \la_oenb_user[117] ;
+ wire \la_oenb_user[118] ;
+ wire \la_oenb_user[119] ;
+ wire \la_oenb_user[11] ;
+ wire \la_oenb_user[120] ;
+ wire \la_oenb_user[121] ;
+ wire \la_oenb_user[122] ;
+ wire \la_oenb_user[123] ;
+ wire \la_oenb_user[124] ;
+ wire \la_oenb_user[125] ;
+ wire \la_oenb_user[126] ;
+ wire \la_oenb_user[127] ;
+ wire \la_oenb_user[12] ;
+ wire \la_oenb_user[13] ;
+ wire \la_oenb_user[14] ;
+ wire \la_oenb_user[15] ;
+ wire \la_oenb_user[16] ;
+ wire \la_oenb_user[17] ;
+ wire \la_oenb_user[18] ;
+ wire \la_oenb_user[19] ;
+ wire \la_oenb_user[1] ;
+ wire \la_oenb_user[20] ;
+ wire \la_oenb_user[21] ;
+ wire \la_oenb_user[22] ;
+ wire \la_oenb_user[23] ;
+ wire \la_oenb_user[24] ;
+ wire \la_oenb_user[25] ;
+ wire \la_oenb_user[26] ;
+ wire \la_oenb_user[27] ;
+ wire \la_oenb_user[28] ;
+ wire \la_oenb_user[29] ;
+ wire \la_oenb_user[2] ;
+ wire \la_oenb_user[30] ;
+ wire \la_oenb_user[31] ;
+ wire \la_oenb_user[32] ;
+ wire \la_oenb_user[33] ;
+ wire \la_oenb_user[34] ;
+ wire \la_oenb_user[35] ;
+ wire \la_oenb_user[36] ;
+ wire \la_oenb_user[37] ;
+ wire \la_oenb_user[38] ;
+ wire \la_oenb_user[39] ;
+ wire \la_oenb_user[3] ;
+ wire \la_oenb_user[40] ;
+ wire \la_oenb_user[41] ;
+ wire \la_oenb_user[42] ;
+ wire \la_oenb_user[43] ;
+ wire \la_oenb_user[44] ;
+ wire \la_oenb_user[45] ;
+ wire \la_oenb_user[46] ;
+ wire \la_oenb_user[47] ;
+ wire \la_oenb_user[48] ;
+ wire \la_oenb_user[49] ;
+ wire \la_oenb_user[4] ;
+ wire \la_oenb_user[50] ;
+ wire \la_oenb_user[51] ;
+ wire \la_oenb_user[52] ;
+ wire \la_oenb_user[53] ;
+ wire \la_oenb_user[54] ;
+ wire \la_oenb_user[55] ;
+ wire \la_oenb_user[56] ;
+ wire \la_oenb_user[57] ;
+ wire \la_oenb_user[58] ;
+ wire \la_oenb_user[59] ;
+ wire \la_oenb_user[5] ;
+ wire \la_oenb_user[60] ;
+ wire \la_oenb_user[61] ;
+ wire \la_oenb_user[62] ;
+ wire \la_oenb_user[63] ;
+ wire \la_oenb_user[64] ;
+ wire \la_oenb_user[65] ;
+ wire \la_oenb_user[66] ;
+ wire \la_oenb_user[67] ;
+ wire \la_oenb_user[68] ;
+ wire \la_oenb_user[69] ;
+ wire \la_oenb_user[6] ;
+ wire \la_oenb_user[70] ;
+ wire \la_oenb_user[71] ;
+ wire \la_oenb_user[72] ;
+ wire \la_oenb_user[73] ;
+ wire \la_oenb_user[74] ;
+ wire \la_oenb_user[75] ;
+ wire \la_oenb_user[76] ;
+ wire \la_oenb_user[77] ;
+ wire \la_oenb_user[78] ;
+ wire \la_oenb_user[79] ;
+ wire \la_oenb_user[7] ;
+ wire \la_oenb_user[80] ;
+ wire \la_oenb_user[81] ;
+ wire \la_oenb_user[82] ;
+ wire \la_oenb_user[83] ;
+ wire \la_oenb_user[84] ;
+ wire \la_oenb_user[85] ;
+ wire \la_oenb_user[86] ;
+ wire \la_oenb_user[87] ;
+ wire \la_oenb_user[88] ;
+ wire \la_oenb_user[89] ;
+ wire \la_oenb_user[8] ;
+ wire \la_oenb_user[90] ;
+ wire \la_oenb_user[91] ;
+ wire \la_oenb_user[92] ;
+ wire \la_oenb_user[93] ;
+ wire \la_oenb_user[94] ;
+ wire \la_oenb_user[95] ;
+ wire \la_oenb_user[96] ;
+ wire \la_oenb_user[97] ;
+ wire \la_oenb_user[98] ;
+ wire \la_oenb_user[99] ;
+ wire \la_oenb_user[9] ;
+ wire \mask_rev[0] ;
+ wire \mask_rev[10] ;
+ wire \mask_rev[11] ;
+ wire \mask_rev[12] ;
+ wire \mask_rev[13] ;
+ wire \mask_rev[14] ;
+ wire \mask_rev[15] ;
+ wire \mask_rev[16] ;
+ wire \mask_rev[17] ;
+ wire \mask_rev[18] ;
+ wire \mask_rev[19] ;
+ wire \mask_rev[1] ;
+ wire \mask_rev[20] ;
+ wire \mask_rev[21] ;
+ wire \mask_rev[22] ;
+ wire \mask_rev[23] ;
+ wire \mask_rev[24] ;
+ wire \mask_rev[25] ;
+ wire \mask_rev[26] ;
+ wire \mask_rev[27] ;
+ wire \mask_rev[28] ;
+ wire \mask_rev[29] ;
+ wire \mask_rev[2] ;
+ wire \mask_rev[30] ;
+ wire \mask_rev[31] ;
+ wire \mask_rev[3] ;
+ wire \mask_rev[4] ;
+ wire \mask_rev[5] ;
+ wire \mask_rev[6] ;
+ wire \mask_rev[7] ;
+ wire \mask_rev[8] ;
+ wire \mask_rev[9] ;
+ wire \mgmt_io_in[0] ;
+ wire \mgmt_io_in[10] ;
+ wire \mgmt_io_in[11] ;
+ wire \mgmt_io_in[12] ;
+ wire \mgmt_io_in[13] ;
+ wire \mgmt_io_in[14] ;
+ wire \mgmt_io_in[15] ;
+ wire \mgmt_io_in[16] ;
+ wire \mgmt_io_in[17] ;
+ wire \mgmt_io_in[18] ;
+ wire \mgmt_io_in[19] ;
+ wire \mgmt_io_in[1] ;
+ wire \mgmt_io_in[20] ;
+ wire \mgmt_io_in[21] ;
+ wire \mgmt_io_in[22] ;
+ wire \mgmt_io_in[23] ;
+ wire \mgmt_io_in[24] ;
+ wire \mgmt_io_in[25] ;
+ wire \mgmt_io_in[26] ;
+ wire \mgmt_io_in[27] ;
+ wire \mgmt_io_in[28] ;
+ wire \mgmt_io_in[29] ;
+ wire \mgmt_io_in[2] ;
+ wire \mgmt_io_in[30] ;
+ wire \mgmt_io_in[31] ;
+ wire \mgmt_io_in[32] ;
+ wire \mgmt_io_in[33] ;
+ wire \mgmt_io_in[34] ;
+ wire \mgmt_io_in[35] ;
+ wire \mgmt_io_in[36] ;
+ wire \mgmt_io_in[37] ;
+ wire \mgmt_io_in[3] ;
+ wire \mgmt_io_in[4] ;
+ wire \mgmt_io_in[5] ;
+ wire \mgmt_io_in[6] ;
+ wire \mgmt_io_in[7] ;
+ wire \mgmt_io_in[8] ;
+ wire \mgmt_io_in[9] ;
+ wire \mgmt_io_nc[0] ;
+ wire \mgmt_io_nc[10] ;
+ wire \mgmt_io_nc[11] ;
+ wire \mgmt_io_nc[12] ;
+ wire \mgmt_io_nc[13] ;
+ wire \mgmt_io_nc[14] ;
+ wire \mgmt_io_nc[15] ;
+ wire \mgmt_io_nc[16] ;
+ wire \mgmt_io_nc[17] ;
+ wire \mgmt_io_nc[18] ;
+ wire \mgmt_io_nc[19] ;
+ wire \mgmt_io_nc[1] ;
+ wire \mgmt_io_nc[20] ;
+ wire \mgmt_io_nc[21] ;
+ wire \mgmt_io_nc[22] ;
+ wire \mgmt_io_nc[23] ;
+ wire \mgmt_io_nc[24] ;
+ wire \mgmt_io_nc[25] ;
+ wire \mgmt_io_nc[26] ;
+ wire \mgmt_io_nc[27] ;
+ wire \mgmt_io_nc[28] ;
+ wire \mgmt_io_nc[29] ;
+ wire \mgmt_io_nc[2] ;
+ wire \mgmt_io_nc[30] ;
+ wire \mgmt_io_nc[31] ;
+ wire \mgmt_io_nc[32] ;
+ wire \mgmt_io_nc[33] ;
+ wire \mgmt_io_nc[34] ;
+ wire \mgmt_io_nc[35] ;
+ wire \mgmt_io_nc[36] ;
+ wire \mgmt_io_nc[37] ;
+ wire \mgmt_io_nc[3] ;
+ wire \mgmt_io_nc[4] ;
+ wire \mgmt_io_nc[5] ;
+ wire \mgmt_io_nc[6] ;
+ wire \mgmt_io_nc[7] ;
+ wire \mgmt_io_nc[8] ;
+ wire \mgmt_io_nc[9] ;
+ wire \mgmt_io_oeb[0] ;
+ wire \mgmt_io_oeb[1] ;
+ wire \mgmt_io_oeb[2] ;
+ wire \mgmt_io_oeb[3] ;
+ wire \mgmt_io_oeb[4] ;
+ wire \mgmt_io_out[0] ;
+ wire \mgmt_io_out[1] ;
+ wire \mgmt_io_out[2] ;
+ wire \mgmt_io_out[3] ;
+ wire \mgmt_io_out[4] ;
+ wire mprj2_vcc_pwrgood;
+ wire mprj2_vdd_pwrgood;
+ wire mprj_ack_i_core;
+ wire mprj_ack_i_user;
+ wire \mprj_adr_o_core[0] ;
+ wire \mprj_adr_o_core[10] ;
+ wire \mprj_adr_o_core[11] ;
+ wire \mprj_adr_o_core[12] ;
+ wire \mprj_adr_o_core[13] ;
+ wire \mprj_adr_o_core[14] ;
+ wire \mprj_adr_o_core[15] ;
+ wire \mprj_adr_o_core[16] ;
+ wire \mprj_adr_o_core[17] ;
+ wire \mprj_adr_o_core[18] ;
+ wire \mprj_adr_o_core[19] ;
+ wire \mprj_adr_o_core[1] ;
+ wire \mprj_adr_o_core[20] ;
+ wire \mprj_adr_o_core[21] ;
+ wire \mprj_adr_o_core[22] ;
+ wire \mprj_adr_o_core[23] ;
+ wire \mprj_adr_o_core[24] ;
+ wire \mprj_adr_o_core[25] ;
+ wire \mprj_adr_o_core[26] ;
+ wire \mprj_adr_o_core[27] ;
+ wire \mprj_adr_o_core[28] ;
+ wire \mprj_adr_o_core[29] ;
+ wire \mprj_adr_o_core[2] ;
+ wire \mprj_adr_o_core[30] ;
+ wire \mprj_adr_o_core[31] ;
+ wire \mprj_adr_o_core[3] ;
+ wire \mprj_adr_o_core[4] ;
+ wire \mprj_adr_o_core[5] ;
+ wire \mprj_adr_o_core[6] ;
+ wire \mprj_adr_o_core[7] ;
+ wire \mprj_adr_o_core[8] ;
+ wire \mprj_adr_o_core[9] ;
+ wire \mprj_adr_o_user[0] ;
+ wire \mprj_adr_o_user[10] ;
+ wire \mprj_adr_o_user[11] ;
+ wire \mprj_adr_o_user[12] ;
+ wire \mprj_adr_o_user[13] ;
+ wire \mprj_adr_o_user[14] ;
+ wire \mprj_adr_o_user[15] ;
+ wire \mprj_adr_o_user[16] ;
+ wire \mprj_adr_o_user[17] ;
+ wire \mprj_adr_o_user[18] ;
+ wire \mprj_adr_o_user[19] ;
+ wire \mprj_adr_o_user[1] ;
+ wire \mprj_adr_o_user[20] ;
+ wire \mprj_adr_o_user[21] ;
+ wire \mprj_adr_o_user[22] ;
+ wire \mprj_adr_o_user[23] ;
+ wire \mprj_adr_o_user[24] ;
+ wire \mprj_adr_o_user[25] ;
+ wire \mprj_adr_o_user[26] ;
+ wire \mprj_adr_o_user[27] ;
+ wire \mprj_adr_o_user[28] ;
+ wire \mprj_adr_o_user[29] ;
+ wire \mprj_adr_o_user[2] ;
+ wire \mprj_adr_o_user[30] ;
+ wire \mprj_adr_o_user[31] ;
+ wire \mprj_adr_o_user[3] ;
+ wire \mprj_adr_o_user[4] ;
+ wire \mprj_adr_o_user[5] ;
+ wire \mprj_adr_o_user[6] ;
+ wire \mprj_adr_o_user[7] ;
+ wire \mprj_adr_o_user[8] ;
+ wire \mprj_adr_o_user[9] ;
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_cyc_o_core;
+ wire mprj_cyc_o_user;
+ wire \mprj_dat_i_core[0] ;
+ wire \mprj_dat_i_core[10] ;
+ wire \mprj_dat_i_core[11] ;
+ wire \mprj_dat_i_core[12] ;
+ wire \mprj_dat_i_core[13] ;
+ wire \mprj_dat_i_core[14] ;
+ wire \mprj_dat_i_core[15] ;
+ wire \mprj_dat_i_core[16] ;
+ wire \mprj_dat_i_core[17] ;
+ wire \mprj_dat_i_core[18] ;
+ wire \mprj_dat_i_core[19] ;
+ wire \mprj_dat_i_core[1] ;
+ wire \mprj_dat_i_core[20] ;
+ wire \mprj_dat_i_core[21] ;
+ wire \mprj_dat_i_core[22] ;
+ wire \mprj_dat_i_core[23] ;
+ wire \mprj_dat_i_core[24] ;
+ wire \mprj_dat_i_core[25] ;
+ wire \mprj_dat_i_core[26] ;
+ wire \mprj_dat_i_core[27] ;
+ wire \mprj_dat_i_core[28] ;
+ wire \mprj_dat_i_core[29] ;
+ wire \mprj_dat_i_core[2] ;
+ wire \mprj_dat_i_core[30] ;
+ wire \mprj_dat_i_core[31] ;
+ wire \mprj_dat_i_core[3] ;
+ wire \mprj_dat_i_core[4] ;
+ wire \mprj_dat_i_core[5] ;
+ wire \mprj_dat_i_core[6] ;
+ wire \mprj_dat_i_core[7] ;
+ wire \mprj_dat_i_core[8] ;
+ wire \mprj_dat_i_core[9] ;
+ wire \mprj_dat_i_user[0] ;
+ wire \mprj_dat_i_user[10] ;
+ wire \mprj_dat_i_user[11] ;
+ wire \mprj_dat_i_user[12] ;
+ wire \mprj_dat_i_user[13] ;
+ wire \mprj_dat_i_user[14] ;
+ wire \mprj_dat_i_user[15] ;
+ wire \mprj_dat_i_user[16] ;
+ wire \mprj_dat_i_user[17] ;
+ wire \mprj_dat_i_user[18] ;
+ wire \mprj_dat_i_user[19] ;
+ wire \mprj_dat_i_user[1] ;
+ wire \mprj_dat_i_user[20] ;
+ wire \mprj_dat_i_user[21] ;
+ wire \mprj_dat_i_user[22] ;
+ wire \mprj_dat_i_user[23] ;
+ wire \mprj_dat_i_user[24] ;
+ wire \mprj_dat_i_user[25] ;
+ wire \mprj_dat_i_user[26] ;
+ wire \mprj_dat_i_user[27] ;
+ wire \mprj_dat_i_user[28] ;
+ wire \mprj_dat_i_user[29] ;
+ wire \mprj_dat_i_user[2] ;
+ wire \mprj_dat_i_user[30] ;
+ wire \mprj_dat_i_user[31] ;
+ wire \mprj_dat_i_user[3] ;
+ wire \mprj_dat_i_user[4] ;
+ wire \mprj_dat_i_user[5] ;
+ wire \mprj_dat_i_user[6] ;
+ wire \mprj_dat_i_user[7] ;
+ wire \mprj_dat_i_user[8] ;
+ wire \mprj_dat_i_user[9] ;
+ wire \mprj_dat_o_core[0] ;
+ wire \mprj_dat_o_core[10] ;
+ wire \mprj_dat_o_core[11] ;
+ wire \mprj_dat_o_core[12] ;
+ wire \mprj_dat_o_core[13] ;
+ wire \mprj_dat_o_core[14] ;
+ wire \mprj_dat_o_core[15] ;
+ wire \mprj_dat_o_core[16] ;
+ wire \mprj_dat_o_core[17] ;
+ wire \mprj_dat_o_core[18] ;
+ wire \mprj_dat_o_core[19] ;
+ wire \mprj_dat_o_core[1] ;
+ wire \mprj_dat_o_core[20] ;
+ wire \mprj_dat_o_core[21] ;
+ wire \mprj_dat_o_core[22] ;
+ wire \mprj_dat_o_core[23] ;
+ wire \mprj_dat_o_core[24] ;
+ wire \mprj_dat_o_core[25] ;
+ wire \mprj_dat_o_core[26] ;
+ wire \mprj_dat_o_core[27] ;
+ wire \mprj_dat_o_core[28] ;
+ wire \mprj_dat_o_core[29] ;
+ wire \mprj_dat_o_core[2] ;
+ wire \mprj_dat_o_core[30] ;
+ wire \mprj_dat_o_core[31] ;
+ wire \mprj_dat_o_core[3] ;
+ wire \mprj_dat_o_core[4] ;
+ wire \mprj_dat_o_core[5] ;
+ wire \mprj_dat_o_core[6] ;
+ wire \mprj_dat_o_core[7] ;
+ wire \mprj_dat_o_core[8] ;
+ wire \mprj_dat_o_core[9] ;
+ wire \mprj_dat_o_user[0] ;
+ wire \mprj_dat_o_user[10] ;
+ wire \mprj_dat_o_user[11] ;
+ wire \mprj_dat_o_user[12] ;
+ wire \mprj_dat_o_user[13] ;
+ wire \mprj_dat_o_user[14] ;
+ wire \mprj_dat_o_user[15] ;
+ wire \mprj_dat_o_user[16] ;
+ wire \mprj_dat_o_user[17] ;
+ wire \mprj_dat_o_user[18] ;
+ wire \mprj_dat_o_user[19] ;
+ wire \mprj_dat_o_user[1] ;
+ wire \mprj_dat_o_user[20] ;
+ wire \mprj_dat_o_user[21] ;
+ wire \mprj_dat_o_user[22] ;
+ wire \mprj_dat_o_user[23] ;
+ wire \mprj_dat_o_user[24] ;
+ wire \mprj_dat_o_user[25] ;
+ wire \mprj_dat_o_user[26] ;
+ wire \mprj_dat_o_user[27] ;
+ wire \mprj_dat_o_user[28] ;
+ wire \mprj_dat_o_user[29] ;
+ wire \mprj_dat_o_user[2] ;
+ wire \mprj_dat_o_user[30] ;
+ wire \mprj_dat_o_user[31] ;
+ wire \mprj_dat_o_user[3] ;
+ wire \mprj_dat_o_user[4] ;
+ wire \mprj_dat_o_user[5] ;
+ wire \mprj_dat_o_user[6] ;
+ wire \mprj_dat_o_user[7] ;
+ wire \mprj_dat_o_user[8] ;
+ wire \mprj_dat_o_user[9] ;
+ wire mprj_iena_wb;
+ inout [37:0] mprj_io;
+ wire \mprj_io_analog_en[0] ;
+ wire \mprj_io_analog_en[10] ;
+ wire \mprj_io_analog_en[11] ;
+ wire \mprj_io_analog_en[12] ;
+ wire \mprj_io_analog_en[13] ;
+ wire \mprj_io_analog_en[14] ;
+ wire \mprj_io_analog_en[15] ;
+ wire \mprj_io_analog_en[16] ;
+ wire \mprj_io_analog_en[17] ;
+ wire \mprj_io_analog_en[18] ;
+ wire \mprj_io_analog_en[19] ;
+ wire \mprj_io_analog_en[1] ;
+ wire \mprj_io_analog_en[20] ;
+ wire \mprj_io_analog_en[21] ;
+ wire \mprj_io_analog_en[22] ;
+ wire \mprj_io_analog_en[23] ;
+ wire \mprj_io_analog_en[24] ;
+ wire \mprj_io_analog_en[25] ;
+ wire \mprj_io_analog_en[26] ;
+ wire \mprj_io_analog_en[2] ;
+ wire \mprj_io_analog_en[3] ;
+ wire \mprj_io_analog_en[4] ;
+ wire \mprj_io_analog_en[5] ;
+ wire \mprj_io_analog_en[6] ;
+ wire \mprj_io_analog_en[7] ;
+ wire \mprj_io_analog_en[8] ;
+ wire \mprj_io_analog_en[9] ;
+ wire \mprj_io_analog_pol[0] ;
+ wire \mprj_io_analog_pol[10] ;
+ wire \mprj_io_analog_pol[11] ;
+ wire \mprj_io_analog_pol[12] ;
+ wire \mprj_io_analog_pol[13] ;
+ wire \mprj_io_analog_pol[14] ;
+ wire \mprj_io_analog_pol[15] ;
+ wire \mprj_io_analog_pol[16] ;
+ wire \mprj_io_analog_pol[17] ;
+ wire \mprj_io_analog_pol[18] ;
+ wire \mprj_io_analog_pol[19] ;
+ wire \mprj_io_analog_pol[1] ;
+ wire \mprj_io_analog_pol[20] ;
+ wire \mprj_io_analog_pol[21] ;
+ wire \mprj_io_analog_pol[22] ;
+ wire \mprj_io_analog_pol[23] ;
+ wire \mprj_io_analog_pol[24] ;
+ wire \mprj_io_analog_pol[25] ;
+ wire \mprj_io_analog_pol[26] ;
+ wire \mprj_io_analog_pol[2] ;
+ wire \mprj_io_analog_pol[3] ;
+ wire \mprj_io_analog_pol[4] ;
+ wire \mprj_io_analog_pol[5] ;
+ wire \mprj_io_analog_pol[6] ;
+ wire \mprj_io_analog_pol[7] ;
+ wire \mprj_io_analog_pol[8] ;
+ wire \mprj_io_analog_pol[9] ;
+ wire \mprj_io_analog_sel[0] ;
+ wire \mprj_io_analog_sel[10] ;
+ wire \mprj_io_analog_sel[11] ;
+ wire \mprj_io_analog_sel[12] ;
+ wire \mprj_io_analog_sel[13] ;
+ wire \mprj_io_analog_sel[14] ;
+ wire \mprj_io_analog_sel[15] ;
+ wire \mprj_io_analog_sel[16] ;
+ wire \mprj_io_analog_sel[17] ;
+ wire \mprj_io_analog_sel[18] ;
+ wire \mprj_io_analog_sel[19] ;
+ wire \mprj_io_analog_sel[1] ;
+ wire \mprj_io_analog_sel[20] ;
+ wire \mprj_io_analog_sel[21] ;
+ wire \mprj_io_analog_sel[22] ;
+ wire \mprj_io_analog_sel[23] ;
+ wire \mprj_io_analog_sel[24] ;
+ wire \mprj_io_analog_sel[25] ;
+ wire \mprj_io_analog_sel[26] ;
+ wire \mprj_io_analog_sel[2] ;
+ wire \mprj_io_analog_sel[3] ;
+ wire \mprj_io_analog_sel[4] ;
+ wire \mprj_io_analog_sel[5] ;
+ wire \mprj_io_analog_sel[6] ;
+ wire \mprj_io_analog_sel[7] ;
+ wire \mprj_io_analog_sel[8] ;
+ wire \mprj_io_analog_sel[9] ;
+ wire \mprj_io_dm[0] ;
+ wire \mprj_io_dm[10] ;
+ wire \mprj_io_dm[11] ;
+ wire \mprj_io_dm[12] ;
+ wire \mprj_io_dm[13] ;
+ wire \mprj_io_dm[14] ;
+ wire \mprj_io_dm[15] ;
+ wire \mprj_io_dm[16] ;
+ wire \mprj_io_dm[17] ;
+ wire \mprj_io_dm[18] ;
+ wire \mprj_io_dm[19] ;
+ wire \mprj_io_dm[1] ;
+ wire \mprj_io_dm[20] ;
+ wire \mprj_io_dm[21] ;
+ wire \mprj_io_dm[22] ;
+ wire \mprj_io_dm[23] ;
+ wire \mprj_io_dm[24] ;
+ wire \mprj_io_dm[25] ;
+ wire \mprj_io_dm[26] ;
+ wire \mprj_io_dm[27] ;
+ wire \mprj_io_dm[28] ;
+ wire \mprj_io_dm[29] ;
+ wire \mprj_io_dm[2] ;
+ wire \mprj_io_dm[30] ;
+ wire \mprj_io_dm[31] ;
+ wire \mprj_io_dm[32] ;
+ wire \mprj_io_dm[33] ;
+ wire \mprj_io_dm[34] ;
+ wire \mprj_io_dm[35] ;
+ wire \mprj_io_dm[36] ;
+ wire \mprj_io_dm[37] ;
+ wire \mprj_io_dm[38] ;
+ wire \mprj_io_dm[39] ;
+ wire \mprj_io_dm[3] ;
+ wire \mprj_io_dm[40] ;
+ wire \mprj_io_dm[41] ;
+ wire \mprj_io_dm[42] ;
+ wire \mprj_io_dm[43] ;
+ wire \mprj_io_dm[44] ;
+ wire \mprj_io_dm[45] ;
+ wire \mprj_io_dm[46] ;
+ wire \mprj_io_dm[47] ;
+ wire \mprj_io_dm[48] ;
+ wire \mprj_io_dm[49] ;
+ wire \mprj_io_dm[4] ;
+ wire \mprj_io_dm[50] ;
+ wire \mprj_io_dm[51] ;
+ wire \mprj_io_dm[52] ;
+ wire \mprj_io_dm[53] ;
+ wire \mprj_io_dm[54] ;
+ wire \mprj_io_dm[55] ;
+ wire \mprj_io_dm[56] ;
+ wire \mprj_io_dm[57] ;
+ wire \mprj_io_dm[58] ;
+ wire \mprj_io_dm[59] ;
+ wire \mprj_io_dm[5] ;
+ wire \mprj_io_dm[60] ;
+ wire \mprj_io_dm[61] ;
+ wire \mprj_io_dm[62] ;
+ wire \mprj_io_dm[63] ;
+ wire \mprj_io_dm[64] ;
+ wire \mprj_io_dm[65] ;
+ wire \mprj_io_dm[66] ;
+ wire \mprj_io_dm[67] ;
+ wire \mprj_io_dm[68] ;
+ wire \mprj_io_dm[69] ;
+ wire \mprj_io_dm[6] ;
+ wire \mprj_io_dm[70] ;
+ wire \mprj_io_dm[71] ;
+ wire \mprj_io_dm[72] ;
+ wire \mprj_io_dm[73] ;
+ wire \mprj_io_dm[74] ;
+ wire \mprj_io_dm[75] ;
+ wire \mprj_io_dm[76] ;
+ wire \mprj_io_dm[77] ;
+ wire \mprj_io_dm[78] ;
+ wire \mprj_io_dm[79] ;
+ wire \mprj_io_dm[7] ;
+ wire \mprj_io_dm[80] ;
+ wire \mprj_io_dm[8] ;
+ wire \mprj_io_dm[9] ;
+ wire \mprj_io_holdover[0] ;
+ wire \mprj_io_holdover[10] ;
+ wire \mprj_io_holdover[11] ;
+ wire \mprj_io_holdover[12] ;
+ wire \mprj_io_holdover[13] ;
+ wire \mprj_io_holdover[14] ;
+ wire \mprj_io_holdover[15] ;
+ wire \mprj_io_holdover[16] ;
+ wire \mprj_io_holdover[17] ;
+ wire \mprj_io_holdover[18] ;
+ wire \mprj_io_holdover[19] ;
+ wire \mprj_io_holdover[1] ;
+ wire \mprj_io_holdover[20] ;
+ wire \mprj_io_holdover[21] ;
+ wire \mprj_io_holdover[22] ;
+ wire \mprj_io_holdover[23] ;
+ wire \mprj_io_holdover[24] ;
+ wire \mprj_io_holdover[25] ;
+ wire \mprj_io_holdover[26] ;
+ wire \mprj_io_holdover[2] ;
+ wire \mprj_io_holdover[3] ;
+ wire \mprj_io_holdover[4] ;
+ wire \mprj_io_holdover[5] ;
+ wire \mprj_io_holdover[6] ;
+ wire \mprj_io_holdover[7] ;
+ wire \mprj_io_holdover[8] ;
+ wire \mprj_io_holdover[9] ;
+ wire \mprj_io_ib_mode_sel[0] ;
+ wire \mprj_io_ib_mode_sel[10] ;
+ wire \mprj_io_ib_mode_sel[11] ;
+ wire \mprj_io_ib_mode_sel[12] ;
+ wire \mprj_io_ib_mode_sel[13] ;
+ wire \mprj_io_ib_mode_sel[14] ;
+ wire \mprj_io_ib_mode_sel[15] ;
+ wire \mprj_io_ib_mode_sel[16] ;
+ wire \mprj_io_ib_mode_sel[17] ;
+ wire \mprj_io_ib_mode_sel[18] ;
+ wire \mprj_io_ib_mode_sel[19] ;
+ wire \mprj_io_ib_mode_sel[1] ;
+ wire \mprj_io_ib_mode_sel[20] ;
+ wire \mprj_io_ib_mode_sel[21] ;
+ wire \mprj_io_ib_mode_sel[22] ;
+ wire \mprj_io_ib_mode_sel[23] ;
+ wire \mprj_io_ib_mode_sel[24] ;
+ wire \mprj_io_ib_mode_sel[25] ;
+ wire \mprj_io_ib_mode_sel[26] ;
+ wire \mprj_io_ib_mode_sel[2] ;
+ wire \mprj_io_ib_mode_sel[3] ;
+ wire \mprj_io_ib_mode_sel[4] ;
+ wire \mprj_io_ib_mode_sel[5] ;
+ wire \mprj_io_ib_mode_sel[6] ;
+ wire \mprj_io_ib_mode_sel[7] ;
+ wire \mprj_io_ib_mode_sel[8] ;
+ wire \mprj_io_ib_mode_sel[9] ;
+ wire \mprj_io_in[0] ;
+ wire \mprj_io_in[10] ;
+ wire \mprj_io_in[11] ;
+ wire \mprj_io_in[12] ;
+ wire \mprj_io_in[13] ;
+ wire \mprj_io_in[14] ;
+ wire \mprj_io_in[15] ;
+ wire \mprj_io_in[16] ;
+ wire \mprj_io_in[17] ;
+ wire \mprj_io_in[18] ;
+ wire \mprj_io_in[19] ;
+ wire \mprj_io_in[1] ;
+ wire \mprj_io_in[20] ;
+ wire \mprj_io_in[21] ;
+ wire \mprj_io_in[22] ;
+ wire \mprj_io_in[23] ;
+ wire \mprj_io_in[24] ;
+ wire \mprj_io_in[25] ;
+ wire \mprj_io_in[26] ;
+ wire \mprj_io_in[2] ;
+ wire \mprj_io_in[3] ;
+ wire \mprj_io_in[4] ;
+ wire \mprj_io_in[5] ;
+ wire \mprj_io_in[6] ;
+ wire \mprj_io_in[7] ;
+ wire \mprj_io_in[8] ;
+ wire \mprj_io_in[9] ;
+ wire \mprj_io_in_3v3[0] ;
+ wire \mprj_io_in_3v3[10] ;
+ wire \mprj_io_in_3v3[11] ;
+ wire \mprj_io_in_3v3[12] ;
+ wire \mprj_io_in_3v3[13] ;
+ wire \mprj_io_in_3v3[14] ;
+ wire \mprj_io_in_3v3[15] ;
+ wire \mprj_io_in_3v3[16] ;
+ wire \mprj_io_in_3v3[17] ;
+ wire \mprj_io_in_3v3[18] ;
+ wire \mprj_io_in_3v3[19] ;
+ wire \mprj_io_in_3v3[1] ;
+ wire \mprj_io_in_3v3[20] ;
+ wire \mprj_io_in_3v3[21] ;
+ wire \mprj_io_in_3v3[22] ;
+ wire \mprj_io_in_3v3[23] ;
+ wire \mprj_io_in_3v3[24] ;
+ wire \mprj_io_in_3v3[25] ;
+ wire \mprj_io_in_3v3[26] ;
+ wire \mprj_io_in_3v3[2] ;
+ wire \mprj_io_in_3v3[3] ;
+ wire \mprj_io_in_3v3[4] ;
+ wire \mprj_io_in_3v3[5] ;
+ wire \mprj_io_in_3v3[6] ;
+ wire \mprj_io_in_3v3[7] ;
+ wire \mprj_io_in_3v3[8] ;
+ wire \mprj_io_in_3v3[9] ;
+ wire \mprj_io_inp_dis[0] ;
+ wire \mprj_io_inp_dis[10] ;
+ wire \mprj_io_inp_dis[11] ;
+ wire \mprj_io_inp_dis[12] ;
+ wire \mprj_io_inp_dis[13] ;
+ wire \mprj_io_inp_dis[14] ;
+ wire \mprj_io_inp_dis[15] ;
+ wire \mprj_io_inp_dis[16] ;
+ wire \mprj_io_inp_dis[17] ;
+ wire \mprj_io_inp_dis[18] ;
+ wire \mprj_io_inp_dis[19] ;
+ wire \mprj_io_inp_dis[1] ;
+ wire \mprj_io_inp_dis[20] ;
+ wire \mprj_io_inp_dis[21] ;
+ wire \mprj_io_inp_dis[22] ;
+ wire \mprj_io_inp_dis[23] ;
+ wire \mprj_io_inp_dis[24] ;
+ wire \mprj_io_inp_dis[25] ;
+ wire \mprj_io_inp_dis[26] ;
+ wire \mprj_io_inp_dis[2] ;
+ wire \mprj_io_inp_dis[3] ;
+ wire \mprj_io_inp_dis[4] ;
+ wire \mprj_io_inp_dis[5] ;
+ wire \mprj_io_inp_dis[6] ;
+ wire \mprj_io_inp_dis[7] ;
+ wire \mprj_io_inp_dis[8] ;
+ wire \mprj_io_inp_dis[9] ;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1;
+ wire mprj_io_loader_data_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_strobe;
+ wire \mprj_io_oeb[0] ;
+ wire \mprj_io_oeb[10] ;
+ wire \mprj_io_oeb[11] ;
+ wire \mprj_io_oeb[12] ;
+ wire \mprj_io_oeb[13] ;
+ wire \mprj_io_oeb[14] ;
+ wire \mprj_io_oeb[15] ;
+ wire \mprj_io_oeb[16] ;
+ wire \mprj_io_oeb[17] ;
+ wire \mprj_io_oeb[18] ;
+ wire \mprj_io_oeb[19] ;
+ wire \mprj_io_oeb[1] ;
+ wire \mprj_io_oeb[20] ;
+ wire \mprj_io_oeb[21] ;
+ wire \mprj_io_oeb[22] ;
+ wire \mprj_io_oeb[23] ;
+ wire \mprj_io_oeb[24] ;
+ wire \mprj_io_oeb[25] ;
+ wire \mprj_io_oeb[26] ;
+ wire \mprj_io_oeb[2] ;
+ wire \mprj_io_oeb[3] ;
+ wire \mprj_io_oeb[4] ;
+ wire \mprj_io_oeb[5] ;
+ wire \mprj_io_oeb[6] ;
+ wire \mprj_io_oeb[7] ;
+ wire \mprj_io_oeb[8] ;
+ wire \mprj_io_oeb[9] ;
+ wire \mprj_io_out[0] ;
+ wire \mprj_io_out[10] ;
+ wire \mprj_io_out[11] ;
+ wire \mprj_io_out[12] ;
+ wire \mprj_io_out[13] ;
+ wire \mprj_io_out[14] ;
+ wire \mprj_io_out[15] ;
+ wire \mprj_io_out[16] ;
+ wire \mprj_io_out[17] ;
+ wire \mprj_io_out[18] ;
+ wire \mprj_io_out[19] ;
+ wire \mprj_io_out[1] ;
+ wire \mprj_io_out[20] ;
+ wire \mprj_io_out[21] ;
+ wire \mprj_io_out[22] ;
+ wire \mprj_io_out[23] ;
+ wire \mprj_io_out[24] ;
+ wire \mprj_io_out[25] ;
+ wire \mprj_io_out[26] ;
+ wire \mprj_io_out[2] ;
+ wire \mprj_io_out[3] ;
+ wire \mprj_io_out[4] ;
+ wire \mprj_io_out[5] ;
+ wire \mprj_io_out[6] ;
+ wire \mprj_io_out[7] ;
+ wire \mprj_io_out[8] ;
+ wire \mprj_io_out[9] ;
+ wire \mprj_io_slow_sel[0] ;
+ wire \mprj_io_slow_sel[10] ;
+ wire \mprj_io_slow_sel[11] ;
+ wire \mprj_io_slow_sel[12] ;
+ wire \mprj_io_slow_sel[13] ;
+ wire \mprj_io_slow_sel[14] ;
+ wire \mprj_io_slow_sel[15] ;
+ wire \mprj_io_slow_sel[16] ;
+ wire \mprj_io_slow_sel[17] ;
+ wire \mprj_io_slow_sel[18] ;
+ wire \mprj_io_slow_sel[19] ;
+ wire \mprj_io_slow_sel[1] ;
+ wire \mprj_io_slow_sel[20] ;
+ wire \mprj_io_slow_sel[21] ;
+ wire \mprj_io_slow_sel[22] ;
+ wire \mprj_io_slow_sel[23] ;
+ wire \mprj_io_slow_sel[24] ;
+ wire \mprj_io_slow_sel[25] ;
+ wire \mprj_io_slow_sel[26] ;
+ wire \mprj_io_slow_sel[2] ;
+ wire \mprj_io_slow_sel[3] ;
+ wire \mprj_io_slow_sel[4] ;
+ wire \mprj_io_slow_sel[5] ;
+ wire \mprj_io_slow_sel[6] ;
+ wire \mprj_io_slow_sel[7] ;
+ wire \mprj_io_slow_sel[8] ;
+ wire \mprj_io_slow_sel[9] ;
+ wire \mprj_io_vtrip_sel[0] ;
+ wire \mprj_io_vtrip_sel[10] ;
+ wire \mprj_io_vtrip_sel[11] ;
+ wire \mprj_io_vtrip_sel[12] ;
+ wire \mprj_io_vtrip_sel[13] ;
+ wire \mprj_io_vtrip_sel[14] ;
+ wire \mprj_io_vtrip_sel[15] ;
+ wire \mprj_io_vtrip_sel[16] ;
+ wire \mprj_io_vtrip_sel[17] ;
+ wire \mprj_io_vtrip_sel[18] ;
+ wire \mprj_io_vtrip_sel[19] ;
+ wire \mprj_io_vtrip_sel[1] ;
+ wire \mprj_io_vtrip_sel[20] ;
+ wire \mprj_io_vtrip_sel[21] ;
+ wire \mprj_io_vtrip_sel[22] ;
+ wire \mprj_io_vtrip_sel[23] ;
+ wire \mprj_io_vtrip_sel[24] ;
+ wire \mprj_io_vtrip_sel[25] ;
+ wire \mprj_io_vtrip_sel[26] ;
+ wire \mprj_io_vtrip_sel[2] ;
+ wire \mprj_io_vtrip_sel[3] ;
+ wire \mprj_io_vtrip_sel[4] ;
+ wire \mprj_io_vtrip_sel[5] ;
+ wire \mprj_io_vtrip_sel[6] ;
+ wire \mprj_io_vtrip_sel[7] ;
+ wire \mprj_io_vtrip_sel[8] ;
+ wire \mprj_io_vtrip_sel[9] ;
+ wire mprj_reset;
+ wire \mprj_sel_o_core[0] ;
+ wire \mprj_sel_o_core[1] ;
+ wire \mprj_sel_o_core[2] ;
+ wire \mprj_sel_o_core[3] ;
+ wire \mprj_sel_o_user[0] ;
+ wire \mprj_sel_o_user[1] ;
+ wire \mprj_sel_o_user[2] ;
+ wire \mprj_sel_o_user[3] ;
+ wire mprj_stb_o_core;
+ wire mprj_stb_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj_we_o_core;
+ wire mprj_we_o_user;
+ wire \one_loop1[0] ;
+ wire \one_loop1[10] ;
+ wire \one_loop1[11] ;
+ wire \one_loop1[1] ;
+ wire \one_loop1[2] ;
+ wire \one_loop1[3] ;
+ wire \one_loop1[4] ;
+ wire \one_loop1[5] ;
+ wire \one_loop1[6] ;
+ wire \one_loop1[7] ;
+ wire \one_loop1[8] ;
+ wire \one_loop1[9] ;
+ wire \one_loop2[0] ;
+ wire \one_loop2[1] ;
+ wire \one_loop2[2] ;
+ wire \one_loop2[3] ;
+ wire \one_loop2[4] ;
+ wire \one_loop2[5] ;
+ wire \one_loop2[6] ;
+ wire \one_loop2[7] ;
+ wire \one_loop2[8] ;
+ wire \one_loop2[9] ;
+ wire pll_clk;
+ wire pll_clk90;
+ wire por_l;
+ wire porb_h;
+ wire porb_l;
+ wire \pwr_ctrl_nc[0] ;
+ wire \pwr_ctrl_nc[1] ;
+ wire \pwr_ctrl_nc[2] ;
+ wire \pwr_ctrl_nc[3] ;
+ wire qspi_enabled;
+ input resetb;
+ wire rstb_h;
+ wire rstb_l;
+ wire sdo_out;
+ wire sdo_outenb;
+ wire ser_rx;
+ wire ser_tx;
+ wire spi_csb;
+ wire spi_enabled;
+ wire \spi_pll90_sel[0] ;
+ wire \spi_pll90_sel[1] ;
+ wire \spi_pll90_sel[2] ;
+ wire spi_pll_dco_ena;
+ wire \spi_pll_div[0] ;
+ wire \spi_pll_div[1] ;
+ wire \spi_pll_div[2] ;
+ wire \spi_pll_div[3] ;
+ wire \spi_pll_div[4] ;
+ wire spi_pll_ena;
+ wire \spi_pll_sel[0] ;
+ wire \spi_pll_sel[1] ;
+ wire \spi_pll_sel[2] ;
+ wire \spi_pll_trim[0] ;
+ wire \spi_pll_trim[10] ;
+ wire \spi_pll_trim[11] ;
+ wire \spi_pll_trim[12] ;
+ wire \spi_pll_trim[13] ;
+ wire \spi_pll_trim[14] ;
+ wire \spi_pll_trim[15] ;
+ wire \spi_pll_trim[16] ;
+ wire \spi_pll_trim[17] ;
+ wire \spi_pll_trim[18] ;
+ wire \spi_pll_trim[19] ;
+ wire \spi_pll_trim[1] ;
+ wire \spi_pll_trim[20] ;
+ wire \spi_pll_trim[21] ;
+ wire \spi_pll_trim[22] ;
+ wire \spi_pll_trim[23] ;
+ wire \spi_pll_trim[24] ;
+ wire \spi_pll_trim[25] ;
+ wire \spi_pll_trim[2] ;
+ wire \spi_pll_trim[3] ;
+ wire \spi_pll_trim[4] ;
+ wire \spi_pll_trim[5] ;
+ wire \spi_pll_trim[6] ;
+ wire \spi_pll_trim[7] ;
+ wire \spi_pll_trim[8] ;
+ wire \spi_pll_trim[9] ;
+ wire \spi_ro_config_core[0] ;
+ wire \spi_ro_config_core[1] ;
+ wire \spi_ro_config_core[2] ;
+ wire \spi_ro_config_core[3] ;
+ wire \spi_ro_config_core[4] ;
+ wire \spi_ro_config_core[5] ;
+ wire \spi_ro_config_core[6] ;
+ wire \spi_ro_config_core[7] ;
+ wire spi_sck;
+ wire spi_sdi;
+ wire spi_sdo;
+ wire spi_sdoenb;
+ wire trap;
+ wire uart_enabled;
+ wire \user_analog[0] ;
+ wire \user_analog[10] ;
+ wire \user_analog[1] ;
+ wire \user_analog[2] ;
+ wire \user_analog[3] ;
+ wire \user_analog[4] ;
+ wire \user_analog[5] ;
+ wire \user_analog[6] ;
+ wire \user_analog[7] ;
+ wire \user_analog[8] ;
+ wire \user_analog[9] ;
+ wire \user_clamp_high[0] ;
+ wire \user_clamp_high[1] ;
+ wire \user_clamp_high[2] ;
+ wire \user_clamp_low[0] ;
+ wire \user_clamp_low[1] ;
+ wire \user_clamp_low[2] ;
+ wire \user_gpio_analog[0] ;
+ wire \user_gpio_analog[10] ;
+ wire \user_gpio_analog[11] ;
+ wire \user_gpio_analog[12] ;
+ wire \user_gpio_analog[13] ;
+ wire \user_gpio_analog[14] ;
+ wire \user_gpio_analog[15] ;
+ wire \user_gpio_analog[16] ;
+ wire \user_gpio_analog[17] ;
+ wire \user_gpio_analog[1] ;
+ wire \user_gpio_analog[2] ;
+ wire \user_gpio_analog[3] ;
+ wire \user_gpio_analog[4] ;
+ wire \user_gpio_analog[5] ;
+ wire \user_gpio_analog[6] ;
+ wire \user_gpio_analog[7] ;
+ wire \user_gpio_analog[8] ;
+ wire \user_gpio_analog[9] ;
+ wire \user_gpio_noesd[0] ;
+ wire \user_gpio_noesd[10] ;
+ wire \user_gpio_noesd[11] ;
+ wire \user_gpio_noesd[12] ;
+ wire \user_gpio_noesd[13] ;
+ wire \user_gpio_noesd[14] ;
+ wire \user_gpio_noesd[15] ;
+ wire \user_gpio_noesd[16] ;
+ wire \user_gpio_noesd[17] ;
+ wire \user_gpio_noesd[1] ;
+ wire \user_gpio_noesd[2] ;
+ wire \user_gpio_noesd[3] ;
+ wire \user_gpio_noesd[4] ;
+ wire \user_gpio_noesd[5] ;
+ wire \user_gpio_noesd[6] ;
+ wire \user_gpio_noesd[7] ;
+ wire \user_gpio_noesd[8] ;
+ wire \user_gpio_noesd[9] ;
+ wire \user_io_in[0] ;
+ wire \user_io_in[10] ;
+ wire \user_io_in[11] ;
+ wire \user_io_in[12] ;
+ wire \user_io_in[13] ;
+ wire \user_io_in[14] ;
+ wire \user_io_in[15] ;
+ wire \user_io_in[16] ;
+ wire \user_io_in[17] ;
+ wire \user_io_in[18] ;
+ wire \user_io_in[19] ;
+ wire \user_io_in[1] ;
+ wire \user_io_in[20] ;
+ wire \user_io_in[21] ;
+ wire \user_io_in[22] ;
+ wire \user_io_in[23] ;
+ wire \user_io_in[24] ;
+ wire \user_io_in[25] ;
+ wire \user_io_in[26] ;
+ wire \user_io_in[2] ;
+ wire \user_io_in[3] ;
+ wire \user_io_in[4] ;
+ wire \user_io_in[5] ;
+ wire \user_io_in[6] ;
+ wire \user_io_in[7] ;
+ wire \user_io_in[8] ;
+ wire \user_io_in[9] ;
+ wire \user_io_in_3v3[0] ;
+ wire \user_io_in_3v3[10] ;
+ wire \user_io_in_3v3[11] ;
+ wire \user_io_in_3v3[12] ;
+ wire \user_io_in_3v3[13] ;
+ wire \user_io_in_3v3[14] ;
+ wire \user_io_in_3v3[15] ;
+ wire \user_io_in_3v3[16] ;
+ wire \user_io_in_3v3[17] ;
+ wire \user_io_in_3v3[18] ;
+ wire \user_io_in_3v3[19] ;
+ wire \user_io_in_3v3[1] ;
+ wire \user_io_in_3v3[20] ;
+ wire \user_io_in_3v3[21] ;
+ wire \user_io_in_3v3[22] ;
+ wire \user_io_in_3v3[23] ;
+ wire \user_io_in_3v3[24] ;
+ wire \user_io_in_3v3[25] ;
+ wire \user_io_in_3v3[26] ;
+ wire \user_io_in_3v3[2] ;
+ wire \user_io_in_3v3[3] ;
+ wire \user_io_in_3v3[4] ;
+ wire \user_io_in_3v3[5] ;
+ wire \user_io_in_3v3[6] ;
+ wire \user_io_in_3v3[7] ;
+ wire \user_io_in_3v3[8] ;
+ wire \user_io_in_3v3[9] ;
+ wire \user_io_oeb[0] ;
+ wire \user_io_oeb[10] ;
+ wire \user_io_oeb[11] ;
+ wire \user_io_oeb[12] ;
+ wire \user_io_oeb[13] ;
+ wire \user_io_oeb[14] ;
+ wire \user_io_oeb[15] ;
+ wire \user_io_oeb[16] ;
+ wire \user_io_oeb[17] ;
+ wire \user_io_oeb[18] ;
+ wire \user_io_oeb[19] ;
+ wire \user_io_oeb[1] ;
+ wire \user_io_oeb[20] ;
+ wire \user_io_oeb[21] ;
+ wire \user_io_oeb[22] ;
+ wire \user_io_oeb[23] ;
+ wire \user_io_oeb[24] ;
+ wire \user_io_oeb[25] ;
+ wire \user_io_oeb[26] ;
+ wire \user_io_oeb[2] ;
+ wire \user_io_oeb[3] ;
+ wire \user_io_oeb[4] ;
+ wire \user_io_oeb[5] ;
+ wire \user_io_oeb[6] ;
+ wire \user_io_oeb[7] ;
+ wire \user_io_oeb[8] ;
+ wire \user_io_oeb[9] ;
+ wire \user_io_out[0] ;
+ wire \user_io_out[10] ;
+ wire \user_io_out[11] ;
+ wire \user_io_out[12] ;
+ wire \user_io_out[13] ;
+ wire \user_io_out[14] ;
+ wire \user_io_out[15] ;
+ wire \user_io_out[16] ;
+ wire \user_io_out[17] ;
+ wire \user_io_out[18] ;
+ wire \user_io_out[19] ;
+ wire \user_io_out[1] ;
+ wire \user_io_out[20] ;
+ wire \user_io_out[21] ;
+ wire \user_io_out[22] ;
+ wire \user_io_out[23] ;
+ wire \user_io_out[24] ;
+ wire \user_io_out[25] ;
+ wire \user_io_out[26] ;
+ wire \user_io_out[2] ;
+ wire \user_io_out[3] ;
+ wire \user_io_out[4] ;
+ wire \user_io_out[5] ;
+ wire \user_io_out[6] ;
+ wire \user_io_out[7] ;
+ wire \user_io_out[8] ;
+ wire \user_io_out[9] ;
+ wire \user_irq[0] ;
+ wire \user_irq[1] ;
+ wire \user_irq[2] ;
+ wire \user_irq_core[0] ;
+ wire \user_irq_core[1] ;
+ wire \user_irq_core[2] ;
+ wire \user_irq_ena[0] ;
+ wire \user_irq_ena[1] ;
+ wire \user_irq_ena[2] ;
+ inout vccd;
+ inout vccd1;
+ wire vccd1_core;
+ inout vccd2;
+ wire vccd2_core;
+ wire vccd_core;
+ inout vdda;
+ inout vdda1;
+ inout vdda1_2;
+ wire vdda1_core;
+ inout vdda2;
+ wire vdda2_core;
+ wire vdda_core;
+ inout vddio;
+ inout vddio_2;
+ wire vddio_core;
+ inout vssa;
+ inout vssa1;
+ inout vssa1_2;
+ wire vssa1_core;
+ inout vssa2;
+ wire vssa2_core;
+ wire vssa_core;
+ inout vssd;
+ inout vssd1;
+ wire vssd1_core;
+ inout vssd2;
+ wire vssd2_core;
+ wire vssd_core;
+ inout vssio;
+ inout vssio_2;
+ wire vssio_core;
+ caravel_clocking \clocking (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .core_clk(caravel_clk),
+ .ext_clk(clock_core),
+ .ext_clk_sel(ext_clk_sel),
+ .ext_reset(ext_reset),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l),
+ .resetb_sync(caravel_rstn),
+ .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .user_clk(caravel_clk2)
+ );
+ gpio_defaults_block_1803 gpio_defaults_block_0 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] })
+ );
+ gpio_defaults_block_1803 gpio_defaults_block_1 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] })
+ );
+ gpio_defaults_block gpio_defaults_block_10 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] })
+ );
+ gpio_defaults_block gpio_defaults_block_11 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] })
+ );
+ gpio_defaults_block gpio_defaults_block_12 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] })
+ );
+ gpio_defaults_block gpio_defaults_block_13 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] })
+ );
+ gpio_defaults_block gpio_defaults_block_14 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_2 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_3 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_4 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] })
+ );
+ gpio_defaults_block gpio_defaults_block_26 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] })
+ );
+ gpio_defaults_block gpio_defaults_block_27 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] })
+ );
+ gpio_defaults_block gpio_defaults_block_28 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] })
+ );
+ gpio_defaults_block gpio_defaults_block_29 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] })
+ );
+ gpio_defaults_block gpio_defaults_block_30 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] })
+ );
+ gpio_defaults_block gpio_defaults_block_31 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] })
+ );
+ gpio_defaults_block gpio_defaults_block_32 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] })
+ );
+ gpio_defaults_block gpio_defaults_block_33 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] })
+ );
+ gpio_defaults_block gpio_defaults_block_34 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] })
+ );
+ gpio_defaults_block gpio_defaults_block_35 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] })
+ );
+ gpio_defaults_block gpio_defaults_block_36 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] })
+ );
+ gpio_defaults_block gpio_defaults_block_37 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] })
+ );
+ gpio_defaults_block gpio_defaults_block_5 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] })
+ );
+ gpio_defaults_block gpio_defaults_block_6 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] })
+ );
+ gpio_defaults_block gpio_defaults_block_7 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] })
+ );
+ gpio_defaults_block gpio_defaults_block_8 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] })
+ );
+ gpio_defaults_block gpio_defaults_block_9 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] })
+ );
+ gpio_control_block \gpio_control_bidir_1[0] (
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] }),
+ .mgmt_gpio_in(\mgmt_io_in[0] ),
+ .mgmt_gpio_oeb(jtag_outenb),
+ .mgmt_gpio_out(jtag_out),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+ .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .pad_gpio_holdover(\mprj_io_holdover[0] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+ .pad_gpio_in(\mprj_io_in[0] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+ .pad_gpio_out(\mprj_io_out[0] ),
+ .pad_gpio_outenb(\mprj_io_oeb[0] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+ .resetn(\gpio_resetn_1_shifted[0] ),
+ .resetn_out(\gpio_resetn_1[0] ),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_clock_out(\gpio_clock_1[0] ),
+ .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_out(\gpio_serial_link_1[0] ),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_load_out(\gpio_load_1[0] ),
+ .user_gpio_in(\user_io_in[0] ),
+ .user_gpio_oeb(\user_io_oeb[0] ),
+ .user_gpio_out(\user_io_out[0] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_1[1] (
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] }),
+ .mgmt_gpio_in(\mgmt_io_in[1] ),
+ .mgmt_gpio_oeb(sdo_outenb),
+ .mgmt_gpio_out(sdo_out),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+ .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] }),
+ .pad_gpio_holdover(\mprj_io_holdover[1] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+ .pad_gpio_in(\mprj_io_in[1] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+ .pad_gpio_out(\mprj_io_out[1] ),
+ .pad_gpio_outenb(\mprj_io_oeb[1] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+ .resetn(\gpio_resetn_1[0] ),
+ .resetn_out(\gpio_resetn_1[1] ),
+ .serial_clock(\gpio_clock_1[0] ),
+ .serial_clock_out(\gpio_clock_1[1] ),
+ .serial_data_in(\gpio_serial_link_1[0] ),
+ .serial_data_out(\gpio_serial_link_1[1] ),
+ .serial_load(\gpio_load_1[0] ),
+ .serial_load_out(\gpio_load_1[1] ),
+ .user_gpio_in(\user_io_in[1] ),
+ .user_gpio_oeb(\user_io_oeb[1] ),
+ .user_gpio_out(\user_io_out[1] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[0] (
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] }),
+ .mgmt_gpio_in(\mgmt_io_in[35] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[2] ),
+ .mgmt_gpio_out(\mgmt_io_out[2] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+ .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] }),
+ .pad_gpio_holdover(\mprj_io_holdover[24] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+ .pad_gpio_in(\mprj_io_in[24] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+ .pad_gpio_out(\mprj_io_out[24] ),
+ .pad_gpio_outenb(\mprj_io_oeb[24] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+ .resetn(\gpio_resetn_2[11] ),
+ .resetn_out(\gpio_resetn_2[10] ),
+ .serial_clock(\gpio_clock_2[11] ),
+ .serial_clock_out(\gpio_clock_2[10] ),
+ .serial_data_in(\gpio_serial_link_2[11] ),
+ .serial_data_out(\gpio_serial_link_2[10] ),
+ .serial_load(\gpio_load_2[11] ),
+ .serial_load_out(\gpio_load_2[10] ),
+ .user_gpio_in(\user_io_in[24] ),
+ .user_gpio_oeb(\user_io_oeb[24] ),
+ .user_gpio_out(\user_io_out[24] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[1] (
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] }),
+ .mgmt_gpio_in(\mgmt_io_in[36] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[3] ),
+ .mgmt_gpio_out(\mgmt_io_out[3] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+ .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] }),
+ .pad_gpio_holdover(\mprj_io_holdover[25] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+ .pad_gpio_in(\mprj_io_in[25] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+ .pad_gpio_out(\mprj_io_out[25] ),
+ .pad_gpio_outenb(\mprj_io_oeb[25] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+ .resetn(\gpio_resetn_2[12] ),
+ .resetn_out(\gpio_resetn_2[11] ),
+ .serial_clock(\gpio_clock_2[12] ),
+ .serial_clock_out(\gpio_clock_2[11] ),
+ .serial_data_in(\gpio_serial_link_2[12] ),
+ .serial_data_out(\gpio_serial_link_2[11] ),
+ .serial_load(\gpio_load_2[12] ),
+ .serial_load_out(\gpio_load_2[11] ),
+ .user_gpio_in(\user_io_in[25] ),
+ .user_gpio_oeb(\user_io_oeb[25] ),
+ .user_gpio_out(\user_io_out[25] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[2] (
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] }),
+ .mgmt_gpio_in(\mgmt_io_in[37] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[4] ),
+ .mgmt_gpio_out(\mgmt_io_out[4] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+ .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] }),
+ .pad_gpio_holdover(\mprj_io_holdover[26] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+ .pad_gpio_in(\mprj_io_in[26] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+ .pad_gpio_out(\mprj_io_out[26] ),
+ .pad_gpio_outenb(\mprj_io_oeb[26] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+ .resetn(\gpio_resetn_2_shifted[12] ),
+ .resetn_out(\gpio_resetn_2[12] ),
+ .serial_clock(\gpio_clock_2_shifted[12] ),
+ .serial_clock_out(\gpio_clock_2[12] ),
+ .serial_data_in(\gpio_serial_link_2_shifted[12] ),
+ .serial_data_out(\gpio_serial_link_2[12] ),
+ .serial_load(\gpio_load_2_shifted[12] ),
+ .serial_load_out(\gpio_load_2[12] ),
+ .user_gpio_in(\user_io_in[26] ),
+ .user_gpio_oeb(\user_io_oeb[26] ),
+ .user_gpio_out(\user_io_out[26] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[0] (
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] }),
+ .mgmt_gpio_in(\mgmt_io_in[8] ),
+ .mgmt_gpio_oeb(\one_loop1[6] ),
+ .mgmt_gpio_out(\mgmt_io_in[8] ),
+ .one(\one_loop1[6] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+ .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] }),
+ .pad_gpio_holdover(\mprj_io_holdover[8] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+ .pad_gpio_in(\mprj_io_in[8] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+ .pad_gpio_out(\mprj_io_out[8] ),
+ .pad_gpio_outenb(\mprj_io_oeb[8] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+ .resetn(\gpio_resetn_1[7] ),
+ .resetn_out(\gpio_resetn_1[8] ),
+ .serial_clock(\gpio_clock_1[7] ),
+ .serial_clock_out(\gpio_clock_1[8] ),
+ .serial_data_in(\gpio_serial_link_1[7] ),
+ .serial_data_out(\gpio_serial_link_1[8] ),
+ .serial_load(\gpio_load_1[7] ),
+ .serial_load_out(\gpio_load_1[8] ),
+ .user_gpio_in(\user_io_in[8] ),
+ .user_gpio_oeb(\user_io_oeb[8] ),
+ .user_gpio_out(\user_io_out[8] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[1] (
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] }),
+ .mgmt_gpio_in(\mgmt_io_in[9] ),
+ .mgmt_gpio_oeb(\one_loop1[7] ),
+ .mgmt_gpio_out(\mgmt_io_in[9] ),
+ .one(\one_loop1[7] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+ .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] }),
+ .pad_gpio_holdover(\mprj_io_holdover[9] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+ .pad_gpio_in(\mprj_io_in[9] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+ .pad_gpio_out(\mprj_io_out[9] ),
+ .pad_gpio_outenb(\mprj_io_oeb[9] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+ .resetn(\gpio_resetn_1[8] ),
+ .resetn_out(\gpio_resetn_1[9] ),
+ .serial_clock(\gpio_clock_1[8] ),
+ .serial_clock_out(\gpio_clock_1[9] ),
+ .serial_data_in(\gpio_serial_link_1[8] ),
+ .serial_data_out(\gpio_serial_link_1[9] ),
+ .serial_load(\gpio_load_1[8] ),
+ .serial_load_out(\gpio_load_1[9] ),
+ .user_gpio_in(\user_io_in[9] ),
+ .user_gpio_oeb(\user_io_oeb[9] ),
+ .user_gpio_out(\user_io_out[9] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[2] (
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] }),
+ .mgmt_gpio_in(\mgmt_io_in[10] ),
+ .mgmt_gpio_oeb(\one_loop1[8] ),
+ .mgmt_gpio_out(\mgmt_io_in[10] ),
+ .one(\one_loop1[8] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+ .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] }),
+ .pad_gpio_holdover(\mprj_io_holdover[10] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+ .pad_gpio_in(\mprj_io_in[10] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+ .pad_gpio_out(\mprj_io_out[10] ),
+ .pad_gpio_outenb(\mprj_io_oeb[10] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+ .resetn(\gpio_resetn_1[9] ),
+ .resetn_out(\gpio_resetn_1[10] ),
+ .serial_clock(\gpio_clock_1[9] ),
+ .serial_clock_out(\gpio_clock_1[10] ),
+ .serial_data_in(\gpio_serial_link_1[9] ),
+ .serial_data_out(\gpio_serial_link_1[10] ),
+ .serial_load(\gpio_load_1[9] ),
+ .serial_load_out(\gpio_load_1[10] ),
+ .user_gpio_in(\user_io_in[10] ),
+ .user_gpio_oeb(\user_io_oeb[10] ),
+ .user_gpio_out(\user_io_out[10] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[3] (
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] }),
+ .mgmt_gpio_in(\mgmt_io_in[11] ),
+ .mgmt_gpio_oeb(\one_loop1[9] ),
+ .mgmt_gpio_out(\mgmt_io_in[11] ),
+ .one(\one_loop1[9] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+ .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] }),
+ .pad_gpio_holdover(\mprj_io_holdover[11] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+ .pad_gpio_in(\mprj_io_in[11] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+ .pad_gpio_out(\mprj_io_out[11] ),
+ .pad_gpio_outenb(\mprj_io_oeb[11] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+ .resetn(\gpio_resetn_1[10] ),
+ .resetn_out(\gpio_resetn_1[11] ),
+ .serial_clock(\gpio_clock_1[10] ),
+ .serial_clock_out(\gpio_clock_1[11] ),
+ .serial_data_in(\gpio_serial_link_1[10] ),
+ .serial_data_out(\gpio_serial_link_1[11] ),
+ .serial_load(\gpio_load_1[10] ),
+ .serial_load_out(\gpio_load_1[11] ),
+ .user_gpio_in(\user_io_in[11] ),
+ .user_gpio_oeb(\user_io_oeb[11] ),
+ .user_gpio_out(\user_io_out[11] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[4] (
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] }),
+ .mgmt_gpio_in(\mgmt_io_in[12] ),
+ .mgmt_gpio_oeb(\one_loop1[10] ),
+ .mgmt_gpio_out(\mgmt_io_in[12] ),
+ .one(\one_loop1[10] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+ .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] }),
+ .pad_gpio_holdover(\mprj_io_holdover[12] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+ .pad_gpio_in(\mprj_io_in[12] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+ .pad_gpio_out(\mprj_io_out[12] ),
+ .pad_gpio_outenb(\mprj_io_oeb[12] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+ .resetn(\gpio_resetn_1[11] ),
+ .resetn_out(\gpio_resetn_1[12] ),
+ .serial_clock(\gpio_clock_1[11] ),
+ .serial_clock_out(\gpio_clock_1[12] ),
+ .serial_data_in(\gpio_serial_link_1[11] ),
+ .serial_data_out(\gpio_serial_link_1[12] ),
+ .serial_load(\gpio_load_1[11] ),
+ .serial_load_out(\gpio_load_1[12] ),
+ .user_gpio_in(\user_io_in[12] ),
+ .user_gpio_oeb(\user_io_oeb[12] ),
+ .user_gpio_out(\user_io_out[12] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[5] (
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] }),
+ .mgmt_gpio_in(\mgmt_io_in[13] ),
+ .mgmt_gpio_oeb(\one_loop1[11] ),
+ .mgmt_gpio_out(\mgmt_io_in[13] ),
+ .one(\one_loop1[11] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+ .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] }),
+ .pad_gpio_holdover(\mprj_io_holdover[13] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+ .pad_gpio_in(\mprj_io_in[13] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+ .pad_gpio_out(\mprj_io_out[13] ),
+ .pad_gpio_outenb(\mprj_io_oeb[13] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+ .resetn(\gpio_resetn_1[12] ),
+ .resetn_out(\gpio_resetn_1[13] ),
+ .serial_clock(\gpio_clock_1[12] ),
+ .serial_clock_out(\gpio_clock_1[13] ),
+ .serial_data_in(\gpio_serial_link_1[12] ),
+ .serial_data_out(\gpio_serial_link_1[13] ),
+ .serial_load(\gpio_load_1[12] ),
+ .serial_load_out(\gpio_load_1[13] ),
+ .user_gpio_in(\user_io_in[13] ),
+ .user_gpio_oeb(\user_io_oeb[13] ),
+ .user_gpio_out(\user_io_out[13] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[0] (
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] }),
+ .mgmt_gpio_in(\mgmt_io_in[2] ),
+ .mgmt_gpio_oeb(\one_loop1[0] ),
+ .mgmt_gpio_out(\mgmt_io_in[2] ),
+ .one(\one_loop1[0] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+ .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] }),
+ .pad_gpio_holdover(\mprj_io_holdover[2] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+ .pad_gpio_in(\mprj_io_in[2] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+ .pad_gpio_out(\mprj_io_out[2] ),
+ .pad_gpio_outenb(\mprj_io_oeb[2] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+ .resetn(\gpio_resetn_1[1] ),
+ .resetn_out(\gpio_resetn_1[2] ),
+ .serial_clock(\gpio_clock_1[1] ),
+ .serial_clock_out(\gpio_clock_1[2] ),
+ .serial_data_in(\gpio_serial_link_1[1] ),
+ .serial_data_out(\gpio_serial_link_1[2] ),
+ .serial_load(\gpio_load_1[1] ),
+ .serial_load_out(\gpio_load_1[2] ),
+ .user_gpio_in(\user_io_in[2] ),
+ .user_gpio_oeb(\user_io_oeb[2] ),
+ .user_gpio_out(\user_io_out[2] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[1] (
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] }),
+ .mgmt_gpio_in(\mgmt_io_in[3] ),
+ .mgmt_gpio_oeb(\one_loop1[1] ),
+ .mgmt_gpio_out(\mgmt_io_in[3] ),
+ .one(\one_loop1[1] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+ .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] }),
+ .pad_gpio_holdover(\mprj_io_holdover[3] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+ .pad_gpio_in(\mprj_io_in[3] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+ .pad_gpio_out(\mprj_io_out[3] ),
+ .pad_gpio_outenb(\mprj_io_oeb[3] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+ .resetn(\gpio_resetn_1[2] ),
+ .resetn_out(\gpio_resetn_1[3] ),
+ .serial_clock(\gpio_clock_1[2] ),
+ .serial_clock_out(\gpio_clock_1[3] ),
+ .serial_data_in(\gpio_serial_link_1[2] ),
+ .serial_data_out(\gpio_serial_link_1[3] ),
+ .serial_load(\gpio_load_1[2] ),
+ .serial_load_out(\gpio_load_1[3] ),
+ .user_gpio_in(\user_io_in[3] ),
+ .user_gpio_oeb(\user_io_oeb[3] ),
+ .user_gpio_out(\user_io_out[3] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[2] (
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] }),
+ .mgmt_gpio_in(\mgmt_io_in[4] ),
+ .mgmt_gpio_oeb(\one_loop1[2] ),
+ .mgmt_gpio_out(\mgmt_io_in[4] ),
+ .one(\one_loop1[2] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+ .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] }),
+ .pad_gpio_holdover(\mprj_io_holdover[4] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+ .pad_gpio_in(\mprj_io_in[4] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+ .pad_gpio_out(\mprj_io_out[4] ),
+ .pad_gpio_outenb(\mprj_io_oeb[4] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+ .resetn(\gpio_resetn_1[3] ),
+ .resetn_out(\gpio_resetn_1[4] ),
+ .serial_clock(\gpio_clock_1[3] ),
+ .serial_clock_out(\gpio_clock_1[4] ),
+ .serial_data_in(\gpio_serial_link_1[3] ),
+ .serial_data_out(\gpio_serial_link_1[4] ),
+ .serial_load(\gpio_load_1[3] ),
+ .serial_load_out(\gpio_load_1[4] ),
+ .user_gpio_in(\user_io_in[4] ),
+ .user_gpio_oeb(\user_io_oeb[4] ),
+ .user_gpio_out(\user_io_out[4] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[3] (
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] }),
+ .mgmt_gpio_in(\mgmt_io_in[5] ),
+ .mgmt_gpio_oeb(\one_loop1[3] ),
+ .mgmt_gpio_out(\mgmt_io_in[5] ),
+ .one(\one_loop1[3] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+ .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] }),
+ .pad_gpio_holdover(\mprj_io_holdover[5] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+ .pad_gpio_in(\mprj_io_in[5] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+ .pad_gpio_out(\mprj_io_out[5] ),
+ .pad_gpio_outenb(\mprj_io_oeb[5] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+ .resetn(\gpio_resetn_1[4] ),
+ .resetn_out(\gpio_resetn_1[5] ),
+ .serial_clock(\gpio_clock_1[4] ),
+ .serial_clock_out(\gpio_clock_1[5] ),
+ .serial_data_in(\gpio_serial_link_1[4] ),
+ .serial_data_out(\gpio_serial_link_1[5] ),
+ .serial_load(\gpio_load_1[4] ),
+ .serial_load_out(\gpio_load_1[5] ),
+ .user_gpio_in(\user_io_in[5] ),
+ .user_gpio_oeb(\user_io_oeb[5] ),
+ .user_gpio_out(\user_io_out[5] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[4] (
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] }),
+ .mgmt_gpio_in(\mgmt_io_in[6] ),
+ .mgmt_gpio_oeb(\one_loop1[4] ),
+ .mgmt_gpio_out(\mgmt_io_in[6] ),
+ .one(\one_loop1[4] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+ .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] }),
+ .pad_gpio_holdover(\mprj_io_holdover[6] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+ .pad_gpio_in(\mprj_io_in[6] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+ .pad_gpio_out(\mprj_io_out[6] ),
+ .pad_gpio_outenb(\mprj_io_oeb[6] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+ .resetn(\gpio_resetn_1[5] ),
+ .resetn_out(\gpio_resetn_1[6] ),
+ .serial_clock(\gpio_clock_1[5] ),
+ .serial_clock_out(\gpio_clock_1[6] ),
+ .serial_data_in(\gpio_serial_link_1[5] ),
+ .serial_data_out(\gpio_serial_link_1[6] ),
+ .serial_load(\gpio_load_1[5] ),
+ .serial_load_out(\gpio_load_1[6] ),
+ .user_gpio_in(\user_io_in[6] ),
+ .user_gpio_oeb(\user_io_oeb[6] ),
+ .user_gpio_out(\user_io_out[6] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[5] (
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] }),
+ .mgmt_gpio_in(\mgmt_io_in[7] ),
+ .mgmt_gpio_oeb(\one_loop1[5] ),
+ .mgmt_gpio_out(\mgmt_io_in[7] ),
+ .one(\one_loop1[5] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+ .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] }),
+ .pad_gpio_holdover(\mprj_io_holdover[7] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+ .pad_gpio_in(\mprj_io_in[7] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+ .pad_gpio_out(\mprj_io_out[7] ),
+ .pad_gpio_outenb(\mprj_io_oeb[7] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+ .resetn(\gpio_resetn_1[6] ),
+ .resetn_out(\gpio_resetn_1[7] ),
+ .serial_clock(\gpio_clock_1[6] ),
+ .serial_clock_out(\gpio_clock_1[7] ),
+ .serial_data_in(\gpio_serial_link_1[6] ),
+ .serial_data_out(\gpio_serial_link_1[7] ),
+ .serial_load(\gpio_load_1[6] ),
+ .serial_load_out(\gpio_load_1[7] ),
+ .user_gpio_in(\user_io_in[7] ),
+ .user_gpio_oeb(\user_io_oeb[7] ),
+ .user_gpio_out(\user_io_out[7] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[0] (
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] }),
+ .mgmt_gpio_in(\mgmt_io_in[25] ),
+ .mgmt_gpio_oeb(\one_loop2[0] ),
+ .mgmt_gpio_out(\mgmt_io_in[25] ),
+ .one(\one_loop2[0] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+ .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] }),
+ .pad_gpio_holdover(\mprj_io_holdover[14] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+ .pad_gpio_in(\mprj_io_in[14] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+ .pad_gpio_out(\mprj_io_out[14] ),
+ .pad_gpio_outenb(\mprj_io_oeb[14] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+ .resetn(\gpio_resetn_2[1] ),
+ .resetn_out(\gpio_resetn_2[0] ),
+ .serial_clock(\gpio_clock_2[1] ),
+ .serial_clock_out(\gpio_clock_2[0] ),
+ .serial_data_in(\gpio_serial_link_2[1] ),
+ .serial_data_out(\gpio_serial_link_2[0] ),
+ .serial_load(\gpio_load_2[1] ),
+ .serial_load_out(\gpio_load_2[0] ),
+ .user_gpio_in(\user_io_in[14] ),
+ .user_gpio_oeb(\user_io_oeb[14] ),
+ .user_gpio_out(\user_io_out[14] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[1] (
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] }),
+ .mgmt_gpio_in(\mgmt_io_in[26] ),
+ .mgmt_gpio_oeb(\one_loop2[1] ),
+ .mgmt_gpio_out(\mgmt_io_in[26] ),
+ .one(\one_loop2[1] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+ .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] }),
+ .pad_gpio_holdover(\mprj_io_holdover[15] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+ .pad_gpio_in(\mprj_io_in[15] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+ .pad_gpio_out(\mprj_io_out[15] ),
+ .pad_gpio_outenb(\mprj_io_oeb[15] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+ .resetn(\gpio_resetn_2[2] ),
+ .resetn_out(\gpio_resetn_2[1] ),
+ .serial_clock(\gpio_clock_2[2] ),
+ .serial_clock_out(\gpio_clock_2[1] ),
+ .serial_data_in(\gpio_serial_link_2[2] ),
+ .serial_data_out(\gpio_serial_link_2[1] ),
+ .serial_load(\gpio_load_2[2] ),
+ .serial_load_out(\gpio_load_2[1] ),
+ .user_gpio_in(\user_io_in[15] ),
+ .user_gpio_oeb(\user_io_oeb[15] ),
+ .user_gpio_out(\user_io_out[15] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[2] (
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] }),
+ .mgmt_gpio_in(\mgmt_io_in[27] ),
+ .mgmt_gpio_oeb(\one_loop2[2] ),
+ .mgmt_gpio_out(\mgmt_io_in[27] ),
+ .one(\one_loop2[2] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+ .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] }),
+ .pad_gpio_holdover(\mprj_io_holdover[16] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+ .pad_gpio_in(\mprj_io_in[16] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+ .pad_gpio_out(\mprj_io_out[16] ),
+ .pad_gpio_outenb(\mprj_io_oeb[16] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+ .resetn(\gpio_resetn_2[3] ),
+ .resetn_out(\gpio_resetn_2[2] ),
+ .serial_clock(\gpio_clock_2[3] ),
+ .serial_clock_out(\gpio_clock_2[2] ),
+ .serial_data_in(\gpio_serial_link_2[3] ),
+ .serial_data_out(\gpio_serial_link_2[2] ),
+ .serial_load(\gpio_load_2[3] ),
+ .serial_load_out(\gpio_load_2[2] ),
+ .user_gpio_in(\user_io_in[16] ),
+ .user_gpio_oeb(\user_io_oeb[16] ),
+ .user_gpio_out(\user_io_out[16] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[3] (
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] }),
+ .mgmt_gpio_in(\mgmt_io_in[28] ),
+ .mgmt_gpio_oeb(\one_loop2[3] ),
+ .mgmt_gpio_out(\mgmt_io_in[28] ),
+ .one(\one_loop2[3] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+ .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] }),
+ .pad_gpio_holdover(\mprj_io_holdover[17] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+ .pad_gpio_in(\mprj_io_in[17] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+ .pad_gpio_out(\mprj_io_out[17] ),
+ .pad_gpio_outenb(\mprj_io_oeb[17] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+ .resetn(\gpio_resetn_2[4] ),
+ .resetn_out(\gpio_resetn_2[3] ),
+ .serial_clock(\gpio_clock_2[4] ),
+ .serial_clock_out(\gpio_clock_2[3] ),
+ .serial_data_in(\gpio_serial_link_2[4] ),
+ .serial_data_out(\gpio_serial_link_2[3] ),
+ .serial_load(\gpio_load_2[4] ),
+ .serial_load_out(\gpio_load_2[3] ),
+ .user_gpio_in(\user_io_in[17] ),
+ .user_gpio_oeb(\user_io_oeb[17] ),
+ .user_gpio_out(\user_io_out[17] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[4] (
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] }),
+ .mgmt_gpio_in(\mgmt_io_in[29] ),
+ .mgmt_gpio_oeb(\one_loop2[4] ),
+ .mgmt_gpio_out(\mgmt_io_in[29] ),
+ .one(\one_loop2[4] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+ .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] }),
+ .pad_gpio_holdover(\mprj_io_holdover[18] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+ .pad_gpio_in(\mprj_io_in[18] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+ .pad_gpio_out(\mprj_io_out[18] ),
+ .pad_gpio_outenb(\mprj_io_oeb[18] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+ .resetn(\gpio_resetn_2[5] ),
+ .resetn_out(\gpio_resetn_2[4] ),
+ .serial_clock(\gpio_clock_2[5] ),
+ .serial_clock_out(\gpio_clock_2[4] ),
+ .serial_data_in(\gpio_serial_link_2[5] ),
+ .serial_data_out(\gpio_serial_link_2[4] ),
+ .serial_load(\gpio_load_2[5] ),
+ .serial_load_out(\gpio_load_2[4] ),
+ .user_gpio_in(\user_io_in[18] ),
+ .user_gpio_oeb(\user_io_oeb[18] ),
+ .user_gpio_out(\user_io_out[18] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[5] (
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] }),
+ .mgmt_gpio_in(\mgmt_io_in[30] ),
+ .mgmt_gpio_oeb(\one_loop2[5] ),
+ .mgmt_gpio_out(\mgmt_io_in[30] ),
+ .one(\one_loop2[5] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+ .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] }),
+ .pad_gpio_holdover(\mprj_io_holdover[19] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+ .pad_gpio_in(\mprj_io_in[19] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+ .pad_gpio_out(\mprj_io_out[19] ),
+ .pad_gpio_outenb(\mprj_io_oeb[19] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+ .resetn(\gpio_resetn_2[6] ),
+ .resetn_out(\gpio_resetn_2[5] ),
+ .serial_clock(\gpio_clock_2[6] ),
+ .serial_clock_out(\gpio_clock_2[5] ),
+ .serial_data_in(\gpio_serial_link_2[6] ),
+ .serial_data_out(\gpio_serial_link_2[5] ),
+ .serial_load(\gpio_load_2[6] ),
+ .serial_load_out(\gpio_load_2[5] ),
+ .user_gpio_in(\user_io_in[19] ),
+ .user_gpio_oeb(\user_io_oeb[19] ),
+ .user_gpio_out(\user_io_out[19] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[6] (
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] }),
+ .mgmt_gpio_in(\mgmt_io_in[31] ),
+ .mgmt_gpio_oeb(\one_loop2[6] ),
+ .mgmt_gpio_out(\mgmt_io_in[31] ),
+ .one(\one_loop2[6] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+ .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] }),
+ .pad_gpio_holdover(\mprj_io_holdover[20] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+ .pad_gpio_in(\mprj_io_in[20] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+ .pad_gpio_out(\mprj_io_out[20] ),
+ .pad_gpio_outenb(\mprj_io_oeb[20] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+ .resetn(\gpio_resetn_2[7] ),
+ .resetn_out(\gpio_resetn_2[6] ),
+ .serial_clock(\gpio_clock_2[7] ),
+ .serial_clock_out(\gpio_clock_2[6] ),
+ .serial_data_in(\gpio_serial_link_2[7] ),
+ .serial_data_out(\gpio_serial_link_2[6] ),
+ .serial_load(\gpio_load_2[7] ),
+ .serial_load_out(\gpio_load_2[6] ),
+ .user_gpio_in(\user_io_in[20] ),
+ .user_gpio_oeb(\user_io_oeb[20] ),
+ .user_gpio_out(\user_io_out[20] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[7] (
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] }),
+ .mgmt_gpio_in(\mgmt_io_in[32] ),
+ .mgmt_gpio_oeb(\one_loop2[7] ),
+ .mgmt_gpio_out(\mgmt_io_in[32] ),
+ .one(\one_loop2[7] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+ .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] }),
+ .pad_gpio_holdover(\mprj_io_holdover[21] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+ .pad_gpio_in(\mprj_io_in[21] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+ .pad_gpio_out(\mprj_io_out[21] ),
+ .pad_gpio_outenb(\mprj_io_oeb[21] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+ .resetn(\gpio_resetn_2[8] ),
+ .resetn_out(\gpio_resetn_2[7] ),
+ .serial_clock(\gpio_clock_2[8] ),
+ .serial_clock_out(\gpio_clock_2[7] ),
+ .serial_data_in(\gpio_serial_link_2[8] ),
+ .serial_data_out(\gpio_serial_link_2[7] ),
+ .serial_load(\gpio_load_2[8] ),
+ .serial_load_out(\gpio_load_2[7] ),
+ .user_gpio_in(\user_io_in[21] ),
+ .user_gpio_oeb(\user_io_oeb[21] ),
+ .user_gpio_out(\user_io_out[21] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[8] (
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] }),
+ .mgmt_gpio_in(\mgmt_io_in[33] ),
+ .mgmt_gpio_oeb(\one_loop2[8] ),
+ .mgmt_gpio_out(\mgmt_io_in[33] ),
+ .one(\one_loop2[8] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+ .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] }),
+ .pad_gpio_holdover(\mprj_io_holdover[22] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+ .pad_gpio_in(\mprj_io_in[22] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+ .pad_gpio_out(\mprj_io_out[22] ),
+ .pad_gpio_outenb(\mprj_io_oeb[22] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+ .resetn(\gpio_resetn_2[9] ),
+ .resetn_out(\gpio_resetn_2[8] ),
+ .serial_clock(\gpio_clock_2[9] ),
+ .serial_clock_out(\gpio_clock_2[8] ),
+ .serial_data_in(\gpio_serial_link_2[9] ),
+ .serial_data_out(\gpio_serial_link_2[8] ),
+ .serial_load(\gpio_load_2[9] ),
+ .serial_load_out(\gpio_load_2[8] ),
+ .user_gpio_in(\user_io_in[22] ),
+ .user_gpio_oeb(\user_io_oeb[22] ),
+ .user_gpio_out(\user_io_out[22] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[9] (
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] }),
+ .mgmt_gpio_in(\mgmt_io_in[34] ),
+ .mgmt_gpio_oeb(\one_loop2[9] ),
+ .mgmt_gpio_out(\mgmt_io_in[34] ),
+ .one(\one_loop2[9] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+ .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] }),
+ .pad_gpio_holdover(\mprj_io_holdover[23] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+ .pad_gpio_in(\mprj_io_in[23] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+ .pad_gpio_out(\mprj_io_out[23] ),
+ .pad_gpio_outenb(\mprj_io_oeb[23] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+ .resetn(\gpio_resetn_2[10] ),
+ .resetn_out(\gpio_resetn_2[9] ),
+ .serial_clock(\gpio_clock_2[10] ),
+ .serial_clock_out(\gpio_clock_2[9] ),
+ .serial_data_in(\gpio_serial_link_2[10] ),
+ .serial_data_out(\gpio_serial_link_2[9] ),
+ .serial_load(\gpio_load_2[10] ),
+ .serial_load_out(\gpio_load_2[9] ),
+ .user_gpio_in(\user_io_in[23] ),
+ .user_gpio_oeb(\user_io_oeb[23] ),
+ .user_gpio_out(\user_io_out[23] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ housekeeping housekeeping (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] }),
+ .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] }),
+ .mgmt_gpio_in({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0] }),
+ .mgmt_gpio_oeb({ \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_nc[32] , \mgmt_io_nc[31] , \mgmt_io_nc[30] , \mgmt_io_nc[29] , \mgmt_io_nc[28] , \mgmt_io_nc[27] , \mgmt_io_nc[26] , \mgmt_io_nc[25] , \mgmt_io_nc[24] , \mgmt_io_nc[23] , \mgmt_io_nc[22] , \mgmt_io_nc[21] , \mgmt_io_nc[20] , \mgmt_io_nc[19] , \mgmt_io_nc[18] , \mgmt_io_nc[17] , \mgmt_io_nc[16] , \mgmt_io_nc[15] , \mgmt_io_nc[14] , \mgmt_io_nc[13] , \mgmt_io_nc[12] , \mgmt_io_nc[11] , \mgmt_io_nc[10] , \mgmt_io_nc[9] , \mgmt_io_nc[8] , \mgmt_io_nc[7] , \mgmt_io_nc[6] , \mgmt_io_nc[5] , \mgmt_io_nc[4] , \mgmt_io_nc[3] , \mgmt_io_nc[2] , \mgmt_io_nc[1] , \mgmt_io_nc[0] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0] }),
+ .mgmt_gpio_out({ \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_out[1] , \mgmt_io_out[0] }),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_di(flash_io1_di),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .pll_bypass(ext_clk_sel),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .pll_ena(spi_pll_ena),
+ .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .porb(porb_l),
+ .pwr_ctrl_out({ \pwr_ctrl_nc[3] , \pwr_ctrl_nc[2] , \pwr_ctrl_nc[1] , \pwr_ctrl_nc[0] }),
+ .qspi_enabled(qspi_enabled),
+ .reset(ext_reset),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_2(\gpio_serial_link_2_shifted[12] ),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_resetn(\gpio_resetn_1_shifted[0] ),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0] }),
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
+ .trap(trap),
+ .uart_enabled(uart_enabled),
+ .user_clock(caravel_clk2),
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+ .wb_ack_o(hk_ack_i),
+ .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .wb_clk_i(caravel_clk),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .wb_rstn_i(caravel_rstn),
+ .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .wb_stb_i(hk_stb_o),
+ .wb_we_i(mprj_we_o_core)
+ );
+ mgmt_protect mgmt_buffers (
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_we_o_user(mprj_we_o_user),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood),
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] }),
+ .user_reset(mprj_reset),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core)
+ );
+ user_analog_project_wrapper mprj (
+ .gpio_analog({ \user_gpio_analog[17] , \user_gpio_analog[16] , \user_gpio_analog[15] , \user_gpio_analog[14] , \user_gpio_analog[13] , \user_gpio_analog[12] , \user_gpio_analog[11] , \user_gpio_analog[10] , \user_gpio_analog[9] , \user_gpio_analog[8] , \user_gpio_analog[7] , \user_gpio_analog[6] , \user_gpio_analog[5] , \user_gpio_analog[4] , \user_gpio_analog[3] , \user_gpio_analog[2] , \user_gpio_analog[1] , \user_gpio_analog[0] }),
+ .gpio_noesd({ \user_gpio_noesd[17] , \user_gpio_noesd[16] , \user_gpio_noesd[15] , \user_gpio_noesd[14] , \user_gpio_noesd[13] , \user_gpio_noesd[12] , \user_gpio_noesd[11] , \user_gpio_noesd[10] , \user_gpio_noesd[9] , \user_gpio_noesd[8] , \user_gpio_noesd[7] , \user_gpio_noesd[6] , \user_gpio_noesd[5] , \user_gpio_noesd[4] , \user_gpio_noesd[3] , \user_gpio_noesd[2] , \user_gpio_noesd[1] , \user_gpio_noesd[0] }),
+ .io_analog({ \user_analog[10] , \user_analog[9] , \user_analog[8] , \user_analog[7] , \user_analog[6] , \user_analog[5] , \user_analog[4] , \user_analog[3] , \user_analog[2] , \user_analog[1] , \user_analog[0] }),
+ .io_clamp_high({ \user_clamp_high[2] , \user_clamp_high[1] , \user_clamp_high[0] }),
+ .io_clamp_low({ \user_clamp_low[2] , \user_clamp_low[1] , \user_clamp_low[0] }),
+ .io_in({ \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0] }),
+ .io_in_3v3({ \mprj_io_in_3v3[26] , \mprj_io_in_3v3[25] , \mprj_io_in_3v3[24] , \mprj_io_in_3v3[23] , \mprj_io_in_3v3[22] , \mprj_io_in_3v3[21] , \mprj_io_in_3v3[20] , \mprj_io_in_3v3[19] , \mprj_io_in_3v3[18] , \mprj_io_in_3v3[17] , \mprj_io_in_3v3[16] , \mprj_io_in_3v3[15] , \mprj_io_in_3v3[14] , \mprj_io_in_3v3[13] , \mprj_io_in_3v3[12] , \mprj_io_in_3v3[11] , \mprj_io_in_3v3[10] , \mprj_io_in_3v3[9] , \mprj_io_in_3v3[8] , \mprj_io_in_3v3[7] , \mprj_io_in_3v3[6] , \mprj_io_in_3v3[5] , \mprj_io_in_3v3[4] , \mprj_io_in_3v3[3] , \mprj_io_in_3v3[2] , \mprj_io_in_3v3[1] , \mprj_io_in_3v3[0] }),
+ .io_oeb({ \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0] }),
+ .io_out({ \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0] }),
+ .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core),
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user)
+ );
+ chip_io_alt padframe (
+ .clock(clock),
+ .clock_core(clock_core),
+ .flash_clk(flash_clk),
+ .flash_clk_core(flash_clk_frame),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_csb(flash_csb),
+ .flash_csb_core(flash_csb_frame),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_io0(flash_io0),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1(flash_io1),
+ .flash_io1_di_core(flash_io1_di),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .gpio(gpio),
+ .gpio_in_core(gpio_in_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .mprj_analog({ \user_analog[10] , \user_analog[9] , \user_analog[8] , \user_analog[7] , \user_analog[6] , \user_analog[5] , \user_analog[4] , \user_analog[3] , \user_analog[2] , \user_analog[1] , \user_analog[0] }),
+ .mprj_clamp_high({ \user_clamp_high[2] , \user_clamp_high[1] , \user_clamp_high[0] }),
+ .mprj_clamp_low({ \user_clamp_low[2] , \user_clamp_low[1] , \user_clamp_low[0] }),
+ .mprj_gpio_analog({ \user_gpio_analog[17] , \user_gpio_analog[16] , \user_gpio_analog[15] , \user_gpio_analog[14] , \user_gpio_analog[13] , \user_gpio_analog[12] , \user_gpio_analog[11] , \user_gpio_analog[10] , \user_gpio_analog[9] , \user_gpio_analog[8] , \user_gpio_analog[7] , \user_gpio_analog[6] , \user_gpio_analog[5] , \user_gpio_analog[4] , \user_gpio_analog[3] , \user_gpio_analog[2] , \user_gpio_analog[1] , \user_gpio_analog[0] }),
+ .mprj_gpio_noesd({ \user_gpio_noesd[17] , \user_gpio_noesd[16] , \user_gpio_noesd[15] , \user_gpio_noesd[14] , \user_gpio_noesd[13] , \user_gpio_noesd[12] , \user_gpio_noesd[11] , \user_gpio_noesd[10] , \user_gpio_noesd[9] , \user_gpio_noesd[8] , \user_gpio_noesd[7] , \user_gpio_noesd[6] , \user_gpio_noesd[5] , \user_gpio_noesd[4] , \user_gpio_noesd[3] , \user_gpio_noesd[2] , \user_gpio_noesd[1] , \user_gpio_noesd[0] }),
+ .mprj_io(mprj_io),
+ .mprj_io_analog_en({ \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0] }),
+ .mprj_io_analog_pol({ \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0] }),
+ .mprj_io_analog_sel({ \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0] }),
+ .mprj_io_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .mprj_io_holdover({ \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0] }),
+ .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0] }),
+ .mprj_io_in({ \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0] }),
+ .mprj_io_in_3v3({ \mprj_io_in_3v3[26] , \mprj_io_in_3v3[25] , \mprj_io_in_3v3[24] , \mprj_io_in_3v3[23] , \mprj_io_in_3v3[22] , \mprj_io_in_3v3[21] , \mprj_io_in_3v3[20] , \mprj_io_in_3v3[19] , \mprj_io_in_3v3[18] , \mprj_io_in_3v3[17] , \mprj_io_in_3v3[16] , \mprj_io_in_3v3[15] , \mprj_io_in_3v3[14] , \mprj_io_in_3v3[13] , \mprj_io_in_3v3[12] , \mprj_io_in_3v3[11] , \mprj_io_in_3v3[10] , \mprj_io_in_3v3[9] , \mprj_io_in_3v3[8] , \mprj_io_in_3v3[7] , \mprj_io_in_3v3[6] , \mprj_io_in_3v3[5] , \mprj_io_in_3v3[4] , \mprj_io_in_3v3[3] , \mprj_io_in_3v3[2] , \mprj_io_in_3v3[1] , \mprj_io_in_3v3[0] }),
+ .mprj_io_inp_dis({ \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0] }),
+ .mprj_io_oeb({ \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0] }),
+ .mprj_io_out({ \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0] }),
+ .mprj_io_slow_sel({ \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0] }),
+ .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0] }),
+ .por(por_l),
+ .porb_h(porb_h),
+ .resetb(resetb),
+ .resetb_core_h(rstb_h),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd1_pad(vccd1),
+ .vccd2(vccd2_core),
+ .vccd2_pad(vccd2),
+ .vccd_pad(vccd),
+ .vdda(vdda_core),
+ .vdda1(vdda1_core),
+ .vdda1_pad(vdda1),
+ .vdda1_pad2(vdda1_2),
+ .vdda2(vdda2_core),
+ .vdda2_pad(vdda2),
+ .vdda_pad(vdda),
+ .vddio(vddio_core),
+ .vddio_pad(vddio),
+ .vddio_pad2(vddio_2),
+ .vssa(vssa_core),
+ .vssa1(vssa1_core),
+ .vssa1_pad(vssa1),
+ .vssa1_pad2(vssa1_2),
+ .vssa2(vssa2_core),
+ .vssa2_pad(vssa2),
+ .vssa_pad(vssa),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd1_pad(vssd1),
+ .vssd2(vssd2_core),
+ .vssd2_pad(vssd2),
+ .vssd_pad(vssd),
+ .vssio(vssio_core),
+ .vssio_pad(vssio),
+ .vssio_pad2(vssio_2)
+ );
+ digital_pll pll (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .clockp({ pll_clk, pll_clk90 }),
+ .dco(spi_pll_dco_ena),
+ .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .enable(spi_pll_ena),
+ .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .osc(clock_core),
+ .resetb(rstb_l)
+ );
+ simple_por por (
+ .por_l(por_l),
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .vdd1v8(vccd_core),
+ .vdd3v3(vddio_core),
+ .vss3v3(vssio_core),
+ .vss1v8(vssd_core)
+ );
+ xres_buf rstb_level (
+ .A(rstb_h),
+ .LVGND(vssd_core),
+ .LVPWR(vccd_core),
+ .VGND(vssio_core),
+ .VPWR(vddio_core),
+ .X(rstb_l)
+ );
+ mgmt_core_wrapper soc (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .flash_clk(flash_clk_core),
+ .flash_csb(flash_csb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_out_pad(gpio_out_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .hk_ack_i(hk_ack_i),
+ .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .hk_stb_o(hk_stb_o),
+ .hk_cyc_o(hk_cyc_o),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .qspi_enabled(qspi_enabled),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0] }),
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
+ .trap(trap),
+ .uart_enabled(uart_enabled)
+ );
+ user_id_programming user_id_value (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] })
+ );
+ spare_logic_block \spare_logic[0] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[1] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[2] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[3] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+
+ assign \gpio_resetn_1_shifted[13] = \gpio_resetn_1[12] ;
+ assign \gpio_resetn_1_shifted[12] = \gpio_resetn_1[11] ;
+ assign \gpio_resetn_1_shifted[11] = \gpio_resetn_1[10] ;
+ assign \gpio_resetn_1_shifted[10] = \gpio_resetn_1[9] ;
+ assign \gpio_resetn_1_shifted[9] = \gpio_resetn_1[8] ;
+ assign \gpio_resetn_1_shifted[8] = \gpio_resetn_1[7] ;
+ assign \gpio_resetn_1_shifted[7] = \gpio_resetn_1[6] ;
+ assign \gpio_resetn_1_shifted[6] = \gpio_resetn_1[5] ;
+ assign \gpio_resetn_1_shifted[5] = \gpio_resetn_1[4] ;
+ assign \gpio_resetn_1_shifted[4] = \gpio_resetn_1[3] ;
+ assign \gpio_resetn_1_shifted[3] = \gpio_resetn_1[2] ;
+ assign \gpio_resetn_1_shifted[2] = \gpio_resetn_1[1] ;
+ assign \gpio_resetn_1_shifted[1] = \gpio_resetn_1[0] ;
+ assign \gpio_clock_2_shifted[12] = \gpio_clock_1_shifted[0] ;
+ assign \gpio_clock_2_shifted[11] = \gpio_clock_2[12] ;
+ assign \gpio_clock_2_shifted[10] = \gpio_clock_2[11] ;
+ assign \gpio_clock_2_shifted[9] = \gpio_clock_2[10] ;
+ assign \gpio_clock_2_shifted[8] = \gpio_clock_2[9] ;
+ assign \gpio_clock_2_shifted[7] = \gpio_clock_2[8] ;
+ assign \gpio_clock_2_shifted[6] = \gpio_clock_2[7] ;
+ assign \gpio_clock_2_shifted[5] = \gpio_clock_2[6] ;
+ assign \gpio_clock_2_shifted[4] = \gpio_clock_2[5] ;
+ assign \gpio_clock_2_shifted[3] = \gpio_clock_2[4] ;
+ assign \gpio_clock_2_shifted[2] = \gpio_clock_2[3] ;
+ assign \gpio_clock_2_shifted[1] = \gpio_clock_2[2] ;
+ assign \gpio_clock_2_shifted[0] = \gpio_clock_2[1] ;
+ assign \gpio_serial_link_2_shifted[11] = \gpio_serial_link_2[12] ;
+ assign \gpio_serial_link_2_shifted[10] = \gpio_serial_link_2[11] ;
+ assign \gpio_serial_link_2_shifted[9] = \gpio_serial_link_2[10] ;
+ assign \gpio_serial_link_2_shifted[8] = \gpio_serial_link_2[9] ;
+ assign \gpio_serial_link_2_shifted[7] = \gpio_serial_link_2[8] ;
+ assign \gpio_serial_link_2_shifted[6] = \gpio_serial_link_2[7] ;
+ assign \gpio_serial_link_2_shifted[5] = \gpio_serial_link_2[6] ;
+ assign \gpio_serial_link_2_shifted[4] = \gpio_serial_link_2[5] ;
+ assign \gpio_serial_link_2_shifted[3] = \gpio_serial_link_2[4] ;
+ assign \gpio_serial_link_2_shifted[2] = \gpio_serial_link_2[3] ;
+ assign \gpio_serial_link_2_shifted[1] = \gpio_serial_link_2[2] ;
+ assign \gpio_serial_link_2_shifted[0] = \gpio_serial_link_2[1] ;
+ assign \gpio_serial_link_1_shifted[13] = \gpio_serial_link_1[12] ;
+ assign \gpio_serial_link_1_shifted[12] = \gpio_serial_link_1[11] ;
+ assign \gpio_serial_link_1_shifted[11] = \gpio_serial_link_1[10] ;
+ assign \gpio_serial_link_1_shifted[10] = \gpio_serial_link_1[9] ;
+ assign \gpio_serial_link_1_shifted[9] = \gpio_serial_link_1[8] ;
+ assign \gpio_serial_link_1_shifted[8] = \gpio_serial_link_1[7] ;
+ assign \gpio_serial_link_1_shifted[7] = \gpio_serial_link_1[6] ;
+ assign \gpio_serial_link_1_shifted[6] = \gpio_serial_link_1[5] ;
+ assign \gpio_serial_link_1_shifted[5] = \gpio_serial_link_1[4] ;
+ assign \gpio_serial_link_1_shifted[4] = \gpio_serial_link_1[3] ;
+ assign \gpio_serial_link_1_shifted[3] = \gpio_serial_link_1[2] ;
+ assign \gpio_serial_link_1_shifted[2] = \gpio_serial_link_1[1] ;
+ assign \gpio_serial_link_1_shifted[1] = \gpio_serial_link_1[0] ;
+ assign \user_io_in_3v3[26] = \mprj_io_in_3v3[26] ;
+ assign \user_io_in_3v3[25] = \mprj_io_in_3v3[25] ;
+ assign \user_io_in_3v3[24] = \mprj_io_in_3v3[24] ;
+ assign \user_io_in_3v3[23] = \mprj_io_in_3v3[23] ;
+ assign \user_io_in_3v3[22] = \mprj_io_in_3v3[22] ;
+ assign \user_io_in_3v3[21] = \mprj_io_in_3v3[21] ;
+ assign \user_io_in_3v3[20] = \mprj_io_in_3v3[20] ;
+ assign \user_io_in_3v3[19] = \mprj_io_in_3v3[19] ;
+ assign \user_io_in_3v3[18] = \mprj_io_in_3v3[18] ;
+ assign \user_io_in_3v3[17] = \mprj_io_in_3v3[17] ;
+ assign \user_io_in_3v3[16] = \mprj_io_in_3v3[16] ;
+ assign \user_io_in_3v3[15] = \mprj_io_in_3v3[15] ;
+ assign \user_io_in_3v3[14] = \mprj_io_in_3v3[14] ;
+ assign \user_io_in_3v3[13] = \mprj_io_in_3v3[13] ;
+ assign \user_io_in_3v3[12] = \mprj_io_in_3v3[12] ;
+ assign \user_io_in_3v3[11] = \mprj_io_in_3v3[11] ;
+ assign \user_io_in_3v3[10] = \mprj_io_in_3v3[10] ;
+ assign \user_io_in_3v3[9] = \mprj_io_in_3v3[9] ;
+ assign \user_io_in_3v3[8] = \mprj_io_in_3v3[8] ;
+ assign \user_io_in_3v3[7] = \mprj_io_in_3v3[7] ;
+ assign \user_io_in_3v3[6] = \mprj_io_in_3v3[6] ;
+ assign \user_io_in_3v3[5] = \mprj_io_in_3v3[5] ;
+ assign \user_io_in_3v3[4] = \mprj_io_in_3v3[4] ;
+ assign \user_io_in_3v3[3] = \mprj_io_in_3v3[3] ;
+ assign \user_io_in_3v3[2] = \mprj_io_in_3v3[2] ;
+ assign \user_io_in_3v3[1] = \mprj_io_in_3v3[1] ;
+ assign \user_io_in_3v3[0] = \mprj_io_in_3v3[0] ;
+ assign \gpio_load_2_shifted[12] = \gpio_load_1_shifted[0] ;
+ assign \gpio_load_2_shifted[11] = \gpio_load_2[12] ;
+ assign \gpio_load_2_shifted[10] = \gpio_load_2[11] ;
+ assign \gpio_load_2_shifted[9] = \gpio_load_2[10] ;
+ assign \gpio_load_2_shifted[8] = \gpio_load_2[9] ;
+ assign \gpio_load_2_shifted[7] = \gpio_load_2[8] ;
+ assign \gpio_load_2_shifted[6] = \gpio_load_2[7] ;
+ assign \gpio_load_2_shifted[5] = \gpio_load_2[6] ;
+ assign \gpio_load_2_shifted[4] = \gpio_load_2[5] ;
+ assign \gpio_load_2_shifted[3] = \gpio_load_2[4] ;
+ assign \gpio_load_2_shifted[2] = \gpio_load_2[3] ;
+ assign \gpio_load_2_shifted[1] = \gpio_load_2[2] ;
+ assign \gpio_load_2_shifted[0] = \gpio_load_2[1] ;
+ assign \gpio_resetn_2_shifted[12] = \gpio_resetn_1_shifted[0] ;
+ assign \gpio_resetn_2_shifted[11] = \gpio_resetn_2[12] ;
+ assign \gpio_resetn_2_shifted[10] = \gpio_resetn_2[11] ;
+ assign \gpio_resetn_2_shifted[9] = \gpio_resetn_2[10] ;
+ assign \gpio_resetn_2_shifted[8] = \gpio_resetn_2[9] ;
+ assign \gpio_resetn_2_shifted[7] = \gpio_resetn_2[8] ;
+ assign \gpio_resetn_2_shifted[6] = \gpio_resetn_2[7] ;
+ assign \gpio_resetn_2_shifted[5] = \gpio_resetn_2[6] ;
+ assign \gpio_resetn_2_shifted[4] = \gpio_resetn_2[5] ;
+ assign \gpio_resetn_2_shifted[3] = \gpio_resetn_2[4] ;
+ assign \gpio_resetn_2_shifted[2] = \gpio_resetn_2[3] ;
+ assign \gpio_resetn_2_shifted[1] = \gpio_resetn_2[2] ;
+ assign \gpio_resetn_2_shifted[0] = \gpio_resetn_2[1] ;
+ assign \gpio_load_1_shifted[13] = \gpio_load_1[12] ;
+ assign \gpio_load_1_shifted[12] = \gpio_load_1[11] ;
+ assign \gpio_load_1_shifted[11] = \gpio_load_1[10] ;
+ assign \gpio_load_1_shifted[10] = \gpio_load_1[9] ;
+ assign \gpio_load_1_shifted[9] = \gpio_load_1[8] ;
+ assign \gpio_load_1_shifted[8] = \gpio_load_1[7] ;
+ assign \gpio_load_1_shifted[7] = \gpio_load_1[6] ;
+ assign \gpio_load_1_shifted[6] = \gpio_load_1[5] ;
+ assign \gpio_load_1_shifted[5] = \gpio_load_1[4] ;
+ assign \gpio_load_1_shifted[4] = \gpio_load_1[3] ;
+ assign \gpio_load_1_shifted[3] = \gpio_load_1[2] ;
+ assign \gpio_load_1_shifted[2] = \gpio_load_1[1] ;
+ assign \gpio_load_1_shifted[1] = \gpio_load_1[0] ;
+ assign \gpio_clock_1_shifted[13] = \gpio_clock_1[12] ;
+ assign \gpio_clock_1_shifted[12] = \gpio_clock_1[11] ;
+ assign \gpio_clock_1_shifted[11] = \gpio_clock_1[10] ;
+ assign \gpio_clock_1_shifted[10] = \gpio_clock_1[9] ;
+ assign \gpio_clock_1_shifted[9] = \gpio_clock_1[8] ;
+ assign \gpio_clock_1_shifted[8] = \gpio_clock_1[7] ;
+ assign \gpio_clock_1_shifted[7] = \gpio_clock_1[6] ;
+ assign \gpio_clock_1_shifted[6] = \gpio_clock_1[5] ;
+ assign \gpio_clock_1_shifted[5] = \gpio_clock_1[4] ;
+ assign \gpio_clock_1_shifted[4] = \gpio_clock_1[3] ;
+ assign \gpio_clock_1_shifted[3] = \gpio_clock_1[2] ;
+ assign \gpio_clock_1_shifted[2] = \gpio_clock_1[1] ;
+ assign \gpio_clock_1_shifted[1] = \gpio_clock_1[0] ;
+ assign mprj_io_loader_data_2 = \gpio_serial_link_2_shifted[12] ;
+ assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+ assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+ assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+ assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+endmodule
diff --git a/caravel/verilog/gl/caravel.v b/caravel/verilog/gl/caravel.v
new file mode 100644
index 0000000..aa90fe8
--- /dev/null
+++ b/caravel/verilog/gl/caravel.v
@@ -0,0 +1,5053 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+ input clock;
+ wire clock_core;
+ wire debug_in;
+ wire debug_mode;
+ wire debug_oeb;
+ wire debug_out;
+ wire ext_clk_sel;
+ wire ext_reset;
+ output flash_clk;
+ wire flash_clk_core;
+ wire flash_clk_frame;
+ wire flash_clk_ieb;
+ wire flash_clk_ieb_core;
+ wire flash_clk_oeb;
+ wire flash_clk_oeb_core;
+ output flash_csb;
+ wire flash_csb_core;
+ wire flash_csb_frame;
+ wire flash_csb_ieb;
+ wire flash_csb_ieb_core;
+ wire flash_csb_oeb;
+ wire flash_csb_oeb_core;
+ output flash_io0;
+ wire flash_io0_di;
+ wire flash_io0_di_core;
+ wire flash_io0_do;
+ wire flash_io0_do_core;
+ wire flash_io0_ieb;
+ wire flash_io0_ieb_core;
+ wire flash_io0_oeb;
+ wire flash_io0_oeb_core;
+ output flash_io1;
+ wire flash_io1_di;
+ wire flash_io1_di_core;
+ wire flash_io1_do;
+ wire flash_io1_do_core;
+ wire flash_io1_ieb;
+ wire flash_io1_ieb_core;
+ wire flash_io1_oeb;
+ wire flash_io1_oeb_core;
+ wire flash_io2_di_core;
+ wire flash_io2_do_core;
+ wire flash_io2_ieb_core;
+ wire flash_io2_oeb_core;
+ wire flash_io3_di_core;
+ wire flash_io3_do_core;
+ wire flash_io3_ieb_core;
+ wire flash_io3_oeb_core;
+ inout gpio;
+ wire \gpio_clock_1[0] ;
+ wire \gpio_clock_1[10] ;
+ wire \gpio_clock_1[11] ;
+ wire \gpio_clock_1[12] ;
+ wire \gpio_clock_1[13] ;
+ wire \gpio_clock_1[14] ;
+ wire \gpio_clock_1[15] ;
+ wire \gpio_clock_1[16] ;
+ wire \gpio_clock_1[17] ;
+ wire \gpio_clock_1[18] ;
+ wire \gpio_clock_1[1] ;
+ wire \gpio_clock_1[2] ;
+ wire \gpio_clock_1[3] ;
+ wire \gpio_clock_1[4] ;
+ wire \gpio_clock_1[5] ;
+ wire \gpio_clock_1[6] ;
+ wire \gpio_clock_1[7] ;
+ wire \gpio_clock_1[8] ;
+ wire \gpio_clock_1[9] ;
+ wire \gpio_clock_1_shifted[0] ;
+ wire \gpio_clock_1_shifted[10] ;
+ wire \gpio_clock_1_shifted[11] ;
+ wire \gpio_clock_1_shifted[12] ;
+ wire \gpio_clock_1_shifted[13] ;
+ wire \gpio_clock_1_shifted[14] ;
+ wire \gpio_clock_1_shifted[15] ;
+ wire \gpio_clock_1_shifted[16] ;
+ wire \gpio_clock_1_shifted[17] ;
+ wire \gpio_clock_1_shifted[18] ;
+ wire \gpio_clock_1_shifted[1] ;
+ wire \gpio_clock_1_shifted[2] ;
+ wire \gpio_clock_1_shifted[3] ;
+ wire \gpio_clock_1_shifted[4] ;
+ wire \gpio_clock_1_shifted[5] ;
+ wire \gpio_clock_1_shifted[6] ;
+ wire \gpio_clock_1_shifted[7] ;
+ wire \gpio_clock_1_shifted[8] ;
+ wire \gpio_clock_1_shifted[9] ;
+ wire \gpio_clock_2[0] ;
+ wire \gpio_clock_2[10] ;
+ wire \gpio_clock_2[11] ;
+ wire \gpio_clock_2[12] ;
+ wire \gpio_clock_2[13] ;
+ wire \gpio_clock_2[14] ;
+ wire \gpio_clock_2[15] ;
+ wire \gpio_clock_2[16] ;
+ wire \gpio_clock_2[17] ;
+ wire \gpio_clock_2[18] ;
+ wire \gpio_clock_2[1] ;
+ wire \gpio_clock_2[2] ;
+ wire \gpio_clock_2[3] ;
+ wire \gpio_clock_2[4] ;
+ wire \gpio_clock_2[5] ;
+ wire \gpio_clock_2[6] ;
+ wire \gpio_clock_2[7] ;
+ wire \gpio_clock_2[8] ;
+ wire \gpio_clock_2[9] ;
+ wire \gpio_clock_2_shifted[0] ;
+ wire \gpio_clock_2_shifted[10] ;
+ wire \gpio_clock_2_shifted[11] ;
+ wire \gpio_clock_2_shifted[12] ;
+ wire \gpio_clock_2_shifted[13] ;
+ wire \gpio_clock_2_shifted[14] ;
+ wire \gpio_clock_2_shifted[15] ;
+ wire \gpio_clock_2_shifted[16] ;
+ wire \gpio_clock_2_shifted[17] ;
+ wire \gpio_clock_2_shifted[18] ;
+ wire \gpio_clock_2_shifted[1] ;
+ wire \gpio_clock_2_shifted[2] ;
+ wire \gpio_clock_2_shifted[3] ;
+ wire \gpio_clock_2_shifted[4] ;
+ wire \gpio_clock_2_shifted[5] ;
+ wire \gpio_clock_2_shifted[6] ;
+ wire \gpio_clock_2_shifted[7] ;
+ wire \gpio_clock_2_shifted[8] ;
+ wire \gpio_clock_2_shifted[9] ;
+ wire \gpio_defaults[0] ;
+ wire \gpio_defaults[100] ;
+ wire \gpio_defaults[101] ;
+ wire \gpio_defaults[102] ;
+ wire \gpio_defaults[103] ;
+ wire \gpio_defaults[104] ;
+ wire \gpio_defaults[105] ;
+ wire \gpio_defaults[106] ;
+ wire \gpio_defaults[107] ;
+ wire \gpio_defaults[108] ;
+ wire \gpio_defaults[109] ;
+ wire \gpio_defaults[10] ;
+ wire \gpio_defaults[110] ;
+ wire \gpio_defaults[111] ;
+ wire \gpio_defaults[112] ;
+ wire \gpio_defaults[113] ;
+ wire \gpio_defaults[114] ;
+ wire \gpio_defaults[115] ;
+ wire \gpio_defaults[116] ;
+ wire \gpio_defaults[117] ;
+ wire \gpio_defaults[118] ;
+ wire \gpio_defaults[119] ;
+ wire \gpio_defaults[11] ;
+ wire \gpio_defaults[120] ;
+ wire \gpio_defaults[121] ;
+ wire \gpio_defaults[122] ;
+ wire \gpio_defaults[123] ;
+ wire \gpio_defaults[124] ;
+ wire \gpio_defaults[125] ;
+ wire \gpio_defaults[126] ;
+ wire \gpio_defaults[127] ;
+ wire \gpio_defaults[128] ;
+ wire \gpio_defaults[129] ;
+ wire \gpio_defaults[12] ;
+ wire \gpio_defaults[130] ;
+ wire \gpio_defaults[131] ;
+ wire \gpio_defaults[132] ;
+ wire \gpio_defaults[133] ;
+ wire \gpio_defaults[134] ;
+ wire \gpio_defaults[135] ;
+ wire \gpio_defaults[136] ;
+ wire \gpio_defaults[137] ;
+ wire \gpio_defaults[138] ;
+ wire \gpio_defaults[139] ;
+ wire \gpio_defaults[13] ;
+ wire \gpio_defaults[140] ;
+ wire \gpio_defaults[141] ;
+ wire \gpio_defaults[142] ;
+ wire \gpio_defaults[143] ;
+ wire \gpio_defaults[144] ;
+ wire \gpio_defaults[145] ;
+ wire \gpio_defaults[146] ;
+ wire \gpio_defaults[147] ;
+ wire \gpio_defaults[148] ;
+ wire \gpio_defaults[149] ;
+ wire \gpio_defaults[14] ;
+ wire \gpio_defaults[150] ;
+ wire \gpio_defaults[151] ;
+ wire \gpio_defaults[152] ;
+ wire \gpio_defaults[153] ;
+ wire \gpio_defaults[154] ;
+ wire \gpio_defaults[155] ;
+ wire \gpio_defaults[156] ;
+ wire \gpio_defaults[157] ;
+ wire \gpio_defaults[158] ;
+ wire \gpio_defaults[159] ;
+ wire \gpio_defaults[15] ;
+ wire \gpio_defaults[160] ;
+ wire \gpio_defaults[161] ;
+ wire \gpio_defaults[162] ;
+ wire \gpio_defaults[163] ;
+ wire \gpio_defaults[164] ;
+ wire \gpio_defaults[165] ;
+ wire \gpio_defaults[166] ;
+ wire \gpio_defaults[167] ;
+ wire \gpio_defaults[168] ;
+ wire \gpio_defaults[169] ;
+ wire \gpio_defaults[16] ;
+ wire \gpio_defaults[170] ;
+ wire \gpio_defaults[171] ;
+ wire \gpio_defaults[172] ;
+ wire \gpio_defaults[173] ;
+ wire \gpio_defaults[174] ;
+ wire \gpio_defaults[175] ;
+ wire \gpio_defaults[176] ;
+ wire \gpio_defaults[177] ;
+ wire \gpio_defaults[178] ;
+ wire \gpio_defaults[179] ;
+ wire \gpio_defaults[17] ;
+ wire \gpio_defaults[180] ;
+ wire \gpio_defaults[181] ;
+ wire \gpio_defaults[182] ;
+ wire \gpio_defaults[183] ;
+ wire \gpio_defaults[184] ;
+ wire \gpio_defaults[185] ;
+ wire \gpio_defaults[186] ;
+ wire \gpio_defaults[187] ;
+ wire \gpio_defaults[188] ;
+ wire \gpio_defaults[189] ;
+ wire \gpio_defaults[18] ;
+ wire \gpio_defaults[190] ;
+ wire \gpio_defaults[191] ;
+ wire \gpio_defaults[192] ;
+ wire \gpio_defaults[193] ;
+ wire \gpio_defaults[194] ;
+ wire \gpio_defaults[195] ;
+ wire \gpio_defaults[196] ;
+ wire \gpio_defaults[197] ;
+ wire \gpio_defaults[198] ;
+ wire \gpio_defaults[199] ;
+ wire \gpio_defaults[19] ;
+ wire \gpio_defaults[1] ;
+ wire \gpio_defaults[200] ;
+ wire \gpio_defaults[201] ;
+ wire \gpio_defaults[202] ;
+ wire \gpio_defaults[203] ;
+ wire \gpio_defaults[204] ;
+ wire \gpio_defaults[205] ;
+ wire \gpio_defaults[206] ;
+ wire \gpio_defaults[207] ;
+ wire \gpio_defaults[208] ;
+ wire \gpio_defaults[209] ;
+ wire \gpio_defaults[20] ;
+ wire \gpio_defaults[210] ;
+ wire \gpio_defaults[211] ;
+ wire \gpio_defaults[212] ;
+ wire \gpio_defaults[213] ;
+ wire \gpio_defaults[214] ;
+ wire \gpio_defaults[215] ;
+ wire \gpio_defaults[216] ;
+ wire \gpio_defaults[217] ;
+ wire \gpio_defaults[218] ;
+ wire \gpio_defaults[219] ;
+ wire \gpio_defaults[21] ;
+ wire \gpio_defaults[220] ;
+ wire \gpio_defaults[221] ;
+ wire \gpio_defaults[222] ;
+ wire \gpio_defaults[223] ;
+ wire \gpio_defaults[224] ;
+ wire \gpio_defaults[225] ;
+ wire \gpio_defaults[226] ;
+ wire \gpio_defaults[227] ;
+ wire \gpio_defaults[228] ;
+ wire \gpio_defaults[229] ;
+ wire \gpio_defaults[22] ;
+ wire \gpio_defaults[230] ;
+ wire \gpio_defaults[231] ;
+ wire \gpio_defaults[232] ;
+ wire \gpio_defaults[233] ;
+ wire \gpio_defaults[234] ;
+ wire \gpio_defaults[235] ;
+ wire \gpio_defaults[236] ;
+ wire \gpio_defaults[237] ;
+ wire \gpio_defaults[238] ;
+ wire \gpio_defaults[239] ;
+ wire \gpio_defaults[23] ;
+ wire \gpio_defaults[240] ;
+ wire \gpio_defaults[241] ;
+ wire \gpio_defaults[242] ;
+ wire \gpio_defaults[243] ;
+ wire \gpio_defaults[244] ;
+ wire \gpio_defaults[245] ;
+ wire \gpio_defaults[246] ;
+ wire \gpio_defaults[247] ;
+ wire \gpio_defaults[248] ;
+ wire \gpio_defaults[249] ;
+ wire \gpio_defaults[24] ;
+ wire \gpio_defaults[250] ;
+ wire \gpio_defaults[251] ;
+ wire \gpio_defaults[252] ;
+ wire \gpio_defaults[253] ;
+ wire \gpio_defaults[254] ;
+ wire \gpio_defaults[255] ;
+ wire \gpio_defaults[256] ;
+ wire \gpio_defaults[257] ;
+ wire \gpio_defaults[258] ;
+ wire \gpio_defaults[259] ;
+ wire \gpio_defaults[25] ;
+ wire \gpio_defaults[260] ;
+ wire \gpio_defaults[261] ;
+ wire \gpio_defaults[262] ;
+ wire \gpio_defaults[263] ;
+ wire \gpio_defaults[264] ;
+ wire \gpio_defaults[265] ;
+ wire \gpio_defaults[266] ;
+ wire \gpio_defaults[267] ;
+ wire \gpio_defaults[268] ;
+ wire \gpio_defaults[269] ;
+ wire \gpio_defaults[26] ;
+ wire \gpio_defaults[270] ;
+ wire \gpio_defaults[271] ;
+ wire \gpio_defaults[272] ;
+ wire \gpio_defaults[273] ;
+ wire \gpio_defaults[274] ;
+ wire \gpio_defaults[275] ;
+ wire \gpio_defaults[276] ;
+ wire \gpio_defaults[277] ;
+ wire \gpio_defaults[278] ;
+ wire \gpio_defaults[279] ;
+ wire \gpio_defaults[27] ;
+ wire \gpio_defaults[280] ;
+ wire \gpio_defaults[281] ;
+ wire \gpio_defaults[282] ;
+ wire \gpio_defaults[283] ;
+ wire \gpio_defaults[284] ;
+ wire \gpio_defaults[285] ;
+ wire \gpio_defaults[286] ;
+ wire \gpio_defaults[287] ;
+ wire \gpio_defaults[288] ;
+ wire \gpio_defaults[289] ;
+ wire \gpio_defaults[28] ;
+ wire \gpio_defaults[290] ;
+ wire \gpio_defaults[291] ;
+ wire \gpio_defaults[292] ;
+ wire \gpio_defaults[293] ;
+ wire \gpio_defaults[294] ;
+ wire \gpio_defaults[295] ;
+ wire \gpio_defaults[296] ;
+ wire \gpio_defaults[297] ;
+ wire \gpio_defaults[298] ;
+ wire \gpio_defaults[299] ;
+ wire \gpio_defaults[29] ;
+ wire \gpio_defaults[2] ;
+ wire \gpio_defaults[300] ;
+ wire \gpio_defaults[301] ;
+ wire \gpio_defaults[302] ;
+ wire \gpio_defaults[303] ;
+ wire \gpio_defaults[304] ;
+ wire \gpio_defaults[305] ;
+ wire \gpio_defaults[306] ;
+ wire \gpio_defaults[307] ;
+ wire \gpio_defaults[308] ;
+ wire \gpio_defaults[309] ;
+ wire \gpio_defaults[30] ;
+ wire \gpio_defaults[310] ;
+ wire \gpio_defaults[311] ;
+ wire \gpio_defaults[312] ;
+ wire \gpio_defaults[313] ;
+ wire \gpio_defaults[314] ;
+ wire \gpio_defaults[315] ;
+ wire \gpio_defaults[316] ;
+ wire \gpio_defaults[317] ;
+ wire \gpio_defaults[318] ;
+ wire \gpio_defaults[319] ;
+ wire \gpio_defaults[31] ;
+ wire \gpio_defaults[320] ;
+ wire \gpio_defaults[321] ;
+ wire \gpio_defaults[322] ;
+ wire \gpio_defaults[323] ;
+ wire \gpio_defaults[324] ;
+ wire \gpio_defaults[325] ;
+ wire \gpio_defaults[326] ;
+ wire \gpio_defaults[327] ;
+ wire \gpio_defaults[328] ;
+ wire \gpio_defaults[329] ;
+ wire \gpio_defaults[32] ;
+ wire \gpio_defaults[330] ;
+ wire \gpio_defaults[331] ;
+ wire \gpio_defaults[332] ;
+ wire \gpio_defaults[333] ;
+ wire \gpio_defaults[334] ;
+ wire \gpio_defaults[335] ;
+ wire \gpio_defaults[336] ;
+ wire \gpio_defaults[337] ;
+ wire \gpio_defaults[338] ;
+ wire \gpio_defaults[339] ;
+ wire \gpio_defaults[33] ;
+ wire \gpio_defaults[340] ;
+ wire \gpio_defaults[341] ;
+ wire \gpio_defaults[342] ;
+ wire \gpio_defaults[343] ;
+ wire \gpio_defaults[344] ;
+ wire \gpio_defaults[345] ;
+ wire \gpio_defaults[346] ;
+ wire \gpio_defaults[347] ;
+ wire \gpio_defaults[348] ;
+ wire \gpio_defaults[349] ;
+ wire \gpio_defaults[34] ;
+ wire \gpio_defaults[350] ;
+ wire \gpio_defaults[351] ;
+ wire \gpio_defaults[352] ;
+ wire \gpio_defaults[353] ;
+ wire \gpio_defaults[354] ;
+ wire \gpio_defaults[355] ;
+ wire \gpio_defaults[356] ;
+ wire \gpio_defaults[357] ;
+ wire \gpio_defaults[358] ;
+ wire \gpio_defaults[359] ;
+ wire \gpio_defaults[35] ;
+ wire \gpio_defaults[360] ;
+ wire \gpio_defaults[361] ;
+ wire \gpio_defaults[362] ;
+ wire \gpio_defaults[363] ;
+ wire \gpio_defaults[364] ;
+ wire \gpio_defaults[365] ;
+ wire \gpio_defaults[366] ;
+ wire \gpio_defaults[367] ;
+ wire \gpio_defaults[368] ;
+ wire \gpio_defaults[369] ;
+ wire \gpio_defaults[36] ;
+ wire \gpio_defaults[370] ;
+ wire \gpio_defaults[371] ;
+ wire \gpio_defaults[372] ;
+ wire \gpio_defaults[373] ;
+ wire \gpio_defaults[374] ;
+ wire \gpio_defaults[375] ;
+ wire \gpio_defaults[376] ;
+ wire \gpio_defaults[377] ;
+ wire \gpio_defaults[378] ;
+ wire \gpio_defaults[379] ;
+ wire \gpio_defaults[37] ;
+ wire \gpio_defaults[380] ;
+ wire \gpio_defaults[381] ;
+ wire \gpio_defaults[382] ;
+ wire \gpio_defaults[383] ;
+ wire \gpio_defaults[384] ;
+ wire \gpio_defaults[385] ;
+ wire \gpio_defaults[386] ;
+ wire \gpio_defaults[387] ;
+ wire \gpio_defaults[388] ;
+ wire \gpio_defaults[389] ;
+ wire \gpio_defaults[38] ;
+ wire \gpio_defaults[390] ;
+ wire \gpio_defaults[391] ;
+ wire \gpio_defaults[392] ;
+ wire \gpio_defaults[393] ;
+ wire \gpio_defaults[394] ;
+ wire \gpio_defaults[395] ;
+ wire \gpio_defaults[396] ;
+ wire \gpio_defaults[397] ;
+ wire \gpio_defaults[398] ;
+ wire \gpio_defaults[399] ;
+ wire \gpio_defaults[39] ;
+ wire \gpio_defaults[3] ;
+ wire \gpio_defaults[400] ;
+ wire \gpio_defaults[401] ;
+ wire \gpio_defaults[402] ;
+ wire \gpio_defaults[403] ;
+ wire \gpio_defaults[404] ;
+ wire \gpio_defaults[405] ;
+ wire \gpio_defaults[406] ;
+ wire \gpio_defaults[407] ;
+ wire \gpio_defaults[408] ;
+ wire \gpio_defaults[409] ;
+ wire \gpio_defaults[40] ;
+ wire \gpio_defaults[410] ;
+ wire \gpio_defaults[411] ;
+ wire \gpio_defaults[412] ;
+ wire \gpio_defaults[413] ;
+ wire \gpio_defaults[414] ;
+ wire \gpio_defaults[415] ;
+ wire \gpio_defaults[416] ;
+ wire \gpio_defaults[417] ;
+ wire \gpio_defaults[418] ;
+ wire \gpio_defaults[419] ;
+ wire \gpio_defaults[41] ;
+ wire \gpio_defaults[420] ;
+ wire \gpio_defaults[421] ;
+ wire \gpio_defaults[422] ;
+ wire \gpio_defaults[423] ;
+ wire \gpio_defaults[424] ;
+ wire \gpio_defaults[425] ;
+ wire \gpio_defaults[426] ;
+ wire \gpio_defaults[427] ;
+ wire \gpio_defaults[428] ;
+ wire \gpio_defaults[429] ;
+ wire \gpio_defaults[42] ;
+ wire \gpio_defaults[430] ;
+ wire \gpio_defaults[431] ;
+ wire \gpio_defaults[432] ;
+ wire \gpio_defaults[433] ;
+ wire \gpio_defaults[434] ;
+ wire \gpio_defaults[435] ;
+ wire \gpio_defaults[436] ;
+ wire \gpio_defaults[437] ;
+ wire \gpio_defaults[438] ;
+ wire \gpio_defaults[439] ;
+ wire \gpio_defaults[43] ;
+ wire \gpio_defaults[440] ;
+ wire \gpio_defaults[441] ;
+ wire \gpio_defaults[442] ;
+ wire \gpio_defaults[443] ;
+ wire \gpio_defaults[444] ;
+ wire \gpio_defaults[445] ;
+ wire \gpio_defaults[446] ;
+ wire \gpio_defaults[447] ;
+ wire \gpio_defaults[448] ;
+ wire \gpio_defaults[449] ;
+ wire \gpio_defaults[44] ;
+ wire \gpio_defaults[450] ;
+ wire \gpio_defaults[451] ;
+ wire \gpio_defaults[452] ;
+ wire \gpio_defaults[453] ;
+ wire \gpio_defaults[454] ;
+ wire \gpio_defaults[455] ;
+ wire \gpio_defaults[456] ;
+ wire \gpio_defaults[457] ;
+ wire \gpio_defaults[458] ;
+ wire \gpio_defaults[459] ;
+ wire \gpio_defaults[45] ;
+ wire \gpio_defaults[460] ;
+ wire \gpio_defaults[461] ;
+ wire \gpio_defaults[462] ;
+ wire \gpio_defaults[463] ;
+ wire \gpio_defaults[464] ;
+ wire \gpio_defaults[465] ;
+ wire \gpio_defaults[466] ;
+ wire \gpio_defaults[467] ;
+ wire \gpio_defaults[468] ;
+ wire \gpio_defaults[469] ;
+ wire \gpio_defaults[46] ;
+ wire \gpio_defaults[470] ;
+ wire \gpio_defaults[471] ;
+ wire \gpio_defaults[472] ;
+ wire \gpio_defaults[473] ;
+ wire \gpio_defaults[474] ;
+ wire \gpio_defaults[475] ;
+ wire \gpio_defaults[476] ;
+ wire \gpio_defaults[477] ;
+ wire \gpio_defaults[478] ;
+ wire \gpio_defaults[479] ;
+ wire \gpio_defaults[47] ;
+ wire \gpio_defaults[480] ;
+ wire \gpio_defaults[481] ;
+ wire \gpio_defaults[482] ;
+ wire \gpio_defaults[483] ;
+ wire \gpio_defaults[484] ;
+ wire \gpio_defaults[485] ;
+ wire \gpio_defaults[486] ;
+ wire \gpio_defaults[487] ;
+ wire \gpio_defaults[488] ;
+ wire \gpio_defaults[489] ;
+ wire \gpio_defaults[48] ;
+ wire \gpio_defaults[490] ;
+ wire \gpio_defaults[491] ;
+ wire \gpio_defaults[492] ;
+ wire \gpio_defaults[493] ;
+ wire \gpio_defaults[49] ;
+ wire \gpio_defaults[4] ;
+ wire \gpio_defaults[50] ;
+ wire \gpio_defaults[51] ;
+ wire \gpio_defaults[52] ;
+ wire \gpio_defaults[53] ;
+ wire \gpio_defaults[54] ;
+ wire \gpio_defaults[55] ;
+ wire \gpio_defaults[56] ;
+ wire \gpio_defaults[57] ;
+ wire \gpio_defaults[58] ;
+ wire \gpio_defaults[59] ;
+ wire \gpio_defaults[5] ;
+ wire \gpio_defaults[60] ;
+ wire \gpio_defaults[61] ;
+ wire \gpio_defaults[62] ;
+ wire \gpio_defaults[63] ;
+ wire \gpio_defaults[64] ;
+ wire \gpio_defaults[65] ;
+ wire \gpio_defaults[66] ;
+ wire \gpio_defaults[67] ;
+ wire \gpio_defaults[68] ;
+ wire \gpio_defaults[69] ;
+ wire \gpio_defaults[6] ;
+ wire \gpio_defaults[70] ;
+ wire \gpio_defaults[71] ;
+ wire \gpio_defaults[72] ;
+ wire \gpio_defaults[73] ;
+ wire \gpio_defaults[74] ;
+ wire \gpio_defaults[75] ;
+ wire \gpio_defaults[76] ;
+ wire \gpio_defaults[77] ;
+ wire \gpio_defaults[78] ;
+ wire \gpio_defaults[79] ;
+ wire \gpio_defaults[7] ;
+ wire \gpio_defaults[80] ;
+ wire \gpio_defaults[81] ;
+ wire \gpio_defaults[82] ;
+ wire \gpio_defaults[83] ;
+ wire \gpio_defaults[84] ;
+ wire \gpio_defaults[85] ;
+ wire \gpio_defaults[86] ;
+ wire \gpio_defaults[87] ;
+ wire \gpio_defaults[88] ;
+ wire \gpio_defaults[89] ;
+ wire \gpio_defaults[8] ;
+ wire \gpio_defaults[90] ;
+ wire \gpio_defaults[91] ;
+ wire \gpio_defaults[92] ;
+ wire \gpio_defaults[93] ;
+ wire \gpio_defaults[94] ;
+ wire \gpio_defaults[95] ;
+ wire \gpio_defaults[96] ;
+ wire \gpio_defaults[97] ;
+ wire \gpio_defaults[98] ;
+ wire \gpio_defaults[99] ;
+ wire \gpio_defaults[9] ;
+ wire gpio_in_core;
+ wire gpio_inenb_core;
+ wire \gpio_load_1[0] ;
+ wire \gpio_load_1[10] ;
+ wire \gpio_load_1[11] ;
+ wire \gpio_load_1[12] ;
+ wire \gpio_load_1[13] ;
+ wire \gpio_load_1[14] ;
+ wire \gpio_load_1[15] ;
+ wire \gpio_load_1[16] ;
+ wire \gpio_load_1[17] ;
+ wire \gpio_load_1[18] ;
+ wire \gpio_load_1[1] ;
+ wire \gpio_load_1[2] ;
+ wire \gpio_load_1[3] ;
+ wire \gpio_load_1[4] ;
+ wire \gpio_load_1[5] ;
+ wire \gpio_load_1[6] ;
+ wire \gpio_load_1[7] ;
+ wire \gpio_load_1[8] ;
+ wire \gpio_load_1[9] ;
+ wire \gpio_load_1_shifted[0] ;
+ wire \gpio_load_1_shifted[10] ;
+ wire \gpio_load_1_shifted[11] ;
+ wire \gpio_load_1_shifted[12] ;
+ wire \gpio_load_1_shifted[13] ;
+ wire \gpio_load_1_shifted[14] ;
+ wire \gpio_load_1_shifted[15] ;
+ wire \gpio_load_1_shifted[16] ;
+ wire \gpio_load_1_shifted[17] ;
+ wire \gpio_load_1_shifted[18] ;
+ wire \gpio_load_1_shifted[1] ;
+ wire \gpio_load_1_shifted[2] ;
+ wire \gpio_load_1_shifted[3] ;
+ wire \gpio_load_1_shifted[4] ;
+ wire \gpio_load_1_shifted[5] ;
+ wire \gpio_load_1_shifted[6] ;
+ wire \gpio_load_1_shifted[7] ;
+ wire \gpio_load_1_shifted[8] ;
+ wire \gpio_load_1_shifted[9] ;
+ wire \gpio_load_2[0] ;
+ wire \gpio_load_2[10] ;
+ wire \gpio_load_2[11] ;
+ wire \gpio_load_2[12] ;
+ wire \gpio_load_2[13] ;
+ wire \gpio_load_2[14] ;
+ wire \gpio_load_2[15] ;
+ wire \gpio_load_2[16] ;
+ wire \gpio_load_2[17] ;
+ wire \gpio_load_2[18] ;
+ wire \gpio_load_2[1] ;
+ wire \gpio_load_2[2] ;
+ wire \gpio_load_2[3] ;
+ wire \gpio_load_2[4] ;
+ wire \gpio_load_2[5] ;
+ wire \gpio_load_2[6] ;
+ wire \gpio_load_2[7] ;
+ wire \gpio_load_2[8] ;
+ wire \gpio_load_2[9] ;
+ wire \gpio_load_2_shifted[0] ;
+ wire \gpio_load_2_shifted[10] ;
+ wire \gpio_load_2_shifted[11] ;
+ wire \gpio_load_2_shifted[12] ;
+ wire \gpio_load_2_shifted[13] ;
+ wire \gpio_load_2_shifted[14] ;
+ wire \gpio_load_2_shifted[15] ;
+ wire \gpio_load_2_shifted[16] ;
+ wire \gpio_load_2_shifted[17] ;
+ wire \gpio_load_2_shifted[18] ;
+ wire \gpio_load_2_shifted[1] ;
+ wire \gpio_load_2_shifted[2] ;
+ wire \gpio_load_2_shifted[3] ;
+ wire \gpio_load_2_shifted[4] ;
+ wire \gpio_load_2_shifted[5] ;
+ wire \gpio_load_2_shifted[6] ;
+ wire \gpio_load_2_shifted[7] ;
+ wire \gpio_load_2_shifted[8] ;
+ wire \gpio_load_2_shifted[9] ;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_out_core;
+ wire gpio_outenb_core;
+ wire \gpio_resetn_1[0] ;
+ wire \gpio_resetn_1[10] ;
+ wire \gpio_resetn_1[11] ;
+ wire \gpio_resetn_1[12] ;
+ wire \gpio_resetn_1[13] ;
+ wire \gpio_resetn_1[14] ;
+ wire \gpio_resetn_1[15] ;
+ wire \gpio_resetn_1[16] ;
+ wire \gpio_resetn_1[17] ;
+ wire \gpio_resetn_1[18] ;
+ wire \gpio_resetn_1[1] ;
+ wire \gpio_resetn_1[2] ;
+ wire \gpio_resetn_1[3] ;
+ wire \gpio_resetn_1[4] ;
+ wire \gpio_resetn_1[5] ;
+ wire \gpio_resetn_1[6] ;
+ wire \gpio_resetn_1[7] ;
+ wire \gpio_resetn_1[8] ;
+ wire \gpio_resetn_1[9] ;
+ wire \gpio_resetn_1_shifted[0] ;
+ wire \gpio_resetn_1_shifted[10] ;
+ wire \gpio_resetn_1_shifted[11] ;
+ wire \gpio_resetn_1_shifted[12] ;
+ wire \gpio_resetn_1_shifted[13] ;
+ wire \gpio_resetn_1_shifted[14] ;
+ wire \gpio_resetn_1_shifted[15] ;
+ wire \gpio_resetn_1_shifted[16] ;
+ wire \gpio_resetn_1_shifted[17] ;
+ wire \gpio_resetn_1_shifted[18] ;
+ wire \gpio_resetn_1_shifted[1] ;
+ wire \gpio_resetn_1_shifted[2] ;
+ wire \gpio_resetn_1_shifted[3] ;
+ wire \gpio_resetn_1_shifted[4] ;
+ wire \gpio_resetn_1_shifted[5] ;
+ wire \gpio_resetn_1_shifted[6] ;
+ wire \gpio_resetn_1_shifted[7] ;
+ wire \gpio_resetn_1_shifted[8] ;
+ wire \gpio_resetn_1_shifted[9] ;
+ wire \gpio_resetn_2[0] ;
+ wire \gpio_resetn_2[10] ;
+ wire \gpio_resetn_2[11] ;
+ wire \gpio_resetn_2[12] ;
+ wire \gpio_resetn_2[13] ;
+ wire \gpio_resetn_2[14] ;
+ wire \gpio_resetn_2[15] ;
+ wire \gpio_resetn_2[16] ;
+ wire \gpio_resetn_2[17] ;
+ wire \gpio_resetn_2[18] ;
+ wire \gpio_resetn_2[1] ;
+ wire \gpio_resetn_2[2] ;
+ wire \gpio_resetn_2[3] ;
+ wire \gpio_resetn_2[4] ;
+ wire \gpio_resetn_2[5] ;
+ wire \gpio_resetn_2[6] ;
+ wire \gpio_resetn_2[7] ;
+ wire \gpio_resetn_2[8] ;
+ wire \gpio_resetn_2[9] ;
+ wire \gpio_resetn_2_shifted[0] ;
+ wire \gpio_resetn_2_shifted[10] ;
+ wire \gpio_resetn_2_shifted[11] ;
+ wire \gpio_resetn_2_shifted[12] ;
+ wire \gpio_resetn_2_shifted[13] ;
+ wire \gpio_resetn_2_shifted[14] ;
+ wire \gpio_resetn_2_shifted[15] ;
+ wire \gpio_resetn_2_shifted[16] ;
+ wire \gpio_resetn_2_shifted[17] ;
+ wire \gpio_resetn_2_shifted[18] ;
+ wire \gpio_resetn_2_shifted[1] ;
+ wire \gpio_resetn_2_shifted[2] ;
+ wire \gpio_resetn_2_shifted[3] ;
+ wire \gpio_resetn_2_shifted[4] ;
+ wire \gpio_resetn_2_shifted[5] ;
+ wire \gpio_resetn_2_shifted[6] ;
+ wire \gpio_resetn_2_shifted[7] ;
+ wire \gpio_resetn_2_shifted[8] ;
+ wire \gpio_resetn_2_shifted[9] ;
+ wire \gpio_serial_link_1[0] ;
+ wire \gpio_serial_link_1[10] ;
+ wire \gpio_serial_link_1[11] ;
+ wire \gpio_serial_link_1[12] ;
+ wire \gpio_serial_link_1[13] ;
+ wire \gpio_serial_link_1[14] ;
+ wire \gpio_serial_link_1[15] ;
+ wire \gpio_serial_link_1[16] ;
+ wire \gpio_serial_link_1[17] ;
+ wire \gpio_serial_link_1[18] ;
+ wire \gpio_serial_link_1[1] ;
+ wire \gpio_serial_link_1[2] ;
+ wire \gpio_serial_link_1[3] ;
+ wire \gpio_serial_link_1[4] ;
+ wire \gpio_serial_link_1[5] ;
+ wire \gpio_serial_link_1[6] ;
+ wire \gpio_serial_link_1[7] ;
+ wire \gpio_serial_link_1[8] ;
+ wire \gpio_serial_link_1[9] ;
+ wire \gpio_serial_link_1_shifted[0] ;
+ wire \gpio_serial_link_1_shifted[10] ;
+ wire \gpio_serial_link_1_shifted[11] ;
+ wire \gpio_serial_link_1_shifted[12] ;
+ wire \gpio_serial_link_1_shifted[13] ;
+ wire \gpio_serial_link_1_shifted[14] ;
+ wire \gpio_serial_link_1_shifted[15] ;
+ wire \gpio_serial_link_1_shifted[16] ;
+ wire \gpio_serial_link_1_shifted[17] ;
+ wire \gpio_serial_link_1_shifted[18] ;
+ wire \gpio_serial_link_1_shifted[1] ;
+ wire \gpio_serial_link_1_shifted[2] ;
+ wire \gpio_serial_link_1_shifted[3] ;
+ wire \gpio_serial_link_1_shifted[4] ;
+ wire \gpio_serial_link_1_shifted[5] ;
+ wire \gpio_serial_link_1_shifted[6] ;
+ wire \gpio_serial_link_1_shifted[7] ;
+ wire \gpio_serial_link_1_shifted[8] ;
+ wire \gpio_serial_link_1_shifted[9] ;
+ wire \gpio_serial_link_2[0] ;
+ wire \gpio_serial_link_2[10] ;
+ wire \gpio_serial_link_2[11] ;
+ wire \gpio_serial_link_2[12] ;
+ wire \gpio_serial_link_2[13] ;
+ wire \gpio_serial_link_2[14] ;
+ wire \gpio_serial_link_2[15] ;
+ wire \gpio_serial_link_2[16] ;
+ wire \gpio_serial_link_2[17] ;
+ wire \gpio_serial_link_2[18] ;
+ wire \gpio_serial_link_2[1] ;
+ wire \gpio_serial_link_2[2] ;
+ wire \gpio_serial_link_2[3] ;
+ wire \gpio_serial_link_2[4] ;
+ wire \gpio_serial_link_2[5] ;
+ wire \gpio_serial_link_2[6] ;
+ wire \gpio_serial_link_2[7] ;
+ wire \gpio_serial_link_2[8] ;
+ wire \gpio_serial_link_2[9] ;
+ wire \gpio_serial_link_2_shifted[0] ;
+ wire \gpio_serial_link_2_shifted[10] ;
+ wire \gpio_serial_link_2_shifted[11] ;
+ wire \gpio_serial_link_2_shifted[12] ;
+ wire \gpio_serial_link_2_shifted[13] ;
+ wire \gpio_serial_link_2_shifted[14] ;
+ wire \gpio_serial_link_2_shifted[15] ;
+ wire \gpio_serial_link_2_shifted[16] ;
+ wire \gpio_serial_link_2_shifted[17] ;
+ wire \gpio_serial_link_2_shifted[18] ;
+ wire \gpio_serial_link_2_shifted[1] ;
+ wire \gpio_serial_link_2_shifted[2] ;
+ wire \gpio_serial_link_2_shifted[3] ;
+ wire \gpio_serial_link_2_shifted[4] ;
+ wire \gpio_serial_link_2_shifted[5] ;
+ wire \gpio_serial_link_2_shifted[6] ;
+ wire \gpio_serial_link_2_shifted[7] ;
+ wire \gpio_serial_link_2_shifted[8] ;
+ wire \gpio_serial_link_2_shifted[9] ;
+ wire hk_ack_i;
+ wire \hk_dat_i[0] ;
+ wire \hk_dat_i[10] ;
+ wire \hk_dat_i[11] ;
+ wire \hk_dat_i[12] ;
+ wire \hk_dat_i[13] ;
+ wire \hk_dat_i[14] ;
+ wire \hk_dat_i[15] ;
+ wire \hk_dat_i[16] ;
+ wire \hk_dat_i[17] ;
+ wire \hk_dat_i[18] ;
+ wire \hk_dat_i[19] ;
+ wire \hk_dat_i[1] ;
+ wire \hk_dat_i[20] ;
+ wire \hk_dat_i[21] ;
+ wire \hk_dat_i[22] ;
+ wire \hk_dat_i[23] ;
+ wire \hk_dat_i[24] ;
+ wire \hk_dat_i[25] ;
+ wire \hk_dat_i[26] ;
+ wire \hk_dat_i[27] ;
+ wire \hk_dat_i[28] ;
+ wire \hk_dat_i[29] ;
+ wire \hk_dat_i[2] ;
+ wire \hk_dat_i[30] ;
+ wire \hk_dat_i[31] ;
+ wire \hk_dat_i[3] ;
+ wire \hk_dat_i[4] ;
+ wire \hk_dat_i[5] ;
+ wire \hk_dat_i[6] ;
+ wire \hk_dat_i[7] ;
+ wire \hk_dat_i[8] ;
+ wire \hk_dat_i[9] ;
+ wire hk_stb_o;
+ wire hk_cyc_o;
+ wire \hkspi_sram_addr[0] ;
+ wire \hkspi_sram_addr[1] ;
+ wire \hkspi_sram_addr[2] ;
+ wire \hkspi_sram_addr[3] ;
+ wire \hkspi_sram_addr[4] ;
+ wire \hkspi_sram_addr[5] ;
+ wire \hkspi_sram_addr[6] ;
+ wire \hkspi_sram_addr[7] ;
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire \hkspi_sram_data[0] ;
+ wire \hkspi_sram_data[10] ;
+ wire \hkspi_sram_data[11] ;
+ wire \hkspi_sram_data[12] ;
+ wire \hkspi_sram_data[13] ;
+ wire \hkspi_sram_data[14] ;
+ wire \hkspi_sram_data[15] ;
+ wire \hkspi_sram_data[16] ;
+ wire \hkspi_sram_data[17] ;
+ wire \hkspi_sram_data[18] ;
+ wire \hkspi_sram_data[19] ;
+ wire \hkspi_sram_data[1] ;
+ wire \hkspi_sram_data[20] ;
+ wire \hkspi_sram_data[21] ;
+ wire \hkspi_sram_data[22] ;
+ wire \hkspi_sram_data[23] ;
+ wire \hkspi_sram_data[24] ;
+ wire \hkspi_sram_data[25] ;
+ wire \hkspi_sram_data[26] ;
+ wire \hkspi_sram_data[27] ;
+ wire \hkspi_sram_data[28] ;
+ wire \hkspi_sram_data[29] ;
+ wire \hkspi_sram_data[2] ;
+ wire \hkspi_sram_data[30] ;
+ wire \hkspi_sram_data[31] ;
+ wire \hkspi_sram_data[3] ;
+ wire \hkspi_sram_data[4] ;
+ wire \hkspi_sram_data[5] ;
+ wire \hkspi_sram_data[6] ;
+ wire \hkspi_sram_data[7] ;
+ wire \hkspi_sram_data[8] ;
+ wire \hkspi_sram_data[9] ;
+ wire \irq_spi[0] ;
+ wire \irq_spi[1] ;
+ wire \irq_spi[2] ;
+ wire \la_data_in_mprj[0] ;
+ wire \la_data_in_mprj[100] ;
+ wire \la_data_in_mprj[101] ;
+ wire \la_data_in_mprj[102] ;
+ wire \la_data_in_mprj[103] ;
+ wire \la_data_in_mprj[104] ;
+ wire \la_data_in_mprj[105] ;
+ wire \la_data_in_mprj[106] ;
+ wire \la_data_in_mprj[107] ;
+ wire \la_data_in_mprj[108] ;
+ wire \la_data_in_mprj[109] ;
+ wire \la_data_in_mprj[10] ;
+ wire \la_data_in_mprj[110] ;
+ wire \la_data_in_mprj[111] ;
+ wire \la_data_in_mprj[112] ;
+ wire \la_data_in_mprj[113] ;
+ wire \la_data_in_mprj[114] ;
+ wire \la_data_in_mprj[115] ;
+ wire \la_data_in_mprj[116] ;
+ wire \la_data_in_mprj[117] ;
+ wire \la_data_in_mprj[118] ;
+ wire \la_data_in_mprj[119] ;
+ wire \la_data_in_mprj[11] ;
+ wire \la_data_in_mprj[120] ;
+ wire \la_data_in_mprj[121] ;
+ wire \la_data_in_mprj[122] ;
+ wire \la_data_in_mprj[123] ;
+ wire \la_data_in_mprj[124] ;
+ wire \la_data_in_mprj[125] ;
+ wire \la_data_in_mprj[126] ;
+ wire \la_data_in_mprj[127] ;
+ wire \la_data_in_mprj[12] ;
+ wire \la_data_in_mprj[13] ;
+ wire \la_data_in_mprj[14] ;
+ wire \la_data_in_mprj[15] ;
+ wire \la_data_in_mprj[16] ;
+ wire \la_data_in_mprj[17] ;
+ wire \la_data_in_mprj[18] ;
+ wire \la_data_in_mprj[19] ;
+ wire \la_data_in_mprj[1] ;
+ wire \la_data_in_mprj[20] ;
+ wire \la_data_in_mprj[21] ;
+ wire \la_data_in_mprj[22] ;
+ wire \la_data_in_mprj[23] ;
+ wire \la_data_in_mprj[24] ;
+ wire \la_data_in_mprj[25] ;
+ wire \la_data_in_mprj[26] ;
+ wire \la_data_in_mprj[27] ;
+ wire \la_data_in_mprj[28] ;
+ wire \la_data_in_mprj[29] ;
+ wire \la_data_in_mprj[2] ;
+ wire \la_data_in_mprj[30] ;
+ wire \la_data_in_mprj[31] ;
+ wire \la_data_in_mprj[32] ;
+ wire \la_data_in_mprj[33] ;
+ wire \la_data_in_mprj[34] ;
+ wire \la_data_in_mprj[35] ;
+ wire \la_data_in_mprj[36] ;
+ wire \la_data_in_mprj[37] ;
+ wire \la_data_in_mprj[38] ;
+ wire \la_data_in_mprj[39] ;
+ wire \la_data_in_mprj[3] ;
+ wire \la_data_in_mprj[40] ;
+ wire \la_data_in_mprj[41] ;
+ wire \la_data_in_mprj[42] ;
+ wire \la_data_in_mprj[43] ;
+ wire \la_data_in_mprj[44] ;
+ wire \la_data_in_mprj[45] ;
+ wire \la_data_in_mprj[46] ;
+ wire \la_data_in_mprj[47] ;
+ wire \la_data_in_mprj[48] ;
+ wire \la_data_in_mprj[49] ;
+ wire \la_data_in_mprj[4] ;
+ wire \la_data_in_mprj[50] ;
+ wire \la_data_in_mprj[51] ;
+ wire \la_data_in_mprj[52] ;
+ wire \la_data_in_mprj[53] ;
+ wire \la_data_in_mprj[54] ;
+ wire \la_data_in_mprj[55] ;
+ wire \la_data_in_mprj[56] ;
+ wire \la_data_in_mprj[57] ;
+ wire \la_data_in_mprj[58] ;
+ wire \la_data_in_mprj[59] ;
+ wire \la_data_in_mprj[5] ;
+ wire \la_data_in_mprj[60] ;
+ wire \la_data_in_mprj[61] ;
+ wire \la_data_in_mprj[62] ;
+ wire \la_data_in_mprj[63] ;
+ wire \la_data_in_mprj[64] ;
+ wire \la_data_in_mprj[65] ;
+ wire \la_data_in_mprj[66] ;
+ wire \la_data_in_mprj[67] ;
+ wire \la_data_in_mprj[68] ;
+ wire \la_data_in_mprj[69] ;
+ wire \la_data_in_mprj[6] ;
+ wire \la_data_in_mprj[70] ;
+ wire \la_data_in_mprj[71] ;
+ wire \la_data_in_mprj[72] ;
+ wire \la_data_in_mprj[73] ;
+ wire \la_data_in_mprj[74] ;
+ wire \la_data_in_mprj[75] ;
+ wire \la_data_in_mprj[76] ;
+ wire \la_data_in_mprj[77] ;
+ wire \la_data_in_mprj[78] ;
+ wire \la_data_in_mprj[79] ;
+ wire \la_data_in_mprj[7] ;
+ wire \la_data_in_mprj[80] ;
+ wire \la_data_in_mprj[81] ;
+ wire \la_data_in_mprj[82] ;
+ wire \la_data_in_mprj[83] ;
+ wire \la_data_in_mprj[84] ;
+ wire \la_data_in_mprj[85] ;
+ wire \la_data_in_mprj[86] ;
+ wire \la_data_in_mprj[87] ;
+ wire \la_data_in_mprj[88] ;
+ wire \la_data_in_mprj[89] ;
+ wire \la_data_in_mprj[8] ;
+ wire \la_data_in_mprj[90] ;
+ wire \la_data_in_mprj[91] ;
+ wire \la_data_in_mprj[92] ;
+ wire \la_data_in_mprj[93] ;
+ wire \la_data_in_mprj[94] ;
+ wire \la_data_in_mprj[95] ;
+ wire \la_data_in_mprj[96] ;
+ wire \la_data_in_mprj[97] ;
+ wire \la_data_in_mprj[98] ;
+ wire \la_data_in_mprj[99] ;
+ wire \la_data_in_mprj[9] ;
+ wire \la_data_in_user[0] ;
+ wire \la_data_in_user[100] ;
+ wire \la_data_in_user[101] ;
+ wire \la_data_in_user[102] ;
+ wire \la_data_in_user[103] ;
+ wire \la_data_in_user[104] ;
+ wire \la_data_in_user[105] ;
+ wire \la_data_in_user[106] ;
+ wire \la_data_in_user[107] ;
+ wire \la_data_in_user[108] ;
+ wire \la_data_in_user[109] ;
+ wire \la_data_in_user[10] ;
+ wire \la_data_in_user[110] ;
+ wire \la_data_in_user[111] ;
+ wire \la_data_in_user[112] ;
+ wire \la_data_in_user[113] ;
+ wire \la_data_in_user[114] ;
+ wire \la_data_in_user[115] ;
+ wire \la_data_in_user[116] ;
+ wire \la_data_in_user[117] ;
+ wire \la_data_in_user[118] ;
+ wire \la_data_in_user[119] ;
+ wire \la_data_in_user[11] ;
+ wire \la_data_in_user[120] ;
+ wire \la_data_in_user[121] ;
+ wire \la_data_in_user[122] ;
+ wire \la_data_in_user[123] ;
+ wire \la_data_in_user[124] ;
+ wire \la_data_in_user[125] ;
+ wire \la_data_in_user[126] ;
+ wire \la_data_in_user[127] ;
+ wire \la_data_in_user[12] ;
+ wire \la_data_in_user[13] ;
+ wire \la_data_in_user[14] ;
+ wire \la_data_in_user[15] ;
+ wire \la_data_in_user[16] ;
+ wire \la_data_in_user[17] ;
+ wire \la_data_in_user[18] ;
+ wire \la_data_in_user[19] ;
+ wire \la_data_in_user[1] ;
+ wire \la_data_in_user[20] ;
+ wire \la_data_in_user[21] ;
+ wire \la_data_in_user[22] ;
+ wire \la_data_in_user[23] ;
+ wire \la_data_in_user[24] ;
+ wire \la_data_in_user[25] ;
+ wire \la_data_in_user[26] ;
+ wire \la_data_in_user[27] ;
+ wire \la_data_in_user[28] ;
+ wire \la_data_in_user[29] ;
+ wire \la_data_in_user[2] ;
+ wire \la_data_in_user[30] ;
+ wire \la_data_in_user[31] ;
+ wire \la_data_in_user[32] ;
+ wire \la_data_in_user[33] ;
+ wire \la_data_in_user[34] ;
+ wire \la_data_in_user[35] ;
+ wire \la_data_in_user[36] ;
+ wire \la_data_in_user[37] ;
+ wire \la_data_in_user[38] ;
+ wire \la_data_in_user[39] ;
+ wire \la_data_in_user[3] ;
+ wire \la_data_in_user[40] ;
+ wire \la_data_in_user[41] ;
+ wire \la_data_in_user[42] ;
+ wire \la_data_in_user[43] ;
+ wire \la_data_in_user[44] ;
+ wire \la_data_in_user[45] ;
+ wire \la_data_in_user[46] ;
+ wire \la_data_in_user[47] ;
+ wire \la_data_in_user[48] ;
+ wire \la_data_in_user[49] ;
+ wire \la_data_in_user[4] ;
+ wire \la_data_in_user[50] ;
+ wire \la_data_in_user[51] ;
+ wire \la_data_in_user[52] ;
+ wire \la_data_in_user[53] ;
+ wire \la_data_in_user[54] ;
+ wire \la_data_in_user[55] ;
+ wire \la_data_in_user[56] ;
+ wire \la_data_in_user[57] ;
+ wire \la_data_in_user[58] ;
+ wire \la_data_in_user[59] ;
+ wire \la_data_in_user[5] ;
+ wire \la_data_in_user[60] ;
+ wire \la_data_in_user[61] ;
+ wire \la_data_in_user[62] ;
+ wire \la_data_in_user[63] ;
+ wire \la_data_in_user[64] ;
+ wire \la_data_in_user[65] ;
+ wire \la_data_in_user[66] ;
+ wire \la_data_in_user[67] ;
+ wire \la_data_in_user[68] ;
+ wire \la_data_in_user[69] ;
+ wire \la_data_in_user[6] ;
+ wire \la_data_in_user[70] ;
+ wire \la_data_in_user[71] ;
+ wire \la_data_in_user[72] ;
+ wire \la_data_in_user[73] ;
+ wire \la_data_in_user[74] ;
+ wire \la_data_in_user[75] ;
+ wire \la_data_in_user[76] ;
+ wire \la_data_in_user[77] ;
+ wire \la_data_in_user[78] ;
+ wire \la_data_in_user[79] ;
+ wire \la_data_in_user[7] ;
+ wire \la_data_in_user[80] ;
+ wire \la_data_in_user[81] ;
+ wire \la_data_in_user[82] ;
+ wire \la_data_in_user[83] ;
+ wire \la_data_in_user[84] ;
+ wire \la_data_in_user[85] ;
+ wire \la_data_in_user[86] ;
+ wire \la_data_in_user[87] ;
+ wire \la_data_in_user[88] ;
+ wire \la_data_in_user[89] ;
+ wire \la_data_in_user[8] ;
+ wire \la_data_in_user[90] ;
+ wire \la_data_in_user[91] ;
+ wire \la_data_in_user[92] ;
+ wire \la_data_in_user[93] ;
+ wire \la_data_in_user[94] ;
+ wire \la_data_in_user[95] ;
+ wire \la_data_in_user[96] ;
+ wire \la_data_in_user[97] ;
+ wire \la_data_in_user[98] ;
+ wire \la_data_in_user[99] ;
+ wire \la_data_in_user[9] ;
+ wire \la_data_out_mprj[0] ;
+ wire \la_data_out_mprj[100] ;
+ wire \la_data_out_mprj[101] ;
+ wire \la_data_out_mprj[102] ;
+ wire \la_data_out_mprj[103] ;
+ wire \la_data_out_mprj[104] ;
+ wire \la_data_out_mprj[105] ;
+ wire \la_data_out_mprj[106] ;
+ wire \la_data_out_mprj[107] ;
+ wire \la_data_out_mprj[108] ;
+ wire \la_data_out_mprj[109] ;
+ wire \la_data_out_mprj[10] ;
+ wire \la_data_out_mprj[110] ;
+ wire \la_data_out_mprj[111] ;
+ wire \la_data_out_mprj[112] ;
+ wire \la_data_out_mprj[113] ;
+ wire \la_data_out_mprj[114] ;
+ wire \la_data_out_mprj[115] ;
+ wire \la_data_out_mprj[116] ;
+ wire \la_data_out_mprj[117] ;
+ wire \la_data_out_mprj[118] ;
+ wire \la_data_out_mprj[119] ;
+ wire \la_data_out_mprj[11] ;
+ wire \la_data_out_mprj[120] ;
+ wire \la_data_out_mprj[121] ;
+ wire \la_data_out_mprj[122] ;
+ wire \la_data_out_mprj[123] ;
+ wire \la_data_out_mprj[124] ;
+ wire \la_data_out_mprj[125] ;
+ wire \la_data_out_mprj[126] ;
+ wire \la_data_out_mprj[127] ;
+ wire \la_data_out_mprj[12] ;
+ wire \la_data_out_mprj[13] ;
+ wire \la_data_out_mprj[14] ;
+ wire \la_data_out_mprj[15] ;
+ wire \la_data_out_mprj[16] ;
+ wire \la_data_out_mprj[17] ;
+ wire \la_data_out_mprj[18] ;
+ wire \la_data_out_mprj[19] ;
+ wire \la_data_out_mprj[1] ;
+ wire \la_data_out_mprj[20] ;
+ wire \la_data_out_mprj[21] ;
+ wire \la_data_out_mprj[22] ;
+ wire \la_data_out_mprj[23] ;
+ wire \la_data_out_mprj[24] ;
+ wire \la_data_out_mprj[25] ;
+ wire \la_data_out_mprj[26] ;
+ wire \la_data_out_mprj[27] ;
+ wire \la_data_out_mprj[28] ;
+ wire \la_data_out_mprj[29] ;
+ wire \la_data_out_mprj[2] ;
+ wire \la_data_out_mprj[30] ;
+ wire \la_data_out_mprj[31] ;
+ wire \la_data_out_mprj[32] ;
+ wire \la_data_out_mprj[33] ;
+ wire \la_data_out_mprj[34] ;
+ wire \la_data_out_mprj[35] ;
+ wire \la_data_out_mprj[36] ;
+ wire \la_data_out_mprj[37] ;
+ wire \la_data_out_mprj[38] ;
+ wire \la_data_out_mprj[39] ;
+ wire \la_data_out_mprj[3] ;
+ wire \la_data_out_mprj[40] ;
+ wire \la_data_out_mprj[41] ;
+ wire \la_data_out_mprj[42] ;
+ wire \la_data_out_mprj[43] ;
+ wire \la_data_out_mprj[44] ;
+ wire \la_data_out_mprj[45] ;
+ wire \la_data_out_mprj[46] ;
+ wire \la_data_out_mprj[47] ;
+ wire \la_data_out_mprj[48] ;
+ wire \la_data_out_mprj[49] ;
+ wire \la_data_out_mprj[4] ;
+ wire \la_data_out_mprj[50] ;
+ wire \la_data_out_mprj[51] ;
+ wire \la_data_out_mprj[52] ;
+ wire \la_data_out_mprj[53] ;
+ wire \la_data_out_mprj[54] ;
+ wire \la_data_out_mprj[55] ;
+ wire \la_data_out_mprj[56] ;
+ wire \la_data_out_mprj[57] ;
+ wire \la_data_out_mprj[58] ;
+ wire \la_data_out_mprj[59] ;
+ wire \la_data_out_mprj[5] ;
+ wire \la_data_out_mprj[60] ;
+ wire \la_data_out_mprj[61] ;
+ wire \la_data_out_mprj[62] ;
+ wire \la_data_out_mprj[63] ;
+ wire \la_data_out_mprj[64] ;
+ wire \la_data_out_mprj[65] ;
+ wire \la_data_out_mprj[66] ;
+ wire \la_data_out_mprj[67] ;
+ wire \la_data_out_mprj[68] ;
+ wire \la_data_out_mprj[69] ;
+ wire \la_data_out_mprj[6] ;
+ wire \la_data_out_mprj[70] ;
+ wire \la_data_out_mprj[71] ;
+ wire \la_data_out_mprj[72] ;
+ wire \la_data_out_mprj[73] ;
+ wire \la_data_out_mprj[74] ;
+ wire \la_data_out_mprj[75] ;
+ wire \la_data_out_mprj[76] ;
+ wire \la_data_out_mprj[77] ;
+ wire \la_data_out_mprj[78] ;
+ wire \la_data_out_mprj[79] ;
+ wire \la_data_out_mprj[7] ;
+ wire \la_data_out_mprj[80] ;
+ wire \la_data_out_mprj[81] ;
+ wire \la_data_out_mprj[82] ;
+ wire \la_data_out_mprj[83] ;
+ wire \la_data_out_mprj[84] ;
+ wire \la_data_out_mprj[85] ;
+ wire \la_data_out_mprj[86] ;
+ wire \la_data_out_mprj[87] ;
+ wire \la_data_out_mprj[88] ;
+ wire \la_data_out_mprj[89] ;
+ wire \la_data_out_mprj[8] ;
+ wire \la_data_out_mprj[90] ;
+ wire \la_data_out_mprj[91] ;
+ wire \la_data_out_mprj[92] ;
+ wire \la_data_out_mprj[93] ;
+ wire \la_data_out_mprj[94] ;
+ wire \la_data_out_mprj[95] ;
+ wire \la_data_out_mprj[96] ;
+ wire \la_data_out_mprj[97] ;
+ wire \la_data_out_mprj[98] ;
+ wire \la_data_out_mprj[99] ;
+ wire \la_data_out_mprj[9] ;
+ wire \la_data_out_user[0] ;
+ wire \la_data_out_user[100] ;
+ wire \la_data_out_user[101] ;
+ wire \la_data_out_user[102] ;
+ wire \la_data_out_user[103] ;
+ wire \la_data_out_user[104] ;
+ wire \la_data_out_user[105] ;
+ wire \la_data_out_user[106] ;
+ wire \la_data_out_user[107] ;
+ wire \la_data_out_user[108] ;
+ wire \la_data_out_user[109] ;
+ wire \la_data_out_user[10] ;
+ wire \la_data_out_user[110] ;
+ wire \la_data_out_user[111] ;
+ wire \la_data_out_user[112] ;
+ wire \la_data_out_user[113] ;
+ wire \la_data_out_user[114] ;
+ wire \la_data_out_user[115] ;
+ wire \la_data_out_user[116] ;
+ wire \la_data_out_user[117] ;
+ wire \la_data_out_user[118] ;
+ wire \la_data_out_user[119] ;
+ wire \la_data_out_user[11] ;
+ wire \la_data_out_user[120] ;
+ wire \la_data_out_user[121] ;
+ wire \la_data_out_user[122] ;
+ wire \la_data_out_user[123] ;
+ wire \la_data_out_user[124] ;
+ wire \la_data_out_user[125] ;
+ wire \la_data_out_user[126] ;
+ wire \la_data_out_user[127] ;
+ wire \la_data_out_user[12] ;
+ wire \la_data_out_user[13] ;
+ wire \la_data_out_user[14] ;
+ wire \la_data_out_user[15] ;
+ wire \la_data_out_user[16] ;
+ wire \la_data_out_user[17] ;
+ wire \la_data_out_user[18] ;
+ wire \la_data_out_user[19] ;
+ wire \la_data_out_user[1] ;
+ wire \la_data_out_user[20] ;
+ wire \la_data_out_user[21] ;
+ wire \la_data_out_user[22] ;
+ wire \la_data_out_user[23] ;
+ wire \la_data_out_user[24] ;
+ wire \la_data_out_user[25] ;
+ wire \la_data_out_user[26] ;
+ wire \la_data_out_user[27] ;
+ wire \la_data_out_user[28] ;
+ wire \la_data_out_user[29] ;
+ wire \la_data_out_user[2] ;
+ wire \la_data_out_user[30] ;
+ wire \la_data_out_user[31] ;
+ wire \la_data_out_user[32] ;
+ wire \la_data_out_user[33] ;
+ wire \la_data_out_user[34] ;
+ wire \la_data_out_user[35] ;
+ wire \la_data_out_user[36] ;
+ wire \la_data_out_user[37] ;
+ wire \la_data_out_user[38] ;
+ wire \la_data_out_user[39] ;
+ wire \la_data_out_user[3] ;
+ wire \la_data_out_user[40] ;
+ wire \la_data_out_user[41] ;
+ wire \la_data_out_user[42] ;
+ wire \la_data_out_user[43] ;
+ wire \la_data_out_user[44] ;
+ wire \la_data_out_user[45] ;
+ wire \la_data_out_user[46] ;
+ wire \la_data_out_user[47] ;
+ wire \la_data_out_user[48] ;
+ wire \la_data_out_user[49] ;
+ wire \la_data_out_user[4] ;
+ wire \la_data_out_user[50] ;
+ wire \la_data_out_user[51] ;
+ wire \la_data_out_user[52] ;
+ wire \la_data_out_user[53] ;
+ wire \la_data_out_user[54] ;
+ wire \la_data_out_user[55] ;
+ wire \la_data_out_user[56] ;
+ wire \la_data_out_user[57] ;
+ wire \la_data_out_user[58] ;
+ wire \la_data_out_user[59] ;
+ wire \la_data_out_user[5] ;
+ wire \la_data_out_user[60] ;
+ wire \la_data_out_user[61] ;
+ wire \la_data_out_user[62] ;
+ wire \la_data_out_user[63] ;
+ wire \la_data_out_user[64] ;
+ wire \la_data_out_user[65] ;
+ wire \la_data_out_user[66] ;
+ wire \la_data_out_user[67] ;
+ wire \la_data_out_user[68] ;
+ wire \la_data_out_user[69] ;
+ wire \la_data_out_user[6] ;
+ wire \la_data_out_user[70] ;
+ wire \la_data_out_user[71] ;
+ wire \la_data_out_user[72] ;
+ wire \la_data_out_user[73] ;
+ wire \la_data_out_user[74] ;
+ wire \la_data_out_user[75] ;
+ wire \la_data_out_user[76] ;
+ wire \la_data_out_user[77] ;
+ wire \la_data_out_user[78] ;
+ wire \la_data_out_user[79] ;
+ wire \la_data_out_user[7] ;
+ wire \la_data_out_user[80] ;
+ wire \la_data_out_user[81] ;
+ wire \la_data_out_user[82] ;
+ wire \la_data_out_user[83] ;
+ wire \la_data_out_user[84] ;
+ wire \la_data_out_user[85] ;
+ wire \la_data_out_user[86] ;
+ wire \la_data_out_user[87] ;
+ wire \la_data_out_user[88] ;
+ wire \la_data_out_user[89] ;
+ wire \la_data_out_user[8] ;
+ wire \la_data_out_user[90] ;
+ wire \la_data_out_user[91] ;
+ wire \la_data_out_user[92] ;
+ wire \la_data_out_user[93] ;
+ wire \la_data_out_user[94] ;
+ wire \la_data_out_user[95] ;
+ wire \la_data_out_user[96] ;
+ wire \la_data_out_user[97] ;
+ wire \la_data_out_user[98] ;
+ wire \la_data_out_user[99] ;
+ wire \la_data_out_user[9] ;
+ wire \la_iena_mprj[0] ;
+ wire \la_iena_mprj[100] ;
+ wire \la_iena_mprj[101] ;
+ wire \la_iena_mprj[102] ;
+ wire \la_iena_mprj[103] ;
+ wire \la_iena_mprj[104] ;
+ wire \la_iena_mprj[105] ;
+ wire \la_iena_mprj[106] ;
+ wire \la_iena_mprj[107] ;
+ wire \la_iena_mprj[108] ;
+ wire \la_iena_mprj[109] ;
+ wire \la_iena_mprj[10] ;
+ wire \la_iena_mprj[110] ;
+ wire \la_iena_mprj[111] ;
+ wire \la_iena_mprj[112] ;
+ wire \la_iena_mprj[113] ;
+ wire \la_iena_mprj[114] ;
+ wire \la_iena_mprj[115] ;
+ wire \la_iena_mprj[116] ;
+ wire \la_iena_mprj[117] ;
+ wire \la_iena_mprj[118] ;
+ wire \la_iena_mprj[119] ;
+ wire \la_iena_mprj[11] ;
+ wire \la_iena_mprj[120] ;
+ wire \la_iena_mprj[121] ;
+ wire \la_iena_mprj[122] ;
+ wire \la_iena_mprj[123] ;
+ wire \la_iena_mprj[124] ;
+ wire \la_iena_mprj[125] ;
+ wire \la_iena_mprj[126] ;
+ wire \la_iena_mprj[127] ;
+ wire \la_iena_mprj[12] ;
+ wire \la_iena_mprj[13] ;
+ wire \la_iena_mprj[14] ;
+ wire \la_iena_mprj[15] ;
+ wire \la_iena_mprj[16] ;
+ wire \la_iena_mprj[17] ;
+ wire \la_iena_mprj[18] ;
+ wire \la_iena_mprj[19] ;
+ wire \la_iena_mprj[1] ;
+ wire \la_iena_mprj[20] ;
+ wire \la_iena_mprj[21] ;
+ wire \la_iena_mprj[22] ;
+ wire \la_iena_mprj[23] ;
+ wire \la_iena_mprj[24] ;
+ wire \la_iena_mprj[25] ;
+ wire \la_iena_mprj[26] ;
+ wire \la_iena_mprj[27] ;
+ wire \la_iena_mprj[28] ;
+ wire \la_iena_mprj[29] ;
+ wire \la_iena_mprj[2] ;
+ wire \la_iena_mprj[30] ;
+ wire \la_iena_mprj[31] ;
+ wire \la_iena_mprj[32] ;
+ wire \la_iena_mprj[33] ;
+ wire \la_iena_mprj[34] ;
+ wire \la_iena_mprj[35] ;
+ wire \la_iena_mprj[36] ;
+ wire \la_iena_mprj[37] ;
+ wire \la_iena_mprj[38] ;
+ wire \la_iena_mprj[39] ;
+ wire \la_iena_mprj[3] ;
+ wire \la_iena_mprj[40] ;
+ wire \la_iena_mprj[41] ;
+ wire \la_iena_mprj[42] ;
+ wire \la_iena_mprj[43] ;
+ wire \la_iena_mprj[44] ;
+ wire \la_iena_mprj[45] ;
+ wire \la_iena_mprj[46] ;
+ wire \la_iena_mprj[47] ;
+ wire \la_iena_mprj[48] ;
+ wire \la_iena_mprj[49] ;
+ wire \la_iena_mprj[4] ;
+ wire \la_iena_mprj[50] ;
+ wire \la_iena_mprj[51] ;
+ wire \la_iena_mprj[52] ;
+ wire \la_iena_mprj[53] ;
+ wire \la_iena_mprj[54] ;
+ wire \la_iena_mprj[55] ;
+ wire \la_iena_mprj[56] ;
+ wire \la_iena_mprj[57] ;
+ wire \la_iena_mprj[58] ;
+ wire \la_iena_mprj[59] ;
+ wire \la_iena_mprj[5] ;
+ wire \la_iena_mprj[60] ;
+ wire \la_iena_mprj[61] ;
+ wire \la_iena_mprj[62] ;
+ wire \la_iena_mprj[63] ;
+ wire \la_iena_mprj[64] ;
+ wire \la_iena_mprj[65] ;
+ wire \la_iena_mprj[66] ;
+ wire \la_iena_mprj[67] ;
+ wire \la_iena_mprj[68] ;
+ wire \la_iena_mprj[69] ;
+ wire \la_iena_mprj[6] ;
+ wire \la_iena_mprj[70] ;
+ wire \la_iena_mprj[71] ;
+ wire \la_iena_mprj[72] ;
+ wire \la_iena_mprj[73] ;
+ wire \la_iena_mprj[74] ;
+ wire \la_iena_mprj[75] ;
+ wire \la_iena_mprj[76] ;
+ wire \la_iena_mprj[77] ;
+ wire \la_iena_mprj[78] ;
+ wire \la_iena_mprj[79] ;
+ wire \la_iena_mprj[7] ;
+ wire \la_iena_mprj[80] ;
+ wire \la_iena_mprj[81] ;
+ wire \la_iena_mprj[82] ;
+ wire \la_iena_mprj[83] ;
+ wire \la_iena_mprj[84] ;
+ wire \la_iena_mprj[85] ;
+ wire \la_iena_mprj[86] ;
+ wire \la_iena_mprj[87] ;
+ wire \la_iena_mprj[88] ;
+ wire \la_iena_mprj[89] ;
+ wire \la_iena_mprj[8] ;
+ wire \la_iena_mprj[90] ;
+ wire \la_iena_mprj[91] ;
+ wire \la_iena_mprj[92] ;
+ wire \la_iena_mprj[93] ;
+ wire \la_iena_mprj[94] ;
+ wire \la_iena_mprj[95] ;
+ wire \la_iena_mprj[96] ;
+ wire \la_iena_mprj[97] ;
+ wire \la_iena_mprj[98] ;
+ wire \la_iena_mprj[99] ;
+ wire \la_iena_mprj[9] ;
+ wire \la_oenb_mprj[0] ;
+ wire \la_oenb_mprj[100] ;
+ wire \la_oenb_mprj[101] ;
+ wire \la_oenb_mprj[102] ;
+ wire \la_oenb_mprj[103] ;
+ wire \la_oenb_mprj[104] ;
+ wire \la_oenb_mprj[105] ;
+ wire \la_oenb_mprj[106] ;
+ wire \la_oenb_mprj[107] ;
+ wire \la_oenb_mprj[108] ;
+ wire \la_oenb_mprj[109] ;
+ wire \la_oenb_mprj[10] ;
+ wire \la_oenb_mprj[110] ;
+ wire \la_oenb_mprj[111] ;
+ wire \la_oenb_mprj[112] ;
+ wire \la_oenb_mprj[113] ;
+ wire \la_oenb_mprj[114] ;
+ wire \la_oenb_mprj[115] ;
+ wire \la_oenb_mprj[116] ;
+ wire \la_oenb_mprj[117] ;
+ wire \la_oenb_mprj[118] ;
+ wire \la_oenb_mprj[119] ;
+ wire \la_oenb_mprj[11] ;
+ wire \la_oenb_mprj[120] ;
+ wire \la_oenb_mprj[121] ;
+ wire \la_oenb_mprj[122] ;
+ wire \la_oenb_mprj[123] ;
+ wire \la_oenb_mprj[124] ;
+ wire \la_oenb_mprj[125] ;
+ wire \la_oenb_mprj[126] ;
+ wire \la_oenb_mprj[127] ;
+ wire \la_oenb_mprj[12] ;
+ wire \la_oenb_mprj[13] ;
+ wire \la_oenb_mprj[14] ;
+ wire \la_oenb_mprj[15] ;
+ wire \la_oenb_mprj[16] ;
+ wire \la_oenb_mprj[17] ;
+ wire \la_oenb_mprj[18] ;
+ wire \la_oenb_mprj[19] ;
+ wire \la_oenb_mprj[1] ;
+ wire \la_oenb_mprj[20] ;
+ wire \la_oenb_mprj[21] ;
+ wire \la_oenb_mprj[22] ;
+ wire \la_oenb_mprj[23] ;
+ wire \la_oenb_mprj[24] ;
+ wire \la_oenb_mprj[25] ;
+ wire \la_oenb_mprj[26] ;
+ wire \la_oenb_mprj[27] ;
+ wire \la_oenb_mprj[28] ;
+ wire \la_oenb_mprj[29] ;
+ wire \la_oenb_mprj[2] ;
+ wire \la_oenb_mprj[30] ;
+ wire \la_oenb_mprj[31] ;
+ wire \la_oenb_mprj[32] ;
+ wire \la_oenb_mprj[33] ;
+ wire \la_oenb_mprj[34] ;
+ wire \la_oenb_mprj[35] ;
+ wire \la_oenb_mprj[36] ;
+ wire \la_oenb_mprj[37] ;
+ wire \la_oenb_mprj[38] ;
+ wire \la_oenb_mprj[39] ;
+ wire \la_oenb_mprj[3] ;
+ wire \la_oenb_mprj[40] ;
+ wire \la_oenb_mprj[41] ;
+ wire \la_oenb_mprj[42] ;
+ wire \la_oenb_mprj[43] ;
+ wire \la_oenb_mprj[44] ;
+ wire \la_oenb_mprj[45] ;
+ wire \la_oenb_mprj[46] ;
+ wire \la_oenb_mprj[47] ;
+ wire \la_oenb_mprj[48] ;
+ wire \la_oenb_mprj[49] ;
+ wire \la_oenb_mprj[4] ;
+ wire \la_oenb_mprj[50] ;
+ wire \la_oenb_mprj[51] ;
+ wire \la_oenb_mprj[52] ;
+ wire \la_oenb_mprj[53] ;
+ wire \la_oenb_mprj[54] ;
+ wire \la_oenb_mprj[55] ;
+ wire \la_oenb_mprj[56] ;
+ wire \la_oenb_mprj[57] ;
+ wire \la_oenb_mprj[58] ;
+ wire \la_oenb_mprj[59] ;
+ wire \la_oenb_mprj[5] ;
+ wire \la_oenb_mprj[60] ;
+ wire \la_oenb_mprj[61] ;
+ wire \la_oenb_mprj[62] ;
+ wire \la_oenb_mprj[63] ;
+ wire \la_oenb_mprj[64] ;
+ wire \la_oenb_mprj[65] ;
+ wire \la_oenb_mprj[66] ;
+ wire \la_oenb_mprj[67] ;
+ wire \la_oenb_mprj[68] ;
+ wire \la_oenb_mprj[69] ;
+ wire \la_oenb_mprj[6] ;
+ wire \la_oenb_mprj[70] ;
+ wire \la_oenb_mprj[71] ;
+ wire \la_oenb_mprj[72] ;
+ wire \la_oenb_mprj[73] ;
+ wire \la_oenb_mprj[74] ;
+ wire \la_oenb_mprj[75] ;
+ wire \la_oenb_mprj[76] ;
+ wire \la_oenb_mprj[77] ;
+ wire \la_oenb_mprj[78] ;
+ wire \la_oenb_mprj[79] ;
+ wire \la_oenb_mprj[7] ;
+ wire \la_oenb_mprj[80] ;
+ wire \la_oenb_mprj[81] ;
+ wire \la_oenb_mprj[82] ;
+ wire \la_oenb_mprj[83] ;
+ wire \la_oenb_mprj[84] ;
+ wire \la_oenb_mprj[85] ;
+ wire \la_oenb_mprj[86] ;
+ wire \la_oenb_mprj[87] ;
+ wire \la_oenb_mprj[88] ;
+ wire \la_oenb_mprj[89] ;
+ wire \la_oenb_mprj[8] ;
+ wire \la_oenb_mprj[90] ;
+ wire \la_oenb_mprj[91] ;
+ wire \la_oenb_mprj[92] ;
+ wire \la_oenb_mprj[93] ;
+ wire \la_oenb_mprj[94] ;
+ wire \la_oenb_mprj[95] ;
+ wire \la_oenb_mprj[96] ;
+ wire \la_oenb_mprj[97] ;
+ wire \la_oenb_mprj[98] ;
+ wire \la_oenb_mprj[99] ;
+ wire \la_oenb_mprj[9] ;
+ wire \la_oenb_user[0] ;
+ wire \la_oenb_user[100] ;
+ wire \la_oenb_user[101] ;
+ wire \la_oenb_user[102] ;
+ wire \la_oenb_user[103] ;
+ wire \la_oenb_user[104] ;
+ wire \la_oenb_user[105] ;
+ wire \la_oenb_user[106] ;
+ wire \la_oenb_user[107] ;
+ wire \la_oenb_user[108] ;
+ wire \la_oenb_user[109] ;
+ wire \la_oenb_user[10] ;
+ wire \la_oenb_user[110] ;
+ wire \la_oenb_user[111] ;
+ wire \la_oenb_user[112] ;
+ wire \la_oenb_user[113] ;
+ wire \la_oenb_user[114] ;
+ wire \la_oenb_user[115] ;
+ wire \la_oenb_user[116] ;
+ wire \la_oenb_user[117] ;
+ wire \la_oenb_user[118] ;
+ wire \la_oenb_user[119] ;
+ wire \la_oenb_user[11] ;
+ wire \la_oenb_user[120] ;
+ wire \la_oenb_user[121] ;
+ wire \la_oenb_user[122] ;
+ wire \la_oenb_user[123] ;
+ wire \la_oenb_user[124] ;
+ wire \la_oenb_user[125] ;
+ wire \la_oenb_user[126] ;
+ wire \la_oenb_user[127] ;
+ wire \la_oenb_user[12] ;
+ wire \la_oenb_user[13] ;
+ wire \la_oenb_user[14] ;
+ wire \la_oenb_user[15] ;
+ wire \la_oenb_user[16] ;
+ wire \la_oenb_user[17] ;
+ wire \la_oenb_user[18] ;
+ wire \la_oenb_user[19] ;
+ wire \la_oenb_user[1] ;
+ wire \la_oenb_user[20] ;
+ wire \la_oenb_user[21] ;
+ wire \la_oenb_user[22] ;
+ wire \la_oenb_user[23] ;
+ wire \la_oenb_user[24] ;
+ wire \la_oenb_user[25] ;
+ wire \la_oenb_user[26] ;
+ wire \la_oenb_user[27] ;
+ wire \la_oenb_user[28] ;
+ wire \la_oenb_user[29] ;
+ wire \la_oenb_user[2] ;
+ wire \la_oenb_user[30] ;
+ wire \la_oenb_user[31] ;
+ wire \la_oenb_user[32] ;
+ wire \la_oenb_user[33] ;
+ wire \la_oenb_user[34] ;
+ wire \la_oenb_user[35] ;
+ wire \la_oenb_user[36] ;
+ wire \la_oenb_user[37] ;
+ wire \la_oenb_user[38] ;
+ wire \la_oenb_user[39] ;
+ wire \la_oenb_user[3] ;
+ wire \la_oenb_user[40] ;
+ wire \la_oenb_user[41] ;
+ wire \la_oenb_user[42] ;
+ wire \la_oenb_user[43] ;
+ wire \la_oenb_user[44] ;
+ wire \la_oenb_user[45] ;
+ wire \la_oenb_user[46] ;
+ wire \la_oenb_user[47] ;
+ wire \la_oenb_user[48] ;
+ wire \la_oenb_user[49] ;
+ wire \la_oenb_user[4] ;
+ wire \la_oenb_user[50] ;
+ wire \la_oenb_user[51] ;
+ wire \la_oenb_user[52] ;
+ wire \la_oenb_user[53] ;
+ wire \la_oenb_user[54] ;
+ wire \la_oenb_user[55] ;
+ wire \la_oenb_user[56] ;
+ wire \la_oenb_user[57] ;
+ wire \la_oenb_user[58] ;
+ wire \la_oenb_user[59] ;
+ wire \la_oenb_user[5] ;
+ wire \la_oenb_user[60] ;
+ wire \la_oenb_user[61] ;
+ wire \la_oenb_user[62] ;
+ wire \la_oenb_user[63] ;
+ wire \la_oenb_user[64] ;
+ wire \la_oenb_user[65] ;
+ wire \la_oenb_user[66] ;
+ wire \la_oenb_user[67] ;
+ wire \la_oenb_user[68] ;
+ wire \la_oenb_user[69] ;
+ wire \la_oenb_user[6] ;
+ wire \la_oenb_user[70] ;
+ wire \la_oenb_user[71] ;
+ wire \la_oenb_user[72] ;
+ wire \la_oenb_user[73] ;
+ wire \la_oenb_user[74] ;
+ wire \la_oenb_user[75] ;
+ wire \la_oenb_user[76] ;
+ wire \la_oenb_user[77] ;
+ wire \la_oenb_user[78] ;
+ wire \la_oenb_user[79] ;
+ wire \la_oenb_user[7] ;
+ wire \la_oenb_user[80] ;
+ wire \la_oenb_user[81] ;
+ wire \la_oenb_user[82] ;
+ wire \la_oenb_user[83] ;
+ wire \la_oenb_user[84] ;
+ wire \la_oenb_user[85] ;
+ wire \la_oenb_user[86] ;
+ wire \la_oenb_user[87] ;
+ wire \la_oenb_user[88] ;
+ wire \la_oenb_user[89] ;
+ wire \la_oenb_user[8] ;
+ wire \la_oenb_user[90] ;
+ wire \la_oenb_user[91] ;
+ wire \la_oenb_user[92] ;
+ wire \la_oenb_user[93] ;
+ wire \la_oenb_user[94] ;
+ wire \la_oenb_user[95] ;
+ wire \la_oenb_user[96] ;
+ wire \la_oenb_user[97] ;
+ wire \la_oenb_user[98] ;
+ wire \la_oenb_user[99] ;
+ wire \la_oenb_user[9] ;
+ wire \mask_rev[0] ;
+ wire \mask_rev[10] ;
+ wire \mask_rev[11] ;
+ wire \mask_rev[12] ;
+ wire \mask_rev[13] ;
+ wire \mask_rev[14] ;
+ wire \mask_rev[15] ;
+ wire \mask_rev[16] ;
+ wire \mask_rev[17] ;
+ wire \mask_rev[18] ;
+ wire \mask_rev[19] ;
+ wire \mask_rev[1] ;
+ wire \mask_rev[20] ;
+ wire \mask_rev[21] ;
+ wire \mask_rev[22] ;
+ wire \mask_rev[23] ;
+ wire \mask_rev[24] ;
+ wire \mask_rev[25] ;
+ wire \mask_rev[26] ;
+ wire \mask_rev[27] ;
+ wire \mask_rev[28] ;
+ wire \mask_rev[29] ;
+ wire \mask_rev[2] ;
+ wire \mask_rev[30] ;
+ wire \mask_rev[31] ;
+ wire \mask_rev[3] ;
+ wire \mask_rev[4] ;
+ wire \mask_rev[5] ;
+ wire \mask_rev[6] ;
+ wire \mask_rev[7] ;
+ wire \mask_rev[8] ;
+ wire \mask_rev[9] ;
+ wire \mgmt_io_in[0] ;
+ wire \mgmt_io_in[10] ;
+ wire \mgmt_io_in[11] ;
+ wire \mgmt_io_in[12] ;
+ wire \mgmt_io_in[13] ;
+ wire \mgmt_io_in[14] ;
+ wire \mgmt_io_in[15] ;
+ wire \mgmt_io_in[16] ;
+ wire \mgmt_io_in[17] ;
+ wire \mgmt_io_in[18] ;
+ wire \mgmt_io_in[19] ;
+ wire \mgmt_io_in[1] ;
+ wire \mgmt_io_in[20] ;
+ wire \mgmt_io_in[21] ;
+ wire \mgmt_io_in[22] ;
+ wire \mgmt_io_in[23] ;
+ wire \mgmt_io_in[24] ;
+ wire \mgmt_io_in[25] ;
+ wire \mgmt_io_in[26] ;
+ wire \mgmt_io_in[27] ;
+ wire \mgmt_io_in[28] ;
+ wire \mgmt_io_in[29] ;
+ wire \mgmt_io_in[2] ;
+ wire \mgmt_io_in[30] ;
+ wire \mgmt_io_in[31] ;
+ wire \mgmt_io_in[32] ;
+ wire \mgmt_io_in[33] ;
+ wire \mgmt_io_in[34] ;
+ wire \mgmt_io_in[35] ;
+ wire \mgmt_io_in[36] ;
+ wire \mgmt_io_in[37] ;
+ wire \mgmt_io_in[3] ;
+ wire \mgmt_io_in[4] ;
+ wire \mgmt_io_in[5] ;
+ wire \mgmt_io_in[6] ;
+ wire \mgmt_io_in[7] ;
+ wire \mgmt_io_in[8] ;
+ wire \mgmt_io_in[9] ;
+ wire \mgmt_io_nc[0] ;
+ wire \mgmt_io_nc[10] ;
+ wire \mgmt_io_nc[11] ;
+ wire \mgmt_io_nc[12] ;
+ wire \mgmt_io_nc[13] ;
+ wire \mgmt_io_nc[14] ;
+ wire \mgmt_io_nc[15] ;
+ wire \mgmt_io_nc[16] ;
+ wire \mgmt_io_nc[17] ;
+ wire \mgmt_io_nc[18] ;
+ wire \mgmt_io_nc[19] ;
+ wire \mgmt_io_nc[1] ;
+ wire \mgmt_io_nc[20] ;
+ wire \mgmt_io_nc[21] ;
+ wire \mgmt_io_nc[22] ;
+ wire \mgmt_io_nc[23] ;
+ wire \mgmt_io_nc[24] ;
+ wire \mgmt_io_nc[25] ;
+ wire \mgmt_io_nc[26] ;
+ wire \mgmt_io_nc[27] ;
+ wire \mgmt_io_nc[28] ;
+ wire \mgmt_io_nc[29] ;
+ wire \mgmt_io_nc[2] ;
+ wire \mgmt_io_nc[30] ;
+ wire \mgmt_io_nc[31] ;
+ wire \mgmt_io_nc[32] ;
+ wire \mgmt_io_nc[33] ;
+ wire \mgmt_io_nc[3] ;
+ wire \mgmt_io_nc[4] ;
+ wire \mgmt_io_nc[5] ;
+ wire \mgmt_io_nc[6] ;
+ wire \mgmt_io_nc[7] ;
+ wire \mgmt_io_nc[8] ;
+ wire \mgmt_io_nc[9] ;
+ wire \mgmt_io_oeb[0] ;
+ wire \mgmt_io_oeb[1] ;
+ wire \mgmt_io_oeb[2] ;
+ wire \mgmt_io_oeb[3] ;
+ wire \mgmt_io_oeb[4] ;
+ wire \mgmt_io_out[0] ;
+ wire \mgmt_io_out[1] ;
+ wire \mgmt_io_out[2] ;
+ wire \mgmt_io_out[3] ;
+ wire \mgmt_io_out[4] ;
+ wire mprj2_vcc_pwrgood;
+ wire mprj2_vdd_pwrgood;
+ wire mprj_ack_i_core;
+ wire mprj_ack_i_user;
+ wire \mprj_adr_o_core[0] ;
+ wire \mprj_adr_o_core[10] ;
+ wire \mprj_adr_o_core[11] ;
+ wire \mprj_adr_o_core[12] ;
+ wire \mprj_adr_o_core[13] ;
+ wire \mprj_adr_o_core[14] ;
+ wire \mprj_adr_o_core[15] ;
+ wire \mprj_adr_o_core[16] ;
+ wire \mprj_adr_o_core[17] ;
+ wire \mprj_adr_o_core[18] ;
+ wire \mprj_adr_o_core[19] ;
+ wire \mprj_adr_o_core[1] ;
+ wire \mprj_adr_o_core[20] ;
+ wire \mprj_adr_o_core[21] ;
+ wire \mprj_adr_o_core[22] ;
+ wire \mprj_adr_o_core[23] ;
+ wire \mprj_adr_o_core[24] ;
+ wire \mprj_adr_o_core[25] ;
+ wire \mprj_adr_o_core[26] ;
+ wire \mprj_adr_o_core[27] ;
+ wire \mprj_adr_o_core[28] ;
+ wire \mprj_adr_o_core[29] ;
+ wire \mprj_adr_o_core[2] ;
+ wire \mprj_adr_o_core[30] ;
+ wire \mprj_adr_o_core[31] ;
+ wire \mprj_adr_o_core[3] ;
+ wire \mprj_adr_o_core[4] ;
+ wire \mprj_adr_o_core[5] ;
+ wire \mprj_adr_o_core[6] ;
+ wire \mprj_adr_o_core[7] ;
+ wire \mprj_adr_o_core[8] ;
+ wire \mprj_adr_o_core[9] ;
+ wire \mprj_adr_o_user[0] ;
+ wire \mprj_adr_o_user[10] ;
+ wire \mprj_adr_o_user[11] ;
+ wire \mprj_adr_o_user[12] ;
+ wire \mprj_adr_o_user[13] ;
+ wire \mprj_adr_o_user[14] ;
+ wire \mprj_adr_o_user[15] ;
+ wire \mprj_adr_o_user[16] ;
+ wire \mprj_adr_o_user[17] ;
+ wire \mprj_adr_o_user[18] ;
+ wire \mprj_adr_o_user[19] ;
+ wire \mprj_adr_o_user[1] ;
+ wire \mprj_adr_o_user[20] ;
+ wire \mprj_adr_o_user[21] ;
+ wire \mprj_adr_o_user[22] ;
+ wire \mprj_adr_o_user[23] ;
+ wire \mprj_adr_o_user[24] ;
+ wire \mprj_adr_o_user[25] ;
+ wire \mprj_adr_o_user[26] ;
+ wire \mprj_adr_o_user[27] ;
+ wire \mprj_adr_o_user[28] ;
+ wire \mprj_adr_o_user[29] ;
+ wire \mprj_adr_o_user[2] ;
+ wire \mprj_adr_o_user[30] ;
+ wire \mprj_adr_o_user[31] ;
+ wire \mprj_adr_o_user[3] ;
+ wire \mprj_adr_o_user[4] ;
+ wire \mprj_adr_o_user[5] ;
+ wire \mprj_adr_o_user[6] ;
+ wire \mprj_adr_o_user[7] ;
+ wire \mprj_adr_o_user[8] ;
+ wire \mprj_adr_o_user[9] ;
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_cyc_o_core;
+ wire mprj_cyc_o_user;
+ wire \mprj_dat_i_core[0] ;
+ wire \mprj_dat_i_core[10] ;
+ wire \mprj_dat_i_core[11] ;
+ wire \mprj_dat_i_core[12] ;
+ wire \mprj_dat_i_core[13] ;
+ wire \mprj_dat_i_core[14] ;
+ wire \mprj_dat_i_core[15] ;
+ wire \mprj_dat_i_core[16] ;
+ wire \mprj_dat_i_core[17] ;
+ wire \mprj_dat_i_core[18] ;
+ wire \mprj_dat_i_core[19] ;
+ wire \mprj_dat_i_core[1] ;
+ wire \mprj_dat_i_core[20] ;
+ wire \mprj_dat_i_core[21] ;
+ wire \mprj_dat_i_core[22] ;
+ wire \mprj_dat_i_core[23] ;
+ wire \mprj_dat_i_core[24] ;
+ wire \mprj_dat_i_core[25] ;
+ wire \mprj_dat_i_core[26] ;
+ wire \mprj_dat_i_core[27] ;
+ wire \mprj_dat_i_core[28] ;
+ wire \mprj_dat_i_core[29] ;
+ wire \mprj_dat_i_core[2] ;
+ wire \mprj_dat_i_core[30] ;
+ wire \mprj_dat_i_core[31] ;
+ wire \mprj_dat_i_core[3] ;
+ wire \mprj_dat_i_core[4] ;
+ wire \mprj_dat_i_core[5] ;
+ wire \mprj_dat_i_core[6] ;
+ wire \mprj_dat_i_core[7] ;
+ wire \mprj_dat_i_core[8] ;
+ wire \mprj_dat_i_core[9] ;
+ wire \mprj_dat_i_user[0] ;
+ wire \mprj_dat_i_user[10] ;
+ wire \mprj_dat_i_user[11] ;
+ wire \mprj_dat_i_user[12] ;
+ wire \mprj_dat_i_user[13] ;
+ wire \mprj_dat_i_user[14] ;
+ wire \mprj_dat_i_user[15] ;
+ wire \mprj_dat_i_user[16] ;
+ wire \mprj_dat_i_user[17] ;
+ wire \mprj_dat_i_user[18] ;
+ wire \mprj_dat_i_user[19] ;
+ wire \mprj_dat_i_user[1] ;
+ wire \mprj_dat_i_user[20] ;
+ wire \mprj_dat_i_user[21] ;
+ wire \mprj_dat_i_user[22] ;
+ wire \mprj_dat_i_user[23] ;
+ wire \mprj_dat_i_user[24] ;
+ wire \mprj_dat_i_user[25] ;
+ wire \mprj_dat_i_user[26] ;
+ wire \mprj_dat_i_user[27] ;
+ wire \mprj_dat_i_user[28] ;
+ wire \mprj_dat_i_user[29] ;
+ wire \mprj_dat_i_user[2] ;
+ wire \mprj_dat_i_user[30] ;
+ wire \mprj_dat_i_user[31] ;
+ wire \mprj_dat_i_user[3] ;
+ wire \mprj_dat_i_user[4] ;
+ wire \mprj_dat_i_user[5] ;
+ wire \mprj_dat_i_user[6] ;
+ wire \mprj_dat_i_user[7] ;
+ wire \mprj_dat_i_user[8] ;
+ wire \mprj_dat_i_user[9] ;
+ wire \mprj_dat_o_core[0] ;
+ wire \mprj_dat_o_core[10] ;
+ wire \mprj_dat_o_core[11] ;
+ wire \mprj_dat_o_core[12] ;
+ wire \mprj_dat_o_core[13] ;
+ wire \mprj_dat_o_core[14] ;
+ wire \mprj_dat_o_core[15] ;
+ wire \mprj_dat_o_core[16] ;
+ wire \mprj_dat_o_core[17] ;
+ wire \mprj_dat_o_core[18] ;
+ wire \mprj_dat_o_core[19] ;
+ wire \mprj_dat_o_core[1] ;
+ wire \mprj_dat_o_core[20] ;
+ wire \mprj_dat_o_core[21] ;
+ wire \mprj_dat_o_core[22] ;
+ wire \mprj_dat_o_core[23] ;
+ wire \mprj_dat_o_core[24] ;
+ wire \mprj_dat_o_core[25] ;
+ wire \mprj_dat_o_core[26] ;
+ wire \mprj_dat_o_core[27] ;
+ wire \mprj_dat_o_core[28] ;
+ wire \mprj_dat_o_core[29] ;
+ wire \mprj_dat_o_core[2] ;
+ wire \mprj_dat_o_core[30] ;
+ wire \mprj_dat_o_core[31] ;
+ wire \mprj_dat_o_core[3] ;
+ wire \mprj_dat_o_core[4] ;
+ wire \mprj_dat_o_core[5] ;
+ wire \mprj_dat_o_core[6] ;
+ wire \mprj_dat_o_core[7] ;
+ wire \mprj_dat_o_core[8] ;
+ wire \mprj_dat_o_core[9] ;
+ wire \mprj_dat_o_user[0] ;
+ wire \mprj_dat_o_user[10] ;
+ wire \mprj_dat_o_user[11] ;
+ wire \mprj_dat_o_user[12] ;
+ wire \mprj_dat_o_user[13] ;
+ wire \mprj_dat_o_user[14] ;
+ wire \mprj_dat_o_user[15] ;
+ wire \mprj_dat_o_user[16] ;
+ wire \mprj_dat_o_user[17] ;
+ wire \mprj_dat_o_user[18] ;
+ wire \mprj_dat_o_user[19] ;
+ wire \mprj_dat_o_user[1] ;
+ wire \mprj_dat_o_user[20] ;
+ wire \mprj_dat_o_user[21] ;
+ wire \mprj_dat_o_user[22] ;
+ wire \mprj_dat_o_user[23] ;
+ wire \mprj_dat_o_user[24] ;
+ wire \mprj_dat_o_user[25] ;
+ wire \mprj_dat_o_user[26] ;
+ wire \mprj_dat_o_user[27] ;
+ wire \mprj_dat_o_user[28] ;
+ wire \mprj_dat_o_user[29] ;
+ wire \mprj_dat_o_user[2] ;
+ wire \mprj_dat_o_user[30] ;
+ wire \mprj_dat_o_user[31] ;
+ wire \mprj_dat_o_user[3] ;
+ wire \mprj_dat_o_user[4] ;
+ wire \mprj_dat_o_user[5] ;
+ wire \mprj_dat_o_user[6] ;
+ wire \mprj_dat_o_user[7] ;
+ wire \mprj_dat_o_user[8] ;
+ wire \mprj_dat_o_user[9] ;
+ wire mprj_iena_wb;
+ inout [37:0] mprj_io;
+ wire \mprj_io_analog_en[0] ;
+ wire \mprj_io_analog_en[10] ;
+ wire \mprj_io_analog_en[11] ;
+ wire \mprj_io_analog_en[12] ;
+ wire \mprj_io_analog_en[13] ;
+ wire \mprj_io_analog_en[14] ;
+ wire \mprj_io_analog_en[15] ;
+ wire \mprj_io_analog_en[16] ;
+ wire \mprj_io_analog_en[17] ;
+ wire \mprj_io_analog_en[18] ;
+ wire \mprj_io_analog_en[19] ;
+ wire \mprj_io_analog_en[1] ;
+ wire \mprj_io_analog_en[20] ;
+ wire \mprj_io_analog_en[21] ;
+ wire \mprj_io_analog_en[22] ;
+ wire \mprj_io_analog_en[23] ;
+ wire \mprj_io_analog_en[24] ;
+ wire \mprj_io_analog_en[25] ;
+ wire \mprj_io_analog_en[26] ;
+ wire \mprj_io_analog_en[27] ;
+ wire \mprj_io_analog_en[28] ;
+ wire \mprj_io_analog_en[29] ;
+ wire \mprj_io_analog_en[2] ;
+ wire \mprj_io_analog_en[30] ;
+ wire \mprj_io_analog_en[31] ;
+ wire \mprj_io_analog_en[32] ;
+ wire \mprj_io_analog_en[33] ;
+ wire \mprj_io_analog_en[34] ;
+ wire \mprj_io_analog_en[35] ;
+ wire \mprj_io_analog_en[36] ;
+ wire \mprj_io_analog_en[37] ;
+ wire \mprj_io_analog_en[3] ;
+ wire \mprj_io_analog_en[4] ;
+ wire \mprj_io_analog_en[5] ;
+ wire \mprj_io_analog_en[6] ;
+ wire \mprj_io_analog_en[7] ;
+ wire \mprj_io_analog_en[8] ;
+ wire \mprj_io_analog_en[9] ;
+ wire \mprj_io_analog_pol[0] ;
+ wire \mprj_io_analog_pol[10] ;
+ wire \mprj_io_analog_pol[11] ;
+ wire \mprj_io_analog_pol[12] ;
+ wire \mprj_io_analog_pol[13] ;
+ wire \mprj_io_analog_pol[14] ;
+ wire \mprj_io_analog_pol[15] ;
+ wire \mprj_io_analog_pol[16] ;
+ wire \mprj_io_analog_pol[17] ;
+ wire \mprj_io_analog_pol[18] ;
+ wire \mprj_io_analog_pol[19] ;
+ wire \mprj_io_analog_pol[1] ;
+ wire \mprj_io_analog_pol[20] ;
+ wire \mprj_io_analog_pol[21] ;
+ wire \mprj_io_analog_pol[22] ;
+ wire \mprj_io_analog_pol[23] ;
+ wire \mprj_io_analog_pol[24] ;
+ wire \mprj_io_analog_pol[25] ;
+ wire \mprj_io_analog_pol[26] ;
+ wire \mprj_io_analog_pol[27] ;
+ wire \mprj_io_analog_pol[28] ;
+ wire \mprj_io_analog_pol[29] ;
+ wire \mprj_io_analog_pol[2] ;
+ wire \mprj_io_analog_pol[30] ;
+ wire \mprj_io_analog_pol[31] ;
+ wire \mprj_io_analog_pol[32] ;
+ wire \mprj_io_analog_pol[33] ;
+ wire \mprj_io_analog_pol[34] ;
+ wire \mprj_io_analog_pol[35] ;
+ wire \mprj_io_analog_pol[36] ;
+ wire \mprj_io_analog_pol[37] ;
+ wire \mprj_io_analog_pol[3] ;
+ wire \mprj_io_analog_pol[4] ;
+ wire \mprj_io_analog_pol[5] ;
+ wire \mprj_io_analog_pol[6] ;
+ wire \mprj_io_analog_pol[7] ;
+ wire \mprj_io_analog_pol[8] ;
+ wire \mprj_io_analog_pol[9] ;
+ wire \mprj_io_analog_sel[0] ;
+ wire \mprj_io_analog_sel[10] ;
+ wire \mprj_io_analog_sel[11] ;
+ wire \mprj_io_analog_sel[12] ;
+ wire \mprj_io_analog_sel[13] ;
+ wire \mprj_io_analog_sel[14] ;
+ wire \mprj_io_analog_sel[15] ;
+ wire \mprj_io_analog_sel[16] ;
+ wire \mprj_io_analog_sel[17] ;
+ wire \mprj_io_analog_sel[18] ;
+ wire \mprj_io_analog_sel[19] ;
+ wire \mprj_io_analog_sel[1] ;
+ wire \mprj_io_analog_sel[20] ;
+ wire \mprj_io_analog_sel[21] ;
+ wire \mprj_io_analog_sel[22] ;
+ wire \mprj_io_analog_sel[23] ;
+ wire \mprj_io_analog_sel[24] ;
+ wire \mprj_io_analog_sel[25] ;
+ wire \mprj_io_analog_sel[26] ;
+ wire \mprj_io_analog_sel[27] ;
+ wire \mprj_io_analog_sel[28] ;
+ wire \mprj_io_analog_sel[29] ;
+ wire \mprj_io_analog_sel[2] ;
+ wire \mprj_io_analog_sel[30] ;
+ wire \mprj_io_analog_sel[31] ;
+ wire \mprj_io_analog_sel[32] ;
+ wire \mprj_io_analog_sel[33] ;
+ wire \mprj_io_analog_sel[34] ;
+ wire \mprj_io_analog_sel[35] ;
+ wire \mprj_io_analog_sel[36] ;
+ wire \mprj_io_analog_sel[37] ;
+ wire \mprj_io_analog_sel[3] ;
+ wire \mprj_io_analog_sel[4] ;
+ wire \mprj_io_analog_sel[5] ;
+ wire \mprj_io_analog_sel[6] ;
+ wire \mprj_io_analog_sel[7] ;
+ wire \mprj_io_analog_sel[8] ;
+ wire \mprj_io_analog_sel[9] ;
+ wire \mprj_io_dm[0] ;
+ wire \mprj_io_dm[100] ;
+ wire \mprj_io_dm[101] ;
+ wire \mprj_io_dm[102] ;
+ wire \mprj_io_dm[103] ;
+ wire \mprj_io_dm[104] ;
+ wire \mprj_io_dm[105] ;
+ wire \mprj_io_dm[106] ;
+ wire \mprj_io_dm[107] ;
+ wire \mprj_io_dm[108] ;
+ wire \mprj_io_dm[109] ;
+ wire \mprj_io_dm[10] ;
+ wire \mprj_io_dm[110] ;
+ wire \mprj_io_dm[111] ;
+ wire \mprj_io_dm[112] ;
+ wire \mprj_io_dm[113] ;
+ wire \mprj_io_dm[11] ;
+ wire \mprj_io_dm[12] ;
+ wire \mprj_io_dm[13] ;
+ wire \mprj_io_dm[14] ;
+ wire \mprj_io_dm[15] ;
+ wire \mprj_io_dm[16] ;
+ wire \mprj_io_dm[17] ;
+ wire \mprj_io_dm[18] ;
+ wire \mprj_io_dm[19] ;
+ wire \mprj_io_dm[1] ;
+ wire \mprj_io_dm[20] ;
+ wire \mprj_io_dm[21] ;
+ wire \mprj_io_dm[22] ;
+ wire \mprj_io_dm[23] ;
+ wire \mprj_io_dm[24] ;
+ wire \mprj_io_dm[25] ;
+ wire \mprj_io_dm[26] ;
+ wire \mprj_io_dm[27] ;
+ wire \mprj_io_dm[28] ;
+ wire \mprj_io_dm[29] ;
+ wire \mprj_io_dm[2] ;
+ wire \mprj_io_dm[30] ;
+ wire \mprj_io_dm[31] ;
+ wire \mprj_io_dm[32] ;
+ wire \mprj_io_dm[33] ;
+ wire \mprj_io_dm[34] ;
+ wire \mprj_io_dm[35] ;
+ wire \mprj_io_dm[36] ;
+ wire \mprj_io_dm[37] ;
+ wire \mprj_io_dm[38] ;
+ wire \mprj_io_dm[39] ;
+ wire \mprj_io_dm[3] ;
+ wire \mprj_io_dm[40] ;
+ wire \mprj_io_dm[41] ;
+ wire \mprj_io_dm[42] ;
+ wire \mprj_io_dm[43] ;
+ wire \mprj_io_dm[44] ;
+ wire \mprj_io_dm[45] ;
+ wire \mprj_io_dm[46] ;
+ wire \mprj_io_dm[47] ;
+ wire \mprj_io_dm[48] ;
+ wire \mprj_io_dm[49] ;
+ wire \mprj_io_dm[4] ;
+ wire \mprj_io_dm[50] ;
+ wire \mprj_io_dm[51] ;
+ wire \mprj_io_dm[52] ;
+ wire \mprj_io_dm[53] ;
+ wire \mprj_io_dm[54] ;
+ wire \mprj_io_dm[55] ;
+ wire \mprj_io_dm[56] ;
+ wire \mprj_io_dm[57] ;
+ wire \mprj_io_dm[58] ;
+ wire \mprj_io_dm[59] ;
+ wire \mprj_io_dm[5] ;
+ wire \mprj_io_dm[60] ;
+ wire \mprj_io_dm[61] ;
+ wire \mprj_io_dm[62] ;
+ wire \mprj_io_dm[63] ;
+ wire \mprj_io_dm[64] ;
+ wire \mprj_io_dm[65] ;
+ wire \mprj_io_dm[66] ;
+ wire \mprj_io_dm[67] ;
+ wire \mprj_io_dm[68] ;
+ wire \mprj_io_dm[69] ;
+ wire \mprj_io_dm[6] ;
+ wire \mprj_io_dm[70] ;
+ wire \mprj_io_dm[71] ;
+ wire \mprj_io_dm[72] ;
+ wire \mprj_io_dm[73] ;
+ wire \mprj_io_dm[74] ;
+ wire \mprj_io_dm[75] ;
+ wire \mprj_io_dm[76] ;
+ wire \mprj_io_dm[77] ;
+ wire \mprj_io_dm[78] ;
+ wire \mprj_io_dm[79] ;
+ wire \mprj_io_dm[7] ;
+ wire \mprj_io_dm[80] ;
+ wire \mprj_io_dm[81] ;
+ wire \mprj_io_dm[82] ;
+ wire \mprj_io_dm[83] ;
+ wire \mprj_io_dm[84] ;
+ wire \mprj_io_dm[85] ;
+ wire \mprj_io_dm[86] ;
+ wire \mprj_io_dm[87] ;
+ wire \mprj_io_dm[88] ;
+ wire \mprj_io_dm[89] ;
+ wire \mprj_io_dm[8] ;
+ wire \mprj_io_dm[90] ;
+ wire \mprj_io_dm[91] ;
+ wire \mprj_io_dm[92] ;
+ wire \mprj_io_dm[93] ;
+ wire \mprj_io_dm[94] ;
+ wire \mprj_io_dm[95] ;
+ wire \mprj_io_dm[96] ;
+ wire \mprj_io_dm[97] ;
+ wire \mprj_io_dm[98] ;
+ wire \mprj_io_dm[99] ;
+ wire \mprj_io_dm[9] ;
+ wire \mprj_io_holdover[0] ;
+ wire \mprj_io_holdover[10] ;
+ wire \mprj_io_holdover[11] ;
+ wire \mprj_io_holdover[12] ;
+ wire \mprj_io_holdover[13] ;
+ wire \mprj_io_holdover[14] ;
+ wire \mprj_io_holdover[15] ;
+ wire \mprj_io_holdover[16] ;
+ wire \mprj_io_holdover[17] ;
+ wire \mprj_io_holdover[18] ;
+ wire \mprj_io_holdover[19] ;
+ wire \mprj_io_holdover[1] ;
+ wire \mprj_io_holdover[20] ;
+ wire \mprj_io_holdover[21] ;
+ wire \mprj_io_holdover[22] ;
+ wire \mprj_io_holdover[23] ;
+ wire \mprj_io_holdover[24] ;
+ wire \mprj_io_holdover[25] ;
+ wire \mprj_io_holdover[26] ;
+ wire \mprj_io_holdover[27] ;
+ wire \mprj_io_holdover[28] ;
+ wire \mprj_io_holdover[29] ;
+ wire \mprj_io_holdover[2] ;
+ wire \mprj_io_holdover[30] ;
+ wire \mprj_io_holdover[31] ;
+ wire \mprj_io_holdover[32] ;
+ wire \mprj_io_holdover[33] ;
+ wire \mprj_io_holdover[34] ;
+ wire \mprj_io_holdover[35] ;
+ wire \mprj_io_holdover[36] ;
+ wire \mprj_io_holdover[37] ;
+ wire \mprj_io_holdover[3] ;
+ wire \mprj_io_holdover[4] ;
+ wire \mprj_io_holdover[5] ;
+ wire \mprj_io_holdover[6] ;
+ wire \mprj_io_holdover[7] ;
+ wire \mprj_io_holdover[8] ;
+ wire \mprj_io_holdover[9] ;
+ wire \mprj_io_ib_mode_sel[0] ;
+ wire \mprj_io_ib_mode_sel[10] ;
+ wire \mprj_io_ib_mode_sel[11] ;
+ wire \mprj_io_ib_mode_sel[12] ;
+ wire \mprj_io_ib_mode_sel[13] ;
+ wire \mprj_io_ib_mode_sel[14] ;
+ wire \mprj_io_ib_mode_sel[15] ;
+ wire \mprj_io_ib_mode_sel[16] ;
+ wire \mprj_io_ib_mode_sel[17] ;
+ wire \mprj_io_ib_mode_sel[18] ;
+ wire \mprj_io_ib_mode_sel[19] ;
+ wire \mprj_io_ib_mode_sel[1] ;
+ wire \mprj_io_ib_mode_sel[20] ;
+ wire \mprj_io_ib_mode_sel[21] ;
+ wire \mprj_io_ib_mode_sel[22] ;
+ wire \mprj_io_ib_mode_sel[23] ;
+ wire \mprj_io_ib_mode_sel[24] ;
+ wire \mprj_io_ib_mode_sel[25] ;
+ wire \mprj_io_ib_mode_sel[26] ;
+ wire \mprj_io_ib_mode_sel[27] ;
+ wire \mprj_io_ib_mode_sel[28] ;
+ wire \mprj_io_ib_mode_sel[29] ;
+ wire \mprj_io_ib_mode_sel[2] ;
+ wire \mprj_io_ib_mode_sel[30] ;
+ wire \mprj_io_ib_mode_sel[31] ;
+ wire \mprj_io_ib_mode_sel[32] ;
+ wire \mprj_io_ib_mode_sel[33] ;
+ wire \mprj_io_ib_mode_sel[34] ;
+ wire \mprj_io_ib_mode_sel[35] ;
+ wire \mprj_io_ib_mode_sel[36] ;
+ wire \mprj_io_ib_mode_sel[37] ;
+ wire \mprj_io_ib_mode_sel[3] ;
+ wire \mprj_io_ib_mode_sel[4] ;
+ wire \mprj_io_ib_mode_sel[5] ;
+ wire \mprj_io_ib_mode_sel[6] ;
+ wire \mprj_io_ib_mode_sel[7] ;
+ wire \mprj_io_ib_mode_sel[8] ;
+ wire \mprj_io_ib_mode_sel[9] ;
+ wire \mprj_io_in[0] ;
+ wire \mprj_io_in[10] ;
+ wire \mprj_io_in[11] ;
+ wire \mprj_io_in[12] ;
+ wire \mprj_io_in[13] ;
+ wire \mprj_io_in[14] ;
+ wire \mprj_io_in[15] ;
+ wire \mprj_io_in[16] ;
+ wire \mprj_io_in[17] ;
+ wire \mprj_io_in[18] ;
+ wire \mprj_io_in[19] ;
+ wire \mprj_io_in[1] ;
+ wire \mprj_io_in[20] ;
+ wire \mprj_io_in[21] ;
+ wire \mprj_io_in[22] ;
+ wire \mprj_io_in[23] ;
+ wire \mprj_io_in[24] ;
+ wire \mprj_io_in[25] ;
+ wire \mprj_io_in[26] ;
+ wire \mprj_io_in[27] ;
+ wire \mprj_io_in[28] ;
+ wire \mprj_io_in[29] ;
+ wire \mprj_io_in[2] ;
+ wire \mprj_io_in[30] ;
+ wire \mprj_io_in[31] ;
+ wire \mprj_io_in[32] ;
+ wire \mprj_io_in[33] ;
+ wire \mprj_io_in[34] ;
+ wire \mprj_io_in[35] ;
+ wire \mprj_io_in[36] ;
+ wire \mprj_io_in[37] ;
+ wire \mprj_io_in[3] ;
+ wire \mprj_io_in[4] ;
+ wire \mprj_io_in[5] ;
+ wire \mprj_io_in[6] ;
+ wire \mprj_io_in[7] ;
+ wire \mprj_io_in[8] ;
+ wire \mprj_io_in[9] ;
+ wire \mprj_io_inp_dis[0] ;
+ wire \mprj_io_inp_dis[10] ;
+ wire \mprj_io_inp_dis[11] ;
+ wire \mprj_io_inp_dis[12] ;
+ wire \mprj_io_inp_dis[13] ;
+ wire \mprj_io_inp_dis[14] ;
+ wire \mprj_io_inp_dis[15] ;
+ wire \mprj_io_inp_dis[16] ;
+ wire \mprj_io_inp_dis[17] ;
+ wire \mprj_io_inp_dis[18] ;
+ wire \mprj_io_inp_dis[19] ;
+ wire \mprj_io_inp_dis[1] ;
+ wire \mprj_io_inp_dis[20] ;
+ wire \mprj_io_inp_dis[21] ;
+ wire \mprj_io_inp_dis[22] ;
+ wire \mprj_io_inp_dis[23] ;
+ wire \mprj_io_inp_dis[24] ;
+ wire \mprj_io_inp_dis[25] ;
+ wire \mprj_io_inp_dis[26] ;
+ wire \mprj_io_inp_dis[27] ;
+ wire \mprj_io_inp_dis[28] ;
+ wire \mprj_io_inp_dis[29] ;
+ wire \mprj_io_inp_dis[2] ;
+ wire \mprj_io_inp_dis[30] ;
+ wire \mprj_io_inp_dis[31] ;
+ wire \mprj_io_inp_dis[32] ;
+ wire \mprj_io_inp_dis[33] ;
+ wire \mprj_io_inp_dis[34] ;
+ wire \mprj_io_inp_dis[35] ;
+ wire \mprj_io_inp_dis[36] ;
+ wire \mprj_io_inp_dis[37] ;
+ wire \mprj_io_inp_dis[3] ;
+ wire \mprj_io_inp_dis[4] ;
+ wire \mprj_io_inp_dis[5] ;
+ wire \mprj_io_inp_dis[6] ;
+ wire \mprj_io_inp_dis[7] ;
+ wire \mprj_io_inp_dis[8] ;
+ wire \mprj_io_inp_dis[9] ;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1;
+ wire mprj_io_loader_data_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_strobe;
+ wire \mprj_io_oeb[0] ;
+ wire \mprj_io_oeb[10] ;
+ wire \mprj_io_oeb[11] ;
+ wire \mprj_io_oeb[12] ;
+ wire \mprj_io_oeb[13] ;
+ wire \mprj_io_oeb[14] ;
+ wire \mprj_io_oeb[15] ;
+ wire \mprj_io_oeb[16] ;
+ wire \mprj_io_oeb[17] ;
+ wire \mprj_io_oeb[18] ;
+ wire \mprj_io_oeb[19] ;
+ wire \mprj_io_oeb[1] ;
+ wire \mprj_io_oeb[20] ;
+ wire \mprj_io_oeb[21] ;
+ wire \mprj_io_oeb[22] ;
+ wire \mprj_io_oeb[23] ;
+ wire \mprj_io_oeb[24] ;
+ wire \mprj_io_oeb[25] ;
+ wire \mprj_io_oeb[26] ;
+ wire \mprj_io_oeb[27] ;
+ wire \mprj_io_oeb[28] ;
+ wire \mprj_io_oeb[29] ;
+ wire \mprj_io_oeb[2] ;
+ wire \mprj_io_oeb[30] ;
+ wire \mprj_io_oeb[31] ;
+ wire \mprj_io_oeb[32] ;
+ wire \mprj_io_oeb[33] ;
+ wire \mprj_io_oeb[34] ;
+ wire \mprj_io_oeb[35] ;
+ wire \mprj_io_oeb[36] ;
+ wire \mprj_io_oeb[37] ;
+ wire \mprj_io_oeb[3] ;
+ wire \mprj_io_oeb[4] ;
+ wire \mprj_io_oeb[5] ;
+ wire \mprj_io_oeb[6] ;
+ wire \mprj_io_oeb[7] ;
+ wire \mprj_io_oeb[8] ;
+ wire \mprj_io_oeb[9] ;
+ wire \mprj_io_out[0] ;
+ wire \mprj_io_out[10] ;
+ wire \mprj_io_out[11] ;
+ wire \mprj_io_out[12] ;
+ wire \mprj_io_out[13] ;
+ wire \mprj_io_out[14] ;
+ wire \mprj_io_out[15] ;
+ wire \mprj_io_out[16] ;
+ wire \mprj_io_out[17] ;
+ wire \mprj_io_out[18] ;
+ wire \mprj_io_out[19] ;
+ wire \mprj_io_out[1] ;
+ wire \mprj_io_out[20] ;
+ wire \mprj_io_out[21] ;
+ wire \mprj_io_out[22] ;
+ wire \mprj_io_out[23] ;
+ wire \mprj_io_out[24] ;
+ wire \mprj_io_out[25] ;
+ wire \mprj_io_out[26] ;
+ wire \mprj_io_out[27] ;
+ wire \mprj_io_out[28] ;
+ wire \mprj_io_out[29] ;
+ wire \mprj_io_out[2] ;
+ wire \mprj_io_out[30] ;
+ wire \mprj_io_out[31] ;
+ wire \mprj_io_out[32] ;
+ wire \mprj_io_out[33] ;
+ wire \mprj_io_out[34] ;
+ wire \mprj_io_out[35] ;
+ wire \mprj_io_out[36] ;
+ wire \mprj_io_out[37] ;
+ wire \mprj_io_out[3] ;
+ wire \mprj_io_out[4] ;
+ wire \mprj_io_out[5] ;
+ wire \mprj_io_out[6] ;
+ wire \mprj_io_out[7] ;
+ wire \mprj_io_out[8] ;
+ wire \mprj_io_out[9] ;
+ wire \mprj_io_slow_sel[0] ;
+ wire \mprj_io_slow_sel[10] ;
+ wire \mprj_io_slow_sel[11] ;
+ wire \mprj_io_slow_sel[12] ;
+ wire \mprj_io_slow_sel[13] ;
+ wire \mprj_io_slow_sel[14] ;
+ wire \mprj_io_slow_sel[15] ;
+ wire \mprj_io_slow_sel[16] ;
+ wire \mprj_io_slow_sel[17] ;
+ wire \mprj_io_slow_sel[18] ;
+ wire \mprj_io_slow_sel[19] ;
+ wire \mprj_io_slow_sel[1] ;
+ wire \mprj_io_slow_sel[20] ;
+ wire \mprj_io_slow_sel[21] ;
+ wire \mprj_io_slow_sel[22] ;
+ wire \mprj_io_slow_sel[23] ;
+ wire \mprj_io_slow_sel[24] ;
+ wire \mprj_io_slow_sel[25] ;
+ wire \mprj_io_slow_sel[26] ;
+ wire \mprj_io_slow_sel[27] ;
+ wire \mprj_io_slow_sel[28] ;
+ wire \mprj_io_slow_sel[29] ;
+ wire \mprj_io_slow_sel[2] ;
+ wire \mprj_io_slow_sel[30] ;
+ wire \mprj_io_slow_sel[31] ;
+ wire \mprj_io_slow_sel[32] ;
+ wire \mprj_io_slow_sel[33] ;
+ wire \mprj_io_slow_sel[34] ;
+ wire \mprj_io_slow_sel[35] ;
+ wire \mprj_io_slow_sel[36] ;
+ wire \mprj_io_slow_sel[37] ;
+ wire \mprj_io_slow_sel[3] ;
+ wire \mprj_io_slow_sel[4] ;
+ wire \mprj_io_slow_sel[5] ;
+ wire \mprj_io_slow_sel[6] ;
+ wire \mprj_io_slow_sel[7] ;
+ wire \mprj_io_slow_sel[8] ;
+ wire \mprj_io_slow_sel[9] ;
+ wire \mprj_io_vtrip_sel[0] ;
+ wire \mprj_io_vtrip_sel[10] ;
+ wire \mprj_io_vtrip_sel[11] ;
+ wire \mprj_io_vtrip_sel[12] ;
+ wire \mprj_io_vtrip_sel[13] ;
+ wire \mprj_io_vtrip_sel[14] ;
+ wire \mprj_io_vtrip_sel[15] ;
+ wire \mprj_io_vtrip_sel[16] ;
+ wire \mprj_io_vtrip_sel[17] ;
+ wire \mprj_io_vtrip_sel[18] ;
+ wire \mprj_io_vtrip_sel[19] ;
+ wire \mprj_io_vtrip_sel[1] ;
+ wire \mprj_io_vtrip_sel[20] ;
+ wire \mprj_io_vtrip_sel[21] ;
+ wire \mprj_io_vtrip_sel[22] ;
+ wire \mprj_io_vtrip_sel[23] ;
+ wire \mprj_io_vtrip_sel[24] ;
+ wire \mprj_io_vtrip_sel[25] ;
+ wire \mprj_io_vtrip_sel[26] ;
+ wire \mprj_io_vtrip_sel[27] ;
+ wire \mprj_io_vtrip_sel[28] ;
+ wire \mprj_io_vtrip_sel[29] ;
+ wire \mprj_io_vtrip_sel[2] ;
+ wire \mprj_io_vtrip_sel[30] ;
+ wire \mprj_io_vtrip_sel[31] ;
+ wire \mprj_io_vtrip_sel[32] ;
+ wire \mprj_io_vtrip_sel[33] ;
+ wire \mprj_io_vtrip_sel[34] ;
+ wire \mprj_io_vtrip_sel[35] ;
+ wire \mprj_io_vtrip_sel[36] ;
+ wire \mprj_io_vtrip_sel[37] ;
+ wire \mprj_io_vtrip_sel[3] ;
+ wire \mprj_io_vtrip_sel[4] ;
+ wire \mprj_io_vtrip_sel[5] ;
+ wire \mprj_io_vtrip_sel[6] ;
+ wire \mprj_io_vtrip_sel[7] ;
+ wire \mprj_io_vtrip_sel[8] ;
+ wire \mprj_io_vtrip_sel[9] ;
+ wire mprj_reset;
+ wire \mprj_sel_o_core[0] ;
+ wire \mprj_sel_o_core[1] ;
+ wire \mprj_sel_o_core[2] ;
+ wire \mprj_sel_o_core[3] ;
+ wire \mprj_sel_o_user[0] ;
+ wire \mprj_sel_o_user[1] ;
+ wire \mprj_sel_o_user[2] ;
+ wire \mprj_sel_o_user[3] ;
+ wire mprj_stb_o_core;
+ wire mprj_stb_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj_we_o_core;
+ wire mprj_we_o_user;
+ wire \one_loop1[10] ;
+ wire \one_loop1[11] ;
+ wire \one_loop1[12] ;
+ wire \one_loop1[13] ;
+ wire \one_loop1[14] ;
+ wire \one_loop1[15] ;
+ wire \one_loop1[16] ;
+ wire \one_loop1[17] ;
+ wire \one_loop1[18] ;
+ wire \one_loop1[2] ;
+ wire \one_loop1[3] ;
+ wire \one_loop1[4] ;
+ wire \one_loop1[5] ;
+ wire \one_loop1[6] ;
+ wire \one_loop1[7] ;
+ wire \one_loop1[8] ;
+ wire \one_loop1[9] ;
+ wire \one_loop2[0] ;
+ wire \one_loop2[10] ;
+ wire \one_loop2[11] ;
+ wire \one_loop2[12] ;
+ wire \one_loop2[13] ;
+ wire \one_loop2[14] ;
+ wire \one_loop2[15] ;
+ wire \one_loop2[1] ;
+ wire \one_loop2[2] ;
+ wire \one_loop2[3] ;
+ wire \one_loop2[4] ;
+ wire \one_loop2[5] ;
+ wire \one_loop2[6] ;
+ wire \one_loop2[7] ;
+ wire \one_loop2[8] ;
+ wire \one_loop2[9] ;
+ wire pll_clk;
+ wire pll_clk90;
+ wire por_l;
+ wire porb_h;
+ wire porb_l;
+ wire qspi_enabled;
+ input resetb;
+ wire rstb_h;
+ wire rstb_l;
+ wire ser_rx;
+ wire ser_tx;
+ wire spi_csb;
+ wire spi_enabled;
+ wire \spi_pll90_sel[0] ;
+ wire \spi_pll90_sel[1] ;
+ wire \spi_pll90_sel[2] ;
+ wire spi_pll_dco_ena;
+ wire \spi_pll_div[0] ;
+ wire \spi_pll_div[1] ;
+ wire \spi_pll_div[2] ;
+ wire \spi_pll_div[3] ;
+ wire \spi_pll_div[4] ;
+ wire spi_pll_ena;
+ wire \spi_pll_sel[0] ;
+ wire \spi_pll_sel[1] ;
+ wire \spi_pll_sel[2] ;
+ wire \spi_pll_trim[0] ;
+ wire \spi_pll_trim[10] ;
+ wire \spi_pll_trim[11] ;
+ wire \spi_pll_trim[12] ;
+ wire \spi_pll_trim[13] ;
+ wire \spi_pll_trim[14] ;
+ wire \spi_pll_trim[15] ;
+ wire \spi_pll_trim[16] ;
+ wire \spi_pll_trim[17] ;
+ wire \spi_pll_trim[18] ;
+ wire \spi_pll_trim[19] ;
+ wire \spi_pll_trim[1] ;
+ wire \spi_pll_trim[20] ;
+ wire \spi_pll_trim[21] ;
+ wire \spi_pll_trim[22] ;
+ wire \spi_pll_trim[23] ;
+ wire \spi_pll_trim[24] ;
+ wire \spi_pll_trim[25] ;
+ wire \spi_pll_trim[2] ;
+ wire \spi_pll_trim[3] ;
+ wire \spi_pll_trim[4] ;
+ wire \spi_pll_trim[5] ;
+ wire \spi_pll_trim[6] ;
+ wire \spi_pll_trim[7] ;
+ wire \spi_pll_trim[8] ;
+ wire \spi_pll_trim[9] ;
+ wire spi_sck;
+ wire spi_sdi;
+ wire spi_sdo;
+ wire spi_sdoenb;
+ wire trap;
+ wire uart_enabled;
+ wire \user_analog_io[0] ;
+ wire \user_analog_io[10] ;
+ wire \user_analog_io[11] ;
+ wire \user_analog_io[12] ;
+ wire \user_analog_io[13] ;
+ wire \user_analog_io[14] ;
+ wire \user_analog_io[15] ;
+ wire \user_analog_io[16] ;
+ wire \user_analog_io[17] ;
+ wire \user_analog_io[18] ;
+ wire \user_analog_io[19] ;
+ wire \user_analog_io[1] ;
+ wire \user_analog_io[20] ;
+ wire \user_analog_io[21] ;
+ wire \user_analog_io[22] ;
+ wire \user_analog_io[23] ;
+ wire \user_analog_io[24] ;
+ wire \user_analog_io[25] ;
+ wire \user_analog_io[26] ;
+ wire \user_analog_io[27] ;
+ wire \user_analog_io[28] ;
+ wire \user_analog_io[2] ;
+ wire \user_analog_io[3] ;
+ wire \user_analog_io[4] ;
+ wire \user_analog_io[5] ;
+ wire \user_analog_io[6] ;
+ wire \user_analog_io[7] ;
+ wire \user_analog_io[8] ;
+ wire \user_analog_io[9] ;
+ wire \user_io_in[0] ;
+ wire \user_io_in[10] ;
+ wire \user_io_in[11] ;
+ wire \user_io_in[12] ;
+ wire \user_io_in[13] ;
+ wire \user_io_in[14] ;
+ wire \user_io_in[15] ;
+ wire \user_io_in[16] ;
+ wire \user_io_in[17] ;
+ wire \user_io_in[18] ;
+ wire \user_io_in[19] ;
+ wire \user_io_in[1] ;
+ wire \user_io_in[20] ;
+ wire \user_io_in[21] ;
+ wire \user_io_in[22] ;
+ wire \user_io_in[23] ;
+ wire \user_io_in[24] ;
+ wire \user_io_in[25] ;
+ wire \user_io_in[26] ;
+ wire \user_io_in[27] ;
+ wire \user_io_in[28] ;
+ wire \user_io_in[29] ;
+ wire \user_io_in[2] ;
+ wire \user_io_in[30] ;
+ wire \user_io_in[31] ;
+ wire \user_io_in[32] ;
+ wire \user_io_in[33] ;
+ wire \user_io_in[34] ;
+ wire \user_io_in[35] ;
+ wire \user_io_in[36] ;
+ wire \user_io_in[37] ;
+ wire \user_io_in[3] ;
+ wire \user_io_in[4] ;
+ wire \user_io_in[5] ;
+ wire \user_io_in[6] ;
+ wire \user_io_in[7] ;
+ wire \user_io_in[8] ;
+ wire \user_io_in[9] ;
+ wire \user_io_oeb[0] ;
+ wire \user_io_oeb[10] ;
+ wire \user_io_oeb[11] ;
+ wire \user_io_oeb[12] ;
+ wire \user_io_oeb[13] ;
+ wire \user_io_oeb[14] ;
+ wire \user_io_oeb[15] ;
+ wire \user_io_oeb[16] ;
+ wire \user_io_oeb[17] ;
+ wire \user_io_oeb[18] ;
+ wire \user_io_oeb[19] ;
+ wire \user_io_oeb[1] ;
+ wire \user_io_oeb[20] ;
+ wire \user_io_oeb[21] ;
+ wire \user_io_oeb[22] ;
+ wire \user_io_oeb[23] ;
+ wire \user_io_oeb[24] ;
+ wire \user_io_oeb[25] ;
+ wire \user_io_oeb[26] ;
+ wire \user_io_oeb[27] ;
+ wire \user_io_oeb[28] ;
+ wire \user_io_oeb[29] ;
+ wire \user_io_oeb[2] ;
+ wire \user_io_oeb[30] ;
+ wire \user_io_oeb[31] ;
+ wire \user_io_oeb[32] ;
+ wire \user_io_oeb[33] ;
+ wire \user_io_oeb[34] ;
+ wire \user_io_oeb[35] ;
+ wire \user_io_oeb[36] ;
+ wire \user_io_oeb[37] ;
+ wire \user_io_oeb[3] ;
+ wire \user_io_oeb[4] ;
+ wire \user_io_oeb[5] ;
+ wire \user_io_oeb[6] ;
+ wire \user_io_oeb[7] ;
+ wire \user_io_oeb[8] ;
+ wire \user_io_oeb[9] ;
+ wire \user_io_out[0] ;
+ wire \user_io_out[10] ;
+ wire \user_io_out[11] ;
+ wire \user_io_out[12] ;
+ wire \user_io_out[13] ;
+ wire \user_io_out[14] ;
+ wire \user_io_out[15] ;
+ wire \user_io_out[16] ;
+ wire \user_io_out[17] ;
+ wire \user_io_out[18] ;
+ wire \user_io_out[19] ;
+ wire \user_io_out[1] ;
+ wire \user_io_out[20] ;
+ wire \user_io_out[21] ;
+ wire \user_io_out[22] ;
+ wire \user_io_out[23] ;
+ wire \user_io_out[24] ;
+ wire \user_io_out[25] ;
+ wire \user_io_out[26] ;
+ wire \user_io_out[27] ;
+ wire \user_io_out[28] ;
+ wire \user_io_out[29] ;
+ wire \user_io_out[2] ;
+ wire \user_io_out[30] ;
+ wire \user_io_out[31] ;
+ wire \user_io_out[32] ;
+ wire \user_io_out[33] ;
+ wire \user_io_out[34] ;
+ wire \user_io_out[35] ;
+ wire \user_io_out[36] ;
+ wire \user_io_out[37] ;
+ wire \user_io_out[3] ;
+ wire \user_io_out[4] ;
+ wire \user_io_out[5] ;
+ wire \user_io_out[6] ;
+ wire \user_io_out[7] ;
+ wire \user_io_out[8] ;
+ wire \user_io_out[9] ;
+ wire \user_irq[0] ;
+ wire \user_irq[1] ;
+ wire \user_irq[2] ;
+ wire \user_irq_core[0] ;
+ wire \user_irq_core[1] ;
+ wire \user_irq_core[2] ;
+ wire \user_irq_ena[0] ;
+ wire \user_irq_ena[1] ;
+ wire \user_irq_ena[2] ;
+ inout vccd;
+ inout vccd1;
+ wire vccd1_core;
+ inout vccd2;
+ wire vccd2_core;
+ wire vccd_core;
+ inout vdda;
+ inout vdda1;
+ inout vdda1_2;
+ wire vdda1_core;
+ inout vdda2;
+ wire vdda2_core;
+ wire vdda_core;
+ inout vddio;
+ inout vddio_2;
+ wire vddio_core;
+ inout vssa;
+ inout vssa1;
+ inout vssa1_2;
+ wire vssa1_core;
+ inout vssa2;
+ wire vssa2_core;
+ wire vssa_core;
+ inout vssd;
+ inout vssd1;
+ wire vssd1_core;
+ inout vssd2;
+ wire vssd2_core;
+ wire vssd_core;
+ inout vssio;
+ inout vssio_2;
+ wire vssio_core;
+ caravel_clocking \clocking (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .core_clk(caravel_clk),
+ .ext_clk(clock_core),
+ .ext_clk_sel(ext_clk_sel),
+ .ext_reset(ext_reset),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l),
+ .resetb_sync(caravel_rstn),
+ .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .user_clk(caravel_clk2)
+ );
+ gpio_defaults_block_1803 gpio_defaults_block_0 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] })
+ );
+ gpio_defaults_block_1803 \gpio_defaults_block_1 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] })
+ );
+ gpio_defaults_block gpio_defaults_block_10 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] })
+ );
+ gpio_defaults_block gpio_defaults_block_11 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] })
+ );
+ gpio_defaults_block gpio_defaults_block_12 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] })
+ );
+ gpio_defaults_block gpio_defaults_block_13 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] })
+ );
+ gpio_defaults_block gpio_defaults_block_14 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] })
+ );
+ gpio_defaults_block gpio_defaults_block_15 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] })
+ );
+ gpio_defaults_block gpio_defaults_block_16 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] })
+ );
+ gpio_defaults_block gpio_defaults_block_17 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] })
+ );
+ gpio_defaults_block gpio_defaults_block_18 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] })
+ );
+ gpio_defaults_block gpio_defaults_block_19 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] })
+ );
+ gpio_defaults_block gpio_defaults_block_20 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] })
+ );
+ gpio_defaults_block gpio_defaults_block_21 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] })
+ );
+ gpio_defaults_block gpio_defaults_block_22 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_2 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_3 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_4 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] })
+ );
+ gpio_defaults_block gpio_defaults_block_23 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] })
+ );
+ gpio_defaults_block gpio_defaults_block_24 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] })
+ );
+ gpio_defaults_block gpio_defaults_block_25 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] })
+ );
+ gpio_defaults_block gpio_defaults_block_26 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] })
+ );
+ gpio_defaults_block gpio_defaults_block_27 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351] })
+ );
+ gpio_defaults_block gpio_defaults_block_28 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364] })
+ );
+ gpio_defaults_block gpio_defaults_block_29 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377] })
+ );
+ gpio_defaults_block gpio_defaults_block_30 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390] })
+ );
+ gpio_defaults_block gpio_defaults_block_31 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403] })
+ );
+ gpio_defaults_block gpio_defaults_block_32 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416] })
+ );
+ gpio_defaults_block gpio_defaults_block_33 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429] })
+ );
+ gpio_defaults_block gpio_defaults_block_34 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442] })
+ );
+ gpio_defaults_block gpio_defaults_block_35 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455] })
+ );
+ gpio_defaults_block gpio_defaults_block_36 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468] })
+ );
+ gpio_defaults_block gpio_defaults_block_37 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481] })
+ );
+ gpio_defaults_block gpio_defaults_block_5 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] })
+ );
+ gpio_defaults_block gpio_defaults_block_6 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] })
+ );
+ gpio_defaults_block gpio_defaults_block_7 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] })
+ );
+ gpio_defaults_block gpio_defaults_block_8 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] })
+ );
+ gpio_defaults_block gpio_defaults_block_9 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] })
+ );
+ gpio_control_block \gpio_control_bidir_1[0] (
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] }),
+ .mgmt_gpio_in(\mgmt_io_in[0] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[0] ),
+ .mgmt_gpio_out(\mgmt_io_out[0] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+ .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .pad_gpio_holdover(\mprj_io_holdover[0] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+ .pad_gpio_in(\mprj_io_in[0] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+ .pad_gpio_out(\mprj_io_out[0] ),
+ .pad_gpio_outenb(\mprj_io_oeb[0] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+ .resetn(\gpio_resetn_1_shifted[0] ),
+ .resetn_out(\gpio_resetn_1[0] ),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_clock_out(\gpio_clock_1[0] ),
+ .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_out(\gpio_serial_link_1[0] ),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_load_out(\gpio_load_1[0] ),
+ .user_gpio_in(\user_io_in[0] ),
+ .user_gpio_oeb(\user_io_oeb[0] ),
+ .user_gpio_out(\user_io_out[0] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_1[1] (
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] }),
+ .mgmt_gpio_in(\mgmt_io_in[1] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[1] ),
+ .mgmt_gpio_out(\mgmt_io_out[1] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+ .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] }),
+ .pad_gpio_holdover(\mprj_io_holdover[1] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+ .pad_gpio_in(\mprj_io_in[1] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+ .pad_gpio_out(\mprj_io_out[1] ),
+ .pad_gpio_outenb(\mprj_io_oeb[1] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+ .resetn(\gpio_resetn_1[0] ),
+ .resetn_out(\gpio_resetn_1[1] ),
+ .serial_clock(\gpio_clock_1[0] ),
+ .serial_clock_out(\gpio_clock_1[1] ),
+ .serial_data_in(\gpio_serial_link_1[0] ),
+ .serial_data_out(\gpio_serial_link_1[1] ),
+ .serial_load(\gpio_load_1[0] ),
+ .serial_load_out(\gpio_load_1[1] ),
+ .user_gpio_in(\user_io_in[1] ),
+ .user_gpio_oeb(\user_io_oeb[1] ),
+ .user_gpio_out(\user_io_out[1] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[0] (
+ .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455] }),
+ .mgmt_gpio_in(\mgmt_io_in[35] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[2] ),
+ .mgmt_gpio_out(\mgmt_io_out[2] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[35] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[35] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[35] ),
+ .pad_gpio_dm({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] }),
+ .pad_gpio_holdover(\mprj_io_holdover[35] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[35] ),
+ .pad_gpio_in(\mprj_io_in[35] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[35] ),
+ .pad_gpio_out(\mprj_io_out[35] ),
+ .pad_gpio_outenb(\mprj_io_oeb[35] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[35] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[35] ),
+ .resetn(\gpio_resetn_2[17] ),
+ .resetn_out(\gpio_resetn_2[16] ),
+ .serial_clock(\gpio_clock_2[17] ),
+ .serial_clock_out(\gpio_clock_2[16] ),
+ .serial_data_in(\gpio_serial_link_2[17] ),
+ .serial_data_out(\gpio_serial_link_2[16] ),
+ .serial_load(\gpio_load_2[17] ),
+ .serial_load_out(\gpio_load_2[16] ),
+ .user_gpio_in(\user_io_in[35] ),
+ .user_gpio_oeb(\user_io_oeb[35] ),
+ .user_gpio_out(\user_io_out[35] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[1] (
+ .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468] }),
+ .mgmt_gpio_in(\mgmt_io_in[36] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[3] ),
+ .mgmt_gpio_out(\mgmt_io_out[3] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[36] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[36] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[36] ),
+ .pad_gpio_dm({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] }),
+ .pad_gpio_holdover(\mprj_io_holdover[36] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[36] ),
+ .pad_gpio_in(\mprj_io_in[36] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[36] ),
+ .pad_gpio_out(\mprj_io_out[36] ),
+ .pad_gpio_outenb(\mprj_io_oeb[36] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[36] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[36] ),
+ .resetn(\gpio_resetn_2[18] ),
+ .resetn_out(\gpio_resetn_2[17] ),
+ .serial_clock(\gpio_clock_2[18] ),
+ .serial_clock_out(\gpio_clock_2[17] ),
+ .serial_data_in(\gpio_serial_link_2[18] ),
+ .serial_data_out(\gpio_serial_link_2[17] ),
+ .serial_load(\gpio_load_2[18] ),
+ .serial_load_out(\gpio_load_2[17] ),
+ .user_gpio_in(\user_io_in[36] ),
+ .user_gpio_oeb(\user_io_oeb[36] ),
+ .user_gpio_out(\user_io_out[36] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[2] (
+ .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481] }),
+ .mgmt_gpio_in(\mgmt_io_in[37] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[4] ),
+ .mgmt_gpio_out(\mgmt_io_out[4] ),
+ .one(),
+ .pad_gpio_ana_en(\mprj_io_analog_en[37] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[37] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[37] ),
+ .pad_gpio_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] }),
+ .pad_gpio_holdover(\mprj_io_holdover[37] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[37] ),
+ .pad_gpio_in(\mprj_io_in[37] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[37] ),
+ .pad_gpio_out(\mprj_io_out[37] ),
+ .pad_gpio_outenb(\mprj_io_oeb[37] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[37] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[37] ),
+ .resetn(\gpio_resetn_2_shifted[18] ),
+ .resetn_out(\gpio_resetn_2[18] ),
+ .serial_clock(\gpio_clock_2_shifted[18] ),
+ .serial_clock_out(\gpio_clock_2[18] ),
+ .serial_data_in(\gpio_serial_link_2_shifted[18] ),
+ .serial_data_out(\gpio_serial_link_2[18] ),
+ .serial_load(\gpio_load_2_shifted[18] ),
+ .serial_load_out(\gpio_load_2[18] ),
+ .user_gpio_in(\user_io_in[37] ),
+ .user_gpio_oeb(\user_io_oeb[37] ),
+ .user_gpio_out(\user_io_out[37] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[0] (
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] }),
+ .mgmt_gpio_in(\mgmt_io_in[8] ),
+ .mgmt_gpio_oeb(\one_loop1[8] ),
+ .mgmt_gpio_out(\mgmt_io_in[8] ),
+ .one(\one_loop1[8] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+ .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] }),
+ .pad_gpio_holdover(\mprj_io_holdover[8] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+ .pad_gpio_in(\mprj_io_in[8] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+ .pad_gpio_out(\mprj_io_out[8] ),
+ .pad_gpio_outenb(\mprj_io_oeb[8] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+ .resetn(\gpio_resetn_1[7] ),
+ .resetn_out(\gpio_resetn_1[8] ),
+ .serial_clock(\gpio_clock_1[7] ),
+ .serial_clock_out(\gpio_clock_1[8] ),
+ .serial_data_in(\gpio_serial_link_1[7] ),
+ .serial_data_out(\gpio_serial_link_1[8] ),
+ .serial_load(\gpio_load_1[7] ),
+ .serial_load_out(\gpio_load_1[8] ),
+ .user_gpio_in(\user_io_in[8] ),
+ .user_gpio_oeb(\user_io_oeb[8] ),
+ .user_gpio_out(\user_io_out[8] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[10] (
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] }),
+ .mgmt_gpio_in(\mgmt_io_in[18] ),
+ .mgmt_gpio_oeb(\one_loop1[18] ),
+ .mgmt_gpio_out(\mgmt_io_in[18] ),
+ .one(\one_loop1[18] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+ .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] }),
+ .pad_gpio_holdover(\mprj_io_holdover[18] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+ .pad_gpio_in(\mprj_io_in[18] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+ .pad_gpio_out(\mprj_io_out[18] ),
+ .pad_gpio_outenb(\mprj_io_oeb[18] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+ .resetn(\gpio_resetn_1[17] ),
+ .resetn_out(\gpio_resetn_1[18] ),
+ .serial_clock(\gpio_clock_1[17] ),
+ .serial_clock_out(\gpio_clock_1[18] ),
+ .serial_data_in(\gpio_serial_link_1[17] ),
+ .serial_data_out(\gpio_serial_link_1[18] ),
+ .serial_load(\gpio_load_1[17] ),
+ .serial_load_out(\gpio_load_1[18] ),
+ .user_gpio_in(\user_io_in[18] ),
+ .user_gpio_oeb(\user_io_oeb[18] ),
+ .user_gpio_out(\user_io_out[18] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[1] (
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] }),
+ .mgmt_gpio_in(\mgmt_io_in[9] ),
+ .mgmt_gpio_oeb(\one_loop1[9] ),
+ .mgmt_gpio_out(\mgmt_io_in[9] ),
+ .one(\one_loop1[9] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+ .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] }),
+ .pad_gpio_holdover(\mprj_io_holdover[9] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+ .pad_gpio_in(\mprj_io_in[9] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+ .pad_gpio_out(\mprj_io_out[9] ),
+ .pad_gpio_outenb(\mprj_io_oeb[9] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+ .resetn(\gpio_resetn_1[8] ),
+ .resetn_out(\gpio_resetn_1[9] ),
+ .serial_clock(\gpio_clock_1[8] ),
+ .serial_clock_out(\gpio_clock_1[9] ),
+ .serial_data_in(\gpio_serial_link_1[8] ),
+ .serial_data_out(\gpio_serial_link_1[9] ),
+ .serial_load(\gpio_load_1[8] ),
+ .serial_load_out(\gpio_load_1[9] ),
+ .user_gpio_in(\user_io_in[9] ),
+ .user_gpio_oeb(\user_io_oeb[9] ),
+ .user_gpio_out(\user_io_out[9] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[2] (
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] }),
+ .mgmt_gpio_in(\mgmt_io_in[10] ),
+ .mgmt_gpio_oeb(\one_loop1[10] ),
+ .mgmt_gpio_out(\mgmt_io_in[10] ),
+ .one(\one_loop1[10] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+ .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] }),
+ .pad_gpio_holdover(\mprj_io_holdover[10] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+ .pad_gpio_in(\mprj_io_in[10] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+ .pad_gpio_out(\mprj_io_out[10] ),
+ .pad_gpio_outenb(\mprj_io_oeb[10] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+ .resetn(\gpio_resetn_1[9] ),
+ .resetn_out(\gpio_resetn_1[10] ),
+ .serial_clock(\gpio_clock_1[9] ),
+ .serial_clock_out(\gpio_clock_1[10] ),
+ .serial_data_in(\gpio_serial_link_1[9] ),
+ .serial_data_out(\gpio_serial_link_1[10] ),
+ .serial_load(\gpio_load_1[9] ),
+ .serial_load_out(\gpio_load_1[10] ),
+ .user_gpio_in(\user_io_in[10] ),
+ .user_gpio_oeb(\user_io_oeb[10] ),
+ .user_gpio_out(\user_io_out[10] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[3] (
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] }),
+ .mgmt_gpio_in(\mgmt_io_in[11] ),
+ .mgmt_gpio_oeb(\one_loop1[11] ),
+ .mgmt_gpio_out(\mgmt_io_in[11] ),
+ .one(\one_loop1[11] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+ .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] }),
+ .pad_gpio_holdover(\mprj_io_holdover[11] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+ .pad_gpio_in(\mprj_io_in[11] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+ .pad_gpio_out(\mprj_io_out[11] ),
+ .pad_gpio_outenb(\mprj_io_oeb[11] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+ .resetn(\gpio_resetn_1[10] ),
+ .resetn_out(\gpio_resetn_1[11] ),
+ .serial_clock(\gpio_clock_1[10] ),
+ .serial_clock_out(\gpio_clock_1[11] ),
+ .serial_data_in(\gpio_serial_link_1[10] ),
+ .serial_data_out(\gpio_serial_link_1[11] ),
+ .serial_load(\gpio_load_1[10] ),
+ .serial_load_out(\gpio_load_1[11] ),
+ .user_gpio_in(\user_io_in[11] ),
+ .user_gpio_oeb(\user_io_oeb[11] ),
+ .user_gpio_out(\user_io_out[11] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[4] (
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] }),
+ .mgmt_gpio_in(\mgmt_io_in[12] ),
+ .mgmt_gpio_oeb(\one_loop1[12] ),
+ .mgmt_gpio_out(\mgmt_io_in[12] ),
+ .one(\one_loop1[12] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+ .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] }),
+ .pad_gpio_holdover(\mprj_io_holdover[12] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+ .pad_gpio_in(\mprj_io_in[12] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+ .pad_gpio_out(\mprj_io_out[12] ),
+ .pad_gpio_outenb(\mprj_io_oeb[12] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+ .resetn(\gpio_resetn_1[11] ),
+ .resetn_out(\gpio_resetn_1[12] ),
+ .serial_clock(\gpio_clock_1[11] ),
+ .serial_clock_out(\gpio_clock_1[12] ),
+ .serial_data_in(\gpio_serial_link_1[11] ),
+ .serial_data_out(\gpio_serial_link_1[12] ),
+ .serial_load(\gpio_load_1[11] ),
+ .serial_load_out(\gpio_load_1[12] ),
+ .user_gpio_in(\user_io_in[12] ),
+ .user_gpio_oeb(\user_io_oeb[12] ),
+ .user_gpio_out(\user_io_out[12] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[5] (
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] }),
+ .mgmt_gpio_in(\mgmt_io_in[13] ),
+ .mgmt_gpio_oeb(\one_loop1[13] ),
+ .mgmt_gpio_out(\mgmt_io_in[13] ),
+ .one(\one_loop1[13] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+ .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] }),
+ .pad_gpio_holdover(\mprj_io_holdover[13] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+ .pad_gpio_in(\mprj_io_in[13] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+ .pad_gpio_out(\mprj_io_out[13] ),
+ .pad_gpio_outenb(\mprj_io_oeb[13] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+ .resetn(\gpio_resetn_1[12] ),
+ .resetn_out(\gpio_resetn_1[13] ),
+ .serial_clock(\gpio_clock_1[12] ),
+ .serial_clock_out(\gpio_clock_1[13] ),
+ .serial_data_in(\gpio_serial_link_1[12] ),
+ .serial_data_out(\gpio_serial_link_1[13] ),
+ .serial_load(\gpio_load_1[12] ),
+ .serial_load_out(\gpio_load_1[13] ),
+ .user_gpio_in(\user_io_in[13] ),
+ .user_gpio_oeb(\user_io_oeb[13] ),
+ .user_gpio_out(\user_io_out[13] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[6] (
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] }),
+ .mgmt_gpio_in(\mgmt_io_in[14] ),
+ .mgmt_gpio_oeb(\one_loop1[14] ),
+ .mgmt_gpio_out(\mgmt_io_in[14] ),
+ .one(\one_loop1[14] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+ .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] }),
+ .pad_gpio_holdover(\mprj_io_holdover[14] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+ .pad_gpio_in(\mprj_io_in[14] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+ .pad_gpio_out(\mprj_io_out[14] ),
+ .pad_gpio_outenb(\mprj_io_oeb[14] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+ .resetn(\gpio_resetn_1[13] ),
+ .resetn_out(\gpio_resetn_1[14] ),
+ .serial_clock(\gpio_clock_1[13] ),
+ .serial_clock_out(\gpio_clock_1[14] ),
+ .serial_data_in(\gpio_serial_link_1[13] ),
+ .serial_data_out(\gpio_serial_link_1[14] ),
+ .serial_load(\gpio_load_1[13] ),
+ .serial_load_out(\gpio_load_1[14] ),
+ .user_gpio_in(\user_io_in[14] ),
+ .user_gpio_oeb(\user_io_oeb[14] ),
+ .user_gpio_out(\user_io_out[14] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[7] (
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] }),
+ .mgmt_gpio_in(\mgmt_io_in[15] ),
+ .mgmt_gpio_oeb(\one_loop1[15] ),
+ .mgmt_gpio_out(\mgmt_io_in[15] ),
+ .one(\one_loop1[15] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+ .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] }),
+ .pad_gpio_holdover(\mprj_io_holdover[15] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+ .pad_gpio_in(\mprj_io_in[15] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+ .pad_gpio_out(\mprj_io_out[15] ),
+ .pad_gpio_outenb(\mprj_io_oeb[15] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+ .resetn(\gpio_resetn_1[14] ),
+ .resetn_out(\gpio_resetn_1[15] ),
+ .serial_clock(\gpio_clock_1[14] ),
+ .serial_clock_out(\gpio_clock_1[15] ),
+ .serial_data_in(\gpio_serial_link_1[14] ),
+ .serial_data_out(\gpio_serial_link_1[15] ),
+ .serial_load(\gpio_load_1[14] ),
+ .serial_load_out(\gpio_load_1[15] ),
+ .user_gpio_in(\user_io_in[15] ),
+ .user_gpio_oeb(\user_io_oeb[15] ),
+ .user_gpio_out(\user_io_out[15] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[8] (
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] }),
+ .mgmt_gpio_in(\mgmt_io_in[16] ),
+ .mgmt_gpio_oeb(\one_loop1[16] ),
+ .mgmt_gpio_out(\mgmt_io_in[16] ),
+ .one(\one_loop1[16] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+ .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] }),
+ .pad_gpio_holdover(\mprj_io_holdover[16] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+ .pad_gpio_in(\mprj_io_in[16] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+ .pad_gpio_out(\mprj_io_out[16] ),
+ .pad_gpio_outenb(\mprj_io_oeb[16] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+ .resetn(\gpio_resetn_1[15] ),
+ .resetn_out(\gpio_resetn_1[16] ),
+ .serial_clock(\gpio_clock_1[15] ),
+ .serial_clock_out(\gpio_clock_1[16] ),
+ .serial_data_in(\gpio_serial_link_1[15] ),
+ .serial_data_out(\gpio_serial_link_1[16] ),
+ .serial_load(\gpio_load_1[15] ),
+ .serial_load_out(\gpio_load_1[16] ),
+ .user_gpio_in(\user_io_in[16] ),
+ .user_gpio_oeb(\user_io_oeb[16] ),
+ .user_gpio_out(\user_io_out[16] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[9] (
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] }),
+ .mgmt_gpio_in(\mgmt_io_in[17] ),
+ .mgmt_gpio_oeb(\one_loop1[17] ),
+ .mgmt_gpio_out(\mgmt_io_in[17] ),
+ .one(\one_loop1[17] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+ .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] }),
+ .pad_gpio_holdover(\mprj_io_holdover[17] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+ .pad_gpio_in(\mprj_io_in[17] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+ .pad_gpio_out(\mprj_io_out[17] ),
+ .pad_gpio_outenb(\mprj_io_oeb[17] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+ .resetn(\gpio_resetn_1[16] ),
+ .resetn_out(\gpio_resetn_1[17] ),
+ .serial_clock(\gpio_clock_1[16] ),
+ .serial_clock_out(\gpio_clock_1[17] ),
+ .serial_data_in(\gpio_serial_link_1[16] ),
+ .serial_data_out(\gpio_serial_link_1[17] ),
+ .serial_load(\gpio_load_1[16] ),
+ .serial_load_out(\gpio_load_1[17] ),
+ .user_gpio_in(\user_io_in[17] ),
+ .user_gpio_oeb(\user_io_oeb[17] ),
+ .user_gpio_out(\user_io_out[17] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[0] (
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] }),
+ .mgmt_gpio_in(\mgmt_io_in[2] ),
+ .mgmt_gpio_oeb(\one_loop1[2] ),
+ .mgmt_gpio_out(\mgmt_io_in[2] ),
+ .one(\one_loop1[2] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+ .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] }),
+ .pad_gpio_holdover(\mprj_io_holdover[2] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+ .pad_gpio_in(\mprj_io_in[2] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+ .pad_gpio_out(\mprj_io_out[2] ),
+ .pad_gpio_outenb(\mprj_io_oeb[2] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+ .resetn(\gpio_resetn_1[1] ),
+ .resetn_out(\gpio_resetn_1[2] ),
+ .serial_clock(\gpio_clock_1[1] ),
+ .serial_clock_out(\gpio_clock_1[2] ),
+ .serial_data_in(\gpio_serial_link_1[1] ),
+ .serial_data_out(\gpio_serial_link_1[2] ),
+ .serial_load(\gpio_load_1[1] ),
+ .serial_load_out(\gpio_load_1[2] ),
+ .user_gpio_in(\user_io_in[2] ),
+ .user_gpio_oeb(\user_io_oeb[2] ),
+ .user_gpio_out(\user_io_out[2] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[1] (
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] }),
+ .mgmt_gpio_in(\mgmt_io_in[3] ),
+ .mgmt_gpio_oeb(\one_loop1[3] ),
+ .mgmt_gpio_out(\mgmt_io_in[3] ),
+ .one(\one_loop1[3] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+ .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] }),
+ .pad_gpio_holdover(\mprj_io_holdover[3] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+ .pad_gpio_in(\mprj_io_in[3] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+ .pad_gpio_out(\mprj_io_out[3] ),
+ .pad_gpio_outenb(\mprj_io_oeb[3] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+ .resetn(\gpio_resetn_1[2] ),
+ .resetn_out(\gpio_resetn_1[3] ),
+ .serial_clock(\gpio_clock_1[2] ),
+ .serial_clock_out(\gpio_clock_1[3] ),
+ .serial_data_in(\gpio_serial_link_1[2] ),
+ .serial_data_out(\gpio_serial_link_1[3] ),
+ .serial_load(\gpio_load_1[2] ),
+ .serial_load_out(\gpio_load_1[3] ),
+ .user_gpio_in(\user_io_in[3] ),
+ .user_gpio_oeb(\user_io_oeb[3] ),
+ .user_gpio_out(\user_io_out[3] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[2] (
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] }),
+ .mgmt_gpio_in(\mgmt_io_in[4] ),
+ .mgmt_gpio_oeb(\one_loop1[4] ),
+ .mgmt_gpio_out(\mgmt_io_in[4] ),
+ .one(\one_loop1[4] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+ .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] }),
+ .pad_gpio_holdover(\mprj_io_holdover[4] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+ .pad_gpio_in(\mprj_io_in[4] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+ .pad_gpio_out(\mprj_io_out[4] ),
+ .pad_gpio_outenb(\mprj_io_oeb[4] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+ .resetn(\gpio_resetn_1[3] ),
+ .resetn_out(\gpio_resetn_1[4] ),
+ .serial_clock(\gpio_clock_1[3] ),
+ .serial_clock_out(\gpio_clock_1[4] ),
+ .serial_data_in(\gpio_serial_link_1[3] ),
+ .serial_data_out(\gpio_serial_link_1[4] ),
+ .serial_load(\gpio_load_1[3] ),
+ .serial_load_out(\gpio_load_1[4] ),
+ .user_gpio_in(\user_io_in[4] ),
+ .user_gpio_oeb(\user_io_oeb[4] ),
+ .user_gpio_out(\user_io_out[4] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[3] (
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] }),
+ .mgmt_gpio_in(\mgmt_io_in[5] ),
+ .mgmt_gpio_oeb(\one_loop1[5] ),
+ .mgmt_gpio_out(\mgmt_io_in[5] ),
+ .one(\one_loop1[5] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+ .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] }),
+ .pad_gpio_holdover(\mprj_io_holdover[5] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+ .pad_gpio_in(\mprj_io_in[5] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+ .pad_gpio_out(\mprj_io_out[5] ),
+ .pad_gpio_outenb(\mprj_io_oeb[5] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+ .resetn(\gpio_resetn_1[4] ),
+ .resetn_out(\gpio_resetn_1[5] ),
+ .serial_clock(\gpio_clock_1[4] ),
+ .serial_clock_out(\gpio_clock_1[5] ),
+ .serial_data_in(\gpio_serial_link_1[4] ),
+ .serial_data_out(\gpio_serial_link_1[5] ),
+ .serial_load(\gpio_load_1[4] ),
+ .serial_load_out(\gpio_load_1[5] ),
+ .user_gpio_in(\user_io_in[5] ),
+ .user_gpio_oeb(\user_io_oeb[5] ),
+ .user_gpio_out(\user_io_out[5] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[4] (
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] }),
+ .mgmt_gpio_in(\mgmt_io_in[6] ),
+ .mgmt_gpio_oeb(\one_loop1[6] ),
+ .mgmt_gpio_out(\mgmt_io_in[6] ),
+ .one(\one_loop1[6] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+ .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] }),
+ .pad_gpio_holdover(\mprj_io_holdover[6] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+ .pad_gpio_in(\mprj_io_in[6] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+ .pad_gpio_out(\mprj_io_out[6] ),
+ .pad_gpio_outenb(\mprj_io_oeb[6] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+ .resetn(\gpio_resetn_1[5] ),
+ .resetn_out(\gpio_resetn_1[6] ),
+ .serial_clock(\gpio_clock_1[5] ),
+ .serial_clock_out(\gpio_clock_1[6] ),
+ .serial_data_in(\gpio_serial_link_1[5] ),
+ .serial_data_out(\gpio_serial_link_1[6] ),
+ .serial_load(\gpio_load_1[5] ),
+ .serial_load_out(\gpio_load_1[6] ),
+ .user_gpio_in(\user_io_in[6] ),
+ .user_gpio_oeb(\user_io_oeb[6] ),
+ .user_gpio_out(\user_io_out[6] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[5] (
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] }),
+ .mgmt_gpio_in(\mgmt_io_in[7] ),
+ .mgmt_gpio_oeb(\one_loop1[7] ),
+ .mgmt_gpio_out(\mgmt_io_in[7] ),
+ .one(\one_loop1[7] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+ .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] }),
+ .pad_gpio_holdover(\mprj_io_holdover[7] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+ .pad_gpio_in(\mprj_io_in[7] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+ .pad_gpio_out(\mprj_io_out[7] ),
+ .pad_gpio_outenb(\mprj_io_oeb[7] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+ .resetn(\gpio_resetn_1[6] ),
+ .resetn_out(\gpio_resetn_1[7] ),
+ .serial_clock(\gpio_clock_1[6] ),
+ .serial_clock_out(\gpio_clock_1[7] ),
+ .serial_data_in(\gpio_serial_link_1[6] ),
+ .serial_data_out(\gpio_serial_link_1[7] ),
+ .serial_load(\gpio_load_1[6] ),
+ .serial_load_out(\gpio_load_1[7] ),
+ .user_gpio_in(\user_io_in[7] ),
+ .user_gpio_oeb(\user_io_oeb[7] ),
+ .user_gpio_out(\user_io_out[7] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[0] (
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] }),
+ .mgmt_gpio_in(\mgmt_io_in[19] ),
+ .mgmt_gpio_oeb(\one_loop2[0] ),
+ .mgmt_gpio_out(\mgmt_io_in[19] ),
+ .one(\one_loop2[0] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+ .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] }),
+ .pad_gpio_holdover(\mprj_io_holdover[19] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+ .pad_gpio_in(\mprj_io_in[19] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+ .pad_gpio_out(\mprj_io_out[19] ),
+ .pad_gpio_outenb(\mprj_io_oeb[19] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+ .resetn(\gpio_resetn_2[1] ),
+ .resetn_out(\gpio_resetn_2[0] ),
+ .serial_clock(\gpio_clock_2[1] ),
+ .serial_clock_out(\gpio_clock_2[0] ),
+ .serial_data_in(\gpio_serial_link_2[1] ),
+ .serial_data_out(\gpio_serial_link_2[0] ),
+ .serial_load(\gpio_load_2[1] ),
+ .serial_load_out(\gpio_load_2[0] ),
+ .user_gpio_in(\user_io_in[19] ),
+ .user_gpio_oeb(\user_io_oeb[19] ),
+ .user_gpio_out(\user_io_out[19] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[10] (
+ .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377] }),
+ .mgmt_gpio_in(\mgmt_io_in[29] ),
+ .mgmt_gpio_oeb(\one_loop2[10] ),
+ .mgmt_gpio_out(\mgmt_io_in[29] ),
+ .one(\one_loop2[10] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[29] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[29] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[29] ),
+ .pad_gpio_dm({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] }),
+ .pad_gpio_holdover(\mprj_io_holdover[29] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[29] ),
+ .pad_gpio_in(\mprj_io_in[29] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[29] ),
+ .pad_gpio_out(\mprj_io_out[29] ),
+ .pad_gpio_outenb(\mprj_io_oeb[29] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[29] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[29] ),
+ .resetn(\gpio_resetn_2[11] ),
+ .resetn_out(\gpio_resetn_2[10] ),
+ .serial_clock(\gpio_clock_2[11] ),
+ .serial_clock_out(\gpio_clock_2[10] ),
+ .serial_data_in(\gpio_serial_link_2[11] ),
+ .serial_data_out(\gpio_serial_link_2[10] ),
+ .serial_load(\gpio_load_2[11] ),
+ .serial_load_out(\gpio_load_2[10] ),
+ .user_gpio_in(\user_io_in[29] ),
+ .user_gpio_oeb(\user_io_oeb[29] ),
+ .user_gpio_out(\user_io_out[29] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[11] (
+ .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390] }),
+ .mgmt_gpio_in(\mgmt_io_in[30] ),
+ .mgmt_gpio_oeb(\one_loop2[11] ),
+ .mgmt_gpio_out(\mgmt_io_in[30] ),
+ .one(\one_loop2[11] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[30] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[30] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[30] ),
+ .pad_gpio_dm({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] }),
+ .pad_gpio_holdover(\mprj_io_holdover[30] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[30] ),
+ .pad_gpio_in(\mprj_io_in[30] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[30] ),
+ .pad_gpio_out(\mprj_io_out[30] ),
+ .pad_gpio_outenb(\mprj_io_oeb[30] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[30] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[30] ),
+ .resetn(\gpio_resetn_2[12] ),
+ .resetn_out(\gpio_resetn_2[11] ),
+ .serial_clock(\gpio_clock_2[12] ),
+ .serial_clock_out(\gpio_clock_2[11] ),
+ .serial_data_in(\gpio_serial_link_2[12] ),
+ .serial_data_out(\gpio_serial_link_2[11] ),
+ .serial_load(\gpio_load_2[12] ),
+ .serial_load_out(\gpio_load_2[11] ),
+ .user_gpio_in(\user_io_in[30] ),
+ .user_gpio_oeb(\user_io_oeb[30] ),
+ .user_gpio_out(\user_io_out[30] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[12] (
+ .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403] }),
+ .mgmt_gpio_in(\mgmt_io_in[31] ),
+ .mgmt_gpio_oeb(\one_loop2[12] ),
+ .mgmt_gpio_out(\mgmt_io_in[31] ),
+ .one(\one_loop2[12] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[31] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[31] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[31] ),
+ .pad_gpio_dm({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] }),
+ .pad_gpio_holdover(\mprj_io_holdover[31] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[31] ),
+ .pad_gpio_in(\mprj_io_in[31] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[31] ),
+ .pad_gpio_out(\mprj_io_out[31] ),
+ .pad_gpio_outenb(\mprj_io_oeb[31] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[31] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[31] ),
+ .resetn(\gpio_resetn_2[13] ),
+ .resetn_out(\gpio_resetn_2[12] ),
+ .serial_clock(\gpio_clock_2[13] ),
+ .serial_clock_out(\gpio_clock_2[12] ),
+ .serial_data_in(\gpio_serial_link_2[13] ),
+ .serial_data_out(\gpio_serial_link_2[12] ),
+ .serial_load(\gpio_load_2[13] ),
+ .serial_load_out(\gpio_load_2[12] ),
+ .user_gpio_in(\user_io_in[31] ),
+ .user_gpio_oeb(\user_io_oeb[31] ),
+ .user_gpio_out(\user_io_out[31] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[13] (
+ .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416] }),
+ .mgmt_gpio_in(\mgmt_io_in[32] ),
+ .mgmt_gpio_oeb(\one_loop2[13] ),
+ .mgmt_gpio_out(\mgmt_io_in[32] ),
+ .one(\one_loop2[13] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[32] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[32] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[32] ),
+ .pad_gpio_dm({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] }),
+ .pad_gpio_holdover(\mprj_io_holdover[32] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[32] ),
+ .pad_gpio_in(\mprj_io_in[32] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[32] ),
+ .pad_gpio_out(\mprj_io_out[32] ),
+ .pad_gpio_outenb(\mprj_io_oeb[32] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[32] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[32] ),
+ .resetn(\gpio_resetn_2[14] ),
+ .resetn_out(\gpio_resetn_2[13] ),
+ .serial_clock(\gpio_clock_2[14] ),
+ .serial_clock_out(\gpio_clock_2[13] ),
+ .serial_data_in(\gpio_serial_link_2[14] ),
+ .serial_data_out(\gpio_serial_link_2[13] ),
+ .serial_load(\gpio_load_2[14] ),
+ .serial_load_out(\gpio_load_2[13] ),
+ .user_gpio_in(\user_io_in[32] ),
+ .user_gpio_oeb(\user_io_oeb[32] ),
+ .user_gpio_out(\user_io_out[32] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[14] (
+ .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429] }),
+ .mgmt_gpio_in(\mgmt_io_in[33] ),
+ .mgmt_gpio_oeb(\one_loop2[14] ),
+ .mgmt_gpio_out(\mgmt_io_in[33] ),
+ .one(\one_loop2[14] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[33] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[33] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[33] ),
+ .pad_gpio_dm({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] }),
+ .pad_gpio_holdover(\mprj_io_holdover[33] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[33] ),
+ .pad_gpio_in(\mprj_io_in[33] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[33] ),
+ .pad_gpio_out(\mprj_io_out[33] ),
+ .pad_gpio_outenb(\mprj_io_oeb[33] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[33] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[33] ),
+ .resetn(\gpio_resetn_2[15] ),
+ .resetn_out(\gpio_resetn_2[14] ),
+ .serial_clock(\gpio_clock_2[15] ),
+ .serial_clock_out(\gpio_clock_2[14] ),
+ .serial_data_in(\gpio_serial_link_2[15] ),
+ .serial_data_out(\gpio_serial_link_2[14] ),
+ .serial_load(\gpio_load_2[15] ),
+ .serial_load_out(\gpio_load_2[14] ),
+ .user_gpio_in(\user_io_in[33] ),
+ .user_gpio_oeb(\user_io_oeb[33] ),
+ .user_gpio_out(\user_io_out[33] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[15] (
+ .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442] }),
+ .mgmt_gpio_in(\mgmt_io_in[34] ),
+ .mgmt_gpio_oeb(\one_loop2[15] ),
+ .mgmt_gpio_out(\mgmt_io_in[34] ),
+ .one(\one_loop2[15] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[34] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[34] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[34] ),
+ .pad_gpio_dm({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] }),
+ .pad_gpio_holdover(\mprj_io_holdover[34] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[34] ),
+ .pad_gpio_in(\mprj_io_in[34] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[34] ),
+ .pad_gpio_out(\mprj_io_out[34] ),
+ .pad_gpio_outenb(\mprj_io_oeb[34] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[34] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[34] ),
+ .resetn(\gpio_resetn_2[16] ),
+ .resetn_out(\gpio_resetn_2[15] ),
+ .serial_clock(\gpio_clock_2[16] ),
+ .serial_clock_out(\gpio_clock_2[15] ),
+ .serial_data_in(\gpio_serial_link_2[16] ),
+ .serial_data_out(\gpio_serial_link_2[15] ),
+ .serial_load(\gpio_load_2[16] ),
+ .serial_load_out(\gpio_load_2[15] ),
+ .user_gpio_in(\user_io_in[34] ),
+ .user_gpio_oeb(\user_io_oeb[34] ),
+ .user_gpio_out(\user_io_out[34] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[1] (
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] }),
+ .mgmt_gpio_in(\mgmt_io_in[20] ),
+ .mgmt_gpio_oeb(\one_loop2[1] ),
+ .mgmt_gpio_out(\mgmt_io_in[20] ),
+ .one(\one_loop2[1] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+ .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] }),
+ .pad_gpio_holdover(\mprj_io_holdover[20] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+ .pad_gpio_in(\mprj_io_in[20] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+ .pad_gpio_out(\mprj_io_out[20] ),
+ .pad_gpio_outenb(\mprj_io_oeb[20] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+ .resetn(\gpio_resetn_2[2] ),
+ .resetn_out(\gpio_resetn_2[1] ),
+ .serial_clock(\gpio_clock_2[2] ),
+ .serial_clock_out(\gpio_clock_2[1] ),
+ .serial_data_in(\gpio_serial_link_2[2] ),
+ .serial_data_out(\gpio_serial_link_2[1] ),
+ .serial_load(\gpio_load_2[2] ),
+ .serial_load_out(\gpio_load_2[1] ),
+ .user_gpio_in(\user_io_in[20] ),
+ .user_gpio_oeb(\user_io_oeb[20] ),
+ .user_gpio_out(\user_io_out[20] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[2] (
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] }),
+ .mgmt_gpio_in(\mgmt_io_in[21] ),
+ .mgmt_gpio_oeb(\one_loop2[2] ),
+ .mgmt_gpio_out(\mgmt_io_in[21] ),
+ .one(\one_loop2[2] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+ .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] }),
+ .pad_gpio_holdover(\mprj_io_holdover[21] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+ .pad_gpio_in(\mprj_io_in[21] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+ .pad_gpio_out(\mprj_io_out[21] ),
+ .pad_gpio_outenb(\mprj_io_oeb[21] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+ .resetn(\gpio_resetn_2[3] ),
+ .resetn_out(\gpio_resetn_2[2] ),
+ .serial_clock(\gpio_clock_2[3] ),
+ .serial_clock_out(\gpio_clock_2[2] ),
+ .serial_data_in(\gpio_serial_link_2[3] ),
+ .serial_data_out(\gpio_serial_link_2[2] ),
+ .serial_load(\gpio_load_2[3] ),
+ .serial_load_out(\gpio_load_2[2] ),
+ .user_gpio_in(\user_io_in[21] ),
+ .user_gpio_oeb(\user_io_oeb[21] ),
+ .user_gpio_out(\user_io_out[21] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[3] (
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] }),
+ .mgmt_gpio_in(\mgmt_io_in[22] ),
+ .mgmt_gpio_oeb(\one_loop2[3] ),
+ .mgmt_gpio_out(\mgmt_io_in[22] ),
+ .one(\one_loop2[3] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+ .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] }),
+ .pad_gpio_holdover(\mprj_io_holdover[22] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+ .pad_gpio_in(\mprj_io_in[22] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+ .pad_gpio_out(\mprj_io_out[22] ),
+ .pad_gpio_outenb(\mprj_io_oeb[22] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+ .resetn(\gpio_resetn_2[4] ),
+ .resetn_out(\gpio_resetn_2[3] ),
+ .serial_clock(\gpio_clock_2[4] ),
+ .serial_clock_out(\gpio_clock_2[3] ),
+ .serial_data_in(\gpio_serial_link_2[4] ),
+ .serial_data_out(\gpio_serial_link_2[3] ),
+ .serial_load(\gpio_load_2[4] ),
+ .serial_load_out(\gpio_load_2[3] ),
+ .user_gpio_in(\user_io_in[22] ),
+ .user_gpio_oeb(\user_io_oeb[22] ),
+ .user_gpio_out(\user_io_out[22] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[4] (
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] }),
+ .mgmt_gpio_in(\mgmt_io_in[23] ),
+ .mgmt_gpio_oeb(\one_loop2[4] ),
+ .mgmt_gpio_out(\mgmt_io_in[23] ),
+ .one(\one_loop2[4] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+ .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] }),
+ .pad_gpio_holdover(\mprj_io_holdover[23] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+ .pad_gpio_in(\mprj_io_in[23] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+ .pad_gpio_out(\mprj_io_out[23] ),
+ .pad_gpio_outenb(\mprj_io_oeb[23] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+ .resetn(\gpio_resetn_2[5] ),
+ .resetn_out(\gpio_resetn_2[4] ),
+ .serial_clock(\gpio_clock_2[5] ),
+ .serial_clock_out(\gpio_clock_2[4] ),
+ .serial_data_in(\gpio_serial_link_2[5] ),
+ .serial_data_out(\gpio_serial_link_2[4] ),
+ .serial_load(\gpio_load_2[5] ),
+ .serial_load_out(\gpio_load_2[4] ),
+ .user_gpio_in(\user_io_in[23] ),
+ .user_gpio_oeb(\user_io_oeb[23] ),
+ .user_gpio_out(\user_io_out[23] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[5] (
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] }),
+ .mgmt_gpio_in(\mgmt_io_in[24] ),
+ .mgmt_gpio_oeb(\one_loop2[5] ),
+ .mgmt_gpio_out(\mgmt_io_in[24] ),
+ .one(\one_loop2[5] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+ .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] }),
+ .pad_gpio_holdover(\mprj_io_holdover[24] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+ .pad_gpio_in(\mprj_io_in[24] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+ .pad_gpio_out(\mprj_io_out[24] ),
+ .pad_gpio_outenb(\mprj_io_oeb[24] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+ .resetn(\gpio_resetn_2[6] ),
+ .resetn_out(\gpio_resetn_2[5] ),
+ .serial_clock(\gpio_clock_2[6] ),
+ .serial_clock_out(\gpio_clock_2[5] ),
+ .serial_data_in(\gpio_serial_link_2[6] ),
+ .serial_data_out(\gpio_serial_link_2[5] ),
+ .serial_load(\gpio_load_2[6] ),
+ .serial_load_out(\gpio_load_2[5] ),
+ .user_gpio_in(\user_io_in[24] ),
+ .user_gpio_oeb(\user_io_oeb[24] ),
+ .user_gpio_out(\user_io_out[24] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[6] (
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] }),
+ .mgmt_gpio_in(\mgmt_io_in[25] ),
+ .mgmt_gpio_oeb(\one_loop2[6] ),
+ .mgmt_gpio_out(\mgmt_io_in[25] ),
+ .one(\one_loop2[6] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+ .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] }),
+ .pad_gpio_holdover(\mprj_io_holdover[25] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+ .pad_gpio_in(\mprj_io_in[25] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+ .pad_gpio_out(\mprj_io_out[25] ),
+ .pad_gpio_outenb(\mprj_io_oeb[25] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+ .resetn(\gpio_resetn_2[7] ),
+ .resetn_out(\gpio_resetn_2[6] ),
+ .serial_clock(\gpio_clock_2[7] ),
+ .serial_clock_out(\gpio_clock_2[6] ),
+ .serial_data_in(\gpio_serial_link_2[7] ),
+ .serial_data_out(\gpio_serial_link_2[6] ),
+ .serial_load(\gpio_load_2[7] ),
+ .serial_load_out(\gpio_load_2[6] ),
+ .user_gpio_in(\user_io_in[25] ),
+ .user_gpio_oeb(\user_io_oeb[25] ),
+ .user_gpio_out(\user_io_out[25] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[7] (
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] }),
+ .mgmt_gpio_in(\mgmt_io_in[26] ),
+ .mgmt_gpio_oeb(\one_loop2[7] ),
+ .mgmt_gpio_out(\mgmt_io_in[26] ),
+ .one(\one_loop2[7] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+ .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] }),
+ .pad_gpio_holdover(\mprj_io_holdover[26] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+ .pad_gpio_in(\mprj_io_in[26] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+ .pad_gpio_out(\mprj_io_out[26] ),
+ .pad_gpio_outenb(\mprj_io_oeb[26] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+ .resetn(\gpio_resetn_2[8] ),
+ .resetn_out(\gpio_resetn_2[7] ),
+ .serial_clock(\gpio_clock_2[8] ),
+ .serial_clock_out(\gpio_clock_2[7] ),
+ .serial_data_in(\gpio_serial_link_2[8] ),
+ .serial_data_out(\gpio_serial_link_2[7] ),
+ .serial_load(\gpio_load_2[8] ),
+ .serial_load_out(\gpio_load_2[7] ),
+ .user_gpio_in(\user_io_in[26] ),
+ .user_gpio_oeb(\user_io_oeb[26] ),
+ .user_gpio_out(\user_io_out[26] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[8] (
+ .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351] }),
+ .mgmt_gpio_in(\mgmt_io_in[27] ),
+ .mgmt_gpio_oeb(\one_loop2[8] ),
+ .mgmt_gpio_out(\mgmt_io_in[27] ),
+ .one(\one_loop2[8] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[27] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[27] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[27] ),
+ .pad_gpio_dm({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] }),
+ .pad_gpio_holdover(\mprj_io_holdover[27] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[27] ),
+ .pad_gpio_in(\mprj_io_in[27] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[27] ),
+ .pad_gpio_out(\mprj_io_out[27] ),
+ .pad_gpio_outenb(\mprj_io_oeb[27] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[27] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[27] ),
+ .resetn(\gpio_resetn_2[9] ),
+ .resetn_out(\gpio_resetn_2[8] ),
+ .serial_clock(\gpio_clock_2[9] ),
+ .serial_clock_out(\gpio_clock_2[8] ),
+ .serial_data_in(\gpio_serial_link_2[9] ),
+ .serial_data_out(\gpio_serial_link_2[8] ),
+ .serial_load(\gpio_load_2[9] ),
+ .serial_load_out(\gpio_load_2[8] ),
+ .user_gpio_in(\user_io_in[27] ),
+ .user_gpio_oeb(\user_io_oeb[27] ),
+ .user_gpio_out(\user_io_out[27] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[9] (
+ .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364] }),
+ .mgmt_gpio_in(\mgmt_io_in[28] ),
+ .mgmt_gpio_oeb(\one_loop2[9] ),
+ .mgmt_gpio_out(\mgmt_io_in[28] ),
+ .one(\one_loop2[9] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[28] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[28] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[28] ),
+ .pad_gpio_dm({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] }),
+ .pad_gpio_holdover(\mprj_io_holdover[28] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[28] ),
+ .pad_gpio_in(\mprj_io_in[28] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[28] ),
+ .pad_gpio_out(\mprj_io_out[28] ),
+ .pad_gpio_outenb(\mprj_io_oeb[28] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[28] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[28] ),
+ .resetn(\gpio_resetn_2[10] ),
+ .resetn_out(\gpio_resetn_2[9] ),
+ .serial_clock(\gpio_clock_2[10] ),
+ .serial_clock_out(\gpio_clock_2[9] ),
+ .serial_data_in(\gpio_serial_link_2[10] ),
+ .serial_data_out(\gpio_serial_link_2[9] ),
+ .serial_load(\gpio_load_2[10] ),
+ .serial_load_out(\gpio_load_2[9] ),
+ .user_gpio_in(\user_io_in[28] ),
+ .user_gpio_oeb(\user_io_oeb[28] ),
+ .user_gpio_out(\user_io_out[28] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ housekeeping housekeeping (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] }),
+ .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] }),
+ .mgmt_gpio_in({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0] }),
+ .mgmt_gpio_oeb({ \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_nc[32] , \mgmt_io_nc[31] , \mgmt_io_nc[30] , \mgmt_io_nc[29] , \mgmt_io_nc[28] , \mgmt_io_nc[27] , \mgmt_io_nc[26] , \mgmt_io_nc[25] , \mgmt_io_nc[24] , \mgmt_io_nc[23] , \mgmt_io_nc[22] , \mgmt_io_nc[21] , \mgmt_io_nc[20] , \mgmt_io_nc[19] , \mgmt_io_nc[18] , \mgmt_io_nc[17] , \mgmt_io_nc[16] , \mgmt_io_nc[15] , \mgmt_io_nc[14] , \mgmt_io_nc[13] , \mgmt_io_nc[12] , \mgmt_io_nc[11] , \mgmt_io_nc[10] , \mgmt_io_nc[9] , \mgmt_io_nc[8] , \mgmt_io_nc[7] , \mgmt_io_nc[6] , \mgmt_io_nc[5] , \mgmt_io_nc[4] , \mgmt_io_nc[3] , \mgmt_io_nc[2] , \mgmt_io_nc[1] , \mgmt_io_nc[0] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0] }),
+ .mgmt_gpio_out({ \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_out[1] , \mgmt_io_out[0] }),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_di(flash_io1_di),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .pll_bypass(ext_clk_sel),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .pll_ena(spi_pll_ena),
+ .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .porb(porb_l),
+ .pwr_ctrl_out(),
+ .qspi_enabled(qspi_enabled),
+ .reset(ext_reset),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_2(\gpio_serial_link_2_shifted[18] ),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_resetn(\gpio_resetn_1_shifted[0] ),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0] }),
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
+ .trap(trap),
+ .uart_enabled(uart_enabled),
+ .user_clock(caravel_clk2),
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+ .wb_ack_o(hk_ack_i),
+ .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .wb_clk_i(caravel_clk),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .wb_rstn_i(caravel_rstn),
+ .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .wb_stb_i(hk_stb_o),
+ .wb_we_i(mprj_we_o_core)
+ );
+ mgmt_protect mgmt_buffers (
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_we_o_user(mprj_we_o_user),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood),
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] }),
+ .user_reset(mprj_reset),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core)
+ );
+ user_project_wrapper mprj (
+ .analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0] }),
+ .io_in({ \user_io_in[37] , \user_io_in[36] , \user_io_in[35] , \user_io_in[34] , \user_io_in[33] , \user_io_in[32] , \user_io_in[31] , \user_io_in[30] , \user_io_in[29] , \user_io_in[28] , \user_io_in[27] , \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0] }),
+ .io_oeb({ \user_io_oeb[37] , \user_io_oeb[36] , \user_io_oeb[35] , \user_io_oeb[34] , \user_io_oeb[33] , \user_io_oeb[32] , \user_io_oeb[31] , \user_io_oeb[30] , \user_io_oeb[29] , \user_io_oeb[28] , \user_io_oeb[27] , \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0] }),
+ .io_out({ \user_io_out[37] , \user_io_out[36] , \user_io_out[35] , \user_io_out[34] , \user_io_out[33] , \user_io_out[32] , \user_io_out[31] , \user_io_out[30] , \user_io_out[29] , \user_io_out[28] , \user_io_out[27] , \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0] }),
+ .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core),
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user)
+ );
+ chip_io padframe (
+ .clock(clock),
+ .clock_core(clock_core),
+ .flash_clk(flash_clk),
+ .flash_clk_core(flash_clk_frame),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_csb(flash_csb),
+ .flash_csb_core(flash_csb_frame),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_io0(flash_io0),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1(flash_io1),
+ .flash_io1_di_core(flash_io1_di),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .gpio(gpio),
+ .gpio_in_core(gpio_in_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .mprj_analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0] }),
+ .mprj_io(mprj_io),
+ .mprj_io_analog_en({ \mprj_io_analog_en[37] , \mprj_io_analog_en[36] , \mprj_io_analog_en[35] , \mprj_io_analog_en[34] , \mprj_io_analog_en[33] , \mprj_io_analog_en[32] , \mprj_io_analog_en[31] , \mprj_io_analog_en[30] , \mprj_io_analog_en[29] , \mprj_io_analog_en[28] , \mprj_io_analog_en[27] , \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0] }),
+ .mprj_io_analog_pol({ \mprj_io_analog_pol[37] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0] }),
+ .mprj_io_analog_sel({ \mprj_io_analog_sel[37] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0] }),
+ .mprj_io_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] , \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] , \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] , \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] , \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] , \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] , \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] , \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] , \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] , \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] , \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] , \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .mprj_io_holdover({ \mprj_io_holdover[37] , \mprj_io_holdover[36] , \mprj_io_holdover[35] , \mprj_io_holdover[34] , \mprj_io_holdover[33] , \mprj_io_holdover[32] , \mprj_io_holdover[31] , \mprj_io_holdover[30] , \mprj_io_holdover[29] , \mprj_io_holdover[28] , \mprj_io_holdover[27] , \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0] }),
+ .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[37] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0] }),
+ .mprj_io_in({ \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0] }),
+ .mprj_io_inp_dis({ \mprj_io_inp_dis[37] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0] }),
+ .mprj_io_oeb({ \mprj_io_oeb[37] , \mprj_io_oeb[36] , \mprj_io_oeb[35] , \mprj_io_oeb[34] , \mprj_io_oeb[33] , \mprj_io_oeb[32] , \mprj_io_oeb[31] , \mprj_io_oeb[30] , \mprj_io_oeb[29] , \mprj_io_oeb[28] , \mprj_io_oeb[27] , \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0] }),
+ .mprj_io_out({ \mprj_io_out[37] , \mprj_io_out[36] , \mprj_io_out[35] , \mprj_io_out[34] , \mprj_io_out[33] , \mprj_io_out[32] , \mprj_io_out[31] , \mprj_io_out[30] , \mprj_io_out[29] , \mprj_io_out[28] , \mprj_io_out[27] , \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0] }),
+ .mprj_io_slow_sel({ \mprj_io_slow_sel[37] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0] }),
+ .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[37] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0] }),
+ .por(por_l),
+ .porb_h(porb_h),
+ .resetb(resetb),
+ .resetb_core_h(rstb_h),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd1_pad(vccd1),
+ .vccd2(vccd2_core),
+ .vccd2_pad(vccd2),
+ .vccd_pad(vccd),
+ .vdda(vdda_core),
+ .vdda1(vdda1_core),
+ .vdda1_pad(vdda1),
+ .vdda1_pad2(vdda1_2),
+ .vdda2(vdda2_core),
+ .vdda2_pad(vdda2),
+ .vdda_pad(vdda),
+ .vddio(vddio_core),
+ .vddio_pad(vddio),
+ .vddio_pad2(vddio_2),
+ .vssa(vssa_core),
+ .vssa1(vssa1_core),
+ .vssa1_pad(vssa1),
+ .vssa1_pad2(vssa1_2),
+ .vssa2(vssa2_core),
+ .vssa2_pad(vssa2),
+ .vssa_pad(vssa),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd1_pad(vssd1),
+ .vssd2(vssd2_core),
+ .vssd2_pad(vssd2),
+ .vssd_pad(vssd),
+ .vssio(vssio_core),
+ .vssio_pad(vssio),
+ .vssio_pad2(vssio_2)
+ );
+ digital_pll pll (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .clockp({ pll_clk, pll_clk90 }),
+ .dco(spi_pll_dco_ena),
+ .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .enable(spi_pll_ena),
+ .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .osc(clock_core),
+ .resetb(rstb_l)
+ );
+ simple_por por (
+ .por_l(por_l),
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .vdd1v8(vccd_core),
+ .vdd3v3(vddio_core),
+ .vss3v3(vssio_core),
+ .vss1v8(vssd_core)
+ );
+ xres_buf rstb_level (
+ .A(rstb_h),
+ .LVGND(vssd_core),
+ .LVPWR(vccd_core),
+ .VGND(vssio_core),
+ .VPWR(vddio_core),
+ .X(rstb_l)
+ );
+ mgmt_core_wrapper soc (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .flash_clk(flash_clk_core),
+ .flash_csb(flash_csb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_out_pad(gpio_out_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .hk_ack_i(hk_ack_i),
+ .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .hk_stb_o(hk_stb_o),
+ .hk_cyc_o(hk_cyc_o),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_wb_iena(mprj_iena_wb),
+ .mprj_we_o(mprj_we_o_core),
+ .qspi_enabled(qspi_enabled),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .sram_ro_addr({ \hkspi_sram_addr[7] , \hkspi_sram_addr[6] , \hkspi_sram_addr[5] , \hkspi_sram_addr[4] , \hkspi_sram_addr[3] , \hkspi_sram_addr[2] , \hkspi_sram_addr[1] , \hkspi_sram_addr[0] }),
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
+ .trap(trap),
+ .uart_enabled(uart_enabled),
+ .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] })
+ );
+ user_id_programming user_id_value (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] })
+ );
+ spare_logic_block \spare_logic[0] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[1] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[2] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+ spare_logic_block \spare_logic[3] (
+ .vssd(vssd_core),
+ .vccd(vccd_core),
+ .spare_xz(),
+ .spare_xi(),
+ .spare_xib(),
+ .spare_xna(),
+ .spare_xno(),
+ .spare_xmx(),
+ .spare_xfq(),
+ .spare_xfqn()
+ );
+
+ assign \gpio_resetn_1_shifted[14] = \gpio_resetn_1[13] ;
+ assign \gpio_resetn_1_shifted[13] = \gpio_resetn_1[12] ;
+ assign \gpio_resetn_1_shifted[12] = \gpio_resetn_1[11] ;
+ assign \gpio_resetn_1_shifted[11] = \gpio_resetn_1[10] ;
+ assign \gpio_resetn_1_shifted[10] = \gpio_resetn_1[9] ;
+ assign \gpio_resetn_1_shifted[9] = \gpio_resetn_1[8] ;
+ assign \gpio_resetn_1_shifted[8] = \gpio_resetn_1[7] ;
+ assign \gpio_resetn_1_shifted[7] = \gpio_resetn_1[6] ;
+ assign \gpio_resetn_1_shifted[6] = \gpio_resetn_1[5] ;
+ assign \gpio_resetn_1_shifted[5] = \gpio_resetn_1[4] ;
+ assign \gpio_resetn_1_shifted[4] = \gpio_resetn_1[3] ;
+ assign \gpio_resetn_1_shifted[3] = \gpio_resetn_1[2] ;
+ assign \gpio_resetn_1_shifted[2] = \gpio_resetn_1[1] ;
+ assign \gpio_resetn_1_shifted[1] = \gpio_resetn_1[0] ;
+ assign \gpio_load_1_shifted[18] = \gpio_load_1[17] ;
+ assign \gpio_load_1_shifted[17] = \gpio_load_1[16] ;
+ assign \gpio_load_1_shifted[16] = \gpio_load_1[15] ;
+ assign \gpio_load_1_shifted[15] = \gpio_load_1[14] ;
+ assign \gpio_load_1_shifted[14] = \gpio_load_1[13] ;
+ assign \gpio_load_1_shifted[13] = \gpio_load_1[12] ;
+ assign \gpio_load_1_shifted[12] = \gpio_load_1[11] ;
+ assign \gpio_load_1_shifted[11] = \gpio_load_1[10] ;
+ assign \gpio_load_1_shifted[10] = \gpio_load_1[9] ;
+ assign \gpio_load_1_shifted[9] = \gpio_load_1[8] ;
+ assign \gpio_load_1_shifted[8] = \gpio_load_1[7] ;
+ assign \gpio_load_1_shifted[7] = \gpio_load_1[6] ;
+ assign \gpio_load_1_shifted[6] = \gpio_load_1[5] ;
+ assign \gpio_load_1_shifted[5] = \gpio_load_1[4] ;
+ assign \gpio_load_1_shifted[4] = \gpio_load_1[3] ;
+ assign \gpio_load_1_shifted[3] = \gpio_load_1[2] ;
+ assign \gpio_load_1_shifted[2] = \gpio_load_1[1] ;
+ assign \gpio_load_1_shifted[1] = \gpio_load_1[0] ;
+ assign \gpio_load_2_shifted[18] = \gpio_load_1_shifted[0] ;
+ assign \gpio_load_2_shifted[17] = \gpio_load_2[18] ;
+ assign \gpio_load_2_shifted[16] = \gpio_load_2[17] ;
+ assign \gpio_load_2_shifted[15] = \gpio_load_2[16] ;
+ assign \gpio_load_2_shifted[14] = \gpio_load_2[15] ;
+ assign \gpio_load_2_shifted[13] = \gpio_load_2[14] ;
+ assign \gpio_load_2_shifted[12] = \gpio_load_2[13] ;
+ assign \gpio_load_2_shifted[11] = \gpio_load_2[12] ;
+ assign \gpio_load_2_shifted[10] = \gpio_load_2[11] ;
+ assign \gpio_load_2_shifted[9] = \gpio_load_2[10] ;
+ assign \gpio_load_2_shifted[8] = \gpio_load_2[9] ;
+ assign \gpio_load_2_shifted[7] = \gpio_load_2[8] ;
+ assign \gpio_load_2_shifted[6] = \gpio_load_2[7] ;
+ assign \gpio_load_2_shifted[5] = \gpio_load_2[6] ;
+ assign \gpio_load_2_shifted[4] = \gpio_load_2[5] ;
+ assign \gpio_load_2_shifted[3] = \gpio_load_2[4] ;
+ assign \gpio_load_2_shifted[2] = \gpio_load_2[3] ;
+ assign \gpio_load_2_shifted[1] = \gpio_load_2[2] ;
+ assign \gpio_load_2_shifted[0] = \gpio_load_2[1] ;
+ assign \gpio_resetn_2_shifted[18] = \gpio_resetn_1_shifted[0] ;
+ assign \gpio_resetn_2_shifted[17] = \gpio_resetn_2[18] ;
+ assign \gpio_resetn_2_shifted[16] = \gpio_resetn_2[17] ;
+ assign \gpio_resetn_2_shifted[15] = \gpio_resetn_2[16] ;
+ assign \gpio_resetn_2_shifted[14] = \gpio_resetn_2[15] ;
+ assign \gpio_resetn_2_shifted[13] = \gpio_resetn_2[14] ;
+ assign \gpio_resetn_2_shifted[12] = \gpio_resetn_2[13] ;
+ assign \gpio_resetn_2_shifted[11] = \gpio_resetn_2[12] ;
+ assign \gpio_resetn_2_shifted[10] = \gpio_resetn_2[11] ;
+ assign \gpio_resetn_2_shifted[9] = \gpio_resetn_2[10] ;
+ assign \gpio_resetn_2_shifted[8] = \gpio_resetn_2[9] ;
+ assign \gpio_resetn_2_shifted[7] = \gpio_resetn_2[8] ;
+ assign \gpio_resetn_2_shifted[6] = \gpio_resetn_2[7] ;
+ assign \gpio_resetn_2_shifted[5] = \gpio_resetn_2[6] ;
+ assign \gpio_resetn_2_shifted[4] = \gpio_resetn_2[5] ;
+ assign \gpio_resetn_2_shifted[3] = \gpio_resetn_2[4] ;
+ assign \gpio_resetn_2_shifted[2] = \gpio_resetn_2[3] ;
+ assign \gpio_resetn_2_shifted[1] = \gpio_resetn_2[2] ;
+ assign \gpio_resetn_2_shifted[0] = \gpio_resetn_2[1] ;
+ assign \gpio_serial_link_2_shifted[17] = \gpio_serial_link_2[18] ;
+ assign \gpio_serial_link_2_shifted[16] = \gpio_serial_link_2[17] ;
+ assign \gpio_serial_link_2_shifted[15] = \gpio_serial_link_2[16] ;
+ assign \gpio_serial_link_2_shifted[14] = \gpio_serial_link_2[15] ;
+ assign \gpio_serial_link_2_shifted[13] = \gpio_serial_link_2[14] ;
+ assign \gpio_serial_link_2_shifted[12] = \gpio_serial_link_2[13] ;
+ assign \gpio_serial_link_2_shifted[11] = \gpio_serial_link_2[12] ;
+ assign \gpio_serial_link_2_shifted[10] = \gpio_serial_link_2[11] ;
+ assign \gpio_serial_link_2_shifted[9] = \gpio_serial_link_2[10] ;
+ assign \gpio_serial_link_2_shifted[8] = \gpio_serial_link_2[9] ;
+ assign \gpio_serial_link_2_shifted[7] = \gpio_serial_link_2[8] ;
+ assign \gpio_serial_link_2_shifted[6] = \gpio_serial_link_2[7] ;
+ assign \gpio_serial_link_2_shifted[5] = \gpio_serial_link_2[6] ;
+ assign \gpio_serial_link_2_shifted[4] = \gpio_serial_link_2[5] ;
+ assign \gpio_serial_link_2_shifted[3] = \gpio_serial_link_2[4] ;
+ assign \gpio_serial_link_2_shifted[2] = \gpio_serial_link_2[3] ;
+ assign \gpio_serial_link_2_shifted[1] = \gpio_serial_link_2[2] ;
+ assign \gpio_serial_link_2_shifted[0] = \gpio_serial_link_2[1] ;
+ assign \gpio_serial_link_1_shifted[18] = \gpio_serial_link_1[17] ;
+ assign \gpio_serial_link_1_shifted[17] = \gpio_serial_link_1[16] ;
+ assign \gpio_serial_link_1_shifted[16] = \gpio_serial_link_1[15] ;
+ assign \gpio_serial_link_1_shifted[15] = \gpio_serial_link_1[14] ;
+ assign \gpio_serial_link_1_shifted[14] = \gpio_serial_link_1[13] ;
+ assign \gpio_serial_link_1_shifted[13] = \gpio_serial_link_1[12] ;
+ assign \gpio_serial_link_1_shifted[12] = \gpio_serial_link_1[11] ;
+ assign \gpio_serial_link_1_shifted[11] = \gpio_serial_link_1[10] ;
+ assign \gpio_serial_link_1_shifted[10] = \gpio_serial_link_1[9] ;
+ assign \gpio_serial_link_1_shifted[9] = \gpio_serial_link_1[8] ;
+ assign \gpio_serial_link_1_shifted[8] = \gpio_serial_link_1[7] ;
+ assign \gpio_serial_link_1_shifted[7] = \gpio_serial_link_1[6] ;
+ assign \gpio_serial_link_1_shifted[6] = \gpio_serial_link_1[5] ;
+ assign \gpio_serial_link_1_shifted[5] = \gpio_serial_link_1[4] ;
+ assign \gpio_serial_link_1_shifted[4] = \gpio_serial_link_1[3] ;
+ assign \gpio_serial_link_1_shifted[3] = \gpio_serial_link_1[2] ;
+ assign \gpio_serial_link_1_shifted[2] = \gpio_serial_link_1[1] ;
+ assign \gpio_serial_link_1_shifted[1] = \gpio_serial_link_1[0] ;
+ assign \gpio_resetn_1_shifted[15] = \gpio_resetn_1[14] ;
+ assign \gpio_clock_2_shifted[14] = \gpio_clock_2[15] ;
+ assign \gpio_clock_1_shifted[5] = \gpio_clock_1[4] ;
+ assign \gpio_clock_1_shifted[2] = \gpio_clock_1[1] ;
+ assign \gpio_clock_1_shifted[3] = \gpio_clock_1[2] ;
+ assign \gpio_clock_2_shifted[2] = \gpio_clock_2[3] ;
+ assign \gpio_clock_1_shifted[12] = \gpio_clock_1[11] ;
+ assign \gpio_clock_1_shifted[4] = \gpio_clock_1[3] ;
+ assign \gpio_clock_2_shifted[7] = \gpio_clock_2[8] ;
+ assign \gpio_clock_2_shifted[12] = \gpio_clock_2[13] ;
+ assign \gpio_clock_2_shifted[11] = \gpio_clock_2[12] ;
+ assign \gpio_clock_1_shifted[16] = \gpio_clock_1[15] ;
+ assign \gpio_clock_1_shifted[14] = \gpio_clock_1[13] ;
+ assign \gpio_clock_1_shifted[7] = \gpio_clock_1[6] ;
+ assign \gpio_clock_2_shifted[5] = \gpio_clock_2[6] ;
+ assign \gpio_clock_1_shifted[6] = \gpio_clock_1[5] ;
+ assign \gpio_clock_2_shifted[4] = \gpio_clock_2[5] ;
+ assign \gpio_clock_2_shifted[13] = \gpio_clock_2[14] ;
+ assign \gpio_clock_2_shifted[0] = \gpio_clock_2[1] ;
+ assign \gpio_clock_1_shifted[17] = \gpio_clock_1[16] ;
+ assign \gpio_resetn_1_shifted[17] = \gpio_resetn_1[16] ;
+ assign \gpio_clock_2_shifted[3] = \gpio_clock_2[4] ;
+ assign \gpio_resetn_1_shifted[18] = \gpio_resetn_1[17] ;
+ assign \gpio_clock_2_shifted[1] = \gpio_clock_2[2] ;
+ assign \gpio_clock_2_shifted[15] = \gpio_clock_2[16] ;
+ assign \gpio_clock_1_shifted[13] = \gpio_clock_1[12] ;
+ assign \gpio_clock_1_shifted[11] = \gpio_clock_1[10] ;
+ assign mprj_io_loader_data_2 = \gpio_serial_link_2_shifted[18] ;
+ assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+ assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+ assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+ assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+ assign \gpio_clock_1_shifted[1] = \gpio_clock_1[0] ;
+ assign \gpio_clock_1_shifted[9] = \gpio_clock_1[8] ;
+ assign \gpio_resetn_1_shifted[16] = \gpio_resetn_1[15] ;
+ assign \gpio_clock_1_shifted[15] = \gpio_clock_1[14] ;
+ assign \gpio_clock_1_shifted[8] = \gpio_clock_1[7] ;
+ assign \gpio_clock_1_shifted[10] = \gpio_clock_1[9] ;
+ assign \gpio_clock_2_shifted[8] = \gpio_clock_2[9] ;
+ assign \gpio_clock_2_shifted[9] = \gpio_clock_2[10] ;
+ assign \gpio_clock_1_shifted[18] = \gpio_clock_1[17] ;
+ assign \gpio_clock_2_shifted[16] = \gpio_clock_2[17] ;
+ assign \gpio_clock_2_shifted[6] = \gpio_clock_2[7] ;
+ assign \gpio_clock_2_shifted[17] = \gpio_clock_2[18] ;
+ assign \gpio_clock_2_shifted[10] = \gpio_clock_2[11] ;
+ assign \gpio_clock_2_shifted[18] = \gpio_clock_1_shifted[0] ;
+endmodule
diff --git a/caravel/verilog/gl/caravel_clocking.v b/caravel/verilog/gl/caravel_clocking.v
new file mode 100644
index 0000000..3e798c0
--- /dev/null
+++ b/caravel/verilog/gl/caravel_clocking.v
@@ -0,0 +1,4599 @@
+module caravel_clocking (VGND,
+ VPWR,
+ core_clk,
+ ext_clk,
+ ext_clk_sel,
+ ext_reset,
+ pll_clk,
+ pll_clk90,
+ resetb,
+ resetb_sync,
+ user_clk,
+ sel,
+ sel2);
+ input VGND;
+ input VPWR;
+ output core_clk;
+ input ext_clk;
+ input ext_clk_sel;
+ input ext_reset;
+ input pll_clk;
+ input pll_clk90;
+ input resetb;
+ output resetb_sync;
+ output user_clk;
+ input [2:0] sel;
+ input [2:0] sel2;
+
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire clknet_0_ext_clk;
+ wire clknet_0_pll_clk;
+ wire clknet_0_pll_clk90;
+ wire clknet_1_0_0_ext_clk;
+ wire clknet_1_0_0_pll_clk;
+ wire clknet_1_0_0_pll_clk90;
+ wire clknet_1_1_0_ext_clk;
+ wire clknet_1_1_0_pll_clk;
+ wire clknet_1_1_0_pll_clk90;
+ wire \divider.even_0.N[0] ;
+ wire \divider.even_0.N[1] ;
+ wire \divider.even_0.N[2] ;
+ wire \divider.even_0.counter[0] ;
+ wire \divider.even_0.counter[1] ;
+ wire \divider.even_0.counter[2] ;
+ wire \divider.even_0.out_counter ;
+ wire \divider.odd_0.counter2[0] ;
+ wire \divider.odd_0.counter2[1] ;
+ wire \divider.odd_0.counter2[2] ;
+ wire \divider.odd_0.counter[0] ;
+ wire \divider.odd_0.counter[1] ;
+ wire \divider.odd_0.counter[2] ;
+ wire \divider.odd_0.initial_begin[0] ;
+ wire \divider.odd_0.initial_begin[1] ;
+ wire \divider.odd_0.initial_begin[2] ;
+ wire \divider.odd_0.old_N[0] ;
+ wire \divider.odd_0.old_N[1] ;
+ wire \divider.odd_0.old_N[2] ;
+ wire \divider.odd_0.out_counter ;
+ wire \divider.odd_0.out_counter2 ;
+ wire \divider.odd_0.rst_pulse ;
+ wire \divider.out ;
+ wire \divider.syncNp[0] ;
+ wire \divider.syncNp[1] ;
+ wire \divider.syncNp[2] ;
+ wire \divider2.even_0.N[0] ;
+ wire \divider2.even_0.N[1] ;
+ wire \divider2.even_0.N[2] ;
+ wire \divider2.even_0.counter[0] ;
+ wire \divider2.even_0.counter[1] ;
+ wire \divider2.even_0.counter[2] ;
+ wire \divider2.even_0.out_counter ;
+ wire \divider2.odd_0.counter2[0] ;
+ wire \divider2.odd_0.counter2[1] ;
+ wire \divider2.odd_0.counter2[2] ;
+ wire \divider2.odd_0.counter[0] ;
+ wire \divider2.odd_0.counter[1] ;
+ wire \divider2.odd_0.counter[2] ;
+ wire \divider2.odd_0.initial_begin[0] ;
+ wire \divider2.odd_0.initial_begin[1] ;
+ wire \divider2.odd_0.initial_begin[2] ;
+ wire \divider2.odd_0.old_N[0] ;
+ wire \divider2.odd_0.old_N[1] ;
+ wire \divider2.odd_0.old_N[2] ;
+ wire \divider2.odd_0.out_counter ;
+ wire \divider2.odd_0.out_counter2 ;
+ wire \divider2.odd_0.rst_pulse ;
+ wire \divider2.out ;
+ wire \divider2.syncNp[0] ;
+ wire \divider2.syncNp[1] ;
+ wire \divider2.syncNp[2] ;
+ wire ext_clk_syncd;
+ wire ext_clk_syncd_pre;
+ wire net1;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net2;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net3;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net4;
+ wire net5;
+ wire net6;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire pll_clk_sel;
+ wire \reset_delay[0] ;
+ wire \reset_delay[1] ;
+ wire \reset_delay[2] ;
+ wire use_pll_first;
+ wire use_pll_second;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA__283__A2 (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__322__A (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__323__B_N (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__347__S (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__349__B (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__421__A1 (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__422__A1 (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__425__A1 (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__439__D (.DIODE(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__445__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__446__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__447__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__448__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__449__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__450__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__451__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__452__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__453__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__454__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__455__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__456__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__457__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__458__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__459__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__460__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__461__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__462__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__463__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__464__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__465__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__466__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__467__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__468__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__469__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__470__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__471__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__472__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__473__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__474__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__475__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__476__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__477__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__478__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__479__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__480__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__481__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__482__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__483__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__484__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__485__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__486__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__487__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__488__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__489__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__490__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__491__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__492__SET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__493__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__494__RESET_B (.DIODE(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_ext_clk_A (.DIODE(ext_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk90_A (.DIODE(pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_pll_clk_A (.DIODE(pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(ext_clk_sel),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(ext_reset),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(resetb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(sel2[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(sel2[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input6_A (.DIODE(sel2[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input7_A (.DIODE(sel[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input8_A (.DIODE(sel[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input9_A (.DIODE(sel[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_0_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_0_122 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_142 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_0_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_157 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_0_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_19_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_116 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_19_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_19_128 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_19_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_19_140 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_19_154 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_160 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_19_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_19_178 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_19_188 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_20 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_19_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_19_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_19_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_19_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_19_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_66 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_19_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_19_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_1_127 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_1_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_155 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_45 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_49 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_115 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_2_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_147 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_151 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_170 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_2_196 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_2_42 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_147 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_172 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_199 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_20 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_95 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_107 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_115 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_118 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_34 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_5_108 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_5_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_5_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_5_76 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_5_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_5_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_6_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_6_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_6_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_168 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_6_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_196 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_6_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_6_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_6_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_56 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_64 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_66 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_6_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_129 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_155 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_187 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_200 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_7_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_127 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_170 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_8_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_151 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_190 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_9_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_9_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_62 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_9_79 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_100 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_101 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_102 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_103 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_104 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_105 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_106 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_107 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_108 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_109 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_110 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_111 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_112 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_113 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_114 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_115 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_116 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_117 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_118 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_119 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_120 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_121 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_122 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_123 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_124 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_125 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_126 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_127 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_128 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_129 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_130 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_131 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_132 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_133 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_134 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_135 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_136 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_137 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_138 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_139 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_140 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_141 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_142 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_143 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_144 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_145 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_146 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_147 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_148 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_149 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_150 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_151 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_152 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_153 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_154 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_155 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_156 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_157 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_158 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_159 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_160 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_161 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_162 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_163 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_164 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_165 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_166 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_167 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_168 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_169 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_170 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_171 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_172 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_173 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_174 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_175 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_176 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_177 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_178 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_179 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_180 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_181 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_182 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_183 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_184 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_185 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_186 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_187 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_188 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_189 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_190 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_191 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_192 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_193 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_194 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_195 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_196 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_197 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_198 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_199 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_200 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_201 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_202 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_203 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_204 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_86 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_87 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_88 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_89 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_90 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_91 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_92 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_93 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_94 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_95 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_96 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_97 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_98 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_99 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _216_ (.A0(_016_),
+ .A1(\divider2.even_0.counter[1] ),
+ .S(\divider2.even_0.N[0] ),
+ .X(_121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _217_ (.A(_121_),
+ .X(_119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _218_ (.A0(_015_),
+ .A1(\divider2.even_0.counter[0] ),
+ .S(\divider2.even_0.N[0] ),
+ .X(_122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _219_ (.A(_122_),
+ .X(_118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _220_ (.A(\divider2.even_0.N[1] ),
+ .B_N(\divider2.odd_0.old_N[1] ),
+ .X(_123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _221_ (.A(\divider2.odd_0.old_N[1] ),
+ .B_N(\divider2.even_0.N[1] ),
+ .X(_124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _222_ (.A(_123_),
+ .B(_124_),
+ .C(\divider2.odd_0.old_N[0] ),
+ .Y(_125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _223_ (.A(\divider2.even_0.N[2] ),
+ .B(\divider2.odd_0.old_N[2] ),
+ .Y(_126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _224_ (.A(\divider2.even_0.N[2] ),
+ .B(\divider2.odd_0.old_N[2] ),
+ .X(_127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _225_ (.A1(\divider2.even_0.N[2] ),
+ .A2(\divider2.even_0.N[1] ),
+ .B1(\divider2.even_0.N[0] ),
+ .X(_128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _226_ (.A1(_126_),
+ .A2(_127_),
+ .B1(_128_),
+ .Y(_129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _227_ (.A1(\divider2.even_0.N[2] ),
+ .A2(\divider2.even_0.N[1] ),
+ .B1(\divider2.even_0.N[0] ),
+ .Y(_130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _228_ (.A(\divider2.odd_0.rst_pulse ),
+ .Y(_131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _229_ (.A(_130_),
+ .B(_131_),
+ .Y(_000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _230_ (.A1(_125_),
+ .A2(_129_),
+ .B1(_000_),
+ .X(_117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _231_ (.A(\divider2.odd_0.counter[2] ),
+ .B(\divider2.odd_0.counter[1] ),
+ .Y(_132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _232_ (.A(_132_),
+ .B(\divider2.odd_0.counter[0] ),
+ .Y(_133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _233_ (.A(\divider2.odd_0.out_counter ),
+ .Y(_134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3b_1 _234_ (.A_N(_133_),
+ .B(_134_),
+ .C(_128_),
+ .Y(_135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _235_ (.A(_131_),
+ .X(_136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _236_ (.A(_130_),
+ .X(_137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _237_ (.A1(_137_),
+ .A2(_133_),
+ .B1_N(_134_),
+ .Y(_138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _238_ (.A(_135_),
+ .B(_136_),
+ .C(_138_),
+ .Y(_116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _239_ (.A(_137_),
+ .B(_136_),
+ .C(\divider2.odd_0.counter[2] ),
+ .Y(_139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _240_ (.A1(_022_),
+ .A2(_000_),
+ .B1_N(_139_),
+ .X(_115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _241_ (.A(_137_),
+ .B(_131_),
+ .C(\divider2.odd_0.counter[1] ),
+ .Y(_140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _242_ (.A1(_021_),
+ .A2(_000_),
+ .B1_N(_140_),
+ .X(_114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _243_ (.A(_137_),
+ .B(_131_),
+ .C(\divider2.odd_0.counter[0] ),
+ .Y(_141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _244_ (.A1(_020_),
+ .A2(_000_),
+ .B1_N(_141_),
+ .X(_113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _245_ (.A0(\divider2.odd_0.initial_begin[2] ),
+ .A1(_025_),
+ .S(_002_),
+ .X(_142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _246_ (.A(_142_),
+ .X(_112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _247__1 (.A(clknet_1_0_0_pll_clk90),
+ .Y(net14),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _248_ (.A0(\divider2.odd_0.initial_begin[1] ),
+ .A1(_024_),
+ .S(_002_),
+ .X(_143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _249_ (.A(_143_),
+ .X(_111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _250_ (.A0(\divider2.odd_0.initial_begin[0] ),
+ .A1(_023_),
+ .S(_002_),
+ .X(_144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _251_ (.A(_144_),
+ .X(_110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _252__2 (.A(clknet_1_0_0_pll_clk90),
+ .Y(net15),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _253_ (.A(\divider2.odd_0.initial_begin[2] ),
+ .B(\divider2.odd_0.initial_begin[1] ),
+ .Y(_145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _254_ (.A1(\divider2.even_0.N[2] ),
+ .A2(\divider2.even_0.N[1] ),
+ .B1(\divider2.even_0.N[0] ),
+ .C1(_145_),
+ .X(_033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _255_ (.A(\divider2.odd_0.out_counter2 ),
+ .Y(_146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_2 _256_ (.A(\divider2.odd_0.counter2[2] ),
+ .B(\divider2.odd_0.counter2[1] ),
+ .C_N(\divider2.odd_0.counter2[0] ),
+ .Y(_034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _257_ (.A(_033_),
+ .B(_146_),
+ .C(_034_),
+ .Y(_147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _258_ (.A(\divider2.odd_0.counter2[2] ),
+ .B(\divider2.odd_0.counter2[1] ),
+ .Y(_148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _259_ (.A(_148_),
+ .B(\divider2.odd_0.counter2[0] ),
+ .Y(_149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_4 _260_ (.A1(\divider2.even_0.N[2] ),
+ .A2(\divider2.even_0.N[1] ),
+ .B1(\divider2.even_0.N[0] ),
+ .C1(_145_),
+ .Y(_150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _261_ (.A1(_149_),
+ .A2(_150_),
+ .B1_N(_146_),
+ .Y(_151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _262_ (.A(_147_),
+ .B(_151_),
+ .C(_136_),
+ .Y(_109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _263_ (.A(_150_),
+ .B(_131_),
+ .Y(_152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _264_ (.A(_152_),
+ .B(_019_),
+ .Y(_153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _265_ (.A(_150_),
+ .B(_136_),
+ .C(\divider2.odd_0.counter2[2] ),
+ .Y(_154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _266_ (.A(_153_),
+ .B(_154_),
+ .Y(_108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _267__3 (.A(clknet_1_0_0_pll_clk90),
+ .Y(net16),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _268_ (.A(_152_),
+ .B(_018_),
+ .Y(_155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _269_ (.A(_150_),
+ .B(_136_),
+ .C(\divider2.odd_0.counter2[1] ),
+ .Y(_156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _270_ (.A(_155_),
+ .B(_156_),
+ .Y(_107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _271_ (.A(\divider2.odd_0.counter2[0] ),
+ .Y(_065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _272_ (.A(_152_),
+ .B(_017_),
+ .Y(_157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _273_ (.A1(_065_),
+ .A2(_152_),
+ .B1(_157_),
+ .Y(_106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_2 _274_ (.A(\divider2.even_0.counter[1] ),
+ .B(\divider2.even_0.counter[2] ),
+ .C_N(\divider2.even_0.counter[0] ),
+ .Y(_032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _275_ (.A(\divider2.even_0.N[0] ),
+ .Y(_158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _276_ (.A(\divider2.even_0.out_counter ),
+ .Y(_159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _277_ (.A1(_032_),
+ .A2(_158_),
+ .B1(_159_),
+ .X(_160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _278_ (.A(_032_),
+ .B(_158_),
+ .C(_159_),
+ .Y(_161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _279_ (.A(_160_),
+ .B(_161_),
+ .Y(_105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _280_ (.A(\divider.odd_0.counter[2] ),
+ .B(\divider.odd_0.counter[1] ),
+ .Y(_162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _281_ (.A(_162_),
+ .B(\divider.odd_0.counter[0] ),
+ .Y(_163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _282_ (.A(\divider.odd_0.out_counter ),
+ .Y(_164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _283_ (.A1(net30),
+ .A2(net26),
+ .B1(\divider.even_0.N[0] ),
+ .X(_165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3b_1 _284_ (.A_N(_163_),
+ .B(_164_),
+ .C(_165_),
+ .Y(_166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _285_ (.A(\divider.odd_0.rst_pulse ),
+ .Y(_167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _286_ (.A(_167_),
+ .X(_168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _287_ (.A1(\divider.even_0.N[2] ),
+ .A2(\divider.even_0.N[1] ),
+ .B1(\divider.even_0.N[0] ),
+ .Y(_169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _288_ (.A(_169_),
+ .X(_170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _289_ (.A1(_170_),
+ .A2(_163_),
+ .B1_N(_164_),
+ .Y(_171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _290_ (.A(_166_),
+ .B(_168_),
+ .C(_171_),
+ .Y(_104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _291_ (.A(_169_),
+ .B(_167_),
+ .Y(_001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _292_ (.A(_170_),
+ .B(\divider.odd_0.counter[2] ),
+ .C(_168_),
+ .Y(_172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _293_ (.A1(_011_),
+ .A2(_001_),
+ .B1_N(_172_),
+ .X(_103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _294_ (.A(_170_),
+ .B(\divider.odd_0.counter[1] ),
+ .C(_167_),
+ .Y(_173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _295_ (.A1(_010_),
+ .A2(_001_),
+ .B1_N(_173_),
+ .X(_102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _296_ (.A(_170_),
+ .B(\divider.odd_0.counter[0] ),
+ .C(_167_),
+ .Y(_174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _297_ (.A1(_009_),
+ .A2(_001_),
+ .B1_N(_174_),
+ .X(_101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _298_ (.A0(\divider.odd_0.initial_begin[2] ),
+ .A1(_014_),
+ .S(_003_),
+ .X(_175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _299_ (.A(_175_),
+ .X(_100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _300__4 (.A(clknet_1_0_0_pll_clk),
+ .Y(net17),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _301_ (.A0(\divider.odd_0.initial_begin[1] ),
+ .A1(_013_),
+ .S(_003_),
+ .X(_176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _302_ (.A(_176_),
+ .X(_099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _303_ (.A0(\divider.odd_0.initial_begin[0] ),
+ .A1(_012_),
+ .S(_003_),
+ .X(_177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _304_ (.A(_177_),
+ .X(_098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _305__5 (.A(clknet_1_1_0_pll_clk),
+ .Y(net18),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _306_ (.A(\divider.odd_0.initial_begin[2] ),
+ .B(\divider.odd_0.initial_begin[1] ),
+ .Y(_178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _307_ (.A1(\divider.even_0.N[2] ),
+ .A2(\divider.even_0.N[1] ),
+ .B1(\divider.even_0.N[0] ),
+ .C1(_178_),
+ .X(_029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _308_ (.A(\divider.odd_0.out_counter2 ),
+ .Y(_179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_2 _309_ (.A(\divider.odd_0.counter2[2] ),
+ .B(\divider.odd_0.counter2[1] ),
+ .C_N(\divider.odd_0.counter2[0] ),
+ .Y(_030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _310_ (.A(net38),
+ .B(_179_),
+ .C(_030_),
+ .Y(_180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _311_ (.A(\divider.odd_0.counter2[2] ),
+ .B(\divider.odd_0.counter2[1] ),
+ .Y(_181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _312_ (.A(_181_),
+ .B(\divider.odd_0.counter2[0] ),
+ .Y(_182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_4 _313_ (.A1(net27),
+ .A2(net28),
+ .B1(net32),
+ .C1(_178_),
+ .Y(_183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _314_ (.A1(_182_),
+ .A2(_183_),
+ .B1_N(_179_),
+ .Y(_184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _315_ (.A(_180_),
+ .B(_184_),
+ .C(_168_),
+ .Y(_097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _316_ (.A(\divider.even_0.N[0] ),
+ .B(\divider.even_0.counter[1] ),
+ .C(\divider.even_0.counter[0] ),
+ .Y(_185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _317_ (.A(\divider.even_0.counter[2] ),
+ .B(_185_),
+ .X(_096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _318_ (.A0(_005_),
+ .A1(\divider.even_0.counter[1] ),
+ .S(net34),
+ .X(_186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _319_ (.A(_186_),
+ .X(_095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _320_ (.A0(_004_),
+ .A1(\divider.even_0.counter[0] ),
+ .S(net34),
+ .X(_187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _321_ (.A(_187_),
+ .X(_094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _322_ (.A(net26),
+ .B_N(\divider.odd_0.old_N[1] ),
+ .X(_188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _323_ (.A(\divider.odd_0.old_N[1] ),
+ .B_N(net26),
+ .X(_189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _324_ (.A(_188_),
+ .B(_189_),
+ .C(\divider.odd_0.old_N[0] ),
+ .Y(_190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _325_ (.A(net30),
+ .B(\divider.odd_0.old_N[2] ),
+ .Y(_191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _326_ (.A(net30),
+ .B(\divider.odd_0.old_N[2] ),
+ .X(_192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _327_ (.A1(_191_),
+ .A2(_192_),
+ .B1(_165_),
+ .Y(_193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _328_ (.A1(_190_),
+ .A2(_193_),
+ .B1(_001_),
+ .X(_093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _329_ (.A(_183_),
+ .B(_167_),
+ .Y(_194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _330_ (.A(_194_),
+ .B(_008_),
+ .Y(_195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _331_ (.A(_183_),
+ .B(_168_),
+ .C(\divider.odd_0.counter2[2] ),
+ .Y(_196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _332_ (.A(_195_),
+ .B(_196_),
+ .Y(_092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _333__6 (.A(clknet_1_1_0_pll_clk),
+ .Y(net19),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _334_ (.A(_194_),
+ .B(_007_),
+ .Y(_197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _335_ (.A(_183_),
+ .B(_168_),
+ .C(\divider.odd_0.counter2[1] ),
+ .Y(_198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _336_ (.A(_197_),
+ .B(_198_),
+ .Y(_091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _337_ (.A(\divider.odd_0.counter2[0] ),
+ .Y(_045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _338_ (.A(_194_),
+ .B(_006_),
+ .Y(_199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _339_ (.A1(_045_),
+ .A2(_194_),
+ .B1(_199_),
+ .Y(_090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _340_ (.A(\divider.even_0.counter[2] ),
+ .B(\divider.even_0.counter[1] ),
+ .Y(_200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _341_ (.A(net31),
+ .Y(_201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_1 _342_ (.A(_200_),
+ .B(_201_),
+ .C(\divider.even_0.counter[0] ),
+ .Y(_202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _343_ (.A(\divider.even_0.out_counter ),
+ .B(_202_),
+ .Y(_089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _344__9 (.A(net10),
+ .Y(net22),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _345__8 (.A(net10),
+ .Y(net21),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _346__7 (.A(net10),
+ .Y(net20),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _347_ (.A0(ext_clk_syncd_pre),
+ .A1(clknet_1_0_0_ext_clk),
+ .S(net3),
+ .X(_203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _348_ (.A(_203_),
+ .X(_088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _349_ (.A(net30),
+ .B(net26),
+ .Y(_026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _350_ (.A(\divider2.even_0.N[2] ),
+ .B(\divider2.even_0.N[1] ),
+ .Y(_027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3b_1 _351_ (.A(\divider.even_0.counter[2] ),
+ .B(\divider.even_0.counter[1] ),
+ .C_N(\divider.even_0.counter[0] ),
+ .Y(_028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _352_ (.A(_163_),
+ .Y(_031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _353_ (.A(_133_),
+ .Y(_035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _354_ (.A(\divider.odd_0.out_counter ),
+ .B(\divider.odd_0.out_counter2 ),
+ .Y(_204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2ai_2 _355_ (.A1_N(_201_),
+ .A2_N(_036_),
+ .B1(_170_),
+ .B2(_204_),
+ .Y(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _356_ (.A(\divider2.odd_0.out_counter ),
+ .B(\divider2.odd_0.out_counter2 ),
+ .Y(_205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2ai_2 _357_ (.A1_N(_158_),
+ .A2_N(_038_),
+ .B1(_137_),
+ .B2(_205_),
+ .Y(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _358_ (.A(\divider.odd_0.initial_begin[0] ),
+ .Y(_039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _359_ (.A(net33),
+ .B(net29),
+ .Y(_040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _360_ (.A(\divider.odd_0.initial_begin[1] ),
+ .B(\divider.odd_0.initial_begin[0] ),
+ .Y(_041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _361_ (.A(net33),
+ .B(\divider.even_0.N[2] ),
+ .C(net29),
+ .Y(_206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _362_ (.A1(net33),
+ .A2(net29),
+ .B1(\divider.even_0.N[2] ),
+ .X(_044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _363_ (.A(_206_),
+ .B(_044_),
+ .Y(_042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _364_ (.A(\divider.odd_0.initial_begin[1] ),
+ .B(\divider.odd_0.initial_begin[0] ),
+ .Y(_207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _365_ (.A(\divider.odd_0.initial_begin[2] ),
+ .B(_207_),
+ .X(_043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _366_ (.A(\divider.odd_0.counter2[1] ),
+ .B(\divider.odd_0.counter2[0] ),
+ .Y(_047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _367_ (.A(\divider.odd_0.counter2[1] ),
+ .B(\divider.odd_0.counter2[0] ),
+ .Y(_208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _368_ (.A(\divider.odd_0.counter2[2] ),
+ .B(_208_),
+ .X(_049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _369_ (.A(\divider.odd_0.counter[0] ),
+ .Y(_051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _370_ (.A(\divider.odd_0.counter[1] ),
+ .B(\divider.odd_0.counter[0] ),
+ .Y(_053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _371_ (.A(\divider.odd_0.counter[1] ),
+ .B(\divider.odd_0.counter[0] ),
+ .Y(_209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _372_ (.A(\divider.odd_0.counter[2] ),
+ .B(_209_),
+ .X(_055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _373_ (.A(\divider.even_0.counter[0] ),
+ .Y(_057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _374_ (.A(\divider.even_0.counter[1] ),
+ .B(\divider.even_0.counter[0] ),
+ .Y(_058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _375_ (.A(\divider2.odd_0.initial_begin[0] ),
+ .Y(_059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _376_ (.A(\divider2.even_0.N[0] ),
+ .B(\divider2.even_0.N[1] ),
+ .Y(_060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _377_ (.A(\divider2.odd_0.initial_begin[1] ),
+ .B(\divider2.odd_0.initial_begin[0] ),
+ .Y(_061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _378_ (.A(\divider2.even_0.N[0] ),
+ .B(\divider2.even_0.N[2] ),
+ .C(\divider2.even_0.N[1] ),
+ .Y(_210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _379_ (.A1(\divider2.even_0.N[0] ),
+ .A2(\divider2.even_0.N[1] ),
+ .B1(\divider2.even_0.N[2] ),
+ .X(_064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _380_ (.A(_210_),
+ .B(_064_),
+ .Y(_062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _381_ (.A(\divider2.odd_0.initial_begin[1] ),
+ .B(\divider2.odd_0.initial_begin[0] ),
+ .Y(_211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _382_ (.A(\divider2.odd_0.initial_begin[2] ),
+ .B(_211_),
+ .X(_063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _383_ (.A(\divider2.odd_0.counter2[1] ),
+ .B(\divider2.odd_0.counter2[0] ),
+ .Y(_067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _384_ (.A(\divider2.odd_0.counter2[1] ),
+ .B(\divider2.odd_0.counter2[0] ),
+ .Y(_212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _385_ (.A(\divider2.odd_0.counter2[2] ),
+ .B(_212_),
+ .X(_069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _386_ (.A(\divider2.odd_0.counter[0] ),
+ .Y(_071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _387_ (.A(\divider2.odd_0.counter[1] ),
+ .B(\divider2.odd_0.counter[0] ),
+ .Y(_073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _388_ (.A(\divider2.odd_0.counter[1] ),
+ .B(\divider2.odd_0.counter[0] ),
+ .Y(_213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _389_ (.A(\divider2.odd_0.counter[2] ),
+ .B(_213_),
+ .X(_075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _390_ (.A(\divider2.even_0.counter[0] ),
+ .Y(_077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xnor2_1 _391_ (.A(\divider2.even_0.counter[1] ),
+ .B(\divider2.even_0.counter[0] ),
+ .Y(_078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _392_ (.A(net1),
+ .Y(pll_clk_sel),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _393_ (.A(net2),
+ .B(\reset_delay[0] ),
+ .Y(net11),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _394_ (.A(\divider2.even_0.counter[1] ),
+ .B(\divider2.even_0.N[0] ),
+ .C(\divider2.even_0.counter[0] ),
+ .Y(_214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__xor2_1 _395_ (.A(\divider2.even_0.counter[2] ),
+ .B(_214_),
+ .X(_120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 _396__13 (.LO(net13),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _397_ (.A0(_000_),
+ .A1(\divider2.odd_0.rst_pulse ),
+ .S(_033_),
+ .X(_002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _398_ (.A0(_001_),
+ .A1(\divider.odd_0.rst_pulse ),
+ .S(_029_),
+ .X(_003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _399_ (.A0(_037_),
+ .A1(\divider.out ),
+ .S(use_pll_second),
+ .X(net10),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _400_ (.A0(_037_),
+ .A1(\divider2.out ),
+ .S(use_pll_second),
+ .X(net12),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _401_ (.A0(_065_),
+ .A1(\divider2.even_0.N[0] ),
+ .S(_034_),
+ .X(_066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _402_ (.A0(_066_),
+ .A1(\divider2.even_0.N[0] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _403_ (.A0(_067_),
+ .A1(\divider2.even_0.N[1] ),
+ .S(_034_),
+ .X(_068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _404_ (.A0(_068_),
+ .A1(\divider2.even_0.N[1] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _405_ (.A0(_073_),
+ .A1(\divider2.even_0.N[1] ),
+ .S(_035_),
+ .X(_074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _406_ (.A0(_074_),
+ .A1(\divider2.even_0.N[1] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _407_ (.A0(_075_),
+ .A1(\divider2.even_0.N[2] ),
+ .S(_035_),
+ .X(_076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _408_ (.A0(_076_),
+ .A1(\divider2.even_0.N[2] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _409_ (.A0(_077_),
+ .A1(\divider2.even_0.N[1] ),
+ .S(_032_),
+ .X(_015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _410_ (.A0(_039_),
+ .A1(_040_),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _411_ (.A0(_041_),
+ .A1(_042_),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _412_ (.A0(_043_),
+ .A1(_044_),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _413_ (.A0(_045_),
+ .A1(\divider.even_0.N[0] ),
+ .S(_030_),
+ .X(_046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _414_ (.A0(_046_),
+ .A1(\divider.even_0.N[0] ),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _415_ (.A0(_047_),
+ .A1(\divider.even_0.N[1] ),
+ .S(_030_),
+ .X(_048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _416_ (.A0(_048_),
+ .A1(\divider.even_0.N[1] ),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _417_ (.A0(_049_),
+ .A1(\divider.even_0.N[2] ),
+ .S(_030_),
+ .X(_050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _418_ (.A0(_050_),
+ .A1(net37),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _419_ (.A0(_051_),
+ .A1(net35),
+ .S(_031_),
+ .X(_052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _420_ (.A0(_052_),
+ .A1(net36),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _421_ (.A0(_053_),
+ .A1(net26),
+ .S(_031_),
+ .X(_054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _422_ (.A0(_054_),
+ .A1(net26),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _423_ (.A0(_055_),
+ .A1(net37),
+ .S(_031_),
+ .X(_056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _424_ (.A0(_056_),
+ .A1(net30),
+ .S(\divider.odd_0.rst_pulse ),
+ .X(_011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _425_ (.A0(_057_),
+ .A1(net26),
+ .S(_028_),
+ .X(_004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _426_ (.A0(_058_),
+ .A1(net30),
+ .S(_028_),
+ .X(_005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _427_ (.A0(_059_),
+ .A1(_060_),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _428_ (.A0(_061_),
+ .A1(_062_),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _429_ (.A0(_063_),
+ .A1(_064_),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _430_ (.A0(_069_),
+ .A1(\divider2.even_0.N[2] ),
+ .S(_034_),
+ .X(_070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _431_ (.A0(_070_),
+ .A1(\divider2.even_0.N[2] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _432_ (.A0(_071_),
+ .A1(\divider2.even_0.N[0] ),
+ .S(_035_),
+ .X(_072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _433_ (.A0(_072_),
+ .A1(\divider2.even_0.N[0] ),
+ .S(\divider2.odd_0.rst_pulse ),
+ .X(_020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _434_ (.A0(_078_),
+ .A1(\divider2.even_0.N[2] ),
+ .S(_032_),
+ .X(_016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _435_ (.A0(\divider.even_0.out_counter ),
+ .A1(clknet_1_1_0_pll_clk),
+ .S(_026_),
+ .X(_036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _436_ (.A0(clknet_1_1_0_ext_clk),
+ .A1(ext_clk_syncd),
+ .S(use_pll_first),
+ .X(_037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _437_ (.A0(\divider2.even_0.out_counter ),
+ .A1(clknet_1_1_0_pll_clk90),
+ .S(_027_),
+ .X(_038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _438_ (.D(\divider.even_0.N[0] ),
+ .Q(\divider.odd_0.old_N[0] ),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _439_ (.D(net26),
+ .Q(\divider.odd_0.old_N[1] ),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _440_ (.D(net30),
+ .Q(\divider.odd_0.old_N[2] ),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _441_ (.D(\divider2.even_0.N[0] ),
+ .Q(\divider2.odd_0.old_N[0] ),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _442_ (.D(\divider2.even_0.N[1] ),
+ .Q(\divider2.odd_0.old_N[1] ),
+ .CLK(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _443_ (.D(\divider2.even_0.N[2] ),
+ .Q(\divider2.odd_0.old_N[2] ),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _444_ (.D(_088_),
+ .Q(ext_clk_syncd_pre),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _445_ (.D(net25),
+ .Q(\reset_delay[0] ),
+ .SET_B(net3),
+ .CLK(net20),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _446_ (.D(net24),
+ .Q(\reset_delay[1] ),
+ .SET_B(net3),
+ .CLK(net21),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _447_ (.D(net13),
+ .Q(\reset_delay[2] ),
+ .SET_B(net3),
+ .CLK(net22),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _448_ (.D(pll_clk_sel),
+ .Q(use_pll_first),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _449_ (.D(use_pll_first),
+ .Q(use_pll_second),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _450_ (.D(net23),
+ .Q(ext_clk_syncd),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _451_ (.D(net7),
+ .Q(\divider.syncNp[0] ),
+ .RESET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _452_ (.D(net8),
+ .Q(\divider.syncNp[1] ),
+ .SET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _453_ (.D(net9),
+ .Q(\divider.syncNp[2] ),
+ .RESET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _454_ (.D(\divider.syncNp[0] ),
+ .Q(\divider.even_0.N[0] ),
+ .RESET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_4 _455_ (.D(\divider.syncNp[1] ),
+ .Q(\divider.even_0.N[1] ),
+ .SET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _456_ (.D(\divider.syncNp[2] ),
+ .Q(\divider.even_0.N[2] ),
+ .RESET_B(net3),
+ .CLK(\divider.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _457_ (.D(net4),
+ .Q(\divider2.syncNp[0] ),
+ .RESET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _458_ (.D(net5),
+ .Q(\divider2.syncNp[1] ),
+ .SET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _459_ (.D(net6),
+ .Q(\divider2.syncNp[2] ),
+ .RESET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _460_ (.D(\divider2.syncNp[0] ),
+ .Q(\divider2.even_0.N[0] ),
+ .RESET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_4 _461_ (.D(\divider2.syncNp[1] ),
+ .Q(\divider2.even_0.N[1] ),
+ .SET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _462_ (.D(\divider2.syncNp[2] ),
+ .Q(\divider2.even_0.N[2] ),
+ .RESET_B(net3),
+ .CLK(\divider2.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _463_ (.D(_089_),
+ .Q(\divider.even_0.out_counter ),
+ .SET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _464_ (.D(_090_),
+ .Q(\divider.odd_0.counter2[0] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _465_ (.D(_091_),
+ .Q(\divider.odd_0.counter2[1] ),
+ .SET_B(net3),
+ .CLK(net19),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _466_ (.D(_092_),
+ .Q(\divider.odd_0.counter2[2] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _467_ (.D(_093_),
+ .Q(\divider.odd_0.rst_pulse ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_2 _468_ (.D(_094_),
+ .Q(\divider.even_0.counter[0] ),
+ .SET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _469_ (.D(_095_),
+ .Q(\divider.even_0.counter[1] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _470_ (.D(_096_),
+ .Q(\divider.even_0.counter[2] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _471_ (.D(_097_),
+ .Q(\divider.odd_0.out_counter2 ),
+ .SET_B(net3),
+ .CLK(net18),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _472_ (.D(_098_),
+ .Q(\divider.odd_0.initial_begin[0] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _473_ (.D(_099_),
+ .Q(\divider.odd_0.initial_begin[1] ),
+ .SET_B(net3),
+ .CLK(net17),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _474_ (.D(_100_),
+ .Q(\divider.odd_0.initial_begin[2] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _475_ (.D(_101_),
+ .Q(\divider.odd_0.counter[0] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _476_ (.D(_102_),
+ .Q(\divider.odd_0.counter[1] ),
+ .SET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _477_ (.D(_103_),
+ .Q(\divider.odd_0.counter[2] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _478_ (.D(_104_),
+ .Q(\divider.odd_0.out_counter ),
+ .SET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _479_ (.D(_105_),
+ .Q(\divider2.even_0.out_counter ),
+ .SET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _480_ (.D(_106_),
+ .Q(\divider2.odd_0.counter2[0] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _481_ (.D(_107_),
+ .Q(\divider2.odd_0.counter2[1] ),
+ .SET_B(net3),
+ .CLK(net16),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _482_ (.D(_108_),
+ .Q(\divider2.odd_0.counter2[2] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _483_ (.D(_109_),
+ .Q(\divider2.odd_0.out_counter2 ),
+ .SET_B(net3),
+ .CLK(net15),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _484_ (.D(_110_),
+ .Q(\divider2.odd_0.initial_begin[0] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _485_ (.D(_111_),
+ .Q(\divider2.odd_0.initial_begin[1] ),
+ .SET_B(net3),
+ .CLK(net14),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _486_ (.D(_112_),
+ .Q(\divider2.odd_0.initial_begin[2] ),
+ .RESET_B(net3),
+ .CLK_N(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _487_ (.D(_113_),
+ .Q(\divider2.odd_0.counter[0] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _488_ (.D(_114_),
+ .Q(\divider2.odd_0.counter[1] ),
+ .SET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _489_ (.D(_115_),
+ .Q(\divider2.odd_0.counter[2] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _490_ (.D(_116_),
+ .Q(\divider2.odd_0.out_counter ),
+ .SET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _491_ (.D(_117_),
+ .Q(\divider2.odd_0.rst_pulse ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _492_ (.D(_118_),
+ .Q(\divider2.even_0.counter[0] ),
+ .SET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _493_ (.D(_119_),
+ .Q(\divider2.even_0.counter[1] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _494_ (.D(_120_),
+ .Q(\divider2.even_0.counter[2] ),
+ .RESET_B(net3),
+ .CLK(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_ext_clk (.A(ext_clk),
+ .X(clknet_0_ext_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk (.A(pll_clk),
+ .X(clknet_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_pll_clk90 (.A(pll_clk90),
+ .X(clknet_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_ext_clk (.A(clknet_0_ext_clk),
+ .X(clknet_1_0_0_ext_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk (.A(clknet_0_pll_clk),
+ .X(clknet_1_0_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_pll_clk90 (.A(clknet_0_pll_clk90),
+ .X(clknet_1_0_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_ext_clk (.A(clknet_0_ext_clk),
+ .X(clknet_1_1_0_ext_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk (.A(clknet_0_pll_clk),
+ .X(clknet_1_1_0_pll_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_pll_clk90 (.A(clknet_0_pll_clk90),
+ .X(clknet_1_1_0_pll_clk90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(ext_clk_syncd_pre),
+ .X(net23),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(\reset_delay[2] ),
+ .X(net24),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(\reset_delay[1] ),
+ .X(net25),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input1 (.A(ext_clk_sel),
+ .X(net1),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input2 (.A(ext_reset),
+ .X(net2),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 input3 (.A(resetb),
+ .X(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input4 (.A(sel2[0]),
+ .X(net4),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input5 (.A(sel2[1]),
+ .X(net5),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input6 (.A(sel2[2]),
+ .X(net6),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input7 (.A(sel[0]),
+ .X(net7),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input8 (.A(sel[1]),
+ .X(net8),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input9 (.A(sel[2]),
+ .X(net9),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 output10 (.A(net10),
+ .X(core_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output11 (.A(net11),
+ .X(resetb_sync),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 output12 (.A(net12),
+ .X(user_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 rebuffer10 (.A(\divider.even_0.N[0] ),
+ .X(net32),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 rebuffer11 (.A(\divider.even_0.N[0] ),
+ .X(net33),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlygate4sd1_1 rebuffer12 (.A(net33),
+ .X(net34),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlygate4sd1_1 rebuffer13 (.A(\divider.even_0.N[0] ),
+ .X(net35),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlygate4sd1_1 rebuffer14 (.A(net35),
+ .X(net36),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlygate4sd1_1 rebuffer16 (.A(_029_),
+ .X(net38),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 rebuffer5 (.A(net37),
+ .X(net27),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlygate4sd1_1 rebuffer6 (.A(\divider.even_0.N[1] ),
+ .X(net28),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 rebuffer7 (.A(\divider.even_0.N[1] ),
+ .X(net29),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 rebuffer9 (.A(\divider.even_0.N[0] ),
+ .X(net31),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 split15 (.A(\divider.even_0.N[2] ),
+ .X(net37),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 split4 (.A(\divider.even_0.N[1] ),
+ .X(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 split8 (.A(net37),
+ .X(net30),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+endmodule
diff --git a/caravel/verilog/gl/chip_io.v b/caravel/verilog/gl/chip_io.v
new file mode 100644
index 0000000..9a8d37c
--- /dev/null
+++ b/caravel/verilog/gl/chip_io.v
@@ -0,0 +1,3803 @@
+/* Generated by Yosys 0.9+4052 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) */
+
+module chip_io(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_pad, vdda_pad, vssa_pad, vdda1_pad, vdda1_pad2, vdda2_pad, vssa1_pad, vssa1_pad2, vssa2_pad, vccd1_pad, vccd2_pad, vssd1_pad, vssd2_pad, vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, mprj_io, mprj_io_out, mprj_io_oeb, mprj_io_inp_dis, mprj_io_ib_mode_sel, mprj_io_vtrip_sel, mprj_io_slow_sel, mprj_io_holdover, mprj_io_analog_en, mprj_io_analog_sel, mprj_io_analog_pol, mprj_io_dm, mprj_io_in, mprj_analog_io);
+ wire analog_a;
+ wire analog_b;
+ input clock;
+ output clock_core;
+ wire \dm_all[0] ;
+ wire \dm_all[1] ;
+ wire \dm_all[2] ;
+ output flash_clk;
+ input flash_clk_core;
+ input flash_clk_ieb_core;
+ input flash_clk_oeb_core;
+ output flash_csb;
+ input flash_csb_core;
+ input flash_csb_ieb_core;
+ input flash_csb_oeb_core;
+ inout flash_io0;
+ output flash_io0_di_core;
+ input flash_io0_do_core;
+ input flash_io0_ieb_core;
+ wire \flash_io0_mode[0] ;
+ wire \flash_io0_mode[1] ;
+ wire \flash_io0_mode[2] ;
+ input flash_io0_oeb_core;
+ inout flash_io1;
+ output flash_io1_di_core;
+ input flash_io1_do_core;
+ input flash_io1_ieb_core;
+ wire \flash_io1_mode[0] ;
+ wire \flash_io1_mode[1] ;
+ wire \flash_io1_mode[2] ;
+ input flash_io1_oeb_core;
+ inout gpio;
+ output gpio_in_core;
+ input gpio_inenb_core;
+ input gpio_mode0_core;
+ input gpio_mode1_core;
+ input gpio_out_core;
+ input gpio_outenb_core;
+ wire loop_clock;
+ wire loop_flash_clk;
+ wire loop_flash_csb;
+ wire loop_flash_io0;
+ wire loop_flash_io1;
+ wire loop_gpio;
+ inout [28:0] mprj_analog_io;
+ inout [37:0] mprj_io;
+ input [37:0] mprj_io_analog_en;
+ input [37:0] mprj_io_analog_pol;
+ input [37:0] mprj_io_analog_sel;
+ input [113:0] mprj_io_dm;
+ wire \mprj_io_enh[0] ;
+ wire \mprj_io_enh[10] ;
+ wire \mprj_io_enh[11] ;
+ wire \mprj_io_enh[12] ;
+ wire \mprj_io_enh[13] ;
+ wire \mprj_io_enh[14] ;
+ wire \mprj_io_enh[15] ;
+ wire \mprj_io_enh[16] ;
+ wire \mprj_io_enh[17] ;
+ wire \mprj_io_enh[18] ;
+ wire \mprj_io_enh[19] ;
+ wire \mprj_io_enh[1] ;
+ wire \mprj_io_enh[20] ;
+ wire \mprj_io_enh[21] ;
+ wire \mprj_io_enh[22] ;
+ wire \mprj_io_enh[23] ;
+ wire \mprj_io_enh[24] ;
+ wire \mprj_io_enh[25] ;
+ wire \mprj_io_enh[26] ;
+ wire \mprj_io_enh[27] ;
+ wire \mprj_io_enh[28] ;
+ wire \mprj_io_enh[29] ;
+ wire \mprj_io_enh[2] ;
+ wire \mprj_io_enh[30] ;
+ wire \mprj_io_enh[31] ;
+ wire \mprj_io_enh[32] ;
+ wire \mprj_io_enh[33] ;
+ wire \mprj_io_enh[34] ;
+ wire \mprj_io_enh[35] ;
+ wire \mprj_io_enh[36] ;
+ wire \mprj_io_enh[37] ;
+ wire \mprj_io_enh[3] ;
+ wire \mprj_io_enh[4] ;
+ wire \mprj_io_enh[5] ;
+ wire \mprj_io_enh[6] ;
+ wire \mprj_io_enh[7] ;
+ wire \mprj_io_enh[8] ;
+ wire \mprj_io_enh[9] ;
+ wire \mprj_io_hldh_n[0] ;
+ wire \mprj_io_hldh_n[10] ;
+ wire \mprj_io_hldh_n[11] ;
+ wire \mprj_io_hldh_n[12] ;
+ wire \mprj_io_hldh_n[13] ;
+ wire \mprj_io_hldh_n[14] ;
+ wire \mprj_io_hldh_n[15] ;
+ wire \mprj_io_hldh_n[16] ;
+ wire \mprj_io_hldh_n[17] ;
+ wire \mprj_io_hldh_n[18] ;
+ wire \mprj_io_hldh_n[19] ;
+ wire \mprj_io_hldh_n[1] ;
+ wire \mprj_io_hldh_n[20] ;
+ wire \mprj_io_hldh_n[21] ;
+ wire \mprj_io_hldh_n[22] ;
+ wire \mprj_io_hldh_n[23] ;
+ wire \mprj_io_hldh_n[24] ;
+ wire \mprj_io_hldh_n[25] ;
+ wire \mprj_io_hldh_n[26] ;
+ wire \mprj_io_hldh_n[27] ;
+ wire \mprj_io_hldh_n[28] ;
+ wire \mprj_io_hldh_n[29] ;
+ wire \mprj_io_hldh_n[2] ;
+ wire \mprj_io_hldh_n[30] ;
+ wire \mprj_io_hldh_n[31] ;
+ wire \mprj_io_hldh_n[32] ;
+ wire \mprj_io_hldh_n[33] ;
+ wire \mprj_io_hldh_n[34] ;
+ wire \mprj_io_hldh_n[35] ;
+ wire \mprj_io_hldh_n[36] ;
+ wire \mprj_io_hldh_n[37] ;
+ wire \mprj_io_hldh_n[3] ;
+ wire \mprj_io_hldh_n[4] ;
+ wire \mprj_io_hldh_n[5] ;
+ wire \mprj_io_hldh_n[6] ;
+ wire \mprj_io_hldh_n[7] ;
+ wire \mprj_io_hldh_n[8] ;
+ wire \mprj_io_hldh_n[9] ;
+ input [37:0] mprj_io_holdover;
+ input [37:0] mprj_io_ib_mode_sel;
+ output [37:0] mprj_io_in;
+ input [37:0] mprj_io_inp_dis;
+ input [37:0] mprj_io_oeb;
+ input [37:0] mprj_io_out;
+ input [37:0] mprj_io_slow_sel;
+ input [37:0] mprj_io_vtrip_sel;
+ wire \mprj_pads.analog_a ;
+ wire \mprj_pads.analog_b ;
+ wire \mprj_pads.analog_en[0] ;
+ wire \mprj_pads.analog_en[10] ;
+ wire \mprj_pads.analog_en[11] ;
+ wire \mprj_pads.analog_en[12] ;
+ wire \mprj_pads.analog_en[13] ;
+ wire \mprj_pads.analog_en[14] ;
+ wire \mprj_pads.analog_en[15] ;
+ wire \mprj_pads.analog_en[16] ;
+ wire \mprj_pads.analog_en[17] ;
+ wire \mprj_pads.analog_en[18] ;
+ wire \mprj_pads.analog_en[19] ;
+ wire \mprj_pads.analog_en[1] ;
+ wire \mprj_pads.analog_en[20] ;
+ wire \mprj_pads.analog_en[21] ;
+ wire \mprj_pads.analog_en[22] ;
+ wire \mprj_pads.analog_en[23] ;
+ wire \mprj_pads.analog_en[24] ;
+ wire \mprj_pads.analog_en[25] ;
+ wire \mprj_pads.analog_en[26] ;
+ wire \mprj_pads.analog_en[27] ;
+ wire \mprj_pads.analog_en[28] ;
+ wire \mprj_pads.analog_en[29] ;
+ wire \mprj_pads.analog_en[2] ;
+ wire \mprj_pads.analog_en[30] ;
+ wire \mprj_pads.analog_en[31] ;
+ wire \mprj_pads.analog_en[32] ;
+ wire \mprj_pads.analog_en[33] ;
+ wire \mprj_pads.analog_en[34] ;
+ wire \mprj_pads.analog_en[35] ;
+ wire \mprj_pads.analog_en[36] ;
+ wire \mprj_pads.analog_en[37] ;
+ wire \mprj_pads.analog_en[3] ;
+ wire \mprj_pads.analog_en[4] ;
+ wire \mprj_pads.analog_en[5] ;
+ wire \mprj_pads.analog_en[6] ;
+ wire \mprj_pads.analog_en[7] ;
+ wire \mprj_pads.analog_en[8] ;
+ wire \mprj_pads.analog_en[9] ;
+ wire \mprj_pads.analog_io[0] ;
+ wire \mprj_pads.analog_io[10] ;
+ wire \mprj_pads.analog_io[11] ;
+ wire \mprj_pads.analog_io[12] ;
+ wire \mprj_pads.analog_io[13] ;
+ wire \mprj_pads.analog_io[14] ;
+ wire \mprj_pads.analog_io[15] ;
+ wire \mprj_pads.analog_io[16] ;
+ wire \mprj_pads.analog_io[17] ;
+ wire \mprj_pads.analog_io[18] ;
+ wire \mprj_pads.analog_io[19] ;
+ wire \mprj_pads.analog_io[1] ;
+ wire \mprj_pads.analog_io[20] ;
+ wire \mprj_pads.analog_io[21] ;
+ wire \mprj_pads.analog_io[22] ;
+ wire \mprj_pads.analog_io[23] ;
+ wire \mprj_pads.analog_io[24] ;
+ wire \mprj_pads.analog_io[25] ;
+ wire \mprj_pads.analog_io[26] ;
+ wire \mprj_pads.analog_io[27] ;
+ wire \mprj_pads.analog_io[28] ;
+ wire \mprj_pads.analog_io[2] ;
+ wire \mprj_pads.analog_io[3] ;
+ wire \mprj_pads.analog_io[4] ;
+ wire \mprj_pads.analog_io[5] ;
+ wire \mprj_pads.analog_io[6] ;
+ wire \mprj_pads.analog_io[7] ;
+ wire \mprj_pads.analog_io[8] ;
+ wire \mprj_pads.analog_io[9] ;
+ wire \mprj_pads.analog_noesd_io[0] ;
+ wire \mprj_pads.analog_noesd_io[10] ;
+ wire \mprj_pads.analog_noesd_io[11] ;
+ wire \mprj_pads.analog_noesd_io[12] ;
+ wire \mprj_pads.analog_noesd_io[13] ;
+ wire \mprj_pads.analog_noesd_io[14] ;
+ wire \mprj_pads.analog_noesd_io[15] ;
+ wire \mprj_pads.analog_noesd_io[16] ;
+ wire \mprj_pads.analog_noesd_io[17] ;
+ wire \mprj_pads.analog_noesd_io[18] ;
+ wire \mprj_pads.analog_noesd_io[19] ;
+ wire \mprj_pads.analog_noesd_io[1] ;
+ wire \mprj_pads.analog_noesd_io[20] ;
+ wire \mprj_pads.analog_noesd_io[21] ;
+ wire \mprj_pads.analog_noesd_io[22] ;
+ wire \mprj_pads.analog_noesd_io[23] ;
+ wire \mprj_pads.analog_noesd_io[24] ;
+ wire \mprj_pads.analog_noesd_io[25] ;
+ wire \mprj_pads.analog_noesd_io[26] ;
+ wire \mprj_pads.analog_noesd_io[27] ;
+ wire \mprj_pads.analog_noesd_io[28] ;
+ wire \mprj_pads.analog_noesd_io[2] ;
+ wire \mprj_pads.analog_noesd_io[3] ;
+ wire \mprj_pads.analog_noesd_io[4] ;
+ wire \mprj_pads.analog_noesd_io[5] ;
+ wire \mprj_pads.analog_noesd_io[6] ;
+ wire \mprj_pads.analog_noesd_io[7] ;
+ wire \mprj_pads.analog_noesd_io[8] ;
+ wire \mprj_pads.analog_noesd_io[9] ;
+ wire \mprj_pads.analog_pol[0] ;
+ wire \mprj_pads.analog_pol[10] ;
+ wire \mprj_pads.analog_pol[11] ;
+ wire \mprj_pads.analog_pol[12] ;
+ wire \mprj_pads.analog_pol[13] ;
+ wire \mprj_pads.analog_pol[14] ;
+ wire \mprj_pads.analog_pol[15] ;
+ wire \mprj_pads.analog_pol[16] ;
+ wire \mprj_pads.analog_pol[17] ;
+ wire \mprj_pads.analog_pol[18] ;
+ wire \mprj_pads.analog_pol[19] ;
+ wire \mprj_pads.analog_pol[1] ;
+ wire \mprj_pads.analog_pol[20] ;
+ wire \mprj_pads.analog_pol[21] ;
+ wire \mprj_pads.analog_pol[22] ;
+ wire \mprj_pads.analog_pol[23] ;
+ wire \mprj_pads.analog_pol[24] ;
+ wire \mprj_pads.analog_pol[25] ;
+ wire \mprj_pads.analog_pol[26] ;
+ wire \mprj_pads.analog_pol[27] ;
+ wire \mprj_pads.analog_pol[28] ;
+ wire \mprj_pads.analog_pol[29] ;
+ wire \mprj_pads.analog_pol[2] ;
+ wire \mprj_pads.analog_pol[30] ;
+ wire \mprj_pads.analog_pol[31] ;
+ wire \mprj_pads.analog_pol[32] ;
+ wire \mprj_pads.analog_pol[33] ;
+ wire \mprj_pads.analog_pol[34] ;
+ wire \mprj_pads.analog_pol[35] ;
+ wire \mprj_pads.analog_pol[36] ;
+ wire \mprj_pads.analog_pol[37] ;
+ wire \mprj_pads.analog_pol[3] ;
+ wire \mprj_pads.analog_pol[4] ;
+ wire \mprj_pads.analog_pol[5] ;
+ wire \mprj_pads.analog_pol[6] ;
+ wire \mprj_pads.analog_pol[7] ;
+ wire \mprj_pads.analog_pol[8] ;
+ wire \mprj_pads.analog_pol[9] ;
+ wire \mprj_pads.analog_sel[0] ;
+ wire \mprj_pads.analog_sel[10] ;
+ wire \mprj_pads.analog_sel[11] ;
+ wire \mprj_pads.analog_sel[12] ;
+ wire \mprj_pads.analog_sel[13] ;
+ wire \mprj_pads.analog_sel[14] ;
+ wire \mprj_pads.analog_sel[15] ;
+ wire \mprj_pads.analog_sel[16] ;
+ wire \mprj_pads.analog_sel[17] ;
+ wire \mprj_pads.analog_sel[18] ;
+ wire \mprj_pads.analog_sel[19] ;
+ wire \mprj_pads.analog_sel[1] ;
+ wire \mprj_pads.analog_sel[20] ;
+ wire \mprj_pads.analog_sel[21] ;
+ wire \mprj_pads.analog_sel[22] ;
+ wire \mprj_pads.analog_sel[23] ;
+ wire \mprj_pads.analog_sel[24] ;
+ wire \mprj_pads.analog_sel[25] ;
+ wire \mprj_pads.analog_sel[26] ;
+ wire \mprj_pads.analog_sel[27] ;
+ wire \mprj_pads.analog_sel[28] ;
+ wire \mprj_pads.analog_sel[29] ;
+ wire \mprj_pads.analog_sel[2] ;
+ wire \mprj_pads.analog_sel[30] ;
+ wire \mprj_pads.analog_sel[31] ;
+ wire \mprj_pads.analog_sel[32] ;
+ wire \mprj_pads.analog_sel[33] ;
+ wire \mprj_pads.analog_sel[34] ;
+ wire \mprj_pads.analog_sel[35] ;
+ wire \mprj_pads.analog_sel[36] ;
+ wire \mprj_pads.analog_sel[37] ;
+ wire \mprj_pads.analog_sel[3] ;
+ wire \mprj_pads.analog_sel[4] ;
+ wire \mprj_pads.analog_sel[5] ;
+ wire \mprj_pads.analog_sel[6] ;
+ wire \mprj_pads.analog_sel[7] ;
+ wire \mprj_pads.analog_sel[8] ;
+ wire \mprj_pads.analog_sel[9] ;
+ wire \mprj_pads.dm[0] ;
+ wire \mprj_pads.dm[100] ;
+ wire \mprj_pads.dm[101] ;
+ wire \mprj_pads.dm[102] ;
+ wire \mprj_pads.dm[103] ;
+ wire \mprj_pads.dm[104] ;
+ wire \mprj_pads.dm[105] ;
+ wire \mprj_pads.dm[106] ;
+ wire \mprj_pads.dm[107] ;
+ wire \mprj_pads.dm[108] ;
+ wire \mprj_pads.dm[109] ;
+ wire \mprj_pads.dm[10] ;
+ wire \mprj_pads.dm[110] ;
+ wire \mprj_pads.dm[111] ;
+ wire \mprj_pads.dm[112] ;
+ wire \mprj_pads.dm[113] ;
+ wire \mprj_pads.dm[11] ;
+ wire \mprj_pads.dm[12] ;
+ wire \mprj_pads.dm[13] ;
+ wire \mprj_pads.dm[14] ;
+ wire \mprj_pads.dm[15] ;
+ wire \mprj_pads.dm[16] ;
+ wire \mprj_pads.dm[17] ;
+ wire \mprj_pads.dm[18] ;
+ wire \mprj_pads.dm[19] ;
+ wire \mprj_pads.dm[1] ;
+ wire \mprj_pads.dm[20] ;
+ wire \mprj_pads.dm[21] ;
+ wire \mprj_pads.dm[22] ;
+ wire \mprj_pads.dm[23] ;
+ wire \mprj_pads.dm[24] ;
+ wire \mprj_pads.dm[25] ;
+ wire \mprj_pads.dm[26] ;
+ wire \mprj_pads.dm[27] ;
+ wire \mprj_pads.dm[28] ;
+ wire \mprj_pads.dm[29] ;
+ wire \mprj_pads.dm[2] ;
+ wire \mprj_pads.dm[30] ;
+ wire \mprj_pads.dm[31] ;
+ wire \mprj_pads.dm[32] ;
+ wire \mprj_pads.dm[33] ;
+ wire \mprj_pads.dm[34] ;
+ wire \mprj_pads.dm[35] ;
+ wire \mprj_pads.dm[36] ;
+ wire \mprj_pads.dm[37] ;
+ wire \mprj_pads.dm[38] ;
+ wire \mprj_pads.dm[39] ;
+ wire \mprj_pads.dm[3] ;
+ wire \mprj_pads.dm[40] ;
+ wire \mprj_pads.dm[41] ;
+ wire \mprj_pads.dm[42] ;
+ wire \mprj_pads.dm[43] ;
+ wire \mprj_pads.dm[44] ;
+ wire \mprj_pads.dm[45] ;
+ wire \mprj_pads.dm[46] ;
+ wire \mprj_pads.dm[47] ;
+ wire \mprj_pads.dm[48] ;
+ wire \mprj_pads.dm[49] ;
+ wire \mprj_pads.dm[4] ;
+ wire \mprj_pads.dm[50] ;
+ wire \mprj_pads.dm[51] ;
+ wire \mprj_pads.dm[52] ;
+ wire \mprj_pads.dm[53] ;
+ wire \mprj_pads.dm[54] ;
+ wire \mprj_pads.dm[55] ;
+ wire \mprj_pads.dm[56] ;
+ wire \mprj_pads.dm[57] ;
+ wire \mprj_pads.dm[58] ;
+ wire \mprj_pads.dm[59] ;
+ wire \mprj_pads.dm[5] ;
+ wire \mprj_pads.dm[60] ;
+ wire \mprj_pads.dm[61] ;
+ wire \mprj_pads.dm[62] ;
+ wire \mprj_pads.dm[63] ;
+ wire \mprj_pads.dm[64] ;
+ wire \mprj_pads.dm[65] ;
+ wire \mprj_pads.dm[66] ;
+ wire \mprj_pads.dm[67] ;
+ wire \mprj_pads.dm[68] ;
+ wire \mprj_pads.dm[69] ;
+ wire \mprj_pads.dm[6] ;
+ wire \mprj_pads.dm[70] ;
+ wire \mprj_pads.dm[71] ;
+ wire \mprj_pads.dm[72] ;
+ wire \mprj_pads.dm[73] ;
+ wire \mprj_pads.dm[74] ;
+ wire \mprj_pads.dm[75] ;
+ wire \mprj_pads.dm[76] ;
+ wire \mprj_pads.dm[77] ;
+ wire \mprj_pads.dm[78] ;
+ wire \mprj_pads.dm[79] ;
+ wire \mprj_pads.dm[7] ;
+ wire \mprj_pads.dm[80] ;
+ wire \mprj_pads.dm[81] ;
+ wire \mprj_pads.dm[82] ;
+ wire \mprj_pads.dm[83] ;
+ wire \mprj_pads.dm[84] ;
+ wire \mprj_pads.dm[85] ;
+ wire \mprj_pads.dm[86] ;
+ wire \mprj_pads.dm[87] ;
+ wire \mprj_pads.dm[88] ;
+ wire \mprj_pads.dm[89] ;
+ wire \mprj_pads.dm[8] ;
+ wire \mprj_pads.dm[90] ;
+ wire \mprj_pads.dm[91] ;
+ wire \mprj_pads.dm[92] ;
+ wire \mprj_pads.dm[93] ;
+ wire \mprj_pads.dm[94] ;
+ wire \mprj_pads.dm[95] ;
+ wire \mprj_pads.dm[96] ;
+ wire \mprj_pads.dm[97] ;
+ wire \mprj_pads.dm[98] ;
+ wire \mprj_pads.dm[99] ;
+ wire \mprj_pads.dm[9] ;
+ wire \mprj_pads.enh[0] ;
+ wire \mprj_pads.enh[10] ;
+ wire \mprj_pads.enh[11] ;
+ wire \mprj_pads.enh[12] ;
+ wire \mprj_pads.enh[13] ;
+ wire \mprj_pads.enh[14] ;
+ wire \mprj_pads.enh[15] ;
+ wire \mprj_pads.enh[16] ;
+ wire \mprj_pads.enh[17] ;
+ wire \mprj_pads.enh[18] ;
+ wire \mprj_pads.enh[19] ;
+ wire \mprj_pads.enh[1] ;
+ wire \mprj_pads.enh[20] ;
+ wire \mprj_pads.enh[21] ;
+ wire \mprj_pads.enh[22] ;
+ wire \mprj_pads.enh[23] ;
+ wire \mprj_pads.enh[24] ;
+ wire \mprj_pads.enh[25] ;
+ wire \mprj_pads.enh[26] ;
+ wire \mprj_pads.enh[27] ;
+ wire \mprj_pads.enh[28] ;
+ wire \mprj_pads.enh[29] ;
+ wire \mprj_pads.enh[2] ;
+ wire \mprj_pads.enh[30] ;
+ wire \mprj_pads.enh[31] ;
+ wire \mprj_pads.enh[32] ;
+ wire \mprj_pads.enh[33] ;
+ wire \mprj_pads.enh[34] ;
+ wire \mprj_pads.enh[35] ;
+ wire \mprj_pads.enh[36] ;
+ wire \mprj_pads.enh[37] ;
+ wire \mprj_pads.enh[3] ;
+ wire \mprj_pads.enh[4] ;
+ wire \mprj_pads.enh[5] ;
+ wire \mprj_pads.enh[6] ;
+ wire \mprj_pads.enh[7] ;
+ wire \mprj_pads.enh[8] ;
+ wire \mprj_pads.enh[9] ;
+ wire \mprj_pads.hldh_n[0] ;
+ wire \mprj_pads.hldh_n[10] ;
+ wire \mprj_pads.hldh_n[11] ;
+ wire \mprj_pads.hldh_n[12] ;
+ wire \mprj_pads.hldh_n[13] ;
+ wire \mprj_pads.hldh_n[14] ;
+ wire \mprj_pads.hldh_n[15] ;
+ wire \mprj_pads.hldh_n[16] ;
+ wire \mprj_pads.hldh_n[17] ;
+ wire \mprj_pads.hldh_n[18] ;
+ wire \mprj_pads.hldh_n[19] ;
+ wire \mprj_pads.hldh_n[1] ;
+ wire \mprj_pads.hldh_n[20] ;
+ wire \mprj_pads.hldh_n[21] ;
+ wire \mprj_pads.hldh_n[22] ;
+ wire \mprj_pads.hldh_n[23] ;
+ wire \mprj_pads.hldh_n[24] ;
+ wire \mprj_pads.hldh_n[25] ;
+ wire \mprj_pads.hldh_n[26] ;
+ wire \mprj_pads.hldh_n[27] ;
+ wire \mprj_pads.hldh_n[28] ;
+ wire \mprj_pads.hldh_n[29] ;
+ wire \mprj_pads.hldh_n[2] ;
+ wire \mprj_pads.hldh_n[30] ;
+ wire \mprj_pads.hldh_n[31] ;
+ wire \mprj_pads.hldh_n[32] ;
+ wire \mprj_pads.hldh_n[33] ;
+ wire \mprj_pads.hldh_n[34] ;
+ wire \mprj_pads.hldh_n[35] ;
+ wire \mprj_pads.hldh_n[36] ;
+ wire \mprj_pads.hldh_n[37] ;
+ wire \mprj_pads.hldh_n[3] ;
+ wire \mprj_pads.hldh_n[4] ;
+ wire \mprj_pads.hldh_n[5] ;
+ wire \mprj_pads.hldh_n[6] ;
+ wire \mprj_pads.hldh_n[7] ;
+ wire \mprj_pads.hldh_n[8] ;
+ wire \mprj_pads.hldh_n[9] ;
+ wire \mprj_pads.holdover[0] ;
+ wire \mprj_pads.holdover[10] ;
+ wire \mprj_pads.holdover[11] ;
+ wire \mprj_pads.holdover[12] ;
+ wire \mprj_pads.holdover[13] ;
+ wire \mprj_pads.holdover[14] ;
+ wire \mprj_pads.holdover[15] ;
+ wire \mprj_pads.holdover[16] ;
+ wire \mprj_pads.holdover[17] ;
+ wire \mprj_pads.holdover[18] ;
+ wire \mprj_pads.holdover[19] ;
+ wire \mprj_pads.holdover[1] ;
+ wire \mprj_pads.holdover[20] ;
+ wire \mprj_pads.holdover[21] ;
+ wire \mprj_pads.holdover[22] ;
+ wire \mprj_pads.holdover[23] ;
+ wire \mprj_pads.holdover[24] ;
+ wire \mprj_pads.holdover[25] ;
+ wire \mprj_pads.holdover[26] ;
+ wire \mprj_pads.holdover[27] ;
+ wire \mprj_pads.holdover[28] ;
+ wire \mprj_pads.holdover[29] ;
+ wire \mprj_pads.holdover[2] ;
+ wire \mprj_pads.holdover[30] ;
+ wire \mprj_pads.holdover[31] ;
+ wire \mprj_pads.holdover[32] ;
+ wire \mprj_pads.holdover[33] ;
+ wire \mprj_pads.holdover[34] ;
+ wire \mprj_pads.holdover[35] ;
+ wire \mprj_pads.holdover[36] ;
+ wire \mprj_pads.holdover[37] ;
+ wire \mprj_pads.holdover[3] ;
+ wire \mprj_pads.holdover[4] ;
+ wire \mprj_pads.holdover[5] ;
+ wire \mprj_pads.holdover[6] ;
+ wire \mprj_pads.holdover[7] ;
+ wire \mprj_pads.holdover[8] ;
+ wire \mprj_pads.holdover[9] ;
+ wire \mprj_pads.ib_mode_sel[0] ;
+ wire \mprj_pads.ib_mode_sel[10] ;
+ wire \mprj_pads.ib_mode_sel[11] ;
+ wire \mprj_pads.ib_mode_sel[12] ;
+ wire \mprj_pads.ib_mode_sel[13] ;
+ wire \mprj_pads.ib_mode_sel[14] ;
+ wire \mprj_pads.ib_mode_sel[15] ;
+ wire \mprj_pads.ib_mode_sel[16] ;
+ wire \mprj_pads.ib_mode_sel[17] ;
+ wire \mprj_pads.ib_mode_sel[18] ;
+ wire \mprj_pads.ib_mode_sel[19] ;
+ wire \mprj_pads.ib_mode_sel[1] ;
+ wire \mprj_pads.ib_mode_sel[20] ;
+ wire \mprj_pads.ib_mode_sel[21] ;
+ wire \mprj_pads.ib_mode_sel[22] ;
+ wire \mprj_pads.ib_mode_sel[23] ;
+ wire \mprj_pads.ib_mode_sel[24] ;
+ wire \mprj_pads.ib_mode_sel[25] ;
+ wire \mprj_pads.ib_mode_sel[26] ;
+ wire \mprj_pads.ib_mode_sel[27] ;
+ wire \mprj_pads.ib_mode_sel[28] ;
+ wire \mprj_pads.ib_mode_sel[29] ;
+ wire \mprj_pads.ib_mode_sel[2] ;
+ wire \mprj_pads.ib_mode_sel[30] ;
+ wire \mprj_pads.ib_mode_sel[31] ;
+ wire \mprj_pads.ib_mode_sel[32] ;
+ wire \mprj_pads.ib_mode_sel[33] ;
+ wire \mprj_pads.ib_mode_sel[34] ;
+ wire \mprj_pads.ib_mode_sel[35] ;
+ wire \mprj_pads.ib_mode_sel[36] ;
+ wire \mprj_pads.ib_mode_sel[37] ;
+ wire \mprj_pads.ib_mode_sel[3] ;
+ wire \mprj_pads.ib_mode_sel[4] ;
+ wire \mprj_pads.ib_mode_sel[5] ;
+ wire \mprj_pads.ib_mode_sel[6] ;
+ wire \mprj_pads.ib_mode_sel[7] ;
+ wire \mprj_pads.ib_mode_sel[8] ;
+ wire \mprj_pads.ib_mode_sel[9] ;
+ wire \mprj_pads.inp_dis[0] ;
+ wire \mprj_pads.inp_dis[10] ;
+ wire \mprj_pads.inp_dis[11] ;
+ wire \mprj_pads.inp_dis[12] ;
+ wire \mprj_pads.inp_dis[13] ;
+ wire \mprj_pads.inp_dis[14] ;
+ wire \mprj_pads.inp_dis[15] ;
+ wire \mprj_pads.inp_dis[16] ;
+ wire \mprj_pads.inp_dis[17] ;
+ wire \mprj_pads.inp_dis[18] ;
+ wire \mprj_pads.inp_dis[19] ;
+ wire \mprj_pads.inp_dis[1] ;
+ wire \mprj_pads.inp_dis[20] ;
+ wire \mprj_pads.inp_dis[21] ;
+ wire \mprj_pads.inp_dis[22] ;
+ wire \mprj_pads.inp_dis[23] ;
+ wire \mprj_pads.inp_dis[24] ;
+ wire \mprj_pads.inp_dis[25] ;
+ wire \mprj_pads.inp_dis[26] ;
+ wire \mprj_pads.inp_dis[27] ;
+ wire \mprj_pads.inp_dis[28] ;
+ wire \mprj_pads.inp_dis[29] ;
+ wire \mprj_pads.inp_dis[2] ;
+ wire \mprj_pads.inp_dis[30] ;
+ wire \mprj_pads.inp_dis[31] ;
+ wire \mprj_pads.inp_dis[32] ;
+ wire \mprj_pads.inp_dis[33] ;
+ wire \mprj_pads.inp_dis[34] ;
+ wire \mprj_pads.inp_dis[35] ;
+ wire \mprj_pads.inp_dis[36] ;
+ wire \mprj_pads.inp_dis[37] ;
+ wire \mprj_pads.inp_dis[3] ;
+ wire \mprj_pads.inp_dis[4] ;
+ wire \mprj_pads.inp_dis[5] ;
+ wire \mprj_pads.inp_dis[6] ;
+ wire \mprj_pads.inp_dis[7] ;
+ wire \mprj_pads.inp_dis[8] ;
+ wire \mprj_pads.inp_dis[9] ;
+ wire \mprj_pads.io[0] ;
+ wire \mprj_pads.io[10] ;
+ wire \mprj_pads.io[11] ;
+ wire \mprj_pads.io[12] ;
+ wire \mprj_pads.io[13] ;
+ wire \mprj_pads.io[14] ;
+ wire \mprj_pads.io[15] ;
+ wire \mprj_pads.io[16] ;
+ wire \mprj_pads.io[17] ;
+ wire \mprj_pads.io[18] ;
+ wire \mprj_pads.io[19] ;
+ wire \mprj_pads.io[1] ;
+ wire \mprj_pads.io[20] ;
+ wire \mprj_pads.io[21] ;
+ wire \mprj_pads.io[22] ;
+ wire \mprj_pads.io[23] ;
+ wire \mprj_pads.io[24] ;
+ wire \mprj_pads.io[25] ;
+ wire \mprj_pads.io[26] ;
+ wire \mprj_pads.io[27] ;
+ wire \mprj_pads.io[28] ;
+ wire \mprj_pads.io[29] ;
+ wire \mprj_pads.io[2] ;
+ wire \mprj_pads.io[30] ;
+ wire \mprj_pads.io[31] ;
+ wire \mprj_pads.io[32] ;
+ wire \mprj_pads.io[33] ;
+ wire \mprj_pads.io[34] ;
+ wire \mprj_pads.io[35] ;
+ wire \mprj_pads.io[36] ;
+ wire \mprj_pads.io[37] ;
+ wire \mprj_pads.io[3] ;
+ wire \mprj_pads.io[4] ;
+ wire \mprj_pads.io[5] ;
+ wire \mprj_pads.io[6] ;
+ wire \mprj_pads.io[7] ;
+ wire \mprj_pads.io[8] ;
+ wire \mprj_pads.io[9] ;
+ wire \mprj_pads.io_in[0] ;
+ wire \mprj_pads.io_in[10] ;
+ wire \mprj_pads.io_in[11] ;
+ wire \mprj_pads.io_in[12] ;
+ wire \mprj_pads.io_in[13] ;
+ wire \mprj_pads.io_in[14] ;
+ wire \mprj_pads.io_in[15] ;
+ wire \mprj_pads.io_in[16] ;
+ wire \mprj_pads.io_in[17] ;
+ wire \mprj_pads.io_in[18] ;
+ wire \mprj_pads.io_in[19] ;
+ wire \mprj_pads.io_in[1] ;
+ wire \mprj_pads.io_in[20] ;
+ wire \mprj_pads.io_in[21] ;
+ wire \mprj_pads.io_in[22] ;
+ wire \mprj_pads.io_in[23] ;
+ wire \mprj_pads.io_in[24] ;
+ wire \mprj_pads.io_in[25] ;
+ wire \mprj_pads.io_in[26] ;
+ wire \mprj_pads.io_in[27] ;
+ wire \mprj_pads.io_in[28] ;
+ wire \mprj_pads.io_in[29] ;
+ wire \mprj_pads.io_in[2] ;
+ wire \mprj_pads.io_in[30] ;
+ wire \mprj_pads.io_in[31] ;
+ wire \mprj_pads.io_in[32] ;
+ wire \mprj_pads.io_in[33] ;
+ wire \mprj_pads.io_in[34] ;
+ wire \mprj_pads.io_in[35] ;
+ wire \mprj_pads.io_in[36] ;
+ wire \mprj_pads.io_in[37] ;
+ wire \mprj_pads.io_in[3] ;
+ wire \mprj_pads.io_in[4] ;
+ wire \mprj_pads.io_in[5] ;
+ wire \mprj_pads.io_in[6] ;
+ wire \mprj_pads.io_in[7] ;
+ wire \mprj_pads.io_in[8] ;
+ wire \mprj_pads.io_in[9] ;
+ wire \mprj_pads.io_in_3v3[0] ;
+ wire \mprj_pads.io_in_3v3[10] ;
+ wire \mprj_pads.io_in_3v3[11] ;
+ wire \mprj_pads.io_in_3v3[12] ;
+ wire \mprj_pads.io_in_3v3[13] ;
+ wire \mprj_pads.io_in_3v3[14] ;
+ wire \mprj_pads.io_in_3v3[15] ;
+ wire \mprj_pads.io_in_3v3[16] ;
+ wire \mprj_pads.io_in_3v3[17] ;
+ wire \mprj_pads.io_in_3v3[18] ;
+ wire \mprj_pads.io_in_3v3[19] ;
+ wire \mprj_pads.io_in_3v3[1] ;
+ wire \mprj_pads.io_in_3v3[20] ;
+ wire \mprj_pads.io_in_3v3[21] ;
+ wire \mprj_pads.io_in_3v3[22] ;
+ wire \mprj_pads.io_in_3v3[23] ;
+ wire \mprj_pads.io_in_3v3[24] ;
+ wire \mprj_pads.io_in_3v3[25] ;
+ wire \mprj_pads.io_in_3v3[26] ;
+ wire \mprj_pads.io_in_3v3[27] ;
+ wire \mprj_pads.io_in_3v3[28] ;
+ wire \mprj_pads.io_in_3v3[29] ;
+ wire \mprj_pads.io_in_3v3[2] ;
+ wire \mprj_pads.io_in_3v3[30] ;
+ wire \mprj_pads.io_in_3v3[31] ;
+ wire \mprj_pads.io_in_3v3[32] ;
+ wire \mprj_pads.io_in_3v3[33] ;
+ wire \mprj_pads.io_in_3v3[34] ;
+ wire \mprj_pads.io_in_3v3[35] ;
+ wire \mprj_pads.io_in_3v3[36] ;
+ wire \mprj_pads.io_in_3v3[37] ;
+ wire \mprj_pads.io_in_3v3[3] ;
+ wire \mprj_pads.io_in_3v3[4] ;
+ wire \mprj_pads.io_in_3v3[5] ;
+ wire \mprj_pads.io_in_3v3[6] ;
+ wire \mprj_pads.io_in_3v3[7] ;
+ wire \mprj_pads.io_in_3v3[8] ;
+ wire \mprj_pads.io_in_3v3[9] ;
+ wire \mprj_pads.io_out[0] ;
+ wire \mprj_pads.io_out[10] ;
+ wire \mprj_pads.io_out[11] ;
+ wire \mprj_pads.io_out[12] ;
+ wire \mprj_pads.io_out[13] ;
+ wire \mprj_pads.io_out[14] ;
+ wire \mprj_pads.io_out[15] ;
+ wire \mprj_pads.io_out[16] ;
+ wire \mprj_pads.io_out[17] ;
+ wire \mprj_pads.io_out[18] ;
+ wire \mprj_pads.io_out[19] ;
+ wire \mprj_pads.io_out[1] ;
+ wire \mprj_pads.io_out[20] ;
+ wire \mprj_pads.io_out[21] ;
+ wire \mprj_pads.io_out[22] ;
+ wire \mprj_pads.io_out[23] ;
+ wire \mprj_pads.io_out[24] ;
+ wire \mprj_pads.io_out[25] ;
+ wire \mprj_pads.io_out[26] ;
+ wire \mprj_pads.io_out[27] ;
+ wire \mprj_pads.io_out[28] ;
+ wire \mprj_pads.io_out[29] ;
+ wire \mprj_pads.io_out[2] ;
+ wire \mprj_pads.io_out[30] ;
+ wire \mprj_pads.io_out[31] ;
+ wire \mprj_pads.io_out[32] ;
+ wire \mprj_pads.io_out[33] ;
+ wire \mprj_pads.io_out[34] ;
+ wire \mprj_pads.io_out[35] ;
+ wire \mprj_pads.io_out[36] ;
+ wire \mprj_pads.io_out[37] ;
+ wire \mprj_pads.io_out[3] ;
+ wire \mprj_pads.io_out[4] ;
+ wire \mprj_pads.io_out[5] ;
+ wire \mprj_pads.io_out[6] ;
+ wire \mprj_pads.io_out[7] ;
+ wire \mprj_pads.io_out[8] ;
+ wire \mprj_pads.io_out[9] ;
+ wire \mprj_pads.loop1_io[0] ;
+ wire \mprj_pads.loop1_io[10] ;
+ wire \mprj_pads.loop1_io[11] ;
+ wire \mprj_pads.loop1_io[12] ;
+ wire \mprj_pads.loop1_io[13] ;
+ wire \mprj_pads.loop1_io[14] ;
+ wire \mprj_pads.loop1_io[15] ;
+ wire \mprj_pads.loop1_io[16] ;
+ wire \mprj_pads.loop1_io[17] ;
+ wire \mprj_pads.loop1_io[18] ;
+ wire \mprj_pads.loop1_io[19] ;
+ wire \mprj_pads.loop1_io[1] ;
+ wire \mprj_pads.loop1_io[20] ;
+ wire \mprj_pads.loop1_io[21] ;
+ wire \mprj_pads.loop1_io[22] ;
+ wire \mprj_pads.loop1_io[23] ;
+ wire \mprj_pads.loop1_io[24] ;
+ wire \mprj_pads.loop1_io[25] ;
+ wire \mprj_pads.loop1_io[26] ;
+ wire \mprj_pads.loop1_io[27] ;
+ wire \mprj_pads.loop1_io[28] ;
+ wire \mprj_pads.loop1_io[29] ;
+ wire \mprj_pads.loop1_io[2] ;
+ wire \mprj_pads.loop1_io[30] ;
+ wire \mprj_pads.loop1_io[31] ;
+ wire \mprj_pads.loop1_io[32] ;
+ wire \mprj_pads.loop1_io[33] ;
+ wire \mprj_pads.loop1_io[34] ;
+ wire \mprj_pads.loop1_io[35] ;
+ wire \mprj_pads.loop1_io[36] ;
+ wire \mprj_pads.loop1_io[37] ;
+ wire \mprj_pads.loop1_io[3] ;
+ wire \mprj_pads.loop1_io[4] ;
+ wire \mprj_pads.loop1_io[5] ;
+ wire \mprj_pads.loop1_io[6] ;
+ wire \mprj_pads.loop1_io[7] ;
+ wire \mprj_pads.loop1_io[8] ;
+ wire \mprj_pads.loop1_io[9] ;
+ wire \mprj_pads.no_connect_1a[0] ;
+ wire \mprj_pads.no_connect_1a[1] ;
+ wire \mprj_pads.no_connect_1a[2] ;
+ wire \mprj_pads.no_connect_1a[3] ;
+ wire \mprj_pads.no_connect_1a[4] ;
+ wire \mprj_pads.no_connect_1a[5] ;
+ wire \mprj_pads.no_connect_1a[6] ;
+ wire \mprj_pads.no_connect_1b[0] ;
+ wire \mprj_pads.no_connect_1b[1] ;
+ wire \mprj_pads.no_connect_1b[2] ;
+ wire \mprj_pads.no_connect_1b[3] ;
+ wire \mprj_pads.no_connect_1b[4] ;
+ wire \mprj_pads.no_connect_1b[5] ;
+ wire \mprj_pads.no_connect_1b[6] ;
+ wire \mprj_pads.no_connect_2a[0] ;
+ wire \mprj_pads.no_connect_2a[1] ;
+ wire \mprj_pads.no_connect_2b[0] ;
+ wire \mprj_pads.no_connect_2b[1] ;
+ wire \mprj_pads.oeb[0] ;
+ wire \mprj_pads.oeb[10] ;
+ wire \mprj_pads.oeb[11] ;
+ wire \mprj_pads.oeb[12] ;
+ wire \mprj_pads.oeb[13] ;
+ wire \mprj_pads.oeb[14] ;
+ wire \mprj_pads.oeb[15] ;
+ wire \mprj_pads.oeb[16] ;
+ wire \mprj_pads.oeb[17] ;
+ wire \mprj_pads.oeb[18] ;
+ wire \mprj_pads.oeb[19] ;
+ wire \mprj_pads.oeb[1] ;
+ wire \mprj_pads.oeb[20] ;
+ wire \mprj_pads.oeb[21] ;
+ wire \mprj_pads.oeb[22] ;
+ wire \mprj_pads.oeb[23] ;
+ wire \mprj_pads.oeb[24] ;
+ wire \mprj_pads.oeb[25] ;
+ wire \mprj_pads.oeb[26] ;
+ wire \mprj_pads.oeb[27] ;
+ wire \mprj_pads.oeb[28] ;
+ wire \mprj_pads.oeb[29] ;
+ wire \mprj_pads.oeb[2] ;
+ wire \mprj_pads.oeb[30] ;
+ wire \mprj_pads.oeb[31] ;
+ wire \mprj_pads.oeb[32] ;
+ wire \mprj_pads.oeb[33] ;
+ wire \mprj_pads.oeb[34] ;
+ wire \mprj_pads.oeb[35] ;
+ wire \mprj_pads.oeb[36] ;
+ wire \mprj_pads.oeb[37] ;
+ wire \mprj_pads.oeb[3] ;
+ wire \mprj_pads.oeb[4] ;
+ wire \mprj_pads.oeb[5] ;
+ wire \mprj_pads.oeb[6] ;
+ wire \mprj_pads.oeb[7] ;
+ wire \mprj_pads.oeb[8] ;
+ wire \mprj_pads.oeb[9] ;
+ wire \mprj_pads.porb_h ;
+ wire \mprj_pads.slow_sel[0] ;
+ wire \mprj_pads.slow_sel[10] ;
+ wire \mprj_pads.slow_sel[11] ;
+ wire \mprj_pads.slow_sel[12] ;
+ wire \mprj_pads.slow_sel[13] ;
+ wire \mprj_pads.slow_sel[14] ;
+ wire \mprj_pads.slow_sel[15] ;
+ wire \mprj_pads.slow_sel[16] ;
+ wire \mprj_pads.slow_sel[17] ;
+ wire \mprj_pads.slow_sel[18] ;
+ wire \mprj_pads.slow_sel[19] ;
+ wire \mprj_pads.slow_sel[1] ;
+ wire \mprj_pads.slow_sel[20] ;
+ wire \mprj_pads.slow_sel[21] ;
+ wire \mprj_pads.slow_sel[22] ;
+ wire \mprj_pads.slow_sel[23] ;
+ wire \mprj_pads.slow_sel[24] ;
+ wire \mprj_pads.slow_sel[25] ;
+ wire \mprj_pads.slow_sel[26] ;
+ wire \mprj_pads.slow_sel[27] ;
+ wire \mprj_pads.slow_sel[28] ;
+ wire \mprj_pads.slow_sel[29] ;
+ wire \mprj_pads.slow_sel[2] ;
+ wire \mprj_pads.slow_sel[30] ;
+ wire \mprj_pads.slow_sel[31] ;
+ wire \mprj_pads.slow_sel[32] ;
+ wire \mprj_pads.slow_sel[33] ;
+ wire \mprj_pads.slow_sel[34] ;
+ wire \mprj_pads.slow_sel[35] ;
+ wire \mprj_pads.slow_sel[36] ;
+ wire \mprj_pads.slow_sel[37] ;
+ wire \mprj_pads.slow_sel[3] ;
+ wire \mprj_pads.slow_sel[4] ;
+ wire \mprj_pads.slow_sel[5] ;
+ wire \mprj_pads.slow_sel[6] ;
+ wire \mprj_pads.slow_sel[7] ;
+ wire \mprj_pads.slow_sel[8] ;
+ wire \mprj_pads.slow_sel[9] ;
+ wire \mprj_pads.vccd ;
+ wire \mprj_pads.vdda ;
+ wire \mprj_pads.vdda1 ;
+ wire \mprj_pads.vdda2 ;
+ wire \mprj_pads.vddio ;
+ wire \mprj_pads.vddio_q ;
+ wire \mprj_pads.vssa ;
+ wire \mprj_pads.vssa1 ;
+ wire \mprj_pads.vssa2 ;
+ wire \mprj_pads.vssd ;
+ wire \mprj_pads.vssio ;
+ wire \mprj_pads.vssio_q ;
+ wire \mprj_pads.vtrip_sel[0] ;
+ wire \mprj_pads.vtrip_sel[10] ;
+ wire \mprj_pads.vtrip_sel[11] ;
+ wire \mprj_pads.vtrip_sel[12] ;
+ wire \mprj_pads.vtrip_sel[13] ;
+ wire \mprj_pads.vtrip_sel[14] ;
+ wire \mprj_pads.vtrip_sel[15] ;
+ wire \mprj_pads.vtrip_sel[16] ;
+ wire \mprj_pads.vtrip_sel[17] ;
+ wire \mprj_pads.vtrip_sel[18] ;
+ wire \mprj_pads.vtrip_sel[19] ;
+ wire \mprj_pads.vtrip_sel[1] ;
+ wire \mprj_pads.vtrip_sel[20] ;
+ wire \mprj_pads.vtrip_sel[21] ;
+ wire \mprj_pads.vtrip_sel[22] ;
+ wire \mprj_pads.vtrip_sel[23] ;
+ wire \mprj_pads.vtrip_sel[24] ;
+ wire \mprj_pads.vtrip_sel[25] ;
+ wire \mprj_pads.vtrip_sel[26] ;
+ wire \mprj_pads.vtrip_sel[27] ;
+ wire \mprj_pads.vtrip_sel[28] ;
+ wire \mprj_pads.vtrip_sel[29] ;
+ wire \mprj_pads.vtrip_sel[2] ;
+ wire \mprj_pads.vtrip_sel[30] ;
+ wire \mprj_pads.vtrip_sel[31] ;
+ wire \mprj_pads.vtrip_sel[32] ;
+ wire \mprj_pads.vtrip_sel[33] ;
+ wire \mprj_pads.vtrip_sel[34] ;
+ wire \mprj_pads.vtrip_sel[35] ;
+ wire \mprj_pads.vtrip_sel[36] ;
+ wire \mprj_pads.vtrip_sel[37] ;
+ wire \mprj_pads.vtrip_sel[3] ;
+ wire \mprj_pads.vtrip_sel[4] ;
+ wire \mprj_pads.vtrip_sel[5] ;
+ wire \mprj_pads.vtrip_sel[6] ;
+ wire \mprj_pads.vtrip_sel[7] ;
+ wire \mprj_pads.vtrip_sel[8] ;
+ wire \mprj_pads.vtrip_sel[9] ;
+ input por;
+ input porb_h;
+ input resetb;
+ output resetb_core_h;
+ inout vccd;
+ inout vccd1;
+ inout vccd1_pad;
+ inout vccd2;
+ inout vccd2_pad;
+ inout vccd_pad;
+ inout vdda;
+ inout vdda1;
+ inout vdda1_pad;
+ inout vdda1_pad2;
+ inout vdda2;
+ inout vdda2_pad;
+ inout vdda_pad;
+ inout vddio;
+ inout vddio_pad;
+ inout vddio_pad2;
+ wire vddio_q;
+ inout vssa;
+ inout vssa1;
+ inout vssa1_pad;
+ inout vssa1_pad2;
+ inout vssa2;
+ inout vssa2_pad;
+ inout vssa_pad;
+ inout vssd;
+ inout vssd1;
+ inout vssd1_pad;
+ inout vssd2;
+ inout vssd2_pad;
+ inout vssd_pad;
+ inout vssio;
+ inout vssio_pad;
+ inout vssio_pad2;
+ wire vssio_q;
+ wire xresloop;
+ sky130_ef_io__gpiov2_pad_wrapped clock_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vssd, vssd, vccd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_clock),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(clock_core),
+ .INP_DIS(por),
+ .IN_H(),
+ .OE_N(vccd),
+ .OUT(vssd),
+ .PAD(clock),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_clock),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_clk_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_clk),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(loop_flash_clk),
+ .IN_H(),
+ .OE_N(flash_clk_oeb_core),
+ .OUT(flash_clk_core),
+ .PAD(flash_clk),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_clk),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_csb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_csb),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(loop_flash_csb),
+ .IN_H(),
+ .OE_N(flash_csb_oeb_core),
+ .OUT(flash_csb_core),
+ .PAD(flash_csb),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_csb),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io0_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io0),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io0_di_core),
+ .INP_DIS(flash_io0_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io0_oeb_core),
+ .OUT(flash_io0_do_core),
+ .PAD(flash_io0),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io0),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io1_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io1),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io1_di_core),
+ .INP_DIS(flash_io1_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io1_oeb_core),
+ .OUT(flash_io1_do_core),
+ .PAD(flash_io1),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io1),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped gpio_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ gpio_mode1_core, gpio_mode1_core, gpio_mode0_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_gpio),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(gpio_in_core),
+ .INP_DIS(gpio_inenb_core),
+ .IN_H(),
+ .OE_N(gpio_outenb_core),
+ .OUT(gpio_out_core),
+ .PAD(gpio),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_gpio),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD_PAD(vccd_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDA_PAD(vdda_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_PAD(vddio_pad),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_PAD(vddio_pad2),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSA_PAD(vssa_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSD_PAD(vssd_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_PAD(vssio_pad),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_PAD(vssio_pad2),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[0]),
+ .ANALOG_POL(mprj_io_analog_pol[0]),
+ .ANALOG_SEL(mprj_io_analog_sel[0]),
+ .DM(mprj_io_dm[2:0]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[0] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[0]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[0]),
+ .IN(\mprj_pads.io_in[0] ),
+ .INP_DIS(mprj_io_inp_dis[0]),
+ .IN_H(\mprj_pads.io_in_3v3[0] ),
+ .OE_N(mprj_io_oeb[0]),
+ .OUT(mprj_io_out[0]),
+ .PAD(mprj_io[0]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[0] ),
+ .SLOW(mprj_io_slow_sel[0]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[0] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[0])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[10]),
+ .ANALOG_POL(mprj_io_analog_pol[10]),
+ .ANALOG_SEL(mprj_io_analog_sel[10]),
+ .DM(mprj_io_dm[32:30]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[10] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[10]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[10]),
+ .IN(\mprj_pads.io_in[10] ),
+ .INP_DIS(mprj_io_inp_dis[10]),
+ .IN_H(\mprj_pads.io_in_3v3[10] ),
+ .OE_N(mprj_io_oeb[10]),
+ .OUT(mprj_io_out[10]),
+ .PAD(mprj_io[10]),
+ .PAD_A_ESD_0_H(mprj_analog_io[3]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[3] ),
+ .SLOW(mprj_io_slow_sel[10]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[10] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[10])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[11]),
+ .ANALOG_POL(mprj_io_analog_pol[11]),
+ .ANALOG_SEL(mprj_io_analog_sel[11]),
+ .DM(mprj_io_dm[35:33]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[11] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[11]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[11]),
+ .IN(\mprj_pads.io_in[11] ),
+ .INP_DIS(mprj_io_inp_dis[11]),
+ .IN_H(\mprj_pads.io_in_3v3[11] ),
+ .OE_N(mprj_io_oeb[11]),
+ .OUT(mprj_io_out[11]),
+ .PAD(mprj_io[11]),
+ .PAD_A_ESD_0_H(mprj_analog_io[4]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[4] ),
+ .SLOW(mprj_io_slow_sel[11]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[11] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[11])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[12]),
+ .ANALOG_POL(mprj_io_analog_pol[12]),
+ .ANALOG_SEL(mprj_io_analog_sel[12]),
+ .DM(mprj_io_dm[38:36]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[12] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[12]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[12]),
+ .IN(\mprj_pads.io_in[12] ),
+ .INP_DIS(mprj_io_inp_dis[12]),
+ .IN_H(\mprj_pads.io_in_3v3[12] ),
+ .OE_N(mprj_io_oeb[12]),
+ .OUT(mprj_io_out[12]),
+ .PAD(mprj_io[12]),
+ .PAD_A_ESD_0_H(mprj_analog_io[5]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[5] ),
+ .SLOW(mprj_io_slow_sel[12]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[12] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[12])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[13]),
+ .ANALOG_POL(mprj_io_analog_pol[13]),
+ .ANALOG_SEL(mprj_io_analog_sel[13]),
+ .DM(mprj_io_dm[41:39]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[13] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[13]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[13]),
+ .IN(\mprj_pads.io_in[13] ),
+ .INP_DIS(mprj_io_inp_dis[13]),
+ .IN_H(\mprj_pads.io_in_3v3[13] ),
+ .OE_N(mprj_io_oeb[13]),
+ .OUT(mprj_io_out[13]),
+ .PAD(mprj_io[13]),
+ .PAD_A_ESD_0_H(mprj_analog_io[6]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[6] ),
+ .SLOW(mprj_io_slow_sel[13]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[13] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[13])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[14]),
+ .ANALOG_POL(mprj_io_analog_pol[14]),
+ .ANALOG_SEL(mprj_io_analog_sel[14]),
+ .DM(mprj_io_dm[44:42]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[14] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[14]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[14]),
+ .IN(\mprj_pads.io_in[14] ),
+ .INP_DIS(mprj_io_inp_dis[14]),
+ .IN_H(\mprj_pads.io_in_3v3[14] ),
+ .OE_N(mprj_io_oeb[14]),
+ .OUT(mprj_io_out[14]),
+ .PAD(mprj_io[14]),
+ .PAD_A_ESD_0_H(mprj_analog_io[7]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[7] ),
+ .SLOW(mprj_io_slow_sel[14]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[14] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[14])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[15]),
+ .ANALOG_POL(mprj_io_analog_pol[15]),
+ .ANALOG_SEL(mprj_io_analog_sel[15]),
+ .DM(mprj_io_dm[47:45]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[15] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[15]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[15]),
+ .IN(\mprj_pads.io_in[15] ),
+ .INP_DIS(mprj_io_inp_dis[15]),
+ .IN_H(\mprj_pads.io_in_3v3[15] ),
+ .OE_N(mprj_io_oeb[15]),
+ .OUT(mprj_io_out[15]),
+ .PAD(mprj_io[15]),
+ .PAD_A_ESD_0_H(mprj_analog_io[8]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[8] ),
+ .SLOW(mprj_io_slow_sel[15]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[15] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[15])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[16]),
+ .ANALOG_POL(mprj_io_analog_pol[16]),
+ .ANALOG_SEL(mprj_io_analog_sel[16]),
+ .DM(mprj_io_dm[50:48]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[16] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[16]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[16]),
+ .IN(\mprj_pads.io_in[16] ),
+ .INP_DIS(mprj_io_inp_dis[16]),
+ .IN_H(\mprj_pads.io_in_3v3[16] ),
+ .OE_N(mprj_io_oeb[16]),
+ .OUT(mprj_io_out[16]),
+ .PAD(mprj_io[16]),
+ .PAD_A_ESD_0_H(mprj_analog_io[9]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[9] ),
+ .SLOW(mprj_io_slow_sel[16]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[16] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[16])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[17]),
+ .ANALOG_POL(mprj_io_analog_pol[17]),
+ .ANALOG_SEL(mprj_io_analog_sel[17]),
+ .DM(mprj_io_dm[53:51]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[17] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[17]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[17]),
+ .IN(\mprj_pads.io_in[17] ),
+ .INP_DIS(mprj_io_inp_dis[17]),
+ .IN_H(\mprj_pads.io_in_3v3[17] ),
+ .OE_N(mprj_io_oeb[17]),
+ .OUT(mprj_io_out[17]),
+ .PAD(mprj_io[17]),
+ .PAD_A_ESD_0_H(mprj_analog_io[10]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[10] ),
+ .SLOW(mprj_io_slow_sel[17]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[17] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[17])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[18] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[18]),
+ .ANALOG_POL(mprj_io_analog_pol[18]),
+ .ANALOG_SEL(mprj_io_analog_sel[18]),
+ .DM(mprj_io_dm[56:54]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[18] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[18]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[18]),
+ .IN(\mprj_pads.io_in[18] ),
+ .INP_DIS(mprj_io_inp_dis[18]),
+ .IN_H(\mprj_pads.io_in_3v3[18] ),
+ .OE_N(mprj_io_oeb[18]),
+ .OUT(mprj_io_out[18]),
+ .PAD(mprj_io[18]),
+ .PAD_A_ESD_0_H(mprj_analog_io[11]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[11] ),
+ .SLOW(mprj_io_slow_sel[18]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[18] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[18])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[1]),
+ .ANALOG_POL(mprj_io_analog_pol[1]),
+ .ANALOG_SEL(mprj_io_analog_sel[1]),
+ .DM(mprj_io_dm[5:3]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[1] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[1]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[1]),
+ .IN(\mprj_pads.io_in[1] ),
+ .INP_DIS(mprj_io_inp_dis[1]),
+ .IN_H(\mprj_pads.io_in_3v3[1] ),
+ .OE_N(mprj_io_oeb[1]),
+ .OUT(mprj_io_out[1]),
+ .PAD(mprj_io[1]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[1] ),
+ .SLOW(mprj_io_slow_sel[1]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[1] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[1])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[2]),
+ .ANALOG_POL(mprj_io_analog_pol[2]),
+ .ANALOG_SEL(mprj_io_analog_sel[2]),
+ .DM(mprj_io_dm[8:6]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[2] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[2]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[2]),
+ .IN(\mprj_pads.io_in[2] ),
+ .INP_DIS(mprj_io_inp_dis[2]),
+ .IN_H(\mprj_pads.io_in_3v3[2] ),
+ .OE_N(mprj_io_oeb[2]),
+ .OUT(mprj_io_out[2]),
+ .PAD(mprj_io[2]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[2] ),
+ .SLOW(mprj_io_slow_sel[2]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[2] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[2])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[3]),
+ .ANALOG_POL(mprj_io_analog_pol[3]),
+ .ANALOG_SEL(mprj_io_analog_sel[3]),
+ .DM(mprj_io_dm[11:9]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[3] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[3]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[3]),
+ .IN(\mprj_pads.io_in[3] ),
+ .INP_DIS(mprj_io_inp_dis[3]),
+ .IN_H(\mprj_pads.io_in_3v3[3] ),
+ .OE_N(mprj_io_oeb[3]),
+ .OUT(mprj_io_out[3]),
+ .PAD(mprj_io[3]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[3] ),
+ .SLOW(mprj_io_slow_sel[3]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[3] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[3])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[4]),
+ .ANALOG_POL(mprj_io_analog_pol[4]),
+ .ANALOG_SEL(mprj_io_analog_sel[4]),
+ .DM(mprj_io_dm[14:12]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[4] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[4]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[4]),
+ .IN(\mprj_pads.io_in[4] ),
+ .INP_DIS(mprj_io_inp_dis[4]),
+ .IN_H(\mprj_pads.io_in_3v3[4] ),
+ .OE_N(mprj_io_oeb[4]),
+ .OUT(mprj_io_out[4]),
+ .PAD(mprj_io[4]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[4] ),
+ .SLOW(mprj_io_slow_sel[4]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[4] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[4])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[5]),
+ .ANALOG_POL(mprj_io_analog_pol[5]),
+ .ANALOG_SEL(mprj_io_analog_sel[5]),
+ .DM(mprj_io_dm[17:15]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[5] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[5]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[5]),
+ .IN(\mprj_pads.io_in[5] ),
+ .INP_DIS(mprj_io_inp_dis[5]),
+ .IN_H(\mprj_pads.io_in_3v3[5] ),
+ .OE_N(mprj_io_oeb[5]),
+ .OUT(mprj_io_out[5]),
+ .PAD(mprj_io[5]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[5] ),
+ .SLOW(mprj_io_slow_sel[5]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[5] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[5])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[6]),
+ .ANALOG_POL(mprj_io_analog_pol[6]),
+ .ANALOG_SEL(mprj_io_analog_sel[6]),
+ .DM(mprj_io_dm[20:18]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[6] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[6]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[6]),
+ .IN(\mprj_pads.io_in[6] ),
+ .INP_DIS(mprj_io_inp_dis[6]),
+ .IN_H(\mprj_pads.io_in_3v3[6] ),
+ .OE_N(mprj_io_oeb[6]),
+ .OUT(mprj_io_out[6]),
+ .PAD(mprj_io[6]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[6] ),
+ .SLOW(mprj_io_slow_sel[6]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[6] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[6])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[7]),
+ .ANALOG_POL(mprj_io_analog_pol[7]),
+ .ANALOG_SEL(mprj_io_analog_sel[7]),
+ .DM(mprj_io_dm[23:21]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[7] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[7]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[7]),
+ .IN(\mprj_pads.io_in[7] ),
+ .INP_DIS(mprj_io_inp_dis[7]),
+ .IN_H(\mprj_pads.io_in_3v3[7] ),
+ .OE_N(mprj_io_oeb[7]),
+ .OUT(mprj_io_out[7]),
+ .PAD(mprj_io[7]),
+ .PAD_A_ESD_0_H(mprj_analog_io[0]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[0] ),
+ .SLOW(mprj_io_slow_sel[7]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[7] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[7])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[8]),
+ .ANALOG_POL(mprj_io_analog_pol[8]),
+ .ANALOG_SEL(mprj_io_analog_sel[8]),
+ .DM(mprj_io_dm[26:24]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[8] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[8]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[8]),
+ .IN(\mprj_pads.io_in[8] ),
+ .INP_DIS(mprj_io_inp_dis[8]),
+ .IN_H(\mprj_pads.io_in_3v3[8] ),
+ .OE_N(mprj_io_oeb[8]),
+ .OUT(mprj_io_out[8]),
+ .PAD(mprj_io[8]),
+ .PAD_A_ESD_0_H(mprj_analog_io[1]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[1] ),
+ .SLOW(mprj_io_slow_sel[8]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[8] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[8])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[9]),
+ .ANALOG_POL(mprj_io_analog_pol[9]),
+ .ANALOG_SEL(mprj_io_analog_sel[9]),
+ .DM(mprj_io_dm[29:27]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[9] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[9]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[9]),
+ .IN(\mprj_pads.io_in[9] ),
+ .INP_DIS(mprj_io_inp_dis[9]),
+ .IN_H(\mprj_pads.io_in_3v3[9] ),
+ .OE_N(mprj_io_oeb[9]),
+ .OUT(mprj_io_out[9]),
+ .PAD(mprj_io[9]),
+ .PAD_A_ESD_0_H(mprj_analog_io[2]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[2] ),
+ .SLOW(mprj_io_slow_sel[9]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[9] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[9])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[19]),
+ .ANALOG_POL(mprj_io_analog_pol[19]),
+ .ANALOG_SEL(mprj_io_analog_sel[19]),
+ .DM(mprj_io_dm[59:57]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[19] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[19]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[19]),
+ .IN(\mprj_pads.io_in[19] ),
+ .INP_DIS(mprj_io_inp_dis[19]),
+ .IN_H(\mprj_pads.io_in_3v3[19] ),
+ .OE_N(mprj_io_oeb[19]),
+ .OUT(mprj_io_out[19]),
+ .PAD(mprj_io[19]),
+ .PAD_A_ESD_0_H(mprj_analog_io[12]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[12] ),
+ .SLOW(mprj_io_slow_sel[19]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[19] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[19])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[29]),
+ .ANALOG_POL(mprj_io_analog_pol[29]),
+ .ANALOG_SEL(mprj_io_analog_sel[29]),
+ .DM(mprj_io_dm[89:87]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[29] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[29]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[29]),
+ .IN(\mprj_pads.io_in[29] ),
+ .INP_DIS(mprj_io_inp_dis[29]),
+ .IN_H(\mprj_pads.io_in_3v3[29] ),
+ .OE_N(mprj_io_oeb[29]),
+ .OUT(mprj_io_out[29]),
+ .PAD(mprj_io[29]),
+ .PAD_A_ESD_0_H(mprj_analog_io[22]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[22] ),
+ .SLOW(mprj_io_slow_sel[29]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[29] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[29])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[30]),
+ .ANALOG_POL(mprj_io_analog_pol[30]),
+ .ANALOG_SEL(mprj_io_analog_sel[30]),
+ .DM(mprj_io_dm[92:90]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[30] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[30]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[30]),
+ .IN(\mprj_pads.io_in[30] ),
+ .INP_DIS(mprj_io_inp_dis[30]),
+ .IN_H(\mprj_pads.io_in_3v3[30] ),
+ .OE_N(mprj_io_oeb[30]),
+ .OUT(mprj_io_out[30]),
+ .PAD(mprj_io[30]),
+ .PAD_A_ESD_0_H(mprj_analog_io[23]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[23] ),
+ .SLOW(mprj_io_slow_sel[30]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[30] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[30])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[31]),
+ .ANALOG_POL(mprj_io_analog_pol[31]),
+ .ANALOG_SEL(mprj_io_analog_sel[31]),
+ .DM(mprj_io_dm[95:93]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[31] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[31]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[31]),
+ .IN(\mprj_pads.io_in[31] ),
+ .INP_DIS(mprj_io_inp_dis[31]),
+ .IN_H(\mprj_pads.io_in_3v3[31] ),
+ .OE_N(mprj_io_oeb[31]),
+ .OUT(mprj_io_out[31]),
+ .PAD(mprj_io[31]),
+ .PAD_A_ESD_0_H(mprj_analog_io[24]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[24] ),
+ .SLOW(mprj_io_slow_sel[31]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[31] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[31])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[32]),
+ .ANALOG_POL(mprj_io_analog_pol[32]),
+ .ANALOG_SEL(mprj_io_analog_sel[32]),
+ .DM(mprj_io_dm[98:96]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[32] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[32]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[32]),
+ .IN(\mprj_pads.io_in[32] ),
+ .INP_DIS(mprj_io_inp_dis[32]),
+ .IN_H(\mprj_pads.io_in_3v3[32] ),
+ .OE_N(mprj_io_oeb[32]),
+ .OUT(mprj_io_out[32]),
+ .PAD(mprj_io[32]),
+ .PAD_A_ESD_0_H(mprj_analog_io[25]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[25] ),
+ .SLOW(mprj_io_slow_sel[32]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[32] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[32])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[14] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[33]),
+ .ANALOG_POL(mprj_io_analog_pol[33]),
+ .ANALOG_SEL(mprj_io_analog_sel[33]),
+ .DM(mprj_io_dm[101:99]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[33] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[33]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[33]),
+ .IN(\mprj_pads.io_in[33] ),
+ .INP_DIS(mprj_io_inp_dis[33]),
+ .IN_H(\mprj_pads.io_in_3v3[33] ),
+ .OE_N(mprj_io_oeb[33]),
+ .OUT(mprj_io_out[33]),
+ .PAD(mprj_io[33]),
+ .PAD_A_ESD_0_H(mprj_analog_io[26]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[26] ),
+ .SLOW(mprj_io_slow_sel[33]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[33] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[33])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[15] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[34]),
+ .ANALOG_POL(mprj_io_analog_pol[34]),
+ .ANALOG_SEL(mprj_io_analog_sel[34]),
+ .DM(mprj_io_dm[104:102]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[34] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[34]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[34]),
+ .IN(\mprj_pads.io_in[34] ),
+ .INP_DIS(mprj_io_inp_dis[34]),
+ .IN_H(\mprj_pads.io_in_3v3[34] ),
+ .OE_N(mprj_io_oeb[34]),
+ .OUT(mprj_io_out[34]),
+ .PAD(mprj_io[34]),
+ .PAD_A_ESD_0_H(mprj_analog_io[27]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[27] ),
+ .SLOW(mprj_io_slow_sel[34]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[34] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[34])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[16] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[35]),
+ .ANALOG_POL(mprj_io_analog_pol[35]),
+ .ANALOG_SEL(mprj_io_analog_sel[35]),
+ .DM(mprj_io_dm[107:105]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[35] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[35]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[35]),
+ .IN(\mprj_pads.io_in[35] ),
+ .INP_DIS(mprj_io_inp_dis[35]),
+ .IN_H(\mprj_pads.io_in_3v3[35] ),
+ .OE_N(mprj_io_oeb[35]),
+ .OUT(mprj_io_out[35]),
+ .PAD(mprj_io[35]),
+ .PAD_A_ESD_0_H(mprj_analog_io[28]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[28] ),
+ .SLOW(mprj_io_slow_sel[35]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[35] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[35])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[17] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[36]),
+ .ANALOG_POL(mprj_io_analog_pol[36]),
+ .ANALOG_SEL(mprj_io_analog_sel[36]),
+ .DM(mprj_io_dm[110:108]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[36] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[36]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[36]),
+ .IN(\mprj_pads.io_in[36] ),
+ .INP_DIS(mprj_io_inp_dis[36]),
+ .IN_H(\mprj_pads.io_in_3v3[36] ),
+ .OE_N(mprj_io_oeb[36]),
+ .OUT(mprj_io_out[36]),
+ .PAD(mprj_io[36]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_2b[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_2a[0] ),
+ .SLOW(mprj_io_slow_sel[36]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[36] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[36])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[18] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[37]),
+ .ANALOG_POL(mprj_io_analog_pol[37]),
+ .ANALOG_SEL(mprj_io_analog_sel[37]),
+ .DM(mprj_io_dm[113:111]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[37] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[37]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[37]),
+ .IN(\mprj_pads.io_in[37] ),
+ .INP_DIS(mprj_io_inp_dis[37]),
+ .IN_H(\mprj_pads.io_in_3v3[37] ),
+ .OE_N(mprj_io_oeb[37]),
+ .OUT(mprj_io_out[37]),
+ .PAD(mprj_io[37]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_2b[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_2a[1] ),
+ .SLOW(mprj_io_slow_sel[37]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[37] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[37])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[20]),
+ .ANALOG_POL(mprj_io_analog_pol[20]),
+ .ANALOG_SEL(mprj_io_analog_sel[20]),
+ .DM(mprj_io_dm[62:60]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[20] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[20]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[20]),
+ .IN(\mprj_pads.io_in[20] ),
+ .INP_DIS(mprj_io_inp_dis[20]),
+ .IN_H(\mprj_pads.io_in_3v3[20] ),
+ .OE_N(mprj_io_oeb[20]),
+ .OUT(mprj_io_out[20]),
+ .PAD(mprj_io[20]),
+ .PAD_A_ESD_0_H(mprj_analog_io[13]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[13] ),
+ .SLOW(mprj_io_slow_sel[20]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[20] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[20])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[21]),
+ .ANALOG_POL(mprj_io_analog_pol[21]),
+ .ANALOG_SEL(mprj_io_analog_sel[21]),
+ .DM(mprj_io_dm[65:63]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[21] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[21]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[21]),
+ .IN(\mprj_pads.io_in[21] ),
+ .INP_DIS(mprj_io_inp_dis[21]),
+ .IN_H(\mprj_pads.io_in_3v3[21] ),
+ .OE_N(mprj_io_oeb[21]),
+ .OUT(mprj_io_out[21]),
+ .PAD(mprj_io[21]),
+ .PAD_A_ESD_0_H(mprj_analog_io[14]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[14] ),
+ .SLOW(mprj_io_slow_sel[21]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[21] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[21])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[22]),
+ .ANALOG_POL(mprj_io_analog_pol[22]),
+ .ANALOG_SEL(mprj_io_analog_sel[22]),
+ .DM(mprj_io_dm[68:66]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[22] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[22]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[22]),
+ .IN(\mprj_pads.io_in[22] ),
+ .INP_DIS(mprj_io_inp_dis[22]),
+ .IN_H(\mprj_pads.io_in_3v3[22] ),
+ .OE_N(mprj_io_oeb[22]),
+ .OUT(mprj_io_out[22]),
+ .PAD(mprj_io[22]),
+ .PAD_A_ESD_0_H(mprj_analog_io[15]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[15] ),
+ .SLOW(mprj_io_slow_sel[22]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[22] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[22])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[23]),
+ .ANALOG_POL(mprj_io_analog_pol[23]),
+ .ANALOG_SEL(mprj_io_analog_sel[23]),
+ .DM(mprj_io_dm[71:69]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[23] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[23]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[23]),
+ .IN(\mprj_pads.io_in[23] ),
+ .INP_DIS(mprj_io_inp_dis[23]),
+ .IN_H(\mprj_pads.io_in_3v3[23] ),
+ .OE_N(mprj_io_oeb[23]),
+ .OUT(mprj_io_out[23]),
+ .PAD(mprj_io[23]),
+ .PAD_A_ESD_0_H(mprj_analog_io[16]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[16] ),
+ .SLOW(mprj_io_slow_sel[23]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[23] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[23])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[24]),
+ .ANALOG_POL(mprj_io_analog_pol[24]),
+ .ANALOG_SEL(mprj_io_analog_sel[24]),
+ .DM(mprj_io_dm[74:72]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[24] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[24]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[24]),
+ .IN(\mprj_pads.io_in[24] ),
+ .INP_DIS(mprj_io_inp_dis[24]),
+ .IN_H(\mprj_pads.io_in_3v3[24] ),
+ .OE_N(mprj_io_oeb[24]),
+ .OUT(mprj_io_out[24]),
+ .PAD(mprj_io[24]),
+ .PAD_A_ESD_0_H(mprj_analog_io[17]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[17] ),
+ .SLOW(mprj_io_slow_sel[24]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[24] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[24])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[25]),
+ .ANALOG_POL(mprj_io_analog_pol[25]),
+ .ANALOG_SEL(mprj_io_analog_sel[25]),
+ .DM(mprj_io_dm[77:75]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[25] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[25]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[25]),
+ .IN(\mprj_pads.io_in[25] ),
+ .INP_DIS(mprj_io_inp_dis[25]),
+ .IN_H(\mprj_pads.io_in_3v3[25] ),
+ .OE_N(mprj_io_oeb[25]),
+ .OUT(mprj_io_out[25]),
+ .PAD(mprj_io[25]),
+ .PAD_A_ESD_0_H(mprj_analog_io[18]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[18] ),
+ .SLOW(mprj_io_slow_sel[25]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[25] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[25])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[26]),
+ .ANALOG_POL(mprj_io_analog_pol[26]),
+ .ANALOG_SEL(mprj_io_analog_sel[26]),
+ .DM(mprj_io_dm[80:78]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[26] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[26]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[26]),
+ .IN(\mprj_pads.io_in[26] ),
+ .INP_DIS(mprj_io_inp_dis[26]),
+ .IN_H(\mprj_pads.io_in_3v3[26] ),
+ .OE_N(mprj_io_oeb[26]),
+ .OUT(mprj_io_out[26]),
+ .PAD(mprj_io[26]),
+ .PAD_A_ESD_0_H(mprj_analog_io[19]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[19] ),
+ .SLOW(mprj_io_slow_sel[26]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[26] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[26])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[27]),
+ .ANALOG_POL(mprj_io_analog_pol[27]),
+ .ANALOG_SEL(mprj_io_analog_sel[27]),
+ .DM(mprj_io_dm[83:81]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[27] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[27]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[27]),
+ .IN(\mprj_pads.io_in[27] ),
+ .INP_DIS(mprj_io_inp_dis[27]),
+ .IN_H(\mprj_pads.io_in_3v3[27] ),
+ .OE_N(mprj_io_oeb[27]),
+ .OUT(mprj_io_out[27]),
+ .PAD(mprj_io[27]),
+ .PAD_A_ESD_0_H(mprj_analog_io[20]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[20] ),
+ .SLOW(mprj_io_slow_sel[27]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[27] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[27])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[28]),
+ .ANALOG_POL(mprj_io_analog_pol[28]),
+ .ANALOG_SEL(mprj_io_analog_sel[28]),
+ .DM(mprj_io_dm[86:84]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[28] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[28]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[28]),
+ .IN(\mprj_pads.io_in[28] ),
+ .INP_DIS(mprj_io_inp_dis[28]),
+ .IN_H(\mprj_pads.io_in_3v3[28] ),
+ .OE_N(mprj_io_oeb[28]),
+ .OUT(mprj_io_out[28]),
+ .PAD(mprj_io[28]),
+ .PAD_A_ESD_0_H(mprj_analog_io[21]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.analog_noesd_io[21] ),
+ .SLOW(mprj_io_slow_sel[28]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[28] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[28])
+ );
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DISABLE_PULLUP_H(vssio),
+ .ENABLE_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .EN_VDDIO_SIG_H(vssio),
+ .FILT_IN_H(vssio),
+ .INP_SEL_H(vssio),
+ .PAD(resetb),
+ .PAD_A_ESD_H(xresloop),
+ .PULLUP_H(vssio),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .TIE_WEAK_HI_H(xresloop),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .XRES_H_N(resetb_core_h)
+ );
+ sky130_ef_io__corner_pad user1_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd1),
+ .VCCD_PAD(vccd1_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSD1(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDA_PAD(vdda1_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDA_PAD(vdda1_pad2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSA_PAD(vssa1_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSA_PAD(vssa1_pad2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSD1(vssd1),
+ .VSSD_PAD(vssd1_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad user2_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd2),
+ .VCCD_PAD(vccd2_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSD1(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDA_PAD(vdda2_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSA_PAD(vssa2_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSD1(vssd2),
+ .VSSD_PAD(vssd2_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ assign \mprj_io_enh[9] = porb_h;
+ assign \mprj_io_enh[8] = porb_h;
+ assign \mprj_io_enh[7] = porb_h;
+ assign \mprj_io_enh[6] = porb_h;
+ assign \mprj_io_enh[5] = porb_h;
+ assign \mprj_io_enh[4] = porb_h;
+ assign \mprj_io_enh[3] = porb_h;
+ assign \mprj_io_enh[2] = porb_h;
+ assign \mprj_io_enh[1] = porb_h;
+ assign \mprj_io_enh[0] = porb_h;
+ assign \mprj_pads.enh[37] = porb_h;
+ assign \mprj_pads.enh[36] = porb_h;
+ assign \mprj_pads.enh[35] = porb_h;
+ assign \mprj_pads.enh[34] = porb_h;
+ assign \mprj_pads.enh[33] = porb_h;
+ assign \mprj_pads.enh[32] = porb_h;
+ assign \mprj_pads.enh[31] = porb_h;
+ assign \mprj_pads.enh[30] = porb_h;
+ assign \mprj_pads.enh[29] = porb_h;
+ assign \mprj_pads.enh[28] = porb_h;
+ assign \mprj_pads.enh[27] = porb_h;
+ assign \mprj_pads.enh[26] = porb_h;
+ assign \mprj_pads.enh[25] = porb_h;
+ assign \mprj_pads.enh[24] = porb_h;
+ assign \mprj_pads.enh[23] = porb_h;
+ assign \mprj_pads.enh[22] = porb_h;
+ assign \mprj_pads.enh[21] = porb_h;
+ assign \mprj_pads.enh[20] = porb_h;
+ assign \mprj_pads.enh[19] = porb_h;
+ assign \mprj_pads.enh[18] = porb_h;
+ assign \mprj_pads.enh[17] = porb_h;
+ assign \mprj_pads.enh[16] = porb_h;
+ assign \mprj_pads.enh[15] = porb_h;
+ assign \mprj_pads.enh[14] = porb_h;
+ assign \mprj_pads.enh[13] = porb_h;
+ assign \mprj_pads.enh[12] = porb_h;
+ assign \mprj_pads.enh[11] = porb_h;
+ assign \mprj_pads.enh[10] = porb_h;
+ assign \mprj_pads.enh[9] = porb_h;
+ assign \mprj_pads.enh[8] = porb_h;
+ assign \mprj_pads.enh[7] = porb_h;
+ assign \mprj_pads.enh[6] = porb_h;
+ assign \mprj_pads.enh[5] = porb_h;
+ assign \mprj_pads.enh[4] = porb_h;
+ assign \mprj_pads.enh[3] = porb_h;
+ assign \mprj_pads.enh[2] = porb_h;
+ assign \mprj_pads.enh[1] = porb_h;
+ assign \mprj_pads.enh[0] = porb_h;
+ assign \mprj_pads.holdover[37] = mprj_io_holdover[37];
+ assign \mprj_pads.holdover[36] = mprj_io_holdover[36];
+ assign \mprj_pads.holdover[35] = mprj_io_holdover[35];
+ assign \mprj_pads.holdover[34] = mprj_io_holdover[34];
+ assign \mprj_pads.holdover[33] = mprj_io_holdover[33];
+ assign \mprj_pads.holdover[32] = mprj_io_holdover[32];
+ assign \mprj_pads.holdover[31] = mprj_io_holdover[31];
+ assign \mprj_pads.holdover[30] = mprj_io_holdover[30];
+ assign \mprj_pads.holdover[29] = mprj_io_holdover[29];
+ assign \mprj_pads.holdover[28] = mprj_io_holdover[28];
+ assign \mprj_pads.holdover[27] = mprj_io_holdover[27];
+ assign \mprj_pads.holdover[26] = mprj_io_holdover[26];
+ assign \mprj_pads.holdover[25] = mprj_io_holdover[25];
+ assign \mprj_pads.holdover[24] = mprj_io_holdover[24];
+ assign \mprj_pads.holdover[23] = mprj_io_holdover[23];
+ assign \mprj_pads.holdover[22] = mprj_io_holdover[22];
+ assign \mprj_pads.holdover[21] = mprj_io_holdover[21];
+ assign \mprj_pads.holdover[20] = mprj_io_holdover[20];
+ assign \mprj_pads.holdover[19] = mprj_io_holdover[19];
+ assign \mprj_pads.holdover[18] = mprj_io_holdover[18];
+ assign \mprj_pads.holdover[17] = mprj_io_holdover[17];
+ assign \mprj_pads.holdover[16] = mprj_io_holdover[16];
+ assign \mprj_pads.holdover[15] = mprj_io_holdover[15];
+ assign \mprj_pads.holdover[14] = mprj_io_holdover[14];
+ assign \mprj_pads.holdover[13] = mprj_io_holdover[13];
+ assign \mprj_pads.holdover[12] = mprj_io_holdover[12];
+ assign \mprj_pads.holdover[11] = mprj_io_holdover[11];
+ assign \mprj_pads.holdover[10] = mprj_io_holdover[10];
+ assign \mprj_pads.holdover[9] = mprj_io_holdover[9];
+ assign \mprj_pads.holdover[8] = mprj_io_holdover[8];
+ assign \mprj_pads.holdover[7] = mprj_io_holdover[7];
+ assign \mprj_pads.holdover[6] = mprj_io_holdover[6];
+ assign \mprj_pads.holdover[5] = mprj_io_holdover[5];
+ assign \mprj_pads.holdover[4] = mprj_io_holdover[4];
+ assign \mprj_pads.holdover[3] = mprj_io_holdover[3];
+ assign \mprj_pads.holdover[2] = mprj_io_holdover[2];
+ assign \mprj_pads.holdover[1] = mprj_io_holdover[1];
+ assign \mprj_pads.holdover[0] = mprj_io_holdover[0];
+ assign \mprj_pads.io_out[37] = mprj_io_out[37];
+ assign \mprj_pads.io_out[36] = mprj_io_out[36];
+ assign \mprj_pads.io_out[35] = mprj_io_out[35];
+ assign \mprj_pads.io_out[34] = mprj_io_out[34];
+ assign \mprj_pads.io_out[33] = mprj_io_out[33];
+ assign \mprj_pads.io_out[32] = mprj_io_out[32];
+ assign \mprj_pads.io_out[31] = mprj_io_out[31];
+ assign \mprj_pads.io_out[30] = mprj_io_out[30];
+ assign \mprj_pads.io_out[29] = mprj_io_out[29];
+ assign \mprj_pads.io_out[28] = mprj_io_out[28];
+ assign \mprj_pads.io_out[27] = mprj_io_out[27];
+ assign \mprj_pads.io_out[26] = mprj_io_out[26];
+ assign \mprj_pads.io_out[25] = mprj_io_out[25];
+ assign \mprj_pads.io_out[24] = mprj_io_out[24];
+ assign \mprj_pads.io_out[23] = mprj_io_out[23];
+ assign \mprj_pads.io_out[22] = mprj_io_out[22];
+ assign \mprj_pads.io_out[21] = mprj_io_out[21];
+ assign \mprj_pads.io_out[20] = mprj_io_out[20];
+ assign \mprj_pads.io_out[19] = mprj_io_out[19];
+ assign \mprj_pads.io_out[18] = mprj_io_out[18];
+ assign \mprj_pads.io_out[17] = mprj_io_out[17];
+ assign \mprj_pads.io_out[16] = mprj_io_out[16];
+ assign \mprj_pads.io_out[15] = mprj_io_out[15];
+ assign \mprj_pads.io_out[14] = mprj_io_out[14];
+ assign \mprj_pads.io_out[13] = mprj_io_out[13];
+ assign \mprj_pads.io_out[12] = mprj_io_out[12];
+ assign \mprj_pads.io_out[11] = mprj_io_out[11];
+ assign \mprj_pads.io_out[10] = mprj_io_out[10];
+ assign \mprj_pads.io_out[9] = mprj_io_out[9];
+ assign \mprj_pads.io_out[8] = mprj_io_out[8];
+ assign \mprj_pads.io_out[7] = mprj_io_out[7];
+ assign \mprj_pads.io_out[6] = mprj_io_out[6];
+ assign \mprj_pads.io_out[5] = mprj_io_out[5];
+ assign \mprj_pads.io_out[4] = mprj_io_out[4];
+ assign \mprj_pads.io_out[3] = mprj_io_out[3];
+ assign \mprj_pads.io_out[2] = mprj_io_out[2];
+ assign \mprj_pads.io_out[1] = mprj_io_out[1];
+ assign \mprj_pads.io_out[0] = mprj_io_out[0];
+ assign \mprj_io_hldh_n[37] = vddio;
+ assign \mprj_io_hldh_n[36] = vddio;
+ assign \mprj_io_hldh_n[35] = vddio;
+ assign \mprj_io_hldh_n[34] = vddio;
+ assign \mprj_io_hldh_n[33] = vddio;
+ assign \mprj_io_hldh_n[32] = vddio;
+ assign \mprj_io_hldh_n[31] = vddio;
+ assign \mprj_io_hldh_n[30] = vddio;
+ assign \mprj_io_hldh_n[29] = vddio;
+ assign \mprj_io_hldh_n[28] = vddio;
+ assign \mprj_io_hldh_n[27] = vddio;
+ assign \mprj_io_hldh_n[26] = vddio;
+ assign \mprj_io_hldh_n[25] = vddio;
+ assign \mprj_io_hldh_n[24] = vddio;
+ assign \mprj_io_hldh_n[23] = vddio;
+ assign \mprj_io_hldh_n[22] = vddio;
+ assign \mprj_io_hldh_n[21] = vddio;
+ assign \mprj_io_hldh_n[20] = vddio;
+ assign \mprj_io_hldh_n[19] = vddio;
+ assign \mprj_io_hldh_n[18] = vddio;
+ assign \mprj_io_hldh_n[17] = vddio;
+ assign \mprj_io_hldh_n[16] = vddio;
+ assign \mprj_io_hldh_n[15] = vddio;
+ assign \mprj_io_hldh_n[14] = vddio;
+ assign \mprj_io_hldh_n[13] = vddio;
+ assign \mprj_io_hldh_n[12] = vddio;
+ assign \mprj_io_hldh_n[11] = vddio;
+ assign \mprj_io_hldh_n[10] = vddio;
+ assign \mprj_io_hldh_n[9] = vddio;
+ assign \mprj_io_hldh_n[8] = vddio;
+ assign \mprj_io_hldh_n[7] = vddio;
+ assign \mprj_io_hldh_n[6] = vddio;
+ assign \mprj_io_hldh_n[5] = vddio;
+ assign \mprj_io_hldh_n[4] = vddio;
+ assign \mprj_io_hldh_n[3] = vddio;
+ assign \mprj_io_hldh_n[2] = vddio;
+ assign \mprj_io_hldh_n[1] = vddio;
+ assign \mprj_io_hldh_n[0] = vddio;
+ assign \mprj_pads.ib_mode_sel[37] = mprj_io_ib_mode_sel[37];
+ assign \mprj_pads.ib_mode_sel[36] = mprj_io_ib_mode_sel[36];
+ assign \mprj_pads.ib_mode_sel[35] = mprj_io_ib_mode_sel[35];
+ assign \mprj_pads.ib_mode_sel[34] = mprj_io_ib_mode_sel[34];
+ assign \mprj_pads.ib_mode_sel[33] = mprj_io_ib_mode_sel[33];
+ assign \mprj_pads.ib_mode_sel[32] = mprj_io_ib_mode_sel[32];
+ assign \mprj_pads.ib_mode_sel[31] = mprj_io_ib_mode_sel[31];
+ assign \mprj_pads.ib_mode_sel[30] = mprj_io_ib_mode_sel[30];
+ assign \mprj_pads.ib_mode_sel[29] = mprj_io_ib_mode_sel[29];
+ assign \mprj_pads.ib_mode_sel[28] = mprj_io_ib_mode_sel[28];
+ assign \mprj_pads.ib_mode_sel[27] = mprj_io_ib_mode_sel[27];
+ assign \mprj_pads.ib_mode_sel[26] = mprj_io_ib_mode_sel[26];
+ assign \mprj_pads.ib_mode_sel[25] = mprj_io_ib_mode_sel[25];
+ assign \mprj_pads.ib_mode_sel[24] = mprj_io_ib_mode_sel[24];
+ assign \mprj_pads.ib_mode_sel[23] = mprj_io_ib_mode_sel[23];
+ assign \mprj_pads.ib_mode_sel[22] = mprj_io_ib_mode_sel[22];
+ assign \mprj_pads.ib_mode_sel[21] = mprj_io_ib_mode_sel[21];
+ assign \mprj_pads.ib_mode_sel[20] = mprj_io_ib_mode_sel[20];
+ assign \mprj_pads.ib_mode_sel[19] = mprj_io_ib_mode_sel[19];
+ assign \mprj_pads.ib_mode_sel[18] = mprj_io_ib_mode_sel[18];
+ assign \mprj_pads.ib_mode_sel[17] = mprj_io_ib_mode_sel[17];
+ assign \mprj_pads.ib_mode_sel[16] = mprj_io_ib_mode_sel[16];
+ assign \mprj_pads.ib_mode_sel[15] = mprj_io_ib_mode_sel[15];
+ assign \mprj_pads.ib_mode_sel[14] = mprj_io_ib_mode_sel[14];
+ assign \mprj_pads.ib_mode_sel[13] = mprj_io_ib_mode_sel[13];
+ assign \mprj_pads.ib_mode_sel[12] = mprj_io_ib_mode_sel[12];
+ assign \mprj_pads.ib_mode_sel[11] = mprj_io_ib_mode_sel[11];
+ assign \mprj_pads.ib_mode_sel[10] = mprj_io_ib_mode_sel[10];
+ assign \mprj_pads.ib_mode_sel[9] = mprj_io_ib_mode_sel[9];
+ assign \mprj_pads.ib_mode_sel[8] = mprj_io_ib_mode_sel[8];
+ assign \mprj_pads.ib_mode_sel[7] = mprj_io_ib_mode_sel[7];
+ assign \mprj_pads.ib_mode_sel[6] = mprj_io_ib_mode_sel[6];
+ assign \mprj_pads.ib_mode_sel[5] = mprj_io_ib_mode_sel[5];
+ assign \mprj_pads.ib_mode_sel[4] = mprj_io_ib_mode_sel[4];
+ assign \mprj_pads.ib_mode_sel[3] = mprj_io_ib_mode_sel[3];
+ assign \mprj_pads.ib_mode_sel[2] = mprj_io_ib_mode_sel[2];
+ assign \mprj_pads.ib_mode_sel[1] = mprj_io_ib_mode_sel[1];
+ assign \mprj_pads.ib_mode_sel[0] = mprj_io_ib_mode_sel[0];
+ assign \mprj_pads.hldh_n[37] = vddio;
+ assign \mprj_pads.hldh_n[36] = vddio;
+ assign \mprj_pads.hldh_n[35] = vddio;
+ assign \mprj_pads.hldh_n[34] = vddio;
+ assign \mprj_pads.hldh_n[33] = vddio;
+ assign \mprj_pads.hldh_n[32] = vddio;
+ assign \mprj_pads.hldh_n[31] = vddio;
+ assign \mprj_pads.hldh_n[30] = vddio;
+ assign \mprj_pads.hldh_n[29] = vddio;
+ assign \mprj_pads.hldh_n[28] = vddio;
+ assign \mprj_pads.hldh_n[27] = vddio;
+ assign \mprj_pads.hldh_n[26] = vddio;
+ assign \mprj_pads.hldh_n[25] = vddio;
+ assign \mprj_pads.hldh_n[24] = vddio;
+ assign \mprj_pads.hldh_n[23] = vddio;
+ assign \mprj_pads.hldh_n[22] = vddio;
+ assign \mprj_pads.hldh_n[21] = vddio;
+ assign \mprj_pads.hldh_n[20] = vddio;
+ assign \mprj_pads.hldh_n[19] = vddio;
+ assign \mprj_pads.hldh_n[18] = vddio;
+ assign \mprj_pads.hldh_n[17] = vddio;
+ assign \mprj_pads.hldh_n[16] = vddio;
+ assign \mprj_pads.hldh_n[15] = vddio;
+ assign \mprj_pads.hldh_n[14] = vddio;
+ assign \mprj_pads.hldh_n[13] = vddio;
+ assign \mprj_pads.hldh_n[12] = vddio;
+ assign \mprj_pads.hldh_n[11] = vddio;
+ assign \mprj_pads.hldh_n[10] = vddio;
+ assign \mprj_pads.hldh_n[9] = vddio;
+ assign \mprj_pads.hldh_n[8] = vddio;
+ assign \mprj_pads.hldh_n[7] = vddio;
+ assign \mprj_pads.hldh_n[6] = vddio;
+ assign \mprj_pads.hldh_n[5] = vddio;
+ assign \mprj_pads.hldh_n[4] = vddio;
+ assign \mprj_pads.hldh_n[3] = vddio;
+ assign \mprj_pads.hldh_n[2] = vddio;
+ assign \mprj_pads.hldh_n[1] = vddio;
+ assign \mprj_pads.hldh_n[0] = vddio;
+ assign \mprj_pads.io[37] = mprj_io[37];
+ assign \mprj_pads.io[36] = mprj_io[36];
+ assign \mprj_pads.io[35] = mprj_io[35];
+ assign \mprj_pads.io[34] = mprj_io[34];
+ assign \mprj_pads.io[33] = mprj_io[33];
+ assign \mprj_pads.io[32] = mprj_io[32];
+ assign \mprj_pads.io[31] = mprj_io[31];
+ assign \mprj_pads.io[30] = mprj_io[30];
+ assign \mprj_pads.io[29] = mprj_io[29];
+ assign \mprj_pads.io[28] = mprj_io[28];
+ assign \mprj_pads.io[27] = mprj_io[27];
+ assign \mprj_pads.io[26] = mprj_io[26];
+ assign \mprj_pads.io[25] = mprj_io[25];
+ assign \mprj_pads.io[24] = mprj_io[24];
+ assign \mprj_pads.io[23] = mprj_io[23];
+ assign \mprj_pads.io[22] = mprj_io[22];
+ assign \mprj_pads.io[21] = mprj_io[21];
+ assign \mprj_pads.io[20] = mprj_io[20];
+ assign \mprj_pads.io[19] = mprj_io[19];
+ assign \mprj_pads.io[18] = mprj_io[18];
+ assign \mprj_pads.io[17] = mprj_io[17];
+ assign \mprj_pads.io[16] = mprj_io[16];
+ assign \mprj_pads.io[15] = mprj_io[15];
+ assign \mprj_pads.io[14] = mprj_io[14];
+ assign \mprj_pads.io[13] = mprj_io[13];
+ assign \mprj_pads.io[12] = mprj_io[12];
+ assign \mprj_pads.io[11] = mprj_io[11];
+ assign \mprj_pads.io[10] = mprj_io[10];
+ assign \mprj_pads.io[9] = mprj_io[9];
+ assign \mprj_pads.io[8] = mprj_io[8];
+ assign \mprj_pads.io[7] = mprj_io[7];
+ assign \mprj_pads.io[6] = mprj_io[6];
+ assign \mprj_pads.io[5] = mprj_io[5];
+ assign \mprj_pads.io[4] = mprj_io[4];
+ assign \mprj_pads.io[3] = mprj_io[3];
+ assign \mprj_pads.io[2] = mprj_io[2];
+ assign \mprj_pads.io[1] = mprj_io[1];
+ assign \mprj_pads.io[0] = mprj_io[0];
+ assign \mprj_pads.dm[113] = mprj_io_dm[113];
+ assign \mprj_pads.dm[112] = mprj_io_dm[112];
+ assign \mprj_pads.dm[111] = mprj_io_dm[111];
+ assign \mprj_pads.dm[110] = mprj_io_dm[110];
+ assign \mprj_pads.dm[109] = mprj_io_dm[109];
+ assign \mprj_pads.dm[108] = mprj_io_dm[108];
+ assign \mprj_pads.dm[107] = mprj_io_dm[107];
+ assign \mprj_pads.dm[106] = mprj_io_dm[106];
+ assign \mprj_pads.dm[105] = mprj_io_dm[105];
+ assign \mprj_pads.dm[104] = mprj_io_dm[104];
+ assign \mprj_pads.dm[103] = mprj_io_dm[103];
+ assign \mprj_pads.dm[102] = mprj_io_dm[102];
+ assign \mprj_pads.dm[101] = mprj_io_dm[101];
+ assign \mprj_pads.dm[100] = mprj_io_dm[100];
+ assign \mprj_pads.dm[99] = mprj_io_dm[99];
+ assign \mprj_pads.dm[98] = mprj_io_dm[98];
+ assign \mprj_pads.dm[97] = mprj_io_dm[97];
+ assign \mprj_pads.dm[96] = mprj_io_dm[96];
+ assign \mprj_pads.dm[95] = mprj_io_dm[95];
+ assign \mprj_pads.dm[94] = mprj_io_dm[94];
+ assign \mprj_pads.dm[93] = mprj_io_dm[93];
+ assign \mprj_pads.dm[92] = mprj_io_dm[92];
+ assign \mprj_pads.dm[91] = mprj_io_dm[91];
+ assign \mprj_pads.dm[90] = mprj_io_dm[90];
+ assign \mprj_pads.dm[89] = mprj_io_dm[89];
+ assign \mprj_pads.dm[88] = mprj_io_dm[88];
+ assign \mprj_pads.dm[87] = mprj_io_dm[87];
+ assign \mprj_pads.dm[86] = mprj_io_dm[86];
+ assign \mprj_pads.dm[85] = mprj_io_dm[85];
+ assign \mprj_pads.dm[84] = mprj_io_dm[84];
+ assign \mprj_pads.dm[83] = mprj_io_dm[83];
+ assign \mprj_pads.dm[82] = mprj_io_dm[82];
+ assign \mprj_pads.dm[81] = mprj_io_dm[81];
+ assign \mprj_pads.dm[80] = mprj_io_dm[80];
+ assign \mprj_pads.dm[79] = mprj_io_dm[79];
+ assign \mprj_pads.dm[78] = mprj_io_dm[78];
+ assign \mprj_pads.dm[77] = mprj_io_dm[77];
+ assign \mprj_pads.dm[76] = mprj_io_dm[76];
+ assign \mprj_pads.dm[75] = mprj_io_dm[75];
+ assign \mprj_pads.dm[74] = mprj_io_dm[74];
+ assign \mprj_pads.dm[73] = mprj_io_dm[73];
+ assign \mprj_pads.dm[72] = mprj_io_dm[72];
+ assign \mprj_pads.dm[71] = mprj_io_dm[71];
+ assign \mprj_pads.dm[70] = mprj_io_dm[70];
+ assign \mprj_pads.dm[69] = mprj_io_dm[69];
+ assign \mprj_pads.dm[68] = mprj_io_dm[68];
+ assign \mprj_pads.dm[67] = mprj_io_dm[67];
+ assign \mprj_pads.dm[66] = mprj_io_dm[66];
+ assign \mprj_pads.dm[65] = mprj_io_dm[65];
+ assign \mprj_pads.dm[64] = mprj_io_dm[64];
+ assign \mprj_pads.dm[63] = mprj_io_dm[63];
+ assign \mprj_pads.dm[62] = mprj_io_dm[62];
+ assign \mprj_pads.dm[61] = mprj_io_dm[61];
+ assign \mprj_pads.dm[60] = mprj_io_dm[60];
+ assign \mprj_pads.dm[59] = mprj_io_dm[59];
+ assign \mprj_pads.dm[58] = mprj_io_dm[58];
+ assign \mprj_pads.dm[57] = mprj_io_dm[57];
+ assign \mprj_pads.dm[56] = mprj_io_dm[56];
+ assign \mprj_pads.dm[55] = mprj_io_dm[55];
+ assign \mprj_pads.dm[54] = mprj_io_dm[54];
+ assign \mprj_pads.dm[53] = mprj_io_dm[53];
+ assign \mprj_pads.dm[52] = mprj_io_dm[52];
+ assign \mprj_pads.dm[51] = mprj_io_dm[51];
+ assign \mprj_pads.dm[50] = mprj_io_dm[50];
+ assign \mprj_pads.dm[49] = mprj_io_dm[49];
+ assign \mprj_pads.dm[48] = mprj_io_dm[48];
+ assign \mprj_pads.dm[47] = mprj_io_dm[47];
+ assign \mprj_pads.dm[46] = mprj_io_dm[46];
+ assign \mprj_pads.dm[45] = mprj_io_dm[45];
+ assign \mprj_pads.dm[44] = mprj_io_dm[44];
+ assign \mprj_pads.dm[43] = mprj_io_dm[43];
+ assign \mprj_pads.dm[42] = mprj_io_dm[42];
+ assign \mprj_pads.dm[41] = mprj_io_dm[41];
+ assign \mprj_pads.dm[40] = mprj_io_dm[40];
+ assign \mprj_pads.dm[39] = mprj_io_dm[39];
+ assign \mprj_pads.dm[38] = mprj_io_dm[38];
+ assign \mprj_pads.dm[37] = mprj_io_dm[37];
+ assign \mprj_pads.dm[36] = mprj_io_dm[36];
+ assign \mprj_pads.dm[35] = mprj_io_dm[35];
+ assign \mprj_pads.dm[34] = mprj_io_dm[34];
+ assign \mprj_pads.dm[33] = mprj_io_dm[33];
+ assign \mprj_pads.dm[32] = mprj_io_dm[32];
+ assign \mprj_pads.dm[31] = mprj_io_dm[31];
+ assign \mprj_pads.dm[30] = mprj_io_dm[30];
+ assign \mprj_pads.dm[29] = mprj_io_dm[29];
+ assign \mprj_pads.dm[28] = mprj_io_dm[28];
+ assign \mprj_pads.dm[27] = mprj_io_dm[27];
+ assign \mprj_pads.dm[26] = mprj_io_dm[26];
+ assign \mprj_pads.dm[25] = mprj_io_dm[25];
+ assign \mprj_pads.dm[24] = mprj_io_dm[24];
+ assign \mprj_pads.dm[23] = mprj_io_dm[23];
+ assign \mprj_pads.dm[22] = mprj_io_dm[22];
+ assign \mprj_pads.dm[21] = mprj_io_dm[21];
+ assign \mprj_pads.dm[20] = mprj_io_dm[20];
+ assign \mprj_pads.dm[19] = mprj_io_dm[19];
+ assign \mprj_pads.dm[18] = mprj_io_dm[18];
+ assign \mprj_pads.dm[17] = mprj_io_dm[17];
+ assign \mprj_pads.dm[16] = mprj_io_dm[16];
+ assign \mprj_pads.dm[15] = mprj_io_dm[15];
+ assign \mprj_pads.dm[14] = mprj_io_dm[14];
+ assign \mprj_pads.dm[13] = mprj_io_dm[13];
+ assign \mprj_pads.dm[12] = mprj_io_dm[12];
+ assign \mprj_pads.dm[11] = mprj_io_dm[11];
+ assign \mprj_pads.dm[10] = mprj_io_dm[10];
+ assign \mprj_pads.dm[9] = mprj_io_dm[9];
+ assign \mprj_pads.dm[8] = mprj_io_dm[8];
+ assign \mprj_pads.dm[7] = mprj_io_dm[7];
+ assign \mprj_pads.dm[6] = mprj_io_dm[6];
+ assign \mprj_pads.dm[5] = mprj_io_dm[5];
+ assign \mprj_pads.dm[4] = mprj_io_dm[4];
+ assign \mprj_pads.dm[3] = mprj_io_dm[3];
+ assign \mprj_pads.dm[2] = mprj_io_dm[2];
+ assign \mprj_pads.dm[1] = mprj_io_dm[1];
+ assign \mprj_pads.dm[0] = mprj_io_dm[0];
+ assign \flash_io0_mode[2] = flash_io0_ieb_core;
+ assign \flash_io0_mode[1] = flash_io0_ieb_core;
+ assign \flash_io0_mode[0] = flash_io0_oeb_core;
+ assign \mprj_pads.analog_sel[37] = mprj_io_analog_sel[37];
+ assign \mprj_pads.analog_sel[36] = mprj_io_analog_sel[36];
+ assign \mprj_pads.analog_sel[35] = mprj_io_analog_sel[35];
+ assign \mprj_pads.analog_sel[34] = mprj_io_analog_sel[34];
+ assign \mprj_pads.analog_sel[33] = mprj_io_analog_sel[33];
+ assign \mprj_pads.analog_sel[32] = mprj_io_analog_sel[32];
+ assign \mprj_pads.analog_sel[31] = mprj_io_analog_sel[31];
+ assign \mprj_pads.analog_sel[30] = mprj_io_analog_sel[30];
+ assign \mprj_pads.analog_sel[29] = mprj_io_analog_sel[29];
+ assign \mprj_pads.analog_sel[28] = mprj_io_analog_sel[28];
+ assign \mprj_pads.analog_sel[27] = mprj_io_analog_sel[27];
+ assign \mprj_pads.analog_sel[26] = mprj_io_analog_sel[26];
+ assign \mprj_pads.analog_sel[25] = mprj_io_analog_sel[25];
+ assign \mprj_pads.analog_sel[24] = mprj_io_analog_sel[24];
+ assign \mprj_pads.analog_sel[23] = mprj_io_analog_sel[23];
+ assign \mprj_pads.analog_sel[22] = mprj_io_analog_sel[22];
+ assign \mprj_pads.analog_sel[21] = mprj_io_analog_sel[21];
+ assign \mprj_pads.analog_sel[20] = mprj_io_analog_sel[20];
+ assign \mprj_pads.analog_sel[19] = mprj_io_analog_sel[19];
+ assign \mprj_pads.analog_sel[18] = mprj_io_analog_sel[18];
+ assign \mprj_pads.analog_sel[17] = mprj_io_analog_sel[17];
+ assign \mprj_pads.analog_sel[16] = mprj_io_analog_sel[16];
+ assign \mprj_pads.analog_sel[15] = mprj_io_analog_sel[15];
+ assign \mprj_pads.analog_sel[14] = mprj_io_analog_sel[14];
+ assign \mprj_pads.analog_sel[13] = mprj_io_analog_sel[13];
+ assign \mprj_pads.analog_sel[12] = mprj_io_analog_sel[12];
+ assign \mprj_pads.analog_sel[11] = mprj_io_analog_sel[11];
+ assign \mprj_pads.analog_sel[10] = mprj_io_analog_sel[10];
+ assign \mprj_pads.analog_sel[9] = mprj_io_analog_sel[9];
+ assign \mprj_pads.analog_sel[8] = mprj_io_analog_sel[8];
+ assign \mprj_pads.analog_sel[7] = mprj_io_analog_sel[7];
+ assign \mprj_pads.analog_sel[6] = mprj_io_analog_sel[6];
+ assign \mprj_pads.analog_sel[5] = mprj_io_analog_sel[5];
+ assign \mprj_pads.analog_sel[4] = mprj_io_analog_sel[4];
+ assign \mprj_pads.analog_sel[3] = mprj_io_analog_sel[3];
+ assign \mprj_pads.analog_sel[2] = mprj_io_analog_sel[2];
+ assign \mprj_pads.analog_sel[1] = mprj_io_analog_sel[1];
+ assign \mprj_pads.analog_sel[0] = mprj_io_analog_sel[0];
+ assign \mprj_pads.analog_io[28] = mprj_analog_io[28];
+ assign \mprj_pads.analog_io[27] = mprj_analog_io[27];
+ assign \mprj_pads.analog_io[26] = mprj_analog_io[26];
+ assign \mprj_pads.analog_io[25] = mprj_analog_io[25];
+ assign \mprj_pads.analog_io[24] = mprj_analog_io[24];
+ assign \mprj_pads.analog_io[23] = mprj_analog_io[23];
+ assign \mprj_pads.analog_io[22] = mprj_analog_io[22];
+ assign \mprj_pads.analog_io[21] = mprj_analog_io[21];
+ assign \mprj_pads.analog_io[20] = mprj_analog_io[20];
+ assign \mprj_pads.analog_io[19] = mprj_analog_io[19];
+ assign \mprj_pads.analog_io[18] = mprj_analog_io[18];
+ assign \mprj_pads.analog_io[17] = mprj_analog_io[17];
+ assign \mprj_pads.analog_io[16] = mprj_analog_io[16];
+ assign \mprj_pads.analog_io[15] = mprj_analog_io[15];
+ assign \mprj_pads.analog_io[14] = mprj_analog_io[14];
+ assign \mprj_pads.analog_io[13] = mprj_analog_io[13];
+ assign \mprj_pads.analog_io[12] = mprj_analog_io[12];
+ assign \mprj_pads.analog_io[11] = mprj_analog_io[11];
+ assign \mprj_pads.analog_io[10] = mprj_analog_io[10];
+ assign \mprj_pads.analog_io[9] = mprj_analog_io[9];
+ assign \mprj_pads.analog_io[8] = mprj_analog_io[8];
+ assign \mprj_pads.analog_io[7] = mprj_analog_io[7];
+ assign \mprj_pads.analog_io[6] = mprj_analog_io[6];
+ assign \mprj_pads.analog_io[5] = mprj_analog_io[5];
+ assign \mprj_pads.analog_io[4] = mprj_analog_io[4];
+ assign \mprj_pads.analog_io[3] = mprj_analog_io[3];
+ assign \mprj_pads.analog_io[2] = mprj_analog_io[2];
+ assign \mprj_pads.analog_io[1] = mprj_analog_io[1];
+ assign \mprj_pads.analog_io[0] = mprj_analog_io[0];
+ assign \mprj_pads.vtrip_sel[37] = mprj_io_vtrip_sel[37];
+ assign \mprj_pads.vtrip_sel[36] = mprj_io_vtrip_sel[36];
+ assign \mprj_pads.vtrip_sel[35] = mprj_io_vtrip_sel[35];
+ assign \mprj_pads.vtrip_sel[34] = mprj_io_vtrip_sel[34];
+ assign \mprj_pads.vtrip_sel[33] = mprj_io_vtrip_sel[33];
+ assign \mprj_pads.vtrip_sel[32] = mprj_io_vtrip_sel[32];
+ assign \mprj_pads.vtrip_sel[31] = mprj_io_vtrip_sel[31];
+ assign \mprj_pads.vtrip_sel[30] = mprj_io_vtrip_sel[30];
+ assign \mprj_pads.vtrip_sel[29] = mprj_io_vtrip_sel[29];
+ assign \mprj_pads.vtrip_sel[28] = mprj_io_vtrip_sel[28];
+ assign \mprj_pads.vtrip_sel[27] = mprj_io_vtrip_sel[27];
+ assign \mprj_pads.vtrip_sel[26] = mprj_io_vtrip_sel[26];
+ assign \mprj_pads.vtrip_sel[25] = mprj_io_vtrip_sel[25];
+ assign \mprj_pads.vtrip_sel[24] = mprj_io_vtrip_sel[24];
+ assign \mprj_pads.vtrip_sel[23] = mprj_io_vtrip_sel[23];
+ assign \mprj_pads.vtrip_sel[22] = mprj_io_vtrip_sel[22];
+ assign \mprj_pads.vtrip_sel[21] = mprj_io_vtrip_sel[21];
+ assign \mprj_pads.vtrip_sel[20] = mprj_io_vtrip_sel[20];
+ assign \mprj_pads.vtrip_sel[19] = mprj_io_vtrip_sel[19];
+ assign \mprj_pads.vtrip_sel[18] = mprj_io_vtrip_sel[18];
+ assign \mprj_pads.vtrip_sel[17] = mprj_io_vtrip_sel[17];
+ assign \mprj_pads.vtrip_sel[16] = mprj_io_vtrip_sel[16];
+ assign \mprj_pads.vtrip_sel[15] = mprj_io_vtrip_sel[15];
+ assign \mprj_pads.vtrip_sel[14] = mprj_io_vtrip_sel[14];
+ assign \mprj_pads.vtrip_sel[13] = mprj_io_vtrip_sel[13];
+ assign \mprj_pads.vtrip_sel[12] = mprj_io_vtrip_sel[12];
+ assign \mprj_pads.vtrip_sel[11] = mprj_io_vtrip_sel[11];
+ assign \mprj_pads.vtrip_sel[10] = mprj_io_vtrip_sel[10];
+ assign \mprj_pads.vtrip_sel[9] = mprj_io_vtrip_sel[9];
+ assign \mprj_pads.vtrip_sel[8] = mprj_io_vtrip_sel[8];
+ assign \mprj_pads.vtrip_sel[7] = mprj_io_vtrip_sel[7];
+ assign \mprj_pads.vtrip_sel[6] = mprj_io_vtrip_sel[6];
+ assign \mprj_pads.vtrip_sel[5] = mprj_io_vtrip_sel[5];
+ assign \mprj_pads.vtrip_sel[4] = mprj_io_vtrip_sel[4];
+ assign \mprj_pads.vtrip_sel[3] = mprj_io_vtrip_sel[3];
+ assign \mprj_pads.vtrip_sel[2] = mprj_io_vtrip_sel[2];
+ assign \mprj_pads.vtrip_sel[1] = mprj_io_vtrip_sel[1];
+ assign \mprj_pads.vtrip_sel[0] = mprj_io_vtrip_sel[0];
+ assign \mprj_pads.analog_en[37] = mprj_io_analog_en[37];
+ assign \mprj_pads.analog_en[36] = mprj_io_analog_en[36];
+ assign \mprj_pads.analog_en[35] = mprj_io_analog_en[35];
+ assign \mprj_pads.analog_en[34] = mprj_io_analog_en[34];
+ assign \mprj_pads.analog_en[33] = mprj_io_analog_en[33];
+ assign \mprj_pads.analog_en[32] = mprj_io_analog_en[32];
+ assign \mprj_pads.analog_en[31] = mprj_io_analog_en[31];
+ assign \mprj_pads.analog_en[30] = mprj_io_analog_en[30];
+ assign \mprj_pads.analog_en[29] = mprj_io_analog_en[29];
+ assign \mprj_pads.analog_en[28] = mprj_io_analog_en[28];
+ assign \mprj_pads.analog_en[27] = mprj_io_analog_en[27];
+ assign \mprj_pads.analog_en[26] = mprj_io_analog_en[26];
+ assign \mprj_pads.analog_en[25] = mprj_io_analog_en[25];
+ assign \mprj_pads.analog_en[24] = mprj_io_analog_en[24];
+ assign \mprj_pads.analog_en[23] = mprj_io_analog_en[23];
+ assign \mprj_pads.analog_en[22] = mprj_io_analog_en[22];
+ assign \mprj_pads.analog_en[21] = mprj_io_analog_en[21];
+ assign \mprj_pads.analog_en[20] = mprj_io_analog_en[20];
+ assign \mprj_pads.analog_en[19] = mprj_io_analog_en[19];
+ assign \mprj_pads.analog_en[18] = mprj_io_analog_en[18];
+ assign \mprj_pads.analog_en[17] = mprj_io_analog_en[17];
+ assign \mprj_pads.analog_en[16] = mprj_io_analog_en[16];
+ assign \mprj_pads.analog_en[15] = mprj_io_analog_en[15];
+ assign \mprj_pads.analog_en[14] = mprj_io_analog_en[14];
+ assign \mprj_pads.analog_en[13] = mprj_io_analog_en[13];
+ assign \mprj_pads.analog_en[12] = mprj_io_analog_en[12];
+ assign \mprj_pads.analog_en[11] = mprj_io_analog_en[11];
+ assign \mprj_pads.analog_en[10] = mprj_io_analog_en[10];
+ assign \mprj_pads.analog_en[9] = mprj_io_analog_en[9];
+ assign \mprj_pads.analog_en[8] = mprj_io_analog_en[8];
+ assign \mprj_pads.analog_en[7] = mprj_io_analog_en[7];
+ assign \mprj_pads.analog_en[6] = mprj_io_analog_en[6];
+ assign \mprj_pads.analog_en[5] = mprj_io_analog_en[5];
+ assign \mprj_pads.analog_en[4] = mprj_io_analog_en[4];
+ assign \mprj_pads.analog_en[3] = mprj_io_analog_en[3];
+ assign \mprj_pads.analog_en[2] = mprj_io_analog_en[2];
+ assign \mprj_pads.analog_en[1] = mprj_io_analog_en[1];
+ assign \mprj_pads.analog_en[0] = mprj_io_analog_en[0];
+ assign \mprj_pads.slow_sel[37] = mprj_io_slow_sel[37];
+ assign \mprj_pads.slow_sel[36] = mprj_io_slow_sel[36];
+ assign \mprj_pads.slow_sel[35] = mprj_io_slow_sel[35];
+ assign \mprj_pads.slow_sel[34] = mprj_io_slow_sel[34];
+ assign \mprj_pads.slow_sel[33] = mprj_io_slow_sel[33];
+ assign \mprj_pads.slow_sel[32] = mprj_io_slow_sel[32];
+ assign \mprj_pads.slow_sel[31] = mprj_io_slow_sel[31];
+ assign \mprj_pads.slow_sel[30] = mprj_io_slow_sel[30];
+ assign \mprj_pads.slow_sel[29] = mprj_io_slow_sel[29];
+ assign \mprj_pads.slow_sel[28] = mprj_io_slow_sel[28];
+ assign \mprj_pads.slow_sel[27] = mprj_io_slow_sel[27];
+ assign \mprj_pads.slow_sel[26] = mprj_io_slow_sel[26];
+ assign \mprj_pads.slow_sel[25] = mprj_io_slow_sel[25];
+ assign \mprj_pads.slow_sel[24] = mprj_io_slow_sel[24];
+ assign \mprj_pads.slow_sel[23] = mprj_io_slow_sel[23];
+ assign \mprj_pads.slow_sel[22] = mprj_io_slow_sel[22];
+ assign \mprj_pads.slow_sel[21] = mprj_io_slow_sel[21];
+ assign \mprj_pads.slow_sel[20] = mprj_io_slow_sel[20];
+ assign \mprj_pads.slow_sel[19] = mprj_io_slow_sel[19];
+ assign \mprj_pads.slow_sel[18] = mprj_io_slow_sel[18];
+ assign \mprj_pads.slow_sel[17] = mprj_io_slow_sel[17];
+ assign \mprj_pads.slow_sel[16] = mprj_io_slow_sel[16];
+ assign \mprj_pads.slow_sel[15] = mprj_io_slow_sel[15];
+ assign \mprj_pads.slow_sel[14] = mprj_io_slow_sel[14];
+ assign \mprj_pads.slow_sel[13] = mprj_io_slow_sel[13];
+ assign \mprj_pads.slow_sel[12] = mprj_io_slow_sel[12];
+ assign \mprj_pads.slow_sel[11] = mprj_io_slow_sel[11];
+ assign \mprj_pads.slow_sel[10] = mprj_io_slow_sel[10];
+ assign \mprj_pads.slow_sel[9] = mprj_io_slow_sel[9];
+ assign \mprj_pads.slow_sel[8] = mprj_io_slow_sel[8];
+ assign \mprj_pads.slow_sel[7] = mprj_io_slow_sel[7];
+ assign \mprj_pads.slow_sel[6] = mprj_io_slow_sel[6];
+ assign \mprj_pads.slow_sel[5] = mprj_io_slow_sel[5];
+ assign \mprj_pads.slow_sel[4] = mprj_io_slow_sel[4];
+ assign \mprj_pads.slow_sel[3] = mprj_io_slow_sel[3];
+ assign \mprj_pads.slow_sel[2] = mprj_io_slow_sel[2];
+ assign \mprj_pads.slow_sel[1] = mprj_io_slow_sel[1];
+ assign \mprj_pads.slow_sel[0] = mprj_io_slow_sel[0];
+ assign \dm_all[2] = gpio_mode1_core;
+ assign \dm_all[1] = gpio_mode1_core;
+ assign \dm_all[0] = gpio_mode0_core;
+ assign \flash_io1_mode[2] = flash_io1_ieb_core;
+ assign \flash_io1_mode[1] = flash_io1_ieb_core;
+ assign \flash_io1_mode[0] = flash_io1_oeb_core;
+ assign \mprj_pads.inp_dis[37] = mprj_io_inp_dis[37];
+ assign \mprj_pads.inp_dis[36] = mprj_io_inp_dis[36];
+ assign \mprj_pads.inp_dis[35] = mprj_io_inp_dis[35];
+ assign \mprj_pads.inp_dis[34] = mprj_io_inp_dis[34];
+ assign \mprj_pads.inp_dis[33] = mprj_io_inp_dis[33];
+ assign \mprj_pads.inp_dis[32] = mprj_io_inp_dis[32];
+ assign \mprj_pads.inp_dis[31] = mprj_io_inp_dis[31];
+ assign \mprj_pads.inp_dis[30] = mprj_io_inp_dis[30];
+ assign \mprj_pads.inp_dis[29] = mprj_io_inp_dis[29];
+ assign \mprj_pads.inp_dis[28] = mprj_io_inp_dis[28];
+ assign \mprj_pads.inp_dis[27] = mprj_io_inp_dis[27];
+ assign \mprj_pads.inp_dis[26] = mprj_io_inp_dis[26];
+ assign \mprj_pads.inp_dis[25] = mprj_io_inp_dis[25];
+ assign \mprj_pads.inp_dis[24] = mprj_io_inp_dis[24];
+ assign \mprj_pads.inp_dis[23] = mprj_io_inp_dis[23];
+ assign \mprj_pads.inp_dis[22] = mprj_io_inp_dis[22];
+ assign \mprj_pads.inp_dis[21] = mprj_io_inp_dis[21];
+ assign \mprj_pads.inp_dis[20] = mprj_io_inp_dis[20];
+ assign \mprj_pads.inp_dis[19] = mprj_io_inp_dis[19];
+ assign \mprj_pads.inp_dis[18] = mprj_io_inp_dis[18];
+ assign \mprj_pads.inp_dis[17] = mprj_io_inp_dis[17];
+ assign \mprj_pads.inp_dis[16] = mprj_io_inp_dis[16];
+ assign \mprj_pads.inp_dis[15] = mprj_io_inp_dis[15];
+ assign \mprj_pads.inp_dis[14] = mprj_io_inp_dis[14];
+ assign \mprj_pads.inp_dis[13] = mprj_io_inp_dis[13];
+ assign \mprj_pads.inp_dis[12] = mprj_io_inp_dis[12];
+ assign \mprj_pads.inp_dis[11] = mprj_io_inp_dis[11];
+ assign \mprj_pads.inp_dis[10] = mprj_io_inp_dis[10];
+ assign \mprj_pads.inp_dis[9] = mprj_io_inp_dis[9];
+ assign \mprj_pads.inp_dis[8] = mprj_io_inp_dis[8];
+ assign \mprj_pads.inp_dis[7] = mprj_io_inp_dis[7];
+ assign \mprj_pads.inp_dis[6] = mprj_io_inp_dis[6];
+ assign \mprj_pads.inp_dis[5] = mprj_io_inp_dis[5];
+ assign \mprj_pads.inp_dis[4] = mprj_io_inp_dis[4];
+ assign \mprj_pads.inp_dis[3] = mprj_io_inp_dis[3];
+ assign \mprj_pads.inp_dis[2] = mprj_io_inp_dis[2];
+ assign \mprj_pads.inp_dis[1] = mprj_io_inp_dis[1];
+ assign \mprj_pads.inp_dis[0] = mprj_io_inp_dis[0];
+ assign \mprj_pads.analog_pol[37] = mprj_io_analog_pol[37];
+ assign \mprj_pads.analog_pol[36] = mprj_io_analog_pol[36];
+ assign \mprj_pads.analog_pol[35] = mprj_io_analog_pol[35];
+ assign \mprj_pads.analog_pol[34] = mprj_io_analog_pol[34];
+ assign \mprj_pads.analog_pol[33] = mprj_io_analog_pol[33];
+ assign \mprj_pads.analog_pol[32] = mprj_io_analog_pol[32];
+ assign \mprj_pads.analog_pol[31] = mprj_io_analog_pol[31];
+ assign \mprj_pads.analog_pol[30] = mprj_io_analog_pol[30];
+ assign \mprj_pads.analog_pol[29] = mprj_io_analog_pol[29];
+ assign \mprj_pads.analog_pol[28] = mprj_io_analog_pol[28];
+ assign \mprj_pads.analog_pol[27] = mprj_io_analog_pol[27];
+ assign \mprj_pads.analog_pol[26] = mprj_io_analog_pol[26];
+ assign \mprj_pads.analog_pol[25] = mprj_io_analog_pol[25];
+ assign \mprj_pads.analog_pol[24] = mprj_io_analog_pol[24];
+ assign \mprj_pads.analog_pol[23] = mprj_io_analog_pol[23];
+ assign \mprj_pads.analog_pol[22] = mprj_io_analog_pol[22];
+ assign \mprj_pads.analog_pol[21] = mprj_io_analog_pol[21];
+ assign \mprj_pads.analog_pol[20] = mprj_io_analog_pol[20];
+ assign \mprj_pads.analog_pol[19] = mprj_io_analog_pol[19];
+ assign \mprj_pads.analog_pol[18] = mprj_io_analog_pol[18];
+ assign \mprj_pads.analog_pol[17] = mprj_io_analog_pol[17];
+ assign \mprj_pads.analog_pol[16] = mprj_io_analog_pol[16];
+ assign \mprj_pads.analog_pol[15] = mprj_io_analog_pol[15];
+ assign \mprj_pads.analog_pol[14] = mprj_io_analog_pol[14];
+ assign \mprj_pads.analog_pol[13] = mprj_io_analog_pol[13];
+ assign \mprj_pads.analog_pol[12] = mprj_io_analog_pol[12];
+ assign \mprj_pads.analog_pol[11] = mprj_io_analog_pol[11];
+ assign \mprj_pads.analog_pol[10] = mprj_io_analog_pol[10];
+ assign \mprj_pads.analog_pol[9] = mprj_io_analog_pol[9];
+ assign \mprj_pads.analog_pol[8] = mprj_io_analog_pol[8];
+ assign \mprj_pads.analog_pol[7] = mprj_io_analog_pol[7];
+ assign \mprj_pads.analog_pol[6] = mprj_io_analog_pol[6];
+ assign \mprj_pads.analog_pol[5] = mprj_io_analog_pol[5];
+ assign \mprj_pads.analog_pol[4] = mprj_io_analog_pol[4];
+ assign \mprj_pads.analog_pol[3] = mprj_io_analog_pol[3];
+ assign \mprj_pads.analog_pol[2] = mprj_io_analog_pol[2];
+ assign \mprj_pads.analog_pol[1] = mprj_io_analog_pol[1];
+ assign \mprj_pads.analog_pol[0] = mprj_io_analog_pol[0];
+ assign \mprj_pads.oeb[37] = mprj_io_oeb[37];
+ assign \mprj_pads.oeb[36] = mprj_io_oeb[36];
+ assign \mprj_pads.oeb[35] = mprj_io_oeb[35];
+ assign \mprj_pads.oeb[34] = mprj_io_oeb[34];
+ assign \mprj_pads.oeb[33] = mprj_io_oeb[33];
+ assign \mprj_pads.oeb[32] = mprj_io_oeb[32];
+ assign \mprj_pads.oeb[31] = mprj_io_oeb[31];
+ assign \mprj_pads.oeb[30] = mprj_io_oeb[30];
+ assign \mprj_pads.oeb[29] = mprj_io_oeb[29];
+ assign \mprj_pads.oeb[28] = mprj_io_oeb[28];
+ assign \mprj_pads.oeb[27] = mprj_io_oeb[27];
+ assign \mprj_pads.oeb[26] = mprj_io_oeb[26];
+ assign \mprj_pads.oeb[25] = mprj_io_oeb[25];
+ assign \mprj_pads.oeb[24] = mprj_io_oeb[24];
+ assign \mprj_pads.oeb[23] = mprj_io_oeb[23];
+ assign \mprj_pads.oeb[22] = mprj_io_oeb[22];
+ assign \mprj_pads.oeb[21] = mprj_io_oeb[21];
+ assign \mprj_pads.oeb[20] = mprj_io_oeb[20];
+ assign \mprj_pads.oeb[19] = mprj_io_oeb[19];
+ assign \mprj_pads.oeb[18] = mprj_io_oeb[18];
+ assign \mprj_pads.oeb[17] = mprj_io_oeb[17];
+ assign \mprj_pads.oeb[16] = mprj_io_oeb[16];
+ assign \mprj_pads.oeb[15] = mprj_io_oeb[15];
+ assign \mprj_pads.oeb[14] = mprj_io_oeb[14];
+ assign \mprj_pads.oeb[13] = mprj_io_oeb[13];
+ assign \mprj_pads.oeb[12] = mprj_io_oeb[12];
+ assign \mprj_pads.oeb[11] = mprj_io_oeb[11];
+ assign \mprj_pads.oeb[10] = mprj_io_oeb[10];
+ assign \mprj_pads.oeb[9] = mprj_io_oeb[9];
+ assign \mprj_pads.oeb[8] = mprj_io_oeb[8];
+ assign \mprj_pads.oeb[7] = mprj_io_oeb[7];
+ assign \mprj_pads.oeb[6] = mprj_io_oeb[6];
+ assign \mprj_pads.oeb[5] = mprj_io_oeb[5];
+ assign \mprj_pads.oeb[4] = mprj_io_oeb[4];
+ assign \mprj_pads.oeb[3] = mprj_io_oeb[3];
+ assign \mprj_pads.oeb[2] = mprj_io_oeb[2];
+ assign \mprj_pads.oeb[1] = mprj_io_oeb[1];
+ assign \mprj_pads.oeb[0] = mprj_io_oeb[0];
+ assign \mprj_pads.vddio = vddio;
+ assign \mprj_pads.vssio = vssio;
+ assign \mprj_pads.vccd = vccd;
+ assign \mprj_pads.vssd = vssd;
+ assign \mprj_pads.vdda1 = vdda1;
+ assign \mprj_pads.vdda2 = vdda2;
+ assign \mprj_pads.vssa1 = vssa1;
+ assign \mprj_pads.vssa2 = vssa2;
+ assign \mprj_pads.porb_h = porb_h;
+ assign \mprj_io_enh[26] = porb_h;
+ assign \mprj_io_enh[34] = porb_h;
+ assign \mprj_io_enh[10] = porb_h;
+ assign \mprj_io_enh[27] = porb_h;
+ assign \mprj_io_enh[36] = porb_h;
+ assign \mprj_io_enh[13] = porb_h;
+ assign \mprj_io_enh[28] = porb_h;
+ assign \mprj_io_enh[19] = porb_h;
+ assign \mprj_io_enh[17] = porb_h;
+ assign \mprj_io_enh[35] = porb_h;
+ assign \mprj_io_enh[18] = porb_h;
+ assign \mprj_io_enh[21] = porb_h;
+ assign \mprj_io_enh[11] = porb_h;
+ assign \mprj_io_enh[25] = porb_h;
+ assign \mprj_io_enh[23] = porb_h;
+ assign \mprj_io_enh[16] = porb_h;
+ assign \mprj_io_enh[20] = porb_h;
+ assign \mprj_io_enh[22] = porb_h;
+ assign \mprj_io_enh[31] = porb_h;
+ assign \mprj_io_enh[32] = porb_h;
+ assign \mprj_io_enh[30] = porb_h;
+ assign \mprj_io_enh[33] = porb_h;
+ assign \mprj_io_enh[12] = porb_h;
+ assign \mprj_io_enh[14] = porb_h;
+ assign \mprj_io_enh[24] = porb_h;
+ assign \mprj_io_enh[15] = porb_h;
+ assign vssio_q = \mprj_pads.vssio_q ;
+ assign vddio_q = \mprj_pads.vddio_q ;
+ assign analog_b = \mprj_pads.analog_b ;
+ assign analog_a = \mprj_pads.analog_a ;
+ assign \mprj_io_enh[37] = porb_h;
+ assign \mprj_io_enh[29] = porb_h;
+ assign mprj_io_in = { \mprj_pads.io_in[37] , \mprj_pads.io_in[36] , \mprj_pads.io_in[35] , \mprj_pads.io_in[34] , \mprj_pads.io_in[33] , \mprj_pads.io_in[32] , \mprj_pads.io_in[31] , \mprj_pads.io_in[30] , \mprj_pads.io_in[29] , \mprj_pads.io_in[28] , \mprj_pads.io_in[27] , \mprj_pads.io_in[26] , \mprj_pads.io_in[25] , \mprj_pads.io_in[24] , \mprj_pads.io_in[23] , \mprj_pads.io_in[22] , \mprj_pads.io_in[21] , \mprj_pads.io_in[20] , \mprj_pads.io_in[19] , \mprj_pads.io_in[18] , \mprj_pads.io_in[17] , \mprj_pads.io_in[16] , \mprj_pads.io_in[15] , \mprj_pads.io_in[14] , \mprj_pads.io_in[13] , \mprj_pads.io_in[12] , \mprj_pads.io_in[11] , \mprj_pads.io_in[10] , \mprj_pads.io_in[9] , \mprj_pads.io_in[8] , \mprj_pads.io_in[7] , \mprj_pads.io_in[6] , \mprj_pads.io_in[5] , \mprj_pads.io_in[4] , \mprj_pads.io_in[3] , \mprj_pads.io_in[2] , \mprj_pads.io_in[1] , \mprj_pads.io_in[0] };
+endmodule
diff --git a/caravel/verilog/gl/chip_io_alt.v b/caravel/verilog/gl/chip_io_alt.v
new file mode 100644
index 0000000..c6ebe51
--- /dev/null
+++ b/caravel/verilog/gl/chip_io_alt.v
@@ -0,0 +1,3118 @@
+/* Generated by Yosys 0.9+4052 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) */
+
+module chip_io_alt(vddio_pad, vddio_pad2, vssio_pad, vssio_pad2, vccd_pad, vssd_pad, vdda_pad, vssa_pad, vdda1_pad, vdda1_pad2, vdda2_pad, vssa1_pad, vssa1_pad2, vssa2_pad, vccd1_pad, vccd2_pad, vssd1_pad, vssd2_pad, vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, mprj_io, mprj_io_out, mprj_io_oeb, mprj_io_inp_dis, mprj_io_ib_mode_sel, mprj_io_vtrip_sel, mprj_io_slow_sel, mprj_io_holdover, mprj_io_analog_en, mprj_io_analog_sel, mprj_io_analog_pol, mprj_io_dm, mprj_io_in, mprj_io_in_3v3, mprj_gpio_analog, mprj_gpio_noesd, mprj_analog, mprj_clamp_high, mprj_clamp_low);
+ wire analog_a;
+ wire analog_b;
+ input clock;
+ output clock_core;
+ wire \dm_all[0] ;
+ wire \dm_all[1] ;
+ wire \dm_all[2] ;
+ output flash_clk;
+ input flash_clk_core;
+ input flash_clk_ieb_core;
+ input flash_clk_oeb_core;
+ output flash_csb;
+ input flash_csb_core;
+ input flash_csb_ieb_core;
+ input flash_csb_oeb_core;
+ inout flash_io0;
+ output flash_io0_di_core;
+ input flash_io0_do_core;
+ input flash_io0_ieb_core;
+ wire \flash_io0_mode[0] ;
+ wire \flash_io0_mode[1] ;
+ wire \flash_io0_mode[2] ;
+ input flash_io0_oeb_core;
+ inout flash_io1;
+ output flash_io1_di_core;
+ input flash_io1_do_core;
+ input flash_io1_ieb_core;
+ wire \flash_io1_mode[0] ;
+ wire \flash_io1_mode[1] ;
+ wire \flash_io1_mode[2] ;
+ input flash_io1_oeb_core;
+ inout gpio;
+ output gpio_in_core;
+ input gpio_inenb_core;
+ input gpio_mode0_core;
+ input gpio_mode1_core;
+ input gpio_out_core;
+ input gpio_outenb_core;
+ wire loop_clock;
+ wire loop_flash_clk;
+ wire loop_flash_csb;
+ wire loop_flash_io0;
+ wire loop_flash_io1;
+ wire loop_gpio;
+ inout [10:0] mprj_analog;
+ input [2:0] mprj_clamp_high;
+ input [2:0] mprj_clamp_low;
+ inout [17:0] mprj_gpio_analog;
+ inout [17:0] mprj_gpio_noesd;
+ inout [37:0] mprj_io;
+ input [26:0] mprj_io_analog_en;
+ input [26:0] mprj_io_analog_pol;
+ input [26:0] mprj_io_analog_sel;
+ input [80:0] mprj_io_dm;
+ wire \mprj_io_enh[0] ;
+ wire \mprj_io_enh[10] ;
+ wire \mprj_io_enh[11] ;
+ wire \mprj_io_enh[12] ;
+ wire \mprj_io_enh[13] ;
+ wire \mprj_io_enh[14] ;
+ wire \mprj_io_enh[15] ;
+ wire \mprj_io_enh[16] ;
+ wire \mprj_io_enh[17] ;
+ wire \mprj_io_enh[18] ;
+ wire \mprj_io_enh[19] ;
+ wire \mprj_io_enh[1] ;
+ wire \mprj_io_enh[20] ;
+ wire \mprj_io_enh[21] ;
+ wire \mprj_io_enh[22] ;
+ wire \mprj_io_enh[23] ;
+ wire \mprj_io_enh[24] ;
+ wire \mprj_io_enh[25] ;
+ wire \mprj_io_enh[26] ;
+ wire \mprj_io_enh[2] ;
+ wire \mprj_io_enh[3] ;
+ wire \mprj_io_enh[4] ;
+ wire \mprj_io_enh[5] ;
+ wire \mprj_io_enh[6] ;
+ wire \mprj_io_enh[7] ;
+ wire \mprj_io_enh[8] ;
+ wire \mprj_io_enh[9] ;
+ wire \mprj_io_hldh_n[0] ;
+ wire \mprj_io_hldh_n[10] ;
+ wire \mprj_io_hldh_n[11] ;
+ wire \mprj_io_hldh_n[12] ;
+ wire \mprj_io_hldh_n[13] ;
+ wire \mprj_io_hldh_n[14] ;
+ wire \mprj_io_hldh_n[15] ;
+ wire \mprj_io_hldh_n[16] ;
+ wire \mprj_io_hldh_n[17] ;
+ wire \mprj_io_hldh_n[18] ;
+ wire \mprj_io_hldh_n[19] ;
+ wire \mprj_io_hldh_n[1] ;
+ wire \mprj_io_hldh_n[20] ;
+ wire \mprj_io_hldh_n[21] ;
+ wire \mprj_io_hldh_n[22] ;
+ wire \mprj_io_hldh_n[23] ;
+ wire \mprj_io_hldh_n[24] ;
+ wire \mprj_io_hldh_n[25] ;
+ wire \mprj_io_hldh_n[26] ;
+ wire \mprj_io_hldh_n[2] ;
+ wire \mprj_io_hldh_n[3] ;
+ wire \mprj_io_hldh_n[4] ;
+ wire \mprj_io_hldh_n[5] ;
+ wire \mprj_io_hldh_n[6] ;
+ wire \mprj_io_hldh_n[7] ;
+ wire \mprj_io_hldh_n[8] ;
+ wire \mprj_io_hldh_n[9] ;
+ input [26:0] mprj_io_holdover;
+ input [26:0] mprj_io_ib_mode_sel;
+ output [26:0] mprj_io_in;
+ output [26:0] mprj_io_in_3v3;
+ input [26:0] mprj_io_inp_dis;
+ input [26:0] mprj_io_oeb;
+ input [26:0] mprj_io_out;
+ input [26:0] mprj_io_slow_sel;
+ input [26:0] mprj_io_vtrip_sel;
+ wire \mprj_pads.analog_a ;
+ wire \mprj_pads.analog_b ;
+ wire \mprj_pads.analog_en[0] ;
+ wire \mprj_pads.analog_en[10] ;
+ wire \mprj_pads.analog_en[11] ;
+ wire \mprj_pads.analog_en[12] ;
+ wire \mprj_pads.analog_en[13] ;
+ wire \mprj_pads.analog_en[14] ;
+ wire \mprj_pads.analog_en[15] ;
+ wire \mprj_pads.analog_en[16] ;
+ wire \mprj_pads.analog_en[17] ;
+ wire \mprj_pads.analog_en[18] ;
+ wire \mprj_pads.analog_en[19] ;
+ wire \mprj_pads.analog_en[1] ;
+ wire \mprj_pads.analog_en[20] ;
+ wire \mprj_pads.analog_en[21] ;
+ wire \mprj_pads.analog_en[22] ;
+ wire \mprj_pads.analog_en[23] ;
+ wire \mprj_pads.analog_en[24] ;
+ wire \mprj_pads.analog_en[25] ;
+ wire \mprj_pads.analog_en[26] ;
+ wire \mprj_pads.analog_en[2] ;
+ wire \mprj_pads.analog_en[3] ;
+ wire \mprj_pads.analog_en[4] ;
+ wire \mprj_pads.analog_en[5] ;
+ wire \mprj_pads.analog_en[6] ;
+ wire \mprj_pads.analog_en[7] ;
+ wire \mprj_pads.analog_en[8] ;
+ wire \mprj_pads.analog_en[9] ;
+ wire \mprj_pads.analog_io[0] ;
+ wire \mprj_pads.analog_io[10] ;
+ wire \mprj_pads.analog_io[11] ;
+ wire \mprj_pads.analog_io[12] ;
+ wire \mprj_pads.analog_io[13] ;
+ wire \mprj_pads.analog_io[14] ;
+ wire \mprj_pads.analog_io[15] ;
+ wire \mprj_pads.analog_io[16] ;
+ wire \mprj_pads.analog_io[17] ;
+ wire \mprj_pads.analog_io[1] ;
+ wire \mprj_pads.analog_io[2] ;
+ wire \mprj_pads.analog_io[3] ;
+ wire \mprj_pads.analog_io[4] ;
+ wire \mprj_pads.analog_io[5] ;
+ wire \mprj_pads.analog_io[6] ;
+ wire \mprj_pads.analog_io[7] ;
+ wire \mprj_pads.analog_io[8] ;
+ wire \mprj_pads.analog_io[9] ;
+ wire \mprj_pads.analog_noesd_io[0] ;
+ wire \mprj_pads.analog_noesd_io[10] ;
+ wire \mprj_pads.analog_noesd_io[11] ;
+ wire \mprj_pads.analog_noesd_io[12] ;
+ wire \mprj_pads.analog_noesd_io[13] ;
+ wire \mprj_pads.analog_noesd_io[14] ;
+ wire \mprj_pads.analog_noesd_io[15] ;
+ wire \mprj_pads.analog_noesd_io[16] ;
+ wire \mprj_pads.analog_noesd_io[17] ;
+ wire \mprj_pads.analog_noesd_io[1] ;
+ wire \mprj_pads.analog_noesd_io[2] ;
+ wire \mprj_pads.analog_noesd_io[3] ;
+ wire \mprj_pads.analog_noesd_io[4] ;
+ wire \mprj_pads.analog_noesd_io[5] ;
+ wire \mprj_pads.analog_noesd_io[6] ;
+ wire \mprj_pads.analog_noesd_io[7] ;
+ wire \mprj_pads.analog_noesd_io[8] ;
+ wire \mprj_pads.analog_noesd_io[9] ;
+ wire \mprj_pads.analog_pol[0] ;
+ wire \mprj_pads.analog_pol[10] ;
+ wire \mprj_pads.analog_pol[11] ;
+ wire \mprj_pads.analog_pol[12] ;
+ wire \mprj_pads.analog_pol[13] ;
+ wire \mprj_pads.analog_pol[14] ;
+ wire \mprj_pads.analog_pol[15] ;
+ wire \mprj_pads.analog_pol[16] ;
+ wire \mprj_pads.analog_pol[17] ;
+ wire \mprj_pads.analog_pol[18] ;
+ wire \mprj_pads.analog_pol[19] ;
+ wire \mprj_pads.analog_pol[1] ;
+ wire \mprj_pads.analog_pol[20] ;
+ wire \mprj_pads.analog_pol[21] ;
+ wire \mprj_pads.analog_pol[22] ;
+ wire \mprj_pads.analog_pol[23] ;
+ wire \mprj_pads.analog_pol[24] ;
+ wire \mprj_pads.analog_pol[25] ;
+ wire \mprj_pads.analog_pol[26] ;
+ wire \mprj_pads.analog_pol[2] ;
+ wire \mprj_pads.analog_pol[3] ;
+ wire \mprj_pads.analog_pol[4] ;
+ wire \mprj_pads.analog_pol[5] ;
+ wire \mprj_pads.analog_pol[6] ;
+ wire \mprj_pads.analog_pol[7] ;
+ wire \mprj_pads.analog_pol[8] ;
+ wire \mprj_pads.analog_pol[9] ;
+ wire \mprj_pads.analog_sel[0] ;
+ wire \mprj_pads.analog_sel[10] ;
+ wire \mprj_pads.analog_sel[11] ;
+ wire \mprj_pads.analog_sel[12] ;
+ wire \mprj_pads.analog_sel[13] ;
+ wire \mprj_pads.analog_sel[14] ;
+ wire \mprj_pads.analog_sel[15] ;
+ wire \mprj_pads.analog_sel[16] ;
+ wire \mprj_pads.analog_sel[17] ;
+ wire \mprj_pads.analog_sel[18] ;
+ wire \mprj_pads.analog_sel[19] ;
+ wire \mprj_pads.analog_sel[1] ;
+ wire \mprj_pads.analog_sel[20] ;
+ wire \mprj_pads.analog_sel[21] ;
+ wire \mprj_pads.analog_sel[22] ;
+ wire \mprj_pads.analog_sel[23] ;
+ wire \mprj_pads.analog_sel[24] ;
+ wire \mprj_pads.analog_sel[25] ;
+ wire \mprj_pads.analog_sel[26] ;
+ wire \mprj_pads.analog_sel[2] ;
+ wire \mprj_pads.analog_sel[3] ;
+ wire \mprj_pads.analog_sel[4] ;
+ wire \mprj_pads.analog_sel[5] ;
+ wire \mprj_pads.analog_sel[6] ;
+ wire \mprj_pads.analog_sel[7] ;
+ wire \mprj_pads.analog_sel[8] ;
+ wire \mprj_pads.analog_sel[9] ;
+ wire \mprj_pads.dm[0] ;
+ wire \mprj_pads.dm[10] ;
+ wire \mprj_pads.dm[11] ;
+ wire \mprj_pads.dm[12] ;
+ wire \mprj_pads.dm[13] ;
+ wire \mprj_pads.dm[14] ;
+ wire \mprj_pads.dm[15] ;
+ wire \mprj_pads.dm[16] ;
+ wire \mprj_pads.dm[17] ;
+ wire \mprj_pads.dm[18] ;
+ wire \mprj_pads.dm[19] ;
+ wire \mprj_pads.dm[1] ;
+ wire \mprj_pads.dm[20] ;
+ wire \mprj_pads.dm[21] ;
+ wire \mprj_pads.dm[22] ;
+ wire \mprj_pads.dm[23] ;
+ wire \mprj_pads.dm[24] ;
+ wire \mprj_pads.dm[25] ;
+ wire \mprj_pads.dm[26] ;
+ wire \mprj_pads.dm[27] ;
+ wire \mprj_pads.dm[28] ;
+ wire \mprj_pads.dm[29] ;
+ wire \mprj_pads.dm[2] ;
+ wire \mprj_pads.dm[30] ;
+ wire \mprj_pads.dm[31] ;
+ wire \mprj_pads.dm[32] ;
+ wire \mprj_pads.dm[33] ;
+ wire \mprj_pads.dm[34] ;
+ wire \mprj_pads.dm[35] ;
+ wire \mprj_pads.dm[36] ;
+ wire \mprj_pads.dm[37] ;
+ wire \mprj_pads.dm[38] ;
+ wire \mprj_pads.dm[39] ;
+ wire \mprj_pads.dm[3] ;
+ wire \mprj_pads.dm[40] ;
+ wire \mprj_pads.dm[41] ;
+ wire \mprj_pads.dm[42] ;
+ wire \mprj_pads.dm[43] ;
+ wire \mprj_pads.dm[44] ;
+ wire \mprj_pads.dm[45] ;
+ wire \mprj_pads.dm[46] ;
+ wire \mprj_pads.dm[47] ;
+ wire \mprj_pads.dm[48] ;
+ wire \mprj_pads.dm[49] ;
+ wire \mprj_pads.dm[4] ;
+ wire \mprj_pads.dm[50] ;
+ wire \mprj_pads.dm[51] ;
+ wire \mprj_pads.dm[52] ;
+ wire \mprj_pads.dm[53] ;
+ wire \mprj_pads.dm[54] ;
+ wire \mprj_pads.dm[55] ;
+ wire \mprj_pads.dm[56] ;
+ wire \mprj_pads.dm[57] ;
+ wire \mprj_pads.dm[58] ;
+ wire \mprj_pads.dm[59] ;
+ wire \mprj_pads.dm[5] ;
+ wire \mprj_pads.dm[60] ;
+ wire \mprj_pads.dm[61] ;
+ wire \mprj_pads.dm[62] ;
+ wire \mprj_pads.dm[63] ;
+ wire \mprj_pads.dm[64] ;
+ wire \mprj_pads.dm[65] ;
+ wire \mprj_pads.dm[66] ;
+ wire \mprj_pads.dm[67] ;
+ wire \mprj_pads.dm[68] ;
+ wire \mprj_pads.dm[69] ;
+ wire \mprj_pads.dm[6] ;
+ wire \mprj_pads.dm[70] ;
+ wire \mprj_pads.dm[71] ;
+ wire \mprj_pads.dm[72] ;
+ wire \mprj_pads.dm[73] ;
+ wire \mprj_pads.dm[74] ;
+ wire \mprj_pads.dm[75] ;
+ wire \mprj_pads.dm[76] ;
+ wire \mprj_pads.dm[77] ;
+ wire \mprj_pads.dm[78] ;
+ wire \mprj_pads.dm[79] ;
+ wire \mprj_pads.dm[7] ;
+ wire \mprj_pads.dm[80] ;
+ wire \mprj_pads.dm[8] ;
+ wire \mprj_pads.dm[9] ;
+ wire \mprj_pads.enh[0] ;
+ wire \mprj_pads.enh[10] ;
+ wire \mprj_pads.enh[11] ;
+ wire \mprj_pads.enh[12] ;
+ wire \mprj_pads.enh[13] ;
+ wire \mprj_pads.enh[14] ;
+ wire \mprj_pads.enh[15] ;
+ wire \mprj_pads.enh[16] ;
+ wire \mprj_pads.enh[17] ;
+ wire \mprj_pads.enh[18] ;
+ wire \mprj_pads.enh[19] ;
+ wire \mprj_pads.enh[1] ;
+ wire \mprj_pads.enh[20] ;
+ wire \mprj_pads.enh[21] ;
+ wire \mprj_pads.enh[22] ;
+ wire \mprj_pads.enh[23] ;
+ wire \mprj_pads.enh[24] ;
+ wire \mprj_pads.enh[25] ;
+ wire \mprj_pads.enh[26] ;
+ wire \mprj_pads.enh[2] ;
+ wire \mprj_pads.enh[3] ;
+ wire \mprj_pads.enh[4] ;
+ wire \mprj_pads.enh[5] ;
+ wire \mprj_pads.enh[6] ;
+ wire \mprj_pads.enh[7] ;
+ wire \mprj_pads.enh[8] ;
+ wire \mprj_pads.enh[9] ;
+ wire \mprj_pads.hldh_n[0] ;
+ wire \mprj_pads.hldh_n[10] ;
+ wire \mprj_pads.hldh_n[11] ;
+ wire \mprj_pads.hldh_n[12] ;
+ wire \mprj_pads.hldh_n[13] ;
+ wire \mprj_pads.hldh_n[14] ;
+ wire \mprj_pads.hldh_n[15] ;
+ wire \mprj_pads.hldh_n[16] ;
+ wire \mprj_pads.hldh_n[17] ;
+ wire \mprj_pads.hldh_n[18] ;
+ wire \mprj_pads.hldh_n[19] ;
+ wire \mprj_pads.hldh_n[1] ;
+ wire \mprj_pads.hldh_n[20] ;
+ wire \mprj_pads.hldh_n[21] ;
+ wire \mprj_pads.hldh_n[22] ;
+ wire \mprj_pads.hldh_n[23] ;
+ wire \mprj_pads.hldh_n[24] ;
+ wire \mprj_pads.hldh_n[25] ;
+ wire \mprj_pads.hldh_n[26] ;
+ wire \mprj_pads.hldh_n[2] ;
+ wire \mprj_pads.hldh_n[3] ;
+ wire \mprj_pads.hldh_n[4] ;
+ wire \mprj_pads.hldh_n[5] ;
+ wire \mprj_pads.hldh_n[6] ;
+ wire \mprj_pads.hldh_n[7] ;
+ wire \mprj_pads.hldh_n[8] ;
+ wire \mprj_pads.hldh_n[9] ;
+ wire \mprj_pads.holdover[0] ;
+ wire \mprj_pads.holdover[10] ;
+ wire \mprj_pads.holdover[11] ;
+ wire \mprj_pads.holdover[12] ;
+ wire \mprj_pads.holdover[13] ;
+ wire \mprj_pads.holdover[14] ;
+ wire \mprj_pads.holdover[15] ;
+ wire \mprj_pads.holdover[16] ;
+ wire \mprj_pads.holdover[17] ;
+ wire \mprj_pads.holdover[18] ;
+ wire \mprj_pads.holdover[19] ;
+ wire \mprj_pads.holdover[1] ;
+ wire \mprj_pads.holdover[20] ;
+ wire \mprj_pads.holdover[21] ;
+ wire \mprj_pads.holdover[22] ;
+ wire \mprj_pads.holdover[23] ;
+ wire \mprj_pads.holdover[24] ;
+ wire \mprj_pads.holdover[25] ;
+ wire \mprj_pads.holdover[26] ;
+ wire \mprj_pads.holdover[2] ;
+ wire \mprj_pads.holdover[3] ;
+ wire \mprj_pads.holdover[4] ;
+ wire \mprj_pads.holdover[5] ;
+ wire \mprj_pads.holdover[6] ;
+ wire \mprj_pads.holdover[7] ;
+ wire \mprj_pads.holdover[8] ;
+ wire \mprj_pads.holdover[9] ;
+ wire \mprj_pads.ib_mode_sel[0] ;
+ wire \mprj_pads.ib_mode_sel[10] ;
+ wire \mprj_pads.ib_mode_sel[11] ;
+ wire \mprj_pads.ib_mode_sel[12] ;
+ wire \mprj_pads.ib_mode_sel[13] ;
+ wire \mprj_pads.ib_mode_sel[14] ;
+ wire \mprj_pads.ib_mode_sel[15] ;
+ wire \mprj_pads.ib_mode_sel[16] ;
+ wire \mprj_pads.ib_mode_sel[17] ;
+ wire \mprj_pads.ib_mode_sel[18] ;
+ wire \mprj_pads.ib_mode_sel[19] ;
+ wire \mprj_pads.ib_mode_sel[1] ;
+ wire \mprj_pads.ib_mode_sel[20] ;
+ wire \mprj_pads.ib_mode_sel[21] ;
+ wire \mprj_pads.ib_mode_sel[22] ;
+ wire \mprj_pads.ib_mode_sel[23] ;
+ wire \mprj_pads.ib_mode_sel[24] ;
+ wire \mprj_pads.ib_mode_sel[25] ;
+ wire \mprj_pads.ib_mode_sel[26] ;
+ wire \mprj_pads.ib_mode_sel[2] ;
+ wire \mprj_pads.ib_mode_sel[3] ;
+ wire \mprj_pads.ib_mode_sel[4] ;
+ wire \mprj_pads.ib_mode_sel[5] ;
+ wire \mprj_pads.ib_mode_sel[6] ;
+ wire \mprj_pads.ib_mode_sel[7] ;
+ wire \mprj_pads.ib_mode_sel[8] ;
+ wire \mprj_pads.ib_mode_sel[9] ;
+ wire \mprj_pads.inp_dis[0] ;
+ wire \mprj_pads.inp_dis[10] ;
+ wire \mprj_pads.inp_dis[11] ;
+ wire \mprj_pads.inp_dis[12] ;
+ wire \mprj_pads.inp_dis[13] ;
+ wire \mprj_pads.inp_dis[14] ;
+ wire \mprj_pads.inp_dis[15] ;
+ wire \mprj_pads.inp_dis[16] ;
+ wire \mprj_pads.inp_dis[17] ;
+ wire \mprj_pads.inp_dis[18] ;
+ wire \mprj_pads.inp_dis[19] ;
+ wire \mprj_pads.inp_dis[1] ;
+ wire \mprj_pads.inp_dis[20] ;
+ wire \mprj_pads.inp_dis[21] ;
+ wire \mprj_pads.inp_dis[22] ;
+ wire \mprj_pads.inp_dis[23] ;
+ wire \mprj_pads.inp_dis[24] ;
+ wire \mprj_pads.inp_dis[25] ;
+ wire \mprj_pads.inp_dis[26] ;
+ wire \mprj_pads.inp_dis[2] ;
+ wire \mprj_pads.inp_dis[3] ;
+ wire \mprj_pads.inp_dis[4] ;
+ wire \mprj_pads.inp_dis[5] ;
+ wire \mprj_pads.inp_dis[6] ;
+ wire \mprj_pads.inp_dis[7] ;
+ wire \mprj_pads.inp_dis[8] ;
+ wire \mprj_pads.inp_dis[9] ;
+ wire \mprj_pads.io[0] ;
+ wire \mprj_pads.io[10] ;
+ wire \mprj_pads.io[11] ;
+ wire \mprj_pads.io[12] ;
+ wire \mprj_pads.io[13] ;
+ wire \mprj_pads.io[14] ;
+ wire \mprj_pads.io[15] ;
+ wire \mprj_pads.io[16] ;
+ wire \mprj_pads.io[17] ;
+ wire \mprj_pads.io[18] ;
+ wire \mprj_pads.io[19] ;
+ wire \mprj_pads.io[1] ;
+ wire \mprj_pads.io[20] ;
+ wire \mprj_pads.io[21] ;
+ wire \mprj_pads.io[22] ;
+ wire \mprj_pads.io[23] ;
+ wire \mprj_pads.io[24] ;
+ wire \mprj_pads.io[25] ;
+ wire \mprj_pads.io[26] ;
+ wire \mprj_pads.io[2] ;
+ wire \mprj_pads.io[3] ;
+ wire \mprj_pads.io[4] ;
+ wire \mprj_pads.io[5] ;
+ wire \mprj_pads.io[6] ;
+ wire \mprj_pads.io[7] ;
+ wire \mprj_pads.io[8] ;
+ wire \mprj_pads.io[9] ;
+ wire \mprj_pads.io_in[0] ;
+ wire \mprj_pads.io_in[10] ;
+ wire \mprj_pads.io_in[11] ;
+ wire \mprj_pads.io_in[12] ;
+ wire \mprj_pads.io_in[13] ;
+ wire \mprj_pads.io_in[14] ;
+ wire \mprj_pads.io_in[15] ;
+ wire \mprj_pads.io_in[16] ;
+ wire \mprj_pads.io_in[17] ;
+ wire \mprj_pads.io_in[18] ;
+ wire \mprj_pads.io_in[19] ;
+ wire \mprj_pads.io_in[1] ;
+ wire \mprj_pads.io_in[20] ;
+ wire \mprj_pads.io_in[21] ;
+ wire \mprj_pads.io_in[22] ;
+ wire \mprj_pads.io_in[23] ;
+ wire \mprj_pads.io_in[24] ;
+ wire \mprj_pads.io_in[25] ;
+ wire \mprj_pads.io_in[26] ;
+ wire \mprj_pads.io_in[2] ;
+ wire \mprj_pads.io_in[3] ;
+ wire \mprj_pads.io_in[4] ;
+ wire \mprj_pads.io_in[5] ;
+ wire \mprj_pads.io_in[6] ;
+ wire \mprj_pads.io_in[7] ;
+ wire \mprj_pads.io_in[8] ;
+ wire \mprj_pads.io_in[9] ;
+ wire \mprj_pads.io_in_3v3[0] ;
+ wire \mprj_pads.io_in_3v3[10] ;
+ wire \mprj_pads.io_in_3v3[11] ;
+ wire \mprj_pads.io_in_3v3[12] ;
+ wire \mprj_pads.io_in_3v3[13] ;
+ wire \mprj_pads.io_in_3v3[14] ;
+ wire \mprj_pads.io_in_3v3[15] ;
+ wire \mprj_pads.io_in_3v3[16] ;
+ wire \mprj_pads.io_in_3v3[17] ;
+ wire \mprj_pads.io_in_3v3[18] ;
+ wire \mprj_pads.io_in_3v3[19] ;
+ wire \mprj_pads.io_in_3v3[1] ;
+ wire \mprj_pads.io_in_3v3[20] ;
+ wire \mprj_pads.io_in_3v3[21] ;
+ wire \mprj_pads.io_in_3v3[22] ;
+ wire \mprj_pads.io_in_3v3[23] ;
+ wire \mprj_pads.io_in_3v3[24] ;
+ wire \mprj_pads.io_in_3v3[25] ;
+ wire \mprj_pads.io_in_3v3[26] ;
+ wire \mprj_pads.io_in_3v3[2] ;
+ wire \mprj_pads.io_in_3v3[3] ;
+ wire \mprj_pads.io_in_3v3[4] ;
+ wire \mprj_pads.io_in_3v3[5] ;
+ wire \mprj_pads.io_in_3v3[6] ;
+ wire \mprj_pads.io_in_3v3[7] ;
+ wire \mprj_pads.io_in_3v3[8] ;
+ wire \mprj_pads.io_in_3v3[9] ;
+ wire \mprj_pads.io_out[0] ;
+ wire \mprj_pads.io_out[10] ;
+ wire \mprj_pads.io_out[11] ;
+ wire \mprj_pads.io_out[12] ;
+ wire \mprj_pads.io_out[13] ;
+ wire \mprj_pads.io_out[14] ;
+ wire \mprj_pads.io_out[15] ;
+ wire \mprj_pads.io_out[16] ;
+ wire \mprj_pads.io_out[17] ;
+ wire \mprj_pads.io_out[18] ;
+ wire \mprj_pads.io_out[19] ;
+ wire \mprj_pads.io_out[1] ;
+ wire \mprj_pads.io_out[20] ;
+ wire \mprj_pads.io_out[21] ;
+ wire \mprj_pads.io_out[22] ;
+ wire \mprj_pads.io_out[23] ;
+ wire \mprj_pads.io_out[24] ;
+ wire \mprj_pads.io_out[25] ;
+ wire \mprj_pads.io_out[26] ;
+ wire \mprj_pads.io_out[2] ;
+ wire \mprj_pads.io_out[3] ;
+ wire \mprj_pads.io_out[4] ;
+ wire \mprj_pads.io_out[5] ;
+ wire \mprj_pads.io_out[6] ;
+ wire \mprj_pads.io_out[7] ;
+ wire \mprj_pads.io_out[8] ;
+ wire \mprj_pads.io_out[9] ;
+ wire \mprj_pads.loop1_io[0] ;
+ wire \mprj_pads.loop1_io[10] ;
+ wire \mprj_pads.loop1_io[11] ;
+ wire \mprj_pads.loop1_io[12] ;
+ wire \mprj_pads.loop1_io[13] ;
+ wire \mprj_pads.loop1_io[14] ;
+ wire \mprj_pads.loop1_io[15] ;
+ wire \mprj_pads.loop1_io[16] ;
+ wire \mprj_pads.loop1_io[17] ;
+ wire \mprj_pads.loop1_io[18] ;
+ wire \mprj_pads.loop1_io[19] ;
+ wire \mprj_pads.loop1_io[1] ;
+ wire \mprj_pads.loop1_io[20] ;
+ wire \mprj_pads.loop1_io[21] ;
+ wire \mprj_pads.loop1_io[22] ;
+ wire \mprj_pads.loop1_io[23] ;
+ wire \mprj_pads.loop1_io[24] ;
+ wire \mprj_pads.loop1_io[25] ;
+ wire \mprj_pads.loop1_io[26] ;
+ wire \mprj_pads.loop1_io[2] ;
+ wire \mprj_pads.loop1_io[3] ;
+ wire \mprj_pads.loop1_io[4] ;
+ wire \mprj_pads.loop1_io[5] ;
+ wire \mprj_pads.loop1_io[6] ;
+ wire \mprj_pads.loop1_io[7] ;
+ wire \mprj_pads.loop1_io[8] ;
+ wire \mprj_pads.loop1_io[9] ;
+ wire \mprj_pads.no_connect_1a[0] ;
+ wire \mprj_pads.no_connect_1a[1] ;
+ wire \mprj_pads.no_connect_1a[2] ;
+ wire \mprj_pads.no_connect_1a[3] ;
+ wire \mprj_pads.no_connect_1a[4] ;
+ wire \mprj_pads.no_connect_1a[5] ;
+ wire \mprj_pads.no_connect_1a[6] ;
+ wire \mprj_pads.no_connect_1b[0] ;
+ wire \mprj_pads.no_connect_1b[1] ;
+ wire \mprj_pads.no_connect_1b[2] ;
+ wire \mprj_pads.no_connect_1b[3] ;
+ wire \mprj_pads.no_connect_1b[4] ;
+ wire \mprj_pads.no_connect_1b[5] ;
+ wire \mprj_pads.no_connect_1b[6] ;
+ wire \mprj_pads.no_connect_2a[0] ;
+ wire \mprj_pads.no_connect_2a[1] ;
+ wire \mprj_pads.no_connect_2b[0] ;
+ wire \mprj_pads.no_connect_2b[1] ;
+ wire \mprj_pads.oeb[0] ;
+ wire \mprj_pads.oeb[10] ;
+ wire \mprj_pads.oeb[11] ;
+ wire \mprj_pads.oeb[12] ;
+ wire \mprj_pads.oeb[13] ;
+ wire \mprj_pads.oeb[14] ;
+ wire \mprj_pads.oeb[15] ;
+ wire \mprj_pads.oeb[16] ;
+ wire \mprj_pads.oeb[17] ;
+ wire \mprj_pads.oeb[18] ;
+ wire \mprj_pads.oeb[19] ;
+ wire \mprj_pads.oeb[1] ;
+ wire \mprj_pads.oeb[20] ;
+ wire \mprj_pads.oeb[21] ;
+ wire \mprj_pads.oeb[22] ;
+ wire \mprj_pads.oeb[23] ;
+ wire \mprj_pads.oeb[24] ;
+ wire \mprj_pads.oeb[25] ;
+ wire \mprj_pads.oeb[26] ;
+ wire \mprj_pads.oeb[2] ;
+ wire \mprj_pads.oeb[3] ;
+ wire \mprj_pads.oeb[4] ;
+ wire \mprj_pads.oeb[5] ;
+ wire \mprj_pads.oeb[6] ;
+ wire \mprj_pads.oeb[7] ;
+ wire \mprj_pads.oeb[8] ;
+ wire \mprj_pads.oeb[9] ;
+ wire \mprj_pads.porb_h ;
+ wire \mprj_pads.slow_sel[0] ;
+ wire \mprj_pads.slow_sel[10] ;
+ wire \mprj_pads.slow_sel[11] ;
+ wire \mprj_pads.slow_sel[12] ;
+ wire \mprj_pads.slow_sel[13] ;
+ wire \mprj_pads.slow_sel[14] ;
+ wire \mprj_pads.slow_sel[15] ;
+ wire \mprj_pads.slow_sel[16] ;
+ wire \mprj_pads.slow_sel[17] ;
+ wire \mprj_pads.slow_sel[18] ;
+ wire \mprj_pads.slow_sel[19] ;
+ wire \mprj_pads.slow_sel[1] ;
+ wire \mprj_pads.slow_sel[20] ;
+ wire \mprj_pads.slow_sel[21] ;
+ wire \mprj_pads.slow_sel[22] ;
+ wire \mprj_pads.slow_sel[23] ;
+ wire \mprj_pads.slow_sel[24] ;
+ wire \mprj_pads.slow_sel[25] ;
+ wire \mprj_pads.slow_sel[26] ;
+ wire \mprj_pads.slow_sel[2] ;
+ wire \mprj_pads.slow_sel[3] ;
+ wire \mprj_pads.slow_sel[4] ;
+ wire \mprj_pads.slow_sel[5] ;
+ wire \mprj_pads.slow_sel[6] ;
+ wire \mprj_pads.slow_sel[7] ;
+ wire \mprj_pads.slow_sel[8] ;
+ wire \mprj_pads.slow_sel[9] ;
+ wire \mprj_pads.vccd ;
+ wire \mprj_pads.vdda ;
+ wire \mprj_pads.vdda1 ;
+ wire \mprj_pads.vdda2 ;
+ wire \mprj_pads.vddio ;
+ wire \mprj_pads.vddio_q ;
+ wire \mprj_pads.vssa ;
+ wire \mprj_pads.vssa1 ;
+ wire \mprj_pads.vssa2 ;
+ wire \mprj_pads.vssd ;
+ wire \mprj_pads.vssio ;
+ wire \mprj_pads.vssio_q ;
+ wire \mprj_pads.vtrip_sel[0] ;
+ wire \mprj_pads.vtrip_sel[10] ;
+ wire \mprj_pads.vtrip_sel[11] ;
+ wire \mprj_pads.vtrip_sel[12] ;
+ wire \mprj_pads.vtrip_sel[13] ;
+ wire \mprj_pads.vtrip_sel[14] ;
+ wire \mprj_pads.vtrip_sel[15] ;
+ wire \mprj_pads.vtrip_sel[16] ;
+ wire \mprj_pads.vtrip_sel[17] ;
+ wire \mprj_pads.vtrip_sel[18] ;
+ wire \mprj_pads.vtrip_sel[19] ;
+ wire \mprj_pads.vtrip_sel[1] ;
+ wire \mprj_pads.vtrip_sel[20] ;
+ wire \mprj_pads.vtrip_sel[21] ;
+ wire \mprj_pads.vtrip_sel[22] ;
+ wire \mprj_pads.vtrip_sel[23] ;
+ wire \mprj_pads.vtrip_sel[24] ;
+ wire \mprj_pads.vtrip_sel[25] ;
+ wire \mprj_pads.vtrip_sel[26] ;
+ wire \mprj_pads.vtrip_sel[2] ;
+ wire \mprj_pads.vtrip_sel[3] ;
+ wire \mprj_pads.vtrip_sel[4] ;
+ wire \mprj_pads.vtrip_sel[5] ;
+ wire \mprj_pads.vtrip_sel[6] ;
+ wire \mprj_pads.vtrip_sel[7] ;
+ wire \mprj_pads.vtrip_sel[8] ;
+ wire \mprj_pads.vtrip_sel[9] ;
+ input por;
+ input porb_h;
+ input resetb;
+ output resetb_core_h;
+ inout vccd;
+ inout vccd1;
+ inout vccd1_pad;
+ inout vccd2;
+ inout vccd2_pad;
+ inout vccd_pad;
+ inout vdda;
+ inout vdda1;
+ inout vdda1_pad;
+ inout vdda1_pad2;
+ inout vdda2;
+ inout vdda2_pad;
+ inout vdda_pad;
+ inout vddio;
+ inout vddio_pad;
+ inout vddio_pad2;
+ wire vddio_q;
+ inout vssa;
+ inout vssa1;
+ inout vssa1_pad;
+ inout vssa1_pad2;
+ inout vssa2;
+ inout vssa2_pad;
+ inout vssa_pad;
+ inout vssd;
+ inout vssd1;
+ inout vssd1_pad;
+ inout vssd2;
+ inout vssd2_pad;
+ inout vssd_pad;
+ inout vssio;
+ inout vssio_pad;
+ inout vssio_pad2;
+ wire vssio_q;
+ wire xresloop;
+ sky130_ef_io__gpiov2_pad_wrapped clock_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vssd, vssd, vccd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_clock),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(clock_core),
+ .INP_DIS(por),
+ .IN_H(),
+ .OE_N(vccd),
+ .OUT(vssd),
+ .PAD(clock),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_clock),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_clk_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_clk),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(loop_flash_clk),
+ .IN_H(),
+ .OE_N(flash_clk_oeb_core),
+ .OUT(flash_clk_core),
+ .PAD(flash_clk),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_clk),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_csb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ vccd, vccd, vssd }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_csb),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(),
+ .INP_DIS(loop_flash_csb),
+ .IN_H(),
+ .OE_N(flash_csb_oeb_core),
+ .OUT(flash_csb_core),
+ .PAD(flash_csb),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_csb),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io0_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io0),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io0_di_core),
+ .INP_DIS(flash_io0_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io0_oeb_core),
+ .OUT(flash_io0_do_core),
+ .PAD(flash_io0),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io0),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped flash_io1_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_flash_io1),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(flash_io1_di_core),
+ .INP_DIS(flash_io1_ieb_core),
+ .IN_H(),
+ .OE_N(flash_io1_oeb_core),
+ .OUT(flash_io1_do_core),
+ .PAD(flash_io1),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_flash_io1),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped gpio_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(vssd),
+ .ANALOG_POL(vssd),
+ .ANALOG_SEL(vssd),
+ .DM({ gpio_mode1_core, gpio_mode1_core, gpio_mode0_core }),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(loop_gpio),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssa),
+ .HLD_H_N(vddio),
+ .HLD_OVR(vssd),
+ .IB_MODE_SEL(vssd),
+ .IN(gpio_in_core),
+ .INP_DIS(gpio_inenb_core),
+ .IN_H(),
+ .OE_N(gpio_outenb_core),
+ .OUT(gpio_out_core),
+ .PAD(gpio),
+ .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(),
+ .SLOW(vssd),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop_gpio),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(vssd)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad \mgmt_corner[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD_PAD(vccd_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDA_PAD(vdda_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_PAD(vddio_pad),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_PAD(vddio_pad2),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSA_PAD(vssa_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSD_PAD(vssd_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_PAD(vssio_pad),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_PAD(vssio_pad2),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[0]),
+ .ANALOG_POL(mprj_io_analog_pol[0]),
+ .ANALOG_SEL(mprj_io_analog_sel[0]),
+ .DM(mprj_io_dm[2:0]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[0] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[0]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[0]),
+ .IN(\mprj_pads.io_in[0] ),
+ .INP_DIS(mprj_io_inp_dis[0]),
+ .IN_H(\mprj_pads.io_in_3v3[0] ),
+ .OE_N(mprj_io_oeb[0]),
+ .OUT(mprj_io_out[0]),
+ .PAD(mprj_io[0]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[0] ),
+ .SLOW(mprj_io_slow_sel[0]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[0] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[0])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[10]),
+ .ANALOG_POL(mprj_io_analog_pol[10]),
+ .ANALOG_SEL(mprj_io_analog_sel[10]),
+ .DM(mprj_io_dm[32:30]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[10] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[10]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[10]),
+ .IN(\mprj_pads.io_in[10] ),
+ .INP_DIS(mprj_io_inp_dis[10]),
+ .IN_H(\mprj_pads.io_in_3v3[10] ),
+ .OE_N(mprj_io_oeb[10]),
+ .OUT(mprj_io_out[10]),
+ .PAD(mprj_io[10]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[3]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[3]),
+ .SLOW(mprj_io_slow_sel[10]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[10] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[10])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[11]),
+ .ANALOG_POL(mprj_io_analog_pol[11]),
+ .ANALOG_SEL(mprj_io_analog_sel[11]),
+ .DM(mprj_io_dm[35:33]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[11] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[11]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[11]),
+ .IN(\mprj_pads.io_in[11] ),
+ .INP_DIS(mprj_io_inp_dis[11]),
+ .IN_H(\mprj_pads.io_in_3v3[11] ),
+ .OE_N(mprj_io_oeb[11]),
+ .OUT(mprj_io_out[11]),
+ .PAD(mprj_io[11]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[4]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[4]),
+ .SLOW(mprj_io_slow_sel[11]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[11] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[11])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[12]),
+ .ANALOG_POL(mprj_io_analog_pol[12]),
+ .ANALOG_SEL(mprj_io_analog_sel[12]),
+ .DM(mprj_io_dm[38:36]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[12] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[12]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[12]),
+ .IN(\mprj_pads.io_in[12] ),
+ .INP_DIS(mprj_io_inp_dis[12]),
+ .IN_H(\mprj_pads.io_in_3v3[12] ),
+ .OE_N(mprj_io_oeb[12]),
+ .OUT(mprj_io_out[12]),
+ .PAD(mprj_io[12]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[5]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[5]),
+ .SLOW(mprj_io_slow_sel[12]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[12] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[12])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[13] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[13]),
+ .ANALOG_POL(mprj_io_analog_pol[13]),
+ .ANALOG_SEL(mprj_io_analog_sel[13]),
+ .DM(mprj_io_dm[41:39]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[13] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[13]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[13]),
+ .IN(\mprj_pads.io_in[13] ),
+ .INP_DIS(mprj_io_inp_dis[13]),
+ .IN_H(\mprj_pads.io_in_3v3[13] ),
+ .OE_N(mprj_io_oeb[13]),
+ .OUT(mprj_io_out[13]),
+ .PAD(mprj_io[13]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[6]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[6]),
+ .SLOW(mprj_io_slow_sel[13]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[13] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[13])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[1]),
+ .ANALOG_POL(mprj_io_analog_pol[1]),
+ .ANALOG_SEL(mprj_io_analog_sel[1]),
+ .DM(mprj_io_dm[5:3]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[1] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[1]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[1]),
+ .IN(\mprj_pads.io_in[1] ),
+ .INP_DIS(mprj_io_inp_dis[1]),
+ .IN_H(\mprj_pads.io_in_3v3[1] ),
+ .OE_N(mprj_io_oeb[1]),
+ .OUT(mprj_io_out[1]),
+ .PAD(mprj_io[1]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[1] ),
+ .SLOW(mprj_io_slow_sel[1]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[1] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[1])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[2]),
+ .ANALOG_POL(mprj_io_analog_pol[2]),
+ .ANALOG_SEL(mprj_io_analog_sel[2]),
+ .DM(mprj_io_dm[8:6]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[2] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[2]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[2]),
+ .IN(\mprj_pads.io_in[2] ),
+ .INP_DIS(mprj_io_inp_dis[2]),
+ .IN_H(\mprj_pads.io_in_3v3[2] ),
+ .OE_N(mprj_io_oeb[2]),
+ .OUT(mprj_io_out[2]),
+ .PAD(mprj_io[2]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[2] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[2] ),
+ .SLOW(mprj_io_slow_sel[2]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[2] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[2])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[3]),
+ .ANALOG_POL(mprj_io_analog_pol[3]),
+ .ANALOG_SEL(mprj_io_analog_sel[3]),
+ .DM(mprj_io_dm[11:9]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[3] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[3]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[3]),
+ .IN(\mprj_pads.io_in[3] ),
+ .INP_DIS(mprj_io_inp_dis[3]),
+ .IN_H(\mprj_pads.io_in_3v3[3] ),
+ .OE_N(mprj_io_oeb[3]),
+ .OUT(mprj_io_out[3]),
+ .PAD(mprj_io[3]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[3] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[3] ),
+ .SLOW(mprj_io_slow_sel[3]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[3] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[3])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[4]),
+ .ANALOG_POL(mprj_io_analog_pol[4]),
+ .ANALOG_SEL(mprj_io_analog_sel[4]),
+ .DM(mprj_io_dm[14:12]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[4] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[4]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[4]),
+ .IN(\mprj_pads.io_in[4] ),
+ .INP_DIS(mprj_io_inp_dis[4]),
+ .IN_H(\mprj_pads.io_in_3v3[4] ),
+ .OE_N(mprj_io_oeb[4]),
+ .OUT(mprj_io_out[4]),
+ .PAD(mprj_io[4]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[4] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[4] ),
+ .SLOW(mprj_io_slow_sel[4]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[4] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[4])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[5]),
+ .ANALOG_POL(mprj_io_analog_pol[5]),
+ .ANALOG_SEL(mprj_io_analog_sel[5]),
+ .DM(mprj_io_dm[17:15]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[5] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[5]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[5]),
+ .IN(\mprj_pads.io_in[5] ),
+ .INP_DIS(mprj_io_inp_dis[5]),
+ .IN_H(\mprj_pads.io_in_3v3[5] ),
+ .OE_N(mprj_io_oeb[5]),
+ .OUT(mprj_io_out[5]),
+ .PAD(mprj_io[5]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[5] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[5] ),
+ .SLOW(mprj_io_slow_sel[5]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[5] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[5])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[6]),
+ .ANALOG_POL(mprj_io_analog_pol[6]),
+ .ANALOG_SEL(mprj_io_analog_sel[6]),
+ .DM(mprj_io_dm[20:18]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[6] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[6]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[6]),
+ .IN(\mprj_pads.io_in[6] ),
+ .INP_DIS(mprj_io_inp_dis[6]),
+ .IN_H(\mprj_pads.io_in_3v3[6] ),
+ .OE_N(mprj_io_oeb[6]),
+ .OUT(mprj_io_out[6]),
+ .PAD(mprj_io[6]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_1b[6] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_1a[6] ),
+ .SLOW(mprj_io_slow_sel[6]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[6] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[6])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[7]),
+ .ANALOG_POL(mprj_io_analog_pol[7]),
+ .ANALOG_SEL(mprj_io_analog_sel[7]),
+ .DM(mprj_io_dm[23:21]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[7] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[7]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[7]),
+ .IN(\mprj_pads.io_in[7] ),
+ .INP_DIS(mprj_io_inp_dis[7]),
+ .IN_H(\mprj_pads.io_in_3v3[7] ),
+ .OE_N(mprj_io_oeb[7]),
+ .OUT(mprj_io_out[7]),
+ .PAD(mprj_io[7]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[0]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[0]),
+ .SLOW(mprj_io_slow_sel[7]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[7] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[7])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[8]),
+ .ANALOG_POL(mprj_io_analog_pol[8]),
+ .ANALOG_SEL(mprj_io_analog_sel[8]),
+ .DM(mprj_io_dm[26:24]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[8] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[8]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[8]),
+ .IN(\mprj_pads.io_in[8] ),
+ .INP_DIS(mprj_io_inp_dis[8]),
+ .IN_H(\mprj_pads.io_in_3v3[8] ),
+ .OE_N(mprj_io_oeb[8]),
+ .OUT(mprj_io_out[8]),
+ .PAD(mprj_io[8]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[1]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[1]),
+ .SLOW(mprj_io_slow_sel[8]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[8] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[8])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[9]),
+ .ANALOG_POL(mprj_io_analog_pol[9]),
+ .ANALOG_SEL(mprj_io_analog_sel[9]),
+ .DM(mprj_io_dm[29:27]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[9] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[9]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[9]),
+ .IN(\mprj_pads.io_in[9] ),
+ .INP_DIS(mprj_io_inp_dis[9]),
+ .IN_H(\mprj_pads.io_in_3v3[9] ),
+ .OE_N(mprj_io_oeb[9]),
+ .OUT(mprj_io_out[9]),
+ .PAD(mprj_io[9]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[2]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[2]),
+ .SLOW(mprj_io_slow_sel[9]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[9] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[9])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[14]),
+ .ANALOG_POL(mprj_io_analog_pol[14]),
+ .ANALOG_SEL(mprj_io_analog_sel[14]),
+ .DM(mprj_io_dm[44:42]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[14] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[14]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[14]),
+ .IN(\mprj_pads.io_in[14] ),
+ .INP_DIS(mprj_io_inp_dis[14]),
+ .IN_H(\mprj_pads.io_in_3v3[14] ),
+ .OE_N(mprj_io_oeb[14]),
+ .OUT(mprj_io_out[14]),
+ .PAD(mprj_io[25]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[7]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[7]),
+ .SLOW(mprj_io_slow_sel[14]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[14] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[14])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[10] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[24]),
+ .ANALOG_POL(mprj_io_analog_pol[24]),
+ .ANALOG_SEL(mprj_io_analog_sel[24]),
+ .DM(mprj_io_dm[74:72]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[24] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[24]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[24]),
+ .IN(\mprj_pads.io_in[24] ),
+ .INP_DIS(mprj_io_inp_dis[24]),
+ .IN_H(\mprj_pads.io_in_3v3[24] ),
+ .OE_N(mprj_io_oeb[24]),
+ .OUT(mprj_io_out[24]),
+ .PAD(mprj_io[35]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[17]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[17]),
+ .SLOW(mprj_io_slow_sel[24]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[24] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[24])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[11] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[25]),
+ .ANALOG_POL(mprj_io_analog_pol[25]),
+ .ANALOG_SEL(mprj_io_analog_sel[25]),
+ .DM(mprj_io_dm[77:75]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[25] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[25]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[25]),
+ .IN(\mprj_pads.io_in[25] ),
+ .INP_DIS(mprj_io_inp_dis[25]),
+ .IN_H(\mprj_pads.io_in_3v3[25] ),
+ .OE_N(mprj_io_oeb[25]),
+ .OUT(mprj_io_out[25]),
+ .PAD(mprj_io[36]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_2b[0] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_2a[0] ),
+ .SLOW(mprj_io_slow_sel[25]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[25] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[25])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[12] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[26]),
+ .ANALOG_POL(mprj_io_analog_pol[26]),
+ .ANALOG_SEL(mprj_io_analog_sel[26]),
+ .DM(mprj_io_dm[80:78]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[26] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[26]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[26]),
+ .IN(\mprj_pads.io_in[26] ),
+ .INP_DIS(mprj_io_inp_dis[26]),
+ .IN_H(\mprj_pads.io_in_3v3[26] ),
+ .OE_N(mprj_io_oeb[26]),
+ .OUT(mprj_io_out[26]),
+ .PAD(mprj_io[37]),
+ .PAD_A_ESD_0_H(\mprj_pads.no_connect_2b[1] ),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(\mprj_pads.no_connect_2a[1] ),
+ .SLOW(mprj_io_slow_sel[26]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[26] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[26])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[15]),
+ .ANALOG_POL(mprj_io_analog_pol[15]),
+ .ANALOG_SEL(mprj_io_analog_sel[15]),
+ .DM(mprj_io_dm[47:45]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[15] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[15]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[15]),
+ .IN(\mprj_pads.io_in[15] ),
+ .INP_DIS(mprj_io_inp_dis[15]),
+ .IN_H(\mprj_pads.io_in_3v3[15] ),
+ .OE_N(mprj_io_oeb[15]),
+ .OUT(mprj_io_out[15]),
+ .PAD(mprj_io[26]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[8]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[8]),
+ .SLOW(mprj_io_slow_sel[15]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[15] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[15])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[16]),
+ .ANALOG_POL(mprj_io_analog_pol[16]),
+ .ANALOG_SEL(mprj_io_analog_sel[16]),
+ .DM(mprj_io_dm[50:48]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[16] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[16]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[16]),
+ .IN(\mprj_pads.io_in[16] ),
+ .INP_DIS(mprj_io_inp_dis[16]),
+ .IN_H(\mprj_pads.io_in_3v3[16] ),
+ .OE_N(mprj_io_oeb[16]),
+ .OUT(mprj_io_out[16]),
+ .PAD(mprj_io[27]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[9]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[9]),
+ .SLOW(mprj_io_slow_sel[16]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[16] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[16])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[17]),
+ .ANALOG_POL(mprj_io_analog_pol[17]),
+ .ANALOG_SEL(mprj_io_analog_sel[17]),
+ .DM(mprj_io_dm[53:51]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[17] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[17]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[17]),
+ .IN(\mprj_pads.io_in[17] ),
+ .INP_DIS(mprj_io_inp_dis[17]),
+ .IN_H(\mprj_pads.io_in_3v3[17] ),
+ .OE_N(mprj_io_oeb[17]),
+ .OUT(mprj_io_out[17]),
+ .PAD(mprj_io[28]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[10]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[10]),
+ .SLOW(mprj_io_slow_sel[17]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[17] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[17])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[4] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[18]),
+ .ANALOG_POL(mprj_io_analog_pol[18]),
+ .ANALOG_SEL(mprj_io_analog_sel[18]),
+ .DM(mprj_io_dm[56:54]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[18] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[18]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[18]),
+ .IN(\mprj_pads.io_in[18] ),
+ .INP_DIS(mprj_io_inp_dis[18]),
+ .IN_H(\mprj_pads.io_in_3v3[18] ),
+ .OE_N(mprj_io_oeb[18]),
+ .OUT(mprj_io_out[18]),
+ .PAD(mprj_io[29]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[11]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[11]),
+ .SLOW(mprj_io_slow_sel[18]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[18] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[18])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[5] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[19]),
+ .ANALOG_POL(mprj_io_analog_pol[19]),
+ .ANALOG_SEL(mprj_io_analog_sel[19]),
+ .DM(mprj_io_dm[59:57]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[19] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[19]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[19]),
+ .IN(\mprj_pads.io_in[19] ),
+ .INP_DIS(mprj_io_inp_dis[19]),
+ .IN_H(\mprj_pads.io_in_3v3[19] ),
+ .OE_N(mprj_io_oeb[19]),
+ .OUT(mprj_io_out[19]),
+ .PAD(mprj_io[30]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[12]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[12]),
+ .SLOW(mprj_io_slow_sel[19]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[19] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[19])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[6] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[20]),
+ .ANALOG_POL(mprj_io_analog_pol[20]),
+ .ANALOG_SEL(mprj_io_analog_sel[20]),
+ .DM(mprj_io_dm[62:60]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[20] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[20]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[20]),
+ .IN(\mprj_pads.io_in[20] ),
+ .INP_DIS(mprj_io_inp_dis[20]),
+ .IN_H(\mprj_pads.io_in_3v3[20] ),
+ .OE_N(mprj_io_oeb[20]),
+ .OUT(mprj_io_out[20]),
+ .PAD(mprj_io[31]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[13]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[13]),
+ .SLOW(mprj_io_slow_sel[20]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[20] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[20])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[7] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[21]),
+ .ANALOG_POL(mprj_io_analog_pol[21]),
+ .ANALOG_SEL(mprj_io_analog_sel[21]),
+ .DM(mprj_io_dm[65:63]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[21] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[21]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[21]),
+ .IN(\mprj_pads.io_in[21] ),
+ .INP_DIS(mprj_io_inp_dis[21]),
+ .IN_H(\mprj_pads.io_in_3v3[21] ),
+ .OE_N(mprj_io_oeb[21]),
+ .OUT(mprj_io_out[21]),
+ .PAD(mprj_io[32]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[14]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[14]),
+ .SLOW(mprj_io_slow_sel[21]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[21] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[21])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[8] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[22]),
+ .ANALOG_POL(mprj_io_analog_pol[22]),
+ .ANALOG_SEL(mprj_io_analog_sel[22]),
+ .DM(mprj_io_dm[68:66]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[22] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[22]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[22]),
+ .IN(\mprj_pads.io_in[22] ),
+ .INP_DIS(mprj_io_inp_dis[22]),
+ .IN_H(\mprj_pads.io_in_3v3[22] ),
+ .OE_N(mprj_io_oeb[22]),
+ .OUT(mprj_io_out[22]),
+ .PAD(mprj_io[33]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[15]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[15]),
+ .SLOW(mprj_io_slow_sel[22]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[22] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[22])
+ );
+ sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[9] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .ANALOG_EN(mprj_io_analog_en[23]),
+ .ANALOG_POL(mprj_io_analog_pol[23]),
+ .ANALOG_SEL(mprj_io_analog_sel[23]),
+ .DM(mprj_io_dm[71:69]),
+ .ENABLE_H(porb_h),
+ .ENABLE_INP_H(\mprj_pads.loop1_io[23] ),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .ENABLE_VSWITCH_H(vssio),
+ .HLD_H_N(vddio),
+ .HLD_OVR(mprj_io_holdover[23]),
+ .IB_MODE_SEL(mprj_io_ib_mode_sel[23]),
+ .IN(\mprj_pads.io_in[23] ),
+ .INP_DIS(mprj_io_inp_dis[23]),
+ .IN_H(\mprj_pads.io_in_3v3[23] ),
+ .OE_N(mprj_io_oeb[23]),
+ .OUT(mprj_io_out[23]),
+ .PAD(mprj_io[34]),
+ .PAD_A_ESD_0_H(mprj_gpio_analog[16]),
+ .PAD_A_ESD_1_H(),
+ .PAD_A_NOESD_H(mprj_gpio_noesd[16]),
+ .SLOW(mprj_io_slow_sel[23]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(\mprj_pads.loop1_io[23] ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .VTRIP_SEL(mprj_io_vtrip_sel[23])
+ );
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DISABLE_PULLUP_H(vssio),
+ .ENABLE_H(porb_h),
+ .ENABLE_VDDIO(vccd),
+ .EN_VDDIO_SIG_H(vssio),
+ .FILT_IN_H(vssio),
+ .INP_SEL_H(vssio),
+ .PAD(resetb),
+ .PAD_A_ESD_H(xresloop),
+ .PULLUP_H(vssio),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .TIE_WEAK_HI_H(xresloop),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio),
+ .XRES_H_N(resetb_core_h)
+ );
+ sky130_ef_io__analog_pad \user1_analog_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[0]),
+ .P_PAD(mprj_io[14]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user1_analog_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[1]),
+ .P_PAD(mprj_io[15]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user1_analog_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[2]),
+ .P_PAD(mprj_io[16]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user1_analog_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[3]),
+ .P_PAD(mprj_io[17]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__top_power_hvc user1_analog_pad_with_clamp (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DRN_HVC(mprj_clamp_high[0]),
+ .P_CORE(mprj_analog[4]),
+ .P_PAD(mprj_io[18]),
+ .SRC_BDY_HVC(mprj_clamp_low[0]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad user1_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd1),
+ .VCCD_PAD(vccd1_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSD1(vssd1),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDA_PAD(vdda1_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDA_PAD(vdda1_pad2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSA_PAD(vssa1_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSA_PAD(vssa1_pad2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd1),
+ .VCCHIB(vccd),
+ .VDDA(vdda1),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa1),
+ .VSSD(vssd),
+ .VSSD1(vssd1),
+ .VSSD_PAD(vssd1_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user2_analog_pad[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[7]),
+ .P_PAD(mprj_io[21]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user2_analog_pad[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[8]),
+ .P_PAD(mprj_io[22]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user2_analog_pad[2] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[9]),
+ .P_PAD(mprj_io[23]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__analog_pad \user2_analog_pad[3] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .P_CORE(mprj_analog[10]),
+ .P_PAD(mprj_io[24]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__top_power_hvc \user2_analog_pad_with_clamp[0] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DRN_HVC(mprj_clamp_high[1]),
+ .P_CORE(mprj_analog[5]),
+ .P_PAD(mprj_io[19]),
+ .SRC_BDY_HVC(mprj_clamp_low[1]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__top_power_hvc \user2_analog_pad_with_clamp[1] (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .DRN_HVC(mprj_clamp_high[2]),
+ .P_CORE(mprj_analog[6]),
+ .P_PAD(mprj_io[20]),
+ .SRC_BDY_HVC(mprj_clamp_low[2]),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__corner_pad user2_corner (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd2),
+ .VCCD_PAD(vccd2_pad),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSD1(vssd2),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDA_PAD(vdda2_pad),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSA_PAD(vssa2_pad),
+ .VSSD(vssd),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
+ .AMUXBUS_A(\mprj_pads.analog_a ),
+ .AMUXBUS_B(\mprj_pads.analog_b ),
+ .VCCD(vccd),
+ .VCCD1(vccd2),
+ .VCCHIB(vccd),
+ .VDDA(vdda2),
+ .VDDIO(vddio),
+ .VDDIO_Q(\mprj_pads.vddio_q ),
+ .VSSA(vssa2),
+ .VSSD(vssd),
+ .VSSD1(vssd2),
+ .VSSD_PAD(vssd2_pad),
+ .VSSIO(vssio),
+ .VSSIO_Q(\mprj_pads.vssio_q ),
+ .VSWITCH(vddio)
+ );
+ assign \mprj_io_enh[1] = porb_h;
+ assign \mprj_io_enh[0] = porb_h;
+ assign \flash_io1_mode[2] = flash_io1_ieb_core;
+ assign \flash_io1_mode[1] = flash_io1_ieb_core;
+ assign \flash_io1_mode[0] = flash_io1_oeb_core;
+ assign \mprj_io_hldh_n[26] = vddio;
+ assign \mprj_io_hldh_n[25] = vddio;
+ assign \mprj_io_hldh_n[24] = vddio;
+ assign \mprj_io_hldh_n[23] = vddio;
+ assign \mprj_io_hldh_n[22] = vddio;
+ assign \mprj_io_hldh_n[21] = vddio;
+ assign \mprj_io_hldh_n[20] = vddio;
+ assign \mprj_io_hldh_n[19] = vddio;
+ assign \mprj_io_hldh_n[18] = vddio;
+ assign \mprj_io_hldh_n[17] = vddio;
+ assign \mprj_io_hldh_n[16] = vddio;
+ assign \mprj_io_hldh_n[15] = vddio;
+ assign \mprj_io_hldh_n[14] = vddio;
+ assign \mprj_io_hldh_n[13] = vddio;
+ assign \mprj_io_hldh_n[12] = vddio;
+ assign \mprj_io_hldh_n[11] = vddio;
+ assign \mprj_io_hldh_n[10] = vddio;
+ assign \mprj_io_hldh_n[9] = vddio;
+ assign \mprj_io_hldh_n[8] = vddio;
+ assign \mprj_io_hldh_n[7] = vddio;
+ assign \mprj_io_hldh_n[6] = vddio;
+ assign \mprj_io_hldh_n[5] = vddio;
+ assign \mprj_io_hldh_n[4] = vddio;
+ assign \mprj_io_hldh_n[3] = vddio;
+ assign \mprj_io_hldh_n[2] = vddio;
+ assign \mprj_io_hldh_n[1] = vddio;
+ assign \mprj_io_hldh_n[0] = vddio;
+ assign \mprj_pads.vtrip_sel[26] = mprj_io_vtrip_sel[26];
+ assign \mprj_pads.vtrip_sel[25] = mprj_io_vtrip_sel[25];
+ assign \mprj_pads.vtrip_sel[24] = mprj_io_vtrip_sel[24];
+ assign \mprj_pads.vtrip_sel[23] = mprj_io_vtrip_sel[23];
+ assign \mprj_pads.vtrip_sel[22] = mprj_io_vtrip_sel[22];
+ assign \mprj_pads.vtrip_sel[21] = mprj_io_vtrip_sel[21];
+ assign \mprj_pads.vtrip_sel[20] = mprj_io_vtrip_sel[20];
+ assign \mprj_pads.vtrip_sel[19] = mprj_io_vtrip_sel[19];
+ assign \mprj_pads.vtrip_sel[18] = mprj_io_vtrip_sel[18];
+ assign \mprj_pads.vtrip_sel[17] = mprj_io_vtrip_sel[17];
+ assign \mprj_pads.vtrip_sel[16] = mprj_io_vtrip_sel[16];
+ assign \mprj_pads.vtrip_sel[15] = mprj_io_vtrip_sel[15];
+ assign \mprj_pads.vtrip_sel[14] = mprj_io_vtrip_sel[14];
+ assign \mprj_pads.vtrip_sel[13] = mprj_io_vtrip_sel[13];
+ assign \mprj_pads.vtrip_sel[12] = mprj_io_vtrip_sel[12];
+ assign \mprj_pads.vtrip_sel[11] = mprj_io_vtrip_sel[11];
+ assign \mprj_pads.vtrip_sel[10] = mprj_io_vtrip_sel[10];
+ assign \mprj_pads.vtrip_sel[9] = mprj_io_vtrip_sel[9];
+ assign \mprj_pads.vtrip_sel[8] = mprj_io_vtrip_sel[8];
+ assign \mprj_pads.vtrip_sel[7] = mprj_io_vtrip_sel[7];
+ assign \mprj_pads.vtrip_sel[6] = mprj_io_vtrip_sel[6];
+ assign \mprj_pads.vtrip_sel[5] = mprj_io_vtrip_sel[5];
+ assign \mprj_pads.vtrip_sel[4] = mprj_io_vtrip_sel[4];
+ assign \mprj_pads.vtrip_sel[3] = mprj_io_vtrip_sel[3];
+ assign \mprj_pads.vtrip_sel[2] = mprj_io_vtrip_sel[2];
+ assign \mprj_pads.vtrip_sel[1] = mprj_io_vtrip_sel[1];
+ assign \mprj_pads.vtrip_sel[0] = mprj_io_vtrip_sel[0];
+ assign \mprj_pads.holdover[26] = mprj_io_holdover[26];
+ assign \mprj_pads.holdover[25] = mprj_io_holdover[25];
+ assign \mprj_pads.holdover[24] = mprj_io_holdover[24];
+ assign \mprj_pads.holdover[23] = mprj_io_holdover[23];
+ assign \mprj_pads.holdover[22] = mprj_io_holdover[22];
+ assign \mprj_pads.holdover[21] = mprj_io_holdover[21];
+ assign \mprj_pads.holdover[20] = mprj_io_holdover[20];
+ assign \mprj_pads.holdover[19] = mprj_io_holdover[19];
+ assign \mprj_pads.holdover[18] = mprj_io_holdover[18];
+ assign \mprj_pads.holdover[17] = mprj_io_holdover[17];
+ assign \mprj_pads.holdover[16] = mprj_io_holdover[16];
+ assign \mprj_pads.holdover[15] = mprj_io_holdover[15];
+ assign \mprj_pads.holdover[14] = mprj_io_holdover[14];
+ assign \mprj_pads.holdover[13] = mprj_io_holdover[13];
+ assign \mprj_pads.holdover[12] = mprj_io_holdover[12];
+ assign \mprj_pads.holdover[11] = mprj_io_holdover[11];
+ assign \mprj_pads.holdover[10] = mprj_io_holdover[10];
+ assign \mprj_pads.holdover[9] = mprj_io_holdover[9];
+ assign \mprj_pads.holdover[8] = mprj_io_holdover[8];
+ assign \mprj_pads.holdover[7] = mprj_io_holdover[7];
+ assign \mprj_pads.holdover[6] = mprj_io_holdover[6];
+ assign \mprj_pads.holdover[5] = mprj_io_holdover[5];
+ assign \mprj_pads.holdover[4] = mprj_io_holdover[4];
+ assign \mprj_pads.holdover[3] = mprj_io_holdover[3];
+ assign \mprj_pads.holdover[2] = mprj_io_holdover[2];
+ assign \mprj_pads.holdover[1] = mprj_io_holdover[1];
+ assign \mprj_pads.holdover[0] = mprj_io_holdover[0];
+ assign \mprj_pads.hldh_n[26] = vddio;
+ assign \mprj_pads.hldh_n[25] = vddio;
+ assign \mprj_pads.hldh_n[24] = vddio;
+ assign \mprj_pads.hldh_n[23] = vddio;
+ assign \mprj_pads.hldh_n[22] = vddio;
+ assign \mprj_pads.hldh_n[21] = vddio;
+ assign \mprj_pads.hldh_n[20] = vddio;
+ assign \mprj_pads.hldh_n[19] = vddio;
+ assign \mprj_pads.hldh_n[18] = vddio;
+ assign \mprj_pads.hldh_n[17] = vddio;
+ assign \mprj_pads.hldh_n[16] = vddio;
+ assign \mprj_pads.hldh_n[15] = vddio;
+ assign \mprj_pads.hldh_n[14] = vddio;
+ assign \mprj_pads.hldh_n[13] = vddio;
+ assign \mprj_pads.hldh_n[12] = vddio;
+ assign \mprj_pads.hldh_n[11] = vddio;
+ assign \mprj_pads.hldh_n[10] = vddio;
+ assign \mprj_pads.hldh_n[9] = vddio;
+ assign \mprj_pads.hldh_n[8] = vddio;
+ assign \mprj_pads.hldh_n[7] = vddio;
+ assign \mprj_pads.hldh_n[6] = vddio;
+ assign \mprj_pads.hldh_n[5] = vddio;
+ assign \mprj_pads.hldh_n[4] = vddio;
+ assign \mprj_pads.hldh_n[3] = vddio;
+ assign \mprj_pads.hldh_n[2] = vddio;
+ assign \mprj_pads.hldh_n[1] = vddio;
+ assign \mprj_pads.hldh_n[0] = vddio;
+ assign \mprj_pads.analog_en[26] = mprj_io_analog_en[26];
+ assign \mprj_pads.analog_en[25] = mprj_io_analog_en[25];
+ assign \mprj_pads.analog_en[24] = mprj_io_analog_en[24];
+ assign \mprj_pads.analog_en[23] = mprj_io_analog_en[23];
+ assign \mprj_pads.analog_en[22] = mprj_io_analog_en[22];
+ assign \mprj_pads.analog_en[21] = mprj_io_analog_en[21];
+ assign \mprj_pads.analog_en[20] = mprj_io_analog_en[20];
+ assign \mprj_pads.analog_en[19] = mprj_io_analog_en[19];
+ assign \mprj_pads.analog_en[18] = mprj_io_analog_en[18];
+ assign \mprj_pads.analog_en[17] = mprj_io_analog_en[17];
+ assign \mprj_pads.analog_en[16] = mprj_io_analog_en[16];
+ assign \mprj_pads.analog_en[15] = mprj_io_analog_en[15];
+ assign \mprj_pads.analog_en[14] = mprj_io_analog_en[14];
+ assign \mprj_pads.analog_en[13] = mprj_io_analog_en[13];
+ assign \mprj_pads.analog_en[12] = mprj_io_analog_en[12];
+ assign \mprj_pads.analog_en[11] = mprj_io_analog_en[11];
+ assign \mprj_pads.analog_en[10] = mprj_io_analog_en[10];
+ assign \mprj_pads.analog_en[9] = mprj_io_analog_en[9];
+ assign \mprj_pads.analog_en[8] = mprj_io_analog_en[8];
+ assign \mprj_pads.analog_en[7] = mprj_io_analog_en[7];
+ assign \mprj_pads.analog_en[6] = mprj_io_analog_en[6];
+ assign \mprj_pads.analog_en[5] = mprj_io_analog_en[5];
+ assign \mprj_pads.analog_en[4] = mprj_io_analog_en[4];
+ assign \mprj_pads.analog_en[3] = mprj_io_analog_en[3];
+ assign \mprj_pads.analog_en[2] = mprj_io_analog_en[2];
+ assign \mprj_pads.analog_en[1] = mprj_io_analog_en[1];
+ assign \mprj_pads.analog_en[0] = mprj_io_analog_en[0];
+ assign \mprj_pads.oeb[26] = mprj_io_oeb[26];
+ assign \mprj_pads.oeb[25] = mprj_io_oeb[25];
+ assign \mprj_pads.oeb[24] = mprj_io_oeb[24];
+ assign \mprj_pads.oeb[23] = mprj_io_oeb[23];
+ assign \mprj_pads.oeb[22] = mprj_io_oeb[22];
+ assign \mprj_pads.oeb[21] = mprj_io_oeb[21];
+ assign \mprj_pads.oeb[20] = mprj_io_oeb[20];
+ assign \mprj_pads.oeb[19] = mprj_io_oeb[19];
+ assign \mprj_pads.oeb[18] = mprj_io_oeb[18];
+ assign \mprj_pads.oeb[17] = mprj_io_oeb[17];
+ assign \mprj_pads.oeb[16] = mprj_io_oeb[16];
+ assign \mprj_pads.oeb[15] = mprj_io_oeb[15];
+ assign \mprj_pads.oeb[14] = mprj_io_oeb[14];
+ assign \mprj_pads.oeb[13] = mprj_io_oeb[13];
+ assign \mprj_pads.oeb[12] = mprj_io_oeb[12];
+ assign \mprj_pads.oeb[11] = mprj_io_oeb[11];
+ assign \mprj_pads.oeb[10] = mprj_io_oeb[10];
+ assign \mprj_pads.oeb[9] = mprj_io_oeb[9];
+ assign \mprj_pads.oeb[8] = mprj_io_oeb[8];
+ assign \mprj_pads.oeb[7] = mprj_io_oeb[7];
+ assign \mprj_pads.oeb[6] = mprj_io_oeb[6];
+ assign \mprj_pads.oeb[5] = mprj_io_oeb[5];
+ assign \mprj_pads.oeb[4] = mprj_io_oeb[4];
+ assign \mprj_pads.oeb[3] = mprj_io_oeb[3];
+ assign \mprj_pads.oeb[2] = mprj_io_oeb[2];
+ assign \mprj_pads.oeb[1] = mprj_io_oeb[1];
+ assign \mprj_pads.oeb[0] = mprj_io_oeb[0];
+ assign \mprj_pads.analog_noesd_io[17] = mprj_gpio_noesd[17];
+ assign \mprj_pads.analog_noesd_io[16] = mprj_gpio_noesd[16];
+ assign \mprj_pads.analog_noesd_io[15] = mprj_gpio_noesd[15];
+ assign \mprj_pads.analog_noesd_io[14] = mprj_gpio_noesd[14];
+ assign \mprj_pads.analog_noesd_io[13] = mprj_gpio_noesd[13];
+ assign \mprj_pads.analog_noesd_io[12] = mprj_gpio_noesd[12];
+ assign \mprj_pads.analog_noesd_io[11] = mprj_gpio_noesd[11];
+ assign \mprj_pads.analog_noesd_io[10] = mprj_gpio_noesd[10];
+ assign \mprj_pads.analog_noesd_io[9] = mprj_gpio_noesd[9];
+ assign \mprj_pads.analog_noesd_io[8] = mprj_gpio_noesd[8];
+ assign \mprj_pads.analog_noesd_io[7] = mprj_gpio_noesd[7];
+ assign \mprj_pads.analog_noesd_io[6] = mprj_gpio_noesd[6];
+ assign \mprj_pads.analog_noesd_io[5] = mprj_gpio_noesd[5];
+ assign \mprj_pads.analog_noesd_io[4] = mprj_gpio_noesd[4];
+ assign \mprj_pads.analog_noesd_io[3] = mprj_gpio_noesd[3];
+ assign \mprj_pads.analog_noesd_io[2] = mprj_gpio_noesd[2];
+ assign \mprj_pads.analog_noesd_io[1] = mprj_gpio_noesd[1];
+ assign \mprj_pads.analog_noesd_io[0] = mprj_gpio_noesd[0];
+ assign \flash_io0_mode[2] = flash_io0_ieb_core;
+ assign \flash_io0_mode[1] = flash_io0_ieb_core;
+ assign \flash_io0_mode[0] = flash_io0_oeb_core;
+ assign \mprj_pads.slow_sel[26] = mprj_io_slow_sel[26];
+ assign \mprj_pads.slow_sel[25] = mprj_io_slow_sel[25];
+ assign \mprj_pads.slow_sel[24] = mprj_io_slow_sel[24];
+ assign \mprj_pads.slow_sel[23] = mprj_io_slow_sel[23];
+ assign \mprj_pads.slow_sel[22] = mprj_io_slow_sel[22];
+ assign \mprj_pads.slow_sel[21] = mprj_io_slow_sel[21];
+ assign \mprj_pads.slow_sel[20] = mprj_io_slow_sel[20];
+ assign \mprj_pads.slow_sel[19] = mprj_io_slow_sel[19];
+ assign \mprj_pads.slow_sel[18] = mprj_io_slow_sel[18];
+ assign \mprj_pads.slow_sel[17] = mprj_io_slow_sel[17];
+ assign \mprj_pads.slow_sel[16] = mprj_io_slow_sel[16];
+ assign \mprj_pads.slow_sel[15] = mprj_io_slow_sel[15];
+ assign \mprj_pads.slow_sel[14] = mprj_io_slow_sel[14];
+ assign \mprj_pads.slow_sel[13] = mprj_io_slow_sel[13];
+ assign \mprj_pads.slow_sel[12] = mprj_io_slow_sel[12];
+ assign \mprj_pads.slow_sel[11] = mprj_io_slow_sel[11];
+ assign \mprj_pads.slow_sel[10] = mprj_io_slow_sel[10];
+ assign \mprj_pads.slow_sel[9] = mprj_io_slow_sel[9];
+ assign \mprj_pads.slow_sel[8] = mprj_io_slow_sel[8];
+ assign \mprj_pads.slow_sel[7] = mprj_io_slow_sel[7];
+ assign \mprj_pads.slow_sel[6] = mprj_io_slow_sel[6];
+ assign \mprj_pads.slow_sel[5] = mprj_io_slow_sel[5];
+ assign \mprj_pads.slow_sel[4] = mprj_io_slow_sel[4];
+ assign \mprj_pads.slow_sel[3] = mprj_io_slow_sel[3];
+ assign \mprj_pads.slow_sel[2] = mprj_io_slow_sel[2];
+ assign \mprj_pads.slow_sel[1] = mprj_io_slow_sel[1];
+ assign \mprj_pads.slow_sel[0] = mprj_io_slow_sel[0];
+ assign \mprj_pads.dm[80] = mprj_io_dm[80];
+ assign \mprj_pads.dm[79] = mprj_io_dm[79];
+ assign \mprj_pads.dm[78] = mprj_io_dm[78];
+ assign \mprj_pads.dm[77] = mprj_io_dm[77];
+ assign \mprj_pads.dm[76] = mprj_io_dm[76];
+ assign \mprj_pads.dm[75] = mprj_io_dm[75];
+ assign \mprj_pads.dm[74] = mprj_io_dm[74];
+ assign \mprj_pads.dm[73] = mprj_io_dm[73];
+ assign \mprj_pads.dm[72] = mprj_io_dm[72];
+ assign \mprj_pads.dm[71] = mprj_io_dm[71];
+ assign \mprj_pads.dm[70] = mprj_io_dm[70];
+ assign \mprj_pads.dm[69] = mprj_io_dm[69];
+ assign \mprj_pads.dm[68] = mprj_io_dm[68];
+ assign \mprj_pads.dm[67] = mprj_io_dm[67];
+ assign \mprj_pads.dm[66] = mprj_io_dm[66];
+ assign \mprj_pads.dm[65] = mprj_io_dm[65];
+ assign \mprj_pads.dm[64] = mprj_io_dm[64];
+ assign \mprj_pads.dm[63] = mprj_io_dm[63];
+ assign \mprj_pads.dm[62] = mprj_io_dm[62];
+ assign \mprj_pads.dm[61] = mprj_io_dm[61];
+ assign \mprj_pads.dm[60] = mprj_io_dm[60];
+ assign \mprj_pads.dm[59] = mprj_io_dm[59];
+ assign \mprj_pads.dm[58] = mprj_io_dm[58];
+ assign \mprj_pads.dm[57] = mprj_io_dm[57];
+ assign \mprj_pads.dm[56] = mprj_io_dm[56];
+ assign \mprj_pads.dm[55] = mprj_io_dm[55];
+ assign \mprj_pads.dm[54] = mprj_io_dm[54];
+ assign \mprj_pads.dm[53] = mprj_io_dm[53];
+ assign \mprj_pads.dm[52] = mprj_io_dm[52];
+ assign \mprj_pads.dm[51] = mprj_io_dm[51];
+ assign \mprj_pads.dm[50] = mprj_io_dm[50];
+ assign \mprj_pads.dm[49] = mprj_io_dm[49];
+ assign \mprj_pads.dm[48] = mprj_io_dm[48];
+ assign \mprj_pads.dm[47] = mprj_io_dm[47];
+ assign \mprj_pads.dm[46] = mprj_io_dm[46];
+ assign \mprj_pads.dm[45] = mprj_io_dm[45];
+ assign \mprj_pads.dm[44] = mprj_io_dm[44];
+ assign \mprj_pads.dm[43] = mprj_io_dm[43];
+ assign \mprj_pads.dm[42] = mprj_io_dm[42];
+ assign \mprj_pads.dm[41] = mprj_io_dm[41];
+ assign \mprj_pads.dm[40] = mprj_io_dm[40];
+ assign \mprj_pads.dm[39] = mprj_io_dm[39];
+ assign \mprj_pads.dm[38] = mprj_io_dm[38];
+ assign \mprj_pads.dm[37] = mprj_io_dm[37];
+ assign \mprj_pads.dm[36] = mprj_io_dm[36];
+ assign \mprj_pads.dm[35] = mprj_io_dm[35];
+ assign \mprj_pads.dm[34] = mprj_io_dm[34];
+ assign \mprj_pads.dm[33] = mprj_io_dm[33];
+ assign \mprj_pads.dm[32] = mprj_io_dm[32];
+ assign \mprj_pads.dm[31] = mprj_io_dm[31];
+ assign \mprj_pads.dm[30] = mprj_io_dm[30];
+ assign \mprj_pads.dm[29] = mprj_io_dm[29];
+ assign \mprj_pads.dm[28] = mprj_io_dm[28];
+ assign \mprj_pads.dm[27] = mprj_io_dm[27];
+ assign \mprj_pads.dm[26] = mprj_io_dm[26];
+ assign \mprj_pads.dm[25] = mprj_io_dm[25];
+ assign \mprj_pads.dm[24] = mprj_io_dm[24];
+ assign \mprj_pads.dm[23] = mprj_io_dm[23];
+ assign \mprj_pads.dm[22] = mprj_io_dm[22];
+ assign \mprj_pads.dm[21] = mprj_io_dm[21];
+ assign \mprj_pads.dm[20] = mprj_io_dm[20];
+ assign \mprj_pads.dm[19] = mprj_io_dm[19];
+ assign \mprj_pads.dm[18] = mprj_io_dm[18];
+ assign \mprj_pads.dm[17] = mprj_io_dm[17];
+ assign \mprj_pads.dm[16] = mprj_io_dm[16];
+ assign \mprj_pads.dm[15] = mprj_io_dm[15];
+ assign \mprj_pads.dm[14] = mprj_io_dm[14];
+ assign \mprj_pads.dm[13] = mprj_io_dm[13];
+ assign \mprj_pads.dm[12] = mprj_io_dm[12];
+ assign \mprj_pads.dm[11] = mprj_io_dm[11];
+ assign \mprj_pads.dm[10] = mprj_io_dm[10];
+ assign \mprj_pads.dm[9] = mprj_io_dm[9];
+ assign \mprj_pads.dm[8] = mprj_io_dm[8];
+ assign \mprj_pads.dm[7] = mprj_io_dm[7];
+ assign \mprj_pads.dm[6] = mprj_io_dm[6];
+ assign \mprj_pads.dm[5] = mprj_io_dm[5];
+ assign \mprj_pads.dm[4] = mprj_io_dm[4];
+ assign \mprj_pads.dm[3] = mprj_io_dm[3];
+ assign \mprj_pads.dm[2] = mprj_io_dm[2];
+ assign \mprj_pads.dm[1] = mprj_io_dm[1];
+ assign \mprj_pads.dm[0] = mprj_io_dm[0];
+ assign \mprj_pads.analog_io[17] = mprj_gpio_analog[17];
+ assign \mprj_pads.analog_io[16] = mprj_gpio_analog[16];
+ assign \mprj_pads.analog_io[15] = mprj_gpio_analog[15];
+ assign \mprj_pads.analog_io[14] = mprj_gpio_analog[14];
+ assign \mprj_pads.analog_io[13] = mprj_gpio_analog[13];
+ assign \mprj_pads.analog_io[12] = mprj_gpio_analog[12];
+ assign \mprj_pads.analog_io[11] = mprj_gpio_analog[11];
+ assign \mprj_pads.analog_io[10] = mprj_gpio_analog[10];
+ assign \mprj_pads.analog_io[9] = mprj_gpio_analog[9];
+ assign \mprj_pads.analog_io[8] = mprj_gpio_analog[8];
+ assign \mprj_pads.analog_io[7] = mprj_gpio_analog[7];
+ assign \mprj_pads.analog_io[6] = mprj_gpio_analog[6];
+ assign \mprj_pads.analog_io[5] = mprj_gpio_analog[5];
+ assign \mprj_pads.analog_io[4] = mprj_gpio_analog[4];
+ assign \mprj_pads.analog_io[3] = mprj_gpio_analog[3];
+ assign \mprj_pads.analog_io[2] = mprj_gpio_analog[2];
+ assign \mprj_pads.analog_io[1] = mprj_gpio_analog[1];
+ assign \mprj_pads.analog_io[0] = mprj_gpio_analog[0];
+ assign \mprj_pads.inp_dis[26] = mprj_io_inp_dis[26];
+ assign \mprj_pads.inp_dis[25] = mprj_io_inp_dis[25];
+ assign \mprj_pads.inp_dis[24] = mprj_io_inp_dis[24];
+ assign \mprj_pads.inp_dis[23] = mprj_io_inp_dis[23];
+ assign \mprj_pads.inp_dis[22] = mprj_io_inp_dis[22];
+ assign \mprj_pads.inp_dis[21] = mprj_io_inp_dis[21];
+ assign \mprj_pads.inp_dis[20] = mprj_io_inp_dis[20];
+ assign \mprj_pads.inp_dis[19] = mprj_io_inp_dis[19];
+ assign \mprj_pads.inp_dis[18] = mprj_io_inp_dis[18];
+ assign \mprj_pads.inp_dis[17] = mprj_io_inp_dis[17];
+ assign \mprj_pads.inp_dis[16] = mprj_io_inp_dis[16];
+ assign \mprj_pads.inp_dis[15] = mprj_io_inp_dis[15];
+ assign \mprj_pads.inp_dis[14] = mprj_io_inp_dis[14];
+ assign \mprj_pads.inp_dis[13] = mprj_io_inp_dis[13];
+ assign \mprj_pads.inp_dis[12] = mprj_io_inp_dis[12];
+ assign \mprj_pads.inp_dis[11] = mprj_io_inp_dis[11];
+ assign \mprj_pads.inp_dis[10] = mprj_io_inp_dis[10];
+ assign \mprj_pads.inp_dis[9] = mprj_io_inp_dis[9];
+ assign \mprj_pads.inp_dis[8] = mprj_io_inp_dis[8];
+ assign \mprj_pads.inp_dis[7] = mprj_io_inp_dis[7];
+ assign \mprj_pads.inp_dis[6] = mprj_io_inp_dis[6];
+ assign \mprj_pads.inp_dis[5] = mprj_io_inp_dis[5];
+ assign \mprj_pads.inp_dis[4] = mprj_io_inp_dis[4];
+ assign \mprj_pads.inp_dis[3] = mprj_io_inp_dis[3];
+ assign \mprj_pads.inp_dis[2] = mprj_io_inp_dis[2];
+ assign \mprj_pads.inp_dis[1] = mprj_io_inp_dis[1];
+ assign \mprj_pads.inp_dis[0] = mprj_io_inp_dis[0];
+ assign \mprj_pads.ib_mode_sel[26] = mprj_io_ib_mode_sel[26];
+ assign \mprj_pads.ib_mode_sel[25] = mprj_io_ib_mode_sel[25];
+ assign \mprj_pads.ib_mode_sel[24] = mprj_io_ib_mode_sel[24];
+ assign \mprj_pads.ib_mode_sel[23] = mprj_io_ib_mode_sel[23];
+ assign \mprj_pads.ib_mode_sel[22] = mprj_io_ib_mode_sel[22];
+ assign \mprj_pads.ib_mode_sel[21] = mprj_io_ib_mode_sel[21];
+ assign \mprj_pads.ib_mode_sel[20] = mprj_io_ib_mode_sel[20];
+ assign \mprj_pads.ib_mode_sel[19] = mprj_io_ib_mode_sel[19];
+ assign \mprj_pads.ib_mode_sel[18] = mprj_io_ib_mode_sel[18];
+ assign \mprj_pads.ib_mode_sel[17] = mprj_io_ib_mode_sel[17];
+ assign \mprj_pads.ib_mode_sel[16] = mprj_io_ib_mode_sel[16];
+ assign \mprj_pads.ib_mode_sel[15] = mprj_io_ib_mode_sel[15];
+ assign \mprj_pads.ib_mode_sel[14] = mprj_io_ib_mode_sel[14];
+ assign \mprj_pads.ib_mode_sel[13] = mprj_io_ib_mode_sel[13];
+ assign \mprj_pads.ib_mode_sel[12] = mprj_io_ib_mode_sel[12];
+ assign \mprj_pads.ib_mode_sel[11] = mprj_io_ib_mode_sel[11];
+ assign \mprj_pads.ib_mode_sel[10] = mprj_io_ib_mode_sel[10];
+ assign \mprj_pads.ib_mode_sel[9] = mprj_io_ib_mode_sel[9];
+ assign \mprj_pads.ib_mode_sel[8] = mprj_io_ib_mode_sel[8];
+ assign \mprj_pads.ib_mode_sel[7] = mprj_io_ib_mode_sel[7];
+ assign \mprj_pads.ib_mode_sel[6] = mprj_io_ib_mode_sel[6];
+ assign \mprj_pads.ib_mode_sel[5] = mprj_io_ib_mode_sel[5];
+ assign \mprj_pads.ib_mode_sel[4] = mprj_io_ib_mode_sel[4];
+ assign \mprj_pads.ib_mode_sel[3] = mprj_io_ib_mode_sel[3];
+ assign \mprj_pads.ib_mode_sel[2] = mprj_io_ib_mode_sel[2];
+ assign \mprj_pads.ib_mode_sel[1] = mprj_io_ib_mode_sel[1];
+ assign \mprj_pads.ib_mode_sel[0] = mprj_io_ib_mode_sel[0];
+ assign \mprj_pads.io_out[26] = mprj_io_out[26];
+ assign \mprj_pads.io_out[25] = mprj_io_out[25];
+ assign \mprj_pads.io_out[24] = mprj_io_out[24];
+ assign \mprj_pads.io_out[23] = mprj_io_out[23];
+ assign \mprj_pads.io_out[22] = mprj_io_out[22];
+ assign \mprj_pads.io_out[21] = mprj_io_out[21];
+ assign \mprj_pads.io_out[20] = mprj_io_out[20];
+ assign \mprj_pads.io_out[19] = mprj_io_out[19];
+ assign \mprj_pads.io_out[18] = mprj_io_out[18];
+ assign \mprj_pads.io_out[17] = mprj_io_out[17];
+ assign \mprj_pads.io_out[16] = mprj_io_out[16];
+ assign \mprj_pads.io_out[15] = mprj_io_out[15];
+ assign \mprj_pads.io_out[14] = mprj_io_out[14];
+ assign \mprj_pads.io_out[13] = mprj_io_out[13];
+ assign \mprj_pads.io_out[12] = mprj_io_out[12];
+ assign \mprj_pads.io_out[11] = mprj_io_out[11];
+ assign \mprj_pads.io_out[10] = mprj_io_out[10];
+ assign \mprj_pads.io_out[9] = mprj_io_out[9];
+ assign \mprj_pads.io_out[8] = mprj_io_out[8];
+ assign \mprj_pads.io_out[7] = mprj_io_out[7];
+ assign \mprj_pads.io_out[6] = mprj_io_out[6];
+ assign \mprj_pads.io_out[5] = mprj_io_out[5];
+ assign \mprj_pads.io_out[4] = mprj_io_out[4];
+ assign \mprj_pads.io_out[3] = mprj_io_out[3];
+ assign \mprj_pads.io_out[2] = mprj_io_out[2];
+ assign \mprj_pads.io_out[1] = mprj_io_out[1];
+ assign \mprj_pads.io_out[0] = mprj_io_out[0];
+ assign \mprj_pads.analog_sel[26] = mprj_io_analog_sel[26];
+ assign \mprj_pads.analog_sel[25] = mprj_io_analog_sel[25];
+ assign \mprj_pads.analog_sel[24] = mprj_io_analog_sel[24];
+ assign \mprj_pads.analog_sel[23] = mprj_io_analog_sel[23];
+ assign \mprj_pads.analog_sel[22] = mprj_io_analog_sel[22];
+ assign \mprj_pads.analog_sel[21] = mprj_io_analog_sel[21];
+ assign \mprj_pads.analog_sel[20] = mprj_io_analog_sel[20];
+ assign \mprj_pads.analog_sel[19] = mprj_io_analog_sel[19];
+ assign \mprj_pads.analog_sel[18] = mprj_io_analog_sel[18];
+ assign \mprj_pads.analog_sel[17] = mprj_io_analog_sel[17];
+ assign \mprj_pads.analog_sel[16] = mprj_io_analog_sel[16];
+ assign \mprj_pads.analog_sel[15] = mprj_io_analog_sel[15];
+ assign \mprj_pads.analog_sel[14] = mprj_io_analog_sel[14];
+ assign \mprj_pads.analog_sel[13] = mprj_io_analog_sel[13];
+ assign \mprj_pads.analog_sel[12] = mprj_io_analog_sel[12];
+ assign \mprj_pads.analog_sel[11] = mprj_io_analog_sel[11];
+ assign \mprj_pads.analog_sel[10] = mprj_io_analog_sel[10];
+ assign \mprj_pads.analog_sel[9] = mprj_io_analog_sel[9];
+ assign \mprj_pads.analog_sel[8] = mprj_io_analog_sel[8];
+ assign \mprj_pads.analog_sel[7] = mprj_io_analog_sel[7];
+ assign \mprj_pads.analog_sel[6] = mprj_io_analog_sel[6];
+ assign \mprj_pads.analog_sel[5] = mprj_io_analog_sel[5];
+ assign \mprj_pads.analog_sel[4] = mprj_io_analog_sel[4];
+ assign \mprj_pads.analog_sel[3] = mprj_io_analog_sel[3];
+ assign \mprj_pads.analog_sel[2] = mprj_io_analog_sel[2];
+ assign \mprj_pads.analog_sel[1] = mprj_io_analog_sel[1];
+ assign \mprj_pads.analog_sel[0] = mprj_io_analog_sel[0];
+ assign \mprj_pads.enh[26] = porb_h;
+ assign \mprj_pads.enh[25] = porb_h;
+ assign \mprj_pads.enh[24] = porb_h;
+ assign \mprj_pads.enh[23] = porb_h;
+ assign \mprj_pads.enh[22] = porb_h;
+ assign \mprj_pads.enh[21] = porb_h;
+ assign \mprj_pads.enh[20] = porb_h;
+ assign \mprj_pads.enh[19] = porb_h;
+ assign \mprj_pads.enh[18] = porb_h;
+ assign \mprj_pads.enh[17] = porb_h;
+ assign \mprj_pads.enh[16] = porb_h;
+ assign \mprj_pads.enh[15] = porb_h;
+ assign \mprj_pads.enh[14] = porb_h;
+ assign \mprj_pads.enh[13] = porb_h;
+ assign \mprj_pads.enh[12] = porb_h;
+ assign \mprj_pads.enh[11] = porb_h;
+ assign \mprj_pads.enh[10] = porb_h;
+ assign \mprj_pads.enh[9] = porb_h;
+ assign \mprj_pads.enh[8] = porb_h;
+ assign \mprj_pads.enh[7] = porb_h;
+ assign \mprj_pads.enh[6] = porb_h;
+ assign \mprj_pads.enh[5] = porb_h;
+ assign \mprj_pads.enh[4] = porb_h;
+ assign \mprj_pads.enh[3] = porb_h;
+ assign \mprj_pads.enh[2] = porb_h;
+ assign \mprj_pads.enh[1] = porb_h;
+ assign \mprj_pads.enh[0] = porb_h;
+ assign \mprj_pads.analog_pol[26] = mprj_io_analog_pol[26];
+ assign \mprj_pads.analog_pol[25] = mprj_io_analog_pol[25];
+ assign \mprj_pads.analog_pol[24] = mprj_io_analog_pol[24];
+ assign \mprj_pads.analog_pol[23] = mprj_io_analog_pol[23];
+ assign \mprj_pads.analog_pol[22] = mprj_io_analog_pol[22];
+ assign \mprj_pads.analog_pol[21] = mprj_io_analog_pol[21];
+ assign \mprj_pads.analog_pol[20] = mprj_io_analog_pol[20];
+ assign \mprj_pads.analog_pol[19] = mprj_io_analog_pol[19];
+ assign \mprj_pads.analog_pol[18] = mprj_io_analog_pol[18];
+ assign \mprj_pads.analog_pol[17] = mprj_io_analog_pol[17];
+ assign \mprj_pads.analog_pol[16] = mprj_io_analog_pol[16];
+ assign \mprj_pads.analog_pol[15] = mprj_io_analog_pol[15];
+ assign \mprj_pads.analog_pol[14] = mprj_io_analog_pol[14];
+ assign \mprj_pads.analog_pol[13] = mprj_io_analog_pol[13];
+ assign \mprj_pads.analog_pol[12] = mprj_io_analog_pol[12];
+ assign \mprj_pads.analog_pol[11] = mprj_io_analog_pol[11];
+ assign \mprj_pads.analog_pol[10] = mprj_io_analog_pol[10];
+ assign \mprj_pads.analog_pol[9] = mprj_io_analog_pol[9];
+ assign \mprj_pads.analog_pol[8] = mprj_io_analog_pol[8];
+ assign \mprj_pads.analog_pol[7] = mprj_io_analog_pol[7];
+ assign \mprj_pads.analog_pol[6] = mprj_io_analog_pol[6];
+ assign \mprj_pads.analog_pol[5] = mprj_io_analog_pol[5];
+ assign \mprj_pads.analog_pol[4] = mprj_io_analog_pol[4];
+ assign \mprj_pads.analog_pol[3] = mprj_io_analog_pol[3];
+ assign \mprj_pads.analog_pol[2] = mprj_io_analog_pol[2];
+ assign \mprj_pads.analog_pol[1] = mprj_io_analog_pol[1];
+ assign \mprj_pads.analog_pol[0] = mprj_io_analog_pol[0];
+ assign \mprj_pads.io[26] = mprj_io[37];
+ assign \mprj_pads.io[25] = mprj_io[36];
+ assign \mprj_pads.io[24] = mprj_io[35];
+ assign \mprj_pads.io[23] = mprj_io[34];
+ assign \mprj_pads.io[22] = mprj_io[33];
+ assign \mprj_pads.io[21] = mprj_io[32];
+ assign \mprj_pads.io[20] = mprj_io[31];
+ assign \mprj_pads.io[19] = mprj_io[30];
+ assign \mprj_pads.io[18] = mprj_io[29];
+ assign \mprj_pads.io[17] = mprj_io[28];
+ assign \mprj_pads.io[16] = mprj_io[27];
+ assign \mprj_pads.io[15] = mprj_io[26];
+ assign \mprj_pads.io[14] = mprj_io[25];
+ assign \mprj_pads.io[13] = mprj_io[13];
+ assign \mprj_pads.io[12] = mprj_io[12];
+ assign \mprj_pads.io[11] = mprj_io[11];
+ assign \mprj_pads.io[10] = mprj_io[10];
+ assign \mprj_pads.io[9] = mprj_io[9];
+ assign \mprj_pads.io[8] = mprj_io[8];
+ assign \mprj_pads.io[7] = mprj_io[7];
+ assign \mprj_pads.io[6] = mprj_io[6];
+ assign \mprj_pads.io[5] = mprj_io[5];
+ assign \mprj_pads.io[4] = mprj_io[4];
+ assign \mprj_pads.io[3] = mprj_io[3];
+ assign \mprj_pads.io[2] = mprj_io[2];
+ assign \mprj_pads.io[1] = mprj_io[1];
+ assign \mprj_pads.io[0] = mprj_io[0];
+ assign \mprj_pads.vddio = vddio;
+ assign \mprj_pads.vssio = vssio;
+ assign \mprj_pads.vccd = vccd;
+ assign \mprj_pads.vssd = vssd;
+ assign \mprj_pads.vdda1 = vdda1;
+ assign \mprj_pads.vdda2 = vdda2;
+ assign \mprj_pads.vssa1 = vssa1;
+ assign \mprj_pads.vssa2 = vssa2;
+ assign \mprj_pads.porb_h = porb_h;
+ assign \mprj_io_enh[2] = porb_h;
+ assign \mprj_io_enh[6] = porb_h;
+ assign \mprj_io_enh[16] = porb_h;
+ assign \mprj_io_enh[20] = porb_h;
+ assign \mprj_io_enh[4] = porb_h;
+ assign \mprj_io_enh[10] = porb_h;
+ assign \mprj_io_enh[8] = porb_h;
+ assign \mprj_io_enh[24] = porb_h;
+ assign \mprj_io_enh[13] = porb_h;
+ assign \mprj_io_enh[23] = porb_h;
+ assign \mprj_io_enh[19] = porb_h;
+ assign \mprj_io_enh[5] = porb_h;
+ assign \mprj_io_enh[3] = porb_h;
+ assign \mprj_io_enh[12] = porb_h;
+ assign \mprj_io_enh[22] = porb_h;
+ assign \mprj_io_enh[21] = porb_h;
+ assign \mprj_io_enh[11] = porb_h;
+ assign \mprj_io_enh[15] = porb_h;
+ assign \mprj_io_enh[9] = porb_h;
+ assign \mprj_io_enh[7] = porb_h;
+ assign \mprj_io_enh[25] = porb_h;
+ assign \mprj_io_enh[17] = porb_h;
+ assign \mprj_io_enh[18] = porb_h;
+ assign \dm_all[0] = gpio_mode0_core;
+ assign \mprj_io_enh[14] = porb_h;
+ assign \dm_all[2] = gpio_mode1_core;
+ assign \dm_all[1] = gpio_mode1_core;
+ assign \mprj_io_enh[26] = porb_h;
+ assign vssio_q = \mprj_pads.vssio_q ;
+ assign vddio_q = \mprj_pads.vddio_q ;
+ assign analog_b = \mprj_pads.analog_b ;
+ assign analog_a = \mprj_pads.analog_a ;
+ assign mprj_io_in_3v3 = { \mprj_pads.io_in_3v3[26] , \mprj_pads.io_in_3v3[25] , \mprj_pads.io_in_3v3[24] , \mprj_pads.io_in_3v3[23] , \mprj_pads.io_in_3v3[22] , \mprj_pads.io_in_3v3[21] , \mprj_pads.io_in_3v3[20] , \mprj_pads.io_in_3v3[19] , \mprj_pads.io_in_3v3[18] , \mprj_pads.io_in_3v3[17] , \mprj_pads.io_in_3v3[16] , \mprj_pads.io_in_3v3[15] , \mprj_pads.io_in_3v3[14] , \mprj_pads.io_in_3v3[13] , \mprj_pads.io_in_3v3[12] , \mprj_pads.io_in_3v3[11] , \mprj_pads.io_in_3v3[10] , \mprj_pads.io_in_3v3[9] , \mprj_pads.io_in_3v3[8] , \mprj_pads.io_in_3v3[7] , \mprj_pads.io_in_3v3[6] , \mprj_pads.io_in_3v3[5] , \mprj_pads.io_in_3v3[4] , \mprj_pads.io_in_3v3[3] , \mprj_pads.io_in_3v3[2] , \mprj_pads.io_in_3v3[1] , \mprj_pads.io_in_3v3[0] };
+ assign mprj_io_in = { \mprj_pads.io_in[26] , \mprj_pads.io_in[25] , \mprj_pads.io_in[24] , \mprj_pads.io_in[23] , \mprj_pads.io_in[22] , \mprj_pads.io_in[21] , \mprj_pads.io_in[20] , \mprj_pads.io_in[19] , \mprj_pads.io_in[18] , \mprj_pads.io_in[17] , \mprj_pads.io_in[16] , \mprj_pads.io_in[15] , \mprj_pads.io_in[14] , \mprj_pads.io_in[13] , \mprj_pads.io_in[12] , \mprj_pads.io_in[11] , \mprj_pads.io_in[10] , \mprj_pads.io_in[9] , \mprj_pads.io_in[8] , \mprj_pads.io_in[7] , \mprj_pads.io_in[6] , \mprj_pads.io_in[5] , \mprj_pads.io_in[4] , \mprj_pads.io_in[3] , \mprj_pads.io_in[2] , \mprj_pads.io_in[1] , \mprj_pads.io_in[0] };
+endmodule
diff --git a/caravel/verilog/gl/digital_pll.v b/caravel/verilog/gl/digital_pll.v
new file mode 100644
index 0000000..a56dae6
--- /dev/null
+++ b/caravel/verilog/gl/digital_pll.v
@@ -0,0 +1,3853 @@
+module digital_pll (VGND,
+ VPWR,
+ dco,
+ enable,
+ osc,
+ resetb,
+ clockp,
+ div,
+ ext_trim);
+ input VGND;
+ input VPWR;
+ input dco;
+ input enable;
+ input osc;
+ input resetb;
+ output [1:0] clockp;
+ input [4:0] div;
+ input [25:0] ext_trim;
+
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire \pll_control.clock ;
+ wire \pll_control.count0[0] ;
+ wire \pll_control.count0[1] ;
+ wire \pll_control.count0[2] ;
+ wire \pll_control.count0[3] ;
+ wire \pll_control.count0[4] ;
+ wire \pll_control.count1[0] ;
+ wire \pll_control.count1[1] ;
+ wire \pll_control.count1[2] ;
+ wire \pll_control.count1[3] ;
+ wire \pll_control.count1[4] ;
+ wire \pll_control.oscbuf[0] ;
+ wire \pll_control.oscbuf[1] ;
+ wire \pll_control.oscbuf[2] ;
+ wire \pll_control.prep[0] ;
+ wire \pll_control.prep[1] ;
+ wire \pll_control.prep[2] ;
+ wire \pll_control.tint[0] ;
+ wire \pll_control.tint[1] ;
+ wire \pll_control.tint[2] ;
+ wire \pll_control.tint[3] ;
+ wire \pll_control.tint[4] ;
+ wire \pll_control.tval[0] ;
+ wire \pll_control.tval[1] ;
+ wire \ringosc.c[0] ;
+ wire \ringosc.c[1] ;
+ wire \ringosc.dstage[0].id.d0 ;
+ wire \ringosc.dstage[0].id.d1 ;
+ wire \ringosc.dstage[0].id.d2 ;
+ wire \ringosc.dstage[0].id.in ;
+ wire \ringosc.dstage[0].id.out ;
+ wire \ringosc.dstage[0].id.trim[0] ;
+ wire \ringosc.dstage[0].id.trim[1] ;
+ wire \ringosc.dstage[0].id.ts ;
+ wire \ringosc.dstage[10].id.d0 ;
+ wire \ringosc.dstage[10].id.d1 ;
+ wire \ringosc.dstage[10].id.d2 ;
+ wire \ringosc.dstage[10].id.in ;
+ wire \ringosc.dstage[10].id.out ;
+ wire \ringosc.dstage[10].id.trim[0] ;
+ wire \ringosc.dstage[10].id.trim[1] ;
+ wire \ringosc.dstage[10].id.ts ;
+ wire \ringosc.dstage[11].id.d0 ;
+ wire \ringosc.dstage[11].id.d1 ;
+ wire \ringosc.dstage[11].id.d2 ;
+ wire \ringosc.dstage[11].id.out ;
+ wire \ringosc.dstage[11].id.trim[0] ;
+ wire \ringosc.dstage[11].id.trim[1] ;
+ wire \ringosc.dstage[11].id.ts ;
+ wire \ringosc.dstage[1].id.d0 ;
+ wire \ringosc.dstage[1].id.d1 ;
+ wire \ringosc.dstage[1].id.d2 ;
+ wire \ringosc.dstage[1].id.out ;
+ wire \ringosc.dstage[1].id.trim[0] ;
+ wire \ringosc.dstage[1].id.trim[1] ;
+ wire \ringosc.dstage[1].id.ts ;
+ wire \ringosc.dstage[2].id.d0 ;
+ wire \ringosc.dstage[2].id.d1 ;
+ wire \ringosc.dstage[2].id.d2 ;
+ wire \ringosc.dstage[2].id.out ;
+ wire \ringosc.dstage[2].id.trim[0] ;
+ wire \ringosc.dstage[2].id.trim[1] ;
+ wire \ringosc.dstage[2].id.ts ;
+ wire \ringosc.dstage[3].id.d0 ;
+ wire \ringosc.dstage[3].id.d1 ;
+ wire \ringosc.dstage[3].id.d2 ;
+ wire \ringosc.dstage[3].id.out ;
+ wire \ringosc.dstage[3].id.trim[0] ;
+ wire \ringosc.dstage[3].id.trim[1] ;
+ wire \ringosc.dstage[3].id.ts ;
+ wire \ringosc.dstage[4].id.d0 ;
+ wire \ringosc.dstage[4].id.d1 ;
+ wire \ringosc.dstage[4].id.d2 ;
+ wire \ringosc.dstage[4].id.out ;
+ wire \ringosc.dstage[4].id.trim[0] ;
+ wire \ringosc.dstage[4].id.trim[1] ;
+ wire \ringosc.dstage[4].id.ts ;
+ wire \ringosc.dstage[5].id.d0 ;
+ wire \ringosc.dstage[5].id.d1 ;
+ wire \ringosc.dstage[5].id.d2 ;
+ wire \ringosc.dstage[5].id.out ;
+ wire \ringosc.dstage[5].id.trim[0] ;
+ wire \ringosc.dstage[5].id.trim[1] ;
+ wire \ringosc.dstage[5].id.ts ;
+ wire \ringosc.dstage[6].id.d0 ;
+ wire \ringosc.dstage[6].id.d1 ;
+ wire \ringosc.dstage[6].id.d2 ;
+ wire \ringosc.dstage[6].id.out ;
+ wire \ringosc.dstage[6].id.trim[0] ;
+ wire \ringosc.dstage[6].id.trim[1] ;
+ wire \ringosc.dstage[6].id.ts ;
+ wire \ringosc.dstage[7].id.d0 ;
+ wire \ringosc.dstage[7].id.d1 ;
+ wire \ringosc.dstage[7].id.d2 ;
+ wire \ringosc.dstage[7].id.out ;
+ wire \ringosc.dstage[7].id.trim[0] ;
+ wire \ringosc.dstage[7].id.trim[1] ;
+ wire \ringosc.dstage[7].id.ts ;
+ wire \ringosc.dstage[8].id.d0 ;
+ wire \ringosc.dstage[8].id.d1 ;
+ wire \ringosc.dstage[8].id.d2 ;
+ wire \ringosc.dstage[8].id.out ;
+ wire \ringosc.dstage[8].id.trim[0] ;
+ wire \ringosc.dstage[8].id.trim[1] ;
+ wire \ringosc.dstage[8].id.ts ;
+ wire \ringosc.dstage[9].id.d0 ;
+ wire \ringosc.dstage[9].id.d1 ;
+ wire \ringosc.dstage[9].id.d2 ;
+ wire \ringosc.dstage[9].id.trim[0] ;
+ wire \ringosc.dstage[9].id.trim[1] ;
+ wire \ringosc.dstage[9].id.ts ;
+ wire \ringosc.iss.ctrl0 ;
+ wire \ringosc.iss.d0 ;
+ wire \ringosc.iss.d1 ;
+ wire \ringosc.iss.d2 ;
+ wire \ringosc.iss.one ;
+ wire \ringosc.iss.reset ;
+ wire \ringosc.iss.trim[0] ;
+ wire \ringosc.iss.trim[1] ;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA__177__A (.DIODE(div[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__181__A (.DIODE(enable),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__181__B (.DIODE(resetb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__182__A (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__201__A1 (.DIODE(div[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__201__B1 (.DIODE(div[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__202__A (.DIODE(div[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__204__A1 (.DIODE(div[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__207__A (.DIODE(div[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__210__A1 (.DIODE(div[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__210__B1 (.DIODE(div[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__211__A1 (.DIODE(div[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__216__A (.DIODE(div[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__218__B1 (.DIODE(div[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__330__A1 (.DIODE(ext_trim[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__330__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__331__A1 (.DIODE(ext_trim[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__331__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__332__A1 (.DIODE(ext_trim[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__332__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__333__A1 (.DIODE(ext_trim[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__333__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__334__A1 (.DIODE(ext_trim[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__334__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__335__A1 (.DIODE(ext_trim[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__335__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__336__A1 (.DIODE(ext_trim[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__336__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__337__A1 (.DIODE(ext_trim[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__337__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__338__A1 (.DIODE(ext_trim[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__338__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__339__A1 (.DIODE(ext_trim[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__339__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__340__A1 (.DIODE(ext_trim[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__340__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__341__A1 (.DIODE(ext_trim[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__341__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__342__A1 (.DIODE(ext_trim[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__342__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__343__A1 (.DIODE(ext_trim[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__343__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__344__A1 (.DIODE(ext_trim[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__344__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__345__A1 (.DIODE(ext_trim[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__345__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__346__A1 (.DIODE(ext_trim[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__346__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__347__A1 (.DIODE(ext_trim[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__347__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__348__A1 (.DIODE(ext_trim[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__348__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__349__A1 (.DIODE(ext_trim[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__349__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__350__A1 (.DIODE(ext_trim[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__350__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__351__A1 (.DIODE(ext_trim[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__351__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__352__A1 (.DIODE(ext_trim[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__352__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__353__A1 (.DIODE(ext_trim[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__353__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__354__A1 (.DIODE(ext_trim[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__354__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__355__A1 (.DIODE(ext_trim[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__355__S (.DIODE(dco),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA__356__D (.DIODE(osc),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_62 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_66 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_0_70 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_0_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_10_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_104 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_10_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_36 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_10_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_11_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_11_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_11_130 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_11_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_11_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_11_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_11_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_11_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_11_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_12_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_12_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_12_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_80 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_13_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_13_34 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_13_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_14_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_14_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_14_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_14_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_14_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_14_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_14_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_15_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_15_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_15_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_15_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_15_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_15_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_15_76 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_15_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_16_115 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_16_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_16_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_16_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_16_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_16_59 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_16_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_16_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_16_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_16_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_17_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_17_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_17_30 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_18_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_18_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_18_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_18_49 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_18_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_18_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_19_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_1_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_1_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_20_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_20_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_20_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_20_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_104 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_21_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_22_133 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_22_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_22_31 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_22_42 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_2_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_4_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_129 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_58 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_4_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_5_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_5_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_5_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_122 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_6_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_6_62 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_116 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_127 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_7_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_86 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_87 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_88 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_89 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_90 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_91 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_92 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_93 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_94 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_95 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _164_ (.A(\pll_control.count0[4] ),
+ .Y(_072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _165_ (.A(\pll_control.count1[4] ),
+ .Y(_073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _166_ (.A(\pll_control.count0[2] ),
+ .Y(_074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _167_ (.A(\pll_control.count0[1] ),
+ .Y(_075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _168_ (.A(\pll_control.count0[0] ),
+ .Y(_076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _169_ (.A(\pll_control.count1[0] ),
+ .Y(_077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _170_ (.A(\pll_control.tint[4] ),
+ .Y(_078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _171_ (.A(\pll_control.tint[3] ),
+ .Y(_079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _172_ (.A(\pll_control.tint[2] ),
+ .Y(_080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _173_ (.A(\pll_control.tint[1] ),
+ .Y(_081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _174_ (.A(\pll_control.tint[0] ),
+ .Y(_082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _175_ (.A(\pll_control.tval[1] ),
+ .Y(_083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _176_ (.A(\pll_control.tval[0] ),
+ .Y(_084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _177_ (.A(div[0]),
+ .Y(_085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_2 _178_ (.A1_N(\pll_control.oscbuf[1] ),
+ .A2_N(\pll_control.oscbuf[2] ),
+ .B1(\pll_control.oscbuf[1] ),
+ .B2(\pll_control.oscbuf[2] ),
+ .X(_086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _179_ (.A(_086_),
+ .Y(_087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _180_ (.A1(\pll_control.count1[4] ),
+ .A2(_086_),
+ .B1(\pll_control.count0[4] ),
+ .B2(_087_),
+ .X(_071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _181_ (.A(enable),
+ .B(resetb),
+ .Y(\ringosc.iss.reset ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _182_ (.A(dco),
+ .B(\ringosc.iss.reset ),
+ .Y(_050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _183_ (.A1(\pll_control.count1[3] ),
+ .A2(_086_),
+ .B1(\pll_control.count0[3] ),
+ .B2(_087_),
+ .X(_070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _184_ (.A1(\pll_control.count1[2] ),
+ .A2(_086_),
+ .B1(\pll_control.count0[2] ),
+ .B2(_087_),
+ .X(_069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _185_ (.A1(\pll_control.count1[1] ),
+ .A2(_086_),
+ .B1(\pll_control.count0[1] ),
+ .B2(_087_),
+ .X(_068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _186_ (.A1(\pll_control.count1[0] ),
+ .A2(_086_),
+ .B1(\pll_control.count0[0] ),
+ .B2(_087_),
+ .X(_067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _187_ (.A1(\pll_control.prep[1] ),
+ .A2(_087_),
+ .B1(\pll_control.prep[2] ),
+ .B2(_086_),
+ .X(_066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _188_ (.A1(\pll_control.prep[1] ),
+ .A2(_086_),
+ .B1(\pll_control.prep[0] ),
+ .B2(_087_),
+ .X(_065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _189_ (.A(\pll_control.prep[0] ),
+ .B(_087_),
+ .X(_064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _190_ (.A(\pll_control.count0[3] ),
+ .B(\pll_control.count1[3] ),
+ .Y(_088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_2 _191_ (.A1(\pll_control.count0[3] ),
+ .A2(\pll_control.count1[3] ),
+ .B1(_088_),
+ .X(_089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _192_ (.A(\pll_control.count0[2] ),
+ .B(\pll_control.count1[2] ),
+ .Y(_090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _193_ (.A(_076_),
+ .B(_077_),
+ .Y(_091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _194_ (.A1_N(\pll_control.count0[1] ),
+ .A2_N(\pll_control.count1[1] ),
+ .B1(\pll_control.count0[1] ),
+ .B2(\pll_control.count1[1] ),
+ .X(_092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _195_ (.A1(\pll_control.count0[1] ),
+ .A2(\pll_control.count1[1] ),
+ .B1(_091_),
+ .B2(_092_),
+ .X(_093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _196_ (.A(_093_),
+ .Y(_094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _197_ (.A1_N(\pll_control.count0[2] ),
+ .A2_N(\pll_control.count1[2] ),
+ .B1(_090_),
+ .B2(_094_),
+ .X(_095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_2 _198_ (.A1_N(_089_),
+ .A2_N(_095_),
+ .B1(_089_),
+ .B2(_095_),
+ .X(_096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_2 _199_ (.A1(\pll_control.count0[2] ),
+ .A2(\pll_control.count1[2] ),
+ .B1(_090_),
+ .Y(_097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_2 _200_ (.A1_N(_093_),
+ .A2_N(_097_),
+ .B1(_093_),
+ .B2(_097_),
+ .X(_098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_2 _201_ (.A1(div[3]),
+ .A2(_096_),
+ .B1(div[2]),
+ .B2(_098_),
+ .Y(_099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _202_ (.A(div[3]),
+ .B(_096_),
+ .X(_100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _203_ (.A(_100_),
+ .Y(_101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_2 _204_ (.A1(div[2]),
+ .A2(_098_),
+ .B1(_100_),
+ .C1(_099_),
+ .X(_102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _205_ (.A(_102_),
+ .Y(_103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2ai_2 _206_ (.A1_N(_091_),
+ .A2_N(_092_),
+ .B1(_091_),
+ .B2(_092_),
+ .Y(_104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _207_ (.A(div[1]),
+ .B(_104_),
+ .Y(_105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_2 _208_ (.A1(_076_),
+ .A2(_077_),
+ .B1(_091_),
+ .Y(_106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _209_ (.A(_106_),
+ .Y(_107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _210_ (.A1(div[1]),
+ .A2(_104_),
+ .B1(div[0]),
+ .B2(_107_),
+ .C1(_105_),
+ .X(_108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_2 _211_ (.A1(div[1]),
+ .A2(_104_),
+ .B1(_108_),
+ .Y(_109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _212_ (.A1(\pll_control.count0[4] ),
+ .A2(\pll_control.count1[4] ),
+ .B1(_072_),
+ .B2(_073_),
+ .X(_110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _213_ (.A1_N(\pll_control.count0[3] ),
+ .A2_N(\pll_control.count1[3] ),
+ .B1(_088_),
+ .B2(_095_),
+ .X(_111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _214_ (.A(_110_),
+ .B(_111_),
+ .X(_112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_2 _215_ (.A1(_110_),
+ .A2(_111_),
+ .B1_N(_112_),
+ .X(_113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _216_ (.A(div[4]),
+ .B(_113_),
+ .Y(_114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _217_ (.A1(_099_),
+ .A2(_101_),
+ .B1(_103_),
+ .B2(_109_),
+ .C1(_114_),
+ .X(_115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_2 _218_ (.A1(_072_),
+ .A2(_073_),
+ .B1(div[4]),
+ .B2(_113_),
+ .C1(_112_),
+ .Y(_116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _219_ (.A(_115_),
+ .B(_116_),
+ .X(_117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _220_ (.A(_117_),
+ .Y(_118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _221_ (.A(_081_),
+ .B(_082_),
+ .X(_119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _222_ (.A(_119_),
+ .Y(_120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _223_ (.A(_079_),
+ .B(_080_),
+ .C(_119_),
+ .X(_015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _224_ (.A(_083_),
+ .B(_084_),
+ .C(_015_),
+ .X(_121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_2 _225_ (.A1(_085_),
+ .A2(_106_),
+ .B1(_108_),
+ .C1(_102_),
+ .D1(_114_),
+ .Y(_122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _226_ (.A(\pll_control.prep[1] ),
+ .B(_087_),
+ .C(\pll_control.prep[2] ),
+ .D(\pll_control.prep[0] ),
+ .X(_123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _227_ (.A(\pll_control.tint[1] ),
+ .B(\pll_control.tint[0] ),
+ .X(_124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _228_ (.A(_124_),
+ .Y(_125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _229_ (.A(\pll_control.tint[3] ),
+ .B(\pll_control.tint[2] ),
+ .X(_126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _230_ (.A(_126_),
+ .Y(_127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _231_ (.A(_124_),
+ .B(_126_),
+ .X(_000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _232_ (.A(\pll_control.tint[4] ),
+ .B(_000_),
+ .X(_001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _233_ (.A(\pll_control.tval[1] ),
+ .B(\pll_control.tval[0] ),
+ .C(_001_),
+ .X(_128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _234_ (.A1(_116_),
+ .A2(_122_),
+ .B1(_117_),
+ .B2(_128_),
+ .C1(_123_),
+ .X(_129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _235_ (.A1(_078_),
+ .A2(_118_),
+ .A3(_121_),
+ .B1(_129_),
+ .X(_130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _236_ (.A(_130_),
+ .Y(_131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _237_ (.A1(\pll_control.tval[1] ),
+ .A2(_118_),
+ .B1(_083_),
+ .B2(_117_),
+ .X(_132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _238_ (.A1(_083_),
+ .A2(_117_),
+ .B1(_084_),
+ .B2(_132_),
+ .X(_133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _239_ (.A(_120_),
+ .B(_125_),
+ .Y(_134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _240_ (.A1(\pll_control.tint[0] ),
+ .A2(_118_),
+ .B1(_082_),
+ .B2(_117_),
+ .X(_135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_2 _241_ (.A1(_134_),
+ .A2(_135_),
+ .A3(_133_),
+ .B1(_117_),
+ .B2(_125_),
+ .X(_136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _242_ (.A1(\pll_control.tint[2] ),
+ .A2(_118_),
+ .B1(_080_),
+ .B2(_117_),
+ .X(_137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _243_ (.A1(_079_),
+ .A2(_118_),
+ .B1(\pll_control.tint[3] ),
+ .B2(_117_),
+ .X(_138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _244_ (.A(_138_),
+ .Y(_139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_2 _245_ (.A1(_137_),
+ .A2(_138_),
+ .A3(_136_),
+ .B1(_117_),
+ .B2(_127_),
+ .X(_140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _246_ (.A(_140_),
+ .Y(_141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _247_ (.A1(\pll_control.tint[4] ),
+ .A2(_118_),
+ .B1(_078_),
+ .B2(_117_),
+ .X(_142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _248_ (.A(_142_),
+ .Y(_143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_2 _249_ (.A1(_141_),
+ .A2(_142_),
+ .B1(_140_),
+ .B2(_143_),
+ .C1(_131_),
+ .X(_144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _250_ (.A1(_078_),
+ .A2(_130_),
+ .B1(_144_),
+ .Y(_063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _251_ (.A(_136_),
+ .B(_137_),
+ .X(_145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _252_ (.A1(_080_),
+ .A2(_117_),
+ .B1(_145_),
+ .Y(_146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _253_ (.A(_146_),
+ .Y(_147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_2 _254_ (.A1(_139_),
+ .A2(_146_),
+ .B1(_138_),
+ .B2(_147_),
+ .C1(_131_),
+ .X(_148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _255_ (.A1(_079_),
+ .A2(_130_),
+ .B1(_148_),
+ .Y(_062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _256_ (.A(_136_),
+ .B(_137_),
+ .Y(_149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _257_ (.A1(_130_),
+ .A2(_145_),
+ .A3(_149_),
+ .B1(\pll_control.tint[2] ),
+ .B2(_131_),
+ .X(_061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _258_ (.A(_133_),
+ .B(_135_),
+ .X(_150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _259_ (.A0(\pll_control.tint[0] ),
+ .A1(_118_),
+ .S(_133_),
+ .X(_151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_2 _260_ (.A1(_082_),
+ .A2(_117_),
+ .B1(_130_),
+ .C1(_151_),
+ .X(_152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _261_ (.A1_N(\pll_control.tint[1] ),
+ .A2_N(_152_),
+ .B1(\pll_control.tint[1] ),
+ .B2(_152_),
+ .X(_060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _262_ (.A(_133_),
+ .B(_135_),
+ .Y(_153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _263_ (.A1(_130_),
+ .A2(_150_),
+ .A3(_153_),
+ .B1(\pll_control.tint[0] ),
+ .B2(_131_),
+ .X(_059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_2 _264_ (.A1_N(_084_),
+ .A2_N(_132_),
+ .B1(_084_),
+ .B2(_132_),
+ .X(_154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_2 _265_ (.A1(_083_),
+ .A2(_130_),
+ .B1(_131_),
+ .B2(_154_),
+ .Y(_058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _266_ (.A1(\pll_control.tval[0] ),
+ .A2(_130_),
+ .B1(_084_),
+ .B2(_131_),
+ .X(_057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _267_ (.A(_075_),
+ .B(_076_),
+ .C(_074_),
+ .X(_155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _268_ (.A(_155_),
+ .Y(_156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _269_ (.A(\pll_control.count0[3] ),
+ .B(_156_),
+ .Y(_157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_2 _270_ (.A1(_072_),
+ .A2(_157_),
+ .B1(_087_),
+ .Y(_056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _271_ (.A1(\pll_control.count0[3] ),
+ .A2(_156_),
+ .B1(\pll_control.count0[4] ),
+ .B2(_157_),
+ .C1(_086_),
+ .X(_055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _272_ (.A(\pll_control.count0[3] ),
+ .B(_156_),
+ .C(\pll_control.count0[4] ),
+ .D(_086_),
+ .X(_158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _273_ (.A1(_075_),
+ .A2(_076_),
+ .B1(_074_),
+ .Y(_159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_2 _274_ (.A1(_086_),
+ .A2(_155_),
+ .A3(_159_),
+ .B1(_158_),
+ .X(_054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _275_ (.A1(_075_),
+ .A2(_076_),
+ .B1(\pll_control.count0[1] ),
+ .B2(\pll_control.count0[0] ),
+ .C1(_086_),
+ .X(_160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _276_ (.A(_158_),
+ .B(_160_),
+ .X(_053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311o_2 _277_ (.A1(\pll_control.count0[3] ),
+ .A2(_156_),
+ .A3(\pll_control.count0[4] ),
+ .B1(_076_),
+ .C1(_087_),
+ .X(_052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _278_ (.A(\pll_control.tint[4] ),
+ .B(_126_),
+ .X(_004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _279_ (.A(\pll_control.tint[1] ),
+ .B(_004_),
+ .X(_007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _280_ (.A(\pll_control.tint[3] ),
+ .B(_080_),
+ .X(_161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _281_ (.A1(_124_),
+ .A2(_161_),
+ .A3(\pll_control.tint[4] ),
+ .B1(_004_),
+ .X(_009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _282_ (.A1(\pll_control.tint[4] ),
+ .A2(_161_),
+ .A3(\pll_control.tint[1] ),
+ .B1(_004_),
+ .X(_013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _283_ (.A1(\pll_control.tint[4] ),
+ .A2(_161_),
+ .A3(_120_),
+ .B1(_004_),
+ .X(_006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_2 _284_ (.A1(\pll_control.tint[4] ),
+ .A2(_161_),
+ .B1(_004_),
+ .X(_003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o41a_2 _285_ (.A1(_079_),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[4] ),
+ .A4(_124_),
+ .B1(_003_),
+ .X(_010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o41a_2 _286_ (.A1(_079_),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[4] ),
+ .A4(\pll_control.tint[1] ),
+ .B1(_003_),
+ .X(_005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o41a_2 _287_ (.A1(_079_),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[4] ),
+ .A4(_120_),
+ .B1(_003_),
+ .X(_012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _288_ (.A(_120_),
+ .B(_004_),
+ .X(_011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _289_ (.A1(_079_),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[4] ),
+ .B1(_003_),
+ .X(_002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_2 _290_ (.A1(\pll_control.tint[3] ),
+ .A2(\pll_control.tint[2] ),
+ .A3(_124_),
+ .B1(\pll_control.tint[4] ),
+ .X(_008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_2 _291_ (.A1(\pll_control.tint[3] ),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[1] ),
+ .B1(\pll_control.tint[4] ),
+ .X(_014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _292_ (.A(_078_),
+ .B(_015_),
+ .Y(_022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _293_ (.A1(\pll_control.tint[1] ),
+ .A2(_082_),
+ .A3(_126_),
+ .B1(\pll_control.tint[4] ),
+ .C1(_000_),
+ .X(_024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _294_ (.A(_124_),
+ .B(_161_),
+ .C(_078_),
+ .X(_162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _295_ (.A1(_078_),
+ .A2(_126_),
+ .A3(_081_),
+ .B1(_162_),
+ .C1(_024_),
+ .X(_017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o41a_2 _296_ (.A1(\pll_control.tint[1] ),
+ .A2(_082_),
+ .A3(_161_),
+ .A4(_078_),
+ .B1(_017_),
+ .X(_025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _297_ (.A(_079_),
+ .B(\pll_control.tint[2] ),
+ .C(_124_),
+ .D(_078_),
+ .X(_163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _298_ (.A1(_078_),
+ .A2(_161_),
+ .A3(_081_),
+ .B1(_163_),
+ .C1(_025_),
+ .X(_016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_2 _299_ (.A(_018_),
+ .B(_022_),
+ .X(_019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o41a_2 _300_ (.A1(_081_),
+ .A2(\pll_control.tint[0] ),
+ .A3(_078_),
+ .A4(_161_),
+ .B1(_025_),
+ .X(_020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _301_ (.A(_078_),
+ .B(_127_),
+ .Y(_021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_2 _302_ (.A(\pll_control.tint[4] ),
+ .B(_126_),
+ .C(_161_),
+ .X(_027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_2 _303_ (.A1(_079_),
+ .A2(\pll_control.tint[2] ),
+ .A3(\pll_control.tint[1] ),
+ .B1(_027_),
+ .X(_023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _304_ (.A1(_120_),
+ .A2(_125_),
+ .A3(_126_),
+ .B1(\pll_control.tint[4] ),
+ .C1(_000_),
+ .X(_028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _305_ (.A(_050_),
+ .X(_049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _306_ (.A(_050_),
+ .X(_048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _307_ (.A(_050_),
+ .X(_047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _308_ (.A(_050_),
+ .X(_046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _309_ (.A(_050_),
+ .X(_045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _310_ (.A(_050_),
+ .X(_044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _311_ (.A(_050_),
+ .X(_043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _312_ (.A(_050_),
+ .X(_042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _313_ (.A(_050_),
+ .X(_041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _314_ (.A(_050_),
+ .X(_040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _315_ (.A(_050_),
+ .X(_039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _316_ (.A(_050_),
+ .X(_038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _317_ (.A(_050_),
+ .X(_037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _318_ (.A(_050_),
+ .X(_036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _319_ (.A(_050_),
+ .X(_035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _320_ (.A(_050_),
+ .X(_034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _321_ (.A(_050_),
+ .X(_033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _322_ (.A(_050_),
+ .X(_032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _323_ (.A(_050_),
+ .X(_031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _324_ (.A(_050_),
+ .X(_030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _325_ (.A(_050_),
+ .X(_029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _326_ (.A(\pll_control.tint[4] ),
+ .X(_026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _327_ (.A(_050_),
+ .X(_051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _328_ (.A(\pll_control.clock ),
+ .X(clockp[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _329_ (.A0(_015_),
+ .A1(_000_),
+ .S(\pll_control.tint[4] ),
+ .X(_018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _330_ (.A0(_012_),
+ .A1(ext_trim[11]),
+ .S(dco),
+ .X(\ringosc.dstage[11].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _331_ (.A0(_027_),
+ .A1(ext_trim[24]),
+ .S(dco),
+ .X(\ringosc.dstage[11].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _332_ (.A0(_011_),
+ .A1(ext_trim[10]),
+ .S(dco),
+ .X(\ringosc.dstage[10].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _333_ (.A0(_026_),
+ .A1(ext_trim[23]),
+ .S(dco),
+ .X(\ringosc.dstage[10].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _334_ (.A0(_010_),
+ .A1(ext_trim[9]),
+ .S(dco),
+ .X(\ringosc.dstage[9].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _335_ (.A0(_025_),
+ .A1(ext_trim[22]),
+ .S(dco),
+ .X(\ringosc.dstage[9].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _336_ (.A0(_009_),
+ .A1(ext_trim[8]),
+ .S(dco),
+ .X(\ringosc.dstage[8].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _337_ (.A0(_024_),
+ .A1(ext_trim[21]),
+ .S(dco),
+ .X(\ringosc.dstage[8].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _338_ (.A0(_008_),
+ .A1(ext_trim[7]),
+ .S(dco),
+ .X(\ringosc.dstage[7].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _339_ (.A0(_023_),
+ .A1(ext_trim[20]),
+ .S(dco),
+ .X(\ringosc.dstage[7].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _340_ (.A0(_007_),
+ .A1(ext_trim[6]),
+ .S(dco),
+ .X(\ringosc.dstage[6].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _341_ (.A0(_022_),
+ .A1(ext_trim[19]),
+ .S(dco),
+ .X(\ringosc.dstage[6].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _342_ (.A0(_006_),
+ .A1(ext_trim[5]),
+ .S(dco),
+ .X(\ringosc.dstage[5].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _343_ (.A0(_021_),
+ .A1(ext_trim[18]),
+ .S(dco),
+ .X(\ringosc.dstage[5].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _344_ (.A0(_005_),
+ .A1(ext_trim[4]),
+ .S(dco),
+ .X(\ringosc.dstage[4].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _345_ (.A0(_020_),
+ .A1(ext_trim[17]),
+ .S(dco),
+ .X(\ringosc.dstage[4].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _346_ (.A0(_004_),
+ .A1(ext_trim[3]),
+ .S(dco),
+ .X(\ringosc.dstage[3].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _347_ (.A0(_019_),
+ .A1(ext_trim[16]),
+ .S(dco),
+ .X(\ringosc.dstage[3].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _348_ (.A0(_003_),
+ .A1(ext_trim[2]),
+ .S(dco),
+ .X(\ringosc.dstage[2].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _349_ (.A0(_017_),
+ .A1(ext_trim[15]),
+ .S(dco),
+ .X(\ringosc.dstage[2].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _350_ (.A0(_002_),
+ .A1(ext_trim[1]),
+ .S(dco),
+ .X(\ringosc.dstage[1].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _351_ (.A0(_016_),
+ .A1(ext_trim[14]),
+ .S(dco),
+ .X(\ringosc.dstage[1].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _352_ (.A0(_001_),
+ .A1(ext_trim[0]),
+ .S(dco),
+ .X(\ringosc.dstage[0].id.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _353_ (.A0(_014_),
+ .A1(ext_trim[13]),
+ .S(dco),
+ .X(\ringosc.dstage[0].id.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _354_ (.A0(_013_),
+ .A1(ext_trim[12]),
+ .S(dco),
+ .X(\ringosc.iss.trim[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _355_ (.A0(_028_),
+ .A1(ext_trim[25]),
+ .S(dco),
+ .X(\ringosc.iss.trim[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _356_ (.D(osc),
+ .Q(\pll_control.oscbuf[0] ),
+ .RESET_B(_029_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _357_ (.D(\pll_control.oscbuf[0] ),
+ .Q(\pll_control.oscbuf[1] ),
+ .RESET_B(_030_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _358_ (.D(\pll_control.oscbuf[1] ),
+ .Q(\pll_control.oscbuf[2] ),
+ .RESET_B(_031_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _359_ (.D(_052_),
+ .Q(\pll_control.count0[0] ),
+ .RESET_B(_032_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _360_ (.D(_053_),
+ .Q(\pll_control.count0[1] ),
+ .RESET_B(_033_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _361_ (.D(_054_),
+ .Q(\pll_control.count0[2] ),
+ .RESET_B(_034_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _362_ (.D(_055_),
+ .Q(\pll_control.count0[3] ),
+ .RESET_B(_035_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _363_ (.D(_056_),
+ .Q(\pll_control.count0[4] ),
+ .RESET_B(_036_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _364_ (.D(_057_),
+ .Q(\pll_control.tval[0] ),
+ .RESET_B(_037_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _365_ (.D(_058_),
+ .Q(\pll_control.tval[1] ),
+ .RESET_B(_038_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _366_ (.D(_059_),
+ .Q(\pll_control.tint[0] ),
+ .RESET_B(_039_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _367_ (.D(_060_),
+ .Q(\pll_control.tint[1] ),
+ .RESET_B(_040_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _368_ (.D(_061_),
+ .Q(\pll_control.tint[2] ),
+ .RESET_B(_041_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _369_ (.D(_062_),
+ .Q(\pll_control.tint[3] ),
+ .RESET_B(_042_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _370_ (.D(_063_),
+ .Q(\pll_control.tint[4] ),
+ .RESET_B(_043_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _371_ (.D(_064_),
+ .Q(\pll_control.prep[0] ),
+ .RESET_B(_044_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _372_ (.D(_065_),
+ .Q(\pll_control.prep[1] ),
+ .RESET_B(_045_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _373_ (.D(_066_),
+ .Q(\pll_control.prep[2] ),
+ .RESET_B(_046_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _374_ (.D(_067_),
+ .Q(\pll_control.count1[0] ),
+ .RESET_B(_047_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _375_ (.D(_068_),
+ .Q(\pll_control.count1[1] ),
+ .RESET_B(_048_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _376_ (.D(_069_),
+ .Q(\pll_control.count1[2] ),
+ .RESET_B(_049_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _377_ (.D(_070_),
+ .Q(\pll_control.count1[3] ),
+ .RESET_B(_050_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _378_ (.D(_071_),
+ .Q(\pll_control.count1[4] ),
+ .RESET_B(_051_),
+ .CLK(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[0].id.delaybuf0 (.A(\ringosc.dstage[0].id.in ),
+ .X(\ringosc.dstage[0].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[0].id.delaybuf1 (.A(\ringosc.dstage[0].id.ts ),
+ .X(\ringosc.dstage[0].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[0].id.delayen0 (.A(\ringosc.dstage[0].id.d2 ),
+ .TE(\ringosc.dstage[0].id.trim[0] ),
+ .Z(\ringosc.dstage[0].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[0].id.delayen1 (.A(\ringosc.dstage[0].id.d0 ),
+ .TE(\ringosc.dstage[0].id.trim[1] ),
+ .Z(\ringosc.dstage[0].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[0].id.delayenb0 (.A(\ringosc.dstage[0].id.ts ),
+ .TE_B(\ringosc.dstage[0].id.trim[0] ),
+ .Z(\ringosc.dstage[0].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[0].id.delayenb1 (.A(\ringosc.dstage[0].id.ts ),
+ .TE_B(\ringosc.dstage[0].id.trim[1] ),
+ .Z(\ringosc.dstage[0].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[0].id.delayint0 (.A(\ringosc.dstage[0].id.d1 ),
+ .Y(\ringosc.dstage[0].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[10].id.delaybuf0 (.A(\ringosc.dstage[10].id.in ),
+ .X(\ringosc.dstage[10].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[10].id.delaybuf1 (.A(\ringosc.dstage[10].id.ts ),
+ .X(\ringosc.dstage[10].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[10].id.delayen0 (.A(\ringosc.dstage[10].id.d2 ),
+ .TE(\ringosc.dstage[10].id.trim[0] ),
+ .Z(\ringosc.dstage[10].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[10].id.delayen1 (.A(\ringosc.dstage[10].id.d0 ),
+ .TE(\ringosc.dstage[10].id.trim[1] ),
+ .Z(\ringosc.dstage[10].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[10].id.delayenb0 (.A(\ringosc.dstage[10].id.ts ),
+ .TE_B(\ringosc.dstage[10].id.trim[0] ),
+ .Z(\ringosc.dstage[10].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[10].id.delayenb1 (.A(\ringosc.dstage[10].id.ts ),
+ .TE_B(\ringosc.dstage[10].id.trim[1] ),
+ .Z(\ringosc.dstage[10].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[10].id.delayint0 (.A(\ringosc.dstage[10].id.d1 ),
+ .Y(\ringosc.dstage[10].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[11].id.delaybuf0 (.A(\ringosc.dstage[10].id.out ),
+ .X(\ringosc.dstage[11].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[11].id.delaybuf1 (.A(\ringosc.dstage[11].id.ts ),
+ .X(\ringosc.dstage[11].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[11].id.delayen0 (.A(\ringosc.dstage[11].id.d2 ),
+ .TE(\ringosc.dstage[11].id.trim[0] ),
+ .Z(\ringosc.dstage[11].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[11].id.delayen1 (.A(\ringosc.dstage[11].id.d0 ),
+ .TE(\ringosc.dstage[11].id.trim[1] ),
+ .Z(\ringosc.dstage[11].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[11].id.delayenb0 (.A(\ringosc.dstage[11].id.ts ),
+ .TE_B(\ringosc.dstage[11].id.trim[0] ),
+ .Z(\ringosc.dstage[11].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[11].id.delayenb1 (.A(\ringosc.dstage[11].id.ts ),
+ .TE_B(\ringosc.dstage[11].id.trim[1] ),
+ .Z(\ringosc.dstage[11].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[11].id.delayint0 (.A(\ringosc.dstage[11].id.d1 ),
+ .Y(\ringosc.dstage[11].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[1].id.delaybuf0 (.A(\ringosc.dstage[0].id.out ),
+ .X(\ringosc.dstage[1].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[1].id.delaybuf1 (.A(\ringosc.dstage[1].id.ts ),
+ .X(\ringosc.dstage[1].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[1].id.delayen0 (.A(\ringosc.dstage[1].id.d2 ),
+ .TE(\ringosc.dstage[1].id.trim[0] ),
+ .Z(\ringosc.dstage[1].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[1].id.delayen1 (.A(\ringosc.dstage[1].id.d0 ),
+ .TE(\ringosc.dstage[1].id.trim[1] ),
+ .Z(\ringosc.dstage[1].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[1].id.delayenb0 (.A(\ringosc.dstage[1].id.ts ),
+ .TE_B(\ringosc.dstage[1].id.trim[0] ),
+ .Z(\ringosc.dstage[1].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[1].id.delayenb1 (.A(\ringosc.dstage[1].id.ts ),
+ .TE_B(\ringosc.dstage[1].id.trim[1] ),
+ .Z(\ringosc.dstage[1].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[1].id.delayint0 (.A(\ringosc.dstage[1].id.d1 ),
+ .Y(\ringosc.dstage[1].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[2].id.delaybuf0 (.A(\ringosc.dstage[1].id.out ),
+ .X(\ringosc.dstage[2].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[2].id.delaybuf1 (.A(\ringosc.dstage[2].id.ts ),
+ .X(\ringosc.dstage[2].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[2].id.delayen0 (.A(\ringosc.dstage[2].id.d2 ),
+ .TE(\ringosc.dstage[2].id.trim[0] ),
+ .Z(\ringosc.dstage[2].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[2].id.delayen1 (.A(\ringosc.dstage[2].id.d0 ),
+ .TE(\ringosc.dstage[2].id.trim[1] ),
+ .Z(\ringosc.dstage[2].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[2].id.delayenb0 (.A(\ringosc.dstage[2].id.ts ),
+ .TE_B(\ringosc.dstage[2].id.trim[0] ),
+ .Z(\ringosc.dstage[2].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[2].id.delayenb1 (.A(\ringosc.dstage[2].id.ts ),
+ .TE_B(\ringosc.dstage[2].id.trim[1] ),
+ .Z(\ringosc.dstage[2].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[2].id.delayint0 (.A(\ringosc.dstage[2].id.d1 ),
+ .Y(\ringosc.dstage[2].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[3].id.delaybuf0 (.A(\ringosc.dstage[2].id.out ),
+ .X(\ringosc.dstage[3].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[3].id.delaybuf1 (.A(\ringosc.dstage[3].id.ts ),
+ .X(\ringosc.dstage[3].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[3].id.delayen0 (.A(\ringosc.dstage[3].id.d2 ),
+ .TE(\ringosc.dstage[3].id.trim[0] ),
+ .Z(\ringosc.dstage[3].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[3].id.delayen1 (.A(\ringosc.dstage[3].id.d0 ),
+ .TE(\ringosc.dstage[3].id.trim[1] ),
+ .Z(\ringosc.dstage[3].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[3].id.delayenb0 (.A(\ringosc.dstage[3].id.ts ),
+ .TE_B(\ringosc.dstage[3].id.trim[0] ),
+ .Z(\ringosc.dstage[3].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[3].id.delayenb1 (.A(\ringosc.dstage[3].id.ts ),
+ .TE_B(\ringosc.dstage[3].id.trim[1] ),
+ .Z(\ringosc.dstage[3].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[3].id.delayint0 (.A(\ringosc.dstage[3].id.d1 ),
+ .Y(\ringosc.dstage[3].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[4].id.delaybuf0 (.A(\ringosc.dstage[3].id.out ),
+ .X(\ringosc.dstage[4].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[4].id.delaybuf1 (.A(\ringosc.dstage[4].id.ts ),
+ .X(\ringosc.dstage[4].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[4].id.delayen0 (.A(\ringosc.dstage[4].id.d2 ),
+ .TE(\ringosc.dstage[4].id.trim[0] ),
+ .Z(\ringosc.dstage[4].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[4].id.delayen1 (.A(\ringosc.dstage[4].id.d0 ),
+ .TE(\ringosc.dstage[4].id.trim[1] ),
+ .Z(\ringosc.dstage[4].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[4].id.delayenb0 (.A(\ringosc.dstage[4].id.ts ),
+ .TE_B(\ringosc.dstage[4].id.trim[0] ),
+ .Z(\ringosc.dstage[4].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[4].id.delayenb1 (.A(\ringosc.dstage[4].id.ts ),
+ .TE_B(\ringosc.dstage[4].id.trim[1] ),
+ .Z(\ringosc.dstage[4].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[4].id.delayint0 (.A(\ringosc.dstage[4].id.d1 ),
+ .Y(\ringosc.dstage[4].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[5].id.delaybuf0 (.A(\ringosc.dstage[4].id.out ),
+ .X(\ringosc.dstage[5].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[5].id.delaybuf1 (.A(\ringosc.dstage[5].id.ts ),
+ .X(\ringosc.dstage[5].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[5].id.delayen0 (.A(\ringosc.dstage[5].id.d2 ),
+ .TE(\ringosc.dstage[5].id.trim[0] ),
+ .Z(\ringosc.dstage[5].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[5].id.delayen1 (.A(\ringosc.dstage[5].id.d0 ),
+ .TE(\ringosc.dstage[5].id.trim[1] ),
+ .Z(\ringosc.dstage[5].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[5].id.delayenb0 (.A(\ringosc.dstage[5].id.ts ),
+ .TE_B(\ringosc.dstage[5].id.trim[0] ),
+ .Z(\ringosc.dstage[5].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[5].id.delayenb1 (.A(\ringosc.dstage[5].id.ts ),
+ .TE_B(\ringosc.dstage[5].id.trim[1] ),
+ .Z(\ringosc.dstage[5].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[5].id.delayint0 (.A(\ringosc.dstage[5].id.d1 ),
+ .Y(\ringosc.dstage[5].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[6].id.delaybuf0 (.A(\ringosc.dstage[5].id.out ),
+ .X(\ringosc.dstage[6].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[6].id.delaybuf1 (.A(\ringosc.dstage[6].id.ts ),
+ .X(\ringosc.dstage[6].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[6].id.delayen0 (.A(\ringosc.dstage[6].id.d2 ),
+ .TE(\ringosc.dstage[6].id.trim[0] ),
+ .Z(\ringosc.dstage[6].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[6].id.delayen1 (.A(\ringosc.dstage[6].id.d0 ),
+ .TE(\ringosc.dstage[6].id.trim[1] ),
+ .Z(\ringosc.dstage[6].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[6].id.delayenb0 (.A(\ringosc.dstage[6].id.ts ),
+ .TE_B(\ringosc.dstage[6].id.trim[0] ),
+ .Z(\ringosc.dstage[6].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[6].id.delayenb1 (.A(\ringosc.dstage[6].id.ts ),
+ .TE_B(\ringosc.dstage[6].id.trim[1] ),
+ .Z(\ringosc.dstage[6].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[6].id.delayint0 (.A(\ringosc.dstage[6].id.d1 ),
+ .Y(\ringosc.dstage[6].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[7].id.delaybuf0 (.A(\ringosc.dstage[6].id.out ),
+ .X(\ringosc.dstage[7].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[7].id.delaybuf1 (.A(\ringosc.dstage[7].id.ts ),
+ .X(\ringosc.dstage[7].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[7].id.delayen0 (.A(\ringosc.dstage[7].id.d2 ),
+ .TE(\ringosc.dstage[7].id.trim[0] ),
+ .Z(\ringosc.dstage[7].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[7].id.delayen1 (.A(\ringosc.dstage[7].id.d0 ),
+ .TE(\ringosc.dstage[7].id.trim[1] ),
+ .Z(\ringosc.dstage[7].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[7].id.delayenb0 (.A(\ringosc.dstage[7].id.ts ),
+ .TE_B(\ringosc.dstage[7].id.trim[0] ),
+ .Z(\ringosc.dstage[7].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[7].id.delayenb1 (.A(\ringosc.dstage[7].id.ts ),
+ .TE_B(\ringosc.dstage[7].id.trim[1] ),
+ .Z(\ringosc.dstage[7].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[7].id.delayint0 (.A(\ringosc.dstage[7].id.d1 ),
+ .Y(\ringosc.dstage[7].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[8].id.delaybuf0 (.A(\ringosc.dstage[7].id.out ),
+ .X(\ringosc.dstage[8].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[8].id.delaybuf1 (.A(\ringosc.dstage[8].id.ts ),
+ .X(\ringosc.dstage[8].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[8].id.delayen0 (.A(\ringosc.dstage[8].id.d2 ),
+ .TE(\ringosc.dstage[8].id.trim[0] ),
+ .Z(\ringosc.dstage[8].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[8].id.delayen1 (.A(\ringosc.dstage[8].id.d0 ),
+ .TE(\ringosc.dstage[8].id.trim[1] ),
+ .Z(\ringosc.dstage[8].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[8].id.delayenb0 (.A(\ringosc.dstage[8].id.ts ),
+ .TE_B(\ringosc.dstage[8].id.trim[0] ),
+ .Z(\ringosc.dstage[8].id.out ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[8].id.delayenb1 (.A(\ringosc.dstage[8].id.ts ),
+ .TE_B(\ringosc.dstage[8].id.trim[1] ),
+ .Z(\ringosc.dstage[8].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[8].id.delayint0 (.A(\ringosc.dstage[8].id.d1 ),
+ .Y(\ringosc.dstage[8].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \ringosc.dstage[9].id.delaybuf0 (.A(\ringosc.dstage[8].id.out ),
+ .X(\ringosc.dstage[9].id.ts ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.dstage[9].id.delaybuf1 (.A(\ringosc.dstage[9].id.ts ),
+ .X(\ringosc.dstage[9].id.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[9].id.delayen0 (.A(\ringosc.dstage[9].id.d2 ),
+ .TE(\ringosc.dstage[9].id.trim[0] ),
+ .Z(\ringosc.dstage[10].id.in ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.dstage[9].id.delayen1 (.A(\ringosc.dstage[9].id.d0 ),
+ .TE(\ringosc.dstage[9].id.trim[1] ),
+ .Z(\ringosc.dstage[9].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.dstage[9].id.delayenb0 (.A(\ringosc.dstage[9].id.ts ),
+ .TE_B(\ringosc.dstage[9].id.trim[0] ),
+ .Z(\ringosc.dstage[10].id.in ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.dstage[9].id.delayenb1 (.A(\ringosc.dstage[9].id.ts ),
+ .TE_B(\ringosc.dstage[9].id.trim[1] ),
+ .Z(\ringosc.dstage[9].id.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.dstage[9].id.delayint0 (.A(\ringosc.dstage[9].id.d1 ),
+ .Y(\ringosc.dstage[9].id.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 \ringosc.ibufp00 (.A(\ringosc.dstage[0].id.in ),
+ .Y(\ringosc.c[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 \ringosc.ibufp01 (.A(\ringosc.c[0] ),
+ .Y(\pll_control.clock ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 \ringosc.ibufp10 (.A(\ringosc.dstage[5].id.out ),
+ .Y(\ringosc.c[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 \ringosc.ibufp11 (.A(\ringosc.c[1] ),
+ .Y(clockp[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \ringosc.iss.const1 (.HI(\ringosc.iss.one ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 \ringosc.iss.ctrlen0 (.A(\ringosc.iss.reset ),
+ .B(\ringosc.iss.trim[0] ),
+ .X(\ringosc.iss.ctrl0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 \ringosc.iss.delaybuf0 (.A(\ringosc.dstage[11].id.out ),
+ .X(\ringosc.iss.d0 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.iss.delayen0 (.A(\ringosc.iss.d2 ),
+ .TE(\ringosc.iss.trim[0] ),
+ .Z(\ringosc.dstage[0].id.in ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_2 \ringosc.iss.delayen1 (.A(\ringosc.iss.d0 ),
+ .TE(\ringosc.iss.trim[1] ),
+ .Z(\ringosc.iss.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_8 \ringosc.iss.delayenb0 (.A(\ringosc.dstage[11].id.out ),
+ .TE_B(\ringosc.iss.ctrl0 ),
+ .Z(\ringosc.dstage[0].id.in ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvn_4 \ringosc.iss.delayenb1 (.A(\ringosc.dstage[11].id.out ),
+ .TE_B(\ringosc.iss.trim[1] ),
+ .Z(\ringosc.iss.d1 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_1 \ringosc.iss.delayint0 (.A(\ringosc.iss.d1 ),
+ .Y(\ringosc.iss.d2 ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__einvp_1 \ringosc.iss.reseten0 (.A(\ringosc.iss.one ),
+ .TE(\ringosc.iss.reset ),
+ .Z(\ringosc.dstage[0].id.in ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+endmodule
diff --git a/caravel/verilog/gl/gpio_control_block.v b/caravel/verilog/gl/gpio_control_block.v
new file mode 100644
index 0000000..bb9beae
--- /dev/null
+++ b/caravel/verilog/gl/gpio_control_block.v
@@ -0,0 +1,2037 @@
+module gpio_control_block (mgmt_gpio_in,
+ mgmt_gpio_oeb,
+ mgmt_gpio_out,
+ one,
+ pad_gpio_ana_en,
+ pad_gpio_ana_pol,
+ pad_gpio_ana_sel,
+ pad_gpio_holdover,
+ pad_gpio_ib_mode_sel,
+ pad_gpio_in,
+ pad_gpio_inenb,
+ pad_gpio_out,
+ pad_gpio_outenb,
+ pad_gpio_slow_sel,
+ pad_gpio_vtrip_sel,
+ resetn,
+ resetn_out,
+ serial_clock,
+ serial_clock_out,
+ serial_data_in,
+ serial_data_out,
+ serial_load,
+ serial_load_out,
+ user_gpio_in,
+ user_gpio_oeb,
+ user_gpio_out,
+ vccd,
+ vccd1,
+ vssd,
+ vssd1,
+ zero,
+ gpio_defaults,
+ pad_gpio_dm);
+ output mgmt_gpio_in;
+ input mgmt_gpio_oeb;
+ input mgmt_gpio_out;
+ output one;
+ output pad_gpio_ana_en;
+ output pad_gpio_ana_pol;
+ output pad_gpio_ana_sel;
+ output pad_gpio_holdover;
+ output pad_gpio_ib_mode_sel;
+ input pad_gpio_in;
+ output pad_gpio_inenb;
+ output pad_gpio_out;
+ output pad_gpio_outenb;
+ output pad_gpio_slow_sel;
+ output pad_gpio_vtrip_sel;
+ input resetn;
+ output resetn_out;
+ input serial_clock;
+ output serial_clock_out;
+ input serial_data_in;
+ output serial_data_out;
+ input serial_load;
+ output serial_load_out;
+ output user_gpio_in;
+ input user_gpio_oeb;
+ input user_gpio_out;
+ input vccd;
+ input vccd1;
+ input vssd;
+ input vssd1;
+ output zero;
+ input [12:0] gpio_defaults;
+ output [2:0] pad_gpio_dm;
+
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire clknet_0_serial_clock;
+ wire clknet_1_0_0_serial_clock;
+ wire clknet_1_1_0_serial_clock;
+ wire gpio_logic1;
+ wire gpio_outenb;
+ wire mgmt_ena;
+ wire net1;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net14;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net2;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net3;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net4;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net5;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net6;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire serial_data_pre;
+ wire \shift_register[0] ;
+ wire \shift_register[10] ;
+ wire \shift_register[11] ;
+ wire \shift_register[1] ;
+ wire \shift_register[2] ;
+ wire \shift_register[3] ;
+ wire \shift_register[4] ;
+ wire \shift_register[5] ;
+ wire \shift_register[6] ;
+ wire \shift_register[7] ;
+ wire \shift_register[8] ;
+ wire \shift_register[9] ;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA_0 (.DIODE(one),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_1 (.DIODE(one),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_2 (.DIODE(pad_gpio_in),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_3 (.DIODE(serial_data_in),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_4 (.DIODE(user_gpio_oeb),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_5 (.DIODE(mgmt_gpio_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_6 (.DIODE(user_gpio_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_0_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_0_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_49 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_0_52 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_0_64 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_90 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_45 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_30 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_45 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_68 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_79 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_1_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_1_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_73 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_80 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_31 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_46 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_50 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_68 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_32 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_40 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_36 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_46 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_38 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_39 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _102_ (.A(net17),
+ .B_N(net11),
+ .X(_073_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _103_ (.A(_073_),
+ .X(_043_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _104_ (.A(net17),
+ .B(net11),
+ .X(_074_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _105_ (.A(_074_),
+ .X(_042_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _106__1 (.A(serial_load),
+ .Y(net40),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _106__2 (.A(serial_load),
+ .Y(net41),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _106__3 (.A(serial_load),
+ .Y(net42),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _106__4 (.A(serial_load),
+ .Y(net43),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _106__5 (.A(serial_load),
+ .Y(net44),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _107_ (.A(net44),
+ .X(_041_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _108_ (.A(net17),
+ .B_N(net10),
+ .X(_076_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _109_ (.A(_076_),
+ .X(_040_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _110_ (.A(net17),
+ .B(net10),
+ .X(_077_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _111_ (.A(_077_),
+ .X(_039_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _112_ (.A(_041_),
+ .X(_078_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _113_ (.A(_078_),
+ .X(_038_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _114_ (.A(net17),
+ .B_N(net9),
+ .X(_079_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _115_ (.A(_079_),
+ .X(_037_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _116_ (.A(net17),
+ .B(net9),
+ .X(_080_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _117_ (.A(_080_),
+ .X(_036_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _118_ (.A(_041_),
+ .X(_081_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _119_ (.A(_081_),
+ .X(_035_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _120_ (.A(net17),
+ .B_N(net4),
+ .X(_082_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _121_ (.A(_082_),
+ .X(_034_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _122_ (.A(net17),
+ .B(net4),
+ .X(_083_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _123_ (.A(_083_),
+ .X(_033_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _124_ (.A(_041_),
+ .X(_084_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _125_ (.A(_084_),
+ .X(_032_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _126_ (.A(net17),
+ .B_N(net3),
+ .X(_085_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _127_ (.A(_085_),
+ .X(_031_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _128_ (.A(net17),
+ .B(net3),
+ .X(_086_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _129_ (.A(_086_),
+ .X(_030_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _130_ (.A(_041_),
+ .X(_087_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _131_ (.A(_087_),
+ .X(_029_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _132_ (.A(net17),
+ .B_N(net2),
+ .X(_088_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _133_ (.A(_088_),
+ .X(_028_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _134_ (.A(net17),
+ .B(net2),
+ .X(_045_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _135_ (.A(_045_),
+ .X(_027_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _136_ (.A(net43),
+ .X(_046_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _137_ (.A(_046_),
+ .X(_047_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _138_ (.A(_047_),
+ .X(_026_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _139_ (.A(net17),
+ .B_N(net5),
+ .X(_048_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _140_ (.A(_048_),
+ .X(_025_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _141_ (.A(net17),
+ .B(net5),
+ .X(_049_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _142_ (.A(_049_),
+ .X(_024_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _143_ (.A(_046_),
+ .X(_050_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _144_ (.A(_050_),
+ .X(_023_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _145_ (.A(net17),
+ .B_N(net8),
+ .X(_051_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _146_ (.A(_051_),
+ .X(_022_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _147_ (.A(net17),
+ .B(net8),
+ .X(_052_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _148_ (.A(_052_),
+ .X(_021_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _149_ (.A(_046_),
+ .X(_053_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _150_ (.A(_053_),
+ .X(_020_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _151_ (.A(net17),
+ .B_N(net7),
+ .X(_054_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _152_ (.A(_054_),
+ .X(_019_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _153_ (.A(net17),
+ .B(net7),
+ .X(_055_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _154_ (.A(_055_),
+ .X(_018_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _155_ (.A(_046_),
+ .X(_056_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _156_ (.A(_056_),
+ .X(_017_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _157_ (.A(net17),
+ .B_N(net13),
+ .X(_057_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _158_ (.A(_057_),
+ .X(_016_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _159_ (.A(net17),
+ .B(net13),
+ .X(_058_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _160_ (.A(_058_),
+ .X(_015_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _161_ (.A(_046_),
+ .X(_059_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _162_ (.A(_059_),
+ .X(_014_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _163_ (.A(net17),
+ .B_N(net12),
+ .X(_060_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _164_ (.A(_060_),
+ .X(_013_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _165_ (.A(net17),
+ .B(net12),
+ .X(_061_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _166_ (.A(_061_),
+ .X(_012_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _167_ (.A(net42),
+ .X(_062_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _168_ (.A(_062_),
+ .X(_011_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _169_ (.A(net17),
+ .B_N(net6),
+ .X(_063_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _170_ (.A(_063_),
+ .X(_010_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _171_ (.A(net17),
+ .B(net6),
+ .X(_064_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _172_ (.A(_064_),
+ .X(_009_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _173_ (.A(net41),
+ .X(_065_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _174_ (.A(_065_),
+ .X(_008_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _175_ (.A(net17),
+ .B_N(net1),
+ .X(_066_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _176_ (.A(_066_),
+ .X(_007_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2_1 _177_ (.A(net1),
+ .B(net17),
+ .X(_067_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _178_ (.A(_067_),
+ .X(_006_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _179_ (.A(net30),
+ .B_N(gpio_outenb),
+ .X(_068_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _180_ (.A(_068_),
+ .X(_089_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 _181_ (.A(gpio_outenb),
+ .B(net14),
+ .X(_069_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _182_ (.A(_069_),
+ .X(_000_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__or2b_1 _183_ (.A(net27),
+ .B_N(net26),
+ .X(_070_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _184_ (.A(_070_),
+ .X(_002_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _185_ (.A(net16),
+ .Y(_005_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 _186_ (.A(one),
+ .B(serial_data_pre),
+ .X(_071_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _187_ (.A(_071_),
+ .X(net37),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _188_ (.A(net40),
+ .X(_072_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_1 _189_ (.A(_072_),
+ .X(_044_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 _190_ (.A(net17),
+ .X(net35),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 _191_ (.A(clknet_1_1_0_serial_clock),
+ .X(net36),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 _192_ (.A(serial_load),
+ .X(net38),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_1 _193_ (.A0(net19),
+ .A1(_000_),
+ .S(mgmt_ena),
+ .X(net32),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_1 _194_ (.A0(_001_),
+ .A1(net15),
+ .S(_002_),
+ .X(_003_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_1 _195_ (.A0(net15),
+ .A1(_003_),
+ .S(net14),
+ .X(_004_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_1 _196_ (.A0(net20),
+ .A1(_004_),
+ .S(mgmt_ena),
+ .X(net31),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__ebufn_1 _197_ (.A(net16),
+ .TE_B(_089_),
+ .Z(mgmt_gpio_in),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _198_ (.D(net55),
+ .Q(mgmt_ena),
+ .Q_N(_090_),
+ .RESET_B(_006_),
+ .SET_B(_007_),
+ .CLK_N(_008_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _199_ (.D(net56),
+ .Q(net28),
+ .Q_N(_091_),
+ .RESET_B(_009_),
+ .SET_B(_010_),
+ .CLK_N(_011_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _200_ (.D(net47),
+ .Q(net33),
+ .Q_N(_092_),
+ .RESET_B(_012_),
+ .SET_B(_013_),
+ .CLK_N(_014_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _201_ (.D(net45),
+ .Q(net34),
+ .Q_N(_093_),
+ .RESET_B(_015_),
+ .SET_B(_016_),
+ .CLK_N(_017_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _202_ (.D(net48),
+ .Q(net30),
+ .Q_N(_094_),
+ .RESET_B(_018_),
+ .SET_B(_019_),
+ .CLK_N(_020_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _203_ (.D(net46),
+ .Q(net29),
+ .Q_N(_095_),
+ .RESET_B(_021_),
+ .SET_B(_022_),
+ .CLK_N(_023_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _204_ (.D(net62),
+ .Q(gpio_outenb),
+ .Q_N(_096_),
+ .RESET_B(_024_),
+ .SET_B(_025_),
+ .CLK_N(_026_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _205_ (.D(net53),
+ .Q(net25),
+ .Q_N(_001_),
+ .RESET_B(_027_),
+ .SET_B(_028_),
+ .CLK_N(_029_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _206_ (.D(net51),
+ .Q(net26),
+ .Q_N(_097_),
+ .RESET_B(_030_),
+ .SET_B(_031_),
+ .CLK_N(_032_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _207_ (.D(net63),
+ .Q(net27),
+ .Q_N(_098_),
+ .RESET_B(_033_),
+ .SET_B(_034_),
+ .CLK_N(_035_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _208_ (.D(net52),
+ .Q(net22),
+ .Q_N(_099_),
+ .RESET_B(_036_),
+ .SET_B(_037_),
+ .CLK_N(_038_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _209_ (.D(net59),
+ .Q(net24),
+ .Q_N(_100_),
+ .RESET_B(_039_),
+ .SET_B(_040_),
+ .CLK_N(_041_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbn_1 _210_ (.D(net54),
+ .Q(net23),
+ .Q_N(_101_),
+ .RESET_B(_042_),
+ .SET_B(_043_),
+ .CLK_N(_044_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _211_ (.D(net18),
+ .Q(\shift_register[0] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _212_ (.D(\shift_register[0] ),
+ .Q(\shift_register[1] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _213_ (.D(\shift_register[1] ),
+ .Q(\shift_register[2] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _214_ (.D(\shift_register[2] ),
+ .Q(\shift_register[3] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _215_ (.D(\shift_register[3] ),
+ .Q(\shift_register[4] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _216_ (.D(\shift_register[4] ),
+ .Q(\shift_register[5] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _217_ (.D(\shift_register[5] ),
+ .Q(\shift_register[6] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _218_ (.D(\shift_register[6] ),
+ .Q(\shift_register[7] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _219_ (.D(\shift_register[7] ),
+ .Q(\shift_register[8] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _220_ (.D(\shift_register[8] ),
+ .Q(\shift_register[9] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _221_ (.D(\shift_register[9] ),
+ .Q(\shift_register[10] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _222_ (.D(\shift_register[10] ),
+ .Q(\shift_register[11] ),
+ .RESET_B(net17),
+ .CLK(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfrtp_1 _223_ (.D(\shift_register[11] ),
+ .Q(serial_data_pre),
+ .RESET_B(net17),
+ .CLK(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_clock (.A(serial_clock),
+ .X(clknet_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_serial_clock (.A(clknet_0_serial_clock),
+ .X(clknet_1_0_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_serial_clock (.A(clknet_0_serial_clock),
+ .X(clknet_1_1_0_serial_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 const_source (.HI(one),
+ .LO(zero),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 gpio_in_buf (.A(_005_),
+ .TE(gpio_logic1),
+ .Z(net39),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ gpio_logic_high gpio_logic_high (.gpio_logic1(gpio_logic1),
+ .vccd1(vccd1),
+ .vssd1(vssd1));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(net58),
+ .X(net45),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold10 (.A(\shift_register[7] ),
+ .X(net54),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold11 (.A(\shift_register[0] ),
+ .X(net55),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold12 (.A(\shift_register[2] ),
+ .X(net56),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold13 (.A(\shift_register[4] ),
+ .X(net57),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold14 (.A(\shift_register[9] ),
+ .X(net58),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold15 (.A(\shift_register[6] ),
+ .X(net59),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold16 (.A(\shift_register[8] ),
+ .X(net60),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold17 (.A(\shift_register[3] ),
+ .X(net61),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold18 (.A(net49),
+ .X(net62),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold19 (.A(net50),
+ .X(net63),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(net57),
+ .X(net46),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold20 (.A(\shift_register[11] ),
+ .X(net64),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold21 (.A(\shift_register[5] ),
+ .X(net65),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold22 (.A(\shift_register[10] ),
+ .X(net66),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold3 (.A(net60),
+ .X(net47),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold4 (.A(net61),
+ .X(net48),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold5 (.A(\shift_register[1] ),
+ .X(net49),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold6 (.A(serial_data_pre),
+ .X(net50),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold7 (.A(net64),
+ .X(net51),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold8 (.A(net65),
+ .X(net52),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold9 (.A(net66),
+ .X(net53),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input1 (.A(gpio_defaults[0]),
+ .X(net1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input10 (.A(gpio_defaults[6]),
+ .X(net10),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input11 (.A(gpio_defaults[7]),
+ .X(net11),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input12 (.A(gpio_defaults[8]),
+ .X(net12),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input13 (.A(gpio_defaults[9]),
+ .X(net13),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input14 (.A(mgmt_gpio_oeb),
+ .X(net14),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input15 (.A(mgmt_gpio_out),
+ .X(net15),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input16 (.A(pad_gpio_in),
+ .X(net16),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input17 (.A(resetn),
+ .X(net17),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input18 (.A(serial_data_in),
+ .X(net18),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input19 (.A(user_gpio_oeb),
+ .X(net19),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input2 (.A(gpio_defaults[10]),
+ .X(net2),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input20 (.A(user_gpio_out),
+ .X(net20),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input3 (.A(gpio_defaults[11]),
+ .X(net3),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input4 (.A(gpio_defaults[12]),
+ .X(net4),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input5 (.A(gpio_defaults[1]),
+ .X(net5),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input6 (.A(gpio_defaults[2]),
+ .X(net6),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input7 (.A(gpio_defaults[3]),
+ .X(net7),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input8 (.A(gpio_defaults[4]),
+ .X(net8),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input9 (.A(gpio_defaults[5]),
+ .X(net9),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output22 (.A(net22),
+ .X(pad_gpio_ana_en),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output23 (.A(net23),
+ .X(pad_gpio_ana_pol),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output24 (.A(net24),
+ .X(pad_gpio_ana_sel),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output25 (.A(net25),
+ .X(pad_gpio_dm[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output26 (.A(net26),
+ .X(pad_gpio_dm[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output27 (.A(net27),
+ .X(pad_gpio_dm[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output28 (.A(net28),
+ .X(pad_gpio_holdover),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output29 (.A(net29),
+ .X(pad_gpio_ib_mode_sel),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output30 (.A(net30),
+ .X(pad_gpio_inenb),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output31 (.A(net31),
+ .X(pad_gpio_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output32 (.A(net32),
+ .X(pad_gpio_outenb),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output33 (.A(net33),
+ .X(pad_gpio_slow_sel),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output34 (.A(net34),
+ .X(pad_gpio_vtrip_sel),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output35 (.A(net35),
+ .X(resetn_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 output36 (.A(net36),
+ .X(serial_clock_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output37 (.A(net37),
+ .X(serial_data_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 output38 (.A(net38),
+ .X(serial_load_out),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output39 (.A(net39),
+ .X(user_gpio_in),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+endmodule
diff --git a/caravel/verilog/gl/gpio_defaults_block.v b/caravel/verilog/gl/gpio_defaults_block.v
new file mode 100644
index 0000000..34eb813
--- /dev/null
+++ b/caravel/verilog/gl/gpio_defaults_block.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_low[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_low[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/caravel/verilog/gl/gpio_defaults_block_0403.v b/caravel/verilog/gl/gpio_defaults_block_0403.v
new file mode 100644
index 0000000..33fbfde
--- /dev/null
+++ b/caravel/verilog/gl/gpio_defaults_block_0403.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0403 (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_high[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_low[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/caravel/verilog/gl/gpio_defaults_block_1803.v b/caravel/verilog/gl/gpio_defaults_block_1803.v
new file mode 100644
index 0000000..13ad29a
--- /dev/null
+++ b/caravel/verilog/gl/gpio_defaults_block_1803.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1803 (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/caravel/verilog/gl/gpio_logic_high.v b/caravel/verilog/gl/gpio_logic_high.v
new file mode 100644
index 0000000..dbfbcf6
--- /dev/null
+++ b/caravel/verilog/gl/gpio_logic_high.v
@@ -0,0 +1,108 @@
+module gpio_logic_high (gpio_logic1,
+ vccd1,
+ vssd1);
+ output gpio_logic1;
+ input vccd1;
+ input vssd1;
+
+
+ sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_11 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_1_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_2_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_2_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_4_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 gpio_logic_high (.HI(gpio_logic1),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+endmodule
diff --git a/caravel/verilog/gl/housekeeping.v b/caravel/verilog/gl/housekeeping.v
new file mode 100644
index 0000000..c7ec65d
--- /dev/null
+++ b/caravel/verilog/gl/housekeeping.v
@@ -0,0 +1,100779 @@
+module housekeeping (VGND,
+ VPWR,
+ debug_in,
+ debug_mode,
+ debug_oeb,
+ debug_out,
+ pad_flash_clk,
+ pad_flash_clk_oeb,
+ pad_flash_csb,
+ pad_flash_csb_oeb,
+ pad_flash_io0_di,
+ pad_flash_io0_do,
+ pad_flash_io0_ieb,
+ pad_flash_io0_oeb,
+ pad_flash_io1_di,
+ pad_flash_io1_do,
+ pad_flash_io1_ieb,
+ pad_flash_io1_oeb,
+ pll_bypass,
+ pll_dco_ena,
+ pll_ena,
+ porb,
+ qspi_enabled,
+ reset,
+ ser_rx,
+ ser_tx,
+ serial_clock,
+ serial_data_1,
+ serial_data_2,
+ serial_load,
+ serial_resetn,
+ spi_csb,
+ spi_enabled,
+ spi_sck,
+ spi_sdi,
+ spi_sdo,
+ spi_sdoenb,
+ spimemio_flash_clk,
+ spimemio_flash_csb,
+ spimemio_flash_io0_di,
+ spimemio_flash_io0_do,
+ spimemio_flash_io0_oeb,
+ spimemio_flash_io1_di,
+ spimemio_flash_io1_do,
+ spimemio_flash_io1_oeb,
+ spimemio_flash_io2_di,
+ spimemio_flash_io2_do,
+ spimemio_flash_io2_oeb,
+ spimemio_flash_io3_di,
+ spimemio_flash_io3_do,
+ spimemio_flash_io3_oeb,
+ sram_ro_clk,
+ sram_ro_csb,
+ trap,
+ uart_enabled,
+ user_clock,
+ usr1_vcc_pwrgood,
+ usr1_vdd_pwrgood,
+ usr2_vcc_pwrgood,
+ usr2_vdd_pwrgood,
+ wb_ack_o,
+ wb_clk_i,
+ wb_cyc_i,
+ wb_rstn_i,
+ wb_stb_i,
+ wb_we_i,
+ irq,
+ mask_rev_in,
+ mgmt_gpio_in,
+ mgmt_gpio_oeb,
+ mgmt_gpio_out,
+ pll90_sel,
+ pll_div,
+ pll_sel,
+ pll_trim,
+ pwr_ctrl_out,
+ sram_ro_addr,
+ sram_ro_data,
+ wb_adr_i,
+ wb_dat_i,
+ wb_dat_o,
+ wb_sel_i);
+ input VGND;
+ input VPWR;
+ output debug_in;
+ input debug_mode;
+ input debug_oeb;
+ input debug_out;
+ output pad_flash_clk;
+ output pad_flash_clk_oeb;
+ output pad_flash_csb;
+ output pad_flash_csb_oeb;
+ input pad_flash_io0_di;
+ output pad_flash_io0_do;
+ output pad_flash_io0_ieb;
+ output pad_flash_io0_oeb;
+ input pad_flash_io1_di;
+ output pad_flash_io1_do;
+ output pad_flash_io1_ieb;
+ output pad_flash_io1_oeb;
+ output pll_bypass;
+ output pll_dco_ena;
+ output pll_ena;
+ input porb;
+ input qspi_enabled;
+ output reset;
+ output ser_rx;
+ input ser_tx;
+ output serial_clock;
+ output serial_data_1;
+ output serial_data_2;
+ output serial_load;
+ output serial_resetn;
+ input spi_csb;
+ input spi_enabled;
+ input spi_sck;
+ output spi_sdi;
+ input spi_sdo;
+ input spi_sdoenb;
+ input spimemio_flash_clk;
+ input spimemio_flash_csb;
+ output spimemio_flash_io0_di;
+ input spimemio_flash_io0_do;
+ input spimemio_flash_io0_oeb;
+ output spimemio_flash_io1_di;
+ input spimemio_flash_io1_do;
+ input spimemio_flash_io1_oeb;
+ output spimemio_flash_io2_di;
+ input spimemio_flash_io2_do;
+ input spimemio_flash_io2_oeb;
+ output spimemio_flash_io3_di;
+ input spimemio_flash_io3_do;
+ input spimemio_flash_io3_oeb;
+ output sram_ro_clk;
+ output sram_ro_csb;
+ input trap;
+ input uart_enabled;
+ input user_clock;
+ input usr1_vcc_pwrgood;
+ input usr1_vdd_pwrgood;
+ input usr2_vcc_pwrgood;
+ input usr2_vdd_pwrgood;
+ output wb_ack_o;
+ input wb_clk_i;
+ input wb_cyc_i;
+ input wb_rstn_i;
+ input wb_stb_i;
+ input wb_we_i;
+ output [2:0] irq;
+ input [31:0] mask_rev_in;
+ input [37:0] mgmt_gpio_in;
+ output [37:0] mgmt_gpio_oeb;
+ output [37:0] mgmt_gpio_out;
+ output [2:0] pll90_sel;
+ output [4:0] pll_div;
+ output [2:0] pll_sel;
+ output [25:0] pll_trim;
+ output [3:0] pwr_ctrl_out;
+ output [7:0] sram_ro_addr;
+ input [31:0] sram_ro_data;
+ input [31:0] wb_adr_i;
+ input [31:0] wb_dat_i;
+ output [31:0] wb_dat_o;
+ input [3:0] wb_sel_i;
+
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire _0007_;
+ wire _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire _0022_;
+ wire _0023_;
+ wire _0024_;
+ wire _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0868_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0873_;
+ wire _0874_;
+ wire _0875_;
+ wire _0876_;
+ wire _0877_;
+ wire _0878_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0908_;
+ wire _0909_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0914_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0919_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0937_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0960_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0998_;
+ wire _0999_;
+ wire _1000_;
+ wire _1001_;
+ wire _1002_;
+ wire _1003_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1015_;
+ wire _1016_;
+ wire _1017_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
+ wire _1025_;
+ wire _1026_;
+ wire _1027_;
+ wire _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire _1031_;
+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
+ wire _1046_;
+ wire _1047_;
+ wire _1048_;
+ wire _1049_;
+ wire _1050_;
+ wire _1051_;
+ wire _1052_;
+ wire _1053_;
+ wire _1054_;
+ wire _1055_;
+ wire _1056_;
+ wire _1057_;
+ wire _1058_;
+ wire _1059_;
+ wire _1060_;
+ wire _1061_;
+ wire _1062_;
+ wire _1063_;
+ wire _1064_;
+ wire _1065_;
+ wire _1066_;
+ wire _1067_;
+ wire _1068_;
+ wire _1069_;
+ wire _1070_;
+ wire _1071_;
+ wire _1072_;
+ wire _1073_;
+ wire _1074_;
+ wire _1075_;
+ wire _1076_;
+ wire _1077_;
+ wire _1078_;
+ wire _1079_;
+ wire _1080_;
+ wire _1081_;
+ wire _1082_;
+ wire _1083_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1089_;
+ wire _1090_;
+ wire _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1097_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1109_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1115_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1126_;
+ wire _1127_;
+ wire _1128_;
+ wire _1129_;
+ wire _1130_;
+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1140_;
+ wire _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire _1151_;
+ wire _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1159_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1164_;
+ wire _1165_;
+ wire _1166_;
+ wire _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1188_;
+ wire _1189_;
+ wire _1190_;
+ wire _1191_;
+ wire _1192_;
+ wire _1193_;
+ wire _1194_;
+ wire _1195_;
+ wire _1196_;
+ wire _1197_;
+ wire _1198_;
+ wire _1199_;
+ wire _1200_;
+ wire _1201_;
+ wire _1202_;
+ wire _1203_;
+ wire _1204_;
+ wire _1205_;
+ wire _1206_;
+ wire _1207_;
+ wire _1208_;
+ wire _1209_;
+ wire _1210_;
+ wire _1211_;
+ wire _1212_;
+ wire _1213_;
+ wire _1214_;
+ wire _1215_;
+ wire _1216_;
+ wire _1217_;
+ wire _1218_;
+ wire _1219_;
+ wire _1220_;
+ wire _1221_;
+ wire _1222_;
+ wire _1223_;
+ wire _1224_;
+ wire _1225_;
+ wire _1226_;
+ wire _1227_;
+ wire _1228_;
+ wire _1229_;
+ wire _1230_;
+ wire _1231_;
+ wire _1232_;
+ wire _1233_;
+ wire _1234_;
+ wire _1235_;
+ wire _1236_;
+ wire _1237_;
+ wire _1238_;
+ wire _1239_;
+ wire _1240_;
+ wire _1241_;
+ wire _1242_;
+ wire _1243_;
+ wire _1244_;
+ wire _1245_;
+ wire _1246_;
+ wire _1247_;
+ wire _1248_;
+ wire _1249_;
+ wire _1250_;
+ wire _1251_;
+ wire _1252_;
+ wire _1253_;
+ wire _1254_;
+ wire _1255_;
+ wire _1256_;
+ wire _1257_;
+ wire _1258_;
+ wire _1259_;
+ wire _1260_;
+ wire _1261_;
+ wire _1262_;
+ wire _1263_;
+ wire _1264_;
+ wire _1265_;
+ wire _1266_;
+ wire _1267_;
+ wire _1268_;
+ wire _1269_;
+ wire _1270_;
+ wire _1271_;
+ wire _1272_;
+ wire _1273_;
+ wire _1274_;
+ wire _1275_;
+ wire _1276_;
+ wire _1277_;
+ wire _1278_;
+ wire _1279_;
+ wire _1280_;
+ wire _1281_;
+ wire _1282_;
+ wire _1283_;
+ wire _1284_;
+ wire _1285_;
+ wire _1286_;
+ wire _1287_;
+ wire _1288_;
+ wire _1289_;
+ wire _1290_;
+ wire _1291_;
+ wire _1292_;
+ wire _1293_;
+ wire _1294_;
+ wire _1295_;
+ wire _1296_;
+ wire _1297_;
+ wire _1298_;
+ wire _1299_;
+ wire _1300_;
+ wire _1301_;
+ wire _1302_;
+ wire _1303_;
+ wire _1304_;
+ wire _1305_;
+ wire _1306_;
+ wire _1307_;
+ wire _1308_;
+ wire _1309_;
+ wire _1310_;
+ wire _1311_;
+ wire _1312_;
+ wire _1313_;
+ wire _1314_;
+ wire _1315_;
+ wire _1316_;
+ wire _1317_;
+ wire _1318_;
+ wire _1319_;
+ wire _1320_;
+ wire _1321_;
+ wire _1322_;
+ wire _1323_;
+ wire _1324_;
+ wire _1325_;
+ wire _1326_;
+ wire _1327_;
+ wire _1328_;
+ wire _1329_;
+ wire _1330_;
+ wire _1331_;
+ wire _1332_;
+ wire _1333_;
+ wire _1334_;
+ wire _1335_;
+ wire _1336_;
+ wire _1337_;
+ wire _1338_;
+ wire _1339_;
+ wire _1340_;
+ wire _1341_;
+ wire _1342_;
+ wire _1343_;
+ wire _1344_;
+ wire _1345_;
+ wire _1346_;
+ wire _1347_;
+ wire _1348_;
+ wire _1349_;
+ wire _1350_;
+ wire _1351_;
+ wire _1352_;
+ wire _1353_;
+ wire _1354_;
+ wire _1355_;
+ wire _1356_;
+ wire _1357_;
+ wire _1358_;
+ wire _1359_;
+ wire _1360_;
+ wire _1361_;
+ wire _1362_;
+ wire _1363_;
+ wire _1364_;
+ wire _1365_;
+ wire _1366_;
+ wire _1367_;
+ wire _1368_;
+ wire _1369_;
+ wire _1370_;
+ wire _1371_;
+ wire _1372_;
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+ wire _2015_;
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+ wire _2169_;
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+ wire _2207_;
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+ wire _2307_;
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+ wire _2401_;
+ wire _2402_;
+ wire _2403_;
+ wire _2404_;
+ wire _2405_;
+ wire _2406_;
+ wire _2407_;
+ wire _2408_;
+ wire _2409_;
+ wire _2410_;
+ wire _2411_;
+ wire _2412_;
+ wire _2413_;
+ wire _2414_;
+ wire _2415_;
+ wire _2416_;
+ wire _2417_;
+ wire _2418_;
+ wire _2419_;
+ wire _2420_;
+ wire _2421_;
+ wire _2422_;
+ wire _2423_;
+ wire _2424_;
+ wire _2425_;
+ wire _2426_;
+ wire _2427_;
+ wire _2428_;
+ wire _2429_;
+ wire _2430_;
+ wire _2431_;
+ wire _2432_;
+ wire _2433_;
+ wire _2434_;
+ wire _2435_;
+ wire _2436_;
+ wire _2437_;
+ wire _2438_;
+ wire _2439_;
+ wire _2440_;
+ wire _2441_;
+ wire _2442_;
+ wire _2443_;
+ wire _2444_;
+ wire _2445_;
+ wire _2446_;
+ wire _2447_;
+ wire _2448_;
+ wire _2449_;
+ wire _2450_;
+ wire _2451_;
+ wire _2452_;
+ wire _2453_;
+ wire _2454_;
+ wire _2455_;
+ wire _2456_;
+ wire _2457_;
+ wire _2458_;
+ wire _2459_;
+ wire _2460_;
+ wire _2461_;
+ wire _2462_;
+ wire _2463_;
+ wire _2464_;
+ wire _2465_;
+ wire _2466_;
+ wire _2467_;
+ wire _2468_;
+ wire _2469_;
+ wire _2470_;
+ wire _2471_;
+ wire _2472_;
+ wire _2473_;
+ wire _2474_;
+ wire _2475_;
+ wire _2476_;
+ wire _2477_;
+ wire _2478_;
+ wire _2479_;
+ wire _2480_;
+ wire _2481_;
+ wire _2482_;
+ wire _2483_;
+ wire _2484_;
+ wire _2485_;
+ wire _2486_;
+ wire _2487_;
+ wire _2488_;
+ wire _2489_;
+ wire _2490_;
+ wire _2491_;
+ wire _2492_;
+ wire _2493_;
+ wire _2494_;
+ wire _2495_;
+ wire _2496_;
+ wire _2497_;
+ wire _2498_;
+ wire _2499_;
+ wire _2500_;
+ wire _2501_;
+ wire _2502_;
+ wire _2503_;
+ wire _2504_;
+ wire _2505_;
+ wire _2506_;
+ wire _2507_;
+ wire _2508_;
+ wire _2509_;
+ wire _2510_;
+ wire _2511_;
+ wire _2512_;
+ wire _2513_;
+ wire _2514_;
+ wire _2515_;
+ wire _2516_;
+ wire _2517_;
+ wire _2518_;
+ wire _2519_;
+ wire _2520_;
+ wire _2521_;
+ wire _2522_;
+ wire _2523_;
+ wire _2524_;
+ wire _2525_;
+ wire _2526_;
+ wire _2527_;
+ wire _2528_;
+ wire _2529_;
+ wire _2530_;
+ wire _2531_;
+ wire _2532_;
+ wire _2533_;
+ wire _2534_;
+ wire _2535_;
+ wire _2536_;
+ wire _2537_;
+ wire _2538_;
+ wire _2539_;
+ wire _2540_;
+ wire _2541_;
+ wire _2542_;
+ wire _2543_;
+ wire _2544_;
+ wire _2545_;
+ wire _2546_;
+ wire _2547_;
+ wire _2548_;
+ wire _2549_;
+ wire _2550_;
+ wire _2551_;
+ wire _2552_;
+ wire _2553_;
+ wire _2554_;
+ wire _2555_;
+ wire _2556_;
+ wire _2557_;
+ wire _2558_;
+ wire _2559_;
+ wire _2560_;
+ wire _2561_;
+ wire _2562_;
+ wire _2563_;
+ wire _2564_;
+ wire _2565_;
+ wire _2566_;
+ wire _2567_;
+ wire _2568_;
+ wire _2569_;
+ wire _2570_;
+ wire _2571_;
+ wire _2572_;
+ wire _2573_;
+ wire _2574_;
+ wire _2575_;
+ wire _2576_;
+ wire _2577_;
+ wire _2578_;
+ wire _2579_;
+ wire _2580_;
+ wire _2581_;
+ wire _2582_;
+ wire _2583_;
+ wire _2584_;
+ wire _2585_;
+ wire _2586_;
+ wire _2587_;
+ wire _2588_;
+ wire _2589_;
+ wire _2590_;
+ wire _2591_;
+ wire _2592_;
+ wire _2593_;
+ wire _2594_;
+ wire _2595_;
+ wire _2596_;
+ wire _2597_;
+ wire _2598_;
+ wire _2599_;
+ wire _2600_;
+ wire _2601_;
+ wire _2602_;
+ wire _2603_;
+ wire _2604_;
+ wire _2605_;
+ wire _2606_;
+ wire _2607_;
+ wire _2608_;
+ wire _2609_;
+ wire _2610_;
+ wire _2611_;
+ wire _2612_;
+ wire _2613_;
+ wire _2614_;
+ wire _2615_;
+ wire _2616_;
+ wire _2617_;
+ wire _2618_;
+ wire _2619_;
+ wire _2620_;
+ wire _2621_;
+ wire _2622_;
+ wire _2623_;
+ wire _2624_;
+ wire _2625_;
+ wire _2626_;
+ wire _2627_;
+ wire _2628_;
+ wire _2629_;
+ wire _2630_;
+ wire _2631_;
+ wire _2632_;
+ wire _2633_;
+ wire _2634_;
+ wire _2635_;
+ wire _2636_;
+ wire _2637_;
+ wire _2638_;
+ wire _2639_;
+ wire _2640_;
+ wire _2641_;
+ wire _2642_;
+ wire _2643_;
+ wire _2644_;
+ wire _2645_;
+ wire _2646_;
+ wire _2647_;
+ wire _2648_;
+ wire _2649_;
+ wire _2650_;
+ wire _2651_;
+ wire _2652_;
+ wire _2653_;
+ wire _2654_;
+ wire _2655_;
+ wire _2656_;
+ wire _2657_;
+ wire _2658_;
+ wire _2659_;
+ wire _2660_;
+ wire _2661_;
+ wire _2662_;
+ wire _2663_;
+ wire _2664_;
+ wire _2665_;
+ wire _2666_;
+ wire _2667_;
+ wire _2668_;
+ wire _2669_;
+ wire _2670_;
+ wire _2671_;
+ wire _2672_;
+ wire _2673_;
+ wire _2674_;
+ wire _2675_;
+ wire _2676_;
+ wire _2677_;
+ wire _2678_;
+ wire _2679_;
+ wire _2680_;
+ wire _2681_;
+ wire _2682_;
+ wire _2683_;
+ wire _2684_;
+ wire _2685_;
+ wire _2686_;
+ wire _2687_;
+ wire _2688_;
+ wire _2689_;
+ wire _2690_;
+ wire _2691_;
+ wire _2692_;
+ wire _2693_;
+ wire _2694_;
+ wire _2695_;
+ wire _2696_;
+ wire _2697_;
+ wire _2698_;
+ wire _2700_;
+ wire _2701_;
+ wire _2702_;
+ wire _2703_;
+ wire _2704_;
+ wire _2705_;
+ wire _2706_;
+ wire _2707_;
+ wire _2708_;
+ wire _2709_;
+ wire _2710_;
+ wire _2711_;
+ wire _2712_;
+ wire _2713_;
+ wire _2714_;
+ wire _2715_;
+ wire _2716_;
+ wire _2717_;
+ wire _2718_;
+ wire _2719_;
+ wire _2720_;
+ wire _2721_;
+ wire _2722_;
+ wire _2723_;
+ wire _2724_;
+ wire _2725_;
+ wire _2726_;
+ wire _2727_;
+ wire _2728_;
+ wire _2729_;
+ wire _2730_;
+ wire _2731_;
+ wire _2732_;
+ wire _2733_;
+ wire _2734_;
+ wire _2735_;
+ wire _2736_;
+ wire _2737_;
+ wire _2738_;
+ wire _2739_;
+ wire _2740_;
+ wire _2741_;
+ wire _2742_;
+ wire _2743_;
+ wire _2744_;
+ wire _2745_;
+ wire _2746_;
+ wire _2747_;
+ wire _2748_;
+ wire _2749_;
+ wire _2750_;
+ wire _2751_;
+ wire _2752_;
+ wire _2753_;
+ wire _2754_;
+ wire _2755_;
+ wire _2756_;
+ wire _2757_;
+ wire _2758_;
+ wire _2759_;
+ wire _2760_;
+ wire _2761_;
+ wire _2762_;
+ wire _2763_;
+ wire _2764_;
+ wire _2765_;
+ wire _2766_;
+ wire _2767_;
+ wire _2768_;
+ wire _2769_;
+ wire _2770_;
+ wire _2771_;
+ wire _2772_;
+ wire _2773_;
+ wire _2774_;
+ wire _2775_;
+ wire _2776_;
+ wire _2777_;
+ wire _2778_;
+ wire _2779_;
+ wire _2780_;
+ wire _2781_;
+ wire _2782_;
+ wire _2783_;
+ wire _2784_;
+ wire _2785_;
+ wire _2786_;
+ wire _2787_;
+ wire _2788_;
+ wire _2789_;
+ wire _2790_;
+ wire _2791_;
+ wire _2792_;
+ wire _2793_;
+ wire _2794_;
+ wire _2795_;
+ wire _2796_;
+ wire _2797_;
+ wire _2798_;
+ wire _2799_;
+ wire _2800_;
+ wire _2801_;
+ wire _2802_;
+ wire _2803_;
+ wire _2804_;
+ wire _2805_;
+ wire _2806_;
+ wire _2807_;
+ wire _2808_;
+ wire _2809_;
+ wire _2810_;
+ wire _2811_;
+ wire _2812_;
+ wire _2813_;
+ wire _2814_;
+ wire _2815_;
+ wire _2816_;
+ wire _2817_;
+ wire _2818_;
+ wire _2819_;
+ wire _2820_;
+ wire _2821_;
+ wire _2822_;
+ wire _2823_;
+ wire _2824_;
+ wire _2825_;
+ wire _2826_;
+ wire _2827_;
+ wire _2828_;
+ wire _2829_;
+ wire _2830_;
+ wire _2831_;
+ wire _2832_;
+ wire _2833_;
+ wire _2834_;
+ wire _2835_;
+ wire _2836_;
+ wire _2837_;
+ wire _2838_;
+ wire _2839_;
+ wire _2840_;
+ wire _2841_;
+ wire _2842_;
+ wire _2843_;
+ wire _2844_;
+ wire _2845_;
+ wire _2846_;
+ wire _2847_;
+ wire _2848_;
+ wire _2849_;
+ wire _2850_;
+ wire _2851_;
+ wire _2852_;
+ wire _2853_;
+ wire _2854_;
+ wire _2855_;
+ wire _2856_;
+ wire _2857_;
+ wire _2858_;
+ wire _2859_;
+ wire _2860_;
+ wire _2861_;
+ wire _2862_;
+ wire _2863_;
+ wire _2864_;
+ wire _2865_;
+ wire _2866_;
+ wire _2867_;
+ wire _2868_;
+ wire _2869_;
+ wire _2870_;
+ wire _2871_;
+ wire _2872_;
+ wire _2873_;
+ wire _2874_;
+ wire _2875_;
+ wire _2876_;
+ wire _2877_;
+ wire _2878_;
+ wire _2879_;
+ wire _2880_;
+ wire _2881_;
+ wire _2882_;
+ wire _2883_;
+ wire _2884_;
+ wire _2885_;
+ wire _2886_;
+ wire _2887_;
+ wire _2888_;
+ wire _2889_;
+ wire _2890_;
+ wire _2891_;
+ wire _2892_;
+ wire _2893_;
+ wire _2894_;
+ wire _2895_;
+ wire _2896_;
+ wire _2897_;
+ wire _2898_;
+ wire _2899_;
+ wire _2900_;
+ wire _2901_;
+ wire _2902_;
+ wire _2903_;
+ wire _2904_;
+ wire _2905_;
+ wire _2906_;
+ wire _2907_;
+ wire _2908_;
+ wire _2909_;
+ wire _2910_;
+ wire _2911_;
+ wire _2912_;
+ wire _2913_;
+ wire _2914_;
+ wire _2915_;
+ wire _2916_;
+ wire _2917_;
+ wire _2918_;
+ wire _2919_;
+ wire _2920_;
+ wire _2921_;
+ wire _2922_;
+ wire _2923_;
+ wire _2924_;
+ wire _2925_;
+ wire _2926_;
+ wire _2927_;
+ wire _2928_;
+ wire _2929_;
+ wire _2930_;
+ wire _2931_;
+ wire _2932_;
+ wire _2933_;
+ wire _2934_;
+ wire _2935_;
+ wire _2936_;
+ wire _2937_;
+ wire _2938_;
+ wire _2939_;
+ wire _2940_;
+ wire _2941_;
+ wire _2942_;
+ wire _2943_;
+ wire _2944_;
+ wire _2945_;
+ wire _2946_;
+ wire _2947_;
+ wire _2948_;
+ wire _2949_;
+ wire _2950_;
+ wire _2951_;
+ wire _2952_;
+ wire _2953_;
+ wire _2954_;
+ wire _2955_;
+ wire _2956_;
+ wire _2957_;
+ wire _2958_;
+ wire _2959_;
+ wire _2960_;
+ wire _2961_;
+ wire _2962_;
+ wire _2963_;
+ wire _2964_;
+ wire _2965_;
+ wire _2966_;
+ wire _2967_;
+ wire _2968_;
+ wire _2969_;
+ wire _2970_;
+ wire _2971_;
+ wire _2972_;
+ wire _2973_;
+ wire _2974_;
+ wire _2975_;
+ wire _2976_;
+ wire _2977_;
+ wire _2978_;
+ wire _2979_;
+ wire _2980_;
+ wire _2981_;
+ wire _2982_;
+ wire _2983_;
+ wire _2984_;
+ wire _2985_;
+ wire _2986_;
+ wire _2987_;
+ wire _2988_;
+ wire _2989_;
+ wire _2990_;
+ wire _2991_;
+ wire _2992_;
+ wire _2993_;
+ wire _2994_;
+ wire _2995_;
+ wire _2996_;
+ wire _2997_;
+ wire _2998_;
+ wire _2999_;
+ wire _3000_;
+ wire _3001_;
+ wire _3002_;
+ wire _3003_;
+ wire _3004_;
+ wire _3005_;
+ wire _3006_;
+ wire _3007_;
+ wire _3008_;
+ wire _3009_;
+ wire _3010_;
+ wire _3011_;
+ wire _3012_;
+ wire _3013_;
+ wire _3014_;
+ wire _3015_;
+ wire _3016_;
+ wire _3017_;
+ wire _3018_;
+ wire _3019_;
+ wire _3020_;
+ wire _3021_;
+ wire _3022_;
+ wire _3023_;
+ wire _3024_;
+ wire _3025_;
+ wire _3026_;
+ wire _3027_;
+ wire _3028_;
+ wire _3029_;
+ wire _3030_;
+ wire _3031_;
+ wire _3032_;
+ wire _3033_;
+ wire _3034_;
+ wire _3035_;
+ wire _3036_;
+ wire _3037_;
+ wire _3038_;
+ wire _3039_;
+ wire _3040_;
+ wire _3041_;
+ wire _3042_;
+ wire _3043_;
+ wire _3044_;
+ wire _3045_;
+ wire _3046_;
+ wire _3047_;
+ wire _3048_;
+ wire _3049_;
+ wire _3050_;
+ wire _3051_;
+ wire _3052_;
+ wire _3053_;
+ wire _3054_;
+ wire _3055_;
+ wire _3056_;
+ wire _3057_;
+ wire _3058_;
+ wire _3059_;
+ wire _3060_;
+ wire _3061_;
+ wire _3062_;
+ wire _3063_;
+ wire _3064_;
+ wire _3065_;
+ wire _3066_;
+ wire _3067_;
+ wire _3068_;
+ wire _3069_;
+ wire _3070_;
+ wire _3071_;
+ wire _3072_;
+ wire _3073_;
+ wire _3074_;
+ wire _3075_;
+ wire _3076_;
+ wire _3077_;
+ wire _3078_;
+ wire _3079_;
+ wire _3080_;
+ wire _3081_;
+ wire _3082_;
+ wire _3083_;
+ wire _3084_;
+ wire _3085_;
+ wire _3086_;
+ wire _3087_;
+ wire _3088_;
+ wire _3089_;
+ wire _3090_;
+ wire _3091_;
+ wire _3092_;
+ wire _3093_;
+ wire _3094_;
+ wire _3095_;
+ wire _3096_;
+ wire _3097_;
+ wire _3098_;
+ wire _3099_;
+ wire _3100_;
+ wire _3101_;
+ wire _3102_;
+ wire _3103_;
+ wire _3104_;
+ wire _3105_;
+ wire _3106_;
+ wire _3107_;
+ wire _3108_;
+ wire _3109_;
+ wire _3110_;
+ wire _3111_;
+ wire _3112_;
+ wire _3113_;
+ wire _3114_;
+ wire _3115_;
+ wire _3116_;
+ wire _3117_;
+ wire _3118_;
+ wire _3119_;
+ wire _3120_;
+ wire _3121_;
+ wire _3122_;
+ wire _3123_;
+ wire _3124_;
+ wire _3125_;
+ wire _3126_;
+ wire _3127_;
+ wire _3128_;
+ wire _3129_;
+ wire _3130_;
+ wire _3131_;
+ wire _3132_;
+ wire _3133_;
+ wire _3134_;
+ wire _3135_;
+ wire _3136_;
+ wire _3137_;
+ wire _3138_;
+ wire _3139_;
+ wire _3140_;
+ wire _3141_;
+ wire _3142_;
+ wire _3143_;
+ wire _3144_;
+ wire _3145_;
+ wire _3146_;
+ wire _3147_;
+ wire _3148_;
+ wire _3149_;
+ wire _3150_;
+ wire _3151_;
+ wire _3152_;
+ wire _3153_;
+ wire _3154_;
+ wire _3155_;
+ wire _3156_;
+ wire _3157_;
+ wire _3158_;
+ wire _3159_;
+ wire _3160_;
+ wire _3161_;
+ wire _3162_;
+ wire _3163_;
+ wire _3164_;
+ wire _3165_;
+ wire _3166_;
+ wire _3167_;
+ wire _3168_;
+ wire _3169_;
+ wire _3170_;
+ wire _3171_;
+ wire _3172_;
+ wire _3173_;
+ wire _3174_;
+ wire _3175_;
+ wire _3176_;
+ wire _3177_;
+ wire _3178_;
+ wire _3179_;
+ wire _3180_;
+ wire _3181_;
+ wire _3182_;
+ wire _3183_;
+ wire _3184_;
+ wire _3185_;
+ wire _3186_;
+ wire _3187_;
+ wire _3188_;
+ wire _3189_;
+ wire _3190_;
+ wire _3191_;
+ wire _3192_;
+ wire _3193_;
+ wire _3194_;
+ wire _3195_;
+ wire _3196_;
+ wire _3197_;
+ wire _3198_;
+ wire _3199_;
+ wire _3200_;
+ wire _3201_;
+ wire _3202_;
+ wire _3203_;
+ wire _3204_;
+ wire _3205_;
+ wire _3206_;
+ wire _3207_;
+ wire _3208_;
+ wire _3209_;
+ wire _3210_;
+ wire _3211_;
+ wire _3212_;
+ wire _3213_;
+ wire _3214_;
+ wire _3215_;
+ wire _3216_;
+ wire _3217_;
+ wire _3218_;
+ wire _3219_;
+ wire _3220_;
+ wire _3221_;
+ wire _3222_;
+ wire _3223_;
+ wire _3224_;
+ wire _3225_;
+ wire _3226_;
+ wire _3227_;
+ wire _3228_;
+ wire _3229_;
+ wire _3230_;
+ wire _3231_;
+ wire _3232_;
+ wire _3233_;
+ wire _3234_;
+ wire _3235_;
+ wire _3236_;
+ wire _3237_;
+ wire _3238_;
+ wire _3239_;
+ wire _3240_;
+ wire _3241_;
+ wire _3242_;
+ wire _3243_;
+ wire _3244_;
+ wire _3245_;
+ wire _3246_;
+ wire _3247_;
+ wire _3248_;
+ wire _3249_;
+ wire _3250_;
+ wire _3251_;
+ wire _3252_;
+ wire _3253_;
+ wire _3254_;
+ wire _3255_;
+ wire _3256_;
+ wire _3257_;
+ wire _3258_;
+ wire _3259_;
+ wire _3260_;
+ wire _3261_;
+ wire _3262_;
+ wire _3263_;
+ wire _3264_;
+ wire _3265_;
+ wire _3266_;
+ wire _3267_;
+ wire _3268_;
+ wire _3269_;
+ wire _3270_;
+ wire _3271_;
+ wire _3272_;
+ wire _3273_;
+ wire _3274_;
+ wire _3275_;
+ wire _3276_;
+ wire _3277_;
+ wire _3278_;
+ wire _3279_;
+ wire _3280_;
+ wire _3281_;
+ wire _3282_;
+ wire _3283_;
+ wire _3284_;
+ wire _3285_;
+ wire _3286_;
+ wire _3287_;
+ wire _3288_;
+ wire _3289_;
+ wire _3290_;
+ wire _3291_;
+ wire _3292_;
+ wire _3293_;
+ wire _3294_;
+ wire _3295_;
+ wire _3296_;
+ wire _3297_;
+ wire _3298_;
+ wire _3299_;
+ wire _3300_;
+ wire _3301_;
+ wire _3302_;
+ wire _3303_;
+ wire _3304_;
+ wire _3305_;
+ wire _3306_;
+ wire _3307_;
+ wire _3308_;
+ wire _3309_;
+ wire _3310_;
+ wire _3311_;
+ wire _3312_;
+ wire _3313_;
+ wire _3314_;
+ wire _3315_;
+ wire _3316_;
+ wire _3317_;
+ wire _3318_;
+ wire _3319_;
+ wire _3320_;
+ wire _3321_;
+ wire _3322_;
+ wire _3323_;
+ wire _3324_;
+ wire _3325_;
+ wire _3326_;
+ wire _3327_;
+ wire _3328_;
+ wire _3329_;
+ wire _3330_;
+ wire _3331_;
+ wire _3332_;
+ wire _3333_;
+ wire _3334_;
+ wire _3335_;
+ wire _3336_;
+ wire _3337_;
+ wire _3338_;
+ wire _3339_;
+ wire _3340_;
+ wire _3341_;
+ wire _3342_;
+ wire _3343_;
+ wire _3344_;
+ wire _3345_;
+ wire _3346_;
+ wire _3347_;
+ wire _3348_;
+ wire _3349_;
+ wire _3350_;
+ wire _3351_;
+ wire _3352_;
+ wire _3353_;
+ wire _3354_;
+ wire _3355_;
+ wire _3356_;
+ wire _3357_;
+ wire _3358_;
+ wire _3359_;
+ wire _3360_;
+ wire _3361_;
+ wire _3362_;
+ wire _3363_;
+ wire _3364_;
+ wire _3365_;
+ wire _3366_;
+ wire _3367_;
+ wire _3368_;
+ wire _3369_;
+ wire _3370_;
+ wire _3371_;
+ wire _3372_;
+ wire _3373_;
+ wire _3374_;
+ wire _3375_;
+ wire _3376_;
+ wire _3377_;
+ wire _3378_;
+ wire _3379_;
+ wire _3380_;
+ wire _3381_;
+ wire _3382_;
+ wire _3383_;
+ wire _3384_;
+ wire _3385_;
+ wire _3386_;
+ wire _3387_;
+ wire _3388_;
+ wire _3389_;
+ wire _3390_;
+ wire _3391_;
+ wire _3392_;
+ wire _3393_;
+ wire _3394_;
+ wire _3395_;
+ wire _3396_;
+ wire _3397_;
+ wire _3398_;
+ wire _3399_;
+ wire _3400_;
+ wire _3401_;
+ wire _3402_;
+ wire _3403_;
+ wire _3404_;
+ wire _3405_;
+ wire _3406_;
+ wire _3407_;
+ wire _3408_;
+ wire _3409_;
+ wire _3410_;
+ wire _3411_;
+ wire _3412_;
+ wire _3413_;
+ wire _3414_;
+ wire _3415_;
+ wire _3416_;
+ wire _3417_;
+ wire _3418_;
+ wire _3419_;
+ wire _3420_;
+ wire _3421_;
+ wire _3422_;
+ wire _3423_;
+ wire _3424_;
+ wire _3425_;
+ wire _3426_;
+ wire _3427_;
+ wire _3428_;
+ wire _3429_;
+ wire _3430_;
+ wire _3431_;
+ wire _3432_;
+ wire _3433_;
+ wire _3434_;
+ wire _3435_;
+ wire _3436_;
+ wire _3437_;
+ wire _3438_;
+ wire _3439_;
+ wire _3440_;
+ wire _3441_;
+ wire _3442_;
+ wire _3443_;
+ wire _3444_;
+ wire _3445_;
+ wire _3446_;
+ wire _3447_;
+ wire _3448_;
+ wire _3449_;
+ wire _3450_;
+ wire _3451_;
+ wire _3452_;
+ wire _3453_;
+ wire _3454_;
+ wire _3455_;
+ wire _3456_;
+ wire _3457_;
+ wire _3458_;
+ wire _3459_;
+ wire _3460_;
+ wire _3461_;
+ wire _3462_;
+ wire _3463_;
+ wire _3464_;
+ wire _3465_;
+ wire _3466_;
+ wire _3467_;
+ wire _3468_;
+ wire _3469_;
+ wire _3470_;
+ wire _3471_;
+ wire _3472_;
+ wire _3473_;
+ wire _3474_;
+ wire _3475_;
+ wire _3476_;
+ wire _3477_;
+ wire _3478_;
+ wire _3479_;
+ wire _3480_;
+ wire _3481_;
+ wire _3482_;
+ wire _3483_;
+ wire _3484_;
+ wire _3485_;
+ wire _3486_;
+ wire _3487_;
+ wire _3488_;
+ wire _3489_;
+ wire _3490_;
+ wire _3491_;
+ wire _3492_;
+ wire _3493_;
+ wire _3494_;
+ wire _3495_;
+ wire _3496_;
+ wire _3497_;
+ wire _3498_;
+ wire _3499_;
+ wire _3500_;
+ wire _3501_;
+ wire _3502_;
+ wire _3503_;
+ wire _3504_;
+ wire _3505_;
+ wire _3506_;
+ wire _3507_;
+ wire _3508_;
+ wire _3509_;
+ wire _3510_;
+ wire _3511_;
+ wire _3512_;
+ wire _3513_;
+ wire _3514_;
+ wire _3515_;
+ wire _3516_;
+ wire _3517_;
+ wire _3518_;
+ wire _3519_;
+ wire _3520_;
+ wire _3521_;
+ wire _3522_;
+ wire _3523_;
+ wire _3524_;
+ wire _3525_;
+ wire _3526_;
+ wire _3527_;
+ wire _3528_;
+ wire _3529_;
+ wire _3530_;
+ wire _3531_;
+ wire _3532_;
+ wire _3533_;
+ wire _3534_;
+ wire _3535_;
+ wire _3536_;
+ wire _3537_;
+ wire _3538_;
+ wire _3539_;
+ wire _3540_;
+ wire _3541_;
+ wire _3542_;
+ wire _3543_;
+ wire _3544_;
+ wire _3545_;
+ wire _3546_;
+ wire _3547_;
+ wire _3548_;
+ wire _3549_;
+ wire _3550_;
+ wire _3551_;
+ wire _3552_;
+ wire _3553_;
+ wire _3554_;
+ wire _3555_;
+ wire _3556_;
+ wire _3557_;
+ wire _3558_;
+ wire _3559_;
+ wire _3560_;
+ wire _3561_;
+ wire _3562_;
+ wire _3563_;
+ wire _3564_;
+ wire _3565_;
+ wire _3566_;
+ wire _3567_;
+ wire _3568_;
+ wire _3569_;
+ wire _3570_;
+ wire _3571_;
+ wire _3572_;
+ wire _3573_;
+ wire _3574_;
+ wire _3575_;
+ wire _3576_;
+ wire _3577_;
+ wire _3578_;
+ wire _3579_;
+ wire _3580_;
+ wire _3581_;
+ wire _3582_;
+ wire _3583_;
+ wire _3584_;
+ wire _3585_;
+ wire _3586_;
+ wire _3587_;
+ wire _3588_;
+ wire _3589_;
+ wire _3590_;
+ wire _3591_;
+ wire _3592_;
+ wire _3593_;
+ wire _3594_;
+ wire _3595_;
+ wire _3596_;
+ wire _3597_;
+ wire _3598_;
+ wire _3599_;
+ wire _3600_;
+ wire _3601_;
+ wire _3602_;
+ wire _3603_;
+ wire _3604_;
+ wire _3605_;
+ wire _3606_;
+ wire _3607_;
+ wire _3608_;
+ wire _3609_;
+ wire _3610_;
+ wire _3611_;
+ wire _3612_;
+ wire _3613_;
+ wire _3614_;
+ wire _3615_;
+ wire _3616_;
+ wire _3617_;
+ wire _3618_;
+ wire _3619_;
+ wire _3620_;
+ wire _3621_;
+ wire _3622_;
+ wire _3623_;
+ wire _3624_;
+ wire _3625_;
+ wire _3626_;
+ wire _3627_;
+ wire _3628_;
+ wire _3629_;
+ wire _3630_;
+ wire _3631_;
+ wire _3632_;
+ wire _3633_;
+ wire _3634_;
+ wire _3635_;
+ wire _3636_;
+ wire _3637_;
+ wire _3638_;
+ wire _3639_;
+ wire _3640_;
+ wire _3641_;
+ wire _3642_;
+ wire _3643_;
+ wire _3644_;
+ wire _3645_;
+ wire _3646_;
+ wire _3647_;
+ wire _3648_;
+ wire _3649_;
+ wire _3650_;
+ wire _3651_;
+ wire _3652_;
+ wire _3653_;
+ wire _3654_;
+ wire _3655_;
+ wire _3656_;
+ wire _3657_;
+ wire _3658_;
+ wire _3659_;
+ wire _3660_;
+ wire _3661_;
+ wire _3662_;
+ wire _3663_;
+ wire _3664_;
+ wire _3665_;
+ wire _3666_;
+ wire _3667_;
+ wire _3668_;
+ wire _3669_;
+ wire _3670_;
+ wire _3671_;
+ wire _3672_;
+ wire _3673_;
+ wire _3674_;
+ wire _3675_;
+ wire _3676_;
+ wire _3677_;
+ wire _3678_;
+ wire _3679_;
+ wire _3680_;
+ wire _3681_;
+ wire _3682_;
+ wire _3683_;
+ wire _3684_;
+ wire _3685_;
+ wire _3686_;
+ wire _3687_;
+ wire _3688_;
+ wire _3689_;
+ wire _3690_;
+ wire _3691_;
+ wire _3692_;
+ wire _3693_;
+ wire _3694_;
+ wire _3695_;
+ wire _3696_;
+ wire _3697_;
+ wire _3698_;
+ wire _3699_;
+ wire _3700_;
+ wire _3701_;
+ wire _3702_;
+ wire _3703_;
+ wire _3704_;
+ wire _3705_;
+ wire _3706_;
+ wire _3707_;
+ wire _3708_;
+ wire _3709_;
+ wire _3710_;
+ wire _3711_;
+ wire _3712_;
+ wire _3713_;
+ wire _3714_;
+ wire _3715_;
+ wire _3716_;
+ wire _3717_;
+ wire _3718_;
+ wire _3719_;
+ wire _3720_;
+ wire _3721_;
+ wire _3722_;
+ wire _3723_;
+ wire _3724_;
+ wire _3725_;
+ wire _3726_;
+ wire _3727_;
+ wire _3728_;
+ wire _3729_;
+ wire _3730_;
+ wire _3731_;
+ wire _3732_;
+ wire _3733_;
+ wire _3734_;
+ wire _3735_;
+ wire _3736_;
+ wire _3737_;
+ wire _3738_;
+ wire _3739_;
+ wire _3740_;
+ wire _3741_;
+ wire _3742_;
+ wire _3743_;
+ wire _3744_;
+ wire _3745_;
+ wire _3746_;
+ wire _3747_;
+ wire _3748_;
+ wire _3749_;
+ wire _3750_;
+ wire _3751_;
+ wire _3752_;
+ wire _3753_;
+ wire _3754_;
+ wire _3755_;
+ wire _3756_;
+ wire _3757_;
+ wire _3758_;
+ wire _3759_;
+ wire _3760_;
+ wire _3761_;
+ wire _3762_;
+ wire _3763_;
+ wire _3764_;
+ wire _3765_;
+ wire _3766_;
+ wire _3767_;
+ wire _3768_;
+ wire _3769_;
+ wire _3770_;
+ wire _3771_;
+ wire _3772_;
+ wire _3773_;
+ wire _3774_;
+ wire _3775_;
+ wire _3776_;
+ wire _3777_;
+ wire _3778_;
+ wire _3779_;
+ wire _3780_;
+ wire _3781_;
+ wire _3782_;
+ wire _3783_;
+ wire _3784_;
+ wire _3785_;
+ wire _3786_;
+ wire _3787_;
+ wire _3788_;
+ wire _3789_;
+ wire _3790_;
+ wire _3791_;
+ wire _3792_;
+ wire _3793_;
+ wire _3794_;
+ wire _3795_;
+ wire _3796_;
+ wire _3797_;
+ wire _3798_;
+ wire _3799_;
+ wire _3800_;
+ wire _3801_;
+ wire _3802_;
+ wire _3803_;
+ wire _3804_;
+ wire _3805_;
+ wire _3806_;
+ wire _3807_;
+ wire _3808_;
+ wire _3809_;
+ wire _3810_;
+ wire _3811_;
+ wire _3812_;
+ wire _3813_;
+ wire _3814_;
+ wire _3815_;
+ wire _3816_;
+ wire _3817_;
+ wire _3818_;
+ wire _3819_;
+ wire _3820_;
+ wire _3821_;
+ wire _3822_;
+ wire _3823_;
+ wire _3824_;
+ wire _3825_;
+ wire _3826_;
+ wire _3827_;
+ wire _3828_;
+ wire _3829_;
+ wire _3830_;
+ wire _3831_;
+ wire _3832_;
+ wire _3833_;
+ wire _3834_;
+ wire _3835_;
+ wire _3836_;
+ wire _3837_;
+ wire _3838_;
+ wire _3839_;
+ wire _3840_;
+ wire _3841_;
+ wire _3842_;
+ wire _3843_;
+ wire _3844_;
+ wire _3845_;
+ wire _3846_;
+ wire _3847_;
+ wire _3848_;
+ wire _3849_;
+ wire _3850_;
+ wire _3851_;
+ wire _3852_;
+ wire _3853_;
+ wire _3854_;
+ wire _3855_;
+ wire _3856_;
+ wire _3857_;
+ wire _3858_;
+ wire _3859_;
+ wire _3860_;
+ wire _3861_;
+ wire _3862_;
+ wire _3863_;
+ wire _3864_;
+ wire _3865_;
+ wire _3866_;
+ wire _3867_;
+ wire _3868_;
+ wire _3869_;
+ wire _3870_;
+ wire _3871_;
+ wire _3872_;
+ wire _3873_;
+ wire _3874_;
+ wire _3875_;
+ wire _3876_;
+ wire _3877_;
+ wire _3878_;
+ wire _3879_;
+ wire _3880_;
+ wire _3881_;
+ wire _3882_;
+ wire _3883_;
+ wire _3884_;
+ wire _3885_;
+ wire _3886_;
+ wire _3887_;
+ wire _3888_;
+ wire _3889_;
+ wire _3890_;
+ wire _3891_;
+ wire _3892_;
+ wire _3893_;
+ wire _3894_;
+ wire _3895_;
+ wire _3896_;
+ wire _3897_;
+ wire _3898_;
+ wire _3899_;
+ wire _3900_;
+ wire _3901_;
+ wire _3902_;
+ wire _3903_;
+ wire _3904_;
+ wire _3905_;
+ wire _3906_;
+ wire _3907_;
+ wire _3908_;
+ wire _3909_;
+ wire _3910_;
+ wire _3911_;
+ wire _3912_;
+ wire _3913_;
+ wire _3914_;
+ wire _3915_;
+ wire _3916_;
+ wire _3917_;
+ wire _3918_;
+ wire _3919_;
+ wire _3920_;
+ wire _3921_;
+ wire _3922_;
+ wire _3923_;
+ wire _3924_;
+ wire _3925_;
+ wire _3926_;
+ wire _3927_;
+ wire _3928_;
+ wire _3929_;
+ wire _3930_;
+ wire _3931_;
+ wire _3932_;
+ wire _3933_;
+ wire _3934_;
+ wire _3935_;
+ wire _3936_;
+ wire _3937_;
+ wire _3938_;
+ wire _3939_;
+ wire _3940_;
+ wire _3941_;
+ wire _3942_;
+ wire _3943_;
+ wire _3944_;
+ wire _3945_;
+ wire _3946_;
+ wire _3947_;
+ wire _3948_;
+ wire _3949_;
+ wire _3950_;
+ wire _3951_;
+ wire _3952_;
+ wire _3953_;
+ wire _3954_;
+ wire _3955_;
+ wire _3956_;
+ wire _3957_;
+ wire _3958_;
+ wire _3959_;
+ wire _3960_;
+ wire _3961_;
+ wire _3962_;
+ wire _3963_;
+ wire _3964_;
+ wire _3965_;
+ wire _3966_;
+ wire _3967_;
+ wire _3968_;
+ wire _3969_;
+ wire _3970_;
+ wire _3971_;
+ wire _3972_;
+ wire _3973_;
+ wire _3974_;
+ wire _3975_;
+ wire _3976_;
+ wire _3977_;
+ wire _3978_;
+ wire _3979_;
+ wire _3980_;
+ wire _3981_;
+ wire _3982_;
+ wire _3983_;
+ wire _3984_;
+ wire _3985_;
+ wire _3986_;
+ wire _3987_;
+ wire _3988_;
+ wire _3989_;
+ wire _3990_;
+ wire _3991_;
+ wire _3992_;
+ wire _3993_;
+ wire _3994_;
+ wire _3995_;
+ wire _3996_;
+ wire _3997_;
+ wire _3998_;
+ wire _3999_;
+ wire _4000_;
+ wire _4001_;
+ wire _4002_;
+ wire _4003_;
+ wire _4004_;
+ wire _4005_;
+ wire _4006_;
+ wire _4007_;
+ wire _4008_;
+ wire _4009_;
+ wire _4010_;
+ wire _4011_;
+ wire _4012_;
+ wire _4013_;
+ wire _4014_;
+ wire _4015_;
+ wire _4016_;
+ wire _4017_;
+ wire _4018_;
+ wire _4019_;
+ wire _4020_;
+ wire _4021_;
+ wire _4022_;
+ wire _4023_;
+ wire _4024_;
+ wire _4025_;
+ wire _4026_;
+ wire _4027_;
+ wire _4028_;
+ wire _4029_;
+ wire _4030_;
+ wire _4031_;
+ wire _4032_;
+ wire _4033_;
+ wire _4034_;
+ wire _4035_;
+ wire _4036_;
+ wire _4037_;
+ wire _4038_;
+ wire _4039_;
+ wire _4040_;
+ wire _4041_;
+ wire _4042_;
+ wire _4043_;
+ wire _4044_;
+ wire _4045_;
+ wire _4046_;
+ wire _4047_;
+ wire _4048_;
+ wire _4049_;
+ wire _4050_;
+ wire _4051_;
+ wire _4052_;
+ wire _4053_;
+ wire _4054_;
+ wire _4055_;
+ wire _4056_;
+ wire _4057_;
+ wire _4058_;
+ wire _4059_;
+ wire _4060_;
+ wire _4061_;
+ wire _4062_;
+ wire _4063_;
+ wire _4064_;
+ wire _4065_;
+ wire _4066_;
+ wire _4067_;
+ wire _4068_;
+ wire _4069_;
+ wire _4070_;
+ wire _4071_;
+ wire _4072_;
+ wire _4073_;
+ wire _4074_;
+ wire _4075_;
+ wire _4076_;
+ wire _4077_;
+ wire _4078_;
+ wire _4079_;
+ wire _4080_;
+ wire _4081_;
+ wire _4082_;
+ wire _4083_;
+ wire _4084_;
+ wire _4085_;
+ wire _4086_;
+ wire _4087_;
+ wire _4088_;
+ wire _4089_;
+ wire _4090_;
+ wire _4091_;
+ wire _4092_;
+ wire _4093_;
+ wire _4094_;
+ wire _4095_;
+ wire _4096_;
+ wire _4097_;
+ wire _4098_;
+ wire _4099_;
+ wire _4100_;
+ wire _4101_;
+ wire _4102_;
+ wire _4103_;
+ wire _4104_;
+ wire _4105_;
+ wire _4106_;
+ wire _4107_;
+ wire _4108_;
+ wire _4109_;
+ wire _4110_;
+ wire _4111_;
+ wire _4112_;
+ wire _4113_;
+ wire _4114_;
+ wire _4115_;
+ wire _4116_;
+ wire _4117_;
+ wire _4118_;
+ wire _4119_;
+ wire _4120_;
+ wire _4121_;
+ wire _4122_;
+ wire _4123_;
+ wire _4124_;
+ wire _4125_;
+ wire _4126_;
+ wire _4127_;
+ wire _4128_;
+ wire _4129_;
+ wire _4130_;
+ wire _4131_;
+ wire _4132_;
+ wire _4133_;
+ wire _4134_;
+ wire _4135_;
+ wire _4136_;
+ wire _4137_;
+ wire _4138_;
+ wire _4139_;
+ wire _4140_;
+ wire _4141_;
+ wire _4142_;
+ wire _4143_;
+ wire _4144_;
+ wire _4145_;
+ wire _4146_;
+ wire _4147_;
+ wire _4148_;
+ wire _4149_;
+ wire _4150_;
+ wire _4151_;
+ wire _4152_;
+ wire _4153_;
+ wire _4154_;
+ wire _4155_;
+ wire _4156_;
+ wire _4157_;
+ wire _4158_;
+ wire _4159_;
+ wire _4160_;
+ wire _4161_;
+ wire _4162_;
+ wire _4163_;
+ wire _4164_;
+ wire _4165_;
+ wire _4166_;
+ wire _4167_;
+ wire _4168_;
+ wire _4169_;
+ wire _4170_;
+ wire _4171_;
+ wire _4172_;
+ wire _4173_;
+ wire _4174_;
+ wire _4175_;
+ wire _4176_;
+ wire _4177_;
+ wire _4178_;
+ wire _4179_;
+ wire _4180_;
+ wire _4181_;
+ wire _4182_;
+ wire _4183_;
+ wire _4184_;
+ wire _4185_;
+ wire _4186_;
+ wire _4187_;
+ wire _4188_;
+ wire _4189_;
+ wire _4190_;
+ wire _4191_;
+ wire _4192_;
+ wire _4193_;
+ wire _4194_;
+ wire _4195_;
+ wire _4196_;
+ wire _4197_;
+ wire _4198_;
+ wire _4199_;
+ wire _4200_;
+ wire _4201_;
+ wire _4202_;
+ wire _4203_;
+ wire _4204_;
+ wire _4205_;
+ wire _4206_;
+ wire _4207_;
+ wire _4208_;
+ wire _4209_;
+ wire _4210_;
+ wire _4211_;
+ wire _4212_;
+ wire _4213_;
+ wire _4214_;
+ wire _4215_;
+ wire _4216_;
+ wire _4217_;
+ wire _4218_;
+ wire _4219_;
+ wire _4220_;
+ wire _4221_;
+ wire _4222_;
+ wire _4223_;
+ wire _4224_;
+ wire _4225_;
+ wire _4226_;
+ wire _4227_;
+ wire _4228_;
+ wire _4229_;
+ wire _4230_;
+ wire _4231_;
+ wire _4232_;
+ wire _4233_;
+ wire _4234_;
+ wire _4235_;
+ wire _4236_;
+ wire _4237_;
+ wire _4238_;
+ wire _4239_;
+ wire _4240_;
+ wire _4241_;
+ wire _4242_;
+ wire _4243_;
+ wire _4244_;
+ wire _4245_;
+ wire _4246_;
+ wire _4247_;
+ wire _4248_;
+ wire _4249_;
+ wire _4250_;
+ wire _4251_;
+ wire _4252_;
+ wire _4253_;
+ wire _4254_;
+ wire _4255_;
+ wire _4256_;
+ wire _4257_;
+ wire _4258_;
+ wire _4259_;
+ wire _4260_;
+ wire _4261_;
+ wire _4262_;
+ wire _4263_;
+ wire _4264_;
+ wire _4265_;
+ wire _4266_;
+ wire _4267_;
+ wire _4268_;
+ wire _4269_;
+ wire _4270_;
+ wire _4271_;
+ wire _4272_;
+ wire _4273_;
+ wire _4274_;
+ wire _4275_;
+ wire _4276_;
+ wire _4277_;
+ wire _4278_;
+ wire _4279_;
+ wire _4280_;
+ wire _4281_;
+ wire _4282_;
+ wire _4283_;
+ wire _4284_;
+ wire _4285_;
+ wire _4286_;
+ wire _4287_;
+ wire _4288_;
+ wire _4289_;
+ wire _4290_;
+ wire _4291_;
+ wire _4292_;
+ wire _4293_;
+ wire _4294_;
+ wire _4295_;
+ wire _4296_;
+ wire _4297_;
+ wire _4298_;
+ wire _4299_;
+ wire _4300_;
+ wire _4301_;
+ wire _4302_;
+ wire _4303_;
+ wire _4304_;
+ wire _4305_;
+ wire _4306_;
+ wire _4307_;
+ wire _4308_;
+ wire _4309_;
+ wire _4310_;
+ wire _4311_;
+ wire _4312_;
+ wire _4313_;
+ wire _4314_;
+ wire _4315_;
+ wire _4316_;
+ wire _4317_;
+ wire _4318_;
+ wire _4319_;
+ wire _4320_;
+ wire _4321_;
+ wire _4322_;
+ wire _4323_;
+ wire _4324_;
+ wire _4325_;
+ wire _4326_;
+ wire _4327_;
+ wire _4328_;
+ wire _4329_;
+ wire _4330_;
+ wire _4331_;
+ wire _4332_;
+ wire _4333_;
+ wire _4334_;
+ wire _4335_;
+ wire _4336_;
+ wire _4337_;
+ wire _4338_;
+ wire _4339_;
+ wire _4340_;
+ wire _4341_;
+ wire _4342_;
+ wire _4343_;
+ wire _4344_;
+ wire _4345_;
+ wire _4346_;
+ wire _4347_;
+ wire _4348_;
+ wire _4349_;
+ wire _4350_;
+ wire _4351_;
+ wire _4352_;
+ wire _4353_;
+ wire _4354_;
+ wire _4355_;
+ wire _4356_;
+ wire _4357_;
+ wire _4358_;
+ wire _4359_;
+ wire _4360_;
+ wire _4361_;
+ wire _4362_;
+ wire _4363_;
+ wire _4364_;
+ wire _4365_;
+ wire _4366_;
+ wire _4367_;
+ wire _4368_;
+ wire _4369_;
+ wire _4370_;
+ wire _4371_;
+ wire _4372_;
+ wire _4373_;
+ wire _4374_;
+ wire _4375_;
+ wire _4376_;
+ wire _4377_;
+ wire _4378_;
+ wire _4379_;
+ wire _4380_;
+ wire _4381_;
+ wire _4382_;
+ wire _4383_;
+ wire _4384_;
+ wire _4385_;
+ wire _4386_;
+ wire _4387_;
+ wire _4388_;
+ wire _4389_;
+ wire _4390_;
+ wire _4391_;
+ wire _4392_;
+ wire _4393_;
+ wire _4394_;
+ wire _4395_;
+ wire _4396_;
+ wire _4397_;
+ wire _4398_;
+ wire _4399_;
+ wire _4400_;
+ wire _4401_;
+ wire _4402_;
+ wire _4403_;
+ wire _4404_;
+ wire _4405_;
+ wire _4406_;
+ wire _4407_;
+ wire _4408_;
+ wire _4409_;
+ wire _4410_;
+ wire _4411_;
+ wire _4412_;
+ wire _4413_;
+ wire _4414_;
+ wire _4415_;
+ wire _4416_;
+ wire _4417_;
+ wire _4418_;
+ wire _4419_;
+ wire _4420_;
+ wire _4421_;
+ wire _4422_;
+ wire _4423_;
+ wire _4424_;
+ wire _4425_;
+ wire _4426_;
+ wire _4427_;
+ wire _4428_;
+ wire _4429_;
+ wire _4430_;
+ wire _4431_;
+ wire _4432_;
+ wire _4433_;
+ wire _4434_;
+ wire _4435_;
+ wire _4436_;
+ wire _4437_;
+ wire _4438_;
+ wire _4439_;
+ wire _4440_;
+ wire _4442_;
+ wire \cdata[0] ;
+ wire \cdata[1] ;
+ wire \cdata[2] ;
+ wire \cdata[3] ;
+ wire \cdata[4] ;
+ wire \cdata[5] ;
+ wire \cdata[6] ;
+ wire \cdata[7] ;
+ wire clk1_output_dest;
+ wire clk2_output_dest;
+ wire clknet_0_csclk;
+ wire clknet_0_wb_clk_i;
+ wire clknet_1_0_0_csclk;
+ wire clknet_1_0_0_wb_clk_i;
+ wire clknet_1_0_1_csclk;
+ wire clknet_1_0_1_wb_clk_i;
+ wire clknet_1_1_0_csclk;
+ wire clknet_1_1_0_wb_clk_i;
+ wire clknet_1_1_1_csclk;
+ wire clknet_1_1_1_wb_clk_i;
+ wire clknet_2_0_0_csclk;
+ wire clknet_2_0_0_wb_clk_i;
+ wire clknet_2_1_0_csclk;
+ wire clknet_2_1_0_wb_clk_i;
+ wire clknet_2_2_0_csclk;
+ wire clknet_2_2_0_wb_clk_i;
+ wire clknet_2_3_0_csclk;
+ wire clknet_2_3_0_wb_clk_i;
+ wire clknet_3_0_0_wb_clk_i;
+ wire clknet_3_1_0_wb_clk_i;
+ wire clknet_3_2_0_wb_clk_i;
+ wire clknet_3_3_0_wb_clk_i;
+ wire clknet_3_4_0_wb_clk_i;
+ wire clknet_3_5_0_wb_clk_i;
+ wire clknet_3_6_0_wb_clk_i;
+ wire clknet_3_7_0_wb_clk_i;
+ wire clknet_leaf_0_csclk;
+ wire clknet_leaf_10_csclk;
+ wire clknet_leaf_11_csclk;
+ wire clknet_leaf_12_csclk;
+ wire clknet_leaf_13_csclk;
+ wire clknet_leaf_14_csclk;
+ wire clknet_leaf_15_csclk;
+ wire clknet_leaf_16_csclk;
+ wire clknet_leaf_17_csclk;
+ wire clknet_leaf_18_csclk;
+ wire clknet_leaf_19_csclk;
+ wire clknet_leaf_1_csclk;
+ wire clknet_leaf_20_csclk;
+ wire clknet_leaf_21_csclk;
+ wire clknet_leaf_22_csclk;
+ wire clknet_leaf_23_csclk;
+ wire clknet_leaf_24_csclk;
+ wire clknet_leaf_25_csclk;
+ wire clknet_leaf_26_csclk;
+ wire clknet_leaf_27_csclk;
+ wire clknet_leaf_28_csclk;
+ wire clknet_leaf_29_csclk;
+ wire clknet_leaf_2_csclk;
+ wire clknet_leaf_30_csclk;
+ wire clknet_leaf_31_csclk;
+ wire clknet_leaf_32_csclk;
+ wire clknet_leaf_33_csclk;
+ wire clknet_leaf_34_csclk;
+ wire clknet_leaf_35_csclk;
+ wire clknet_leaf_36_csclk;
+ wire clknet_leaf_37_csclk;
+ wire clknet_leaf_38_csclk;
+ wire clknet_leaf_39_csclk;
+ wire clknet_leaf_3_csclk;
+ wire clknet_leaf_40_csclk;
+ wire clknet_leaf_41_csclk;
+ wire clknet_leaf_43_csclk;
+ wire clknet_leaf_44_csclk;
+ wire clknet_leaf_45_csclk;
+ wire clknet_leaf_46_csclk;
+ wire clknet_leaf_47_csclk;
+ wire clknet_leaf_48_csclk;
+ wire clknet_leaf_49_csclk;
+ wire clknet_leaf_4_csclk;
+ wire clknet_leaf_50_csclk;
+ wire clknet_leaf_51_csclk;
+ wire clknet_leaf_5_csclk;
+ wire clknet_leaf_6_csclk;
+ wire clknet_leaf_7_csclk;
+ wire clknet_leaf_8_csclk;
+ wire clknet_leaf_9_csclk;
+ wire clknet_opt_1_0_csclk;
+ wire clknet_opt_2_0_csclk;
+ wire clknet_opt_3_0_csclk;
+ wire clknet_opt_4_0_csclk;
+ wire clknet_opt_5_0_csclk;
+ wire clknet_opt_6_0_csclk;
+ wire csclk;
+ wire \gpio_configure[0][0] ;
+ wire \gpio_configure[0][10] ;
+ wire \gpio_configure[0][11] ;
+ wire \gpio_configure[0][12] ;
+ wire \gpio_configure[0][1] ;
+ wire \gpio_configure[0][2] ;
+ wire \gpio_configure[0][3] ;
+ wire \gpio_configure[0][4] ;
+ wire \gpio_configure[0][5] ;
+ wire \gpio_configure[0][6] ;
+ wire \gpio_configure[0][7] ;
+ wire \gpio_configure[0][8] ;
+ wire \gpio_configure[0][9] ;
+ wire \gpio_configure[10][0] ;
+ wire \gpio_configure[10][10] ;
+ wire \gpio_configure[10][11] ;
+ wire \gpio_configure[10][12] ;
+ wire \gpio_configure[10][1] ;
+ wire \gpio_configure[10][2] ;
+ wire \gpio_configure[10][3] ;
+ wire \gpio_configure[10][4] ;
+ wire \gpio_configure[10][5] ;
+ wire \gpio_configure[10][6] ;
+ wire \gpio_configure[10][7] ;
+ wire \gpio_configure[10][8] ;
+ wire \gpio_configure[10][9] ;
+ wire \gpio_configure[11][0] ;
+ wire \gpio_configure[11][10] ;
+ wire \gpio_configure[11][11] ;
+ wire \gpio_configure[11][12] ;
+ wire \gpio_configure[11][1] ;
+ wire \gpio_configure[11][2] ;
+ wire \gpio_configure[11][3] ;
+ wire \gpio_configure[11][4] ;
+ wire \gpio_configure[11][5] ;
+ wire \gpio_configure[11][6] ;
+ wire \gpio_configure[11][7] ;
+ wire \gpio_configure[11][8] ;
+ wire \gpio_configure[11][9] ;
+ wire \gpio_configure[12][0] ;
+ wire \gpio_configure[12][10] ;
+ wire \gpio_configure[12][11] ;
+ wire \gpio_configure[12][12] ;
+ wire \gpio_configure[12][1] ;
+ wire \gpio_configure[12][2] ;
+ wire \gpio_configure[12][3] ;
+ wire \gpio_configure[12][4] ;
+ wire \gpio_configure[12][5] ;
+ wire \gpio_configure[12][6] ;
+ wire \gpio_configure[12][7] ;
+ wire \gpio_configure[12][8] ;
+ wire \gpio_configure[12][9] ;
+ wire \gpio_configure[13][0] ;
+ wire \gpio_configure[13][10] ;
+ wire \gpio_configure[13][11] ;
+ wire \gpio_configure[13][12] ;
+ wire \gpio_configure[13][1] ;
+ wire \gpio_configure[13][2] ;
+ wire \gpio_configure[13][3] ;
+ wire \gpio_configure[13][4] ;
+ wire \gpio_configure[13][5] ;
+ wire \gpio_configure[13][6] ;
+ wire \gpio_configure[13][7] ;
+ wire \gpio_configure[13][8] ;
+ wire \gpio_configure[13][9] ;
+ wire \gpio_configure[14][0] ;
+ wire \gpio_configure[14][10] ;
+ wire \gpio_configure[14][11] ;
+ wire \gpio_configure[14][12] ;
+ wire \gpio_configure[14][1] ;
+ wire \gpio_configure[14][2] ;
+ wire \gpio_configure[14][3] ;
+ wire \gpio_configure[14][4] ;
+ wire \gpio_configure[14][5] ;
+ wire \gpio_configure[14][6] ;
+ wire \gpio_configure[14][7] ;
+ wire \gpio_configure[14][8] ;
+ wire \gpio_configure[14][9] ;
+ wire \gpio_configure[15][0] ;
+ wire \gpio_configure[15][10] ;
+ wire \gpio_configure[15][11] ;
+ wire \gpio_configure[15][12] ;
+ wire \gpio_configure[15][1] ;
+ wire \gpio_configure[15][2] ;
+ wire \gpio_configure[15][3] ;
+ wire \gpio_configure[15][4] ;
+ wire \gpio_configure[15][5] ;
+ wire \gpio_configure[15][6] ;
+ wire \gpio_configure[15][7] ;
+ wire \gpio_configure[15][8] ;
+ wire \gpio_configure[15][9] ;
+ wire \gpio_configure[16][0] ;
+ wire \gpio_configure[16][10] ;
+ wire \gpio_configure[16][11] ;
+ wire \gpio_configure[16][12] ;
+ wire \gpio_configure[16][1] ;
+ wire \gpio_configure[16][2] ;
+ wire \gpio_configure[16][3] ;
+ wire \gpio_configure[16][4] ;
+ wire \gpio_configure[16][5] ;
+ wire \gpio_configure[16][6] ;
+ wire \gpio_configure[16][7] ;
+ wire \gpio_configure[16][8] ;
+ wire \gpio_configure[16][9] ;
+ wire \gpio_configure[17][0] ;
+ wire \gpio_configure[17][10] ;
+ wire \gpio_configure[17][11] ;
+ wire \gpio_configure[17][12] ;
+ wire \gpio_configure[17][1] ;
+ wire \gpio_configure[17][2] ;
+ wire \gpio_configure[17][3] ;
+ wire \gpio_configure[17][4] ;
+ wire \gpio_configure[17][5] ;
+ wire \gpio_configure[17][6] ;
+ wire \gpio_configure[17][7] ;
+ wire \gpio_configure[17][8] ;
+ wire \gpio_configure[17][9] ;
+ wire \gpio_configure[18][0] ;
+ wire \gpio_configure[18][10] ;
+ wire \gpio_configure[18][11] ;
+ wire \gpio_configure[18][12] ;
+ wire \gpio_configure[18][1] ;
+ wire \gpio_configure[18][2] ;
+ wire \gpio_configure[18][3] ;
+ wire \gpio_configure[18][4] ;
+ wire \gpio_configure[18][5] ;
+ wire \gpio_configure[18][6] ;
+ wire \gpio_configure[18][7] ;
+ wire \gpio_configure[18][8] ;
+ wire \gpio_configure[18][9] ;
+ wire \gpio_configure[19][0] ;
+ wire \gpio_configure[19][10] ;
+ wire \gpio_configure[19][11] ;
+ wire \gpio_configure[19][12] ;
+ wire \gpio_configure[19][1] ;
+ wire \gpio_configure[19][2] ;
+ wire \gpio_configure[19][3] ;
+ wire \gpio_configure[19][4] ;
+ wire \gpio_configure[19][5] ;
+ wire \gpio_configure[19][6] ;
+ wire \gpio_configure[19][7] ;
+ wire \gpio_configure[19][8] ;
+ wire \gpio_configure[19][9] ;
+ wire \gpio_configure[1][0] ;
+ wire \gpio_configure[1][10] ;
+ wire \gpio_configure[1][11] ;
+ wire \gpio_configure[1][12] ;
+ wire \gpio_configure[1][1] ;
+ wire \gpio_configure[1][2] ;
+ wire \gpio_configure[1][3] ;
+ wire \gpio_configure[1][4] ;
+ wire \gpio_configure[1][5] ;
+ wire \gpio_configure[1][6] ;
+ wire \gpio_configure[1][7] ;
+ wire \gpio_configure[1][8] ;
+ wire \gpio_configure[1][9] ;
+ wire \gpio_configure[20][0] ;
+ wire \gpio_configure[20][10] ;
+ wire \gpio_configure[20][11] ;
+ wire \gpio_configure[20][12] ;
+ wire \gpio_configure[20][1] ;
+ wire \gpio_configure[20][2] ;
+ wire \gpio_configure[20][3] ;
+ wire \gpio_configure[20][4] ;
+ wire \gpio_configure[20][5] ;
+ wire \gpio_configure[20][6] ;
+ wire \gpio_configure[20][7] ;
+ wire \gpio_configure[20][8] ;
+ wire \gpio_configure[20][9] ;
+ wire \gpio_configure[21][0] ;
+ wire \gpio_configure[21][10] ;
+ wire \gpio_configure[21][11] ;
+ wire \gpio_configure[21][12] ;
+ wire \gpio_configure[21][1] ;
+ wire \gpio_configure[21][2] ;
+ wire \gpio_configure[21][3] ;
+ wire \gpio_configure[21][4] ;
+ wire \gpio_configure[21][5] ;
+ wire \gpio_configure[21][6] ;
+ wire \gpio_configure[21][7] ;
+ wire \gpio_configure[21][8] ;
+ wire \gpio_configure[21][9] ;
+ wire \gpio_configure[22][0] ;
+ wire \gpio_configure[22][10] ;
+ wire \gpio_configure[22][11] ;
+ wire \gpio_configure[22][12] ;
+ wire \gpio_configure[22][1] ;
+ wire \gpio_configure[22][2] ;
+ wire \gpio_configure[22][3] ;
+ wire \gpio_configure[22][4] ;
+ wire \gpio_configure[22][5] ;
+ wire \gpio_configure[22][6] ;
+ wire \gpio_configure[22][7] ;
+ wire \gpio_configure[22][8] ;
+ wire \gpio_configure[22][9] ;
+ wire \gpio_configure[23][0] ;
+ wire \gpio_configure[23][10] ;
+ wire \gpio_configure[23][11] ;
+ wire \gpio_configure[23][12] ;
+ wire \gpio_configure[23][1] ;
+ wire \gpio_configure[23][2] ;
+ wire \gpio_configure[23][3] ;
+ wire \gpio_configure[23][4] ;
+ wire \gpio_configure[23][5] ;
+ wire \gpio_configure[23][6] ;
+ wire \gpio_configure[23][7] ;
+ wire \gpio_configure[23][8] ;
+ wire \gpio_configure[23][9] ;
+ wire \gpio_configure[24][0] ;
+ wire \gpio_configure[24][10] ;
+ wire \gpio_configure[24][11] ;
+ wire \gpio_configure[24][12] ;
+ wire \gpio_configure[24][1] ;
+ wire \gpio_configure[24][2] ;
+ wire \gpio_configure[24][3] ;
+ wire \gpio_configure[24][4] ;
+ wire \gpio_configure[24][5] ;
+ wire \gpio_configure[24][6] ;
+ wire \gpio_configure[24][7] ;
+ wire \gpio_configure[24][8] ;
+ wire \gpio_configure[24][9] ;
+ wire \gpio_configure[25][0] ;
+ wire \gpio_configure[25][10] ;
+ wire \gpio_configure[25][11] ;
+ wire \gpio_configure[25][12] ;
+ wire \gpio_configure[25][1] ;
+ wire \gpio_configure[25][2] ;
+ wire \gpio_configure[25][3] ;
+ wire \gpio_configure[25][4] ;
+ wire \gpio_configure[25][5] ;
+ wire \gpio_configure[25][6] ;
+ wire \gpio_configure[25][7] ;
+ wire \gpio_configure[25][8] ;
+ wire \gpio_configure[25][9] ;
+ wire \gpio_configure[26][0] ;
+ wire \gpio_configure[26][10] ;
+ wire \gpio_configure[26][11] ;
+ wire \gpio_configure[26][12] ;
+ wire \gpio_configure[26][1] ;
+ wire \gpio_configure[26][2] ;
+ wire \gpio_configure[26][3] ;
+ wire \gpio_configure[26][4] ;
+ wire \gpio_configure[26][5] ;
+ wire \gpio_configure[26][6] ;
+ wire \gpio_configure[26][7] ;
+ wire \gpio_configure[26][8] ;
+ wire \gpio_configure[26][9] ;
+ wire \gpio_configure[27][0] ;
+ wire \gpio_configure[27][10] ;
+ wire \gpio_configure[27][11] ;
+ wire \gpio_configure[27][12] ;
+ wire \gpio_configure[27][1] ;
+ wire \gpio_configure[27][2] ;
+ wire \gpio_configure[27][3] ;
+ wire \gpio_configure[27][4] ;
+ wire \gpio_configure[27][5] ;
+ wire \gpio_configure[27][6] ;
+ wire \gpio_configure[27][7] ;
+ wire \gpio_configure[27][8] ;
+ wire \gpio_configure[27][9] ;
+ wire \gpio_configure[28][0] ;
+ wire \gpio_configure[28][10] ;
+ wire \gpio_configure[28][11] ;
+ wire \gpio_configure[28][12] ;
+ wire \gpio_configure[28][1] ;
+ wire \gpio_configure[28][2] ;
+ wire \gpio_configure[28][3] ;
+ wire \gpio_configure[28][4] ;
+ wire \gpio_configure[28][5] ;
+ wire \gpio_configure[28][6] ;
+ wire \gpio_configure[28][7] ;
+ wire \gpio_configure[28][8] ;
+ wire \gpio_configure[28][9] ;
+ wire \gpio_configure[29][0] ;
+ wire \gpio_configure[29][10] ;
+ wire \gpio_configure[29][11] ;
+ wire \gpio_configure[29][12] ;
+ wire \gpio_configure[29][1] ;
+ wire \gpio_configure[29][2] ;
+ wire \gpio_configure[29][3] ;
+ wire \gpio_configure[29][4] ;
+ wire \gpio_configure[29][5] ;
+ wire \gpio_configure[29][6] ;
+ wire \gpio_configure[29][7] ;
+ wire \gpio_configure[29][8] ;
+ wire \gpio_configure[29][9] ;
+ wire \gpio_configure[2][0] ;
+ wire \gpio_configure[2][10] ;
+ wire \gpio_configure[2][11] ;
+ wire \gpio_configure[2][12] ;
+ wire \gpio_configure[2][1] ;
+ wire \gpio_configure[2][2] ;
+ wire \gpio_configure[2][3] ;
+ wire \gpio_configure[2][4] ;
+ wire \gpio_configure[2][5] ;
+ wire \gpio_configure[2][6] ;
+ wire \gpio_configure[2][7] ;
+ wire \gpio_configure[2][8] ;
+ wire \gpio_configure[2][9] ;
+ wire \gpio_configure[30][0] ;
+ wire \gpio_configure[30][10] ;
+ wire \gpio_configure[30][11] ;
+ wire \gpio_configure[30][12] ;
+ wire \gpio_configure[30][1] ;
+ wire \gpio_configure[30][2] ;
+ wire \gpio_configure[30][3] ;
+ wire \gpio_configure[30][4] ;
+ wire \gpio_configure[30][5] ;
+ wire \gpio_configure[30][6] ;
+ wire \gpio_configure[30][7] ;
+ wire \gpio_configure[30][8] ;
+ wire \gpio_configure[30][9] ;
+ wire \gpio_configure[31][0] ;
+ wire \gpio_configure[31][10] ;
+ wire \gpio_configure[31][11] ;
+ wire \gpio_configure[31][12] ;
+ wire \gpio_configure[31][1] ;
+ wire \gpio_configure[31][2] ;
+ wire \gpio_configure[31][3] ;
+ wire \gpio_configure[31][4] ;
+ wire \gpio_configure[31][5] ;
+ wire \gpio_configure[31][6] ;
+ wire \gpio_configure[31][7] ;
+ wire \gpio_configure[31][8] ;
+ wire \gpio_configure[31][9] ;
+ wire \gpio_configure[32][0] ;
+ wire \gpio_configure[32][10] ;
+ wire \gpio_configure[32][11] ;
+ wire \gpio_configure[32][12] ;
+ wire \gpio_configure[32][1] ;
+ wire \gpio_configure[32][2] ;
+ wire \gpio_configure[32][3] ;
+ wire \gpio_configure[32][4] ;
+ wire \gpio_configure[32][5] ;
+ wire \gpio_configure[32][6] ;
+ wire \gpio_configure[32][7] ;
+ wire \gpio_configure[32][8] ;
+ wire \gpio_configure[32][9] ;
+ wire \gpio_configure[33][0] ;
+ wire \gpio_configure[33][10] ;
+ wire \gpio_configure[33][11] ;
+ wire \gpio_configure[33][12] ;
+ wire \gpio_configure[33][1] ;
+ wire \gpio_configure[33][2] ;
+ wire \gpio_configure[33][3] ;
+ wire \gpio_configure[33][4] ;
+ wire \gpio_configure[33][5] ;
+ wire \gpio_configure[33][6] ;
+ wire \gpio_configure[33][7] ;
+ wire \gpio_configure[33][8] ;
+ wire \gpio_configure[33][9] ;
+ wire \gpio_configure[34][0] ;
+ wire \gpio_configure[34][10] ;
+ wire \gpio_configure[34][11] ;
+ wire \gpio_configure[34][12] ;
+ wire \gpio_configure[34][1] ;
+ wire \gpio_configure[34][2] ;
+ wire \gpio_configure[34][3] ;
+ wire \gpio_configure[34][4] ;
+ wire \gpio_configure[34][5] ;
+ wire \gpio_configure[34][6] ;
+ wire \gpio_configure[34][7] ;
+ wire \gpio_configure[34][8] ;
+ wire \gpio_configure[34][9] ;
+ wire \gpio_configure[35][0] ;
+ wire \gpio_configure[35][10] ;
+ wire \gpio_configure[35][11] ;
+ wire \gpio_configure[35][12] ;
+ wire \gpio_configure[35][1] ;
+ wire \gpio_configure[35][2] ;
+ wire \gpio_configure[35][3] ;
+ wire \gpio_configure[35][4] ;
+ wire \gpio_configure[35][5] ;
+ wire \gpio_configure[35][6] ;
+ wire \gpio_configure[35][7] ;
+ wire \gpio_configure[35][8] ;
+ wire \gpio_configure[35][9] ;
+ wire \gpio_configure[36][0] ;
+ wire \gpio_configure[36][10] ;
+ wire \gpio_configure[36][11] ;
+ wire \gpio_configure[36][12] ;
+ wire \gpio_configure[36][1] ;
+ wire \gpio_configure[36][2] ;
+ wire \gpio_configure[36][3] ;
+ wire \gpio_configure[36][4] ;
+ wire \gpio_configure[36][5] ;
+ wire \gpio_configure[36][6] ;
+ wire \gpio_configure[36][7] ;
+ wire \gpio_configure[36][8] ;
+ wire \gpio_configure[36][9] ;
+ wire \gpio_configure[37][0] ;
+ wire \gpio_configure[37][10] ;
+ wire \gpio_configure[37][11] ;
+ wire \gpio_configure[37][12] ;
+ wire \gpio_configure[37][1] ;
+ wire \gpio_configure[37][2] ;
+ wire \gpio_configure[37][3] ;
+ wire \gpio_configure[37][4] ;
+ wire \gpio_configure[37][5] ;
+ wire \gpio_configure[37][6] ;
+ wire \gpio_configure[37][7] ;
+ wire \gpio_configure[37][8] ;
+ wire \gpio_configure[37][9] ;
+ wire \gpio_configure[3][0] ;
+ wire \gpio_configure[3][10] ;
+ wire \gpio_configure[3][11] ;
+ wire \gpio_configure[3][12] ;
+ wire \gpio_configure[3][1] ;
+ wire \gpio_configure[3][2] ;
+ wire \gpio_configure[3][3] ;
+ wire \gpio_configure[3][4] ;
+ wire \gpio_configure[3][5] ;
+ wire \gpio_configure[3][6] ;
+ wire \gpio_configure[3][7] ;
+ wire \gpio_configure[3][8] ;
+ wire \gpio_configure[3][9] ;
+ wire \gpio_configure[4][0] ;
+ wire \gpio_configure[4][10] ;
+ wire \gpio_configure[4][11] ;
+ wire \gpio_configure[4][12] ;
+ wire \gpio_configure[4][1] ;
+ wire \gpio_configure[4][2] ;
+ wire \gpio_configure[4][3] ;
+ wire \gpio_configure[4][4] ;
+ wire \gpio_configure[4][5] ;
+ wire \gpio_configure[4][6] ;
+ wire \gpio_configure[4][7] ;
+ wire \gpio_configure[4][8] ;
+ wire \gpio_configure[4][9] ;
+ wire \gpio_configure[5][0] ;
+ wire \gpio_configure[5][10] ;
+ wire \gpio_configure[5][11] ;
+ wire \gpio_configure[5][12] ;
+ wire \gpio_configure[5][1] ;
+ wire \gpio_configure[5][2] ;
+ wire \gpio_configure[5][3] ;
+ wire \gpio_configure[5][4] ;
+ wire \gpio_configure[5][5] ;
+ wire \gpio_configure[5][6] ;
+ wire \gpio_configure[5][7] ;
+ wire \gpio_configure[5][8] ;
+ wire \gpio_configure[5][9] ;
+ wire \gpio_configure[6][0] ;
+ wire \gpio_configure[6][10] ;
+ wire \gpio_configure[6][11] ;
+ wire \gpio_configure[6][12] ;
+ wire \gpio_configure[6][1] ;
+ wire \gpio_configure[6][2] ;
+ wire \gpio_configure[6][3] ;
+ wire \gpio_configure[6][4] ;
+ wire \gpio_configure[6][5] ;
+ wire \gpio_configure[6][6] ;
+ wire \gpio_configure[6][7] ;
+ wire \gpio_configure[6][8] ;
+ wire \gpio_configure[6][9] ;
+ wire \gpio_configure[7][0] ;
+ wire \gpio_configure[7][10] ;
+ wire \gpio_configure[7][11] ;
+ wire \gpio_configure[7][12] ;
+ wire \gpio_configure[7][1] ;
+ wire \gpio_configure[7][2] ;
+ wire \gpio_configure[7][3] ;
+ wire \gpio_configure[7][4] ;
+ wire \gpio_configure[7][5] ;
+ wire \gpio_configure[7][6] ;
+ wire \gpio_configure[7][7] ;
+ wire \gpio_configure[7][8] ;
+ wire \gpio_configure[7][9] ;
+ wire \gpio_configure[8][0] ;
+ wire \gpio_configure[8][10] ;
+ wire \gpio_configure[8][11] ;
+ wire \gpio_configure[8][12] ;
+ wire \gpio_configure[8][1] ;
+ wire \gpio_configure[8][2] ;
+ wire \gpio_configure[8][3] ;
+ wire \gpio_configure[8][4] ;
+ wire \gpio_configure[8][5] ;
+ wire \gpio_configure[8][6] ;
+ wire \gpio_configure[8][7] ;
+ wire \gpio_configure[8][8] ;
+ wire \gpio_configure[8][9] ;
+ wire \gpio_configure[9][0] ;
+ wire \gpio_configure[9][10] ;
+ wire \gpio_configure[9][11] ;
+ wire \gpio_configure[9][12] ;
+ wire \gpio_configure[9][1] ;
+ wire \gpio_configure[9][2] ;
+ wire \gpio_configure[9][3] ;
+ wire \gpio_configure[9][4] ;
+ wire \gpio_configure[9][5] ;
+ wire \gpio_configure[9][6] ;
+ wire \gpio_configure[9][7] ;
+ wire \gpio_configure[9][8] ;
+ wire \gpio_configure[9][9] ;
+ wire \hkspi.SDO ;
+ wire \hkspi.addr[0] ;
+ wire \hkspi.addr[1] ;
+ wire \hkspi.addr[2] ;
+ wire \hkspi.addr[3] ;
+ wire \hkspi.addr[4] ;
+ wire \hkspi.addr[5] ;
+ wire \hkspi.addr[6] ;
+ wire \hkspi.addr[7] ;
+ wire \hkspi.count[0] ;
+ wire \hkspi.count[1] ;
+ wire \hkspi.count[2] ;
+ wire \hkspi.fixed[0] ;
+ wire \hkspi.fixed[1] ;
+ wire \hkspi.fixed[2] ;
+ wire \hkspi.idata[1] ;
+ wire \hkspi.idata[2] ;
+ wire \hkspi.idata[3] ;
+ wire \hkspi.idata[4] ;
+ wire \hkspi.idata[5] ;
+ wire \hkspi.idata[6] ;
+ wire \hkspi.idata[7] ;
+ wire \hkspi.ldata[0] ;
+ wire \hkspi.ldata[1] ;
+ wire \hkspi.ldata[2] ;
+ wire \hkspi.ldata[3] ;
+ wire \hkspi.ldata[4] ;
+ wire \hkspi.ldata[5] ;
+ wire \hkspi.ldata[6] ;
+ wire \hkspi.odata[1] ;
+ wire \hkspi.odata[2] ;
+ wire \hkspi.odata[3] ;
+ wire \hkspi.odata[4] ;
+ wire \hkspi.odata[5] ;
+ wire \hkspi.odata[6] ;
+ wire \hkspi.odata[7] ;
+ wire \hkspi.pass_thru_mgmt ;
+ wire \hkspi.pass_thru_mgmt_delay ;
+ wire \hkspi.pass_thru_user ;
+ wire \hkspi.pass_thru_user_delay ;
+ wire \hkspi.pre_pass_thru_mgmt ;
+ wire \hkspi.pre_pass_thru_user ;
+ wire \hkspi.rdstb ;
+ wire \hkspi.readmode ;
+ wire \hkspi.sdoenb ;
+ wire \hkspi.state[0] ;
+ wire \hkspi.state[1] ;
+ wire \hkspi.state[2] ;
+ wire \hkspi.state[3] ;
+ wire \hkspi.state[4] ;
+ wire \hkspi.writemode ;
+ wire \hkspi.wrstb ;
+ wire hkspi_disable;
+ wire irq_1_inputsrc;
+ wire irq_2_inputsrc;
+ wire \mgmt_gpio_data[0] ;
+ wire \mgmt_gpio_data[10] ;
+ wire \mgmt_gpio_data[11] ;
+ wire \mgmt_gpio_data[12] ;
+ wire \mgmt_gpio_data[13] ;
+ wire \mgmt_gpio_data[14] ;
+ wire \mgmt_gpio_data[15] ;
+ wire \mgmt_gpio_data[16] ;
+ wire \mgmt_gpio_data[17] ;
+ wire \mgmt_gpio_data[18] ;
+ wire \mgmt_gpio_data[19] ;
+ wire \mgmt_gpio_data[1] ;
+ wire \mgmt_gpio_data[20] ;
+ wire \mgmt_gpio_data[21] ;
+ wire \mgmt_gpio_data[22] ;
+ wire \mgmt_gpio_data[23] ;
+ wire \mgmt_gpio_data[24] ;
+ wire \mgmt_gpio_data[25] ;
+ wire \mgmt_gpio_data[26] ;
+ wire \mgmt_gpio_data[27] ;
+ wire \mgmt_gpio_data[28] ;
+ wire \mgmt_gpio_data[29] ;
+ wire \mgmt_gpio_data[2] ;
+ wire \mgmt_gpio_data[30] ;
+ wire \mgmt_gpio_data[31] ;
+ wire \mgmt_gpio_data[32] ;
+ wire \mgmt_gpio_data[33] ;
+ wire \mgmt_gpio_data[34] ;
+ wire \mgmt_gpio_data[35] ;
+ wire \mgmt_gpio_data[36] ;
+ wire \mgmt_gpio_data[37] ;
+ wire \mgmt_gpio_data[3] ;
+ wire \mgmt_gpio_data[4] ;
+ wire \mgmt_gpio_data[5] ;
+ wire \mgmt_gpio_data[6] ;
+ wire \mgmt_gpio_data[7] ;
+ wire \mgmt_gpio_data[8] ;
+ wire \mgmt_gpio_data[9] ;
+ wire \mgmt_gpio_data_buf[0] ;
+ wire \mgmt_gpio_data_buf[10] ;
+ wire \mgmt_gpio_data_buf[11] ;
+ wire \mgmt_gpio_data_buf[12] ;
+ wire \mgmt_gpio_data_buf[13] ;
+ wire \mgmt_gpio_data_buf[14] ;
+ wire \mgmt_gpio_data_buf[15] ;
+ wire \mgmt_gpio_data_buf[16] ;
+ wire \mgmt_gpio_data_buf[17] ;
+ wire \mgmt_gpio_data_buf[18] ;
+ wire \mgmt_gpio_data_buf[19] ;
+ wire \mgmt_gpio_data_buf[1] ;
+ wire \mgmt_gpio_data_buf[20] ;
+ wire \mgmt_gpio_data_buf[21] ;
+ wire \mgmt_gpio_data_buf[22] ;
+ wire \mgmt_gpio_data_buf[23] ;
+ wire \mgmt_gpio_data_buf[2] ;
+ wire \mgmt_gpio_data_buf[3] ;
+ wire \mgmt_gpio_data_buf[4] ;
+ wire \mgmt_gpio_data_buf[5] ;
+ wire \mgmt_gpio_data_buf[6] ;
+ wire \mgmt_gpio_data_buf[7] ;
+ wire \mgmt_gpio_data_buf[8] ;
+ wire \mgmt_gpio_data_buf[9] ;
+ wire \mgmt_gpio_out_pre[10] ;
+ wire \mgmt_gpio_out_pre[13] ;
+ wire \mgmt_gpio_out_pre[14] ;
+ wire \mgmt_gpio_out_pre[15] ;
+ wire \mgmt_gpio_out_pre[32] ;
+ wire \mgmt_gpio_out_pre[33] ;
+ wire \mgmt_gpio_out_pre[6] ;
+ wire \mgmt_gpio_out_pre[8] ;
+ wire \mgmt_gpio_out_pre[9] ;
+ wire net1;
+ wire net10;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net11;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net12;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net13;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+ wire net136;
+ wire net137;
+ wire net138;
+ wire net139;
+ wire net14;
+ wire net140;
+ wire net141;
+ wire net142;
+ wire net143;
+ wire net144;
+ wire net145;
+ wire net146;
+ wire net147;
+ wire net148;
+ wire net149;
+ wire net15;
+ wire net150;
+ wire net151;
+ wire net152;
+ wire net153;
+ wire net154;
+ wire net155;
+ wire net156;
+ wire net157;
+ wire net158;
+ wire net159;
+ wire net16;
+ wire net160;
+ wire net161;
+ wire net162;
+ wire net163;
+ wire net164;
+ wire net165;
+ wire net166;
+ wire net167;
+ wire net168;
+ wire net169;
+ wire net17;
+ wire net170;
+ wire net171;
+ wire net172;
+ wire net173;
+ wire net174;
+ wire net175;
+ wire net176;
+ wire net177;
+ wire net178;
+ wire net179;
+ wire net18;
+ wire net180;
+ wire net181;
+ wire net182;
+ wire net183;
+ wire net184;
+ wire net185;
+ wire net186;
+ wire net187;
+ wire net188;
+ wire net189;
+ wire net19;
+ wire net190;
+ wire net191;
+ wire net192;
+ wire net193;
+ wire net194;
+ wire net195;
+ wire net196;
+ wire net197;
+ wire net198;
+ wire net199;
+ wire net2;
+ wire net20;
+ wire net200;
+ wire net201;
+ wire net202;
+ wire net203;
+ wire net204;
+ wire net205;
+ wire net206;
+ wire net207;
+ wire net208;
+ wire net209;
+ wire net21;
+ wire net210;
+ wire net211;
+ wire net212;
+ wire net213;
+ wire net214;
+ wire net215;
+ wire net216;
+ wire net217;
+ wire net218;
+ wire net219;
+ wire net22;
+ wire net220;
+ wire net221;
+ wire net222;
+ wire net223;
+ wire net224;
+ wire net225;
+ wire net226;
+ wire net227;
+ wire net228;
+ wire net229;
+ wire net23;
+ wire net230;
+ wire net231;
+ wire net232;
+ wire net233;
+ wire net234;
+ wire net235;
+ wire net236;
+ wire net237;
+ wire net238;
+ wire net239;
+ wire net24;
+ wire net240;
+ wire net241;
+ wire net242;
+ wire net243;
+ wire net244;
+ wire net245;
+ wire net246;
+ wire net247;
+ wire net248;
+ wire net249;
+ wire net25;
+ wire net250;
+ wire net251;
+ wire net252;
+ wire net253;
+ wire net254;
+ wire net255;
+ wire net256;
+ wire net257;
+ wire net258;
+ wire net259;
+ wire net26;
+ wire net260;
+ wire net261;
+ wire net262;
+ wire net263;
+ wire net264;
+ wire net265;
+ wire net266;
+ wire net267;
+ wire net268;
+ wire net269;
+ wire net27;
+ wire net270;
+ wire net271;
+ wire net272;
+ wire net273;
+ wire net274;
+ wire net275;
+ wire net276;
+ wire net277;
+ wire net278;
+ wire net279;
+ wire net28;
+ wire net280;
+ wire net281;
+ wire net282;
+ wire net283;
+ wire net284;
+ wire net285;
+ wire net286;
+ wire net287;
+ wire net288;
+ wire net289;
+ wire net29;
+ wire net290;
+ wire net291;
+ wire net292;
+ wire net293;
+ wire net294;
+ wire net295;
+ wire net296;
+ wire net297;
+ wire net298;
+ wire net299;
+ wire net3;
+ wire net30;
+ wire net300;
+ wire net301;
+ wire net302;
+ wire net303;
+ wire net304;
+ wire net305;
+ wire net306;
+ wire net307;
+ wire net308;
+ wire net309;
+ wire net31;
+ wire net310;
+ wire net311;
+ wire net312;
+ wire net313;
+ wire net314;
+ wire net315;
+ wire net316;
+ wire net317;
+ wire net318;
+ wire net319;
+ wire net32;
+ wire net320;
+ wire net321;
+ wire net322;
+ wire net323;
+ wire net324;
+ wire net325;
+ wire net326;
+ wire net327;
+ wire net328;
+ wire net329;
+ wire net33;
+ wire net330;
+ wire net331;
+ wire net332;
+ wire net333;
+ wire net334;
+ wire net335;
+ wire net336;
+ wire net337;
+ wire net338;
+ wire net339;
+ wire net34;
+ wire net340;
+ wire net341;
+ wire net342;
+ wire net343;
+ wire net344;
+ wire net345;
+ wire net346;
+ wire net347;
+ wire net348;
+ wire net349;
+ wire net35;
+ wire net350;
+ wire net351;
+ wire net352;
+ wire net353;
+ wire net354;
+ wire net355;
+ wire net356;
+ wire net357;
+ wire net358;
+ wire net359;
+ wire net36;
+ wire net360;
+ wire net361;
+ wire net362;
+ wire net363;
+ wire net364;
+ wire net365;
+ wire net366;
+ wire net367;
+ wire net368;
+ wire net369;
+ wire net37;
+ wire net370;
+ wire net371;
+ wire net372;
+ wire net373;
+ wire net374;
+ wire net375;
+ wire net376;
+ wire net377;
+ wire net378;
+ wire net379;
+ wire net38;
+ wire net380;
+ wire net381;
+ wire net382;
+ wire net383;
+ wire net384;
+ wire net385;
+ wire net386;
+ wire net387;
+ wire net388;
+ wire net389;
+ wire net39;
+ wire net390;
+ wire net391;
+ wire net392;
+ wire net393;
+ wire net394;
+ wire net4;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net5;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net6;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net7;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net8;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net9;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98;
+ wire net99;
+ wire \pad_count_1[0] ;
+ wire \pad_count_1[1] ;
+ wire \pad_count_1[2] ;
+ wire \pad_count_1[3] ;
+ wire \pad_count_1[4] ;
+ wire \pad_count_2[0] ;
+ wire \pad_count_2[1] ;
+ wire \pad_count_2[2] ;
+ wire \pad_count_2[3] ;
+ wire \pad_count_2[4] ;
+ wire \pad_count_2[5] ;
+ wire reset_reg;
+ wire serial_bb_clock;
+ wire serial_bb_data_1;
+ wire serial_bb_data_2;
+ wire serial_bb_enable;
+ wire serial_bb_load;
+ wire serial_bb_resetn;
+ wire serial_busy;
+ wire serial_clock_pre;
+ wire \serial_data_staging_1[0] ;
+ wire \serial_data_staging_1[10] ;
+ wire \serial_data_staging_1[11] ;
+ wire \serial_data_staging_1[12] ;
+ wire \serial_data_staging_1[1] ;
+ wire \serial_data_staging_1[2] ;
+ wire \serial_data_staging_1[3] ;
+ wire \serial_data_staging_1[4] ;
+ wire \serial_data_staging_1[5] ;
+ wire \serial_data_staging_1[6] ;
+ wire \serial_data_staging_1[7] ;
+ wire \serial_data_staging_1[8] ;
+ wire \serial_data_staging_1[9] ;
+ wire \serial_data_staging_2[0] ;
+ wire \serial_data_staging_2[10] ;
+ wire \serial_data_staging_2[11] ;
+ wire \serial_data_staging_2[12] ;
+ wire \serial_data_staging_2[1] ;
+ wire \serial_data_staging_2[2] ;
+ wire \serial_data_staging_2[3] ;
+ wire \serial_data_staging_2[4] ;
+ wire \serial_data_staging_2[5] ;
+ wire \serial_data_staging_2[6] ;
+ wire \serial_data_staging_2[7] ;
+ wire \serial_data_staging_2[8] ;
+ wire \serial_data_staging_2[9] ;
+ wire serial_load_pre;
+ wire serial_resetn_pre;
+ wire serial_xfer;
+ wire trap_output_dest;
+ wire \wbbd_addr[0] ;
+ wire \wbbd_addr[1] ;
+ wire \wbbd_addr[2] ;
+ wire \wbbd_addr[3] ;
+ wire \wbbd_addr[4] ;
+ wire \wbbd_addr[5] ;
+ wire \wbbd_addr[6] ;
+ wire wbbd_busy;
+ wire \wbbd_data[0] ;
+ wire \wbbd_data[1] ;
+ wire \wbbd_data[2] ;
+ wire \wbbd_data[3] ;
+ wire \wbbd_data[4] ;
+ wire \wbbd_data[5] ;
+ wire \wbbd_data[6] ;
+ wire \wbbd_data[7] ;
+ wire wbbd_sck;
+ wire \wbbd_state[0] ;
+ wire \wbbd_state[1] ;
+ wire \wbbd_state[2] ;
+ wire \wbbd_state[3] ;
+ wire \wbbd_state[4] ;
+ wire \wbbd_state[5] ;
+ wire \wbbd_state[6] ;
+ wire \wbbd_state[7] ;
+ wire \wbbd_state[8] ;
+ wire \wbbd_state[9] ;
+ wire wbbd_write;
+ wire \xfer_count[0] ;
+ wire \xfer_count[1] ;
+ wire \xfer_count[2] ;
+ wire \xfer_count[3] ;
+ wire \xfer_state[0] ;
+ wire \xfer_state[1] ;
+ wire \xfer_state[2] ;
+ wire \xfer_state[3] ;
+ wire [4:0] clknet_0_mgmt_gpio_in;
+ wire [4:0] clknet_1_0_0_mgmt_gpio_in;
+ wire [4:0] clknet_1_0_1_mgmt_gpio_in;
+ wire [4:0] clknet_1_1_0_mgmt_gpio_in;
+ wire [4:0] clknet_1_1_1_mgmt_gpio_in;
+ wire [4:0] clknet_2_0_0_mgmt_gpio_in;
+ wire [4:0] clknet_2_1_0_mgmt_gpio_in;
+ wire [4:0] clknet_2_2_0_mgmt_gpio_in;
+ wire [4:0] clknet_2_3_0_mgmt_gpio_in;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA_0 (.DIODE(user_clock),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_1 (.DIODE(wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_10 (.DIODE(_0113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_100 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_101 (.DIODE(net36),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_102 (.DIODE(net36),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_103 (.DIODE(net37),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_104 (.DIODE(net38),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_105 (.DIODE(net67),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_106 (.DIODE(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_107 (.DIODE(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_108 (.DIODE(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_109 (.DIODE(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_11 (.DIODE(_0115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_110 (.DIODE(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_111 (.DIODE(net80),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_112 (.DIODE(net81),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_113 (.DIODE(net82),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_114 (.DIODE(net85),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_115 (.DIODE(net85),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_116 (.DIODE(net85),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_117 (.DIODE(net85),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_118 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_119 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_12 (.DIODE(_0115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_120 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_121 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_122 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_123 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_124 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_125 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_126 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_127 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_128 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_129 (.DIODE(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_13 (.DIODE(_0115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_130 (.DIODE(net87),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_131 (.DIODE(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_132 (.DIODE(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_133 (.DIODE(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_134 (.DIODE(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_135 (.DIODE(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_136 (.DIODE(net91),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_137 (.DIODE(net91),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_138 (.DIODE(_0085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_139 (.DIODE(_0093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_14 (.DIODE(_0117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_140 (.DIODE(_0107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_141 (.DIODE(_0107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_142 (.DIODE(_0109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_143 (.DIODE(_0134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_144 (.DIODE(_0144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_145 (.DIODE(_0144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_146 (.DIODE(_0144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_147 (.DIODE(_0152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_148 (.DIODE(_0152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_149 (.DIODE(_1023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_15 (.DIODE(_0119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_150 (.DIODE(_1043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_151 (.DIODE(_1106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_152 (.DIODE(_1110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_153 (.DIODE(_1181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_154 (.DIODE(_1245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_155 (.DIODE(_1245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_156 (.DIODE(_1245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_157 (.DIODE(_1275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_158 (.DIODE(_1292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_159 (.DIODE(_1292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_16 (.DIODE(_0121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_160 (.DIODE(_1293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_161 (.DIODE(_2032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_162 (.DIODE(_2045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_163 (.DIODE(_2045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_164 (.DIODE(_2239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_165 (.DIODE(_2306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_166 (.DIODE(_2338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_167 (.DIODE(_2542_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_168 (.DIODE(_2554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_169 (.DIODE(_2554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_17 (.DIODE(_0123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_170 (.DIODE(_2637_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_171 (.DIODE(_2664_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_172 (.DIODE(_3010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_173 (.DIODE(_3010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_174 (.DIODE(_3435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_175 (.DIODE(_3600_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_176 (.DIODE(_4268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_177 (.DIODE(_4421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_178 (.DIODE(_4423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_179 (.DIODE(\gpio_configure[19][6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_18 (.DIODE(_0125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_180 (.DIODE(\hkspi.idata[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_181 (.DIODE(net125),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_182 (.DIODE(net126),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_183 (.DIODE(net126),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_184 (.DIODE(net2),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_185 (.DIODE(net201),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_186 (.DIODE(net201),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_187 (.DIODE(net205),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_188 (.DIODE(net206),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_189 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_19 (.DIODE(_0130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_190 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_191 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_192 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_193 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_194 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_195 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_196 (.DIODE(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_197 (.DIODE(net78),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_198 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_199 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_2 (.DIODE(_0079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_20 (.DIODE(_0132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_200 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_201 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_202 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_203 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_204 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_205 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_206 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_207 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_208 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_209 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_21 (.DIODE(_0142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_210 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_211 (.DIODE(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_212 (.DIODE(_1235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_213 (.DIODE(_1861_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_214 (.DIODE(_2414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_215 (.DIODE(_2416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_216 (.DIODE(_4410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_217 (.DIODE(net368),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_218 (.DIODE(net307),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_22 (.DIODE(_0142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_23 (.DIODE(_0148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_24 (.DIODE(_0150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_25 (.DIODE(_1043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_26 (.DIODE(_1047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_27 (.DIODE(_1047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_28 (.DIODE(_1047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_29 (.DIODE(_1158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_3 (.DIODE(_0083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_30 (.DIODE(_1160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_31 (.DIODE(_1160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_32 (.DIODE(_1160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_33 (.DIODE(_1160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_34 (.DIODE(_1256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_35 (.DIODE(_1267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_36 (.DIODE(_1283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_37 (.DIODE(_1311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_38 (.DIODE(_1313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_39 (.DIODE(_1320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_4 (.DIODE(_0103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_40 (.DIODE(_1321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_41 (.DIODE(_1329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_42 (.DIODE(_1329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_43 (.DIODE(_1336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_44 (.DIODE(_1345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_45 (.DIODE(_1367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_46 (.DIODE(_1387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_47 (.DIODE(_1399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_48 (.DIODE(_1411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_49 (.DIODE(_1870_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_5 (.DIODE(_0103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_50 (.DIODE(_1890_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_51 (.DIODE(_1895_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_52 (.DIODE(_1899_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_53 (.DIODE(_1905_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_54 (.DIODE(_1937_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_55 (.DIODE(_1988_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_56 (.DIODE(_1993_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_57 (.DIODE(_2033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_58 (.DIODE(_2037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_59 (.DIODE(_2052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_6 (.DIODE(_0103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_60 (.DIODE(_2060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_61 (.DIODE(_2072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_62 (.DIODE(_2072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_63 (.DIODE(_2075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_64 (.DIODE(_2224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_65 (.DIODE(_2342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_66 (.DIODE(_2413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_67 (.DIODE(_2417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_68 (.DIODE(_2440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_69 (.DIODE(_2443_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_7 (.DIODE(_0105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_70 (.DIODE(_2464_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_71 (.DIODE(_2484_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_72 (.DIODE(_2520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_73 (.DIODE(_2520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_74 (.DIODE(_2563_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_75 (.DIODE(_2567_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_76 (.DIODE(_2582_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_77 (.DIODE(_2593_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_78 (.DIODE(_2645_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_79 (.DIODE(_2816_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_8 (.DIODE(_0111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_80 (.DIODE(_2977_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_81 (.DIODE(_2998_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_82 (.DIODE(_3151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_83 (.DIODE(_3309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_84 (.DIODE(_4000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_85 (.DIODE(_4206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_86 (.DIODE(_4206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_87 (.DIODE(_4417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_88 (.DIODE(_4432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_89 (.DIODE(_4436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_9 (.DIODE(_0113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_90 (.DIODE(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_91 (.DIODE(\hkspi.idata[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_92 (.DIODE(\mgmt_gpio_data[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_93 (.DIODE(net207),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_94 (.DIODE(net245),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_95 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_96 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_97 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_98 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__diode_2 ANTENNA_99 (.DIODE(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_117 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_130 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_145 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_152 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_173 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_180 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_187 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_194 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_208 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_216 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_230 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_244 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_251 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_258 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_265 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_272 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_287 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_294 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_3 FILLER_0_322 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_0_541 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_0_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_0_577 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_0_61 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_0_66 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_100_250 (.VGND(VGND),
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+ .VPB(VPWR),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPB(VPWR),
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+ .VPB(VPWR),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_100_9 (.VGND(VGND),
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+ .VPB(VPWR),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_101_106 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_101_143 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_101_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_101_169 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_173 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_185 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_101_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_101_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_101_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_101_275 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_101_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_101_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_308 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_101_31 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_101_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_101_326 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_101_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_373 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_101_385 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_101_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_425 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_101_43 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_101_435 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_461 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_101_473 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_101_484 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_492 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_101_500 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_517 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_101_52 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_541 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_101_553 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_559 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_101_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_567 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_101_574 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_599 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_101_611 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_101_615 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_101_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_101_68 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_101_79 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_101_91 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_101_99 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_105 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_102_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_117 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_102_124 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_13 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_144 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_156 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_168 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_180 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_102_192 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_209 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_102_221 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_244 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_102_25 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_102_262 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_268 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_102_287 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_102_298 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_102_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_102_305 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_102_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_102_330 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_102_357 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_363 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_102_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_369 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_102_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_102_387 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_102_397 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_403 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_41 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_102_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_102_437 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_103_169 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_103_225 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_103_237 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_103_247 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_103_255 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_103_263 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_103_271 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_103_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_103_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_103_290 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_103_30 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_103_326 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_103_346 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_103_355 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_103_367 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_103_378 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_103_384 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_103_411 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_103_419 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_6 FILLER_105_554 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_105_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_105_573 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_105_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_105_90 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_105_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_106_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_106_219 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_106_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_106_271 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_106_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_106_362 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_106_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_106_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_107_382 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_107_430 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_492 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_505 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_107_51 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_517 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_529 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_107_541 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_107_549 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_107_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_107_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_107_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_107_569 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_57 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_107_590 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_107_602 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_107_614 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_107_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_107_93 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_107_99 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_12 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_121 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_133 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_139 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_153 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_157 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_178 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_190 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_108_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_228 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_233 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_24 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_248 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_268 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_276 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_318 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_340 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_346 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_356 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_381 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_418 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_108_450 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_462 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_474 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_485 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_493 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_108_519 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_52 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_108_525 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_108_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_108_540 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_574 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_586 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_108_609 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_108_623 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_64 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_108_76 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_108_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_109_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_109_121 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_109_129 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_109_145 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_109_153 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_162 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_109_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_109_220 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_109_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_109_244 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_109_256 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_264 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_274 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_289 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_295 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_298 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_304 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_109_323 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_356 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_362 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_109_376 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_380 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_109_388 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_109_410 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_109_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_109_553 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_109_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_10_139 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_10_161 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_10_183 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_10_19 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_10_197 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_10_222 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_10_228 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_10_232 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_10_244 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_10_25 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_10_295 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_309 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_32 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_10_321 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_10_333 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_348 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_360 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_389 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_401 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_10_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_10_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_10_441 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_451 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_455 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_10_486 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_528 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_549 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_10_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_571 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_10_583 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_10_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_10_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_10_597 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_10_622 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_64 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_10_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_10_76 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_116 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_130 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_171 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_176 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_185 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_229 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_241 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_284 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_110_302 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_341 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_360 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_110_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_387 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_399 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_405 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_415 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_448 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_45 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_460 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_464 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_474 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_484 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_110_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_509 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_110_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_110_581 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_110_596 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_110_623 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_110_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_110_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_110_95 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_110_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_104 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_111_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_117 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_111_126 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_132 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_146 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_158 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_111_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_190 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_202 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_214 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_111_222 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_111_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_238 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_250 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_262 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_111_274 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_111_317 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_324 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_111_349 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_364 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_376 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_111_388 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_425 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_111_445 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_45 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_111_483 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_495 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_111_503 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_111_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_111_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_12 FILLER_111_543 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_111_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_111_606 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_111_62 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_112_138 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_112_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_112_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_112_333 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_112_357 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_113_523 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_113_531 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_113_539 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_113_547 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_113_557 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_113_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_113_573 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_113_585 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_113_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_113_610 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_113_617 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_113_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_113_84 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_113_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_113_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_116_273 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_425 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_455 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_11_465 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_11_49 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_11_495 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_503 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_523 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_11_535 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_547 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_11_559 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_11_573 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_11_585 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_591 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_11_596 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_600 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_11_608 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_11_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_11_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_11_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_11_85 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_11_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_120_118 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_132 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_158 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_170 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_182 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_194 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_207 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_219 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_231 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_120_243 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_120_251 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_120_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_120_261 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_120_271 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_282 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_120_294 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_120_304 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_318 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_120_330 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_347 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_120_359 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_120_363 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_120_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_120_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_120_382 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_120_390 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_402 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_120_414 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_433 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_445 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_457 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_120_470 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_120_48 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_488 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_120_504 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_533 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_120_54 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_120_554 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_120_558 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_586 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_120_60 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_120_602 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_7 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_120_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_120_85 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_120_97 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_121_104 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_121_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_128 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_121_140 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_121_148 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_121_160 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_121_169 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_121_17 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_121_175 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_121_183 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_121_211 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_121_222 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_121_228 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_121_240 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_121_252 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_121_262 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_121_274 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_121_281 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_121_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_121_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_121_310 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_121_320 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_121_332 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_121_337 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_121_345 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_121_349 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_374 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_121_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_121_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_121_42 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_431 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_121_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_121_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_121_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_121_466 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_121_478 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_121_482 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_490 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_121_502 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_121_512 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_121_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_538 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_121_550 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_121_558 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_121_596 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_121_612 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_121_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_121_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_121_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_121_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_121_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_122_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_122_116 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_122_128 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_122_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_122_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_122_157 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_122_178 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_122_190 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_122_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_122_20 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_235 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_247 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_259 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_271 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_283 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_122_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_295 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_122_322 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_326 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_334 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_346 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_358 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_408 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_433 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_122_465 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_122_47 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_122_473 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_489 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_122_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_514 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_526 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_545 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_55 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_581 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_122_61 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_122_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_122_74 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_122_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_122_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_122_92 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_123_101 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_123_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_123_137 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_123_145 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_176 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_188 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_123_194 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_123_216 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_243 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_269 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_273 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_123_288 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_298 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_304 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_123_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_322 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_123_334 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_343 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_123_355 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_363 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_123_373 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_123_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_123_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_397 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_43 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_123_436 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_465 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_123_499 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_123_558 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_123_561 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_123_580 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_123_588 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_123_613 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_123_617 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_123_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_123_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_123_74 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_123_85 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_124_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_124_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_124_118 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_124_129 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_124_136 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_124_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_124_151 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_124_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_124_168 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_124_180 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_124_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_124_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_124_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_124_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_124_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_126_389 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_127_273 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_128_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_424 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_436 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_128_464 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_128_474 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_477 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_489 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_501 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_128_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_128_53 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_128_531 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_568 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_128_580 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_61 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_128_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_128_620 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_128_73 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_128_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_128_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_128_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_106 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_131 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_147 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_15 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_160 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_183 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_195 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_207 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_129_219 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_129_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_129_238 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_268 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_305 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_317 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_325 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_335 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_373 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_129_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_39 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_129_413 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_422 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_129_430 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_441 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_447 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_129_456 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_468 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_480 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_129_492 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_496 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_129_525 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_537 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_129_545 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_129_555 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_129_559 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_129_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_572 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_584 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_596 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_608 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_129_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_63 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_129_75 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_87 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_129_91 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_129_97 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_12_110 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_12_114 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_12_136 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_12_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_146 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_158 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_170 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_182 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_12_19 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_12_194 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_197 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_209 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_12_221 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_12_246 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_12_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_12_273 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_12_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_12_300 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_309 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_347 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_12_35 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_12_359 (.VGND(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_12_373 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_12_381 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_12_390 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_12_411 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_12_419 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_12_421 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_12_429 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_44 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_442 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_454 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_12_466 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_12_474 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_12_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_487 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_12_499 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_12_507 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_12_518 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_12_529 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_12_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_12_555 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_56 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_12_582 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_12_80 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_12_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_12_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_130_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_130_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_130_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_129 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_137 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_144 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_150 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_162 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_174 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_195 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_130_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_210 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_222 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_230 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_240 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_265 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_277 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_289 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_130_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_317 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_130_327 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_331 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_130_341 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_356 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_373 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_392 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_40 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_404 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_130_416 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_130_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_438 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_446 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_456 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_464 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_496 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_508 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_130_52 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_520 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_130_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_542 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_130_554 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_130_562 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_130_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_130_80 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_131_103 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_111 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_131_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_126 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_138 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_150 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_131_162 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_131_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_131_193 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_131_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_131_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_131_225 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_25 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_263 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_131_275 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_131_293 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_299 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_131_307 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_131_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_319 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_131_344 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_131_357 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_131_375 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_131_384 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_40 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_430 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_462 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_131_472 (.VGND(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_12 FILLER_131_561 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_131_64 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_131_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_131_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_131_73 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_131_91 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_131_95 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_132_121 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_132_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_132_137 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_147 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_171 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_183 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_132_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_132_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_132_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_132_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_205 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_132_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_132_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_132_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_132_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_132_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_132_280 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_332 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_132_34 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_132_344 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_132_352 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_132_358 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_401 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_132_413 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_132_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_443 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_455 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_132_475 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_513 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_132_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_540 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_132_556 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_568 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_58 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_132_580 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_132_596 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_132_604 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_70 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_132_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_133_105 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_133_111 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_133_119 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_133_149 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_133_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_133_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_133_249 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_133_255 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_133_26 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_133_285 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_133_289 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_133_3 (.VGND(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_134_356 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_388 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_134_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_455 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_134_46 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_134_467 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_134_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_134_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_134_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_134_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_134_541 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_134_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_134_554 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_560 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_572 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_134_584 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_134_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_134_599 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_134_614 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_134_623 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_134_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_70 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_134_82 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_134_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_134_94 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_102 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_107 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_11 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_111 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_135 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_142 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_160 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_181 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_135_217 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_135_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_254 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_266 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_135_274 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_135_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_328 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_351 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_135_375 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_39 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_135_390 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_135_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_431 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_443 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_447 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_456 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_468 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_488 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_499 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_503 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_135_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_51 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_517 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_135_537 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_55 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_57 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_574 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_586 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_135_598 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_135_610 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_135_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_135_621 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_135_65 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_75 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_135_83 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_135_94 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_110 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_122 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_136_134 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_136_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_167 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_136_179 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_136_183 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_136_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_136_191 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_136_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_273 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_285 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_136_29 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_136_297 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_136_304 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_309 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_321 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_333 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_35 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_136_361 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_136_365 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_136_373 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_136_383 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_136_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_136_395 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_403 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_136_415 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_136_419 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_136_421 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_136_448 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_136_460 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_136_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_136_472 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_136_477 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_136_485 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_136_508 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_136_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_537 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_549 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_136_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_136_580 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_136_59 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_613 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_136_76 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_136_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_137_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_137_110 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_137_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_137_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_137_132 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_137_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_137_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_8 FILLER_137_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_137_274 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_137_34 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_137_46 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_137_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_137_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_137_509 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_137_54 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_137_545 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_137_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_137_576 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_137_599 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_137_60 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_137_615 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_137_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_138_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_138_153 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_138_165 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_138_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_138_300 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_138_33 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_138_349 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_139_249 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_139_257 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_139_268 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_139_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_139_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_139_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_139_299 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_139_304 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_139_312 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_139_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_139_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_139_349 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_139_359 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_139_371 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_12 FILLER_140_601 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_143_281 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_145_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_145_325 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_145_337 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_145_349 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_147_505 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_147_559 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_14_253 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_14_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_14_74 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_14_78 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_151_155 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_151_167 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_151_216 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_151_220 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_151_225 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_151_247 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_151_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_151_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_151_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_153_559 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_153_577 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_153_585 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_153_609 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_153_615 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__fill_1 FILLER_153_621 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_153_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_277 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_345 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_35 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_154_357 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_363 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_154_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_154_41 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_154_413 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_433 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_457 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_553 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_154_565 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_154_598 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_154_63 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_154_80 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_155_110 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_155_591 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_155_595 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_155_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_155_623 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_155_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_155_90 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_156_109 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_156_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_156_133 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_156_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_156_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_156_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_156_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_156_173 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_160_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_160_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_160_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_160_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_160_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_160_387 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_160_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_160_516 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_160_624 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_161_55 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_161_589 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_161_615 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_161_617 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_161_623 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_161_79 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_161_91 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_162_112 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_162_123 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_162_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_162_139 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_162_141 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_162_153 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_162_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_162_177 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_164_324 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_421 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_166_469 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_166_475 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_489 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_166_525 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_166_531 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_166_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_166_550 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_166_558 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_166_579 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_166_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_166_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_166_62 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_166_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_166_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_166_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_166_93 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_117 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_154 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_167_166 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_181 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_167_217 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_167_243 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_248 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_260 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_167_272 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_167_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_303 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_315 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_167_332 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_167_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_357 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_362 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_167_386 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_429 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_43 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_167_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_460 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_167_472 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_491 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_167_514 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_55 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_167_615 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_168_387 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_168_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_168_428 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_168_440 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_168_472 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_168_477 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_168_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_168_530 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_168_533 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_168_546 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_168_582 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_168_589 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_168_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_168_602 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_168_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_168_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_168_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_168_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_169_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_169_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_169_113 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_171_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_171_247 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_172_513 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_172_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_172_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_172_60 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_172_604 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_172_616 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_172_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_172_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_173_108 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_173_11 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_173_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_173_310 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_173_318 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_173_327 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_173_335 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_173_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_173_343 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_38 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_173_386 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_173_429 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_173_437 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_173_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_173_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_489 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_173_50 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_173_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_517 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_541 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_173_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_173_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_100 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_112 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_14 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_181 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_174_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_174_209 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_174_501 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_174_563 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_174_584 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_174_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_174_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_174_73 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_174_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_174_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_107 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_175_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_175_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_193 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_205 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_175_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_175_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_229 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_175_268 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_175_272 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_175_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_320 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_175_332 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_349 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_175_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_175_38 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_393 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_175_415 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_175_423 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_429 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_175_441 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_175_447 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_449 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_175_456 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_175_467 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_175_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_175_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_481 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_175_492 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_498 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_175_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_175_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_577 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_175_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_175_613 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_175_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_175_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_175_73 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_175_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_175_89 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_175_95 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_176_113 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_176_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_176_127 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_148 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_176_160 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_168 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_176_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_176_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_176_248 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_176_283 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_176_287 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_176_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_317 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_176_327 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_176_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_342 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_176_354 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_176_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_176_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_176_369 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_397 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_176_409 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_176_418 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_176_445 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_453 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_176_484 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_176_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_176_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_176_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_176_533 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_176_548 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_176_560 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_176_566 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_576 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_589 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_613 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_176_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_176_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_177_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_142 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_154 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_177_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_196 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_205 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_261 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_325 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_177_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_351 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_359 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_371 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_177_405 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_431 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_455 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_177_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_177_525 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_177_549 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_177_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_177_568 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_177_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_177_574 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_177_595 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_607 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_177_615 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_177_617 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_177_74 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_177_79 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_178_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_178_123 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_133 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_139 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_178_141 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_178_153 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_178_159 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_178_167 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_178_189 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_178_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_213 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_233 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_245 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_260 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_272 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_284 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_178_29 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_296 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_178_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_178_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_178_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_178_365 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_385 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_397 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_178_409 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_178_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_430 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_460 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_47 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_178_472 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_178_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_501 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_513 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_178_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_178_541 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_570 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_178_582 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_178_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_178_59 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_604 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_178_616 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_178_624 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_178_7 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_178_71 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_178_79 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_178_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_178_97 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_179_105 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_179_111 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_133 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_179_145 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_179_169 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_179_173 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_179_186 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_19 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_203 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_179_215 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_179_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_245 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_179_257 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_179_271 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_179_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_281 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_305 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_317 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_179_329 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_179_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_179_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_179_352 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_374 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_179_386 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_400 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_412 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_179_424 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_179_456 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_468 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_480 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_492 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_179_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_179_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_536 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_548 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_179_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_179_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_179_614 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_179_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_179_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_17_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_17_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_17_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_17_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_17_152 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_17_160 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_17_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_17_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_17_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_17_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_17_234 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_17_258 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_17_270 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_17_278 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_30 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_305 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_17_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_364 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_379 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_17_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_403 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_17_411 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_414 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_42 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_17_426 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_17_432 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_440 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_17_461 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_17_485 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_17_491 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_17_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_17_534 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_17_54 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_17_543 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_17_555 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_17_559 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_573 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_17_581 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_6 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_604 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_17_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_17_93 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_101 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_180_137 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_180_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_149 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_157 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_161 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_173 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_180_185 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_180_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_180_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_210 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_222 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_180_234 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_180_243 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_180_26 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_180_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_321 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_333 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_180_345 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_353 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_180_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_180_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_41 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_180_454 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_462 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_180_519 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_180_596 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_181_11 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_181_311 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_319 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_181_331 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_181_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_337 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_349 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_361 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_181_373 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_181_389 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_181_393 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_181_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_181_414 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_426 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_181_438 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_181_446 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_181_469 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_181_48 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_181_481 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_181_493 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_181_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_181_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_181_511 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_184_29 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_184_66 (.VGND(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_186_453 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_186_461 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_497 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_186_509 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_518 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_186_530 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_545 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_186_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_186_579 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_186_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_186_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_186_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_186_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_187_167 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_187_24 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_260 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_187_346 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_187_367 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_187_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_187_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_414 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_42 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_469 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_481 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_187_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_517 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_187_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_187_54 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_187_561 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_188_53 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_188_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_188_553 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_188_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_188_569 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_188_581 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_188_587 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_188_589 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_188_604 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_188_616 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_188_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_188_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_188_73 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_188_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_188_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_188_94 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_8 FILLER_190_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_190_287 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_190_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_190_297 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_190_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_190_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_190_317 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_190_354 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_190_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_190_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_190_41 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_190_413 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_190_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_190_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_190_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_190_482 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_190_49 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_190_577 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_190_584 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_190_61 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_190_73 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_190_94 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_191_109 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_191_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_130 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_191_134 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_142 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_163 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_167 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_187 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_222 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_191_256 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_332 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_350 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_367 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_191_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_393 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_400 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_447 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_508 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_191_549 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_191_558 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_565 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_191_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_191_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_191_600 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_606 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_191_63 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_7 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_191_78 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_191_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_111 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_123 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_192_135 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_139 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_192_153 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_166 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_192_178 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_192_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_192_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_205 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_192_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_192_235 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_192_246 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_265 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_277 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_192_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_329 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_192_344 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_192_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_192_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_403 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_192_41 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_415 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_192_512 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_541 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_544 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_192_568 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_192_579 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_587 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_589 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_60 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_192_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_192_607 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_192_612 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_72 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_192_85 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_192_97 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_193_101 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_193_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_193_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_193_110 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_21_113 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_142 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_154 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_21_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_21_193 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_21_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_261 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_21_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_21_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_21_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_21_298 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_21_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_21_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_21_325 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_21_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_21_361 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_21_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_21_400 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_406 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_21_425 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_21_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_21_485 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_21_499 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_503 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_505 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_21_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_540 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_21_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_21_552 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_585 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_21_597 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_21_610 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_21_617 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_21_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_21_96 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_22_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_22_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_22_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_22_168 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_173 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_22_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_22_217 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_22_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_22_246 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_265 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_277 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_22_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_22_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_22_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_327 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_348 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_356 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_376 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_22_384 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_412 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_22_445 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_467 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_22_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_481 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_522 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_22_542 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_546 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_567 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_579 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_605 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_22_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_22_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_22_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_22_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_22_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_23_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_23_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_158 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_23_174 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_23_182 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_23_205 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_213 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_23_218 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_23_247 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_23_255 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_23_274 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_23_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_23_300 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_6 FILLER_23_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_23_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_24_213 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_24_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_24_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_24_304 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_24_368 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_25_349 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_25_35 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_361 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_25_373 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_25_385 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_25_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_25_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_410 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_25_422 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_25_426 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_434 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_25_446 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_25_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_25_473 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_27_6 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_27_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_27_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_27_81 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_27_89 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_27_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_28_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_28_127 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_31_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_31_52 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_31_541 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_31_553 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_31_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_31_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_31_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_31_585 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_31_597 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_31_609 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_8 FILLER_31_617 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_34_188 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_38_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_38_586 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_38_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_38_599 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_38_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_38_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_38_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_38_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_39_106 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_143 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_155 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_177 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_194 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_202 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_212 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_234 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_39_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_257 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_267 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_39_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_300 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_312 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_328 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_39_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_343 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_35 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_351 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_374 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_39_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_39_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_406 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_39_412 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_429 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_39_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_457 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_480 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_39_499 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_503 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_39_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_39_585 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_590 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_39_598 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_39_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_39_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_39_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_10 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_107 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_126 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_200 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_212 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_299 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_322 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_330 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_345 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_350 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_357 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_363 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_373 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_400 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_407 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_415 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_423 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_431 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_440 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_456 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_3_464 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_3_529 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_554 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_593 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_3_597 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_603 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_606 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_3_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_3_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_3_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_3_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_40_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_40_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_40_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_40_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_40_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_40_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_40_174 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_40_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_40_186 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_40_192 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_40_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_40_215 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_40_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_40_236 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_40_246 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_40_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_40_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_40_268 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_40_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_42_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_42_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_42_513 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_42_533 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_545 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_42_581 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_42_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_42_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_6 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_612 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_42_624 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_42_72 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_42_76 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_42_80 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_42_97 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_43_105 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_43_111 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_113 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_43_137 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_15 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_150 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_43_162 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_43_181 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_188 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_200 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_43_212 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_43_221 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_43_232 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_43_236 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_43_255 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_27 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_43_272 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_43_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_43_301 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_43_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_43_332 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_337 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_349 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_361 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_373 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_43_385 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_42 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_43_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_43_470 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_43_482 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_43_490 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_503 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_43_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_541 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_43_553 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_43_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_577 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_43_605 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_43_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_43_613 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_43_617 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_43_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_43_73 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_43_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_106 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_118 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_12 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_44_130 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_44_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_44_153 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_16 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_177 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_44_193 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_44_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_44_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_316 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_44_331 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_44_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_356 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_372 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_44_384 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_388 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_44_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_44_432 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_438 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_446 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_44_454 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_44_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_44_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_485 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_494 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_506 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_518 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_44_530 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_44_581 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_44_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_59 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_44_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_44_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_44_617 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_44_71 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_44_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_44_94 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_45_106 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_131 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_139 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_151 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_45_163 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_167 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_181 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_45_218 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_249 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_261 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_45_273 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_279 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_45_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_289 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_45_299 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_30 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_312 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_45_324 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_335 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_391 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_45_402 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_406 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_45_415 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_42 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_423 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_446 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_45_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_461 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_45_473 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_45_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_536 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_54 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_45_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_567 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_45_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_575 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_45_593 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_45_624 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_45_69 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_45_92 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_46_103 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_46_114 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_46_12 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_46_129 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_168 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_46_180 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_46_200 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_233 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_46_24 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_46_245 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_46_251 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_46_260 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_273 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_285 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_46_297 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_46_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_46_305 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_46_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_46_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_46_316 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_46_326 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__fill_2 FILLER_46_362 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_46_411 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_46_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_428 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_46_452 (.VGND(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_46_470 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_46_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_46_489 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_46_579 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_46_587 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_46_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_46_601 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_46_74 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_46_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_46_85 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_46_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_47_101 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_47_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_47_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_47_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_47_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_47_129 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_47_140 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_47_164 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_47_176 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_47_188 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_47_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_47_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_47_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_47_232 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_47_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_47_241 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_47_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_47_266 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_47_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_47_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPB(VPWR),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_49_373 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_425 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_49_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_49_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_49_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_49_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_471 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_49_483 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_49_491 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_49_500 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_49_529 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_540 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_49_552 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_49_585 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_49_593 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_49_6 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_49_614 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_49_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_49_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_49_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_49_89 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_114 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_128 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_178 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_186 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_194 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_233 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_248 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_256 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_4_268 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_292 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_304 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_358 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_37 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_389 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_401 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_497 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_507 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_527 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_4_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_574 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_586 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_4_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_4_597 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_603 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_4_623 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_4_79 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_4_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_4_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_50_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_50_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_177 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_50_189 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_50_203 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_50_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_50_250 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_261 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_50_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_50_296 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_50_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_50_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_345 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_50_357 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_363 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_389 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_50_401 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_50_412 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_429 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_441 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_453 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_50_46 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_50_465 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_50_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_50_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_50_485 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_50_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_50_522 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_50_530 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_6 FILLER_53_162 (.VGND(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_55_390 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_55_40 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_55_400 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_57_54 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_61_167 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_61_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_61_223 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_61_225 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_61_237 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_61_249 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_61_261 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_63_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_63_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_3 FILLER_63_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_63_568 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_63_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_63_576 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_63_588 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_63_6 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_63_600 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_63_612 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_63_617 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_63_62 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_63_74 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_63_82 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_63_90 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_63_98 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_107 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_12 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_64_131 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_139 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_141 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_177 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_64_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_238 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_64_246 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_262 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_282 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_294 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_64_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_64_303 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_64_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_321 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_333 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_64_34 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_64_343 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_64_360 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_64_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_382 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_64_392 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_40 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_64_414 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_64_501 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_64_513 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_531 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_548 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_64_556 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_564 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_64_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_64_62 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_64_73 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_64_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_64_98 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_65_101 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_65_514 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_65_518 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_65_526 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_65_532 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_65_561 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_65_566 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_65_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_65_578 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_65_586 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_65_594 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_65_598 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_65_606 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_65_614 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_65_617 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_65_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_65_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_66_112 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_8 FILLER_66_130 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_66_161 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_66_419 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_66_421 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_66_451 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_66_47 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_66_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_67_100 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_68_135 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_68_18 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_68_182 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_68_194 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_68_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_68_203 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_68_224 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_68_230 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_68_250 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_68_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_68_271 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__fill_2 FILLER_68_477 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_68_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_68_565 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_68_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_68_6 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_68_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_68_622 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_68_77 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_68_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_68_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_68_93 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_69_105 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_69_11 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_69_111 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_69_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_69_125 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_69_166 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_69_169 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_69_177 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_69_186 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_69_190 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_69_214 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_69_23 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_69_232 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_69_276 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_69_288 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_69_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_69_300 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_69_311 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_69_319 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_6_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_6_350 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_6_358 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_6_363 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_6_40 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_6_409 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_6_417 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_6_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_6_441 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_451 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_463 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_6_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_6_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPB(VPWR),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_71_546 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_71_552 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_71_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_71_57 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_71_572 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_71_584 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_71_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_71_623 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_71_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_71_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_71_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_71_95 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_126 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_72_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_183 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_20 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_72_233 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_72_245 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_251 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_265 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_277 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_297 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_72_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_72_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_330 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_342 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_354 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_389 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_401 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_72_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_72_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_434 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_463 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_509 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_72_516 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_72_528 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_72_583 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_587 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_72_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_72_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_72_85 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_72_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_147 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_73_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_73_193 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_73_212 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_73_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_73_234 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_73_243 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_73_263 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_73_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_73_275 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_73_281 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_73_292 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_304 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_73_312 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_73_332 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_73_346 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_352 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_374 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_73_38 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_73_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_73_403 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_73_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_440 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_73_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_453 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_471 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_73_483 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_73_49 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_73_497 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_549 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_73_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_565 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_73_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_73_577 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_604 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_73_620 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_73_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_73_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_73_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_73_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_74_104 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_74_115 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_74_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_74_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_74_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_74_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_74_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_74_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_74_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_74_173 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_74_185 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_74_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_74_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_74_248 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_74_253 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_74_26 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_74_282 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_74_291 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_74_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_74_326 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_330 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_74_340 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_375 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_387 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_74_402 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_74_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_74_445 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_464 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_500 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_512 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_74_524 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_533 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_545 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_557 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_569 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_589 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_60 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_74_601 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_64 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_74_76 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_74_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_74_92 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_102 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_75_110 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_75_113 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_165 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_183 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_191 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_203 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_215 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_75_232 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_24 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_245 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_257 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_276 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_281 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_293 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_297 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_75_3 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_335 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_347 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_36 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_366 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_75_376 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_75_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_402 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_427 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_439 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_75_449 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_464 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_486 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_75_499 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_503 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_514 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_52 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_526 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_538 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_75_550 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_75_558 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_75_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_57 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_573 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_75_611 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_75_615 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_75_90 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__fill_2 FILLER_76_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__decap_8 FILLER_76_17 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_175 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_76_218 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_76_230 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_76_25 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_76_253 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_265 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_76_303 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_76_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_76_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_325 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_76_349 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_76_358 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_375 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_387 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_76_399 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_405 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_76_414 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_76_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_438 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_76_455 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_76_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_76_524 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_76_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_76_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_76_557 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_76_565 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_76_574 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_76_582 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_76_587 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_76_613 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_76_79 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_76_83 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_76_85 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_77_417 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_77_482 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_77_502 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_78_477 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_78_481 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_78_494 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_78_512 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_78_524 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_78_536 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_78_542 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_78_550 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_78_561 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_78_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_78_585 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_78_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_78_59 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_78_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_78_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_78_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_78_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_78_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_79_106 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_79_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_124 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_136 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_79_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_154 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_79_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_79_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_79_193 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_79_212 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_79_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_79_240 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_79_248 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_79_260 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_268 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_79_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_79_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_79_296 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_308 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_79_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_341 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_79_353 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_371 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_79_383 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_79_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_420 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_432 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_44 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_79_444 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_482 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_79_494 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_500 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_79_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_514 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_526 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_538 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_79_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_79_580 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_584 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_79_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_79_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_79_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_79_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_110 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_150 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_162 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_193 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_201 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_210 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_222 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_246 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_258 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_270 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_278 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_331 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_349 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_355 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_385 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_391 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_425 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_429 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_439 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_457 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_465 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_7_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_529 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_553 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_7_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_7_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_576 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_612 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_7_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_7_62 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_7_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_7_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_7_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_145 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_80_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_157 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_80_179 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_191 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_80_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_229 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_241 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_80_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_80_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_80_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_80_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_80_29 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_80_299 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_80_307 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_80_309 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_80_313 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_80_321 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_80_334 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_80_353 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_80_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_80_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_80_377 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_80_404 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_80_526 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_80_548 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_80_619 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_80_67 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_80_81 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_81_129 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_81_166 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_81_446 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_81_45 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_81_490 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_81_517 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_81_529 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_81_53 (.VGND(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_82_245 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_82_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_82_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_320 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_332 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_356 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_374 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_390 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_407 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_82_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_415 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_82_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_82_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_452 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_464 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_484 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_496 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_508 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_82_520 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_528 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_82_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_545 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_82_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_82_556 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_82_564 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_573 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_82_585 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_82_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_613 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_82_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_82_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_82_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_82_79 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_82_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_82_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_82_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_83_100 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_83_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_83_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_148 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_83_160 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_8 FILLER_83_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_177 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_83_192 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_199 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_223 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_83_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_23 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_237 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_249 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_83_261 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_265 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_83_271 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_83_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_83_325 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_344 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_83_35 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_356 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_368 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_83_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_3 FILLER_83_389 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_83_398 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_83_415 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_434 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_446 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_83_449 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_460 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_83_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_83_487 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_493 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_83_503 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_83_505 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_509 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_83_517 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_521 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_83_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_83_561 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_83_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_591 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_603 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_83_615 (.VGND(VGND),
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+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_83_620 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_83_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_83_63 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_83_69 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_83_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_83_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_104 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_116 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_128 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_165 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_177 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_6 FILLER_84_189 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_84_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_84_20 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_84_209 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_84_217 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_222 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_234 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_246 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_84_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_265 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_277 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_84_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_298 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_84_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_84_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_350 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_358 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_383 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_409 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_84_417 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_448 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_46 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_465 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_84_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_84_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_84_530 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_84_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_570 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_582 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_84_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_84_74 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_80 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_84_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_84_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_85_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_179 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_191 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_85_199 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_85_206 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_216 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_233 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_244 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_256 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_268 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_319 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_331 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_364 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_376 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_388 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_405 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_85_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_411 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_85_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_457 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_469 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_481 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_493 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_85_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_512 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_524 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_536 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_85_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_578 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_590 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_85_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_66 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_85_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_85_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_85_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_85_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_108 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_124 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_157 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_178 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_86_189 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_86_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_204 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_208 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_86_234 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_240 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_250 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_262 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_86_270 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_280 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_86_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_292 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_86_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_323 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_327 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_344 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_356 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_373 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_86_382 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_404 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_416 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_445 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_453 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_464 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_510 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_522 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_86_530 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_541 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_86_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_567 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_572 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_584 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_597 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_86_609 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_621 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_86_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_86_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_86_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_87_110 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_87_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_128 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_140 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_152 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_164 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_87_177 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_87_200 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_210 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_87_222 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_241 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_87_251 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_87_263 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_275 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_303 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_315 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_323 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_342 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_346 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_356 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_12 FILLER_87_36 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_87_364 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_375 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_4 FILLER_87_388 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_393 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_3 FILLER_87_405 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_415 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_87_427 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_439 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_447 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_87_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_467 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_484 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_496 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_87_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_547 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_87_569 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_578 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_590 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_87_598 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_87_610 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_87_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_87_86 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_87_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_110 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_122 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ sky130_fd_sc_hd__decap_6 FILLER_88_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_88_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_150 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_162 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_188 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_19 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_88_217 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_88_223 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_236 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_88_248 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_88_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_88_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_318 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_330 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_342 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_88_350 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_88_360 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_372 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_384 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_396 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_437 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_88_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_459 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_88_467 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_486 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_88_498 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_88_506 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_88_528 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_88_540 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_546 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_624 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_88_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_88_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_88_89 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_88_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_89_108 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_89_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_174 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_186 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_198 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_21 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_210 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_222 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_225 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_261 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_89_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_313 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_335 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_374 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_386 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_89_400 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_417 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_446 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_449 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_461 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_485 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_491 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_50 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_89_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_89_505 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_509 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_89_517 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_89_543 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_547 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_89_555 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_559 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_89_561 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_570 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_582 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_89_607 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_89_615 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_89_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_89_623 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_89_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_89_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_133 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_172 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_185 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_8_193 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_233 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_238 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_8_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_265 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_277 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_8_321 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_325 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_8_354 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_8_362 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_8_395 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_8_417 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_445 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_457 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_469 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_475 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_501 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_513 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_525 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_8_531 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_8_542 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_609 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_8_621 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_8_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_90_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_122 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_90_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_90_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_90_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_191 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_195 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_197 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_209 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_221 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_23 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_233 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_237 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_257 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_267 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_291 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_303 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_318 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_330 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_342 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_346 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_365 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_377 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_90_389 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_401 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_90_413 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_419 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_421 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_433 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_455 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_90_465 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_90_473 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_477 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_489 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_497 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_512 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_90_524 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_533 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_90_545 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_552 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_564 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_576 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_589 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_601 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_90_613 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_90_619 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_63 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_90_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_90_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_90_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_91_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_91_110 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_91_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_91_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_91_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_91_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ sky130_fd_sc_hd__fill_1 FILLER_93_308 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_93_318 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_93_337 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_93_615 (.VGND(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_95_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_95_393 (.VGND(VGND),
+ .VNB(VGND),
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+ sky130_fd_sc_hd__fill_2 FILLER_95_405 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_95_416 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_95_43 (.VGND(VGND),
+ .VNB(VGND),
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+ .VNB(VGND),
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+ sky130_fd_sc_hd__decap_12 FILLER_97_586 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_314 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_333 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_9_337 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_364 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_376 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_380 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_388 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_393 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_9_402 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_410 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_431 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_443 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_447 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_479 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_9_491 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_9_501 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_505 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_4 FILLER_9_51 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_517 (.VGND(VGND),
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_9_542 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_55 (.VGND(VGND),
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+ sky130_fd_sc_hd__fill_1 FILLER_9_559 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_8 FILLER_9_57 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_580 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_9_592 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_617 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_9_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_9_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_9_91 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_100 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_101 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_102 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_103 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_104 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_105 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_106 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_107 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_108 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_109 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_110 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_111 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_112 (.VGND(VGND),
+ .VNB(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_113 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_114 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_115 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_116 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_117 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_118 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_119 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_120 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_121 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_122 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_123 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_124 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_125 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_126 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_127 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_128 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_129 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_130 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_131 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_132 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_133 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_134 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_135 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_136 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_137 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_138 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_139 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_140 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_141 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_142 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_143 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_144 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_145 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_146 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_147 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_148 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_149 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_150 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_151 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_152 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_153 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_154 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_155 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_156 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_157 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_158 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_159 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_160 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_161 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_162 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_163 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_164 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_165 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_166 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_167 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_168 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_169 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_170 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_171 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_172 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_173 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_174 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_175 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_176 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_177 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_178 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_179 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_180 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_181 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_182 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_183 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_184 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_185 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_186 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_187 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_188 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_189 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_190 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_191 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_192 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_193 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_194 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_195 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_196 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_197 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_198 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_199 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_200 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_201 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_211 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_213 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_214 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_215 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_218 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_219 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_220 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_221 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_222 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_223 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_224 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_225 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_226 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_227 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_228 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_229 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_230 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_231 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_232 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_233 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_234 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_235 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_236 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_237 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_238 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_239 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_240 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_241 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_242 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_243 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_244 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_245 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_246 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_247 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_248 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_249 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_250 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_251 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_252 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_253 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_254 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_255 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_256 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_257 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_258 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_259 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_260 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_261 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_262 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_263 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_264 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_265 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_266 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_267 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_268 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_269 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_270 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_271 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_272 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_273 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_274 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_275 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_276 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_277 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_278 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_279 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_280 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_281 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_282 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_283 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_284 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_285 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_286 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_287 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_288 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_289 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_290 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_291 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_292 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_293 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_294 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_295 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_296 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_297 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_298 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_299 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_300 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_301 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_302 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_303 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_304 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_305 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_306 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_307 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_308 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_309 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_310 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_320 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_338 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_339 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_340 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_341 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_342 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_343 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_344 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_345 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_346 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_347 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_348 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_349 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_350 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_351 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_352 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_353 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_354 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_356 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_358 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_359 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_360 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_361 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_363 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_364 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_365 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_366 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_367 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_368 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_369 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_370 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_371 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_372 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_373 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_374 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_375 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_377 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_378 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_379 (.VGND(VGND),
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+ sky130_fd_sc_hd__decap_3 PHY_380 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_384 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_385 (.VGND(VGND),
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_387 (.VGND(VGND),
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_46 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_47 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_48 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_49 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_50 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_51 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_52 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_54 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_58 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_59 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_60 (.VGND(VGND),
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+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_62 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
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+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_64 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_65 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_66 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_67 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_68 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_69 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_70 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_71 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_72 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_73 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_74 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_75 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_76 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_77 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_78 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_79 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_80 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_81 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_82 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_83 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_84 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_85 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_86 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_87 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_88 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_89 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_90 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_91 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_92 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_93 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_94 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_95 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_96 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_97 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_98 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_99 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1000 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1001 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1002 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1003 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1004 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1005 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1006 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1007 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1008 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1009 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1010 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1011 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1012 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1013 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1014 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1015 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1016 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1017 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1018 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1019 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1020 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1021 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1022 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1023 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1024 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1025 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1026 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1027 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1028 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1029 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1030 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1031 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1032 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1033 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1034 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1035 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1036 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1037 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1038 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1039 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1040 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1041 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1042 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1043 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1044 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1045 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1046 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1047 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1048 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1049 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1050 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1051 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1052 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1053 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1054 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1055 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1056 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1057 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1058 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1059 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1060 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1061 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1062 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1063 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1064 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1065 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1066 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1067 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1068 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1069 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1070 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1071 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1072 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1073 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1074 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1075 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1076 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1077 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1078 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1079 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1080 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1081 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1082 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1083 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1084 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1085 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1086 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1087 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1088 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1089 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1090 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1091 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1092 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1093 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1094 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1095 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1096 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1097 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1098 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1099 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1100 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1101 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1102 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1103 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1104 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1105 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1106 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1107 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1108 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1109 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1110 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1111 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1112 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1113 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1114 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1115 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1116 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1117 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1118 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1119 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1120 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1121 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1122 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1123 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1124 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1125 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1126 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1127 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1128 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1129 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1130 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1131 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1132 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1133 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1134 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1135 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1136 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1137 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1138 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1139 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1140 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1141 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1142 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1143 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1144 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1145 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1146 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1147 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1148 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1149 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1150 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1151 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1152 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1153 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1154 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1155 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1156 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1157 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1158 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1159 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1160 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1161 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1162 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1163 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1164 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1165 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1166 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1167 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1168 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1169 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1170 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1171 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1172 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1173 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1174 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1175 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1176 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1177 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1178 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1179 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1180 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1181 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1182 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1183 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1184 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1185 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1186 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1187 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1188 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1189 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1190 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1191 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1192 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1193 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1194 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1195 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1196 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1197 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1198 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1199 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1200 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1201 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1202 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1203 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1204 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1205 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1206 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1207 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1208 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1209 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1210 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1211 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1212 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1213 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1214 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1215 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1216 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1217 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1218 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1219 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1220 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1221 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1222 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1223 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1224 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1225 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1226 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1227 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1228 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1229 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1230 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1231 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1232 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1233 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1234 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1235 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1236 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1237 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1238 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1239 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1240 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1241 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1242 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1243 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1244 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1245 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1246 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1247 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1248 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1249 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1250 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1251 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1252 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1253 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1254 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1255 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1256 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1257 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1258 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1259 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1260 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1261 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1262 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1263 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1264 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1265 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1266 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1267 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1268 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1269 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1270 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1271 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1272 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1273 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1274 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1275 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1276 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1277 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1278 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1279 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1280 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1281 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1282 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1283 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1284 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1285 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1286 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1287 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1288 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1289 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1290 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1291 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1292 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1293 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1294 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1295 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1296 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1297 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1298 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1299 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1300 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1301 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1302 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1303 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1304 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1305 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1306 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1307 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1308 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1309 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1310 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1311 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1312 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1313 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1314 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1315 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1316 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1317 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1318 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1319 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1320 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1321 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1322 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1323 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1324 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1325 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1326 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1327 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1328 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1329 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1330 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1331 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1332 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1333 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1334 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1335 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1336 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1337 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1338 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1339 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1340 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1341 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1342 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1343 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1344 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1345 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1346 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1347 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1348 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1349 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1350 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1351 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1352 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1353 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1354 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1355 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1356 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1357 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1358 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1359 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1360 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1361 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1362 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1363 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1364 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1365 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1366 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1367 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1368 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1369 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1370 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1371 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1372 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1373 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1374 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1375 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1376 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1377 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1378 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1379 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1380 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1381 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1382 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1383 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1384 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1385 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1386 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1387 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1388 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1389 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1390 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1391 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1392 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1393 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1394 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1395 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1396 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1397 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1398 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1399 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1400 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1401 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1402 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1403 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1404 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1405 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1406 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1407 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1408 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1409 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1410 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1411 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1412 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1413 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1414 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1415 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1416 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1417 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1418 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1419 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1420 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1421 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1422 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1423 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1424 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1425 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1426 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1427 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1428 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1429 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1430 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1431 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1432 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1433 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1434 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1435 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1436 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1437 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1438 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1439 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1440 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1441 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1442 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1443 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1444 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1445 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1446 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1447 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1448 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1449 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1450 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1451 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1452 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1453 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1454 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1455 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1456 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1457 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1458 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1459 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1460 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1461 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1462 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1463 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1464 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1465 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1466 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1467 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1468 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1469 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1470 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1471 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1472 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1473 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1474 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1475 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1476 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1477 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1478 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1479 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1480 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1481 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1482 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1483 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1484 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1485 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1486 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1487 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1488 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1489 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1490 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1491 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1492 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1493 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1494 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1495 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1496 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1497 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1498 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1499 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1500 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1501 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1502 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1503 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1504 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1505 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1506 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1507 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1508 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1509 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1510 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1511 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1512 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1513 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1514 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1515 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1516 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1517 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1518 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1519 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1520 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1521 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1522 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1523 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1524 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1525 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1526 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1527 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1528 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1529 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1530 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1531 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1532 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1533 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1534 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1535 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1536 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1537 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1538 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1539 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1540 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1541 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1542 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1543 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1544 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1545 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1546 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1547 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1548 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1549 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1550 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1551 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1552 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1553 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1554 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1555 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1556 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1557 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1558 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1559 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1560 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1561 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1562 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1563 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1564 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1565 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1566 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1567 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1568 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1569 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1570 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1571 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1572 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1573 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1574 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1575 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1576 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1577 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1578 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1579 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1580 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1581 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1582 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1583 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1584 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1585 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1586 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1587 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1588 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1589 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1590 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1591 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1592 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1593 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1594 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1595 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1596 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1597 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1598 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1599 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1600 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1601 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1602 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1603 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1604 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1605 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1606 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1607 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1608 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1609 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1610 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1611 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1612 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1613 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1614 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1615 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1616 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1617 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1618 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1619 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1620 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1621 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1622 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1623 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1624 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1625 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1626 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1627 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1628 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1629 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1630 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1631 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1632 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1633 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1634 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1635 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1636 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1637 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1638 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1639 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1640 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1641 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1642 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1643 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1644 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1645 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1646 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1647 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1648 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1649 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1650 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1651 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1652 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1653 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1654 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1655 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1656 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1657 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1658 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1659 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1660 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1661 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1662 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1663 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1664 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1665 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1666 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1667 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1668 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1669 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1670 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1671 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1672 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1673 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1674 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1675 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1676 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1677 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1678 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1679 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1680 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1681 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1682 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1683 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1684 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1685 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1686 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1687 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1688 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1689 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1690 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1691 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1692 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1693 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1694 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1695 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1696 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1697 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1698 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1699 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1700 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1701 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1702 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1703 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1704 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1705 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1706 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1707 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1708 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1709 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1710 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1711 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1712 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1713 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1714 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1715 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1716 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1717 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1718 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1719 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1720 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1721 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1722 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1723 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1724 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1725 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1726 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1727 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1728 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1729 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1730 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1731 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1732 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1733 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1734 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1735 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1736 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1737 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1738 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1739 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1740 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1741 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1742 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1743 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1744 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1745 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1746 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1747 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1748 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1749 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1750 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1751 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1752 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1753 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1754 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1755 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1756 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1757 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1758 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1759 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1760 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1761 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1762 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1763 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1764 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1765 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1766 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1767 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1768 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1769 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1770 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1771 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1772 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1773 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1774 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1775 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1776 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1777 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1778 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1779 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1780 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1781 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1782 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1783 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1784 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1785 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1786 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1787 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1788 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1789 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1790 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1791 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1792 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1793 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1794 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1795 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1796 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1797 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1798 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1799 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1800 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1801 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1802 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1803 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1804 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1805 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1806 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1807 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1808 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1809 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1810 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1811 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1812 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1813 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1814 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1815 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1816 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1817 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1818 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1819 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1820 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1821 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1822 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1823 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1824 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1825 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1826 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1827 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1828 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1829 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1830 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1831 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1832 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1833 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1834 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1835 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1836 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1837 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1838 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1839 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1840 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1841 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1842 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1843 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1844 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1845 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1846 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1847 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1848 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1849 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1850 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1851 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1852 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1853 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1854 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1855 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1856 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1857 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1858 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1859 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1860 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1861 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1862 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1863 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1864 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1865 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1866 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1867 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1868 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1869 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1870 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1871 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1872 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1873 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1874 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1875 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1876 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1877 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1878 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1879 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1880 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1881 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1882 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1883 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1884 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1885 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1886 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1887 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1888 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1889 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1890 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1891 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1892 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1893 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1894 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1895 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1896 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1897 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1898 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1899 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1900 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1901 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1902 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1903 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1904 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1905 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1906 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1907 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1908 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1909 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1910 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1911 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1912 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1913 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1914 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1915 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1916 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1917 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1918 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1919 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1920 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1921 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1922 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1923 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1924 (.VGND(VGND),
+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
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+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2112 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2113 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2114 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2115 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2116 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2117 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2118 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2119 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2120 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2121 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2122 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2123 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2124 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2125 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2126 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2127 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2128 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2129 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2130 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2131 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2132 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2133 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2134 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2135 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2136 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2137 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2138 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2139 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2140 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2141 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2142 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2143 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2144 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2145 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2146 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2147 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2148 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2149 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2150 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2151 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2152 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2153 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2154 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2155 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2156 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2157 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2158 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2159 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2160 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2161 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2162 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2163 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2164 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2165 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2166 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2167 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2168 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2169 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2170 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2171 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2172 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2173 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2174 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2175 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2176 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2177 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2178 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2179 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2180 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2181 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2182 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2183 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2184 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2185 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2186 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2187 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2188 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2189 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2190 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2191 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2192 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2193 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2194 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2195 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2196 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2197 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2198 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2199 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2200 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2201 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2202 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2203 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2204 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2205 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2206 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2207 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2208 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2209 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2210 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2211 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2212 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2213 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2214 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2215 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2216 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2217 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2218 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2219 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2220 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2221 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2222 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2223 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2224 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2225 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2226 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2227 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2228 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2229 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2230 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2231 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2232 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2233 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2234 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2235 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2236 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2237 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2238 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2239 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2240 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2241 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2242 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2243 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2244 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2245 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2246 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2247 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2248 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2249 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2250 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2251 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2252 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2253 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2254 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2255 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2256 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2257 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2258 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2259 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2260 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2261 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2262 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2263 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2264 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2265 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2266 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2267 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2268 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2269 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2270 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2271 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2272 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2273 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2274 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2275 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2276 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2277 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2278 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2279 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2280 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2281 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2282 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2283 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2284 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2285 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2286 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2287 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2288 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2289 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2290 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2291 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2292 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2293 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2294 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2295 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2296 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2297 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2298 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2299 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2300 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2301 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2302 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2303 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2304 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2305 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2306 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2307 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2308 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2309 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2310 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2311 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2312 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2313 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2314 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2315 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2316 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2317 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2318 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2319 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2320 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2321 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2322 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2323 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2324 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2325 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2326 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2327 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2328 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2329 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2330 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2331 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2332 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2333 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2334 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2335 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2336 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2337 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2338 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2339 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2340 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2341 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2342 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2343 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2344 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2345 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2346 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2347 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2348 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2349 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2350 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2351 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2352 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2353 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2354 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2355 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2356 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2357 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2358 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2359 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2360 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2361 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2362 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2363 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2364 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2365 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2366 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2367 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2368 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2369 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2370 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2371 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2372 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2373 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2374 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2375 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2376 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2377 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2378 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2379 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2380 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2381 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2382 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2383 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2384 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2385 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2386 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2387 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2388 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2389 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2390 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2391 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2392 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2393 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2394 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2395 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2396 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2397 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2398 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2399 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2400 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2401 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2402 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2403 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2404 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2405 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2406 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2407 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2408 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2409 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2410 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2411 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2412 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2413 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2414 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2415 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2416 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2417 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2418 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2419 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2420 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2421 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2422 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2423 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2424 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2425 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2426 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2427 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2428 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2429 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2430 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2431 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2432 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2433 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2434 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2435 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2436 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2437 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2438 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2439 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2440 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2441 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2442 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2443 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2444 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2445 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2446 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2447 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2448 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2449 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2450 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2451 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2452 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2453 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2454 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2455 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2456 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2457 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2458 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2459 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2460 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2461 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2462 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2463 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2464 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2465 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2466 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2467 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2468 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2469 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2470 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2471 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2472 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2473 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2474 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2475 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2476 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2477 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2478 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2479 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2480 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2481 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2482 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2483 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2484 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2485 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2486 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2487 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2488 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2489 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2490 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2491 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2492 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2493 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2494 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2495 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2496 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2497 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2498 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2499 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2500 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2501 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2502 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2503 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2504 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2505 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2506 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2507 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2508 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2509 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2510 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2511 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2512 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2513 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2514 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2515 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2516 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2517 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2518 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2519 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2520 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2521 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2522 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2523 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2524 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2525 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2526 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2527 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2528 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2529 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2530 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2531 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2532 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2533 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2534 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2535 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2536 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2537 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2538 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2539 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2540 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2541 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2542 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2543 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_388 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_389 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_390 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_391 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_392 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_393 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_394 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_395 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_396 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_397 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_398 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_399 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_400 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_401 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_402 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_403 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_404 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_405 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_406 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_407 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_408 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_409 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_410 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_411 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_412 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_413 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_414 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_415 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_416 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_417 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_418 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_419 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_420 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_421 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_422 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_423 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_424 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_425 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_426 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_427 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_428 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_429 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_430 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_431 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_432 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_433 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_434 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_435 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_436 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_437 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_438 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_439 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_440 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_441 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_442 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_443 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_444 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_445 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_446 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_447 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_448 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_449 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_450 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_451 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_452 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_453 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_454 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_455 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_456 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_457 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_458 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_459 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_460 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_461 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_462 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_463 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_464 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_465 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_466 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_467 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_468 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_469 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_470 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_471 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_472 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_473 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_474 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_475 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_476 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_477 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_478 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_479 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_480 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_481 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_482 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_483 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_484 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_485 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_486 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_487 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_488 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_489 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_490 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_491 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_492 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_493 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_494 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_495 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_496 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_497 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_498 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_499 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_500 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_501 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_502 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_503 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_504 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_505 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_506 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_507 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_508 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_509 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_510 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_511 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_512 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_513 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_514 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_515 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_516 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_517 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_518 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_519 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_520 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_521 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_522 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_523 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_524 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_525 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_526 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_527 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_528 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_529 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_530 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_531 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_532 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_533 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_534 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_535 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_536 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_537 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_538 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_539 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_540 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_541 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_542 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_543 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_544 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_545 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_546 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_547 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_548 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_549 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_550 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_551 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_552 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_553 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_554 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_555 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_556 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_557 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_558 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_559 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_560 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_561 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_562 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_563 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_564 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_565 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_566 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_567 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_568 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_569 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_570 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_571 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_572 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_573 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_574 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_575 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_576 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_577 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_578 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_579 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_580 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_581 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_582 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_583 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_584 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_585 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_586 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_587 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_588 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_589 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_590 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_591 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_592 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_593 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_594 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_595 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_596 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_597 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_598 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_599 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_600 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_601 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_602 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_603 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_604 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_605 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_606 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_607 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_608 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_609 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_610 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_611 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_612 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_613 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_614 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_615 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_616 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_617 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_618 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_619 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_620 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_621 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_622 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_623 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_624 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_625 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_626 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_627 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_628 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_629 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_630 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_631 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_632 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_633 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_634 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_635 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_636 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_637 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_638 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_639 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_640 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_641 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_642 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_643 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_644 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_645 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_646 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_647 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_648 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_649 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_650 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_651 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_652 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_653 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_654 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_655 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_656 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_657 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_658 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_659 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_660 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_661 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_662 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_663 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_664 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_665 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_666 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_667 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_668 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_669 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_670 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_671 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_672 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_673 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_674 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_675 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_676 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_677 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_678 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_679 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_680 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_681 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_682 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_683 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_684 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_685 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_686 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_687 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_688 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_689 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_690 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_691 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_692 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_693 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_694 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_695 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_696 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_697 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_698 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_699 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_700 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_701 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_702 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_703 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_704 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_705 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_706 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_707 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_708 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_709 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_710 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_711 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_712 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_713 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_714 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_715 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_716 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_717 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_718 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_719 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_720 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_721 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_722 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_723 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_724 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_725 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_726 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_727 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_728 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_729 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_730 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_731 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_732 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_733 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_734 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_735 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_736 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_737 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_738 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_739 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_740 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_741 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_742 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_743 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_744 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_745 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_746 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_747 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_748 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_749 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_750 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_751 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_752 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_753 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_754 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_755 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_756 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_757 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_758 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_759 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_760 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_761 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_762 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_763 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_764 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_765 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_766 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_767 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_768 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_769 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_770 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_771 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_772 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_773 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_774 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_775 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_776 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_777 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_778 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_779 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_780 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_781 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_782 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_783 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_784 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_785 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_786 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_787 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_788 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_789 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_790 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_791 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_792 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_793 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_794 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_795 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_796 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_797 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_798 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_799 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_800 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_801 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_802 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_803 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_804 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_805 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_806 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_807 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_808 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_809 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_810 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_811 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_812 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_813 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_814 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_815 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_816 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_817 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_818 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_819 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_820 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_821 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_822 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_823 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_824 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_825 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_826 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_827 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_828 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_829 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_830 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_831 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_832 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_833 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_834 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_835 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_836 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_837 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_838 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_839 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_840 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_841 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_842 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_843 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_844 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_845 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_846 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_847 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_848 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_849 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_850 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_851 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_852 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_853 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_854 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_855 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_856 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_857 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_858 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_859 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_860 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_861 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_862 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_863 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_864 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_865 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_866 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_867 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_868 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_869 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_870 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_871 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_872 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_873 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_874 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_875 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_876 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_877 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_878 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_879 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_880 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_881 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_882 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_883 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_884 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_885 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_886 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_887 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_888 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_889 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_890 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_891 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_892 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_893 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_894 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_895 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_896 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_897 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_898 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_899 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_900 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_901 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_902 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_903 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_904 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_905 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_906 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_907 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_908 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_909 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_910 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_911 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_912 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_913 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_914 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_915 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_916 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_917 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_918 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_919 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_920 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_921 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_922 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_923 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_924 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_925 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_926 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_927 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_928 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_929 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_930 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_931 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_932 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_933 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_934 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_935 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_936 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_937 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_938 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_939 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_940 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_941 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_942 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_943 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_944 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_945 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_946 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_947 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_948 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_949 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_950 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_951 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_952 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_953 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_954 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_955 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_956 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_957 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_958 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_959 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_960 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_961 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_962 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_963 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_964 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_965 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_966 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_967 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_968 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_969 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_970 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_971 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_972 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_973 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_974 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_975 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_976 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_977 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_978 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_979 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_980 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_981 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_982 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_983 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_984 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_985 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_986 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_987 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_988 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_989 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_990 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_991 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_992 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_993 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_994 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_995 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_996 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_997 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_998 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_999 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4443_ (.A0(\mgmt_gpio_data[32] ),
+ .A1(net80),
+ .S(net79),
+ .X(\mgmt_gpio_out_pre[32] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4444_ (.A0(\mgmt_gpio_data[33] ),
+ .A1(net78),
+ .S(net79),
+ .X(\mgmt_gpio_out_pre[33] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4445_ (.A0(\mgmt_gpio_data[10] ),
+ .A1(net58),
+ .S(\hkspi.pass_thru_user ),
+ .X(\mgmt_gpio_out_pre[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4446_ (.A0(\mgmt_gpio_data[9] ),
+ .A1(clknet_2_3_0_mgmt_gpio_in[4]),
+ .S(\hkspi.pass_thru_user ),
+ .X(\mgmt_gpio_out_pre[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4447_ (.A0(\mgmt_gpio_data[8] ),
+ .A1(net67),
+ .S(\hkspi.pass_thru_user_delay ),
+ .X(\mgmt_gpio_out_pre[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4448_ (.A0(\mgmt_gpio_data[6] ),
+ .A1(net77),
+ .S(net126),
+ .X(\mgmt_gpio_out_pre[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4449_ (.A0(\mgmt_gpio_data[15] ),
+ .A1(user_clock),
+ .S(clk2_output_dest),
+ .X(\mgmt_gpio_out_pre[15] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4450_ (.A0(\mgmt_gpio_data[14] ),
+ .A1(clknet_3_6_0_wb_clk_i),
+ .S(clk1_output_dest),
+ .X(\mgmt_gpio_out_pre[14] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4451_ (.A0(\mgmt_gpio_data[13] ),
+ .A1(net125),
+ .S(trap_output_dest),
+ .X(\mgmt_gpio_out_pre[13] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4452_ (.A(_0063_),
+ .Y(_1021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4453_ (.A(_1021_),
+ .X(_1022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4454_ (.A(_1022_),
+ .X(_1023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4455_ (.A(_0073_),
+ .Y(_1024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4456_ (.A(wbbd_busy),
+ .Y(_1025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _4457_ (.A1(_1025_),
+ .A2(_0078_),
+ .B1(_0077_),
+ .X(_1026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4458_ (.A(_1024_),
+ .B(_0075_),
+ .C(_1026_),
+ .X(_1027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_8 _4459_ (.A(_1027_),
+ .X(_1028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4460_ (.A(_0067_),
+ .Y(_1029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4461_ (.A(_0065_),
+ .Y(_1030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4462_ (.A(_1029_),
+ .B(_1030_),
+ .C(_0071_),
+ .D(_0069_),
+ .X(_1031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4463_ (.A(_1028_),
+ .B(_1031_),
+ .X(_1032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4464_ (.A(_1023_),
+ .B(_1032_),
+ .X(_1033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4465_ (.A(_1033_),
+ .X(_1034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4466_ (.A(_1034_),
+ .Y(_1035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4467_ (.A1(serial_bb_data_2),
+ .A2(_1034_),
+ .B1(\cdata[6] ),
+ .B2(_1035_),
+ .X(_1019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4468_ (.A(_0075_),
+ .Y(_1036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _4469_ (.A1(_1025_),
+ .A2(_0078_),
+ .B1_N(_0077_),
+ .X(_1037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4470_ (.A(_0073_),
+ .B(_1036_),
+ .C(_1037_),
+ .X(_1038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4471_ (.A(_1038_),
+ .X(_1039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4472_ (.A(_0071_),
+ .Y(_1040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4473_ (.A(_0069_),
+ .Y(_1041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4474_ (.A(_1029_),
+ .B(_1030_),
+ .C(_1040_),
+ .D(_1041_),
+ .X(_1042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4475_ (.A(_1022_),
+ .X(_1043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4476_ (.A(_1039_),
+ .B(_1042_),
+ .C(_1043_),
+ .X(_1044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4477_ (.A0(\cdata[0] ),
+ .A1(hkspi_disable),
+ .S(_1044_),
+ .X(_1045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4478_ (.A(_1045_),
+ .X(_1018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4479_ (.A(_1029_),
+ .B(_1030_),
+ .C(_1040_),
+ .D(_0069_),
+ .X(_1046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4480_ (.A(_1028_),
+ .B(_1046_),
+ .X(_1047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4481_ (.A(_1043_),
+ .B(_1047_),
+ .X(_1048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4482_ (.A0(net364),
+ .A1(clk1_output_dest),
+ .S(_1048_),
+ .X(_1049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4483_ (.A(_1049_),
+ .X(_1017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4484_ (.A1(serial_bb_enable),
+ .A2(_1034_),
+ .B1(net366),
+ .B2(_1035_),
+ .X(_1016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4485_ (.A0(\cdata[1] ),
+ .A1(clk2_output_dest),
+ .S(_1048_),
+ .X(_1050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4486_ (.A(_1050_),
+ .X(_1015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4487_ (.A(_1024_),
+ .B(_0075_),
+ .C(_1037_),
+ .X(_1051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _4488_ (.A(_1051_),
+ .X(_1052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4489_ (.A(_0071_),
+ .B(_0069_),
+ .C(_0067_),
+ .D(_0065_),
+ .X(_1053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4490_ (.A(_1052_),
+ .B(_1053_),
+ .X(_1054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4491_ (.A(_1023_),
+ .B(_1054_),
+ .X(_1055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4492_ (.A(_1055_),
+ .X(_1056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4493_ (.A(_1056_),
+ .Y(_1057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4494_ (.A1(\gpio_configure[25][7] ),
+ .A2(_1056_),
+ .B1(\cdata[7] ),
+ .B2(_1057_),
+ .X(_1014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4495_ (.A1(\gpio_configure[25][6] ),
+ .A2(_1056_),
+ .B1(\cdata[6] ),
+ .B2(_1057_),
+ .X(_1013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4496_ (.A1(\gpio_configure[25][5] ),
+ .A2(_1056_),
+ .B1(\cdata[5] ),
+ .B2(_1057_),
+ .X(_1012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4497_ (.A1(\gpio_configure[25][4] ),
+ .A2(_1056_),
+ .B1(net359),
+ .B2(_1057_),
+ .X(_1011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4498_ (.A1(\gpio_configure[25][3] ),
+ .A2(_1056_),
+ .B1(net361),
+ .B2(_1057_),
+ .X(_1010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4499_ (.A1(\gpio_configure[25][2] ),
+ .A2(_1056_),
+ .B1(net363),
+ .B2(_1057_),
+ .X(_1009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4500_ (.A1(\gpio_configure[25][1] ),
+ .A2(_1056_),
+ .B1(net366),
+ .B2(_1057_),
+ .X(_1008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4501_ (.A1(\gpio_configure[25][0] ),
+ .A2(_1056_),
+ .B1(net367),
+ .B2(_1057_),
+ .X(_1007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4502_ (.A(_0071_),
+ .B(_0069_),
+ .C(_0067_),
+ .D(_1030_),
+ .X(_1058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4503_ (.A(_1052_),
+ .B(_1058_),
+ .X(_1059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4504_ (.A(_1043_),
+ .B(_1059_),
+ .X(_1060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _4505_ (.A(_1060_),
+ .X(_1061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4506_ (.A(_1061_),
+ .Y(_1062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4507_ (.A1(\gpio_configure[26][12] ),
+ .A2(_1061_),
+ .B1(net359),
+ .B2(_1062_),
+ .X(_1006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4508_ (.A1(\gpio_configure[26][11] ),
+ .A2(_1061_),
+ .B1(net361),
+ .B2(_1062_),
+ .X(_1005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4509_ (.A1(\gpio_configure[26][10] ),
+ .A2(_1061_),
+ .B1(net363),
+ .B2(_1062_),
+ .X(_1004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4510_ (.A1(\gpio_configure[26][9] ),
+ .A2(_1061_),
+ .B1(net365),
+ .B2(_1062_),
+ .X(_1003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4511_ (.A1(\gpio_configure[26][8] ),
+ .A2(_1061_),
+ .B1(net367),
+ .B2(_1062_),
+ .X(_1002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _4512_ (.A1(serial_bb_clock),
+ .A2(_1034_),
+ .B1(net359),
+ .B2(_1035_),
+ .X(_1001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4513_ (.A(_1040_),
+ .B(_0069_),
+ .C(_1029_),
+ .D(_0065_),
+ .X(_1063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4514_ (.A(_0073_),
+ .B(_0075_),
+ .C(_1026_),
+ .X(_1064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4515_ (.A(_1064_),
+ .X(_1065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4516_ (.A(_1063_),
+ .B(_1065_),
+ .X(_1066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4517_ (.A(_1066_),
+ .Y(_1067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4518_ (.A1(net204),
+ .A2(_1067_),
+ .B1(net367),
+ .B2(_1066_),
+ .C1(_0063_),
+ .X(_1000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4519_ (.A(_1046_),
+ .B(_1065_),
+ .C(_1043_),
+ .X(_1068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4520_ (.A0(net367),
+ .A1(reset_reg),
+ .S(_1068_),
+ .X(_1069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4521_ (.A(_1069_),
+ .X(_0999_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4522_ (.A(_0067_),
+ .B(_1030_),
+ .C(_0071_),
+ .D(_1041_),
+ .X(_1070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4523_ (.A(_1028_),
+ .B(_1070_),
+ .X(_1071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4524_ (.A(_1023_),
+ .B(_1071_),
+ .X(_1072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _4525_ (.A(_1072_),
+ .X(_1073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4526_ (.A(_1073_),
+ .Y(_1074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4527_ (.A1(net323),
+ .A2(_1073_),
+ .B1(\cdata[7] ),
+ .B2(_1074_),
+ .X(_0998_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4528_ (.A1(net322),
+ .A2(_1073_),
+ .B1(\cdata[6] ),
+ .B2(_1074_),
+ .X(_0997_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4529_ (.A1(net321),
+ .A2(_1073_),
+ .B1(\cdata[5] ),
+ .B2(_1074_),
+ .X(_0996_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4530_ (.A1(net320),
+ .A2(_1073_),
+ .B1(net359),
+ .B2(_1074_),
+ .X(_0995_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4531_ (.A1(net319),
+ .A2(_1073_),
+ .B1(net361),
+ .B2(_1074_),
+ .X(_0994_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4532_ (.A1(net318),
+ .A2(_1073_),
+ .B1(net363),
+ .B2(_1074_),
+ .X(_0993_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4533_ (.A1(net317),
+ .A2(_1073_),
+ .B1(net365),
+ .B2(_1074_),
+ .X(_0992_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4534_ (.A1(net316),
+ .A2(_1073_),
+ .B1(net367),
+ .B2(_1074_),
+ .X(_0991_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4535_ (.A(_0067_),
+ .B(_0065_),
+ .C(_0071_),
+ .D(_1041_),
+ .X(_1075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4536_ (.A(_1028_),
+ .B(_1075_),
+ .X(_1076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4537_ (.A(_1043_),
+ .B(_1076_),
+ .X(_1077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4538_ (.A0(net367),
+ .A1(net325),
+ .S(_1077_),
+ .X(_1078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4539_ (.A(_1078_),
+ .X(_0990_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4540_ (.A0(net365),
+ .A1(net324),
+ .S(_1077_),
+ .X(_1079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4541_ (.A(_1079_),
+ .X(_0989_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4542_ (.A(\wbbd_state[6] ),
+ .Y(_1080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4543_ (.A(\wbbd_state[5] ),
+ .Y(_1081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4544_ (.A(\wbbd_state[7] ),
+ .Y(_1082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4545_ (.A(\wbbd_state[8] ),
+ .Y(_1083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4546_ (.A(\wbbd_state[9] ),
+ .Y(_1084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _4547_ (.A(_1082_),
+ .B(_1083_),
+ .C(_1084_),
+ .X(_1085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4548_ (.A(_1085_),
+ .X(_0169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_8 _4549_ (.A(_1081_),
+ .B(_0169_),
+ .Y(_1086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _4550_ (.A(_1086_),
+ .Y(_1087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4551_ (.A(\wbbd_state[6] ),
+ .B(_1086_),
+ .X(_1088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _4552_ (.A1(_1080_),
+ .A2(_1087_),
+ .A3(wbbd_write),
+ .B1(_4442_),
+ .B2(_1088_),
+ .X(_0988_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4553_ (.A(_1040_),
+ .B(_0069_),
+ .C(_0067_),
+ .D(_1030_),
+ .X(_1089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4554_ (.A(_1065_),
+ .B(_1089_),
+ .C(_1043_),
+ .X(_1090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4555_ (.A0(net367),
+ .A1(net263),
+ .S(_1090_),
+ .X(_1091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4556_ (.A(_1091_),
+ .X(_0987_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4557_ (.A(_1028_),
+ .B(_1053_),
+ .X(_1092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4558_ (.A(_1043_),
+ .B(_1092_),
+ .X(_1093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4559_ (.A0(net365),
+ .A1(net291),
+ .S(_1093_),
+ .X(_1094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4560_ (.A(_1094_),
+ .X(_0986_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4561_ (.A0(net367),
+ .A1(net290),
+ .S(_1093_),
+ .X(_1095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4562_ (.A(_1095_),
+ .X(_0985_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4563_ (.A(_1042_),
+ .B(_1065_),
+ .X(_1096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4564_ (.A(_1023_),
+ .B(_1096_),
+ .X(_1097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4565_ (.A(_1097_),
+ .X(_1098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4566_ (.A(_1098_),
+ .Y(_1099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4567_ (.A1(net289),
+ .A2(_1098_),
+ .B1(\cdata[7] ),
+ .B2(_1099_),
+ .X(_0984_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4568_ (.A1(net288),
+ .A2(_1098_),
+ .B1(\cdata[6] ),
+ .B2(_1099_),
+ .X(_0983_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4569_ (.A1(net287),
+ .A2(_1098_),
+ .B1(\cdata[5] ),
+ .B2(_1099_),
+ .X(_0982_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4570_ (.A1(net286),
+ .A2(_1098_),
+ .B1(net359),
+ .B2(_1099_),
+ .X(_0981_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4571_ (.A1(net284),
+ .A2(_1098_),
+ .B1(net361),
+ .B2(_1099_),
+ .X(_0980_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4572_ (.A1(net283),
+ .A2(_1098_),
+ .B1(net363),
+ .B2(_1099_),
+ .X(_0979_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4573_ (.A1(net282),
+ .A2(_1098_),
+ .B1(net365),
+ .B2(_1099_),
+ .X(_0978_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4574_ (.A1(net281),
+ .A2(_1098_),
+ .B1(net367),
+ .B2(_1099_),
+ .X(_0977_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4575_ (.A(_1040_),
+ .B(_1041_),
+ .C(_1029_),
+ .D(_0065_),
+ .X(_1100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4576_ (.A(_1065_),
+ .B(_1100_),
+ .X(_1101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4577_ (.A(_1023_),
+ .B(_1101_),
+ .X(_1102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _4578_ (.A(_1102_),
+ .X(_1103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4579_ (.A(_1103_),
+ .Y(_1104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4580_ (.A1(net280),
+ .A2(_1103_),
+ .B1(\cdata[7] ),
+ .B2(_1104_),
+ .X(_0976_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4581_ (.A1(net279),
+ .A2(_1103_),
+ .B1(\cdata[6] ),
+ .B2(_1104_),
+ .X(_0975_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4582_ (.A1(net278),
+ .A2(_1103_),
+ .B1(\cdata[5] ),
+ .B2(_1104_),
+ .X(_0974_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4583_ (.A1(net277),
+ .A2(_1103_),
+ .B1(net359),
+ .B2(_1104_),
+ .X(_0973_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4584_ (.A1(net276),
+ .A2(_1103_),
+ .B1(net361),
+ .B2(_1104_),
+ .X(_0972_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4585_ (.A1(net275),
+ .A2(_1103_),
+ .B1(net363),
+ .B2(_1104_),
+ .X(_0971_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4586_ (.A1(net299),
+ .A2(_1103_),
+ .B1(net365),
+ .B2(_1104_),
+ .X(_0970_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4587_ (.A1(net298),
+ .A2(_1103_),
+ .B1(net367),
+ .B2(_1104_),
+ .X(_0969_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4588_ (.A(_1040_),
+ .B(_1041_),
+ .C(_0067_),
+ .D(_1030_),
+ .X(_1105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4589_ (.A(_1065_),
+ .B(_1105_),
+ .X(_1106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4590_ (.A(_1023_),
+ .B(_1106_),
+ .X(_1107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4591_ (.A(_1107_),
+ .X(_1108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4592_ (.A(_1108_),
+ .Y(_1109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4593_ (.A1(net297),
+ .A2(_1108_),
+ .B1(\cdata[7] ),
+ .B2(_1109_),
+ .X(_0968_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4594_ (.A1(net296),
+ .A2(_1108_),
+ .B1(\cdata[6] ),
+ .B2(_1109_),
+ .X(_0967_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4595_ (.A1(net295),
+ .A2(_1108_),
+ .B1(\cdata[5] ),
+ .B2(_1109_),
+ .X(_0966_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4596_ (.A1(net294),
+ .A2(_1108_),
+ .B1(net359),
+ .B2(_1109_),
+ .X(_0965_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4597_ (.A1(net293),
+ .A2(_1108_),
+ .B1(net361),
+ .B2(_1109_),
+ .X(_0964_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4598_ (.A1(net292),
+ .A2(_1108_),
+ .B1(net363),
+ .B2(_1109_),
+ .X(_0963_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4599_ (.A1(net285),
+ .A2(_1108_),
+ .B1(net365),
+ .B2(_1109_),
+ .X(_0962_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4600_ (.A1(net274),
+ .A2(_1108_),
+ .B1(net367),
+ .B2(_1109_),
+ .X(_0961_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4601_ (.A(_1028_),
+ .B(_1058_),
+ .X(_1110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4602_ (.A(_1023_),
+ .B(_1110_),
+ .X(_1111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4603_ (.A(_1111_),
+ .X(_1112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4604_ (.A(_1112_),
+ .Y(_1113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4605_ (.A1(net262),
+ .A2(_1112_),
+ .B1(\cdata[5] ),
+ .B2(_1113_),
+ .X(_0960_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4606_ (.A1(net261),
+ .A2(_1112_),
+ .B1(net359),
+ .B2(_1113_),
+ .X(_0959_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4607_ (.A1(net260),
+ .A2(_1112_),
+ .B1(net361),
+ .B2(_1113_),
+ .X(_0958_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4608_ (.A1(net273),
+ .A2(_1112_),
+ .B1(net363),
+ .B2(_1113_),
+ .X(_0957_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4609_ (.A1(net272),
+ .A2(_1112_),
+ .B1(net365),
+ .B2(_1113_),
+ .X(_0956_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4610_ (.A1(net271),
+ .A2(_1112_),
+ .B1(net367),
+ .B2(_1113_),
+ .X(_0955_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4611_ (.A(_0071_),
+ .B(_0069_),
+ .C(_1029_),
+ .D(_0065_),
+ .X(_1114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4612_ (.A(_1028_),
+ .B(_1114_),
+ .X(_1115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4613_ (.A(_1043_),
+ .B(_1115_),
+ .X(_1116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _4614_ (.A(_1116_),
+ .X(_1117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4615_ (.A(_1117_),
+ .Y(_1118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4616_ (.A1(net269),
+ .A2(_1117_),
+ .B1(net359),
+ .B2(_1118_),
+ .X(_0954_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4617_ (.A1(net268),
+ .A2(_1117_),
+ .B1(net361),
+ .B2(_1118_),
+ .X(_0953_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4618_ (.A1(net267),
+ .A2(_1117_),
+ .B1(net363),
+ .B2(_1118_),
+ .X(_0952_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4619_ (.A1(net266),
+ .A2(_1117_),
+ .B1(net365),
+ .B2(_1118_),
+ .X(_0951_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4620_ (.A1(net265),
+ .A2(_1117_),
+ .B1(net367),
+ .B2(_1118_),
+ .X(_0950_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4621_ (.A(_1040_),
+ .B(_0069_),
+ .C(_0067_),
+ .D(_0065_),
+ .X(_1119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4622_ (.A(_1065_),
+ .B(_1119_),
+ .X(_1120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4623_ (.A(_1043_),
+ .B(_1120_),
+ .X(_1121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4624_ (.A0(net365),
+ .A1(net264),
+ .S(_1121_),
+ .X(_1122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4625_ (.A(_1122_),
+ .X(_0949_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4626_ (.A0(net367),
+ .A1(net270),
+ .S(_1121_),
+ .X(_1123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4627_ (.A(_1123_),
+ .X(_0948_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4628_ (.A(net375),
+ .Y(_1124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _4629_ (.A(hkspi_disable),
+ .B(\gpio_configure[3][3] ),
+ .C(net67),
+ .X(_1125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_8 _4630_ (.A(_1124_),
+ .B(_1125_),
+ .Y(_1126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4631_ (.A(_1126_),
+ .X(_0261_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4632_ (.A(\hkspi.readmode ),
+ .Y(_0154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4633_ (.A(\hkspi.state[2] ),
+ .Y(_1127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4634_ (.A(_0154_),
+ .B(_1127_),
+ .X(_1128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _4635_ (.A(_1128_),
+ .X(_1129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4636_ (.A(_1129_),
+ .Y(_1130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4637_ (.A1(\hkspi.SDO ),
+ .A2(_1129_),
+ .B1(_0061_),
+ .B2(_1130_),
+ .X(_0947_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4638_ (.A(_0261_),
+ .X(_1131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4639_ (.A(_1131_),
+ .X(_0260_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4640_ (.A1(\hkspi.ldata[6] ),
+ .A2(_1129_),
+ .B1(_0060_),
+ .B2(_1130_),
+ .X(_0946_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4641_ (.A(_0261_),
+ .X(_1132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4642_ (.A(_1132_),
+ .X(_0259_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4643_ (.A1(\hkspi.ldata[5] ),
+ .A2(_1129_),
+ .B1(_0059_),
+ .B2(_1130_),
+ .X(_0945_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4644_ (.A(_0261_),
+ .X(_1133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4645_ (.A(_1133_),
+ .X(_0258_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _4646_ (.A1(\hkspi.ldata[4] ),
+ .A2(_1129_),
+ .B1(_0058_),
+ .B2(_1130_),
+ .X(_0944_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4647_ (.A(_0261_),
+ .X(_1134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4648_ (.A(_1134_),
+ .X(_0257_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4649_ (.A1(\hkspi.ldata[3] ),
+ .A2(_1129_),
+ .B1(_0057_),
+ .B2(_1130_),
+ .X(_0943_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4650_ (.A(_0261_),
+ .X(_1135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4651_ (.A(_1135_),
+ .X(_0256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4652_ (.A1(\hkspi.ldata[2] ),
+ .A2(_1129_),
+ .B1(_0056_),
+ .B2(_1130_),
+ .X(_0942_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4653_ (.A(_0261_),
+ .X(_1136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4654_ (.A(_1136_),
+ .X(_0255_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4655_ (.A1(\hkspi.ldata[1] ),
+ .A2(_1129_),
+ .B1(_0055_),
+ .B2(_1130_),
+ .X(_0941_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4656_ (.A(_0261_),
+ .X(_1137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4657_ (.A(_1137_),
+ .X(_0254_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _4658_ (.A(\hkspi.count[1] ),
+ .B(\hkspi.count[0] ),
+ .C(\hkspi.count[2] ),
+ .X(_1138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4659_ (.A(_1138_),
+ .Y(_0062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4660_ (.A(\gpio_configure[17][8] ),
+ .Y(_1139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4661_ (.A(_1036_),
+ .B(_1026_),
+ .C(_1024_),
+ .X(_1140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4662_ (.A(_1140_),
+ .X(_1141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4663_ (.A(_1042_),
+ .B(_1141_),
+ .X(_1142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4664_ (.A(\gpio_configure[6][0] ),
+ .Y(_1143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4665_ (.A(_0073_),
+ .B(_1036_),
+ .C(_1026_),
+ .X(_1144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4666_ (.A(_1144_),
+ .X(_1145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4667_ (.A(_1063_),
+ .B(_1145_),
+ .X(_1146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4668_ (.A(\gpio_configure[7][0] ),
+ .Y(_1147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4669_ (.A(_1040_),
+ .B(_1041_),
+ .C(_0067_),
+ .D(_0065_),
+ .X(_1148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4670_ (.A(_1148_),
+ .B(_1145_),
+ .X(_1149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4671_ (.A(\gpio_configure[35][8] ),
+ .Y(_1150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4672_ (.A(_1031_),
+ .B(_1039_),
+ .X(_1151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4673_ (.A1(_1147_),
+ .A2(_1149_),
+ .B1(_1150_),
+ .B2(_1151_),
+ .X(_1152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4674_ (.A1(_1139_),
+ .A2(_1142_),
+ .B1(_1143_),
+ .B2(_1146_),
+ .C1(_1152_),
+ .X(_1153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4675_ (.A(\gpio_configure[34][0] ),
+ .Y(_1154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4676_ (.A(_1039_),
+ .B(_1114_),
+ .X(_1155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4677_ (.A(\gpio_configure[2][8] ),
+ .Y(_1156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4678_ (.A(_1058_),
+ .B(_1145_),
+ .X(_1157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4679_ (.A(_1039_),
+ .B(_1089_),
+ .X(_1158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _4680_ (.A(_1158_),
+ .Y(_1159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4681_ (.A(net300),
+ .Y(_1160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4682_ (.A(_1039_),
+ .B(_1100_),
+ .X(_1161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _4683_ (.A1_N(net61),
+ .A2_N(_1159_),
+ .B1(_1160_),
+ .B2(_1161_),
+ .X(_1162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4684_ (.A1(_1154_),
+ .A2(_1155_),
+ .B1(_1156_),
+ .B2(_1157_),
+ .C1(_1162_),
+ .X(_1163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4685_ (.A(\gpio_configure[10][8] ),
+ .Y(_1164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4686_ (.A(_1058_),
+ .B(_1141_),
+ .X(_1165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4687_ (.A(\gpio_configure[4][0] ),
+ .Y(_1166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4688_ (.A(_1029_),
+ .B(_0065_),
+ .C(_0071_),
+ .D(_1041_),
+ .X(_1167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4689_ (.A(_1167_),
+ .B(_1145_),
+ .X(_1168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4690_ (.A(\gpio_configure[3][8] ),
+ .Y(_1169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4691_ (.A(_1031_),
+ .B(_1145_),
+ .X(_1170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4692_ (.A(_1169_),
+ .B(_1170_),
+ .X(_1171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4693_ (.A1(_1164_),
+ .A2(_1165_),
+ .B1(_1166_),
+ .B2(_1168_),
+ .C1(_1171_),
+ .X(_1172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4694_ (.A(\gpio_configure[8][8] ),
+ .Y(_1173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4695_ (.A(_1105_),
+ .B(_1145_),
+ .X(_1174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4696_ (.A(net36),
+ .Y(_1175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4697_ (.A(_1039_),
+ .B(_1105_),
+ .X(_1176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4698_ (.A(_1176_),
+ .X(_1177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4699_ (.A(\gpio_configure[7][8] ),
+ .Y(_1178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4700_ (.A(_1046_),
+ .B(_1145_),
+ .X(_1179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4701_ (.A(\gpio_configure[5][0] ),
+ .Y(_1180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4702_ (.A(_1119_),
+ .B(_1145_),
+ .X(_1181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4703_ (.A1(_1178_),
+ .A2(_1179_),
+ .B1(_1180_),
+ .B2(_1181_),
+ .X(_1182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4704_ (.A1(_1173_),
+ .A2(_1174_),
+ .B1(_1175_),
+ .B2(_1177_),
+ .C1(_1182_),
+ .X(_1183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4705_ (.A(_1153_),
+ .B(_1163_),
+ .C(_1172_),
+ .D(_1183_),
+ .X(_1184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4706_ (.A(\gpio_configure[14][8] ),
+ .Y(_1185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4707_ (.A(_1089_),
+ .B(_1141_),
+ .X(_1186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4708_ (.A(\gpio_configure[11][0] ),
+ .Y(_1187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4709_ (.A(_1075_),
+ .B(_1141_),
+ .X(_1188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4710_ (.A(\gpio_configure[15][8] ),
+ .Y(_1189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4711_ (.A(_1046_),
+ .B(_1141_),
+ .X(_1190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4712_ (.A(\gpio_configure[11][8] ),
+ .Y(_1191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4713_ (.A(_1031_),
+ .B(_1141_),
+ .X(_1192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4714_ (.A1(_1189_),
+ .A2(_1190_),
+ .B1(_1191_),
+ .B2(_1192_),
+ .X(_1193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4715_ (.A1(_1185_),
+ .A2(_1186_),
+ .B1(_1187_),
+ .B2(_1188_),
+ .C1(_1193_),
+ .X(_1194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4716_ (.A(\gpio_configure[8][0] ),
+ .Y(_1195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4717_ (.A(_1100_),
+ .B(_1145_),
+ .X(_1196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4718_ (.A(\gpio_configure[16][8] ),
+ .Y(_1197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4719_ (.A(_1105_),
+ .B(_1141_),
+ .X(_1198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4720_ (.A(\gpio_configure[13][0] ),
+ .Y(_1199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4721_ (.A(_1119_),
+ .B(_1141_),
+ .X(_1200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4722_ (.A(\gpio_configure[12][8] ),
+ .Y(_1201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4723_ (.A(_1070_),
+ .B(_1141_),
+ .X(_1202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4724_ (.A1(_1199_),
+ .A2(_1200_),
+ .B1(_1201_),
+ .B2(_1202_),
+ .X(_1203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4725_ (.A1(_1195_),
+ .A2(_1196_),
+ .B1(_1197_),
+ .B2(_1198_),
+ .C1(_1203_),
+ .X(_1204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4726_ (.A(\gpio_configure[14][0] ),
+ .Y(_1205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4727_ (.A(_1063_),
+ .B(_1141_),
+ .X(_1206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4728_ (.A(\gpio_configure[13][8] ),
+ .Y(_1207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _4729_ (.A(_1029_),
+ .B(_1030_),
+ .C(_0071_),
+ .D(_1041_),
+ .X(_1208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4730_ (.A(_1208_),
+ .B(_1141_),
+ .X(_1209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4731_ (.A(_1207_),
+ .B(_1209_),
+ .X(_1210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4732_ (.A(\gpio_configure[37][0] ),
+ .Y(_1211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4733_ (.A(_1039_),
+ .B(_1119_),
+ .X(_1212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4734_ (.A(\gpio_configure[10][0] ),
+ .Y(_1213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4735_ (.A(_1114_),
+ .B(_1141_),
+ .X(_1214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4736_ (.A1(_1211_),
+ .A2(_1212_),
+ .B1(_1213_),
+ .B2(_1214_),
+ .X(_1215_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4737_ (.A(net71),
+ .Y(_1216_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4738_ (.A(_1039_),
+ .B(_1148_),
+ .X(_1217_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _4739_ (.A(_1217_),
+ .X(_1218_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4740_ (.A(\gpio_configure[9][0] ),
+ .Y(_1219_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4741_ (.A(_1053_),
+ .B(_1141_),
+ .X(_1220_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4742_ (.A(\gpio_configure[16][0] ),
+ .Y(_1221_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4743_ (.A(_1100_),
+ .B(_1141_),
+ .X(_1222_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4744_ (.A(\gpio_configure[33][0] ),
+ .Y(_1223_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4745_ (.A(_1039_),
+ .B(_1053_),
+ .X(_1224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4746_ (.A1(_1221_),
+ .A2(_1222_),
+ .B1(_1223_),
+ .B2(_1224_),
+ .X(_1225_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4747_ (.A1(_1216_),
+ .A2(_1218_),
+ .B1(_1219_),
+ .B2(_1220_),
+ .C1(_1225_),
+ .X(_1226_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _4748_ (.A1(_1205_),
+ .A2(_1206_),
+ .B1(_1210_),
+ .C1(_1215_),
+ .D1(_1226_),
+ .X(_1227_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4749_ (.A(\gpio_configure[37][8] ),
+ .Y(_1228_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4750_ (.A(_1039_),
+ .B(_1208_),
+ .X(_1229_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4751_ (.A(\gpio_configure[35][0] ),
+ .Y(_1230_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4752_ (.A(_1039_),
+ .B(_1075_),
+ .X(_1231_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4753_ (.A(hkspi_disable),
+ .Y(_1232_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4754_ (.A(net43),
+ .Y(_1233_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4755_ (.A(_1039_),
+ .B(_1046_),
+ .X(_1234_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4756_ (.A(_1234_),
+ .X(_1235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _4757_ (.A1(_1039_),
+ .A2(_1042_),
+ .A3(_1232_),
+ .B1(_1233_),
+ .B2(_1235_),
+ .X(_1236_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4758_ (.A1(_1228_),
+ .A2(_1229_),
+ .B1(_1230_),
+ .B2(_1231_),
+ .C1(_1236_),
+ .X(_1237_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4759_ (.A(\gpio_configure[15][0] ),
+ .Y(_1238_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4760_ (.A(_1148_),
+ .B(_1141_),
+ .X(_1239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4761_ (.A(\gpio_configure[9][8] ),
+ .Y(_1240_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4762_ (.A(_1042_),
+ .B(_1145_),
+ .X(_1241_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4763_ (.A(\gpio_configure[36][8] ),
+ .Y(_1242_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _4764_ (.A(_1039_),
+ .B(_1070_),
+ .X(_1243_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4765_ (.A(\gpio_configure[4][8] ),
+ .Y(_1244_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4766_ (.A(_1070_),
+ .B(_1145_),
+ .X(_1245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4767_ (.A1(_1242_),
+ .A2(_1243_),
+ .B1(_1244_),
+ .B2(_1245_),
+ .X(_1246_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4768_ (.A1(_1238_),
+ .A2(_1239_),
+ .B1(_1240_),
+ .B2(_1241_),
+ .C1(_1246_),
+ .X(_1247_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4769_ (.A(\gpio_configure[1][0] ),
+ .Y(_1248_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4770_ (.A(_1053_),
+ .B(_1145_),
+ .X(_1249_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4771_ (.A(\gpio_configure[36][0] ),
+ .Y(_1250_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4772_ (.A(_1039_),
+ .B(_1167_),
+ .X(_1251_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4773_ (.A(\gpio_configure[2][0] ),
+ .Y(_1252_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4774_ (.A(_1114_),
+ .B(_1145_),
+ .X(_1253_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4775_ (.A(\gpio_configure[6][8] ),
+ .Y(_1254_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4776_ (.A(_1089_),
+ .B(_1145_),
+ .X(_1255_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _4777_ (.A1(_1252_),
+ .A2(_1253_),
+ .B1(_1254_),
+ .B2(_1255_),
+ .X(_1256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4778_ (.A1(_1248_),
+ .A2(_1249_),
+ .B1(_1250_),
+ .B2(_1251_),
+ .C1(_1256_),
+ .X(_1257_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4779_ (.A(\gpio_configure[12][0] ),
+ .Y(_1258_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4780_ (.A(_1167_),
+ .B(_1141_),
+ .X(_1259_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4781_ (.A(net52),
+ .Y(_1260_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4782_ (.A(_1039_),
+ .B(_1063_),
+ .X(_1261_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _4783_ (.A(_1261_),
+ .X(_1262_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4784_ (.A(\gpio_configure[5][8] ),
+ .Y(_1263_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4785_ (.A(_1208_),
+ .B(_1145_),
+ .X(_1264_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4786_ (.A(\gpio_configure[34][8] ),
+ .Y(_1265_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4787_ (.A(_1039_),
+ .B(_1058_),
+ .X(_1266_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _4788_ (.A1(_1263_),
+ .A2(_1264_),
+ .B1(_1265_),
+ .B2(_1266_),
+ .X(_1267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4789_ (.A1(_1258_),
+ .A2(_1259_),
+ .B1(_1260_),
+ .B2(_1262_),
+ .C1(_1267_),
+ .X(_1268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4790_ (.A(_1237_),
+ .B(_1247_),
+ .C(_1257_),
+ .D(_1268_),
+ .X(_1269_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4791_ (.A(_1194_),
+ .B(_1204_),
+ .C(_1227_),
+ .D(_1269_),
+ .X(_1270_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4792_ (.A(net281),
+ .Y(_1271_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4793_ (.A(\gpio_configure[27][0] ),
+ .Y(_1272_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4794_ (.A(_1052_),
+ .B(_1075_),
+ .X(_1273_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4795_ (.A(\gpio_configure[0][8] ),
+ .Y(_1274_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4796_ (.A(_1028_),
+ .B(_1105_),
+ .X(_1275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4797_ (.A(net265),
+ .Y(_1276_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4798_ (.A1(_1274_),
+ .A2(_1275_),
+ .B1(_1276_),
+ .B2(_1115_),
+ .X(_1277_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4799_ (.A1(_1271_),
+ .A2(_1096_),
+ .B1(_1272_),
+ .B2(_1273_),
+ .C1(_1277_),
+ .X(_1278_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4800_ (.A(\gpio_configure[24][8] ),
+ .Y(_1279_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4801_ (.A(_0073_),
+ .B(_0075_),
+ .C(_1037_),
+ .X(_1280_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _4802_ (.A(_1280_),
+ .X(_1281_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4803_ (.A(_1105_),
+ .B(_1281_),
+ .X(_1282_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4804_ (.A(\gpio_configure[17][0] ),
+ .Y(_1283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4805_ (.A(_1053_),
+ .B(_1281_),
+ .X(_1284_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4806_ (.A(reset_reg),
+ .B(\hkspi.pre_pass_thru_mgmt ),
+ .C(\hkspi.pass_thru_mgmt_delay ),
+ .X(_1285_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _4807_ (.A(_1285_),
+ .X(net304),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4808_ (.A(net304),
+ .Y(_1286_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4809_ (.A(\gpio_configure[25][8] ),
+ .Y(_1287_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4810_ (.A(_1042_),
+ .B(_1281_),
+ .X(_1288_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _4811_ (.A1(_1046_),
+ .A2(_1065_),
+ .A3(_1286_),
+ .B1(_1287_),
+ .B2(_1288_),
+ .X(_1289_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4812_ (.A1(_1279_),
+ .A2(_1282_),
+ .B1(_1283_),
+ .B2(_1284_),
+ .C1(_1289_),
+ .X(_1290_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4813_ (.A(net325),
+ .Y(_1291_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _4814_ (.A(\gpio_configure[26][0] ),
+ .Y(_1292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4815_ (.A(_1052_),
+ .B(_1114_),
+ .X(_1293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _4816_ (.A(\gpio_configure[31][0] ),
+ .Y(_1294_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4817_ (.A(_1052_),
+ .B(_1148_),
+ .X(_1295_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4818_ (.A(net270),
+ .Y(_1296_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4819_ (.A1(_1294_),
+ .A2(_1295_),
+ .B1(_1296_),
+ .B2(_1120_),
+ .X(_1297_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4820_ (.A1(_1291_),
+ .A2(_1076_),
+ .B1(_1292_),
+ .B2(_1293_),
+ .C1(_1297_),
+ .X(_1298_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4821_ (.A(net20),
+ .Y(_1299_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4822_ (.A(_1065_),
+ .B(_1075_),
+ .X(_1300_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4823_ (.A(\gpio_configure[1][8] ),
+ .Y(_1301_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4824_ (.A(_1028_),
+ .B(_1042_),
+ .X(_1302_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4825_ (.A(irq_1_inputsrc),
+ .Y(_1303_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4826_ (.A(_1028_),
+ .B(_1148_),
+ .X(_1304_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4827_ (.A(serial_busy),
+ .Y(_1305_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4828_ (.A1(_1303_),
+ .A2(_1304_),
+ .B1(_1305_),
+ .B2(_1032_),
+ .X(_1306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4829_ (.A1(_1299_),
+ .A2(_1300_),
+ .B1(_1301_),
+ .B2(_1302_),
+ .C1(_1306_),
+ .X(_1307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4830_ (.A(_1278_),
+ .B(_1290_),
+ .C(_1298_),
+ .D(_1307_),
+ .X(_1308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4831_ (.A(net109),
+ .Y(_1309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4832_ (.A(_1028_),
+ .B(_1167_),
+ .X(_1310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _4833_ (.A(\gpio_configure[32][0] ),
+ .Y(_1311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4834_ (.A(_1052_),
+ .B(_1100_),
+ .X(_1312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4835_ (.A(trap_output_dest),
+ .Y(_1313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4836_ (.A(\gpio_configure[27][8] ),
+ .Y(_1314_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4837_ (.A(_1031_),
+ .B(_1052_),
+ .X(_1315_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4838_ (.A1(_1313_),
+ .A2(_1047_),
+ .B1(_1314_),
+ .B2(_1315_),
+ .X(_1316_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4839_ (.A1(_1309_),
+ .A2(_1310_),
+ .B1(_1311_),
+ .B2(_1312_),
+ .C1(_1316_),
+ .X(_1317_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4840_ (.A(net100),
+ .Y(_1318_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4841_ (.A(_1028_),
+ .B(_1208_),
+ .X(_1319_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4842_ (.A(\gpio_configure[3][0] ),
+ .Y(_1320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4843_ (.A(_1075_),
+ .B(_1145_),
+ .X(_1321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _4844_ (.A(_1031_),
+ .B(_1065_),
+ .X(_1322_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4845_ (.A1(_1318_),
+ .A2(_1319_),
+ .B1(_1320_),
+ .B2(_1321_),
+ .C1(_1322_),
+ .X(_1323_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4846_ (.A(\gpio_configure[24][0] ),
+ .Y(_1324_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4847_ (.A(_1100_),
+ .B(_1281_),
+ .X(_1325_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4848_ (.A(\gpio_configure[20][8] ),
+ .Y(_1326_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4849_ (.A(_1070_),
+ .B(_1281_),
+ .X(_1327_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4850_ (.A(\gpio_configure[30][0] ),
+ .Y(_1328_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4851_ (.A(_1052_),
+ .B(_1063_),
+ .X(_1329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4852_ (.A(net316),
+ .Y(_1330_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4853_ (.A1(_1328_),
+ .A2(_1329_),
+ .B1(_1330_),
+ .B2(_1071_),
+ .X(_1331_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4854_ (.A1(_1324_),
+ .A2(_1325_),
+ .B1(_1326_),
+ .B2(_1327_),
+ .C1(_1331_),
+ .X(_1332_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4855_ (.A(\gpio_configure[29][0] ),
+ .Y(_1333_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4856_ (.A(_1052_),
+ .B(_1119_),
+ .X(_1334_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4857_ (.A(\gpio_configure[25][0] ),
+ .Y(_1335_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4858_ (.A(\gpio_configure[31][8] ),
+ .Y(_1336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4859_ (.A(_1046_),
+ .B(_1052_),
+ .X(_1337_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4860_ (.A(net93),
+ .Y(_1338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4861_ (.A(_1028_),
+ .B(_1089_),
+ .X(_1339_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4862_ (.A1(_1336_),
+ .A2(_1337_),
+ .B1(_1338_),
+ .B2(_1339_),
+ .X(_1340_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4863_ (.A1(_1333_),
+ .A2(_1334_),
+ .B1(_1335_),
+ .B2(_1054_),
+ .C1(_1340_),
+ .X(_1341_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4864_ (.A(_1317_),
+ .B(_1323_),
+ .C(_1332_),
+ .D(_1341_),
+ .X(_1342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4865_ (.A(\gpio_configure[30][8] ),
+ .Y(_1343_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4866_ (.A(_1052_),
+ .B(_1089_),
+ .X(_1344_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _4867_ (.A(net130),
+ .Y(_1345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4868_ (.A(_1028_),
+ .B(_1063_),
+ .X(_1346_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4869_ (.A(net4),
+ .Y(_1347_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4870_ (.A(_1065_),
+ .B(_1208_),
+ .X(_1348_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4871_ (.A(net290),
+ .Y(_1349_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _4872_ (.A1(_1347_),
+ .A2(_1348_),
+ .B1(_1349_),
+ .B2(_1092_),
+ .X(_1350_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4873_ (.A1(_1343_),
+ .A2(_1344_),
+ .B1(_1345_),
+ .B2(_1346_),
+ .C1(_1350_),
+ .X(_1351_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4874_ (.A(net271),
+ .Y(_1352_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4875_ (.A(\gpio_configure[0][0] ),
+ .Y(_0099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4876_ (.A(_1028_),
+ .B(_1100_),
+ .X(_1353_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4877_ (.A(\gpio_configure[18][0] ),
+ .Y(_1354_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4878_ (.A(_1114_),
+ .B(_1281_),
+ .X(_1355_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4879_ (.A(net204),
+ .Y(_1356_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _4880_ (.A1(_1354_),
+ .A2(_1355_),
+ .B1(_1356_),
+ .B2(_1066_),
+ .X(_1357_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4881_ (.A1(_1352_),
+ .A2(_1110_),
+ .B1(_0099_),
+ .B2(_1353_),
+ .C1(_1357_),
+ .X(_1358_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4882_ (.A(\gpio_configure[26][8] ),
+ .Y(_1359_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4883_ (.A(\gpio_configure[28][8] ),
+ .Y(_1360_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4884_ (.A(_1052_),
+ .B(_1070_),
+ .X(_1361_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _4885_ (.A(_1065_),
+ .B(_1167_),
+ .C_N(net34),
+ .X(_1362_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4886_ (.A1(_1359_),
+ .A2(_1059_),
+ .B1(_1360_),
+ .B2(_1361_),
+ .C1(_1362_),
+ .X(_1363_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4887_ (.A(net274),
+ .Y(_1364_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4888_ (.A(\gpio_configure[29][8] ),
+ .Y(_1365_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4889_ (.A(_1052_),
+ .B(_1208_),
+ .X(_1366_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4890_ (.A(\gpio_configure[33][8] ),
+ .Y(_1367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4891_ (.A(_1042_),
+ .B(_1052_),
+ .X(_1368_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4892_ (.A(net123),
+ .Y(_1369_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4893_ (.A(_1028_),
+ .B(_1119_),
+ .X(_1370_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4894_ (.A1(_1367_),
+ .A2(_1368_),
+ .B1(_1369_),
+ .B2(_1370_),
+ .X(_1371_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4895_ (.A1(_1364_),
+ .A2(_1106_),
+ .B1(_1365_),
+ .B2(_1366_),
+ .C1(_1371_),
+ .X(_1372_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4896_ (.A(_1351_),
+ .B(_1358_),
+ .C(_1363_),
+ .D(_1372_),
+ .X(_1373_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4897_ (.A(\gpio_configure[22][0] ),
+ .Y(_1374_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4898_ (.A(_1063_),
+ .B(_1281_),
+ .X(_1375_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4899_ (.A(\gpio_configure[21][8] ),
+ .Y(_1376_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4900_ (.A(_1281_),
+ .B(_1208_),
+ .X(_1377_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4901_ (.A(net125),
+ .Y(_1378_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4902_ (.A(\gpio_configure[32][8] ),
+ .Y(_1379_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4903_ (.A(_1052_),
+ .B(_1105_),
+ .X(_1380_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _4904_ (.A1(_1065_),
+ .A2(_1148_),
+ .A3(_1378_),
+ .B1(_1379_),
+ .B2(_1380_),
+ .X(_1381_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4905_ (.A1(_1374_),
+ .A2(_1375_),
+ .B1(_1376_),
+ .B2(_1377_),
+ .C1(_1381_),
+ .X(_1382_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4906_ (.A(net11),
+ .Y(_1383_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4907_ (.A(_1065_),
+ .B(_1070_),
+ .X(_1384_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4908_ (.A(net298),
+ .Y(_1385_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4909_ (.A(net263),
+ .Y(_1386_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _4910_ (.A(\gpio_configure[28][0] ),
+ .Y(_1387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4911_ (.A(_1052_),
+ .B(_1167_),
+ .X(_1388_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _4912_ (.A1(_1065_),
+ .A2(_1089_),
+ .A3(_1386_),
+ .B1(_1387_),
+ .B2(_1388_),
+ .X(_1389_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _4913_ (.A1(_1383_),
+ .A2(_1384_),
+ .B1(_1385_),
+ .B2(_1101_),
+ .C1(_1389_),
+ .X(_1390_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4914_ (.A(\gpio_configure[20][0] ),
+ .Y(_1391_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4915_ (.A(_1167_),
+ .B(_1281_),
+ .X(_1392_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4916_ (.A(\gpio_configure[21][0] ),
+ .Y(_1393_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4917_ (.A(_1119_),
+ .B(_1281_),
+ .X(_1394_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4918_ (.A(\gpio_configure[19][8] ),
+ .Y(_1395_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4919_ (.A(_1031_),
+ .B(_1281_),
+ .X(_1396_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4920_ (.A(\gpio_configure[18][8] ),
+ .Y(_1397_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4921_ (.A(_1058_),
+ .B(_1281_),
+ .X(_1398_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _4922_ (.A1(_1395_),
+ .A2(_1396_),
+ .B1(_1397_),
+ .B2(_1398_),
+ .X(_1399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4923_ (.A1(_1391_),
+ .A2(_1392_),
+ .B1(_1393_),
+ .B2(_1394_),
+ .C1(_1399_),
+ .X(_1400_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4924_ (.A(\gpio_configure[22][8] ),
+ .Y(_1401_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4925_ (.A(_1089_),
+ .B(_1281_),
+ .X(_1402_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4926_ (.A(\gpio_configure[23][0] ),
+ .Y(_1403_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4927_ (.A(_1148_),
+ .B(_1281_),
+ .X(_1404_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4928_ (.A(\gpio_configure[19][0] ),
+ .Y(_1405_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4929_ (.A(_1075_),
+ .B(_1281_),
+ .X(_1406_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4930_ (.A(\gpio_configure[23][8] ),
+ .Y(_1407_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _4931_ (.A(_1046_),
+ .B(_1281_),
+ .X(_1408_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _4932_ (.A1(_1405_),
+ .A2(_1406_),
+ .B1(_1407_),
+ .B2(_1408_),
+ .X(_1409_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _4933_ (.A1(_1401_),
+ .A2(_1402_),
+ .B1(_1403_),
+ .B2(_1404_),
+ .C1(_1409_),
+ .X(_1410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _4934_ (.A(_1382_),
+ .B(_1390_),
+ .C(_1400_),
+ .D(_1410_),
+ .X(_1411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _4935_ (.A(_1308_),
+ .B(_1342_),
+ .C(_1373_),
+ .D(_1411_),
+ .X(_1412_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _4936_ (.A(_1184_),
+ .B(_1270_),
+ .C(_1412_),
+ .Y(_1413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _4937_ (.A1(_1130_),
+ .A2(_0062_),
+ .A3(_1413_),
+ .B1(\hkspi.ldata[0] ),
+ .B2(_1129_),
+ .X(_0940_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4938_ (.A(_0261_),
+ .X(_1414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4939_ (.A(_1414_),
+ .X(_0253_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4940_ (.A(\hkspi.count[2] ),
+ .Y(_1415_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4941_ (.A(\hkspi.count[1] ),
+ .Y(_1416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4942_ (.A(\hkspi.count[0] ),
+ .Y(_1417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4943_ (.A(_1415_),
+ .B(_1416_),
+ .C(_1417_),
+ .X(_1418_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _4944_ (.A(_1418_),
+ .X(_1419_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4945_ (.A(_1419_),
+ .Y(_1420_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _4946_ (.A1(\hkspi.wrstb ),
+ .A2(\hkspi.writemode ),
+ .B1(\hkspi.state[2] ),
+ .C1(_1420_),
+ .X(_0939_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4947_ (.A(_0261_),
+ .X(_1421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4948_ (.A(_1421_),
+ .X(_0252_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4949_ (.A(net58),
+ .Y(_1422_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _4950_ (.A(\hkspi.count[2] ),
+ .B(\hkspi.count[1] ),
+ .C(_1417_),
+ .X(_1423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _4951_ (.A(\hkspi.state[0] ),
+ .B(_1423_),
+ .Y(_1424_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4952_ (.A(\hkspi.pre_pass_thru_user ),
+ .Y(_1425_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _4953_ (.A(\hkspi.pre_pass_thru_mgmt ),
+ .Y(_1426_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _4954_ (.A1(_1426_),
+ .A2(_1419_),
+ .B1(\hkspi.count[2] ),
+ .C1(\hkspi.state[0] ),
+ .D1(\hkspi.count[1] ),
+ .X(_1427_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _4955_ (.A1(_1422_),
+ .A2(_1424_),
+ .B1(_1425_),
+ .B2(_1427_),
+ .Y(_0938_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4956_ (.A(_0261_),
+ .X(_1428_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4957_ (.A(_1428_),
+ .X(_0251_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _4958_ (.A(\hkspi.count[1] ),
+ .B(_1417_),
+ .Y(_1429_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _4959_ (.A(\hkspi.state[0] ),
+ .Y(_0087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_1 _4960_ (.A1(_1415_),
+ .A2(_0087_),
+ .A3(_1417_),
+ .B1(\hkspi.pre_pass_thru_mgmt ),
+ .X(_1430_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a41o_1 _4961_ (.A1(\hkspi.count[2] ),
+ .A2(\hkspi.state[0] ),
+ .A3(net58),
+ .A4(_1429_),
+ .B1(_1430_),
+ .X(_0937_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4962_ (.A(_0261_),
+ .X(_1431_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4963_ (.A(_1431_),
+ .X(_0250_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _4964_ (.A(\hkspi.state[0] ),
+ .B(_1127_),
+ .C(\hkspi.state[3] ),
+ .X(_1432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4965_ (.A(_1432_),
+ .X(_1433_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _4966_ (.A(_1433_),
+ .Y(_1434_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4967_ (.A1(\hkspi.odata[7] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[6] ),
+ .B2(_1434_),
+ .X(_0936_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4968_ (.A(_0261_),
+ .X(_1435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4969_ (.A(_1435_),
+ .X(_0249_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4970_ (.A1(\hkspi.odata[6] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[5] ),
+ .B2(_1434_),
+ .X(_0935_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4971_ (.A(_0261_),
+ .X(_1436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4972_ (.A(_1436_),
+ .X(_0248_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4973_ (.A1(\hkspi.odata[5] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[4] ),
+ .B2(_1434_),
+ .X(_0934_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4974_ (.A(_0261_),
+ .X(_1437_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4975_ (.A(_1437_),
+ .X(_0247_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4976_ (.A1(\hkspi.odata[4] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[3] ),
+ .B2(_1434_),
+ .X(_0933_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4977_ (.A(_0261_),
+ .X(_1438_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4978_ (.A(_1438_),
+ .X(_0246_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4979_ (.A1(\hkspi.odata[3] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[2] ),
+ .B2(_1434_),
+ .X(_0932_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4980_ (.A(_0261_),
+ .X(_1439_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4981_ (.A(_1439_),
+ .X(_0245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4982_ (.A1(\hkspi.odata[2] ),
+ .A2(_1433_),
+ .B1(\hkspi.odata[1] ),
+ .B2(_1434_),
+ .X(_0931_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4983_ (.A(_0261_),
+ .X(_1440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4984_ (.A(_1440_),
+ .X(_0244_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _4985_ (.A1(\hkspi.odata[1] ),
+ .A2(_1433_),
+ .B1(net58),
+ .B2(_1434_),
+ .X(_0930_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4986_ (.A(_0261_),
+ .X(_1441_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4987_ (.A(_1441_),
+ .X(_0243_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _4988_ (.A(\hkspi.fixed[2] ),
+ .B(\hkspi.fixed[1] ),
+ .Y(_1442_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _4989_ (.A1(\hkspi.count[1] ),
+ .A2(\hkspi.count[0] ),
+ .B1(\hkspi.count[2] ),
+ .X(_1443_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _4990_ (.A1(_1419_),
+ .A2(_1442_),
+ .A3(_1433_),
+ .B1(_0087_),
+ .B2(_1443_),
+ .X(_1444_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _4991_ (.A(_1444_),
+ .B_N(_0090_),
+ .X(_1445_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4992_ (.A0(_0045_),
+ .A1(\hkspi.fixed[2] ),
+ .S(_1445_),
+ .X(_1446_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4993_ (.A(_1446_),
+ .X(_0929_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4994_ (.A(_0261_),
+ .X(_1447_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4995_ (.A(_1447_),
+ .X(_0242_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _4996_ (.A0(_0044_),
+ .A1(\hkspi.fixed[1] ),
+ .S(_1445_),
+ .X(_1448_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4997_ (.A(_1448_),
+ .X(_0928_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _4998_ (.A(_1126_),
+ .X(_1449_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _4999_ (.A(_1449_),
+ .X(_1450_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5000_ (.A(_1450_),
+ .X(_0241_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5001_ (.A0(_0043_),
+ .A1(\hkspi.fixed[0] ),
+ .S(_1445_),
+ .X(_1451_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5002_ (.A(_1451_),
+ .X(_0927_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5003_ (.A(_1449_),
+ .X(_1452_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5004_ (.A(_1452_),
+ .X(_0240_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _5005_ (.A(\hkspi.count[1] ),
+ .B(_1417_),
+ .C(\hkspi.count[2] ),
+ .D(_0087_),
+ .X(_1453_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5006_ (.A(_1453_),
+ .X(_0089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5007_ (.A0(net58),
+ .A1(\hkspi.readmode ),
+ .S(_0089_),
+ .X(_1454_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5008_ (.A(_1454_),
+ .X(_0926_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5009_ (.A(_1449_),
+ .X(_1455_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5010_ (.A(_1455_),
+ .X(_0239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5011_ (.A(_0087_),
+ .B(_1138_),
+ .X(_1456_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _5012_ (.A1(\hkspi.state[0] ),
+ .A2(_0062_),
+ .A3(net58),
+ .B1(\hkspi.writemode ),
+ .B2(_1456_),
+ .X(_0925_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5013_ (.A(_1023_),
+ .B(_1181_),
+ .X(_1457_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _5014_ (.A(_1457_),
+ .X(_1458_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5015_ (.A(_1458_),
+ .Y(_1459_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5016_ (.A1(\gpio_configure[5][7] ),
+ .A2(_1458_),
+ .B1(\cdata[7] ),
+ .B2(_1459_),
+ .X(_0924_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5017_ (.A1(\gpio_configure[5][6] ),
+ .A2(_1458_),
+ .B1(\cdata[6] ),
+ .B2(_1459_),
+ .X(_0923_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5018_ (.A1(\gpio_configure[5][5] ),
+ .A2(_1458_),
+ .B1(\cdata[5] ),
+ .B2(_1459_),
+ .X(_0922_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5019_ (.A1(\gpio_configure[5][4] ),
+ .A2(_1458_),
+ .B1(net360),
+ .B2(_1459_),
+ .X(_0921_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5020_ (.A1(\gpio_configure[5][3] ),
+ .A2(_1458_),
+ .B1(net362),
+ .B2(_1459_),
+ .X(_0920_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5021_ (.A1(\gpio_configure[5][2] ),
+ .A2(_1458_),
+ .B1(net364),
+ .B2(_1459_),
+ .X(_0919_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5022_ (.A1(\gpio_configure[5][1] ),
+ .A2(_1458_),
+ .B1(net366),
+ .B2(_1459_),
+ .X(_0918_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5023_ (.A1(\gpio_configure[5][0] ),
+ .A2(_1458_),
+ .B1(net368),
+ .B2(_1459_),
+ .X(_0917_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5024_ (.A(_1043_),
+ .B(_1170_),
+ .X(_1460_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5025_ (.A(_1460_),
+ .X(_1461_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5026_ (.A(_1461_),
+ .Y(_1462_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5027_ (.A1(\gpio_configure[3][12] ),
+ .A2(_1461_),
+ .B1(net360),
+ .B2(_1462_),
+ .X(_0916_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5028_ (.A1(\gpio_configure[3][11] ),
+ .A2(_1461_),
+ .B1(\cdata[3] ),
+ .B2(_1462_),
+ .X(_0915_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5029_ (.A1(\gpio_configure[3][10] ),
+ .A2(_1461_),
+ .B1(\cdata[2] ),
+ .B2(_1462_),
+ .X(_0914_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5030_ (.A1(\gpio_configure[3][9] ),
+ .A2(_1461_),
+ .B1(\cdata[1] ),
+ .B2(_1462_),
+ .X(_0913_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5031_ (.A1(\gpio_configure[3][8] ),
+ .A2(_1461_),
+ .B1(\cdata[0] ),
+ .B2(_1462_),
+ .X(_0912_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5032_ (.A(_1449_),
+ .X(_1463_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5033_ (.A(_1463_),
+ .X(_0238_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5034_ (.A(\hkspi.state[4] ),
+ .Y(_1464_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _5035_ (.A(\hkspi.state[0] ),
+ .B(\hkspi.state[2] ),
+ .C(\hkspi.state[3] ),
+ .X(_1465_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5036_ (.A(_1465_),
+ .Y(_1466_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _5037_ (.A1(\hkspi.state[1] ),
+ .A2(_1464_),
+ .A3(_1466_),
+ .B1(\hkspi.pass_thru_user ),
+ .X(_0911_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5038_ (.A1(_4407_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[6] ),
+ .B2(_1087_),
+ .X(_0910_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5039_ (.A1(_4406_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[5] ),
+ .B2(_1087_),
+ .X(_0909_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5040_ (.A1(_4405_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[4] ),
+ .B2(_1087_),
+ .X(_0908_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5041_ (.A1(_4404_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[3] ),
+ .B2(_1087_),
+ .X(_0907_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5042_ (.A1(_4403_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[2] ),
+ .B2(_1087_),
+ .X(_0906_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5043_ (.A1(_4402_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[1] ),
+ .B2(_1087_),
+ .X(_0905_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5044_ (.A1(_4401_),
+ .A2(_1086_),
+ .B1(\wbbd_addr[0] ),
+ .B2(_1087_),
+ .X(_0904_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5045_ (.A(_1023_),
+ .B(_1253_),
+ .X(_1467_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5046_ (.A(_1467_),
+ .X(_1468_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5047_ (.A(_1468_),
+ .Y(_1469_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5048_ (.A1(\gpio_configure[2][7] ),
+ .A2(_1468_),
+ .B1(\cdata[7] ),
+ .B2(_1469_),
+ .X(_0903_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5049_ (.A1(\gpio_configure[2][6] ),
+ .A2(_1468_),
+ .B1(\cdata[6] ),
+ .B2(_1469_),
+ .X(_0902_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5050_ (.A1(\gpio_configure[2][5] ),
+ .A2(_1468_),
+ .B1(\cdata[5] ),
+ .B2(_1469_),
+ .X(_0901_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5051_ (.A1(\gpio_configure[2][4] ),
+ .A2(_1468_),
+ .B1(net360),
+ .B2(_1469_),
+ .X(_0900_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5052_ (.A1(\gpio_configure[2][3] ),
+ .A2(_1468_),
+ .B1(net362),
+ .B2(_1469_),
+ .X(_0899_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5053_ (.A1(\gpio_configure[2][2] ),
+ .A2(_1468_),
+ .B1(net364),
+ .B2(_1469_),
+ .X(_0898_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5054_ (.A1(\gpio_configure[2][1] ),
+ .A2(_1468_),
+ .B1(net366),
+ .B2(_1469_),
+ .X(_0897_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5055_ (.A1(\gpio_configure[2][0] ),
+ .A2(_1468_),
+ .B1(net368),
+ .B2(_1469_),
+ .X(_0896_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _5056_ (.A1(net199),
+ .A2(net202),
+ .B1(_1082_),
+ .Y(_1470_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _5057_ (.A1(net202),
+ .A2(net200),
+ .B1(_1084_),
+ .Y(_1471_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _5058_ (.A(net202),
+ .B(net198),
+ .X(_1472_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _5059_ (.A(net202),
+ .B(net197),
+ .X(_1473_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5060_ (.A(_1473_),
+ .X(_0088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _5061_ (.A1(_1083_),
+ .A2(_1472_),
+ .B1(_1081_),
+ .B2(_0088_),
+ .Y(_1474_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _5062_ (.A(_1470_),
+ .B(_1471_),
+ .C(_1474_),
+ .D(_1087_),
+ .X(_1475_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5063_ (.A(_1475_),
+ .X(_1476_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5064_ (.A0(_4400_),
+ .A1(\wbbd_data[7] ),
+ .S(_1476_),
+ .X(_1477_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5065_ (.A(_1477_),
+ .X(_0895_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5066_ (.A0(_4399_),
+ .A1(\wbbd_data[6] ),
+ .S(_1476_),
+ .X(_1478_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5067_ (.A(_1478_),
+ .X(_0894_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5068_ (.A0(_4398_),
+ .A1(\wbbd_data[5] ),
+ .S(_1476_),
+ .X(_1479_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5069_ (.A(_1479_),
+ .X(_0893_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5070_ (.A0(_4397_),
+ .A1(\wbbd_data[4] ),
+ .S(_1476_),
+ .X(_1480_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5071_ (.A(_1480_),
+ .X(_0892_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5072_ (.A0(_4396_),
+ .A1(\wbbd_data[3] ),
+ .S(_1476_),
+ .X(_1481_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5073_ (.A(_1481_),
+ .X(_0891_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5074_ (.A0(_4395_),
+ .A1(\wbbd_data[2] ),
+ .S(_1476_),
+ .X(_1482_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5075_ (.A(_1482_),
+ .X(_0890_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5076_ (.A0(_4394_),
+ .A1(\wbbd_data[1] ),
+ .S(_1476_),
+ .X(_1483_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5077_ (.A(_1483_),
+ .X(_0889_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5078_ (.A0(_4393_),
+ .A1(\wbbd_data[0] ),
+ .S(_1476_),
+ .X(_1484_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5079_ (.A(_1484_),
+ .X(_0888_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5080_ (.A(_1043_),
+ .B(_1157_),
+ .X(_1485_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5081_ (.A(_1485_),
+ .X(_1486_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5082_ (.A(_1486_),
+ .Y(_1487_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5083_ (.A1(\gpio_configure[2][12] ),
+ .A2(_1486_),
+ .B1(net359),
+ .B2(_1487_),
+ .X(_0887_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5084_ (.A1(\gpio_configure[2][11] ),
+ .A2(_1486_),
+ .B1(net361),
+ .B2(_1487_),
+ .X(_0886_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5085_ (.A1(\gpio_configure[2][10] ),
+ .A2(_1486_),
+ .B1(net363),
+ .B2(_1487_),
+ .X(_0885_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5086_ (.A1(\gpio_configure[2][9] ),
+ .A2(_1486_),
+ .B1(net366),
+ .B2(_1487_),
+ .X(_0884_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5087_ (.A1(\gpio_configure[2][8] ),
+ .A2(_1486_),
+ .B1(net367),
+ .B2(_1487_),
+ .X(_0883_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _5088_ (.A(_1021_),
+ .X(_1488_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5089_ (.A(_1488_),
+ .B(_1249_),
+ .X(_1489_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _5090_ (.A(_1489_),
+ .X(_1490_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5091_ (.A(_1490_),
+ .Y(_1491_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5092_ (.A1(\gpio_configure[1][7] ),
+ .A2(_1490_),
+ .B1(\cdata[7] ),
+ .B2(_1491_),
+ .X(_0882_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5093_ (.A1(\gpio_configure[1][6] ),
+ .A2(_1490_),
+ .B1(\cdata[6] ),
+ .B2(_1491_),
+ .X(_0881_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5094_ (.A1(\gpio_configure[1][5] ),
+ .A2(_1490_),
+ .B1(\cdata[5] ),
+ .B2(_1491_),
+ .X(_0880_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5095_ (.A1(\gpio_configure[1][4] ),
+ .A2(_1490_),
+ .B1(net360),
+ .B2(_1491_),
+ .X(_0879_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5096_ (.A1(\gpio_configure[1][3] ),
+ .A2(_1490_),
+ .B1(net362),
+ .B2(_1491_),
+ .X(_0878_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5097_ (.A1(\gpio_configure[1][2] ),
+ .A2(_1490_),
+ .B1(net364),
+ .B2(_1491_),
+ .X(_0877_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5098_ (.A1(\gpio_configure[1][1] ),
+ .A2(_1490_),
+ .B1(net366),
+ .B2(_1491_),
+ .X(_0876_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5099_ (.A1(\gpio_configure[1][0] ),
+ .A2(_1490_),
+ .B1(net368),
+ .B2(_1491_),
+ .X(_0875_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5100_ (.A(_1043_),
+ .B(_1302_),
+ .X(_1492_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5101_ (.A(_1492_),
+ .X(_1493_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5102_ (.A(_1493_),
+ .Y(_1494_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5103_ (.A1(\gpio_configure[1][12] ),
+ .A2(_1493_),
+ .B1(net359),
+ .B2(_1494_),
+ .X(_0874_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5104_ (.A1(\gpio_configure[1][11] ),
+ .A2(_1493_),
+ .B1(net361),
+ .B2(_1494_),
+ .X(_0873_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5105_ (.A1(\gpio_configure[1][10] ),
+ .A2(_1493_),
+ .B1(net363),
+ .B2(_1494_),
+ .X(_0872_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5106_ (.A1(\gpio_configure[1][9] ),
+ .A2(_1493_),
+ .B1(net365),
+ .B2(_1494_),
+ .X(_0871_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5107_ (.A1(\gpio_configure[1][8] ),
+ .A2(_1493_),
+ .B1(net367),
+ .B2(_1494_),
+ .X(_0870_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _5108_ (.A(\wbbd_state[2] ),
+ .B(\wbbd_state[3] ),
+ .C(\wbbd_state[4] ),
+ .D(\wbbd_state[1] ),
+ .X(_1495_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_2 _5109_ (.A1(wbbd_sck),
+ .A2(_1495_),
+ .B1(_1080_),
+ .C1(_1087_),
+ .X(_0869_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5110_ (.A(_1488_),
+ .B(_1353_),
+ .X(_1496_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5111_ (.A(_1496_),
+ .X(_1497_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5112_ (.A(_1497_),
+ .Y(_1498_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5113_ (.A1(\gpio_configure[0][7] ),
+ .A2(_1497_),
+ .B1(\cdata[7] ),
+ .B2(_1498_),
+ .X(_0868_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5114_ (.A1(\gpio_configure[0][6] ),
+ .A2(_1497_),
+ .B1(\cdata[6] ),
+ .B2(_1498_),
+ .X(_0867_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5115_ (.A1(\gpio_configure[0][5] ),
+ .A2(_1497_),
+ .B1(\cdata[5] ),
+ .B2(_1498_),
+ .X(_0866_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5116_ (.A1(\gpio_configure[0][4] ),
+ .A2(_1497_),
+ .B1(net359),
+ .B2(_1498_),
+ .X(_0865_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5117_ (.A1(\gpio_configure[0][3] ),
+ .A2(_1497_),
+ .B1(net361),
+ .B2(_1498_),
+ .X(_0864_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5118_ (.A1(\gpio_configure[0][2] ),
+ .A2(_1497_),
+ .B1(net363),
+ .B2(_1498_),
+ .X(_0863_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5119_ (.A1(\gpio_configure[0][1] ),
+ .A2(_1497_),
+ .B1(net365),
+ .B2(_1498_),
+ .X(_0862_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5120_ (.A1(\gpio_configure[0][0] ),
+ .A2(_1497_),
+ .B1(net367),
+ .B2(_1498_),
+ .X(_0861_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5121_ (.A(_1043_),
+ .B(_1275_),
+ .X(_1499_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5122_ (.A(_1499_),
+ .X(_1500_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5123_ (.A(_1500_),
+ .Y(_1501_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5124_ (.A1(\gpio_configure[0][12] ),
+ .A2(_1500_),
+ .B1(net359),
+ .B2(_1501_),
+ .X(_0860_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5125_ (.A1(\gpio_configure[0][11] ),
+ .A2(_1500_),
+ .B1(net361),
+ .B2(_1501_),
+ .X(_0859_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5126_ (.A1(\gpio_configure[0][10] ),
+ .A2(_1500_),
+ .B1(net363),
+ .B2(_1501_),
+ .X(_0858_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5127_ (.A1(\gpio_configure[0][9] ),
+ .A2(_1500_),
+ .B1(net365),
+ .B2(_1501_),
+ .X(_0857_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5128_ (.A1(\gpio_configure[0][8] ),
+ .A2(_1500_),
+ .B1(net367),
+ .B2(_1501_),
+ .X(_0856_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5129_ (.A(_1449_),
+ .X(_1502_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5130_ (.A(_1502_),
+ .X(_0237_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _5131_ (.A1(\hkspi.state[0] ),
+ .A2(_1423_),
+ .A3(\hkspi.pre_pass_thru_mgmt ),
+ .B1(\hkspi.pass_thru_mgmt_delay ),
+ .B2(_1424_),
+ .X(_0855_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_8 _5132_ (.A(_1125_),
+ .Y(_0079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _5133_ (.A(_1021_),
+ .B(_0079_),
+ .X(_1503_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5134_ (.A(_1177_),
+ .B(_1503_),
+ .X(_1504_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5135_ (.A(_1504_),
+ .X(_1505_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5136_ (.A(_1505_),
+ .Y(_1506_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5137_ (.A1(\mgmt_gpio_data_buf[7] ),
+ .A2(_1505_),
+ .B1(\cdata[7] ),
+ .B2(_1506_),
+ .X(_0854_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5138_ (.A1(\mgmt_gpio_data_buf[6] ),
+ .A2(_1505_),
+ .B1(\cdata[6] ),
+ .B2(_1506_),
+ .X(_0853_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5139_ (.A1(\mgmt_gpio_data_buf[5] ),
+ .A2(_1505_),
+ .B1(\cdata[5] ),
+ .B2(_1506_),
+ .X(_0852_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5140_ (.A1(\mgmt_gpio_data_buf[4] ),
+ .A2(_1505_),
+ .B1(net360),
+ .B2(_1506_),
+ .X(_0851_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5141_ (.A1(\mgmt_gpio_data_buf[3] ),
+ .A2(_1505_),
+ .B1(net362),
+ .B2(_1506_),
+ .X(_0850_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5142_ (.A1(\mgmt_gpio_data_buf[2] ),
+ .A2(_1505_),
+ .B1(net364),
+ .B2(_1506_),
+ .X(_0849_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5143_ (.A1(\mgmt_gpio_data_buf[1] ),
+ .A2(_1505_),
+ .B1(net366),
+ .B2(_1506_),
+ .X(_0848_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5144_ (.A1(\mgmt_gpio_data_buf[0] ),
+ .A2(_1505_),
+ .B1(net368),
+ .B2(_1506_),
+ .X(_0847_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5145_ (.A(_1218_),
+ .B(_1503_),
+ .X(_1507_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5146_ (.A(_1507_),
+ .X(_1508_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5147_ (.A(_1508_),
+ .Y(_1509_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5148_ (.A1(\mgmt_gpio_data_buf[15] ),
+ .A2(_1508_),
+ .B1(\cdata[7] ),
+ .B2(_1509_),
+ .X(_0846_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5149_ (.A1(\mgmt_gpio_data_buf[14] ),
+ .A2(_1508_),
+ .B1(\cdata[6] ),
+ .B2(_1509_),
+ .X(_0845_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5150_ (.A1(\mgmt_gpio_data_buf[13] ),
+ .A2(_1508_),
+ .B1(\cdata[5] ),
+ .B2(_1509_),
+ .X(_0844_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5151_ (.A1(\mgmt_gpio_data_buf[12] ),
+ .A2(_1508_),
+ .B1(net360),
+ .B2(_1509_),
+ .X(_0843_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5152_ (.A1(\mgmt_gpio_data_buf[11] ),
+ .A2(_1508_),
+ .B1(net362),
+ .B2(_1509_),
+ .X(_0842_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5153_ (.A1(\mgmt_gpio_data_buf[10] ),
+ .A2(_1508_),
+ .B1(net364),
+ .B2(_1509_),
+ .X(_0841_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5154_ (.A1(\mgmt_gpio_data_buf[9] ),
+ .A2(_1508_),
+ .B1(net366),
+ .B2(_1509_),
+ .X(_0840_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5155_ (.A1(\mgmt_gpio_data_buf[8] ),
+ .A2(_1508_),
+ .B1(net368),
+ .B2(_1509_),
+ .X(_0839_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5156_ (.A(_1235_),
+ .B(_1503_),
+ .X(_1510_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5157_ (.A(_1510_),
+ .X(_1511_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5158_ (.A(_1511_),
+ .Y(_1512_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5159_ (.A1(\mgmt_gpio_data_buf[23] ),
+ .A2(_1511_),
+ .B1(\cdata[7] ),
+ .B2(_1512_),
+ .X(_0838_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5160_ (.A1(\mgmt_gpio_data_buf[22] ),
+ .A2(_1511_),
+ .B1(\cdata[6] ),
+ .B2(_1512_),
+ .X(_0837_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5161_ (.A1(\mgmt_gpio_data_buf[21] ),
+ .A2(_1511_),
+ .B1(\cdata[5] ),
+ .B2(_1512_),
+ .X(_0836_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5162_ (.A1(\mgmt_gpio_data_buf[20] ),
+ .A2(_1511_),
+ .B1(net360),
+ .B2(_1512_),
+ .X(_0835_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5163_ (.A1(\mgmt_gpio_data_buf[19] ),
+ .A2(_1511_),
+ .B1(\cdata[3] ),
+ .B2(_1512_),
+ .X(_0834_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5164_ (.A1(\mgmt_gpio_data_buf[18] ),
+ .A2(_1511_),
+ .B1(\cdata[2] ),
+ .B2(_1512_),
+ .X(_0833_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5165_ (.A1(\mgmt_gpio_data_buf[17] ),
+ .A2(_1511_),
+ .B1(\cdata[1] ),
+ .B2(_1512_),
+ .X(_0832_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5166_ (.A1(\mgmt_gpio_data_buf[16] ),
+ .A2(_1511_),
+ .B1(net368),
+ .B2(_1512_),
+ .X(_0831_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5167_ (.A(_1488_),
+ .B(_1262_),
+ .X(_1513_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5168_ (.A(_1513_),
+ .X(_1514_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5169_ (.A(_1514_),
+ .Y(_1515_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5170_ (.A1(\mgmt_gpio_data[31] ),
+ .A2(_1514_),
+ .B1(\cdata[7] ),
+ .B2(_1515_),
+ .X(_0830_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5171_ (.A1(\mgmt_gpio_data[30] ),
+ .A2(_1514_),
+ .B1(\cdata[6] ),
+ .B2(_1515_),
+ .X(_0829_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5172_ (.A1(\mgmt_gpio_data[29] ),
+ .A2(_1514_),
+ .B1(\cdata[5] ),
+ .B2(_1515_),
+ .X(_0828_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5173_ (.A1(\mgmt_gpio_data[28] ),
+ .A2(_1514_),
+ .B1(net360),
+ .B2(_1515_),
+ .X(_0827_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5174_ (.A1(\mgmt_gpio_data[27] ),
+ .A2(_1514_),
+ .B1(\cdata[3] ),
+ .B2(_1515_),
+ .X(_0826_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5175_ (.A1(\mgmt_gpio_data[26] ),
+ .A2(_1514_),
+ .B1(\cdata[2] ),
+ .B2(_1515_),
+ .X(_0825_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5176_ (.A1(\mgmt_gpio_data[25] ),
+ .A2(_1514_),
+ .B1(\cdata[1] ),
+ .B2(_1515_),
+ .X(_0824_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5177_ (.A1(\mgmt_gpio_data[24] ),
+ .A2(_1514_),
+ .B1(net368),
+ .B2(_1515_),
+ .X(_0823_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5178_ (.A(_1023_),
+ .B(_1158_),
+ .X(_1516_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _5179_ (.A(_1516_),
+ .X(_1517_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5180_ (.A(_1517_),
+ .Y(_1518_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5181_ (.A1(\mgmt_gpio_data[37] ),
+ .A2(_1517_),
+ .B1(\cdata[5] ),
+ .B2(_1518_),
+ .X(_0822_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5182_ (.A1(\mgmt_gpio_data[36] ),
+ .A2(_1517_),
+ .B1(net360),
+ .B2(_1518_),
+ .X(_0821_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5183_ (.A1(\mgmt_gpio_data[35] ),
+ .A2(_1517_),
+ .B1(\cdata[3] ),
+ .B2(_1518_),
+ .X(_0820_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5184_ (.A1(\mgmt_gpio_data[34] ),
+ .A2(_1517_),
+ .B1(\cdata[2] ),
+ .B2(_1518_),
+ .X(_0819_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5185_ (.A1(\mgmt_gpio_data[33] ),
+ .A2(_1517_),
+ .B1(\cdata[1] ),
+ .B2(_1518_),
+ .X(_0818_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5186_ (.A1(\mgmt_gpio_data[32] ),
+ .A2(_1517_),
+ .B1(net368),
+ .B2(_1518_),
+ .X(_0817_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5187_ (.A(\wbbd_state[0] ),
+ .Y(_1519_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _5188_ (.A1(wbbd_busy),
+ .A2(_1519_),
+ .B1(_1495_),
+ .C1(_1088_),
+ .X(_0816_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5189_ (.A(_1449_),
+ .X(_1520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5190_ (.A(_1520_),
+ .X(_0236_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _5191_ (.A1(\hkspi.state[4] ),
+ .A2(_1466_),
+ .B1(\hkspi.pass_thru_mgmt ),
+ .X(_0815_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_4 _5192_ (.A1(_1262_),
+ .A2(_1177_),
+ .B1(_1043_),
+ .C1(_0086_),
+ .X(_1521_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5193_ (.A(_1521_),
+ .Y(_1522_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5194_ (.A1(\mgmt_gpio_data[7] ),
+ .A2(_1522_),
+ .B1(_0199_),
+ .B2(_1521_),
+ .X(_0814_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5195_ (.A1(\mgmt_gpio_data[6] ),
+ .A2(_1522_),
+ .B1(_0198_),
+ .B2(_1521_),
+ .X(_0813_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5196_ (.A1(\mgmt_gpio_data[5] ),
+ .A2(_1522_),
+ .B1(_0197_),
+ .B2(_1521_),
+ .X(_0812_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5197_ (.A1(\mgmt_gpio_data[4] ),
+ .A2(_1522_),
+ .B1(_0196_),
+ .B2(_1521_),
+ .X(_0811_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5198_ (.A1(\mgmt_gpio_data[3] ),
+ .A2(_1522_),
+ .B1(_0195_),
+ .B2(_1521_),
+ .X(_0810_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5199_ (.A1(\mgmt_gpio_data[2] ),
+ .A2(_1522_),
+ .B1(_0194_),
+ .B2(_1521_),
+ .X(_0809_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5200_ (.A1(\mgmt_gpio_data[1] ),
+ .A2(_1522_),
+ .B1(_0193_),
+ .B2(_1521_),
+ .X(_0808_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5201_ (.A1(\mgmt_gpio_data[0] ),
+ .A2(_1522_),
+ .B1(_0192_),
+ .B2(_1521_),
+ .X(_0807_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_4 _5202_ (.A1(_1218_),
+ .A2(_1262_),
+ .B1(_1043_),
+ .C1(_0084_),
+ .X(_1523_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5203_ (.A(_1523_),
+ .Y(_1524_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5204_ (.A1(\mgmt_gpio_data[15] ),
+ .A2(_1524_),
+ .B1(_0207_),
+ .B2(_1523_),
+ .X(_0806_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5205_ (.A1(\mgmt_gpio_data[14] ),
+ .A2(_1524_),
+ .B1(_0206_),
+ .B2(_1523_),
+ .X(_0805_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5206_ (.A1(\mgmt_gpio_data[13] ),
+ .A2(_1524_),
+ .B1(_0205_),
+ .B2(_1523_),
+ .X(_0804_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5207_ (.A1(\mgmt_gpio_data[12] ),
+ .A2(_1524_),
+ .B1(_0204_),
+ .B2(_1523_),
+ .X(_0803_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5208_ (.A1(\mgmt_gpio_data[11] ),
+ .A2(_1524_),
+ .B1(_0203_),
+ .B2(_1523_),
+ .X(_0802_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5209_ (.A1(\mgmt_gpio_data[10] ),
+ .A2(_1524_),
+ .B1(_0202_),
+ .B2(_1523_),
+ .X(_0801_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5210_ (.A1(\mgmt_gpio_data[9] ),
+ .A2(_1524_),
+ .B1(_0201_),
+ .B2(_1523_),
+ .X(_0800_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5211_ (.A1(\mgmt_gpio_data[8] ),
+ .A2(_1524_),
+ .B1(_0200_),
+ .B2(_1523_),
+ .X(_0799_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5212_ (.A(_1449_),
+ .X(_1525_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5213_ (.A(_1525_),
+ .X(_0235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _5214_ (.A(_0154_),
+ .B(_1466_),
+ .Y(_1526_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _5215_ (.A(\hkspi.state[0] ),
+ .B(_1419_),
+ .Y(_1527_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5216_ (.A1(\hkspi.rdstb ),
+ .A2(_1526_),
+ .B1(_1466_),
+ .B2(_1527_),
+ .X(_0798_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_4 _5217_ (.A1(_1235_),
+ .A2(_1262_),
+ .B1(_1043_),
+ .C1(_0082_),
+ .X(_1528_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5218_ (.A(_1528_),
+ .Y(_1529_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5219_ (.A1(\mgmt_gpio_data[23] ),
+ .A2(_1529_),
+ .B1(_0215_),
+ .B2(_1528_),
+ .X(_0797_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5220_ (.A1(\mgmt_gpio_data[22] ),
+ .A2(_1529_),
+ .B1(_0214_),
+ .B2(_1528_),
+ .X(_0796_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5221_ (.A1(\mgmt_gpio_data[21] ),
+ .A2(_1529_),
+ .B1(_0213_),
+ .B2(_1528_),
+ .X(_0795_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5222_ (.A1(\mgmt_gpio_data[20] ),
+ .A2(_1529_),
+ .B1(_0212_),
+ .B2(_1528_),
+ .X(_0794_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5223_ (.A1(\mgmt_gpio_data[19] ),
+ .A2(_1529_),
+ .B1(_0211_),
+ .B2(_1528_),
+ .X(_0793_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5224_ (.A1(\mgmt_gpio_data[18] ),
+ .A2(_1529_),
+ .B1(_0210_),
+ .B2(_1528_),
+ .X(_0792_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5225_ (.A1(\mgmt_gpio_data[17] ),
+ .A2(_1529_),
+ .B1(_0209_),
+ .B2(_1528_),
+ .X(_0791_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5226_ (.A1(\mgmt_gpio_data[16] ),
+ .A2(_1529_),
+ .B1(_0208_),
+ .B2(_1528_),
+ .X(_0790_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5227_ (.A(_1043_),
+ .B(_1304_),
+ .X(_1530_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5228_ (.A0(net365),
+ .A1(irq_2_inputsrc),
+ .S(_1530_),
+ .X(_1531_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5229_ (.A(_1531_),
+ .X(_0789_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _5230_ (.A0(net367),
+ .A1(irq_1_inputsrc),
+ .S(_1530_),
+ .X(_1532_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5231_ (.A(_1532_),
+ .X(_0788_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5232_ (.A(_1043_),
+ .B(_1315_),
+ .X(_1533_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5233_ (.A(_1533_),
+ .X(_1534_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5234_ (.A(_1534_),
+ .Y(_1535_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5235_ (.A1(\gpio_configure[27][12] ),
+ .A2(_1534_),
+ .B1(net359),
+ .B2(_1535_),
+ .X(_0787_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5236_ (.A1(\gpio_configure[27][11] ),
+ .A2(_1534_),
+ .B1(net361),
+ .B2(_1535_),
+ .X(_0786_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5237_ (.A1(\gpio_configure[27][10] ),
+ .A2(_1534_),
+ .B1(net363),
+ .B2(_1535_),
+ .X(_0785_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5238_ (.A1(\gpio_configure[27][9] ),
+ .A2(_1534_),
+ .B1(net365),
+ .B2(_1535_),
+ .X(_0784_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5239_ (.A1(\gpio_configure[27][8] ),
+ .A2(_1534_),
+ .B1(net367),
+ .B2(_1535_),
+ .X(_0783_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5240_ (.A(_1488_),
+ .B(_1273_),
+ .X(_1536_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5241_ (.A(_1536_),
+ .X(_1537_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5242_ (.A(_1537_),
+ .Y(_1538_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5243_ (.A1(\gpio_configure[27][7] ),
+ .A2(_1537_),
+ .B1(\cdata[7] ),
+ .B2(_1538_),
+ .X(_0782_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5244_ (.A1(\gpio_configure[27][6] ),
+ .A2(_1537_),
+ .B1(\cdata[6] ),
+ .B2(_1538_),
+ .X(_0781_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5245_ (.A1(\gpio_configure[27][5] ),
+ .A2(_1537_),
+ .B1(\cdata[5] ),
+ .B2(_1538_),
+ .X(_0780_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5246_ (.A1(\gpio_configure[27][4] ),
+ .A2(_1537_),
+ .B1(net359),
+ .B2(_1538_),
+ .X(_0779_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5247_ (.A1(\gpio_configure[27][3] ),
+ .A2(_1537_),
+ .B1(net361),
+ .B2(_1538_),
+ .X(_0778_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5248_ (.A1(\gpio_configure[27][2] ),
+ .A2(_1537_),
+ .B1(net363),
+ .B2(_1538_),
+ .X(_0777_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5249_ (.A1(\gpio_configure[27][1] ),
+ .A2(_1537_),
+ .B1(net365),
+ .B2(_1538_),
+ .X(_0776_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5250_ (.A1(\gpio_configure[27][0] ),
+ .A2(_1537_),
+ .B1(net367),
+ .B2(_1538_),
+ .X(_0775_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5251_ (.A(_1043_),
+ .B(_1288_),
+ .X(_1539_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5252_ (.A(_1539_),
+ .X(_1540_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5253_ (.A(_1540_),
+ .Y(_1541_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5254_ (.A1(\gpio_configure[25][12] ),
+ .A2(_1540_),
+ .B1(net359),
+ .B2(_1541_),
+ .X(_0774_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5255_ (.A1(\gpio_configure[25][11] ),
+ .A2(_1540_),
+ .B1(net361),
+ .B2(_1541_),
+ .X(_0773_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5256_ (.A1(\gpio_configure[25][10] ),
+ .A2(_1540_),
+ .B1(net363),
+ .B2(_1541_),
+ .X(_0772_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5257_ (.A1(\gpio_configure[25][9] ),
+ .A2(_1540_),
+ .B1(net365),
+ .B2(_1541_),
+ .X(_0771_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5258_ (.A1(\gpio_configure[25][8] ),
+ .A2(_1540_),
+ .B1(net367),
+ .B2(_1541_),
+ .X(_0770_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5259_ (.A(_1043_),
+ .B(_1361_),
+ .X(_1542_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5260_ (.A(_1542_),
+ .X(_1543_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5261_ (.A(_1543_),
+ .Y(_1544_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5262_ (.A1(\gpio_configure[28][12] ),
+ .A2(_1543_),
+ .B1(net359),
+ .B2(_1544_),
+ .X(_0769_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5263_ (.A1(\gpio_configure[28][11] ),
+ .A2(_1543_),
+ .B1(net361),
+ .B2(_1544_),
+ .X(_0768_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5264_ (.A1(\gpio_configure[28][10] ),
+ .A2(_1543_),
+ .B1(net363),
+ .B2(_1544_),
+ .X(_0767_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5265_ (.A1(\gpio_configure[28][9] ),
+ .A2(_1543_),
+ .B1(net365),
+ .B2(_1544_),
+ .X(_0766_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5266_ (.A1(\gpio_configure[28][8] ),
+ .A2(_1543_),
+ .B1(net367),
+ .B2(_1544_),
+ .X(_0765_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5267_ (.A(_1488_),
+ .B(_1325_),
+ .X(_1545_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _5268_ (.A(_1545_),
+ .X(_1546_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5269_ (.A(_1546_),
+ .Y(_1547_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5270_ (.A1(\gpio_configure[24][7] ),
+ .A2(_1546_),
+ .B1(\cdata[7] ),
+ .B2(_1547_),
+ .X(_0764_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5271_ (.A1(\gpio_configure[24][6] ),
+ .A2(_1546_),
+ .B1(\cdata[6] ),
+ .B2(_1547_),
+ .X(_0763_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5272_ (.A1(\gpio_configure[24][5] ),
+ .A2(_1546_),
+ .B1(\cdata[5] ),
+ .B2(_1547_),
+ .X(_0762_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5273_ (.A1(\gpio_configure[24][4] ),
+ .A2(_1546_),
+ .B1(\cdata[4] ),
+ .B2(_1547_),
+ .X(_0761_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5274_ (.A1(\gpio_configure[24][3] ),
+ .A2(_1546_),
+ .B1(net362),
+ .B2(_1547_),
+ .X(_0760_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5275_ (.A1(\gpio_configure[24][2] ),
+ .A2(_1546_),
+ .B1(\cdata[2] ),
+ .B2(_1547_),
+ .X(_0759_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5276_ (.A1(\gpio_configure[24][1] ),
+ .A2(_1546_),
+ .B1(net366),
+ .B2(_1547_),
+ .X(_0758_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5277_ (.A1(\gpio_configure[24][0] ),
+ .A2(_1546_),
+ .B1(\cdata[0] ),
+ .B2(_1547_),
+ .X(_0757_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5278_ (.A(_1488_),
+ .B(_1388_),
+ .X(_1548_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5279_ (.A(_1548_),
+ .X(_1549_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5280_ (.A(_1549_),
+ .Y(_1550_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5281_ (.A1(\gpio_configure[28][7] ),
+ .A2(_1549_),
+ .B1(\cdata[7] ),
+ .B2(_1550_),
+ .X(_0756_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5282_ (.A1(\gpio_configure[28][6] ),
+ .A2(_1549_),
+ .B1(\cdata[6] ),
+ .B2(_1550_),
+ .X(_0755_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5283_ (.A1(\gpio_configure[28][5] ),
+ .A2(_1549_),
+ .B1(\cdata[5] ),
+ .B2(_1550_),
+ .X(_0754_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5284_ (.A1(\gpio_configure[28][4] ),
+ .A2(_1549_),
+ .B1(net360),
+ .B2(_1550_),
+ .X(_0753_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5285_ (.A1(\gpio_configure[28][3] ),
+ .A2(_1549_),
+ .B1(\cdata[3] ),
+ .B2(_1550_),
+ .X(_0752_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5286_ (.A1(\gpio_configure[28][2] ),
+ .A2(_1549_),
+ .B1(net364),
+ .B2(_1550_),
+ .X(_0751_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5287_ (.A1(\gpio_configure[28][1] ),
+ .A2(_1549_),
+ .B1(\cdata[1] ),
+ .B2(_1550_),
+ .X(_0750_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5288_ (.A1(\gpio_configure[28][0] ),
+ .A2(_1549_),
+ .B1(net368),
+ .B2(_1550_),
+ .X(_0749_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _5289_ (.A(_1022_),
+ .X(_1551_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5290_ (.A(_1551_),
+ .B(_1282_),
+ .X(_1552_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5291_ (.A(_1552_),
+ .X(_1553_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5292_ (.A(_1553_),
+ .Y(_1554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5293_ (.A1(\gpio_configure[24][12] ),
+ .A2(_1553_),
+ .B1(net359),
+ .B2(_1554_),
+ .X(_0748_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5294_ (.A1(\gpio_configure[24][11] ),
+ .A2(_1553_),
+ .B1(net361),
+ .B2(_1554_),
+ .X(_0747_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5295_ (.A1(\gpio_configure[24][10] ),
+ .A2(_1553_),
+ .B1(net363),
+ .B2(_1554_),
+ .X(_0746_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5296_ (.A1(\gpio_configure[24][9] ),
+ .A2(_1553_),
+ .B1(net365),
+ .B2(_1554_),
+ .X(_0745_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5297_ (.A1(\gpio_configure[24][8] ),
+ .A2(_1553_),
+ .B1(net367),
+ .B2(_1554_),
+ .X(_0744_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5298_ (.A(_1551_),
+ .B(_1366_),
+ .X(_1555_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5299_ (.A(_1555_),
+ .X(_1556_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5300_ (.A(_1556_),
+ .Y(_1557_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5301_ (.A1(\gpio_configure[29][12] ),
+ .A2(_1556_),
+ .B1(net359),
+ .B2(_1557_),
+ .X(_0743_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5302_ (.A1(\gpio_configure[29][11] ),
+ .A2(_1556_),
+ .B1(net361),
+ .B2(_1557_),
+ .X(_0742_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5303_ (.A1(\gpio_configure[29][10] ),
+ .A2(_1556_),
+ .B1(net363),
+ .B2(_1557_),
+ .X(_0741_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5304_ (.A1(\gpio_configure[29][9] ),
+ .A2(_1556_),
+ .B1(net365),
+ .B2(_1557_),
+ .X(_0740_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5305_ (.A1(\gpio_configure[29][8] ),
+ .A2(_1556_),
+ .B1(net367),
+ .B2(_1557_),
+ .X(_0739_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5306_ (.A(_1488_),
+ .B(_1404_),
+ .X(_1558_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5307_ (.A(_1558_),
+ .X(_1559_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5308_ (.A(_1559_),
+ .Y(_1560_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5309_ (.A1(\gpio_configure[23][7] ),
+ .A2(_1559_),
+ .B1(\cdata[7] ),
+ .B2(_1560_),
+ .X(_0738_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5310_ (.A1(\gpio_configure[23][6] ),
+ .A2(_1559_),
+ .B1(\cdata[6] ),
+ .B2(_1560_),
+ .X(_0737_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5311_ (.A1(\gpio_configure[23][5] ),
+ .A2(_1559_),
+ .B1(\cdata[5] ),
+ .B2(_1560_),
+ .X(_0736_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5312_ (.A1(\gpio_configure[23][4] ),
+ .A2(_1559_),
+ .B1(net360),
+ .B2(_1560_),
+ .X(_0735_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5313_ (.A1(\gpio_configure[23][3] ),
+ .A2(_1559_),
+ .B1(\cdata[3] ),
+ .B2(_1560_),
+ .X(_0734_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5314_ (.A1(\gpio_configure[23][2] ),
+ .A2(_1559_),
+ .B1(net364),
+ .B2(_1560_),
+ .X(_0733_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5315_ (.A1(\gpio_configure[23][1] ),
+ .A2(_1559_),
+ .B1(\cdata[1] ),
+ .B2(_1560_),
+ .X(_0732_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5316_ (.A1(\gpio_configure[23][0] ),
+ .A2(_1559_),
+ .B1(net368),
+ .B2(_1560_),
+ .X(_0731_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5317_ (.A(_1488_),
+ .B(_1334_),
+ .X(_1561_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5318_ (.A(_1561_),
+ .X(_1562_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5319_ (.A(_1562_),
+ .Y(_1563_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5320_ (.A1(\gpio_configure[29][7] ),
+ .A2(_1562_),
+ .B1(\cdata[7] ),
+ .B2(_1563_),
+ .X(_0730_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5321_ (.A1(\gpio_configure[29][6] ),
+ .A2(_1562_),
+ .B1(\cdata[6] ),
+ .B2(_1563_),
+ .X(_0729_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5322_ (.A1(\gpio_configure[29][5] ),
+ .A2(_1562_),
+ .B1(\cdata[5] ),
+ .B2(_1563_),
+ .X(_0728_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5323_ (.A1(\gpio_configure[29][4] ),
+ .A2(_1562_),
+ .B1(net360),
+ .B2(_1563_),
+ .X(_0727_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5324_ (.A1(\gpio_configure[29][3] ),
+ .A2(_1562_),
+ .B1(net362),
+ .B2(_1563_),
+ .X(_0726_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5325_ (.A1(\gpio_configure[29][2] ),
+ .A2(_1562_),
+ .B1(\cdata[2] ),
+ .B2(_1563_),
+ .X(_0725_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5326_ (.A1(\gpio_configure[29][1] ),
+ .A2(_1562_),
+ .B1(net366),
+ .B2(_1563_),
+ .X(_0724_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5327_ (.A1(\gpio_configure[29][0] ),
+ .A2(_1562_),
+ .B1(\cdata[0] ),
+ .B2(_1563_),
+ .X(_0723_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5328_ (.A(_1551_),
+ .B(_1408_),
+ .X(_1564_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5329_ (.A(_1564_),
+ .X(_1565_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5330_ (.A(_1565_),
+ .Y(_1566_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5331_ (.A1(\gpio_configure[23][12] ),
+ .A2(_1565_),
+ .B1(net359),
+ .B2(_1566_),
+ .X(_0722_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5332_ (.A1(\gpio_configure[23][11] ),
+ .A2(_1565_),
+ .B1(net361),
+ .B2(_1566_),
+ .X(_0721_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5333_ (.A1(\gpio_configure[23][10] ),
+ .A2(_1565_),
+ .B1(net363),
+ .B2(_1566_),
+ .X(_0720_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5334_ (.A1(\gpio_configure[23][9] ),
+ .A2(_1565_),
+ .B1(net365),
+ .B2(_1566_),
+ .X(_0719_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5335_ (.A1(\gpio_configure[23][8] ),
+ .A2(_1565_),
+ .B1(net367),
+ .B2(_1566_),
+ .X(_0718_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5336_ (.A(_1551_),
+ .B(_1344_),
+ .X(_1567_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5337_ (.A(_1567_),
+ .X(_1568_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5338_ (.A(_1568_),
+ .Y(_1569_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5339_ (.A1(\gpio_configure[30][12] ),
+ .A2(_1568_),
+ .B1(net359),
+ .B2(_1569_),
+ .X(_0717_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5340_ (.A1(\gpio_configure[30][11] ),
+ .A2(_1568_),
+ .B1(net361),
+ .B2(_1569_),
+ .X(_0716_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5341_ (.A1(\gpio_configure[30][10] ),
+ .A2(_1568_),
+ .B1(net363),
+ .B2(_1569_),
+ .X(_0715_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5342_ (.A1(\gpio_configure[30][9] ),
+ .A2(_1568_),
+ .B1(net365),
+ .B2(_1569_),
+ .X(_0714_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5343_ (.A1(\gpio_configure[30][8] ),
+ .A2(_1568_),
+ .B1(net367),
+ .B2(_1569_),
+ .X(_0713_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5344_ (.A(_1488_),
+ .B(_1375_),
+ .X(_1570_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5345_ (.A(_1570_),
+ .X(_1571_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5346_ (.A(_1571_),
+ .Y(_1572_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5347_ (.A1(\gpio_configure[22][7] ),
+ .A2(_1571_),
+ .B1(\cdata[7] ),
+ .B2(_1572_),
+ .X(_0712_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5348_ (.A1(\gpio_configure[22][6] ),
+ .A2(_1571_),
+ .B1(\cdata[6] ),
+ .B2(_1572_),
+ .X(_0711_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5349_ (.A1(\gpio_configure[22][5] ),
+ .A2(_1571_),
+ .B1(\cdata[5] ),
+ .B2(_1572_),
+ .X(_0710_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5350_ (.A1(\gpio_configure[22][4] ),
+ .A2(_1571_),
+ .B1(net360),
+ .B2(_1572_),
+ .X(_0709_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5351_ (.A1(\gpio_configure[22][3] ),
+ .A2(_1571_),
+ .B1(\cdata[3] ),
+ .B2(_1572_),
+ .X(_0708_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5352_ (.A1(\gpio_configure[22][2] ),
+ .A2(_1571_),
+ .B1(\cdata[2] ),
+ .B2(_1572_),
+ .X(_0707_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5353_ (.A1(\gpio_configure[22][1] ),
+ .A2(_1571_),
+ .B1(\cdata[1] ),
+ .B2(_1572_),
+ .X(_0706_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5354_ (.A1(\gpio_configure[22][0] ),
+ .A2(_1571_),
+ .B1(net368),
+ .B2(_1572_),
+ .X(_0705_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5355_ (.A(_1488_),
+ .B(_1329_),
+ .X(_1573_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5356_ (.A(_1573_),
+ .X(_1574_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5357_ (.A(_1574_),
+ .Y(_1575_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5358_ (.A1(\gpio_configure[30][7] ),
+ .A2(_1574_),
+ .B1(\cdata[7] ),
+ .B2(_1575_),
+ .X(_0704_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5359_ (.A1(\gpio_configure[30][6] ),
+ .A2(_1574_),
+ .B1(\cdata[6] ),
+ .B2(_1575_),
+ .X(_0703_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5360_ (.A1(\gpio_configure[30][5] ),
+ .A2(_1574_),
+ .B1(\cdata[5] ),
+ .B2(_1575_),
+ .X(_0702_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5361_ (.A1(\gpio_configure[30][4] ),
+ .A2(_1574_),
+ .B1(net360),
+ .B2(_1575_),
+ .X(_0701_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5362_ (.A1(\gpio_configure[30][3] ),
+ .A2(_1574_),
+ .B1(\cdata[3] ),
+ .B2(_1575_),
+ .X(_0700_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5363_ (.A1(\gpio_configure[30][2] ),
+ .A2(_1574_),
+ .B1(\cdata[2] ),
+ .B2(_1575_),
+ .X(_0699_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5364_ (.A1(\gpio_configure[30][1] ),
+ .A2(_1574_),
+ .B1(\cdata[1] ),
+ .B2(_1575_),
+ .X(_0698_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5365_ (.A1(\gpio_configure[30][0] ),
+ .A2(_1574_),
+ .B1(\cdata[0] ),
+ .B2(_1575_),
+ .X(_0697_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5366_ (.A(_1551_),
+ .B(_1402_),
+ .X(_1576_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5367_ (.A(_1576_),
+ .X(_1577_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5368_ (.A(_1577_),
+ .Y(_1578_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5369_ (.A1(\gpio_configure[22][12] ),
+ .A2(_1577_),
+ .B1(net359),
+ .B2(_1578_),
+ .X(_0696_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5370_ (.A1(\gpio_configure[22][11] ),
+ .A2(_1577_),
+ .B1(net361),
+ .B2(_1578_),
+ .X(_0695_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5371_ (.A1(\gpio_configure[22][10] ),
+ .A2(_1577_),
+ .B1(net363),
+ .B2(_1578_),
+ .X(_0694_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5372_ (.A1(\gpio_configure[22][9] ),
+ .A2(_1577_),
+ .B1(net365),
+ .B2(_1578_),
+ .X(_0693_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5373_ (.A1(\gpio_configure[22][8] ),
+ .A2(_1577_),
+ .B1(net367),
+ .B2(_1578_),
+ .X(_0692_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5374_ (.A(_1551_),
+ .B(_1337_),
+ .X(_1579_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5375_ (.A(_1579_),
+ .X(_1580_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5376_ (.A(_1580_),
+ .Y(_1581_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5377_ (.A1(\gpio_configure[31][12] ),
+ .A2(_1580_),
+ .B1(\cdata[4] ),
+ .B2(_1581_),
+ .X(_0691_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5378_ (.A1(\gpio_configure[31][11] ),
+ .A2(_1580_),
+ .B1(\cdata[3] ),
+ .B2(_1581_),
+ .X(_0690_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5379_ (.A1(\gpio_configure[31][10] ),
+ .A2(_1580_),
+ .B1(\cdata[2] ),
+ .B2(_1581_),
+ .X(_0689_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5380_ (.A1(\gpio_configure[31][9] ),
+ .A2(_1580_),
+ .B1(net366),
+ .B2(_1581_),
+ .X(_0688_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5381_ (.A1(\gpio_configure[31][8] ),
+ .A2(_1580_),
+ .B1(\cdata[0] ),
+ .B2(_1581_),
+ .X(_0687_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5382_ (.A(_1488_),
+ .B(_1394_),
+ .X(_1582_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5383_ (.A(_1582_),
+ .X(_1583_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5384_ (.A(_1583_),
+ .Y(_1584_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5385_ (.A1(\gpio_configure[21][7] ),
+ .A2(_1583_),
+ .B1(\cdata[7] ),
+ .B2(_1584_),
+ .X(_0686_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5386_ (.A1(\gpio_configure[21][6] ),
+ .A2(_1583_),
+ .B1(\cdata[6] ),
+ .B2(_1584_),
+ .X(_0685_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5387_ (.A1(\gpio_configure[21][5] ),
+ .A2(_1583_),
+ .B1(\cdata[5] ),
+ .B2(_1584_),
+ .X(_0684_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5388_ (.A1(\gpio_configure[21][4] ),
+ .A2(_1583_),
+ .B1(net360),
+ .B2(_1584_),
+ .X(_0683_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5389_ (.A1(\gpio_configure[21][3] ),
+ .A2(_1583_),
+ .B1(\cdata[3] ),
+ .B2(_1584_),
+ .X(_0682_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5390_ (.A1(\gpio_configure[21][2] ),
+ .A2(_1583_),
+ .B1(\cdata[2] ),
+ .B2(_1584_),
+ .X(_0681_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5391_ (.A1(\gpio_configure[21][1] ),
+ .A2(_1583_),
+ .B1(\cdata[1] ),
+ .B2(_1584_),
+ .X(_0680_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5392_ (.A1(\gpio_configure[21][0] ),
+ .A2(_1583_),
+ .B1(net368),
+ .B2(_1584_),
+ .X(_0679_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5393_ (.A(_1488_),
+ .B(_1295_),
+ .X(_1585_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5394_ (.A(_1585_),
+ .X(_1586_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5395_ (.A(_1586_),
+ .Y(_1587_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5396_ (.A1(\gpio_configure[31][7] ),
+ .A2(_1586_),
+ .B1(\cdata[7] ),
+ .B2(_1587_),
+ .X(_0678_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5397_ (.A1(\gpio_configure[31][6] ),
+ .A2(_1586_),
+ .B1(\cdata[6] ),
+ .B2(_1587_),
+ .X(_0677_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5398_ (.A1(\gpio_configure[31][5] ),
+ .A2(_1586_),
+ .B1(\cdata[5] ),
+ .B2(_1587_),
+ .X(_0676_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5399_ (.A1(\gpio_configure[31][4] ),
+ .A2(_1586_),
+ .B1(net359),
+ .B2(_1587_),
+ .X(_0675_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5400_ (.A1(\gpio_configure[31][3] ),
+ .A2(_1586_),
+ .B1(net361),
+ .B2(_1587_),
+ .X(_0674_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5401_ (.A1(\gpio_configure[31][2] ),
+ .A2(_1586_),
+ .B1(net363),
+ .B2(_1587_),
+ .X(_0673_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5402_ (.A1(\gpio_configure[31][1] ),
+ .A2(_1586_),
+ .B1(net366),
+ .B2(_1587_),
+ .X(_0672_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5403_ (.A1(\gpio_configure[31][0] ),
+ .A2(_1586_),
+ .B1(net368),
+ .B2(_1587_),
+ .X(_0671_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5404_ (.A(_1551_),
+ .B(_1377_),
+ .X(_1588_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5405_ (.A(_1588_),
+ .X(_1589_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5406_ (.A(_1589_),
+ .Y(_1590_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5407_ (.A1(\gpio_configure[21][12] ),
+ .A2(_1589_),
+ .B1(net359),
+ .B2(_1590_),
+ .X(_0670_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5408_ (.A1(\gpio_configure[21][11] ),
+ .A2(_1589_),
+ .B1(net361),
+ .B2(_1590_),
+ .X(_0669_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5409_ (.A1(\gpio_configure[21][10] ),
+ .A2(_1589_),
+ .B1(net363),
+ .B2(_1590_),
+ .X(_0668_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5410_ (.A1(\gpio_configure[21][9] ),
+ .A2(_1589_),
+ .B1(net365),
+ .B2(_1590_),
+ .X(_0667_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5411_ (.A1(\gpio_configure[21][8] ),
+ .A2(_1589_),
+ .B1(net367),
+ .B2(_1590_),
+ .X(_0666_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5412_ (.A(_1551_),
+ .B(_1380_),
+ .X(_1591_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5413_ (.A(_1591_),
+ .X(_1592_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5414_ (.A(_1592_),
+ .Y(_1593_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5415_ (.A1(\gpio_configure[32][12] ),
+ .A2(_1592_),
+ .B1(\cdata[4] ),
+ .B2(_1593_),
+ .X(_0665_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5416_ (.A1(\gpio_configure[32][11] ),
+ .A2(_1592_),
+ .B1(net361),
+ .B2(_1593_),
+ .X(_0664_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5417_ (.A1(\gpio_configure[32][10] ),
+ .A2(_1592_),
+ .B1(net363),
+ .B2(_1593_),
+ .X(_0663_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5418_ (.A1(\gpio_configure[32][9] ),
+ .A2(_1592_),
+ .B1(net365),
+ .B2(_1593_),
+ .X(_0662_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5419_ (.A1(\gpio_configure[32][8] ),
+ .A2(_1592_),
+ .B1(net367),
+ .B2(_1593_),
+ .X(_0661_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5420_ (.A(_1488_),
+ .B(_1392_),
+ .X(_1594_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5421_ (.A(_1594_),
+ .X(_1595_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5422_ (.A(_1595_),
+ .Y(_1596_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5423_ (.A1(\gpio_configure[20][7] ),
+ .A2(_1595_),
+ .B1(\cdata[7] ),
+ .B2(_1596_),
+ .X(_0660_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5424_ (.A1(\gpio_configure[20][6] ),
+ .A2(_1595_),
+ .B1(\cdata[6] ),
+ .B2(_1596_),
+ .X(_0659_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5425_ (.A1(\gpio_configure[20][5] ),
+ .A2(_1595_),
+ .B1(\cdata[5] ),
+ .B2(_1596_),
+ .X(_0658_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5426_ (.A1(\gpio_configure[20][4] ),
+ .A2(_1595_),
+ .B1(net360),
+ .B2(_1596_),
+ .X(_0657_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5427_ (.A1(\gpio_configure[20][3] ),
+ .A2(_1595_),
+ .B1(net362),
+ .B2(_1596_),
+ .X(_0656_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5428_ (.A1(\gpio_configure[20][2] ),
+ .A2(_1595_),
+ .B1(\cdata[2] ),
+ .B2(_1596_),
+ .X(_0655_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5429_ (.A1(\gpio_configure[20][1] ),
+ .A2(_1595_),
+ .B1(net366),
+ .B2(_1596_),
+ .X(_0654_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5430_ (.A1(\gpio_configure[20][0] ),
+ .A2(_1595_),
+ .B1(\cdata[0] ),
+ .B2(_1596_),
+ .X(_0653_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5431_ (.A(_1488_),
+ .B(_1312_),
+ .X(_1597_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5432_ (.A(_1597_),
+ .X(_1598_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5433_ (.A(_1598_),
+ .Y(_1599_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5434_ (.A1(\gpio_configure[32][7] ),
+ .A2(_1598_),
+ .B1(\cdata[7] ),
+ .B2(_1599_),
+ .X(_0652_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5435_ (.A1(\gpio_configure[32][6] ),
+ .A2(_1598_),
+ .B1(\cdata[6] ),
+ .B2(_1599_),
+ .X(_0651_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5436_ (.A1(\gpio_configure[32][5] ),
+ .A2(_1598_),
+ .B1(\cdata[5] ),
+ .B2(_1599_),
+ .X(_0650_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5437_ (.A1(\gpio_configure[32][4] ),
+ .A2(_1598_),
+ .B1(net360),
+ .B2(_1599_),
+ .X(_0649_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5438_ (.A1(\gpio_configure[32][3] ),
+ .A2(_1598_),
+ .B1(\cdata[3] ),
+ .B2(_1599_),
+ .X(_0648_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5439_ (.A1(\gpio_configure[32][2] ),
+ .A2(_1598_),
+ .B1(\cdata[2] ),
+ .B2(_1599_),
+ .X(_0647_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5440_ (.A1(\gpio_configure[32][1] ),
+ .A2(_1598_),
+ .B1(\cdata[1] ),
+ .B2(_1599_),
+ .X(_0646_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5441_ (.A1(\gpio_configure[32][0] ),
+ .A2(_1598_),
+ .B1(net368),
+ .B2(_1599_),
+ .X(_0645_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5442_ (.A(_1551_),
+ .B(_1327_),
+ .X(_1600_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5443_ (.A(_1600_),
+ .X(_1601_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5444_ (.A(_1601_),
+ .Y(_1602_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5445_ (.A1(\gpio_configure[20][12] ),
+ .A2(_1601_),
+ .B1(net359),
+ .B2(_1602_),
+ .X(_0644_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5446_ (.A1(\gpio_configure[20][11] ),
+ .A2(_1601_),
+ .B1(net361),
+ .B2(_1602_),
+ .X(_0643_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5447_ (.A1(\gpio_configure[20][10] ),
+ .A2(_1601_),
+ .B1(net363),
+ .B2(_1602_),
+ .X(_0642_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5448_ (.A1(\gpio_configure[20][9] ),
+ .A2(_1601_),
+ .B1(net365),
+ .B2(_1602_),
+ .X(_0641_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5449_ (.A1(\gpio_configure[20][8] ),
+ .A2(_1601_),
+ .B1(net367),
+ .B2(_1602_),
+ .X(_0640_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5450_ (.A(_1551_),
+ .B(_1368_),
+ .X(_1603_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _5451_ (.A(_1603_),
+ .X(_1604_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5452_ (.A(_1604_),
+ .Y(_1605_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5453_ (.A1(\gpio_configure[33][12] ),
+ .A2(_1604_),
+ .B1(net359),
+ .B2(_1605_),
+ .X(_0639_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5454_ (.A1(\gpio_configure[33][11] ),
+ .A2(_1604_),
+ .B1(net361),
+ .B2(_1605_),
+ .X(_0638_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5455_ (.A1(\gpio_configure[33][10] ),
+ .A2(_1604_),
+ .B1(net363),
+ .B2(_1605_),
+ .X(_0637_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5456_ (.A1(\gpio_configure[33][9] ),
+ .A2(_1604_),
+ .B1(net365),
+ .B2(_1605_),
+ .X(_0636_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5457_ (.A1(\gpio_configure[33][8] ),
+ .A2(_1604_),
+ .B1(net367),
+ .B2(_1605_),
+ .X(_0635_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5458_ (.A(_1488_),
+ .B(_1406_),
+ .X(_1606_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5459_ (.A(_1606_),
+ .X(_1607_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5460_ (.A(_1607_),
+ .Y(_1608_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5461_ (.A1(\gpio_configure[19][7] ),
+ .A2(_1607_),
+ .B1(\cdata[7] ),
+ .B2(_1608_),
+ .X(_0634_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5462_ (.A1(\gpio_configure[19][6] ),
+ .A2(_1607_),
+ .B1(\cdata[6] ),
+ .B2(_1608_),
+ .X(_0633_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5463_ (.A1(\gpio_configure[19][5] ),
+ .A2(_1607_),
+ .B1(\cdata[5] ),
+ .B2(_1608_),
+ .X(_0632_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5464_ (.A1(\gpio_configure[19][4] ),
+ .A2(_1607_),
+ .B1(net359),
+ .B2(_1608_),
+ .X(_0631_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5465_ (.A1(\gpio_configure[19][3] ),
+ .A2(_1607_),
+ .B1(net361),
+ .B2(_1608_),
+ .X(_0630_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5466_ (.A1(\gpio_configure[19][2] ),
+ .A2(_1607_),
+ .B1(net363),
+ .B2(_1608_),
+ .X(_0629_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5467_ (.A1(\gpio_configure[19][1] ),
+ .A2(_1607_),
+ .B1(net365),
+ .B2(_1608_),
+ .X(_0628_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5468_ (.A1(\gpio_configure[19][0] ),
+ .A2(_1607_),
+ .B1(net367),
+ .B2(_1608_),
+ .X(_0627_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5469_ (.A(_1488_),
+ .B(_1224_),
+ .X(_1609_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5470_ (.A(_1609_),
+ .X(_1610_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5471_ (.A(_1610_),
+ .Y(_1611_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5472_ (.A1(\gpio_configure[33][7] ),
+ .A2(_1610_),
+ .B1(\cdata[7] ),
+ .B2(_1611_),
+ .X(_0626_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5473_ (.A1(\gpio_configure[33][6] ),
+ .A2(_1610_),
+ .B1(\cdata[6] ),
+ .B2(_1611_),
+ .X(_0625_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5474_ (.A1(\gpio_configure[33][5] ),
+ .A2(_1610_),
+ .B1(\cdata[5] ),
+ .B2(_1611_),
+ .X(_0624_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5475_ (.A1(\gpio_configure[33][4] ),
+ .A2(_1610_),
+ .B1(net360),
+ .B2(_1611_),
+ .X(_0623_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5476_ (.A1(\gpio_configure[33][3] ),
+ .A2(_1610_),
+ .B1(\cdata[3] ),
+ .B2(_1611_),
+ .X(_0622_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5477_ (.A1(\gpio_configure[33][2] ),
+ .A2(_1610_),
+ .B1(\cdata[2] ),
+ .B2(_1611_),
+ .X(_0621_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5478_ (.A1(\gpio_configure[33][1] ),
+ .A2(_1610_),
+ .B1(\cdata[1] ),
+ .B2(_1611_),
+ .X(_0620_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5479_ (.A1(\gpio_configure[33][0] ),
+ .A2(_1610_),
+ .B1(net368),
+ .B2(_1611_),
+ .X(_0619_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5480_ (.A(_1551_),
+ .B(_1396_),
+ .X(_1612_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5481_ (.A(_1612_),
+ .X(_1613_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5482_ (.A(_1613_),
+ .Y(_1614_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5483_ (.A1(\gpio_configure[19][12] ),
+ .A2(_1613_),
+ .B1(net359),
+ .B2(_1614_),
+ .X(_0618_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5484_ (.A1(\gpio_configure[19][11] ),
+ .A2(_1613_),
+ .B1(net361),
+ .B2(_1614_),
+ .X(_0617_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5485_ (.A1(\gpio_configure[19][10] ),
+ .A2(_1613_),
+ .B1(net363),
+ .B2(_1614_),
+ .X(_0616_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5486_ (.A1(\gpio_configure[19][9] ),
+ .A2(_1613_),
+ .B1(net365),
+ .B2(_1614_),
+ .X(_0615_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5487_ (.A1(\gpio_configure[19][8] ),
+ .A2(_1613_),
+ .B1(net367),
+ .B2(_1614_),
+ .X(_0614_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5488_ (.A(_1551_),
+ .B(_1266_),
+ .X(_1615_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5489_ (.A(_1615_),
+ .X(_1616_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5490_ (.A(_1616_),
+ .Y(_1617_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5491_ (.A1(\gpio_configure[34][12] ),
+ .A2(_1616_),
+ .B1(net359),
+ .B2(_1617_),
+ .X(_0613_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5492_ (.A1(\gpio_configure[34][11] ),
+ .A2(_1616_),
+ .B1(net361),
+ .B2(_1617_),
+ .X(_0612_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5493_ (.A1(\gpio_configure[34][10] ),
+ .A2(_1616_),
+ .B1(net363),
+ .B2(_1617_),
+ .X(_0611_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5494_ (.A1(\gpio_configure[34][9] ),
+ .A2(_1616_),
+ .B1(net365),
+ .B2(_1617_),
+ .X(_0610_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5495_ (.A1(\gpio_configure[34][8] ),
+ .A2(_1616_),
+ .B1(net367),
+ .B2(_1617_),
+ .X(_0609_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5496_ (.A(_1488_),
+ .B(_1355_),
+ .X(_1618_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5497_ (.A(_1618_),
+ .X(_1619_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5498_ (.A(_1619_),
+ .Y(_1620_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5499_ (.A1(\gpio_configure[18][7] ),
+ .A2(_1619_),
+ .B1(\cdata[7] ),
+ .B2(_1620_),
+ .X(_0608_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5500_ (.A1(\gpio_configure[18][6] ),
+ .A2(_1619_),
+ .B1(\cdata[6] ),
+ .B2(_1620_),
+ .X(_0607_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5501_ (.A1(\gpio_configure[18][5] ),
+ .A2(_1619_),
+ .B1(\cdata[5] ),
+ .B2(_1620_),
+ .X(_0606_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5502_ (.A1(\gpio_configure[18][4] ),
+ .A2(_1619_),
+ .B1(net360),
+ .B2(_1620_),
+ .X(_0605_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5503_ (.A1(\gpio_configure[18][3] ),
+ .A2(_1619_),
+ .B1(net362),
+ .B2(_1620_),
+ .X(_0604_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5504_ (.A1(\gpio_configure[18][2] ),
+ .A2(_1619_),
+ .B1(net364),
+ .B2(_1620_),
+ .X(_0603_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5505_ (.A1(\gpio_configure[18][1] ),
+ .A2(_1619_),
+ .B1(net366),
+ .B2(_1620_),
+ .X(_0602_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5506_ (.A1(\gpio_configure[18][0] ),
+ .A2(_1619_),
+ .B1(net368),
+ .B2(_1620_),
+ .X(_0601_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5507_ (.A(_1488_),
+ .B(_1155_),
+ .X(_1621_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5508_ (.A(_1621_),
+ .X(_1622_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5509_ (.A(_1622_),
+ .Y(_1623_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5510_ (.A1(\gpio_configure[34][7] ),
+ .A2(_1622_),
+ .B1(\cdata[7] ),
+ .B2(_1623_),
+ .X(_0600_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5511_ (.A1(\gpio_configure[34][6] ),
+ .A2(_1622_),
+ .B1(\cdata[6] ),
+ .B2(_1623_),
+ .X(_0599_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5512_ (.A1(\gpio_configure[34][5] ),
+ .A2(_1622_),
+ .B1(\cdata[5] ),
+ .B2(_1623_),
+ .X(_0598_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5513_ (.A1(\gpio_configure[34][4] ),
+ .A2(_1622_),
+ .B1(net360),
+ .B2(_1623_),
+ .X(_0597_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5514_ (.A1(\gpio_configure[34][3] ),
+ .A2(_1622_),
+ .B1(net362),
+ .B2(_1623_),
+ .X(_0596_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5515_ (.A1(\gpio_configure[34][2] ),
+ .A2(_1622_),
+ .B1(net364),
+ .B2(_1623_),
+ .X(_0595_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5516_ (.A1(\gpio_configure[34][1] ),
+ .A2(_1622_),
+ .B1(net366),
+ .B2(_1623_),
+ .X(_0594_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5517_ (.A1(\gpio_configure[34][0] ),
+ .A2(_1622_),
+ .B1(\cdata[0] ),
+ .B2(_1623_),
+ .X(_0593_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5518_ (.A(_1551_),
+ .B(_1398_),
+ .X(_1624_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5519_ (.A(_1624_),
+ .X(_1625_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5520_ (.A(_1625_),
+ .Y(_1626_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5521_ (.A1(\gpio_configure[18][12] ),
+ .A2(_1625_),
+ .B1(net359),
+ .B2(_1626_),
+ .X(_0592_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5522_ (.A1(\gpio_configure[18][11] ),
+ .A2(_1625_),
+ .B1(net361),
+ .B2(_1626_),
+ .X(_0591_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5523_ (.A1(\gpio_configure[18][10] ),
+ .A2(_1625_),
+ .B1(net363),
+ .B2(_1626_),
+ .X(_0590_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5524_ (.A1(\gpio_configure[18][9] ),
+ .A2(_1625_),
+ .B1(net365),
+ .B2(_1626_),
+ .X(_0589_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5525_ (.A1(\gpio_configure[18][8] ),
+ .A2(_1625_),
+ .B1(net367),
+ .B2(_1626_),
+ .X(_0588_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5526_ (.A(_1551_),
+ .B(_1151_),
+ .X(_1627_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5527_ (.A(_1627_),
+ .X(_1628_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5528_ (.A(_1628_),
+ .Y(_1629_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5529_ (.A1(\gpio_configure[35][12] ),
+ .A2(_1628_),
+ .B1(\cdata[4] ),
+ .B2(_1629_),
+ .X(_0587_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5530_ (.A1(\gpio_configure[35][11] ),
+ .A2(_1628_),
+ .B1(\cdata[3] ),
+ .B2(_1629_),
+ .X(_0586_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5531_ (.A1(\gpio_configure[35][10] ),
+ .A2(_1628_),
+ .B1(\cdata[2] ),
+ .B2(_1629_),
+ .X(_0585_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5532_ (.A1(\gpio_configure[35][9] ),
+ .A2(_1628_),
+ .B1(net365),
+ .B2(_1629_),
+ .X(_0584_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5533_ (.A1(\gpio_configure[35][8] ),
+ .A2(_1628_),
+ .B1(\cdata[0] ),
+ .B2(_1629_),
+ .X(_0583_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5534_ (.A(_1488_),
+ .B(_1284_),
+ .X(_1630_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5535_ (.A(_1630_),
+ .X(_1631_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5536_ (.A(_1631_),
+ .Y(_1632_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5537_ (.A1(\gpio_configure[17][7] ),
+ .A2(_1631_),
+ .B1(\cdata[7] ),
+ .B2(_1632_),
+ .X(_0582_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5538_ (.A1(\gpio_configure[17][6] ),
+ .A2(_1631_),
+ .B1(\cdata[6] ),
+ .B2(_1632_),
+ .X(_0581_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5539_ (.A1(\gpio_configure[17][5] ),
+ .A2(_1631_),
+ .B1(\cdata[5] ),
+ .B2(_1632_),
+ .X(_0580_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5540_ (.A1(\gpio_configure[17][4] ),
+ .A2(_1631_),
+ .B1(net360),
+ .B2(_1632_),
+ .X(_0579_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5541_ (.A1(\gpio_configure[17][3] ),
+ .A2(_1631_),
+ .B1(net362),
+ .B2(_1632_),
+ .X(_0578_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5542_ (.A1(\gpio_configure[17][2] ),
+ .A2(_1631_),
+ .B1(net364),
+ .B2(_1632_),
+ .X(_0577_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5543_ (.A1(\gpio_configure[17][1] ),
+ .A2(_1631_),
+ .B1(net366),
+ .B2(_1632_),
+ .X(_0576_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5544_ (.A1(\gpio_configure[17][0] ),
+ .A2(_1631_),
+ .B1(net368),
+ .B2(_1632_),
+ .X(_0575_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5545_ (.A(_1488_),
+ .B(_1231_),
+ .X(_1633_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5546_ (.A(_1633_),
+ .X(_1634_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5547_ (.A(_1634_),
+ .Y(_1635_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5548_ (.A1(\gpio_configure[35][7] ),
+ .A2(_1634_),
+ .B1(\cdata[7] ),
+ .B2(_1635_),
+ .X(_0574_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5549_ (.A1(\gpio_configure[35][6] ),
+ .A2(_1634_),
+ .B1(\cdata[6] ),
+ .B2(_1635_),
+ .X(_0573_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5550_ (.A1(\gpio_configure[35][5] ),
+ .A2(_1634_),
+ .B1(\cdata[5] ),
+ .B2(_1635_),
+ .X(_0572_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5551_ (.A1(\gpio_configure[35][4] ),
+ .A2(_1634_),
+ .B1(net360),
+ .B2(_1635_),
+ .X(_0571_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5552_ (.A1(\gpio_configure[35][3] ),
+ .A2(_1634_),
+ .B1(net362),
+ .B2(_1635_),
+ .X(_0570_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5553_ (.A1(\gpio_configure[35][2] ),
+ .A2(_1634_),
+ .B1(\cdata[2] ),
+ .B2(_1635_),
+ .X(_0569_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5554_ (.A1(\gpio_configure[35][1] ),
+ .A2(_1634_),
+ .B1(net366),
+ .B2(_1635_),
+ .X(_0568_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5555_ (.A1(\gpio_configure[35][0] ),
+ .A2(_1634_),
+ .B1(\cdata[0] ),
+ .B2(_1635_),
+ .X(_0567_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5556_ (.A(_1551_),
+ .B(_1142_),
+ .X(_1636_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5557_ (.A(_1636_),
+ .X(_1637_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5558_ (.A(_1637_),
+ .Y(_1638_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5559_ (.A1(\gpio_configure[17][12] ),
+ .A2(_1637_),
+ .B1(\cdata[4] ),
+ .B2(_1638_),
+ .X(_0566_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5560_ (.A1(\gpio_configure[17][11] ),
+ .A2(_1637_),
+ .B1(\cdata[3] ),
+ .B2(_1638_),
+ .X(_0565_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5561_ (.A1(\gpio_configure[17][10] ),
+ .A2(_1637_),
+ .B1(\cdata[2] ),
+ .B2(_1638_),
+ .X(_0564_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5562_ (.A1(\gpio_configure[17][9] ),
+ .A2(_1637_),
+ .B1(net366),
+ .B2(_1638_),
+ .X(_0563_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5563_ (.A1(\gpio_configure[17][8] ),
+ .A2(_1637_),
+ .B1(\cdata[0] ),
+ .B2(_1638_),
+ .X(_0562_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5564_ (.A(_1551_),
+ .B(_1243_),
+ .X(_1639_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5565_ (.A(_1639_),
+ .X(_1640_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5566_ (.A(_1640_),
+ .Y(_1641_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5567_ (.A1(\gpio_configure[36][12] ),
+ .A2(_1640_),
+ .B1(net359),
+ .B2(_1641_),
+ .X(_0561_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5568_ (.A1(\gpio_configure[36][11] ),
+ .A2(_1640_),
+ .B1(net361),
+ .B2(_1641_),
+ .X(_0560_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5569_ (.A1(\gpio_configure[36][10] ),
+ .A2(_1640_),
+ .B1(net363),
+ .B2(_1641_),
+ .X(_0559_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5570_ (.A1(\gpio_configure[36][9] ),
+ .A2(_1640_),
+ .B1(net365),
+ .B2(_1641_),
+ .X(_0558_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5571_ (.A1(\gpio_configure[36][8] ),
+ .A2(_1640_),
+ .B1(net367),
+ .B2(_1641_),
+ .X(_0557_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5572_ (.A(_1022_),
+ .B(_1222_),
+ .X(_1642_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5573_ (.A(_1642_),
+ .X(_1643_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5574_ (.A(_1643_),
+ .Y(_1644_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5575_ (.A1(\gpio_configure[16][7] ),
+ .A2(_1643_),
+ .B1(\cdata[7] ),
+ .B2(_1644_),
+ .X(_0556_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5576_ (.A1(\gpio_configure[16][6] ),
+ .A2(_1643_),
+ .B1(\cdata[6] ),
+ .B2(_1644_),
+ .X(_0555_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5577_ (.A1(\gpio_configure[16][5] ),
+ .A2(_1643_),
+ .B1(\cdata[5] ),
+ .B2(_1644_),
+ .X(_0554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5578_ (.A1(\gpio_configure[16][4] ),
+ .A2(_1643_),
+ .B1(net360),
+ .B2(_1644_),
+ .X(_0553_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5579_ (.A1(\gpio_configure[16][3] ),
+ .A2(_1643_),
+ .B1(net362),
+ .B2(_1644_),
+ .X(_0552_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5580_ (.A1(\gpio_configure[16][2] ),
+ .A2(_1643_),
+ .B1(net364),
+ .B2(_1644_),
+ .X(_0551_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5581_ (.A1(\gpio_configure[16][1] ),
+ .A2(_1643_),
+ .B1(net366),
+ .B2(_1644_),
+ .X(_0550_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5582_ (.A1(\gpio_configure[16][0] ),
+ .A2(_1643_),
+ .B1(net368),
+ .B2(_1644_),
+ .X(_0549_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5583_ (.A(_1022_),
+ .B(_1251_),
+ .X(_1645_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5584_ (.A(_1645_),
+ .X(_1646_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5585_ (.A(_1646_),
+ .Y(_1647_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5586_ (.A1(\gpio_configure[36][7] ),
+ .A2(_1646_),
+ .B1(\cdata[7] ),
+ .B2(_1647_),
+ .X(_0548_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5587_ (.A1(\gpio_configure[36][6] ),
+ .A2(_1646_),
+ .B1(\cdata[6] ),
+ .B2(_1647_),
+ .X(_0547_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5588_ (.A1(\gpio_configure[36][5] ),
+ .A2(_1646_),
+ .B1(\cdata[5] ),
+ .B2(_1647_),
+ .X(_0546_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5589_ (.A1(\gpio_configure[36][4] ),
+ .A2(_1646_),
+ .B1(net360),
+ .B2(_1647_),
+ .X(_0545_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5590_ (.A1(\gpio_configure[36][3] ),
+ .A2(_1646_),
+ .B1(net362),
+ .B2(_1647_),
+ .X(_0544_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5591_ (.A1(\gpio_configure[36][2] ),
+ .A2(_1646_),
+ .B1(\cdata[2] ),
+ .B2(_1647_),
+ .X(_0543_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5592_ (.A1(\gpio_configure[36][1] ),
+ .A2(_1646_),
+ .B1(net366),
+ .B2(_1647_),
+ .X(_0542_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5593_ (.A1(\gpio_configure[36][0] ),
+ .A2(_1646_),
+ .B1(\cdata[0] ),
+ .B2(_1647_),
+ .X(_0541_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5594_ (.A(_1551_),
+ .B(_1198_),
+ .X(_1648_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5595_ (.A(_1648_),
+ .X(_1649_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5596_ (.A(_1649_),
+ .Y(_1650_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5597_ (.A1(\gpio_configure[16][12] ),
+ .A2(_1649_),
+ .B1(\cdata[4] ),
+ .B2(_1650_),
+ .X(_0540_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5598_ (.A1(\gpio_configure[16][11] ),
+ .A2(_1649_),
+ .B1(\cdata[3] ),
+ .B2(_1650_),
+ .X(_0539_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5599_ (.A1(\gpio_configure[16][10] ),
+ .A2(_1649_),
+ .B1(\cdata[2] ),
+ .B2(_1650_),
+ .X(_0538_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5600_ (.A1(\gpio_configure[16][9] ),
+ .A2(_1649_),
+ .B1(net366),
+ .B2(_1650_),
+ .X(_0537_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5601_ (.A1(\gpio_configure[16][8] ),
+ .A2(_1649_),
+ .B1(\cdata[0] ),
+ .B2(_1650_),
+ .X(_0536_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5602_ (.A(_1551_),
+ .B(_1229_),
+ .X(_1651_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5603_ (.A(_1651_),
+ .X(_1652_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5604_ (.A(_1652_),
+ .Y(_1653_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5605_ (.A1(\gpio_configure[37][12] ),
+ .A2(_1652_),
+ .B1(\cdata[4] ),
+ .B2(_1653_),
+ .X(_0535_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5606_ (.A1(\gpio_configure[37][11] ),
+ .A2(_1652_),
+ .B1(net361),
+ .B2(_1653_),
+ .X(_0534_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5607_ (.A1(\gpio_configure[37][10] ),
+ .A2(_1652_),
+ .B1(net363),
+ .B2(_1653_),
+ .X(_0533_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5608_ (.A1(\gpio_configure[37][9] ),
+ .A2(_1652_),
+ .B1(net365),
+ .B2(_1653_),
+ .X(_0532_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5609_ (.A1(\gpio_configure[37][8] ),
+ .A2(_1652_),
+ .B1(net367),
+ .B2(_1653_),
+ .X(_0531_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5610_ (.A(_1022_),
+ .B(_1239_),
+ .X(_1654_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5611_ (.A(_1654_),
+ .X(_1655_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5612_ (.A(_1655_),
+ .Y(_1656_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5613_ (.A1(\gpio_configure[15][7] ),
+ .A2(_1655_),
+ .B1(\cdata[7] ),
+ .B2(_1656_),
+ .X(_0530_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5614_ (.A1(\gpio_configure[15][6] ),
+ .A2(_1655_),
+ .B1(\cdata[6] ),
+ .B2(_1656_),
+ .X(_0529_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5615_ (.A1(\gpio_configure[15][5] ),
+ .A2(_1655_),
+ .B1(\cdata[5] ),
+ .B2(_1656_),
+ .X(_0528_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5616_ (.A1(\gpio_configure[15][4] ),
+ .A2(_1655_),
+ .B1(net360),
+ .B2(_1656_),
+ .X(_0527_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5617_ (.A1(\gpio_configure[15][3] ),
+ .A2(_1655_),
+ .B1(\cdata[3] ),
+ .B2(_1656_),
+ .X(_0526_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5618_ (.A1(\gpio_configure[15][2] ),
+ .A2(_1655_),
+ .B1(net364),
+ .B2(_1656_),
+ .X(_0525_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5619_ (.A1(\gpio_configure[15][1] ),
+ .A2(_1655_),
+ .B1(\cdata[1] ),
+ .B2(_1656_),
+ .X(_0524_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5620_ (.A1(\gpio_configure[15][0] ),
+ .A2(_1655_),
+ .B1(net368),
+ .B2(_1656_),
+ .X(_0523_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5621_ (.A(_1022_),
+ .B(_1212_),
+ .X(_1657_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5622_ (.A(_1657_),
+ .X(_1658_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5623_ (.A(_1658_),
+ .Y(_1659_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5624_ (.A1(\gpio_configure[37][7] ),
+ .A2(_1658_),
+ .B1(\cdata[7] ),
+ .B2(_1659_),
+ .X(_0522_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5625_ (.A1(\gpio_configure[37][6] ),
+ .A2(_1658_),
+ .B1(\cdata[6] ),
+ .B2(_1659_),
+ .X(_0521_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5626_ (.A1(\gpio_configure[37][5] ),
+ .A2(_1658_),
+ .B1(\cdata[5] ),
+ .B2(_1659_),
+ .X(_0520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5627_ (.A1(\gpio_configure[37][4] ),
+ .A2(_1658_),
+ .B1(net360),
+ .B2(_1659_),
+ .X(_0519_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5628_ (.A1(\gpio_configure[37][3] ),
+ .A2(_1658_),
+ .B1(\cdata[3] ),
+ .B2(_1659_),
+ .X(_0518_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5629_ (.A1(\gpio_configure[37][2] ),
+ .A2(_1658_),
+ .B1(net364),
+ .B2(_1659_),
+ .X(_0517_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5630_ (.A1(\gpio_configure[37][1] ),
+ .A2(_1658_),
+ .B1(\cdata[1] ),
+ .B2(_1659_),
+ .X(_0516_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5631_ (.A1(\gpio_configure[37][0] ),
+ .A2(_1658_),
+ .B1(net368),
+ .B2(_1659_),
+ .X(_0515_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5632_ (.A(_1551_),
+ .B(_1190_),
+ .X(_1660_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5633_ (.A(_1660_),
+ .X(_1661_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5634_ (.A(_1661_),
+ .Y(_1662_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5635_ (.A1(\gpio_configure[15][12] ),
+ .A2(_1661_),
+ .B1(\cdata[4] ),
+ .B2(_1662_),
+ .X(_0514_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5636_ (.A1(\gpio_configure[15][11] ),
+ .A2(_1661_),
+ .B1(\cdata[3] ),
+ .B2(_1662_),
+ .X(_0513_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5637_ (.A1(\gpio_configure[15][10] ),
+ .A2(_1661_),
+ .B1(\cdata[2] ),
+ .B2(_1662_),
+ .X(_0512_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5638_ (.A1(\gpio_configure[15][9] ),
+ .A2(_1661_),
+ .B1(\cdata[1] ),
+ .B2(_1662_),
+ .X(_0511_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5639_ (.A1(\gpio_configure[15][8] ),
+ .A2(_1661_),
+ .B1(\cdata[0] ),
+ .B2(_1662_),
+ .X(_0510_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5640_ (.A(\xfer_count[2] ),
+ .Y(_1663_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5641_ (.A(\xfer_count[0] ),
+ .Y(_1664_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5642_ (.A(\xfer_state[1] ),
+ .Y(_1665_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5643_ (.A(\xfer_state[3] ),
+ .Y(_1666_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _5644_ (.A(\xfer_state[2] ),
+ .Y(_1667_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _5645_ (.A1(_1665_),
+ .A2(_1666_),
+ .A3(_1667_),
+ .B1(\xfer_state[1] ),
+ .B2(net306),
+ .X(_1668_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5646_ (.A(\xfer_count[1] ),
+ .Y(_1669_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _5647_ (.A(_1664_),
+ .B(_1668_),
+ .C(_1669_),
+ .X(_1670_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5648_ (.A(\xfer_count[3] ),
+ .Y(_1671_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _5649_ (.A(_1671_),
+ .B(_1663_),
+ .C(\xfer_count[1] ),
+ .D(\xfer_count[0] ),
+ .X(_1672_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _5650_ (.A1(\xfer_state[1] ),
+ .A2(_1672_),
+ .B1(\xfer_state[3] ),
+ .X(_1673_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5651_ (.A(_1668_),
+ .B(_1673_),
+ .X(_1674_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _5652_ (.A1(_1663_),
+ .A2(_1670_),
+ .B1(_1671_),
+ .Y(_1675_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _5653_ (.A1(_1663_),
+ .A2(_1670_),
+ .A3(_1671_),
+ .B1(_1674_),
+ .C1(_1675_),
+ .X(_0509_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_1 _5654_ (.A1(_1663_),
+ .A2(_1669_),
+ .A3(_1664_),
+ .B1(_1673_),
+ .X(_1676_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _5655_ (.A1_N(_1663_),
+ .A2_N(_1670_),
+ .B1(_1668_),
+ .B2(_1676_),
+ .X(_0508_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _5656_ (.A1(_1664_),
+ .A2(_1668_),
+ .B1(_1669_),
+ .Y(_1677_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_2 _5657_ (.A1(\xfer_state[1] ),
+ .A2(\xfer_state[3] ),
+ .A3(_1667_),
+ .B1(_1670_),
+ .C1(_1677_),
+ .X(_0507_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5658__14 (.A(_1668_),
+ .Y(net392),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _5659_ (.A1(_1664_),
+ .A2(_1668_),
+ .B1(\xfer_count[0] ),
+ .B2(net392),
+ .C1(_1674_),
+ .X(_0506_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5660_ (.A(_1022_),
+ .B(_1206_),
+ .X(_1679_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5661_ (.A(_1679_),
+ .X(_1680_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5662_ (.A(_1680_),
+ .Y(_1681_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5663_ (.A1(\gpio_configure[14][7] ),
+ .A2(_1680_),
+ .B1(\cdata[7] ),
+ .B2(_1681_),
+ .X(_0505_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5664_ (.A1(\gpio_configure[14][6] ),
+ .A2(_1680_),
+ .B1(\cdata[6] ),
+ .B2(_1681_),
+ .X(_0504_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5665_ (.A1(\gpio_configure[14][5] ),
+ .A2(_1680_),
+ .B1(\cdata[5] ),
+ .B2(_1681_),
+ .X(_0503_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5666_ (.A1(\gpio_configure[14][4] ),
+ .A2(_1680_),
+ .B1(net360),
+ .B2(_1681_),
+ .X(_0502_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5667_ (.A1(\gpio_configure[14][3] ),
+ .A2(_1680_),
+ .B1(net362),
+ .B2(_1681_),
+ .X(_0501_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5668_ (.A1(\gpio_configure[14][2] ),
+ .A2(_1680_),
+ .B1(\cdata[2] ),
+ .B2(_1681_),
+ .X(_0500_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5669_ (.A1(\gpio_configure[14][1] ),
+ .A2(_1680_),
+ .B1(\cdata[1] ),
+ .B2(_1681_),
+ .X(_0499_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5670_ (.A1(\gpio_configure[14][0] ),
+ .A2(_1680_),
+ .B1(\cdata[0] ),
+ .B2(_1681_),
+ .X(_0498_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5671_ (.A(_1551_),
+ .B(_1186_),
+ .X(_1682_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5672_ (.A(_1682_),
+ .X(_1683_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5673_ (.A(_1683_),
+ .Y(_1684_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5674_ (.A1(\gpio_configure[14][12] ),
+ .A2(_1683_),
+ .B1(\cdata[4] ),
+ .B2(_1684_),
+ .X(_0497_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5675_ (.A1(\gpio_configure[14][11] ),
+ .A2(_1683_),
+ .B1(\cdata[3] ),
+ .B2(_1684_),
+ .X(_0496_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5676_ (.A1(\gpio_configure[14][10] ),
+ .A2(_1683_),
+ .B1(\cdata[2] ),
+ .B2(_1684_),
+ .X(_0495_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5677_ (.A1(\gpio_configure[14][9] ),
+ .A2(_1683_),
+ .B1(net365),
+ .B2(_1684_),
+ .X(_0494_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5678_ (.A1(\gpio_configure[14][8] ),
+ .A2(_1683_),
+ .B1(\cdata[0] ),
+ .B2(_1684_),
+ .X(_0493_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5679_ (.A(_1022_),
+ .B(_1200_),
+ .X(_1685_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5680_ (.A(_1685_),
+ .X(_1686_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5681_ (.A(_1686_),
+ .Y(_1687_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5682_ (.A1(\gpio_configure[13][7] ),
+ .A2(_1686_),
+ .B1(\cdata[7] ),
+ .B2(_1687_),
+ .X(_0492_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5683_ (.A1(\gpio_configure[13][6] ),
+ .A2(_1686_),
+ .B1(\cdata[6] ),
+ .B2(_1687_),
+ .X(_0491_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5684_ (.A1(\gpio_configure[13][5] ),
+ .A2(_1686_),
+ .B1(\cdata[5] ),
+ .B2(_1687_),
+ .X(_0490_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5685_ (.A1(\gpio_configure[13][4] ),
+ .A2(_1686_),
+ .B1(net360),
+ .B2(_1687_),
+ .X(_0489_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5686_ (.A1(\gpio_configure[13][3] ),
+ .A2(_1686_),
+ .B1(\cdata[3] ),
+ .B2(_1687_),
+ .X(_0488_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5687_ (.A1(\gpio_configure[13][2] ),
+ .A2(_1686_),
+ .B1(net364),
+ .B2(_1687_),
+ .X(_0487_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5688_ (.A1(\gpio_configure[13][1] ),
+ .A2(_1686_),
+ .B1(\cdata[1] ),
+ .B2(_1687_),
+ .X(_0486_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5689_ (.A1(\gpio_configure[13][0] ),
+ .A2(_1686_),
+ .B1(net368),
+ .B2(_1687_),
+ .X(_0485_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5690_ (.A(\xfer_state[0] ),
+ .Y(_1688_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5691_ (.A(_1688_),
+ .B(\xfer_state[2] ),
+ .X(_1689_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5692_ (.A(_1689_),
+ .Y(_1690_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5693_ (.A(\pad_count_1[1] ),
+ .B(\pad_count_1[0] ),
+ .X(_1691_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _5694_ (.A(_1691_),
+ .X(_1692_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _5695_ (.A(\pad_count_1[3] ),
+ .B(\pad_count_1[2] ),
+ .X(_1693_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _5696_ (.A(_1667_),
+ .B(_1692_),
+ .C(_1693_),
+ .Y(_1694_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5697_ (.A(\pad_count_1[4] ),
+ .Y(_1695_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _5698_ (.A(_1693_),
+ .B(_1692_),
+ .C(_1695_),
+ .X(_1696_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _5699_ (.A(_1696_),
+ .X(_1697_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _5700_ (.A1(\pad_count_1[4] ),
+ .A2(_1690_),
+ .A3(_1694_),
+ .B1(_1667_),
+ .B2(_1697_),
+ .X(_0484_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_1 _5701_ (.A1(\pad_count_1[2] ),
+ .A2(_1692_),
+ .A3(_1667_),
+ .B1(\pad_count_1[3] ),
+ .X(_1698_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _5702_ (.A1(_1694_),
+ .A2(_1698_),
+ .B1(_1689_),
+ .X(_0483_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5703_ (.A(\pad_count_1[2] ),
+ .Y(_1699_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5704_ (.A(_1692_),
+ .Y(_1700_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _5705_ (.A1(_1667_),
+ .A2(_1692_),
+ .B1(_1689_),
+ .C1(\pad_count_1[2] ),
+ .X(_1701_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _5706_ (.A1(_1699_),
+ .A2(_1700_),
+ .A3(\xfer_state[2] ),
+ .B1(_1701_),
+ .X(_0482_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5707_ (.A(\pad_count_1[1] ),
+ .Y(_1702_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5708_ (.A(\pad_count_1[0] ),
+ .Y(_1703_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _5709_ (.A(_1702_),
+ .B(_1703_),
+ .X(_1704_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5710_ (.A(_1704_),
+ .Y(_1705_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5711_ (.A(\xfer_state[0] ),
+ .B(\xfer_state[2] ),
+ .X(_1706_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _5712_ (.A1(_1667_),
+ .A2(_1700_),
+ .A3(_1705_),
+ .B1(\pad_count_1[1] ),
+ .B2(_1706_),
+ .X(_0481_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5713_ (.A(_1706_),
+ .Y(_1707_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5714_ (.A1(_1703_),
+ .A2(\xfer_state[2] ),
+ .B1(\pad_count_1[0] ),
+ .B2(_1707_),
+ .X(_0480_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5715_ (.A(\pad_count_2[5] ),
+ .Y(_1708_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5716_ (.A(\pad_count_2[4] ),
+ .Y(_1709_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5717_ (.A(\pad_count_2[1] ),
+ .Y(_1710_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5718_ (.A(\pad_count_2[0] ),
+ .Y(_1711_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5719_ (.A(_1710_),
+ .B(_1711_),
+ .X(_1712_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5720_ (.A(\pad_count_2[3] ),
+ .Y(_1713_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5721_ (.A(\pad_count_2[2] ),
+ .Y(_1714_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5722_ (.A(_1713_),
+ .B(_1714_),
+ .X(_1715_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5723_ (.A(_1712_),
+ .B(_1715_),
+ .X(_1716_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _5724_ (.A(_1709_),
+ .B(_1667_),
+ .C(_1716_),
+ .Y(_1717_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5725_ (.A(\pad_count_2[5] ),
+ .B(_1709_),
+ .X(_1718_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _5726_ (.A(_1718_),
+ .X(_1719_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5727_ (.A(_1716_),
+ .B(_1719_),
+ .X(_1720_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _5728_ (.A(_1720_),
+ .X(_1721_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _5729_ (.A1(_1708_),
+ .A2(_1690_),
+ .A3(_1717_),
+ .B1(_1667_),
+ .B2(_1721_),
+ .X(_1722_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5730_ (.A(_1722_),
+ .Y(_0479_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _5731_ (.A1(\xfer_state[2] ),
+ .A2(_1716_),
+ .B1(_1707_),
+ .Y(_1723_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ba_1 _5732_ (.A1(\pad_count_2[4] ),
+ .A2(_1723_),
+ .B1_N(_1717_),
+ .X(_0478_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _5733_ (.A(\pad_count_2[3] ),
+ .B(_1714_),
+ .C(_1712_),
+ .X(_1724_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _5734_ (.A1(_1713_),
+ .A2(_1723_),
+ .B1(_1667_),
+ .B2(_1724_),
+ .Y(_0477_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _5735_ (.A1(\pad_count_2[1] ),
+ .A2(\pad_count_2[0] ),
+ .A3(\xfer_state[2] ),
+ .B1(\pad_count_2[2] ),
+ .X(_1725_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _5736_ (.A1(_1667_),
+ .A2(_1712_),
+ .A3(_1714_),
+ .B1(_1689_),
+ .C1(_1725_),
+ .X(_0476_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5737_ (.A(_1710_),
+ .B(\pad_count_2[0] ),
+ .X(_1726_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _5738_ (.A(\pad_count_2[1] ),
+ .B(_1711_),
+ .X(_1727_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _5739_ (.A1(\xfer_state[2] ),
+ .A2(_1726_),
+ .A3(_1727_),
+ .B1(_1710_),
+ .B2(_1707_),
+ .X(_1728_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5740_ (.A(_1728_),
+ .Y(_0475_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5741_ (.A1(\pad_count_2[0] ),
+ .A2(_1706_),
+ .B1(_1711_),
+ .B2(_1667_),
+ .X(_0474_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5742_ (.A(_1023_),
+ .B(_1209_),
+ .X(_1729_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5743_ (.A(_1729_),
+ .X(_1730_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5744_ (.A(_1730_),
+ .Y(_1731_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5745_ (.A1(\gpio_configure[13][12] ),
+ .A2(_1730_),
+ .B1(\cdata[4] ),
+ .B2(_1731_),
+ .X(_0473_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5746_ (.A1(\gpio_configure[13][11] ),
+ .A2(_1730_),
+ .B1(\cdata[3] ),
+ .B2(_1731_),
+ .X(_0472_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5747_ (.A1(\gpio_configure[13][10] ),
+ .A2(_1730_),
+ .B1(\cdata[2] ),
+ .B2(_1731_),
+ .X(_0471_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5748_ (.A1(\gpio_configure[13][9] ),
+ .A2(_1730_),
+ .B1(net366),
+ .B2(_1731_),
+ .X(_0470_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5749_ (.A1(\gpio_configure[13][8] ),
+ .A2(_1730_),
+ .B1(\cdata[0] ),
+ .B2(_1731_),
+ .X(_0469_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _5750_ (.A(\xfer_state[3] ),
+ .B(net306),
+ .Y(_1732_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _5751_ (.A(\xfer_count[3] ),
+ .B(\xfer_count[2] ),
+ .C(_1669_),
+ .D(\xfer_count[0] ),
+ .X(_1733_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _5752_ (.A(\xfer_count[3] ),
+ .B(\xfer_count[2] ),
+ .C(\xfer_count[1] ),
+ .X(_1734_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _5753_ (.A(\xfer_state[3] ),
+ .B(_1733_),
+ .C(_1734_),
+ .X(_1735_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _5754_ (.A1(_1665_),
+ .A2(_1666_),
+ .A3(_1707_),
+ .B1(_1735_),
+ .X(_1736_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5755_ (.A(_1736_),
+ .Y(_1737_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _5756_ (.A1(_1707_),
+ .A2(_1732_),
+ .A3(_1737_),
+ .B1(serial_clock_pre),
+ .B2(_1736_),
+ .X(_0468_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5757_ (.A(_1022_),
+ .B(_1259_),
+ .X(_1738_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5758_ (.A(_1738_),
+ .X(_1739_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5759_ (.A(_1739_),
+ .Y(_1740_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5760_ (.A1(\gpio_configure[12][7] ),
+ .A2(_1739_),
+ .B1(\cdata[7] ),
+ .B2(_1740_),
+ .X(_0467_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5761_ (.A1(\gpio_configure[12][6] ),
+ .A2(_1739_),
+ .B1(\cdata[6] ),
+ .B2(_1740_),
+ .X(_0466_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5762_ (.A1(\gpio_configure[12][5] ),
+ .A2(_1739_),
+ .B1(\cdata[5] ),
+ .B2(_1740_),
+ .X(_0465_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5763_ (.A1(\gpio_configure[12][4] ),
+ .A2(_1739_),
+ .B1(net360),
+ .B2(_1740_),
+ .X(_0464_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5764_ (.A1(\gpio_configure[12][3] ),
+ .A2(_1739_),
+ .B1(net362),
+ .B2(_1740_),
+ .X(_0463_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5765_ (.A1(\gpio_configure[12][2] ),
+ .A2(_1739_),
+ .B1(\cdata[2] ),
+ .B2(_1740_),
+ .X(_0462_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5766_ (.A1(\gpio_configure[12][1] ),
+ .A2(_1739_),
+ .B1(\cdata[1] ),
+ .B2(_1740_),
+ .X(_0461_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5767_ (.A1(\gpio_configure[12][0] ),
+ .A2(_1739_),
+ .B1(\cdata[0] ),
+ .B2(_1740_),
+ .X(_0460_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5768_ (.A(_1023_),
+ .B(_1202_),
+ .X(_1741_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5769_ (.A(_1741_),
+ .X(_1742_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5770_ (.A(_1742_),
+ .Y(_1743_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5771_ (.A1(\gpio_configure[12][12] ),
+ .A2(_1742_),
+ .B1(net359),
+ .B2(_1743_),
+ .X(_0459_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5772_ (.A1(\gpio_configure[12][11] ),
+ .A2(_1742_),
+ .B1(net361),
+ .B2(_1743_),
+ .X(_0458_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5773_ (.A1(\gpio_configure[12][10] ),
+ .A2(_1742_),
+ .B1(net363),
+ .B2(_1743_),
+ .X(_0457_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5774_ (.A1(\gpio_configure[12][9] ),
+ .A2(_1742_),
+ .B1(net365),
+ .B2(_1743_),
+ .X(_0456_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5775_ (.A1(\gpio_configure[12][8] ),
+ .A2(_1742_),
+ .B1(net367),
+ .B2(_1743_),
+ .X(_0455_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5776_ (.A(_1022_),
+ .B(_1188_),
+ .X(_1744_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5777_ (.A(_1744_),
+ .X(_1745_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5778_ (.A(_1745_),
+ .Y(_1746_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5779_ (.A1(\gpio_configure[11][7] ),
+ .A2(_1745_),
+ .B1(\cdata[7] ),
+ .B2(_1746_),
+ .X(_0454_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5780_ (.A1(\gpio_configure[11][6] ),
+ .A2(_1745_),
+ .B1(\cdata[6] ),
+ .B2(_1746_),
+ .X(_0453_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5781_ (.A1(\gpio_configure[11][5] ),
+ .A2(_1745_),
+ .B1(\cdata[5] ),
+ .B2(_1746_),
+ .X(_0452_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5782_ (.A1(\gpio_configure[11][4] ),
+ .A2(_1745_),
+ .B1(net360),
+ .B2(_1746_),
+ .X(_0451_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5783_ (.A1(\gpio_configure[11][3] ),
+ .A2(_1745_),
+ .B1(net362),
+ .B2(_1746_),
+ .X(_0450_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5784_ (.A1(\gpio_configure[11][2] ),
+ .A2(_1745_),
+ .B1(net364),
+ .B2(_1746_),
+ .X(_0449_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5785_ (.A1(\gpio_configure[11][1] ),
+ .A2(_1745_),
+ .B1(net366),
+ .B2(_1746_),
+ .X(_0448_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5786_ (.A1(\gpio_configure[11][0] ),
+ .A2(_1745_),
+ .B1(net368),
+ .B2(_1746_),
+ .X(_0447_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5787_ (.A(_1734_),
+ .Y(_1747_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _5788_ (.A1(\xfer_count[0] ),
+ .A2(\xfer_state[3] ),
+ .A3(_1747_),
+ .B1(serial_load_pre),
+ .B2(_1736_),
+ .X(_0446_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5789_ (.A(_1023_),
+ .B(_1192_),
+ .X(_1748_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5790_ (.A(_1748_),
+ .X(_1749_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5791_ (.A(_1749_),
+ .Y(_1750_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5792_ (.A1(\gpio_configure[11][12] ),
+ .A2(_1749_),
+ .B1(net359),
+ .B2(_1750_),
+ .X(_0445_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5793_ (.A1(\gpio_configure[11][11] ),
+ .A2(_1749_),
+ .B1(net361),
+ .B2(_1750_),
+ .X(_0444_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5794_ (.A1(\gpio_configure[11][10] ),
+ .A2(_1749_),
+ .B1(net363),
+ .B2(_1750_),
+ .X(_0443_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5795_ (.A1(\gpio_configure[11][9] ),
+ .A2(_1749_),
+ .B1(net366),
+ .B2(_1750_),
+ .X(_0442_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5796_ (.A1(\gpio_configure[11][8] ),
+ .A2(_1749_),
+ .B1(net367),
+ .B2(_1750_),
+ .X(_0441_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5797_ (.A(_1022_),
+ .B(_1214_),
+ .X(_1751_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5798_ (.A(_1751_),
+ .X(_1752_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _5799_ (.A(_1752_),
+ .Y(_1753_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5800_ (.A1(\gpio_configure[10][7] ),
+ .A2(_1752_),
+ .B1(\cdata[7] ),
+ .B2(_1753_),
+ .X(_0440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5801_ (.A1(\gpio_configure[10][6] ),
+ .A2(_1752_),
+ .B1(\cdata[6] ),
+ .B2(_1753_),
+ .X(_0439_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5802_ (.A1(\gpio_configure[10][5] ),
+ .A2(_1752_),
+ .B1(\cdata[5] ),
+ .B2(_1753_),
+ .X(_0438_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5803_ (.A1(\gpio_configure[10][4] ),
+ .A2(_1752_),
+ .B1(net360),
+ .B2(_1753_),
+ .X(_0437_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5804_ (.A1(\gpio_configure[10][3] ),
+ .A2(_1752_),
+ .B1(\cdata[3] ),
+ .B2(_1753_),
+ .X(_0436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5805_ (.A1(\gpio_configure[10][2] ),
+ .A2(_1752_),
+ .B1(net364),
+ .B2(_1753_),
+ .X(_0435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5806_ (.A1(\gpio_configure[10][1] ),
+ .A2(_1752_),
+ .B1(net366),
+ .B2(_1753_),
+ .X(_0434_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5807_ (.A1(\gpio_configure[10][0] ),
+ .A2(_1752_),
+ .B1(net368),
+ .B2(_1753_),
+ .X(_0433_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _5808_ (.A1(\xfer_state[3] ),
+ .A2(_1688_),
+ .B1(_1666_),
+ .B2(_1733_),
+ .C1(serial_busy),
+ .X(_1754_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _5809_ (.A1(\xfer_state[0] ),
+ .A2(serial_xfer),
+ .A3(_1666_),
+ .B1(_1754_),
+ .X(_0432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5810_ (.A(_1023_),
+ .B(_1165_),
+ .X(_1755_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5811_ (.A(_1755_),
+ .X(_1756_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5812_ (.A(_1756_),
+ .Y(_1757_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5813_ (.A1(\gpio_configure[10][12] ),
+ .A2(_1756_),
+ .B1(\cdata[4] ),
+ .B2(_1757_),
+ .X(_0431_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5814_ (.A1(\gpio_configure[10][11] ),
+ .A2(_1756_),
+ .B1(net361),
+ .B2(_1757_),
+ .X(_0430_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5815_ (.A1(\gpio_configure[10][10] ),
+ .A2(_1756_),
+ .B1(\cdata[2] ),
+ .B2(_1757_),
+ .X(_0429_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5816_ (.A1(\gpio_configure[10][9] ),
+ .A2(_1756_),
+ .B1(net365),
+ .B2(_1757_),
+ .X(_0428_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5817_ (.A1(\gpio_configure[10][8] ),
+ .A2(_1756_),
+ .B1(\cdata[0] ),
+ .B2(_1757_),
+ .X(_0427_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5818_ (.A(_1022_),
+ .B(_1220_),
+ .X(_1758_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5819_ (.A(_1758_),
+ .X(_1759_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5820_ (.A(_1759_),
+ .Y(_1760_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5821_ (.A1(\gpio_configure[9][7] ),
+ .A2(_1759_),
+ .B1(\cdata[7] ),
+ .B2(_1760_),
+ .X(_0426_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5822_ (.A1(\gpio_configure[9][6] ),
+ .A2(_1759_),
+ .B1(\cdata[6] ),
+ .B2(_1760_),
+ .X(_0425_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5823_ (.A1(\gpio_configure[9][5] ),
+ .A2(_1759_),
+ .B1(\cdata[5] ),
+ .B2(_1760_),
+ .X(_0424_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5824_ (.A1(\gpio_configure[9][4] ),
+ .A2(_1759_),
+ .B1(net360),
+ .B2(_1760_),
+ .X(_0423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5825_ (.A1(\gpio_configure[9][3] ),
+ .A2(_1759_),
+ .B1(net362),
+ .B2(_1760_),
+ .X(_0422_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5826_ (.A1(\gpio_configure[9][2] ),
+ .A2(_1759_),
+ .B1(net364),
+ .B2(_1760_),
+ .X(_0421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5827_ (.A1(\gpio_configure[9][1] ),
+ .A2(_1759_),
+ .B1(net366),
+ .B2(_1760_),
+ .X(_0420_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5828_ (.A1(\gpio_configure[9][0] ),
+ .A2(_1759_),
+ .B1(net368),
+ .B2(_1760_),
+ .X(_0419_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5829_ (.A(_1023_),
+ .B(_1241_),
+ .X(_1761_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5830_ (.A(_1761_),
+ .X(_1762_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5831_ (.A(_1762_),
+ .Y(_1763_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5832_ (.A1(\gpio_configure[9][12] ),
+ .A2(_1762_),
+ .B1(net359),
+ .B2(_1763_),
+ .X(_0418_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5833_ (.A1(\gpio_configure[9][11] ),
+ .A2(_1762_),
+ .B1(net361),
+ .B2(_1763_),
+ .X(_0417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5834_ (.A1(\gpio_configure[9][10] ),
+ .A2(_1762_),
+ .B1(net363),
+ .B2(_1763_),
+ .X(_0416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5835_ (.A1(\gpio_configure[9][9] ),
+ .A2(_1762_),
+ .B1(net365),
+ .B2(_1763_),
+ .X(_0415_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5836_ (.A1(\gpio_configure[9][8] ),
+ .A2(_1762_),
+ .B1(net367),
+ .B2(_1763_),
+ .X(_0414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5837_ (.A(_1022_),
+ .B(_1196_),
+ .X(_1764_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5838_ (.A(_1764_),
+ .X(_1765_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5839_ (.A(_1765_),
+ .Y(_1766_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5840_ (.A1(\gpio_configure[8][7] ),
+ .A2(_1765_),
+ .B1(\cdata[7] ),
+ .B2(_1766_),
+ .X(_0413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5841_ (.A1(\gpio_configure[8][6] ),
+ .A2(_1765_),
+ .B1(\cdata[6] ),
+ .B2(_1766_),
+ .X(_0412_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5842_ (.A1(\gpio_configure[8][5] ),
+ .A2(_1765_),
+ .B1(\cdata[5] ),
+ .B2(_1766_),
+ .X(_0411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5843_ (.A1(\gpio_configure[8][4] ),
+ .A2(_1765_),
+ .B1(net360),
+ .B2(_1766_),
+ .X(_0410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5844_ (.A1(\gpio_configure[8][3] ),
+ .A2(_1765_),
+ .B1(net362),
+ .B2(_1766_),
+ .X(_0409_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5845_ (.A1(\gpio_configure[8][2] ),
+ .A2(_1765_),
+ .B1(net364),
+ .B2(_1766_),
+ .X(_0408_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5846_ (.A1(\gpio_configure[8][1] ),
+ .A2(_1765_),
+ .B1(net366),
+ .B2(_1766_),
+ .X(_0407_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5847_ (.A1(\gpio_configure[8][0] ),
+ .A2(_1765_),
+ .B1(net368),
+ .B2(_1766_),
+ .X(_0406_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__10 (.A(_0042_),
+ .Y(net388),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__11 (.A(_0042_),
+ .Y(net389),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__12 (.A(_0042_),
+ .Y(net390),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__4 (.A(_0042_),
+ .Y(net382),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__5 (.A(_0042_),
+ .Y(net383),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__6 (.A(_0042_),
+ .Y(net384),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__7 (.A(_0042_),
+ .Y(net385),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__8 (.A(_0042_),
+ .Y(net386),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _5848__9 (.A(_0042_),
+ .Y(net387),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_1 _5849_ (.A(net390),
+ .X(_1768_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5850_ (.A1(\serial_data_staging_1[12] ),
+ .A2(_0042_),
+ .B1(_0002_),
+ .B2(_1768_),
+ .X(_0405_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5851_ (.A1(_1768_),
+ .A2(_0001_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[11] ),
+ .X(_0404_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5852_ (.A1(_1768_),
+ .A2(_0000_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[10] ),
+ .X(_0403_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5853_ (.A1(_1768_),
+ .A2(_0011_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[9] ),
+ .X(_0402_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5854_ (.A1(_1768_),
+ .A2(_0010_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[8] ),
+ .X(_0401_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5855_ (.A1(_1768_),
+ .A2(_0009_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[7] ),
+ .X(_0400_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5856_ (.A1(_1768_),
+ .A2(_0008_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[6] ),
+ .X(_0399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5857_ (.A1(_1768_),
+ .A2(_0007_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[5] ),
+ .X(_0398_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5858_ (.A1(_1768_),
+ .A2(_0006_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[4] ),
+ .X(_0397_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5859_ (.A1(_1768_),
+ .A2(_0005_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[3] ),
+ .X(_0396_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5860_ (.A1(_1768_),
+ .A2(_0004_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[2] ),
+ .X(_0395_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5861_ (.A1(_1768_),
+ .A2(_0003_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_1[1] ),
+ .X(_0394_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5862_ (.A(_0129_),
+ .Y(_1769_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _5863_ (.A1(_0042_),
+ .A2(_1665_),
+ .A3(_1769_),
+ .B1(net389),
+ .B2(\serial_data_staging_1[0] ),
+ .X(_0393_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5864_ (.A(_1023_),
+ .B(_1174_),
+ .X(_1770_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5865_ (.A(_1770_),
+ .X(_1771_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5866_ (.A(_1771_),
+ .Y(_1772_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5867_ (.A1(\gpio_configure[8][12] ),
+ .A2(_1771_),
+ .B1(\cdata[4] ),
+ .B2(_1772_),
+ .X(_0392_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5868_ (.A1(\gpio_configure[8][11] ),
+ .A2(_1771_),
+ .B1(\cdata[3] ),
+ .B2(_1772_),
+ .X(_0391_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5869_ (.A1(\gpio_configure[8][10] ),
+ .A2(_1771_),
+ .B1(\cdata[2] ),
+ .B2(_1772_),
+ .X(_0390_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5870_ (.A1(\gpio_configure[8][9] ),
+ .A2(_1771_),
+ .B1(net365),
+ .B2(_1772_),
+ .X(_0389_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5871_ (.A1(\gpio_configure[8][8] ),
+ .A2(_1771_),
+ .B1(\cdata[0] ),
+ .B2(_1772_),
+ .X(_0388_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5872_ (.A(_1022_),
+ .B(_1149_),
+ .X(_1773_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5873_ (.A(_1773_),
+ .X(_1774_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5874_ (.A(_1774_),
+ .Y(_1775_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5875_ (.A1(\gpio_configure[7][7] ),
+ .A2(_1774_),
+ .B1(\cdata[7] ),
+ .B2(_1775_),
+ .X(_0387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5876_ (.A1(\gpio_configure[7][6] ),
+ .A2(_1774_),
+ .B1(\cdata[6] ),
+ .B2(_1775_),
+ .X(_0386_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5877_ (.A1(\gpio_configure[7][5] ),
+ .A2(_1774_),
+ .B1(\cdata[5] ),
+ .B2(_1775_),
+ .X(_0385_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5878_ (.A1(\gpio_configure[7][4] ),
+ .A2(_1774_),
+ .B1(net360),
+ .B2(_1775_),
+ .X(_0384_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5879_ (.A1(\gpio_configure[7][3] ),
+ .A2(_1774_),
+ .B1(net362),
+ .B2(_1775_),
+ .X(_0383_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5880_ (.A1(\gpio_configure[7][2] ),
+ .A2(_1774_),
+ .B1(net364),
+ .B2(_1775_),
+ .X(_0382_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5881_ (.A1(\gpio_configure[7][1] ),
+ .A2(_1774_),
+ .B1(net366),
+ .B2(_1775_),
+ .X(_0381_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5882_ (.A1(\gpio_configure[7][0] ),
+ .A2(_1774_),
+ .B1(net368),
+ .B2(_1775_),
+ .X(_0380_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5883_ (.A1(_1768_),
+ .A2(_0014_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[12] ),
+ .X(_0379_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5884_ (.A1(_1768_),
+ .A2(_0013_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[11] ),
+ .X(_0378_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5885_ (.A1(_1768_),
+ .A2(_0012_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[10] ),
+ .X(_0377_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5886_ (.A1(_1768_),
+ .A2(_0023_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[9] ),
+ .X(_0376_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5887_ (.A1(_1768_),
+ .A2(_0022_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[8] ),
+ .X(_0375_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5888_ (.A1(_1768_),
+ .A2(_0021_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[7] ),
+ .X(_0374_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5889_ (.A1(net388),
+ .A2(_0020_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[6] ),
+ .X(_0373_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5890_ (.A1(net387),
+ .A2(_0019_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[5] ),
+ .X(_0372_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5891_ (.A1(net386),
+ .A2(_0018_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[4] ),
+ .X(_0371_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5892_ (.A1(net385),
+ .A2(_0017_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[3] ),
+ .X(_0370_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5893_ (.A1(net384),
+ .A2(_0016_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[2] ),
+ .X(_0369_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _5894_ (.A1(net383),
+ .A2(_0015_),
+ .B1(_0042_),
+ .B2(\serial_data_staging_2[1] ),
+ .X(_0368_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5895_ (.A(_0102_),
+ .Y(_1776_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _5896_ (.A1(_0042_),
+ .A2(_1665_),
+ .A3(_1776_),
+ .B1(net382),
+ .B2(\serial_data_staging_2[0] ),
+ .X(_0367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5897_ (.A(_1023_),
+ .B(_1179_),
+ .X(_1777_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5898_ (.A(_1777_),
+ .X(_1778_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5899_ (.A(_1778_),
+ .Y(_1779_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5900_ (.A1(\gpio_configure[7][12] ),
+ .A2(_1778_),
+ .B1(\cdata[4] ),
+ .B2(_1779_),
+ .X(_0366_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5901_ (.A1(\gpio_configure[7][11] ),
+ .A2(_1778_),
+ .B1(\cdata[3] ),
+ .B2(_1779_),
+ .X(_0365_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5902_ (.A1(\gpio_configure[7][10] ),
+ .A2(_1778_),
+ .B1(\cdata[2] ),
+ .B2(_1779_),
+ .X(_0364_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5903_ (.A1(\gpio_configure[7][9] ),
+ .A2(_1778_),
+ .B1(net365),
+ .B2(_1779_),
+ .X(_0363_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5904_ (.A1(\gpio_configure[7][8] ),
+ .A2(_1778_),
+ .B1(\cdata[0] ),
+ .B2(_1779_),
+ .X(_0362_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5905_ (.A(_1022_),
+ .B(_1146_),
+ .X(_1780_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5906_ (.A(_1780_),
+ .X(_1781_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5907_ (.A(_1781_),
+ .Y(_1782_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5908_ (.A1(\gpio_configure[6][7] ),
+ .A2(_1781_),
+ .B1(\cdata[7] ),
+ .B2(_1782_),
+ .X(_0361_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5909_ (.A1(\gpio_configure[6][6] ),
+ .A2(_1781_),
+ .B1(\cdata[6] ),
+ .B2(_1782_),
+ .X(_0360_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5910_ (.A1(\gpio_configure[6][5] ),
+ .A2(_1781_),
+ .B1(\cdata[5] ),
+ .B2(_1782_),
+ .X(_0359_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5911_ (.A1(\gpio_configure[6][4] ),
+ .A2(_1781_),
+ .B1(net360),
+ .B2(_1782_),
+ .X(_0358_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5912_ (.A1(\gpio_configure[6][3] ),
+ .A2(_1781_),
+ .B1(net362),
+ .B2(_1782_),
+ .X(_0357_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5913_ (.A1(\gpio_configure[6][2] ),
+ .A2(_1781_),
+ .B1(net364),
+ .B2(_1782_),
+ .X(_0356_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5914_ (.A1(\gpio_configure[6][1] ),
+ .A2(_1781_),
+ .B1(net366),
+ .B2(_1782_),
+ .X(_0355_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5915_ (.A1(\gpio_configure[6][0] ),
+ .A2(_1781_),
+ .B1(net368),
+ .B2(_1782_),
+ .X(_0354_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5916_ (.A(_1023_),
+ .B(_1255_),
+ .X(_1783_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5917_ (.A(_1783_),
+ .X(_1784_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5918_ (.A(_1784_),
+ .Y(_1785_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5919_ (.A1(\gpio_configure[6][12] ),
+ .A2(_1784_),
+ .B1(net359),
+ .B2(_1785_),
+ .X(_0353_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5920_ (.A1(\gpio_configure[6][11] ),
+ .A2(_1784_),
+ .B1(net361),
+ .B2(_1785_),
+ .X(_0352_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5921_ (.A1(\gpio_configure[6][10] ),
+ .A2(_1784_),
+ .B1(net363),
+ .B2(_1785_),
+ .X(_0351_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5922_ (.A1(\gpio_configure[6][9] ),
+ .A2(_1784_),
+ .B1(net366),
+ .B2(_1785_),
+ .X(_0350_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5923_ (.A1(\gpio_configure[6][8] ),
+ .A2(_1784_),
+ .B1(net367),
+ .B2(_1785_),
+ .X(_0349_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5924_ (.A(\wbbd_state[1] ),
+ .Y(_1786_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _5925_ (.A(net141),
+ .B(net140),
+ .C(net147),
+ .D_N(net148),
+ .X(_1787_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _5926_ (.A(net137),
+ .B(net136),
+ .C(net139),
+ .D(net138),
+ .X(_1788_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _5927_ (.A(net133),
+ .B(net132),
+ .C(net135),
+ .D(net134),
+ .X(_1789_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _5928_ (.A(net162),
+ .B(net161),
+ .C(_1789_),
+ .X(_1790_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5929_ (.A(net146),
+ .B(net145),
+ .X(_1791_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4bb_1 _5930_ (.A(net150),
+ .B(net151),
+ .C_N(net149),
+ .D_N(net152),
+ .X(_1792_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4bb_1 _5931_ (.A(net155),
+ .B(net154),
+ .C_N(net163),
+ .D_N(net201),
+ .X(_1793_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5932_ (.A(net144),
+ .Y(_1794_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5933_ (.A(net143),
+ .Y(_1795_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5934_ (.A(_1794_),
+ .B(_1795_),
+ .X(_1796_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _5935_ (.A(_1791_),
+ .B(_1792_),
+ .C(_1793_),
+ .D_N(_1796_),
+ .X(_1797_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _5936_ (.A(_1787_),
+ .B(_1788_),
+ .C(_1790_),
+ .D(_1797_),
+ .X(_1798_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _5937_ (.A(\wbbd_state[0] ),
+ .B(_1798_),
+ .X(_1799_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _5938_ (.A(_1786_),
+ .B(_1799_),
+ .Y(_1800_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5939_ (.A(_1519_),
+ .B(_1798_),
+ .X(_1801_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _5940_ (.A1(\wbbd_state[0] ),
+ .A2(_1080_),
+ .B1(net326),
+ .B2(_1800_),
+ .C1(_1801_),
+ .X(_0348_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5941_ (.A(_1023_),
+ .B(_1264_),
+ .X(_1802_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5942_ (.A(_1802_),
+ .X(_1803_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5943_ (.A(_1803_),
+ .Y(_1804_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5944_ (.A1(\gpio_configure[5][12] ),
+ .A2(_1803_),
+ .B1(net359),
+ .B2(_1804_),
+ .X(_0347_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5945_ (.A1(\gpio_configure[5][11] ),
+ .A2(_1803_),
+ .B1(net361),
+ .B2(_1804_),
+ .X(_0346_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5946_ (.A1(\gpio_configure[5][10] ),
+ .A2(_1803_),
+ .B1(net363),
+ .B2(_1804_),
+ .X(_0345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5947_ (.A1(\gpio_configure[5][9] ),
+ .A2(_1803_),
+ .B1(net366),
+ .B2(_1804_),
+ .X(_0344_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5948_ (.A1(\gpio_configure[5][8] ),
+ .A2(_1803_),
+ .B1(net367),
+ .B2(_1804_),
+ .X(_0343_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5949_ (.A(_1022_),
+ .B(_1168_),
+ .X(_1805_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5950_ (.A(_1805_),
+ .X(_1806_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5951_ (.A(_1806_),
+ .Y(_1807_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5952_ (.A1(\gpio_configure[4][7] ),
+ .A2(_1806_),
+ .B1(\cdata[7] ),
+ .B2(_1807_),
+ .X(_0342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5953_ (.A1(\gpio_configure[4][6] ),
+ .A2(_1806_),
+ .B1(\cdata[6] ),
+ .B2(_1807_),
+ .X(_0341_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5954_ (.A1(\gpio_configure[4][5] ),
+ .A2(_1806_),
+ .B1(\cdata[5] ),
+ .B2(_1807_),
+ .X(_0340_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5955_ (.A1(\gpio_configure[4][4] ),
+ .A2(_1806_),
+ .B1(net360),
+ .B2(_1807_),
+ .X(_0339_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5956_ (.A1(\gpio_configure[4][3] ),
+ .A2(_1806_),
+ .B1(net362),
+ .B2(_1807_),
+ .X(_0338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5957_ (.A1(\gpio_configure[4][2] ),
+ .A2(_1806_),
+ .B1(net364),
+ .B2(_1807_),
+ .X(_0337_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5958_ (.A1(\gpio_configure[4][1] ),
+ .A2(_1806_),
+ .B1(net366),
+ .B2(_1807_),
+ .X(_0336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5959_ (.A1(\gpio_configure[4][0] ),
+ .A2(_1806_),
+ .B1(net368),
+ .B2(_1807_),
+ .X(_0335_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5960_ (.A(_1023_),
+ .B(_1245_),
+ .X(_1808_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _5961_ (.A(_1808_),
+ .X(_1809_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5962_ (.A(_1809_),
+ .Y(_1810_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5963_ (.A1(\gpio_configure[4][12] ),
+ .A2(_1809_),
+ .B1(net359),
+ .B2(_1810_),
+ .X(_0334_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5964_ (.A1(\gpio_configure[4][11] ),
+ .A2(_1809_),
+ .B1(net361),
+ .B2(_1810_),
+ .X(_0333_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5965_ (.A1(\gpio_configure[4][10] ),
+ .A2(_1809_),
+ .B1(net363),
+ .B2(_1810_),
+ .X(_0332_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5966_ (.A1(\gpio_configure[4][9] ),
+ .A2(_1809_),
+ .B1(net365),
+ .B2(_1810_),
+ .X(_0331_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5967_ (.A1(\gpio_configure[4][8] ),
+ .A2(_1809_),
+ .B1(net367),
+ .B2(_1810_),
+ .X(_0330_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _5968_ (.A(_1022_),
+ .B(_1321_),
+ .X(_1811_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _5969_ (.A(_1811_),
+ .X(_1812_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5970_ (.A(_1812_),
+ .Y(_1813_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5971_ (.A1(\gpio_configure[3][7] ),
+ .A2(_1812_),
+ .B1(\cdata[7] ),
+ .B2(_1813_),
+ .X(_0329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5972_ (.A1(\gpio_configure[3][6] ),
+ .A2(_1812_),
+ .B1(\cdata[6] ),
+ .B2(_1813_),
+ .X(_0328_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5973_ (.A1(\gpio_configure[3][5] ),
+ .A2(_1812_),
+ .B1(\cdata[5] ),
+ .B2(_1813_),
+ .X(_0327_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5974_ (.A1(\gpio_configure[3][4] ),
+ .A2(_1812_),
+ .B1(net360),
+ .B2(_1813_),
+ .X(_0326_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5975_ (.A1(\gpio_configure[3][3] ),
+ .A2(_1812_),
+ .B1(net362),
+ .B2(_1813_),
+ .X(_0325_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5976_ (.A1(\gpio_configure[3][2] ),
+ .A2(_1812_),
+ .B1(\cdata[2] ),
+ .B2(_1813_),
+ .X(_0324_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5977_ (.A1(\gpio_configure[3][1] ),
+ .A2(_1812_),
+ .B1(net366),
+ .B2(_1813_),
+ .X(_0323_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5978_ (.A1(\gpio_configure[3][0] ),
+ .A2(_1812_),
+ .B1(\cdata[0] ),
+ .B2(_1813_),
+ .X(_0322_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5979_ (.A(_1449_),
+ .X(_1814_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5980_ (.A(_1814_),
+ .X(_0234_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _5981_ (.A(\hkspi.count[0] ),
+ .B(_1465_),
+ .C(\hkspi.count[1] ),
+ .X(_1815_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _5982_ (.A1(\hkspi.count[2] ),
+ .A2(_1815_),
+ .B1(_1419_),
+ .B2(_1466_),
+ .X(_0321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5983_ (.A(_1449_),
+ .X(_1816_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5984_ (.A(_1816_),
+ .X(_0233_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _5985_ (.A(_1417_),
+ .B(_1466_),
+ .Y(_1817_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ba_1 _5986_ (.A1(\hkspi.count[1] ),
+ .A2(_1817_),
+ .B1_N(_1815_),
+ .X(_0320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5987_ (.A(_1449_),
+ .X(_1818_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5988_ (.A(_1818_),
+ .X(_0232_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _5989_ (.A1(_1417_),
+ .A2(_1466_),
+ .B1(_1817_),
+ .Y(_0319_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5990_ (.A(_1449_),
+ .X(_1819_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5991_ (.A(_1819_),
+ .X(_0231_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _5992_ (.A(\hkspi.fixed[0] ),
+ .B(_1442_),
+ .Y(_1820_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _5993_ (.A(\hkspi.state[2] ),
+ .B(_1420_),
+ .C(_1820_),
+ .X(_1821_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_4 _5994_ (.A1(\hkspi.state[3] ),
+ .A2(_1821_),
+ .B1(_0087_),
+ .Y(_1822_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _5995_ (.A(_1822_),
+ .Y(_1823_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5996_ (.A1(\hkspi.addr[7] ),
+ .A2(_1822_),
+ .B1(_0054_),
+ .B2(_1823_),
+ .X(_0318_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5997_ (.A(_1449_),
+ .X(_1824_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _5998_ (.A(_1824_),
+ .X(_0230_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _5999_ (.A1(\hkspi.addr[6] ),
+ .A2(_1822_),
+ .B1(_0053_),
+ .B2(_1823_),
+ .X(_0317_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6000_ (.A(_1449_),
+ .X(_1825_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6001_ (.A(_1825_),
+ .X(_0229_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6002_ (.A1(\hkspi.addr[5] ),
+ .A2(_1822_),
+ .B1(_0052_),
+ .B2(_1823_),
+ .X(_0316_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6003_ (.A(_1449_),
+ .X(_1826_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6004_ (.A(_1826_),
+ .X(_0228_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6005_ (.A1(\hkspi.addr[4] ),
+ .A2(_1822_),
+ .B1(_0051_),
+ .B2(_1823_),
+ .X(_0315_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6006_ (.A(_1449_),
+ .X(_1827_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6007_ (.A(_1827_),
+ .X(_0227_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6008_ (.A1(\hkspi.addr[3] ),
+ .A2(_1822_),
+ .B1(_0050_),
+ .B2(_1823_),
+ .X(_0314_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6009_ (.A(_1449_),
+ .X(_1828_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6010_ (.A(_1828_),
+ .X(_0226_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6011_ (.A1(\hkspi.addr[2] ),
+ .A2(_1822_),
+ .B1(_0049_),
+ .B2(_1823_),
+ .X(_0313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6012_ (.A(_1449_),
+ .X(_1829_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6013_ (.A(_1829_),
+ .X(_0225_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6014_ (.A1(\hkspi.addr[1] ),
+ .A2(_1822_),
+ .B1(_0048_),
+ .B2(_1823_),
+ .X(_0312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6015_ (.A(_1449_),
+ .X(_1830_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6016_ (.A(_1830_),
+ .X(_0224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6017_ (.A1(\hkspi.addr[0] ),
+ .A2(_1822_),
+ .B1(_0047_),
+ .B2(_1823_),
+ .X(_0311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _6018_ (.A0(net368),
+ .A1(trap_output_dest),
+ .S(_1048_),
+ .X(_1831_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6019_ (.A(_1831_),
+ .X(_0310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6020_ (.A(_1449_),
+ .X(_1832_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6021_ (.A(_1832_),
+ .X(_0223_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _6022_ (.A(_1415_),
+ .B(_0087_),
+ .C(_1417_),
+ .D(_1416_),
+ .X(_1833_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6023_ (.A(_1833_),
+ .Y(_1834_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6024_ (.A1(\hkspi.pre_pass_thru_user ),
+ .A2(_1834_),
+ .B1(\hkspi.pass_thru_user_delay ),
+ .B2(_1833_),
+ .X(_0309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6025_ (.A1(serial_bb_data_1),
+ .A2(_1034_),
+ .B1(\cdata[5] ),
+ .B2(_1035_),
+ .X(_0308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6026_ (.A1(serial_bb_resetn),
+ .A2(_1034_),
+ .B1(net364),
+ .B2(_1035_),
+ .X(_0307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _6027_ (.A(_1022_),
+ .B(_1293_),
+ .X(_1835_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _6028_ (.A(_1835_),
+ .X(_1836_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6029_ (.A(_1836_),
+ .Y(_1837_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6030_ (.A1(\gpio_configure[26][7] ),
+ .A2(_1836_),
+ .B1(\cdata[7] ),
+ .B2(_1837_),
+ .X(_0306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6031_ (.A1(\gpio_configure[26][6] ),
+ .A2(_1836_),
+ .B1(\cdata[6] ),
+ .B2(_1837_),
+ .X(_0305_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6032_ (.A1(\gpio_configure[26][5] ),
+ .A2(_1836_),
+ .B1(\cdata[5] ),
+ .B2(_1837_),
+ .X(_0304_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6033_ (.A1(\gpio_configure[26][4] ),
+ .A2(_1836_),
+ .B1(\cdata[4] ),
+ .B2(_1837_),
+ .X(_0303_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6034_ (.A1(\gpio_configure[26][3] ),
+ .A2(_1836_),
+ .B1(\cdata[3] ),
+ .B2(_1837_),
+ .X(_0302_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6035_ (.A1(\gpio_configure[26][2] ),
+ .A2(_1836_),
+ .B1(\cdata[2] ),
+ .B2(_1837_),
+ .X(_0301_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6036_ (.A1(\gpio_configure[26][1] ),
+ .A2(_1836_),
+ .B1(\cdata[1] ),
+ .B2(_1837_),
+ .X(_0300_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6037_ (.A1(\gpio_configure[26][0] ),
+ .A2(_1836_),
+ .B1(\cdata[0] ),
+ .B2(_1837_),
+ .X(_0299_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6038_ (.A1(serial_bb_load),
+ .A2(_1034_),
+ .B1(net362),
+ .B2(_1035_),
+ .X(_0298_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6039__1 (.A(clknet_2_1_0_mgmt_gpio_in[4]),
+ .Y(net379),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6040_ (.A(_1449_),
+ .X(_1838_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6041_ (.A(_1838_),
+ .X(_0221_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6042_ (.A(_1126_),
+ .X(_1839_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6043_ (.A(_1839_),
+ .X(_0220_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6044_ (.A(_1126_),
+ .X(_1840_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6045_ (.A(_1840_),
+ .X(_0219_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6046_ (.A(_1126_),
+ .X(_1841_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6047_ (.A(_1841_),
+ .X(_0218_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6048_ (.A(_1126_),
+ .X(_1842_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6049_ (.A(_1842_),
+ .X(_0217_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6050_ (.A(_1126_),
+ .X(_1843_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _6051_ (.A(_1843_),
+ .X(_0216_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _6052_ (.A(_1022_),
+ .B(_1124_),
+ .C(_1161_),
+ .X(_1844_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _6053_ (.A(_1844_),
+ .X(_1845_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6054_ (.A(_1845_),
+ .Y(_1846_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6055_ (.A1(net303),
+ .A2(_1845_),
+ .B1(net362),
+ .B2(_1846_),
+ .X(_0297_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6056_ (.A1(net302),
+ .A2(_1845_),
+ .B1(net364),
+ .B2(_1846_),
+ .X(_0296_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6057_ (.A1(net301),
+ .A2(_1845_),
+ .B1(net366),
+ .B2(_1846_),
+ .X(_0295_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _6058_ (.A1(net300),
+ .A2(_1845_),
+ .B1(net368),
+ .B2(_1846_),
+ .X(_0294_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6059_ (.A(\gpio_configure[3][7] ),
+ .Y(_1847_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6060_ (.A(net70),
+ .Y(_1848_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6061_ (.A(\gpio_configure[36][7] ),
+ .Y(_1849_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6062_ (.A(\gpio_configure[1][7] ),
+ .Y(_1850_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6063_ (.A1(_1849_),
+ .A2(_1251_),
+ .B1(_1850_),
+ .B2(_1249_),
+ .X(_1851_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6064_ (.A1(_1847_),
+ .A2(_1321_),
+ .B1(_1848_),
+ .B2(_1177_),
+ .C1(_1851_),
+ .X(_1852_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6065_ (.A(\gpio_configure[8][7] ),
+ .Y(_1853_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6066_ (.A(\gpio_configure[14][7] ),
+ .Y(_1854_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6067_ (.A(\gpio_configure[37][7] ),
+ .Y(_1855_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6068_ (.A(\gpio_configure[34][7] ),
+ .Y(_1856_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6069_ (.A1(_1855_),
+ .A2(_1212_),
+ .B1(_1856_),
+ .B2(_1155_),
+ .X(_1857_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6070_ (.A1(_1853_),
+ .A2(_1196_),
+ .B1(_1854_),
+ .B2(_1206_),
+ .C1(_1857_),
+ .X(_1858_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _6071_ (.A(_1852_),
+ .B(_1858_),
+ .Y(_1859_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6072_ (.A(\gpio_configure[31][7] ),
+ .Y(_1860_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6073_ (.A(\gpio_configure[29][7] ),
+ .Y(_1861_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6074_ (.A(\gpio_configure[20][7] ),
+ .Y(_1862_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6075_ (.A(net122),
+ .Y(_1863_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6076_ (.A1(_1862_),
+ .A2(_1392_),
+ .B1(_1863_),
+ .B2(_1339_),
+ .X(_1864_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6077_ (.A1(_1860_),
+ .A2(_1295_),
+ .B1(_1861_),
+ .B2(_1334_),
+ .C1(_1864_),
+ .X(_1865_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6078_ (.A(\gpio_configure[22][7] ),
+ .Y(_1866_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6079_ (.A(\gpio_configure[28][7] ),
+ .Y(_1867_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6080_ (.A(\gpio_configure[33][7] ),
+ .Y(_1868_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _6081_ (.A(_1868_),
+ .B(_1224_),
+ .X(_1869_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6082_ (.A1(_1866_),
+ .A2(_1375_),
+ .B1(_1867_),
+ .B2(_1388_),
+ .C1(_1869_),
+ .X(_1870_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6083_ (.A(\gpio_configure[27][7] ),
+ .Y(_1871_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6084_ (.A(net297),
+ .Y(_1872_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6085_ (.A(net10),
+ .Y(_1873_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _6086_ (.A(_1065_),
+ .B(_1167_),
+ .X(_1874_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6087_ (.A(net33),
+ .Y(_1875_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6088_ (.A1(_1873_),
+ .A2(_1874_),
+ .B1(_1875_),
+ .B2(_1348_),
+ .X(_1876_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6089_ (.A1(_1871_),
+ .A2(_1273_),
+ .B1(_1872_),
+ .B2(_1106_),
+ .C1(_1876_),
+ .X(_1877_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6090_ (.A(\gpio_configure[19][7] ),
+ .Y(_1878_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6091_ (.A(\gpio_configure[18][7] ),
+ .Y(_1879_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6092_ (.A(net280),
+ .Y(_1880_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6093_ (.A(net19),
+ .Y(_1881_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6094_ (.A1(_1880_),
+ .A2(_1101_),
+ .B1(_1881_),
+ .B2(_1384_),
+ .X(_1882_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6095_ (.A1(_1878_),
+ .A2(_1406_),
+ .B1(_1879_),
+ .B2(_1355_),
+ .C1(_1882_),
+ .X(_1883_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _6096_ (.A(_1865_),
+ .B(_1870_),
+ .C(_1877_),
+ .D(_1883_),
+ .X(_1884_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6097_ (.A(net117),
+ .Y(_1885_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6098_ (.A(\gpio_configure[17][7] ),
+ .Y(_1886_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6099_ (.A(net99),
+ .Y(_1887_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6100_ (.A(net108),
+ .Y(_1888_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6101_ (.A1(_1887_),
+ .A2(_1370_),
+ .B1(_1888_),
+ .B2(_1319_),
+ .X(_1889_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6102_ (.A1(_1885_),
+ .A2(_1310_),
+ .B1(_1886_),
+ .B2(_1284_),
+ .C1(_1889_),
+ .X(_1890_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6103_ (.A(\gpio_configure[32][7] ),
+ .Y(_1891_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6104_ (.A(\gpio_configure[26][7] ),
+ .Y(_1892_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6105_ (.A(\gpio_configure[0][7] ),
+ .Y(_1893_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6106_ (.A(net28),
+ .Y(_1894_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_4 _6107_ (.A1(_1893_),
+ .A2(_1353_),
+ .B1(_1894_),
+ .B2(_1300_),
+ .X(_1895_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6108_ (.A1(_1891_),
+ .A2(_1312_),
+ .B1(_1892_),
+ .B2(_1293_),
+ .C1(_1895_),
+ .X(_1896_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6109_ (.A(\gpio_configure[24][7] ),
+ .Y(_1897_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6110_ (.A(\gpio_configure[23][7] ),
+ .Y(_1898_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_4 _6111_ (.A(_1028_),
+ .B(_1070_),
+ .C_N(net323),
+ .X(_1899_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6112_ (.A1(_1897_),
+ .A2(_1325_),
+ .B1(_1898_),
+ .B2(_1404_),
+ .C1(_1899_),
+ .X(_1900_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6113_ (.A(\gpio_configure[21][7] ),
+ .Y(_1901_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6114_ (.A(\gpio_configure[30][7] ),
+ .Y(_1902_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6115_ (.A(net289),
+ .Y(_1903_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6116_ (.A(\gpio_configure[25][7] ),
+ .Y(_1904_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6117_ (.A1(_1903_),
+ .A2(_1096_),
+ .B1(_1904_),
+ .B2(_1054_),
+ .X(_1905_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6118_ (.A1(_1901_),
+ .A2(_1394_),
+ .B1(_1902_),
+ .B2(_1329_),
+ .C1(_1905_),
+ .X(_1906_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6119_ (.A(_1890_),
+ .B(_1896_),
+ .C(_1900_),
+ .D(_1906_),
+ .X(_1907_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6120_ (.A(\gpio_configure[5][7] ),
+ .Y(_1908_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6121_ (.A(\gpio_configure[10][7] ),
+ .Y(_1909_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6122_ (.A(\gpio_configure[12][7] ),
+ .Y(_1910_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6123_ (.A(\gpio_configure[6][7] ),
+ .Y(_1911_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6124_ (.A1(_1910_),
+ .A2(_1259_),
+ .B1(_1911_),
+ .B2(_1146_),
+ .X(_1912_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6125_ (.A1(_1908_),
+ .A2(_1181_),
+ .B1(_1909_),
+ .B2(_1214_),
+ .C1(_1912_),
+ .X(_1913_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6126_ (.A(\gpio_configure[11][7] ),
+ .Y(_1914_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6127_ (.A(\gpio_configure[4][7] ),
+ .Y(_1915_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6128_ (.A(\gpio_configure[7][7] ),
+ .Y(_1916_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6129_ (.A(\gpio_configure[2][7] ),
+ .Y(_1917_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6130_ (.A1(_1916_),
+ .A2(_1149_),
+ .B1(_1917_),
+ .B2(_1253_),
+ .X(_1918_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6131_ (.A1(_1914_),
+ .A2(_1188_),
+ .B1(_1915_),
+ .B2(_1168_),
+ .C1(_1918_),
+ .X(_1919_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6132_ (.A(net60),
+ .Y(_1920_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6133_ (.A(\gpio_configure[35][7] ),
+ .Y(_1921_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6134_ (.A(_1218_),
+ .Y(_0083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6135_ (.A(_1235_),
+ .Y(_0080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_1 _6136_ (.A1(net42),
+ .A2(_0083_),
+ .B1(net51),
+ .B2(_0080_),
+ .Y(_1922_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6137_ (.A1(_1920_),
+ .A2(_1262_),
+ .B1(_1921_),
+ .B2(_1231_),
+ .C1(_1922_),
+ .X(_1923_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6138_ (.A(\gpio_configure[15][7] ),
+ .Y(_1924_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6139_ (.A(\gpio_configure[13][7] ),
+ .Y(_1925_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6140_ (.A(\gpio_configure[9][7] ),
+ .Y(_1926_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6141_ (.A(\gpio_configure[16][7] ),
+ .Y(_1927_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6142_ (.A1(_1926_),
+ .A2(_1220_),
+ .B1(_1927_),
+ .B2(_1222_),
+ .X(_1928_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6143_ (.A1(_1924_),
+ .A2(_1239_),
+ .B1(_1925_),
+ .B2(_1200_),
+ .C1(_1928_),
+ .X(_1929_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6144_ (.A(_1913_),
+ .B(_1919_),
+ .C(_1923_),
+ .D(_1929_),
+ .X(_1930_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4b_4 _6145_ (.A_N(_1859_),
+ .B(_1884_),
+ .C(_1907_),
+ .D(_1930_),
+ .Y(\hkspi.idata[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6146_ (.A(net196),
+ .Y(_1931_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _6147_ (.A(_1931_),
+ .B(_1786_),
+ .X(_1932_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _6148_ (.A(_1932_),
+ .X(_1933_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6149_ (.A(_1933_),
+ .Y(_1934_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6150_ (.A1(\hkspi.idata[7] ),
+ .A2(_1933_),
+ .B1(net351),
+ .B2(_1934_),
+ .X(_0293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6151_ (.A(\gpio_configure[35][6] ),
+ .Y(_1935_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6152_ (.A(\gpio_configure[18][6] ),
+ .Y(_1936_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6153_ (.A(net32),
+ .Y(_1937_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6154_ (.A(\gpio_configure[17][6] ),
+ .Y(_1938_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6155_ (.A1(_1937_),
+ .A2(_1348_),
+ .B1(_1938_),
+ .B2(_1284_),
+ .X(_1939_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6156_ (.A1(_1935_),
+ .A2(_1231_),
+ .B1(_1936_),
+ .B2(_1355_),
+ .C1(_1939_),
+ .X(_1940_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6157_ (.A(\gpio_configure[1][6] ),
+ .Y(_1941_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _6158_ (.A(_1065_),
+ .B(_1114_),
+ .X(_1942_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6159_ (.A(\gpio_configure[21][6] ),
+ .Y(_1943_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6160_ (.A(\gpio_configure[29][6] ),
+ .Y(_1944_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6161_ (.A1(_1943_),
+ .A2(_1394_),
+ .B1(_1944_),
+ .B2(_1334_),
+ .X(_1945_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _6162_ (.A1(_1941_),
+ .A2(_1249_),
+ .B1(_1942_),
+ .C1(_1945_),
+ .X(_1946_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6163_ (.A(\gpio_configure[36][6] ),
+ .Y(_1947_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6164_ (.A(\gpio_configure[19][6] ),
+ .Y(_1948_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6165_ (.A(_1177_),
+ .Y(_0085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_1 _6166_ (.A1(net69),
+ .A2(_0085_),
+ .B1(net50),
+ .B2(_0080_),
+ .Y(_1949_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6167_ (.A1(_1947_),
+ .A2(_1251_),
+ .B1(_1948_),
+ .B2(_1406_),
+ .C1(_1949_),
+ .X(_1950_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6168_ (.A(\gpio_configure[28][6] ),
+ .Y(_1951_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6169_ (.A(\gpio_configure[23][6] ),
+ .Y(_1952_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6170_ (.A(\gpio_configure[37][6] ),
+ .Y(_1953_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6171_ (.A(\gpio_configure[24][6] ),
+ .Y(_1954_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6172_ (.A1(_1953_),
+ .A2(_1212_),
+ .B1(_1954_),
+ .B2(_1325_),
+ .X(_1955_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6173_ (.A1(_1951_),
+ .A2(_1388_),
+ .B1(_1952_),
+ .B2(_1404_),
+ .C1(_1955_),
+ .X(_1956_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6174_ (.A(_1940_),
+ .B(_1946_),
+ .C(_1950_),
+ .D(_1956_),
+ .X(_1957_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6175_ (.A(\gpio_configure[9][6] ),
+ .Y(_1958_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6176_ (.A(\gpio_configure[16][6] ),
+ .Y(_1959_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6177_ (.A1(_1958_),
+ .A2(_1220_),
+ .B1(_1959_),
+ .B2(_1222_),
+ .X(_1960_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6178_ (.A(\gpio_configure[13][6] ),
+ .Y(_1961_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6179_ (.A(\gpio_configure[14][6] ),
+ .Y(_1962_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6180_ (.A1(_1961_),
+ .A2(_1200_),
+ .B1(_1962_),
+ .B2(_1206_),
+ .X(_1963_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6181_ (.A(\gpio_configure[15][6] ),
+ .Y(_1964_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6182_ (.A(\gpio_configure[11][6] ),
+ .Y(_1965_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6183_ (.A(\gpio_configure[12][6] ),
+ .Y(_1966_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6184_ (.A(\gpio_configure[10][6] ),
+ .Y(_1967_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6185_ (.A1(_1966_),
+ .A2(_1259_),
+ .B1(_1967_),
+ .B2(_1214_),
+ .X(_1968_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6186_ (.A1(_1964_),
+ .A2(_1239_),
+ .B1(_1965_),
+ .B2(_1188_),
+ .C1(_1968_),
+ .X(_1969_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _6187_ (.A(_1960_),
+ .B(_1963_),
+ .C(_1969_),
+ .X(_1970_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6188_ (.A(\gpio_configure[26][6] ),
+ .Y(_1971_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6189_ (.A(\gpio_configure[25][6] ),
+ .Y(_1972_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6190_ (.A(\gpio_configure[32][6] ),
+ .Y(_1973_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6191_ (.A1_N(net41),
+ .A2_N(_0083_),
+ .B1(_1973_),
+ .B2(_1312_),
+ .X(_1974_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6192_ (.A1(_1971_),
+ .A2(_1293_),
+ .B1(_1972_),
+ .B2(_1054_),
+ .C1(_1974_),
+ .X(_1975_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6193_ (.A(net59),
+ .Y(_1976_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6194_ (.A(\gpio_configure[8][6] ),
+ .Y(_1977_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6195_ (.A(\gpio_configure[30][6] ),
+ .Y(_1978_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6196_ (.A(\gpio_configure[22][6] ),
+ .Y(_1979_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6197_ (.A1(_1978_),
+ .A2(_1329_),
+ .B1(_1979_),
+ .B2(_1375_),
+ .X(_1980_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6198_ (.A1(_1976_),
+ .A2(_1262_),
+ .B1(_1977_),
+ .B2(_1196_),
+ .C1(_1980_),
+ .X(_1981_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6199_ (.A(\gpio_configure[27][6] ),
+ .Y(_1982_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6200_ (.A(\gpio_configure[31][6] ),
+ .Y(_1983_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6201_ (.A(\gpio_configure[33][6] ),
+ .Y(_1984_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6202_ (.A(net296),
+ .Y(_1985_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6203_ (.A1(_1984_),
+ .A2(_1224_),
+ .B1(_1985_),
+ .B2(_1106_),
+ .X(_1986_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6204_ (.A1(_1982_),
+ .A2(_1273_),
+ .B1(_1983_),
+ .B2(_1295_),
+ .C1(_1986_),
+ .X(_1987_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6205_ (.A(\gpio_configure[34][6] ),
+ .Y(_1988_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6206_ (.A(net9),
+ .Y(_1989_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6207_ (.A(net27),
+ .Y(_1990_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6208_ (.A(net18),
+ .Y(_1991_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6209_ (.A1(_1990_),
+ .A2(_1300_),
+ .B1(_1991_),
+ .B2(_1384_),
+ .X(_1992_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6210_ (.A1(_1988_),
+ .A2(_1155_),
+ .B1(_1989_),
+ .B2(_1874_),
+ .C1(_1992_),
+ .X(_1993_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6211_ (.A(_1975_),
+ .B(_1981_),
+ .C(_1987_),
+ .D(_1993_),
+ .X(_1994_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6212_ (.A(\gpio_configure[7][6] ),
+ .Y(_1995_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6213_ (.A(net308),
+ .Y(_1996_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6214_ (.A(net279),
+ .Y(_1997_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6215_ (.A(\gpio_configure[5][6] ),
+ .Y(_1998_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6216_ (.A1(_1997_),
+ .A2(_1101_),
+ .B1(_1998_),
+ .B2(_1181_),
+ .X(_1999_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6217_ (.A1(_1995_),
+ .A2(_1149_),
+ .B1(_1996_),
+ .B2(_1032_),
+ .C1(_1999_),
+ .X(_2000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6218_ (.A(\gpio_configure[4][6] ),
+ .Y(_2001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6219_ (.A(net107),
+ .Y(_2002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6220_ (.A(net288),
+ .Y(_2003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6221_ (.A(net98),
+ .Y(_2004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6222_ (.A1(_2003_),
+ .A2(_1096_),
+ .B1(_2004_),
+ .B2(_1370_),
+ .X(_2005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6223_ (.A1(_2001_),
+ .A2(_1168_),
+ .B1(_2002_),
+ .B2(_1319_),
+ .C1(_2005_),
+ .X(_2006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6224_ (.A(\gpio_configure[6][6] ),
+ .Y(_2007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6225_ (.A(\gpio_configure[20][6] ),
+ .Y(_2008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6226_ (.A(net322),
+ .Y(_2009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6227_ (.A(net116),
+ .Y(_2010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6228_ (.A1(_2009_),
+ .A2(_1071_),
+ .B1(_2010_),
+ .B2(_1310_),
+ .X(_2011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6229_ (.A1(_2007_),
+ .A2(_1146_),
+ .B1(_2008_),
+ .B2(_1392_),
+ .C1(_2011_),
+ .X(_2012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6230_ (.A(\gpio_configure[3][6] ),
+ .Y(_2013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6231_ (.A(\gpio_configure[0][6] ),
+ .Y(_2014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6232_ (.A(\gpio_configure[2][6] ),
+ .Y(_2015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6233_ (.A(net121),
+ .Y(_2016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6234_ (.A1(_2015_),
+ .A2(_1253_),
+ .B1(_2016_),
+ .B2(_1339_),
+ .X(_2017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6235_ (.A1(_2013_),
+ .A2(_1321_),
+ .B1(_2014_),
+ .B2(_1353_),
+ .C1(_2017_),
+ .X(_2018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _6236_ (.A(_2000_),
+ .B(_2006_),
+ .C(_2012_),
+ .D(_2018_),
+ .X(_2019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _6237_ (.A(_1957_),
+ .B(_1970_),
+ .C(_1994_),
+ .D(_2019_),
+ .Y(\hkspi.idata[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6238_ (.A1(_1933_),
+ .A2(\hkspi.idata[6] ),
+ .B1(net350),
+ .B2(_1934_),
+ .X(_0292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6239_ (.A(\gpio_configure[20][5] ),
+ .Y(_2020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6240_ (.A(\gpio_configure[23][5] ),
+ .Y(_2021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6241_ (.A(\gpio_configure[25][5] ),
+ .Y(_2022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6242_ (.A1(_2021_),
+ .A2(_1404_),
+ .B1(_2022_),
+ .B2(_1054_),
+ .X(_2023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6243_ (.A(net278),
+ .Y(_2024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6244_ (.A(\gpio_configure[29][5] ),
+ .Y(_2025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6245_ (.A(net25),
+ .Y(_2026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6246_ (.A(\gpio_configure[31][5] ),
+ .Y(_2027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6247_ (.A1(_2026_),
+ .A2(_1300_),
+ .B1(_2027_),
+ .B2(_1295_),
+ .X(_2028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6248_ (.A1(_2024_),
+ .A2(_1101_),
+ .B1(_2025_),
+ .B2(_1334_),
+ .C1(_2028_),
+ .X(_2029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6249_ (.A(net114),
+ .Y(_2030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6250_ (.A(\gpio_configure[0][5] ),
+ .Y(_2031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6251_ (.A(_1032_),
+ .Y(_2032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6252_ (.A(net106),
+ .Y(_2033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6253_ (.A1_N(net307),
+ .A2_N(_2032_),
+ .B1(_2033_),
+ .B2(_1319_),
+ .X(_2034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6254_ (.A1(_2030_),
+ .A2(_1310_),
+ .B1(_2031_),
+ .B2(_1353_),
+ .C1(_2034_),
+ .X(_2035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _6255_ (.A1(_2020_),
+ .A2(_1392_),
+ .B1(_2023_),
+ .C1(_2029_),
+ .D1(_2035_),
+ .X(_2036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6256_ (.A(\gpio_configure[30][5] ),
+ .Y(_2037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6257_ (.A(net31),
+ .Y(_2038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6258_ (.A(net295),
+ .Y(_2039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6259_ (.A(net8),
+ .Y(_2040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6260_ (.A1(_2039_),
+ .A2(_1106_),
+ .B1(_2040_),
+ .B2(_1874_),
+ .X(_2041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6261_ (.A1(_2037_),
+ .A2(_1329_),
+ .B1(_2038_),
+ .B2(_1348_),
+ .C1(_2041_),
+ .X(_2042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6262_ (.A(net17),
+ .Y(_2043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6263_ (.A(\gpio_configure[27][5] ),
+ .Y(_2044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6264_ (.A(\gpio_configure[32][5] ),
+ .Y(_2045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6265_ (.A(net262),
+ .Y(_2046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6266_ (.A1(_2045_),
+ .A2(_1312_),
+ .B1(_2046_),
+ .B2(_1110_),
+ .X(_2047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6267_ (.A1(_2043_),
+ .A2(_1384_),
+ .B1(_2044_),
+ .B2(_1273_),
+ .C1(_2047_),
+ .X(_2048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6268_ (.A(net321),
+ .Y(_2049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6269_ (.A(\gpio_configure[19][5] ),
+ .Y(_2050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6270_ (.A(net120),
+ .Y(_2051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6271_ (.A(\gpio_configure[28][5] ),
+ .Y(_2052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6272_ (.A1(_2051_),
+ .A2(_1339_),
+ .B1(_2052_),
+ .B2(_1388_),
+ .X(_2053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6273_ (.A1(_2049_),
+ .A2(_1071_),
+ .B1(_2050_),
+ .B2(_1406_),
+ .C1(_2053_),
+ .X(_2054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6274_ (.A(\gpio_configure[21][5] ),
+ .Y(_2055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6275_ (.A(\gpio_configure[24][5] ),
+ .Y(_2056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6276_ (.A(\gpio_configure[18][5] ),
+ .Y(_2057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6277_ (.A(\gpio_configure[17][5] ),
+ .Y(_2058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6278_ (.A1(_2057_),
+ .A2(_1355_),
+ .B1(_2058_),
+ .B2(_1284_),
+ .X(_2059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6279_ (.A1(_2055_),
+ .A2(_1394_),
+ .B1(_2056_),
+ .B2(_1325_),
+ .C1(_2059_),
+ .X(_2060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _6280_ (.A(_2042_),
+ .B(_2048_),
+ .C(_2054_),
+ .D(_2060_),
+ .X(_2061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6281_ (.A(net68),
+ .Y(_2062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6282_ (.A(\gpio_configure[2][5] ),
+ .Y(_2063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6283_ (.A(\gpio_configure[15][5] ),
+ .Y(_2064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6284_ (.A(\gpio_configure[8][5] ),
+ .Y(_2065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6285_ (.A1(_2064_),
+ .A2(_1239_),
+ .B1(_2065_),
+ .B2(_1196_),
+ .X(_2066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6286_ (.A1(_2062_),
+ .A2(_1177_),
+ .B1(_2063_),
+ .B2(_1253_),
+ .C1(_2066_),
+ .X(_2067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6287_ (.A(\gpio_configure[35][5] ),
+ .Y(_2068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6288_ (.A(\gpio_configure[10][5] ),
+ .Y(_2069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6289_ (.A(net287),
+ .Y(_2070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6290_ (.A(\gpio_configure[22][5] ),
+ .Y(_2071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6291_ (.A(\gpio_configure[26][5] ),
+ .Y(_2072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6292_ (.A(net97),
+ .Y(_2073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6293_ (.A1(_2072_),
+ .A2(_1293_),
+ .B1(_2073_),
+ .B2(_1370_),
+ .X(_2074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_4 _6294_ (.A1(_2070_),
+ .A2(_1096_),
+ .B1(_2071_),
+ .B2(_1375_),
+ .C1(_2074_),
+ .X(_2075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6295_ (.A1(_2068_),
+ .A2(_1231_),
+ .B1(_2069_),
+ .B2(_1214_),
+ .C1(_2075_),
+ .X(_2076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6296_ (.A(\gpio_configure[37][5] ),
+ .Y(_2077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6297_ (.A(\gpio_configure[5][5] ),
+ .Y(_2078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6298_ (.A(\gpio_configure[9][5] ),
+ .Y(_2079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6299_ (.A1_N(net49),
+ .A2_N(_0080_),
+ .B1(_2079_),
+ .B2(_1220_),
+ .X(_2080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6300_ (.A1(_2077_),
+ .A2(_1212_),
+ .B1(_2078_),
+ .B2(_1181_),
+ .C1(_2080_),
+ .X(_2081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6301_ (.A(\gpio_configure[11][5] ),
+ .Y(_2082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6302_ (.A(\gpio_configure[7][5] ),
+ .Y(_2083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6303_ (.A(\gpio_configure[3][5] ),
+ .Y(_2084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6304_ (.A(\gpio_configure[6][5] ),
+ .Y(_2085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6305_ (.A1(_2084_),
+ .A2(_1321_),
+ .B1(_2085_),
+ .B2(_1146_),
+ .X(_2086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6306_ (.A1(_2082_),
+ .A2(_1188_),
+ .B1(_2083_),
+ .B2(_1149_),
+ .C1(_2086_),
+ .X(_2087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6307_ (.A(_2067_),
+ .B(_2076_),
+ .C(_2081_),
+ .D(_2087_),
+ .X(_2088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6308_ (.A(\gpio_configure[12][5] ),
+ .Y(_2089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6309_ (.A(\gpio_configure[13][5] ),
+ .Y(_2090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6310_ (.A(\gpio_configure[33][5] ),
+ .Y(_2091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6311_ (.A(\gpio_configure[36][5] ),
+ .Y(_2092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6312_ (.A1(_2091_),
+ .A2(_1224_),
+ .B1(_2092_),
+ .B2(_1251_),
+ .X(_2093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6313_ (.A1(_2089_),
+ .A2(_1259_),
+ .B1(_2090_),
+ .B2(_1200_),
+ .C1(_2093_),
+ .X(_2094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6314_ (.A(\gpio_configure[1][5] ),
+ .Y(_2095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6315_ (.A(\gpio_configure[4][5] ),
+ .Y(_2096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6316_ (.A(\gpio_configure[14][5] ),
+ .Y(_2097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6317_ (.A(net40),
+ .Y(_2098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6318_ (.A1(_2097_),
+ .A2(_1206_),
+ .B1(_2098_),
+ .B2(_1218_),
+ .X(_2099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6319_ (.A1(_2095_),
+ .A2(_1249_),
+ .B1(_2096_),
+ .B2(_1168_),
+ .C1(_2099_),
+ .X(_2100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6320_ (.A(\gpio_configure[16][5] ),
+ .Y(_2101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6321_ (.A(\gpio_configure[34][5] ),
+ .Y(_2102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6322_ (.A(_1262_),
+ .Y(_0081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_4 _6323_ (.A1(net66),
+ .A2(_1159_),
+ .B1(net57),
+ .B2(_0081_),
+ .Y(_2103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6324_ (.A1(_2101_),
+ .A2(_1222_),
+ .B1(_2102_),
+ .B2(_1155_),
+ .C1(_2103_),
+ .X(_2104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_2 _6325_ (.A(_2094_),
+ .B(_2100_),
+ .C(_2104_),
+ .X(_2105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _6326_ (.A(_2036_),
+ .B(_2061_),
+ .C(_2088_),
+ .D(_2105_),
+ .Y(\hkspi.idata[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6327_ (.A1(_1933_),
+ .A2(\hkspi.idata[5] ),
+ .B1(net348),
+ .B2(_1934_),
+ .X(_0291_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6328_ (.A(\gpio_configure[19][4] ),
+ .Y(_2106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6329_ (.A(\gpio_configure[23][4] ),
+ .Y(_2107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6330_ (.A(\gpio_configure[24][12] ),
+ .Y(_2108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6331_ (.A(\gpio_configure[6][12] ),
+ .Y(_2109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6332_ (.A1(_2108_),
+ .A2(_1282_),
+ .B1(_2109_),
+ .B2(_1255_),
+ .X(_2110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6333_ (.A1(_2106_),
+ .A2(_1406_),
+ .B1(_2107_),
+ .B2(_1404_),
+ .C1(_2110_),
+ .X(_2111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6334_ (.A(\gpio_configure[3][4] ),
+ .Y(_2112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6335_ (.A(\gpio_configure[34][12] ),
+ .Y(_2113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6336_ (.A(net96),
+ .Y(_2114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6337_ (.A(\gpio_configure[6][4] ),
+ .Y(_2115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6338_ (.A1(_2114_),
+ .A2(_1370_),
+ .B1(_2115_),
+ .B2(_1146_),
+ .X(_2116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6339_ (.A1(_2112_),
+ .A2(_1321_),
+ .B1(_2113_),
+ .B2(_1266_),
+ .C1(_2116_),
+ .X(_2117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6340_ (.A(\gpio_configure[28][12] ),
+ .Y(_2118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6341_ (.A(\gpio_configure[25][12] ),
+ .Y(_2119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6342_ (.A(net269),
+ .Y(_2120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6343_ (.A(\gpio_configure[36][12] ),
+ .Y(_2121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6344_ (.A1(_2120_),
+ .A2(_1115_),
+ .B1(_2121_),
+ .B2(_1243_),
+ .X(_2122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6345_ (.A1(_2118_),
+ .A2(_1361_),
+ .B1(_2119_),
+ .B2(_1288_),
+ .C1(_2122_),
+ .X(_2123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6346_ (.A(\gpio_configure[24][4] ),
+ .Y(_2124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6347_ (.A(\gpio_configure[23][12] ),
+ .Y(_2125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6348_ (.A(\gpio_configure[21][12] ),
+ .Y(_2126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6349_ (.A(\gpio_configure[28][4] ),
+ .Y(_2127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6350_ (.A1(_2126_),
+ .A2(_1377_),
+ .B1(_2127_),
+ .B2(_1388_),
+ .X(_2128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6351_ (.A1(_2124_),
+ .A2(_1325_),
+ .B1(_2125_),
+ .B2(_1408_),
+ .C1(_2128_),
+ .X(_2129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6352_ (.A(_2111_),
+ .B(_2117_),
+ .C(_2123_),
+ .D(_2129_),
+ .X(_2130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6353_ (.A(\gpio_configure[9][4] ),
+ .Y(_2131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6354_ (.A(\gpio_configure[0][12] ),
+ .Y(_2132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _6355_ (.A1(_2132_),
+ .A2(_1275_),
+ .B1(_1322_),
+ .C1(_1942_),
+ .X(_2133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6356_ (.A(\gpio_configure[37][4] ),
+ .Y(_2134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6357_ (.A(\gpio_configure[20][4] ),
+ .Y(_2135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _6358_ (.A1_N(serial_bb_clock),
+ .A2_N(_2032_),
+ .B1(_2135_),
+ .B2(_1392_),
+ .X(_2136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6359_ (.A1(net381),
+ .A2(_1177_),
+ .B1(_2134_),
+ .B2(_1212_),
+ .C1(_2136_),
+ .X(_2137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6360_ (.A(\gpio_configure[16][4] ),
+ .Y(_2138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6361_ (.A(\gpio_configure[16][12] ),
+ .Y(_2139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6362_ (.A(\gpio_configure[13][12] ),
+ .Y(_2140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6363_ (.A(\gpio_configure[17][12] ),
+ .Y(_2141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6364_ (.A1(_2140_),
+ .A2(_1209_),
+ .B1(_2141_),
+ .B2(_1142_),
+ .X(_2142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6365_ (.A1(_2138_),
+ .A2(_1222_),
+ .B1(_2139_),
+ .B2(_1198_),
+ .C1(_2142_),
+ .X(_2143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_2 _6366_ (.A1(_2131_),
+ .A2(_1220_),
+ .B1(_2133_),
+ .C1(_2137_),
+ .D1(_2143_),
+ .X(_2144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6367_ (.A(\gpio_configure[10][4] ),
+ .Y(_2145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6368_ (.A(\gpio_configure[12][4] ),
+ .Y(_2146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6369_ (.A(\gpio_configure[10][12] ),
+ .Y(_2147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6370_ (.A1(_2146_),
+ .A2(_1259_),
+ .B1(_2147_),
+ .B2(_1165_),
+ .X(_2148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6371_ (.A(\gpio_configure[13][4] ),
+ .Y(_2149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6372_ (.A(\gpio_configure[11][4] ),
+ .Y(_2150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6373_ (.A(\gpio_configure[11][12] ),
+ .Y(_2151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6374_ (.A(\gpio_configure[12][12] ),
+ .Y(_2152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6375_ (.A1(_2151_),
+ .A2(_1192_),
+ .B1(_2152_),
+ .B2(_1202_),
+ .X(_2153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6376_ (.A1(_2149_),
+ .A2(_1200_),
+ .B1(_2150_),
+ .B2(_1188_),
+ .C1(_2153_),
+ .X(_2154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6377_ (.A(\gpio_configure[14][4] ),
+ .Y(_2155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6378_ (.A(\gpio_configure[15][12] ),
+ .Y(_2156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6379_ (.A(\gpio_configure[14][12] ),
+ .Y(_2157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6380_ (.A(\gpio_configure[15][4] ),
+ .Y(_2158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6381_ (.A1(_2157_),
+ .A2(_1186_),
+ .B1(_2158_),
+ .B2(_1239_),
+ .X(_2159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6382_ (.A1(_2155_),
+ .A2(_1206_),
+ .B1(_2156_),
+ .B2(_1190_),
+ .C1(_2159_),
+ .X(_2160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _6383_ (.A1(_2145_),
+ .A2(_1214_),
+ .B1(_2148_),
+ .C1(_2154_),
+ .D1(_2160_),
+ .X(_2161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6384_ (.A(net286),
+ .Y(_2162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6385_ (.A(net16),
+ .Y(_2163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6386_ (.A(net7),
+ .Y(_2164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6387_ (.A(\gpio_configure[30][12] ),
+ .Y(_2165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6388_ (.A1(_2164_),
+ .A2(_1874_),
+ .B1(_2165_),
+ .B2(_1344_),
+ .X(_2166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6389_ (.A1(_2162_),
+ .A2(_1096_),
+ .B1(_2163_),
+ .B2(_1384_),
+ .C1(_2166_),
+ .X(_2167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6390_ (.A(\gpio_configure[30][4] ),
+ .Y(_2168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6391_ (.A(\gpio_configure[31][12] ),
+ .Y(_2169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6392_ (.A(\gpio_configure[33][4] ),
+ .Y(_2170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6393_ (.A(\gpio_configure[37][12] ),
+ .Y(_2171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6394_ (.A1(_2170_),
+ .A2(_1224_),
+ .B1(_2171_),
+ .B2(_1229_),
+ .X(_2172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6395_ (.A1(_2168_),
+ .A2(_1329_),
+ .B1(_2169_),
+ .B2(_1337_),
+ .C1(_2172_),
+ .X(_2173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6396_ (.A(\gpio_configure[22][4] ),
+ .Y(_2174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6397_ (.A(\gpio_configure[29][12] ),
+ .Y(_2175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6398_ (.A(\gpio_configure[17][4] ),
+ .Y(_2176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6399_ (.A(\gpio_configure[22][12] ),
+ .Y(_2177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6400_ (.A1(_2176_),
+ .A2(_1284_),
+ .B1(_2177_),
+ .B2(_1402_),
+ .X(_2178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6401_ (.A1(_2174_),
+ .A2(_1375_),
+ .B1(_2175_),
+ .B2(_1366_),
+ .C1(_2178_),
+ .X(_2179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6402_ (.A(\gpio_configure[27][4] ),
+ .Y(_2180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6403_ (.A(\gpio_configure[25][4] ),
+ .Y(_2181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6404_ (.A(\gpio_configure[19][12] ),
+ .Y(_2182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6405_ (.A(net277),
+ .Y(_2183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6406_ (.A1(_2182_),
+ .A2(_1396_),
+ .B1(_2183_),
+ .B2(_1101_),
+ .X(_2184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6407_ (.A1(_2180_),
+ .A2(_1273_),
+ .B1(_2181_),
+ .B2(_1054_),
+ .C1(_2184_),
+ .X(_2185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6408_ (.A(_2167_),
+ .B(_2173_),
+ .C(_2179_),
+ .D(_2185_),
+ .X(_2186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6409_ (.A(\gpio_configure[20][12] ),
+ .Y(_2187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6410_ (.A(\gpio_configure[36][4] ),
+ .Y(_2188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6411_ (.A(net24),
+ .Y(_2189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6412_ (.A(\gpio_configure[27][12] ),
+ .Y(_2190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6413_ (.A1(_2189_),
+ .A2(_1300_),
+ .B1(_2190_),
+ .B2(_1315_),
+ .X(_2191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6414_ (.A1(_2187_),
+ .A2(_1327_),
+ .B1(_2188_),
+ .B2(_1251_),
+ .C1(_2191_),
+ .X(_2192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6415_ (.A(\gpio_configure[21][4] ),
+ .Y(_2193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6416_ (.A(\gpio_configure[5][12] ),
+ .Y(_2194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6417_ (.A(\gpio_configure[32][12] ),
+ .Y(_2195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6418_ (.A(\gpio_configure[3][12] ),
+ .Y(_2196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6419_ (.A1(_2195_),
+ .A2(_1380_),
+ .B1(_2196_),
+ .B2(_1170_),
+ .X(_2197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6420_ (.A1(_2193_),
+ .A2(_1394_),
+ .B1(_2194_),
+ .B2(_1264_),
+ .C1(_2197_),
+ .X(_2198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6421_ (.A(\gpio_configure[18][4] ),
+ .Y(_2199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6422_ (.A(\gpio_configure[31][4] ),
+ .Y(_2200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6423_ (.A(\gpio_configure[33][12] ),
+ .Y(_2201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6424_ (.A(\gpio_configure[18][12] ),
+ .Y(_2202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6425_ (.A1(_2201_),
+ .A2(_1368_),
+ .B1(_2202_),
+ .B2(_1398_),
+ .X(_2203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6426_ (.A1(_2199_),
+ .A2(_1355_),
+ .B1(_2200_),
+ .B2(_1295_),
+ .C1(_2203_),
+ .X(_2204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6427_ (.A(\gpio_configure[29][4] ),
+ .Y(_2205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6428_ (.A(\gpio_configure[32][4] ),
+ .Y(_2206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6429_ (.A(\gpio_configure[26][12] ),
+ .Y(_2207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6430_ (.A(\gpio_configure[26][4] ),
+ .Y(_2208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6431_ (.A1(_2207_),
+ .A2(_1059_),
+ .B1(_2208_),
+ .B2(_1293_),
+ .X(_2209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6432_ (.A1(_2205_),
+ .A2(_1334_),
+ .B1(_2206_),
+ .B2(_1312_),
+ .C1(_2209_),
+ .X(_2210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6433_ (.A(_2192_),
+ .B(_2198_),
+ .C(_2204_),
+ .D(_2210_),
+ .X(_2211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6434_ (.A(\gpio_configure[8][12] ),
+ .Y(_2212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6435_ (.A(\gpio_configure[0][4] ),
+ .Y(_2213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6436_ (.A(\gpio_configure[34][4] ),
+ .Y(_2214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6437_ (.A1(_2213_),
+ .A2(_1353_),
+ .B1(_2214_),
+ .B2(_1155_),
+ .X(_2215_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6438_ (.A(net105),
+ .Y(_2216_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6439_ (.A(\gpio_configure[1][4] ),
+ .Y(_2217_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6440_ (.A(\gpio_configure[35][12] ),
+ .Y(_2218_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6441_ (.A(\gpio_configure[7][12] ),
+ .Y(_2219_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6442_ (.A1(_2218_),
+ .A2(_1151_),
+ .B1(_2219_),
+ .B2(_1179_),
+ .X(_2220_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6443_ (.A1(_2216_),
+ .A2(_1319_),
+ .B1(_2217_),
+ .B2(_1249_),
+ .C1(_2220_),
+ .X(_2221_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6444_ (.A(net113),
+ .Y(_2222_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6445_ (.A(\gpio_configure[1][12] ),
+ .Y(_2223_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_4 _6446_ (.A1(net56),
+ .A2(_0081_),
+ .B1(net65),
+ .B2(_1159_),
+ .Y(_2224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6447_ (.A1(_2222_),
+ .A2(_1310_),
+ .B1(_2223_),
+ .B2(_1302_),
+ .C1(_2224_),
+ .X(_2225_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _6448_ (.A1(_2212_),
+ .A2(_1174_),
+ .B1(_2215_),
+ .C1(_2221_),
+ .D1(_2225_),
+ .X(_2226_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6449_ (.A(net294),
+ .Y(_2227_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6450_ (.A(net48),
+ .Y(_2228_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6451_ (.A(net119),
+ .Y(_2229_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6452_ (.A(net261),
+ .Y(_2230_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6453_ (.A1(_2229_),
+ .A2(_1339_),
+ .B1(_2230_),
+ .B2(_1110_),
+ .X(_2231_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6454_ (.A1(_2227_),
+ .A2(_1106_),
+ .B1(_2228_),
+ .B2(_1235_),
+ .C1(_2231_),
+ .X(_2232_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6455_ (.A(net39),
+ .Y(_2233_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6456_ (.A(\gpio_configure[4][4] ),
+ .Y(_2234_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6457_ (.A(\gpio_configure[8][4] ),
+ .Y(_2235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6458_ (.A(\gpio_configure[4][12] ),
+ .Y(_2236_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6459_ (.A1(_2235_),
+ .A2(_1196_),
+ .B1(_2236_),
+ .B2(_1245_),
+ .X(_2237_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6460_ (.A1(_2233_),
+ .A2(_1218_),
+ .B1(_2234_),
+ .B2(_1168_),
+ .C1(_2237_),
+ .X(_2238_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6461_ (.A(\gpio_configure[35][4] ),
+ .Y(_2239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6462_ (.A(\gpio_configure[5][4] ),
+ .Y(_2240_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6463_ (.A(\gpio_configure[2][4] ),
+ .Y(_2241_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6464_ (.A(\gpio_configure[2][12] ),
+ .Y(_2242_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6465_ (.A1(_2241_),
+ .A2(_1253_),
+ .B1(_2242_),
+ .B2(_1157_),
+ .X(_2243_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6466_ (.A1(_2239_),
+ .A2(_1231_),
+ .B1(_2240_),
+ .B2(_1181_),
+ .C1(_2243_),
+ .X(_2244_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6467_ (.A(\gpio_configure[9][12] ),
+ .Y(_2245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6468_ (.A(\gpio_configure[7][4] ),
+ .Y(_2246_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6469_ (.A(net320),
+ .Y(_2247_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6470_ (.A(net30),
+ .Y(_2248_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6471_ (.A1(_2247_),
+ .A2(_1071_),
+ .B1(_2248_),
+ .B2(_1348_),
+ .X(_2249_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6472_ (.A1(_2245_),
+ .A2(_1241_),
+ .B1(_2246_),
+ .B2(_1149_),
+ .C1(_2249_),
+ .X(_2250_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6473_ (.A(_2232_),
+ .B(_2238_),
+ .C(_2244_),
+ .D(_2250_),
+ .X(_2251_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6474_ (.A(_2186_),
+ .B(_2211_),
+ .C(_2226_),
+ .D(_2251_),
+ .X(_2252_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_2 _6475_ (.A(_2130_),
+ .B(_2144_),
+ .C(_2161_),
+ .D(_2252_),
+ .Y(\hkspi.idata[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6476_ (.A1(_1933_),
+ .A2(\hkspi.idata[4] ),
+ .B1(net347),
+ .B2(_1934_),
+ .X(_0290_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6477_ (.A(\gpio_configure[12][11] ),
+ .Y(_2253_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6478_ (.A(\gpio_configure[13][3] ),
+ .Y(_4419_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6479_ (.A(\gpio_configure[6][11] ),
+ .Y(_2254_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6480_ (.A(\gpio_configure[36][11] ),
+ .Y(_2255_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6481_ (.A1(_2254_),
+ .A2(_1255_),
+ .B1(_2255_),
+ .B2(_1243_),
+ .X(_2256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6482_ (.A1(_2253_),
+ .A2(_1202_),
+ .B1(_4419_),
+ .B2(_1200_),
+ .C1(_2256_),
+ .X(_2257_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6483_ (.A(\gpio_configure[15][3] ),
+ .Y(_4421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6484_ (.A(\gpio_configure[16][11] ),
+ .Y(_2258_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6485_ (.A(\gpio_configure[36][3] ),
+ .Y(_0093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6486_ (.A(\gpio_configure[8][11] ),
+ .Y(_2259_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6487_ (.A1(_0093_),
+ .A2(_1251_),
+ .B1(_2259_),
+ .B2(_1174_),
+ .X(_2260_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6488_ (.A1(_4421_),
+ .A2(_1239_),
+ .B1(_2258_),
+ .B2(_1198_),
+ .C1(_2260_),
+ .X(_2261_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6489_ (.A(\gpio_configure[33][3] ),
+ .Y(_4439_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6490_ (.A(\gpio_configure[3][3] ),
+ .Y(_4409_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6491_ (.A(\gpio_configure[35][3] ),
+ .Y(_0094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6492_ (.A(\gpio_configure[10][3] ),
+ .Y(_4416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6493_ (.A1(_0094_),
+ .A2(_1231_),
+ .B1(_4416_),
+ .B2(_1214_),
+ .X(_2262_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6494_ (.A1(_4439_),
+ .A2(_1224_),
+ .B1(_4409_),
+ .B2(_1321_),
+ .C1(_2262_),
+ .X(_2263_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6495_ (.A(\gpio_configure[15][11] ),
+ .Y(_2264_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6496_ (.A(\gpio_configure[6][3] ),
+ .Y(_4412_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6497_ (.A(\gpio_configure[13][11] ),
+ .Y(_2265_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6498_ (.A(\gpio_configure[10][11] ),
+ .Y(_2266_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6499_ (.A1(_2265_),
+ .A2(_1209_),
+ .B1(_2266_),
+ .B2(_1165_),
+ .X(_2267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6500_ (.A1(_2264_),
+ .A2(_1190_),
+ .B1(_4412_),
+ .B2(_1146_),
+ .C1(_2267_),
+ .X(_2268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6501_ (.A(_2257_),
+ .B(_2261_),
+ .C(_2263_),
+ .D(_2268_),
+ .X(_2269_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6502_ (.A(\gpio_configure[12][3] ),
+ .Y(_4418_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6503_ (.A(\gpio_configure[34][11] ),
+ .Y(_2270_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6504_ (.A(\gpio_configure[9][11] ),
+ .Y(_2271_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6505_ (.A(net38),
+ .Y(_2272_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6506_ (.A1(_2271_),
+ .A2(_1241_),
+ .B1(_2272_),
+ .B2(_1218_),
+ .X(_2273_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6507_ (.A1(_4418_),
+ .A2(_1259_),
+ .B1(_2270_),
+ .B2(_1266_),
+ .C1(_2273_),
+ .X(_2274_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6508_ (.A(\gpio_configure[17][11] ),
+ .Y(_2275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6509_ (.A(\gpio_configure[16][3] ),
+ .Y(_4422_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6510_ (.A(\gpio_configure[14][11] ),
+ .Y(_2276_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6511_ (.A(\gpio_configure[11][3] ),
+ .Y(_4417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6512_ (.A1(_2276_),
+ .A2(_1186_),
+ .B1(_4417_),
+ .B2(_1188_),
+ .X(_2277_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6513_ (.A1(_2275_),
+ .A2(_1142_),
+ .B1(_4422_),
+ .B2(_1222_),
+ .C1(_2277_),
+ .X(_2278_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6514_ (.A(\gpio_configure[9][3] ),
+ .Y(_4415_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6515_ (.A(\gpio_configure[14][3] ),
+ .Y(_4420_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6516_ (.A(\gpio_configure[4][11] ),
+ .Y(_2279_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6517_ (.A(\gpio_configure[1][3] ),
+ .Y(_2280_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6518_ (.A1(_2279_),
+ .A2(_1245_),
+ .B1(_2280_),
+ .B2(_1249_),
+ .X(_2281_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6519_ (.A1(_4415_),
+ .A2(_1220_),
+ .B1(_4420_),
+ .B2(_1206_),
+ .C1(_2281_),
+ .X(_2282_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6520_ (.A(\gpio_configure[8][3] ),
+ .Y(_4414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6521_ (.A(net46),
+ .Y(_2283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6522_ (.A(\gpio_configure[37][11] ),
+ .Y(_2284_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6523_ (.A(\gpio_configure[2][3] ),
+ .Y(_4408_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6524_ (.A1(_2284_),
+ .A2(_1229_),
+ .B1(_4408_),
+ .B2(_1253_),
+ .X(_2285_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6525_ (.A1(_4414_),
+ .A2(_1196_),
+ .B1(_2283_),
+ .B2(_1235_),
+ .C1(_2285_),
+ .X(_2286_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6526_ (.A(_2274_),
+ .B(_2278_),
+ .C(_2282_),
+ .D(_2286_),
+ .X(_2287_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6527_ (.A(\gpio_configure[34][3] ),
+ .Y(_4440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6528_ (.A(\gpio_configure[7][11] ),
+ .Y(_2288_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6529_ (.A(\gpio_configure[3][11] ),
+ .Y(_2289_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6530_ (.A1(_2288_),
+ .A2(_1179_),
+ .B1(_2289_),
+ .B2(_1170_),
+ .X(_2290_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6531_ (.A(net55),
+ .Y(_2291_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6532_ (.A(\gpio_configure[7][3] ),
+ .Y(_4413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6533_ (.A(\gpio_configure[2][11] ),
+ .Y(_2292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6534_ (.A(net303),
+ .Y(_2293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6535_ (.A1(_2292_),
+ .A2(_1157_),
+ .B1(_2293_),
+ .B2(_1161_),
+ .X(_2294_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6536_ (.A1(_2291_),
+ .A2(_1262_),
+ .B1(_4413_),
+ .B2(_1149_),
+ .C1(_2294_),
+ .X(_2295_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6537_ (.A(\gpio_configure[4][3] ),
+ .Y(_4410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6538_ (.A(net64),
+ .Y(_2296_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6539_ (.A(\gpio_configure[5][11] ),
+ .Y(_2297_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6540_ (.A1_N(net67),
+ .A2_N(_0085_),
+ .B1(_2297_),
+ .B2(_1264_),
+ .X(_2298_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6541_ (.A1(_4410_),
+ .A2(_1168_),
+ .B1(_2296_),
+ .B2(_1158_),
+ .C1(_2298_),
+ .X(_2299_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _6542_ (.A1(_4440_),
+ .A2(_1155_),
+ .B1(_2290_),
+ .C1(_2295_),
+ .D1(_2299_),
+ .X(_2300_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6543_ (.A(\gpio_configure[31][11] ),
+ .Y(_2301_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6544_ (.A(\gpio_configure[0][3] ),
+ .Y(_0097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6545_ (.A(net268),
+ .Y(_2302_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6546_ (.A(net276),
+ .Y(_2303_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6547_ (.A1(_2302_),
+ .A2(_1115_),
+ .B1(_2303_),
+ .B2(_1101_),
+ .X(_2304_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6548_ (.A1(_2301_),
+ .A2(_1337_),
+ .B1(_0097_),
+ .B2(_1353_),
+ .C1(_2304_),
+ .X(_2305_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6549_ (.A(\gpio_configure[26][11] ),
+ .Y(_2306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6550_ (.A(\gpio_configure[28][11] ),
+ .Y(_2307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6551_ (.A(\gpio_configure[1][11] ),
+ .Y(_2308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6552_ (.A(net95),
+ .Y(_2309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6553_ (.A1(_2308_),
+ .A2(_1302_),
+ .B1(_2309_),
+ .B2(_1370_),
+ .X(_2310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6554_ (.A1(_2306_),
+ .A2(_1059_),
+ .B1(_2307_),
+ .B2(_1361_),
+ .C1(_2310_),
+ .X(_2311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6555_ (.A(\gpio_configure[18][11] ),
+ .Y(_2312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6556_ (.A(\gpio_configure[21][11] ),
+ .Y(_2313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6557_ (.A(\gpio_configure[33][11] ),
+ .Y(_2314_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6558_ (.A(net103),
+ .Y(_2315_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6559_ (.A1(_2314_),
+ .A2(_1368_),
+ .B1(_2315_),
+ .B2(_1319_),
+ .X(_2316_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6560_ (.A1(_2312_),
+ .A2(_1398_),
+ .B1(_2313_),
+ .B2(_1377_),
+ .C1(_2316_),
+ .X(_2317_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6561_ (.A(net112),
+ .Y(_2318_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_12 _6562_ (.A(\gpio_configure[30][3] ),
+ .Y(_4436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_8 _6563_ (.A(\gpio_configure[26][3] ),
+ .Y(_4432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6564_ (.A(net118),
+ .Y(_2319_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6565_ (.A1(_4432_),
+ .A2(_1293_),
+ .B1(_2319_),
+ .B2(_1339_),
+ .X(_2320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6566_ (.A1(_2318_),
+ .A2(_1310_),
+ .B1(_4436_),
+ .B2(_1329_),
+ .C1(_2320_),
+ .X(_2321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6567_ (.A(_2305_),
+ .B(_2311_),
+ .C(_2317_),
+ .D(_2321_),
+ .X(_2322_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6568_ (.A(\gpio_configure[29][3] ),
+ .Y(_4435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6569_ (.A(net293),
+ .Y(_2323_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6570_ (.A(net14),
+ .Y(_2324_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6571_ (.A(\gpio_configure[21][3] ),
+ .Y(_4427_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6572_ (.A1(_2324_),
+ .A2(_1384_),
+ .B1(_4427_),
+ .B2(_1394_),
+ .X(_2325_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6573_ (.A1(_4435_),
+ .A2(_1334_),
+ .B1(_2323_),
+ .B2(_1106_),
+ .C1(_2325_),
+ .X(_2326_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6574_ (.A(\gpio_configure[29][11] ),
+ .Y(_2327_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6575_ (.A(\gpio_configure[18][3] ),
+ .Y(_4424_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6576_ (.A(\gpio_configure[24][3] ),
+ .Y(_4430_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6577_ (.A(\gpio_configure[32][11] ),
+ .Y(_2328_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6578_ (.A1(_4430_),
+ .A2(_1325_),
+ .B1(_2328_),
+ .B2(_1380_),
+ .X(_2329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6579_ (.A1(_2327_),
+ .A2(_1366_),
+ .B1(_4424_),
+ .B2(_1355_),
+ .C1(_2329_),
+ .X(_2330_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6580_ (.A(\gpio_configure[5][3] ),
+ .Y(_4411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6581_ (.A(\gpio_configure[11][11] ),
+ .Y(_2331_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6582_ (.A(\gpio_configure[37][3] ),
+ .Y(_0092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6583_ (.A(\gpio_configure[35][11] ),
+ .Y(_2332_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6584_ (.A1(_0092_),
+ .A2(_1212_),
+ .B1(_2332_),
+ .B2(_1151_),
+ .X(_2333_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6585_ (.A1(_4411_),
+ .A2(_1181_),
+ .B1(_2331_),
+ .B2(_1192_),
+ .C1(_2333_),
+ .X(_2334_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _6586_ (.A(_2326_),
+ .B(_2330_),
+ .C(_2334_),
+ .X(_2335_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6587_ (.A(\gpio_configure[19][11] ),
+ .Y(_2336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6588_ (.A(\gpio_configure[23][3] ),
+ .Y(_4429_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6589_ (.A(\gpio_configure[22][11] ),
+ .Y(_2337_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6590_ (.A1(_4429_),
+ .A2(_1404_),
+ .B1(_2337_),
+ .B2(_1402_),
+ .X(_2338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6591_ (.A(net284),
+ .Y(_2339_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6592_ (.A(net6),
+ .Y(_2340_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6593_ (.A(net127),
+ .Y(_2341_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6594_ (.A(\gpio_configure[32][3] ),
+ .Y(_4438_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_4 _6595_ (.A1(_2341_),
+ .A2(_1346_),
+ .B1(_4438_),
+ .B2(_1312_),
+ .X(_2342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6596_ (.A1(_2339_),
+ .A2(_1096_),
+ .B1(_2340_),
+ .B2(_1874_),
+ .C1(_2342_),
+ .X(_2343_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6597_ (.A(\gpio_configure[27][11] ),
+ .Y(_2344_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_8 _6598_ (.A(\gpio_configure[27][3] ),
+ .Y(_4433_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6599_ (.A(net260),
+ .Y(_2345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6600_ (.A1_N(serial_bb_load),
+ .A2_N(_2032_),
+ .B1(_2345_),
+ .B2(_1110_),
+ .X(_2346_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6601_ (.A1(_2344_),
+ .A2(_1315_),
+ .B1(_4433_),
+ .B2(_1273_),
+ .C1(_2346_),
+ .X(_2347_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _6602_ (.A1(_2336_),
+ .A2(_1396_),
+ .B1(_2338_),
+ .C1(_2343_),
+ .D1(_2347_),
+ .X(_2348_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6603_ (.A(\gpio_configure[22][3] ),
+ .Y(_4428_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6604_ (.A(\gpio_configure[23][11] ),
+ .Y(_2349_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_8 _6605_ (.A(\gpio_configure[19][3] ),
+ .Y(_4425_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6606_ (.A(\gpio_configure[24][11] ),
+ .Y(_2350_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6607_ (.A1(_4425_),
+ .A2(_1406_),
+ .B1(_2350_),
+ .B2(_1282_),
+ .X(_2351_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6608_ (.A1(_4428_),
+ .A2(_1375_),
+ .B1(_2349_),
+ .B2(_1408_),
+ .C1(_2351_),
+ .X(_2352_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6609_ (.A(\gpio_configure[25][11] ),
+ .Y(_2353_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6610_ (.A(\gpio_configure[17][3] ),
+ .Y(_4423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6611_ (.A(\gpio_configure[20][3] ),
+ .Y(_4426_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6612_ (.A(\gpio_configure[20][11] ),
+ .Y(_2354_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6613_ (.A1(_4426_),
+ .A2(_1392_),
+ .B1(_2354_),
+ .B2(_1327_),
+ .X(_2355_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6614_ (.A1(_2353_),
+ .A2(_1288_),
+ .B1(_4423_),
+ .B2(_1284_),
+ .C1(_2355_),
+ .X(_2356_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6615_ (.A(\gpio_configure[30][11] ),
+ .Y(_2357_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_8 _6616_ (.A(\gpio_configure[31][3] ),
+ .Y(_4437_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6617_ (.A(\gpio_configure[0][11] ),
+ .Y(_2358_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6618_ (.A(net29),
+ .Y(_2359_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6619_ (.A1(_2358_),
+ .A2(_1275_),
+ .B1(_2359_),
+ .B2(_1348_),
+ .X(_2360_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6620_ (.A1(_2357_),
+ .A2(_1344_),
+ .B1(_4437_),
+ .B2(_1295_),
+ .C1(_2360_),
+ .X(_2361_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6621_ (.A(net319),
+ .Y(_2362_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_8 _6622_ (.A(\gpio_configure[28][3] ),
+ .Y(_4434_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6623_ (.A(\gpio_configure[25][3] ),
+ .Y(_4431_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6624_ (.A(net23),
+ .Y(_2363_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6625_ (.A1(_4431_),
+ .A2(_1054_),
+ .B1(_2363_),
+ .B2(_1300_),
+ .X(_2364_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6626_ (.A1(_2362_),
+ .A2(_1071_),
+ .B1(_4434_),
+ .B2(_1388_),
+ .C1(_2364_),
+ .X(_2365_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6627_ (.A(_2352_),
+ .B(_2356_),
+ .C(_2361_),
+ .D(_2365_),
+ .X(_2366_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _6628_ (.A(_2322_),
+ .B(_2335_),
+ .C(_2348_),
+ .D(_2366_),
+ .X(_2367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _6629_ (.A(_2269_),
+ .B(_2287_),
+ .C(_2300_),
+ .D(_2367_),
+ .Y(\hkspi.idata[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6630_ (.A1(_1933_),
+ .A2(\hkspi.idata[3] ),
+ .B1(net346),
+ .B2(_1934_),
+ .X(_0289_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6631_ (.A(\gpio_configure[15][2] ),
+ .Y(_2368_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6632_ (.A(\gpio_configure[16][10] ),
+ .Y(_2369_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6633_ (.A(\gpio_configure[14][2] ),
+ .Y(_2370_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6634_ (.A(\gpio_configure[14][10] ),
+ .Y(_2371_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6635_ (.A1(_2370_),
+ .A2(_1206_),
+ .B1(_2371_),
+ .B2(_1186_),
+ .X(_2372_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6636_ (.A1(_2368_),
+ .A2(_1239_),
+ .B1(_2369_),
+ .B2(_1198_),
+ .C1(_2372_),
+ .X(_2373_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6637_ (.A(\gpio_configure[10][2] ),
+ .Y(_2374_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6638_ (.A(\gpio_configure[12][10] ),
+ .Y(_2375_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6639_ (.A(\gpio_configure[11][2] ),
+ .Y(_2376_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6640_ (.A(\gpio_configure[11][10] ),
+ .Y(_2377_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6641_ (.A1(_2376_),
+ .A2(_1188_),
+ .B1(_2377_),
+ .B2(_1192_),
+ .X(_2378_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6642_ (.A1(_2374_),
+ .A2(_1214_),
+ .B1(_2375_),
+ .B2(_1202_),
+ .C1(_2378_),
+ .X(_2379_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6643_ (.A(\gpio_configure[12][2] ),
+ .Y(_2380_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6644_ (.A(\gpio_configure[9][2] ),
+ .Y(_2381_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6645_ (.A(\gpio_configure[13][10] ),
+ .Y(_2382_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6646_ (.A(\gpio_configure[10][10] ),
+ .Y(_2383_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6647_ (.A1(_2382_),
+ .A2(_1209_),
+ .B1(_2383_),
+ .B2(_1165_),
+ .X(_2384_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6648_ (.A1(_2380_),
+ .A2(_1259_),
+ .B1(_2381_),
+ .B2(_1220_),
+ .C1(_2384_),
+ .X(_2385_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _6649_ (.A(_2373_),
+ .B(_2379_),
+ .C(_2385_),
+ .X(_2386_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6650_ (.A(\gpio_configure[26][2] ),
+ .Y(_2387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6651_ (.A(net273),
+ .Y(_2388_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6652_ (.A(\gpio_configure[26][10] ),
+ .Y(_2389_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6653_ (.A(net63),
+ .Y(_2390_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6654_ (.A1(_2389_),
+ .A2(_1059_),
+ .B1(_2390_),
+ .B2(_1158_),
+ .X(_2391_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6655_ (.A1(_2387_),
+ .A2(_1293_),
+ .B1(_2388_),
+ .B2(_1110_),
+ .C1(_2391_),
+ .X(_2392_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6656_ (.A(net318),
+ .Y(_2393_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6657_ (.A(\gpio_configure[32][10] ),
+ .Y(_2394_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6658_ (.A(clk1_output_dest),
+ .Y(_2395_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6659_ (.A1(_1058_),
+ .A2(_1065_),
+ .B1(_2395_),
+ .B2(_1047_),
+ .C1(_1942_),
+ .X(_2396_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6660_ (.A1(_2393_),
+ .A2(_1071_),
+ .B1(_2394_),
+ .B2(_1380_),
+ .C1(_2396_),
+ .X(_2397_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6661_ (.A(\gpio_configure[16][2] ),
+ .Y(_2398_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6662_ (.A(\gpio_configure[17][10] ),
+ .Y(_2399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6663_ (.A(\gpio_configure[15][10] ),
+ .Y(_2400_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6664_ (.A(\gpio_configure[13][2] ),
+ .Y(_2401_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6665_ (.A1(_2400_),
+ .A2(_1190_),
+ .B1(_2401_),
+ .B2(_1200_),
+ .X(_2402_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6666_ (.A1(_2398_),
+ .A2(_1222_),
+ .B1(_2399_),
+ .B2(_1142_),
+ .C1(_2402_),
+ .X(_2403_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6667_ (.A(\gpio_configure[2][2] ),
+ .Y(_2404_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6668_ (.A(\gpio_configure[34][10] ),
+ .Y(_2405_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6669_ (.A(net111),
+ .Y(_2406_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6670_ (.A(net292),
+ .Y(_2407_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6671_ (.A1(_2406_),
+ .A2(_1310_),
+ .B1(_2407_),
+ .B2(_1106_),
+ .X(_2408_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6672_ (.A1(_2404_),
+ .A2(_1253_),
+ .B1(_2405_),
+ .B2(_1266_),
+ .C1(_2408_),
+ .X(_2409_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6673_ (.A(\gpio_configure[3][2] ),
+ .Y(_2410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6674_ (.A(\gpio_configure[8][10] ),
+ .Y(_2411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6675_ (.A(net267),
+ .Y(_2412_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6676_ (.A(net129),
+ .Y(_2413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6677_ (.A1(_2412_),
+ .A2(_1115_),
+ .B1(_2413_),
+ .B2(_1346_),
+ .X(_2414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6678_ (.A1(_2410_),
+ .A2(_1321_),
+ .B1(_2411_),
+ .B2(_1174_),
+ .C1(_2414_),
+ .X(_2415_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6679_ (.A(net115),
+ .Y(_2416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6680_ (.A(net54),
+ .Y(_2417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6681_ (.A(\gpio_configure[5][2] ),
+ .Y(_2418_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6682_ (.A(\gpio_configure[9][10] ),
+ .Y(_2419_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6683_ (.A1(_2418_),
+ .A2(_1181_),
+ .B1(_2419_),
+ .B2(_1241_),
+ .X(_2420_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6684_ (.A1(_2416_),
+ .A2(_1339_),
+ .B1(_2417_),
+ .B2(_1262_),
+ .C1(_2420_),
+ .X(_2421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6685_ (.A(\gpio_configure[3][10] ),
+ .Y(_2422_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6686_ (.A(\gpio_configure[34][2] ),
+ .Y(_2423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6687_ (.A(\gpio_configure[8][2] ),
+ .Y(_2424_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6688_ (.A1_N(net45),
+ .A2_N(_0080_),
+ .B1(_2424_),
+ .B2(_1196_),
+ .X(_2425_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6689_ (.A1(_2422_),
+ .A2(_1170_),
+ .B1(_2423_),
+ .B2(_1155_),
+ .C1(_2425_),
+ .X(_2426_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6690_ (.A(_2409_),
+ .B(_2415_),
+ .C(_2421_),
+ .D(_2426_),
+ .X(_2427_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6691_ (.A(_2392_),
+ .B(_2397_),
+ .C(_2403_),
+ .D(_2427_),
+ .X(_2428_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6692_ (.A(\gpio_configure[25][2] ),
+ .Y(_2429_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6693_ (.A(\gpio_configure[35][2] ),
+ .Y(_2430_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6694_ (.A(\gpio_configure[24][2] ),
+ .Y(_2431_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6695_ (.A(\gpio_configure[20][10] ),
+ .Y(_2432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6696_ (.A1(_2431_),
+ .A2(_1325_),
+ .B1(_2432_),
+ .B2(_1327_),
+ .X(_2433_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6697_ (.A1(_2429_),
+ .A2(_1054_),
+ .B1(_2430_),
+ .B2(_1231_),
+ .C1(_2433_),
+ .X(_2434_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6698_ (.A(serial_bb_resetn),
+ .Y(_2435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6699_ (.A(net275),
+ .Y(_2436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6700_ (.A(\gpio_configure[19][10] ),
+ .Y(_2437_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6701_ (.A(\gpio_configure[36][10] ),
+ .Y(_2438_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6702_ (.A1(_2437_),
+ .A2(_1396_),
+ .B1(_2438_),
+ .B2(_1243_),
+ .X(_2439_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_4 _6703_ (.A1(_2435_),
+ .A2(_1032_),
+ .B1(_2436_),
+ .B2(_1101_),
+ .C1(_2439_),
+ .X(_2440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6704_ (.A(\gpio_configure[30][2] ),
+ .Y(_2441_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6705_ (.A(\gpio_configure[30][10] ),
+ .Y(_2442_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6706_ (.A(net26),
+ .Y(_2443_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6707_ (.A(\gpio_configure[37][10] ),
+ .Y(_2444_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6708_ (.A1(_2443_),
+ .A2(_1348_),
+ .B1(_2444_),
+ .B2(_1229_),
+ .X(_2445_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6709_ (.A1(_2441_),
+ .A2(_1329_),
+ .B1(_2442_),
+ .B2(_1344_),
+ .C1(_2445_),
+ .X(_2446_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6710_ (.A(\gpio_configure[20][2] ),
+ .Y(_2447_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6711_ (.A(\gpio_configure[28][10] ),
+ .Y(_2448_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6712_ (.A(\gpio_configure[31][10] ),
+ .Y(_2449_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6713_ (.A(\gpio_configure[21][2] ),
+ .Y(_2450_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6714_ (.A1(_2449_),
+ .A2(_1337_),
+ .B1(_2450_),
+ .B2(_1394_),
+ .X(_2451_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6715_ (.A1(_2447_),
+ .A2(_1392_),
+ .B1(_2448_),
+ .B2(_1361_),
+ .C1(_2451_),
+ .X(_2452_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6716_ (.A(_2434_),
+ .B(_2440_),
+ .C(_2446_),
+ .D(_2452_),
+ .X(_2453_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6717_ (.A(\gpio_configure[29][2] ),
+ .Y(_2454_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6718_ (.A(\gpio_configure[18][10] ),
+ .Y(_2455_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6719_ (.A(\gpio_configure[33][10] ),
+ .Y(_2456_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6720_ (.A(\gpio_configure[32][2] ),
+ .Y(_2457_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6721_ (.A1(_2456_),
+ .A2(_1368_),
+ .B1(_2457_),
+ .B2(_1312_),
+ .X(_2458_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6722_ (.A1(_2454_),
+ .A2(_1334_),
+ .B1(_2455_),
+ .B2(_1398_),
+ .C1(_2458_),
+ .X(_2459_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6723_ (.A(\gpio_configure[21][10] ),
+ .Y(_2460_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6724_ (.A(\gpio_configure[18][2] ),
+ .Y(_2461_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6725_ (.A(\gpio_configure[27][10] ),
+ .Y(_2462_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6726_ (.A(net22),
+ .Y(_2463_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6727_ (.A1(_2462_),
+ .A2(_1315_),
+ .B1(_2463_),
+ .B2(_1300_),
+ .X(_2464_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6728_ (.A1(_2460_),
+ .A2(_1377_),
+ .B1(_2461_),
+ .B2(_1355_),
+ .C1(_2464_),
+ .X(_2465_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6729_ (.A(\gpio_configure[22][10] ),
+ .Y(_2466_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6730_ (.A(\gpio_configure[29][10] ),
+ .Y(_2467_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6731_ (.A(\gpio_configure[4][10] ),
+ .Y(_2468_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6732_ (.A(\gpio_configure[2][10] ),
+ .Y(_2469_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6733_ (.A1(_2468_),
+ .A2(_1245_),
+ .B1(_2469_),
+ .B2(_1157_),
+ .X(_2470_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6734_ (.A1(_2466_),
+ .A2(_1402_),
+ .B1(_2467_),
+ .B2(_1366_),
+ .C1(_2470_),
+ .X(_2471_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6735_ (.A(\gpio_configure[28][2] ),
+ .Y(_2472_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6736_ (.A(\gpio_configure[22][2] ),
+ .Y(_2473_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6737_ (.A(\gpio_configure[17][2] ),
+ .Y(_2474_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6738_ (.A(\gpio_configure[36][2] ),
+ .Y(_2475_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6739_ (.A1(_2474_),
+ .A2(_1284_),
+ .B1(_2475_),
+ .B2(_1251_),
+ .X(_2476_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6740_ (.A1(_2472_),
+ .A2(_1388_),
+ .B1(_2473_),
+ .B2(_1375_),
+ .C1(_2476_),
+ .X(_2477_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6741_ (.A(_2459_),
+ .B(_2465_),
+ .C(_2471_),
+ .D(_2477_),
+ .X(_2478_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6742_ (.A(\gpio_configure[0][2] ),
+ .Y(_2479_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6743_ (.A(\gpio_configure[6][10] ),
+ .Y(_2480_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6744_ (.A(net102),
+ .Y(_2481_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6745_ (.A(\gpio_configure[1][10] ),
+ .Y(_2482_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6746_ (.A1(_2481_),
+ .A2(_1319_),
+ .B1(_2482_),
+ .B2(_1302_),
+ .X(_2483_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6747_ (.A1(_2479_),
+ .A2(_1353_),
+ .B1(_2480_),
+ .B2(_1255_),
+ .C1(_2483_),
+ .X(_2484_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6748_ (.A(\gpio_configure[37][2] ),
+ .Y(_2485_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6749_ (.A(net302),
+ .Y(_2486_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6750_ (.A(\gpio_configure[7][10] ),
+ .Y(_2487_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6751_ (.A1_N(net37),
+ .A2_N(_0083_),
+ .B1(_2487_),
+ .B2(_1179_),
+ .X(_2488_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6752_ (.A1(_2485_),
+ .A2(_1212_),
+ .B1(_2486_),
+ .B2(_1161_),
+ .C1(_2488_),
+ .X(_2489_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6753_ (.A(\gpio_configure[33][2] ),
+ .Y(_2490_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6754_ (.A(\gpio_configure[6][2] ),
+ .Y(_2491_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6755_ (.A(\gpio_configure[7][2] ),
+ .Y(_2492_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6756_ (.A(\gpio_configure[35][10] ),
+ .Y(_2493_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6757_ (.A1(_2492_),
+ .A2(_1149_),
+ .B1(_2493_),
+ .B2(_1151_),
+ .X(_2494_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6758_ (.A1(_2490_),
+ .A2(_1224_),
+ .B1(_2491_),
+ .B2(_1146_),
+ .C1(_2494_),
+ .X(_2495_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _6759_ (.A(_2484_),
+ .B(_2489_),
+ .C(_2495_),
+ .X(_2496_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6760_ (.A(\gpio_configure[23][2] ),
+ .Y(_2497_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6761_ (.A(\gpio_configure[27][2] ),
+ .Y(_2498_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6762_ (.A(\gpio_configure[25][10] ),
+ .Y(_2499_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6763_ (.A(\gpio_configure[31][2] ),
+ .Y(_2500_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6764_ (.A1(_2499_),
+ .A2(_1288_),
+ .B1(_2500_),
+ .B2(_1295_),
+ .X(_2501_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6765_ (.A1(_2497_),
+ .A2(_1404_),
+ .B1(_2498_),
+ .B2(_1273_),
+ .C1(_2501_),
+ .X(_2502_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6766_ (.A(net13),
+ .Y(_2503_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6767_ (.A(\gpio_configure[19][2] ),
+ .Y(_2504_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6768_ (.A(net283),
+ .Y(_2505_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6769_ (.A(net5),
+ .Y(_2506_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6770_ (.A1(_2505_),
+ .A2(_1096_),
+ .B1(_2506_),
+ .B2(_1874_),
+ .X(_2507_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6771_ (.A1(_2503_),
+ .A2(_1384_),
+ .B1(_2504_),
+ .B2(_1406_),
+ .C1(_2507_),
+ .X(_2508_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6772_ (.A(\gpio_configure[5][10] ),
+ .Y(_2509_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6773_ (.A(\gpio_configure[1][2] ),
+ .Y(_2510_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6774_ (.A(\gpio_configure[0][10] ),
+ .Y(_2511_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6775_ (.A(\gpio_configure[4][2] ),
+ .Y(_2512_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6776_ (.A1(_2511_),
+ .A2(_1275_),
+ .B1(_2512_),
+ .B2(_1168_),
+ .X(_2513_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6777_ (.A1(_2509_),
+ .A2(_1264_),
+ .B1(_2510_),
+ .B2(_1249_),
+ .C1(_2513_),
+ .X(_2514_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6778_ (.A(net94),
+ .Y(_2515_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6779_ (.A(\gpio_configure[24][10] ),
+ .Y(_2516_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6780_ (.A(\gpio_configure[23][10] ),
+ .Y(_2517_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6781_ (.A1(_2516_),
+ .A2(_1282_),
+ .B1(_2517_),
+ .B2(_1408_),
+ .X(_2518_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6782_ (.A1(_2515_),
+ .A2(_1370_),
+ .B1(_1422_),
+ .B2(_1177_),
+ .C1(_2518_),
+ .X(_2519_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _6783_ (.A(_2502_),
+ .B(_2508_),
+ .C(_2514_),
+ .D(_2519_),
+ .X(_2520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6784_ (.A(_2453_),
+ .B(_2478_),
+ .C(_2496_),
+ .D(_2520_),
+ .X(_2521_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _6785_ (.A(_2386_),
+ .B(_2428_),
+ .C(_2521_),
+ .Y(\hkspi.idata[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6786_ (.A1(_1933_),
+ .A2(\hkspi.idata[2] ),
+ .B1(net345),
+ .B2(_1934_),
+ .X(_0288_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6787_ (.A(\gpio_configure[30][1] ),
+ .Y(_2522_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6788_ (.A(\gpio_configure[24][1] ),
+ .Y(_2523_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6789_ (.A(net272),
+ .Y(_2524_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6790_ (.A(net317),
+ .Y(_2525_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_4 _6791_ (.A1(_2524_),
+ .A2(_1110_),
+ .B1(_2525_),
+ .B2(_1071_),
+ .X(_2526_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6792_ (.A1(_2522_),
+ .A2(_1329_),
+ .B1(_2523_),
+ .B2(_1325_),
+ .C1(_2526_),
+ .X(_2527_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6793_ (.A(\gpio_configure[17][1] ),
+ .Y(_2528_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6794_ (.A(net12),
+ .Y(_2529_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6795_ (.A(net324),
+ .Y(_2530_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6796_ (.A(net282),
+ .Y(_2531_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6797_ (.A1(_2530_),
+ .A2(_1076_),
+ .B1(_2531_),
+ .B2(_1096_),
+ .X(_2532_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6798_ (.A1(_2528_),
+ .A2(_1284_),
+ .B1(_2529_),
+ .B2(_1384_),
+ .C1(_2532_),
+ .X(_2533_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6799_ (.A(\gpio_configure[6][1] ),
+ .Y(_2534_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6800_ (.A(\gpio_configure[5][9] ),
+ .Y(_2535_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6801_ (.A(\gpio_configure[18][9] ),
+ .Y(_2536_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6802_ (.A(\gpio_configure[37][9] ),
+ .Y(_2537_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6803_ (.A1(_2536_),
+ .A2(_1398_),
+ .B1(_2537_),
+ .B2(_1229_),
+ .C1(_1942_),
+ .X(_2538_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6804_ (.A1(_2534_),
+ .A2(_1146_),
+ .B1(_2535_),
+ .B2(_1264_),
+ .C1(_2538_),
+ .X(_2539_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6805_ (.A(\gpio_configure[27][9] ),
+ .Y(_2540_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6806_ (.A(net101),
+ .Y(_2541_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6807_ (.A(clk2_output_dest),
+ .Y(_2542_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6808_ (.A(net124),
+ .Y(_2543_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6809_ (.A1(_2542_),
+ .A2(_1047_),
+ .B1(_2543_),
+ .B2(_1370_),
+ .X(_2544_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6810_ (.A1(_2540_),
+ .A2(_1315_),
+ .B1(_2541_),
+ .B2(_1319_),
+ .C1(_2544_),
+ .X(_2545_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6811_ (.A(net266),
+ .Y(_2546_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6812_ (.A(\gpio_configure[26][9] ),
+ .Y(_2547_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6813_ (.A(net15),
+ .Y(_2548_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6814_ (.A(net264),
+ .Y(_2549_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6815_ (.A1(_2548_),
+ .A2(_1348_),
+ .B1(_2549_),
+ .B2(_1120_),
+ .X(_2550_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6816_ (.A1(_2546_),
+ .A2(_1115_),
+ .B1(_2547_),
+ .B2(_1059_),
+ .C1(_2550_),
+ .X(_2551_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6817_ (.A(net110),
+ .Y(_2552_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6818_ (.A(\gpio_configure[31][1] ),
+ .Y(_2553_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6819_ (.A(\gpio_configure[32][1] ),
+ .Y(_2554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6820_ (.A(net104),
+ .Y(_2555_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6821_ (.A1(_2554_),
+ .A2(_1312_),
+ .B1(_2555_),
+ .B2(_1339_),
+ .X(_2556_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6822_ (.A1(_2552_),
+ .A2(_1310_),
+ .B1(_2553_),
+ .B2(_1295_),
+ .C1(_2556_),
+ .X(_2557_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6823_ (.A(\gpio_configure[26][1] ),
+ .Y(_2558_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6824_ (.A(\gpio_configure[30][9] ),
+ .Y(_2559_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6825_ (.A(\gpio_configure[29][1] ),
+ .Y(_2560_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6826_ (.A(\gpio_configure[32][9] ),
+ .Y(_2561_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6827_ (.A1(_2560_),
+ .A2(_1334_),
+ .B1(_2561_),
+ .B2(_1380_),
+ .X(_2562_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6828_ (.A1(_2558_),
+ .A2(_1293_),
+ .B1(_2559_),
+ .B2(_1344_),
+ .C1(_2562_),
+ .X(_2563_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6829_ (.A(_2545_),
+ .B(_2551_),
+ .C(_2557_),
+ .D(_2563_),
+ .X(_2564_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6830_ (.A(_2527_),
+ .B(_2533_),
+ .C(_2539_),
+ .D(_2564_),
+ .X(_2565_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6831_ (.A(net21),
+ .Y(_2566_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _6832_ (.A(\gpio_configure[28][1] ),
+ .Y(_2567_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6833_ (.A(\gpio_configure[1][9] ),
+ .Y(_2568_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6834_ (.A(net285),
+ .Y(_2569_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6835_ (.A1(_2568_),
+ .A2(_1302_),
+ .B1(_2569_),
+ .B2(_1106_),
+ .X(_2570_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6836_ (.A1(_2566_),
+ .A2(_1300_),
+ .B1(_2567_),
+ .B2(_1388_),
+ .C1(_2570_),
+ .X(_2571_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6837_ (.A(\gpio_configure[0][9] ),
+ .Y(_2572_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6838_ (.A(\gpio_configure[0][1] ),
+ .Y(_2573_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6839_ (.A(net291),
+ .Y(_2574_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6840_ (.A(\gpio_configure[33][9] ),
+ .Y(_2575_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6841_ (.A1(_2574_),
+ .A2(_1092_),
+ .B1(_2575_),
+ .B2(_1368_),
+ .X(_2576_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6842_ (.A1(_2572_),
+ .A2(_1275_),
+ .B1(_2573_),
+ .B2(_1353_),
+ .C1(_2576_),
+ .X(_2577_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6843_ (.A(\gpio_configure[23][9] ),
+ .Y(_2578_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6844_ (.A(\gpio_configure[25][1] ),
+ .Y(_2579_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6845_ (.A(\gpio_configure[28][9] ),
+ .Y(_2580_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6846_ (.A1(_2579_),
+ .A2(_1054_),
+ .B1(_2580_),
+ .B2(_1361_),
+ .X(_2581_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6847_ (.A(net128),
+ .Y(_2582_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6848_ (.A(\gpio_configure[29][9] ),
+ .Y(_2583_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6849_ (.A(net35),
+ .Y(_2584_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_2 _6850_ (.A1_N(serial_bb_enable),
+ .A2_N(_2032_),
+ .B1(_2584_),
+ .B2(_1874_),
+ .X(_2585_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6851_ (.A1(_2582_),
+ .A2(_1346_),
+ .B1(_2583_),
+ .B2(_1366_),
+ .C1(_2585_),
+ .X(_2586_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _6852_ (.A1(_2578_),
+ .A2(_1408_),
+ .B1(_2581_),
+ .C1(_2586_),
+ .X(_2587_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6853_ (.A(\gpio_configure[21][1] ),
+ .Y(_2588_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6854_ (.A(\gpio_configure[23][1] ),
+ .Y(_2589_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6855_ (.A(\gpio_configure[20][1] ),
+ .Y(_2590_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6856_ (.A(\gpio_configure[31][9] ),
+ .Y(_2591_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6857_ (.A1(_2590_),
+ .A2(_1392_),
+ .B1(_2591_),
+ .B2(_1337_),
+ .X(_2592_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _6858_ (.A1(_2588_),
+ .A2(_1394_),
+ .B1(_2589_),
+ .B2(_1404_),
+ .C1(_2592_),
+ .X(_2593_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6859_ (.A(\gpio_configure[18][1] ),
+ .Y(_2594_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6860_ (.A(\gpio_configure[27][1] ),
+ .Y(_2595_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6861_ (.A(net299),
+ .Y(_2596_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6862_ (.A(irq_2_inputsrc),
+ .Y(_2597_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6863_ (.A1(_2596_),
+ .A2(_1101_),
+ .B1(_2597_),
+ .B2(_1304_),
+ .X(_2598_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6864_ (.A1(_2594_),
+ .A2(_1355_),
+ .B1(_2595_),
+ .B2(_1273_),
+ .C1(_2598_),
+ .X(_2599_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6865_ (.A(\gpio_configure[22][1] ),
+ .Y(_2600_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6866_ (.A(\gpio_configure[22][9] ),
+ .Y(_2601_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6867_ (.A(\gpio_configure[20][9] ),
+ .Y(_2602_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6868_ (.A(\gpio_configure[25][9] ),
+ .Y(_2603_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6869_ (.A1(_2602_),
+ .A2(_1327_),
+ .B1(_2603_),
+ .B2(_1288_),
+ .X(_2604_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6870_ (.A1(_2600_),
+ .A2(_1375_),
+ .B1(_2601_),
+ .B2(_1402_),
+ .C1(_2604_),
+ .X(_2605_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6871_ (.A(\gpio_configure[19][1] ),
+ .Y(_2606_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6872_ (.A(\gpio_configure[19][9] ),
+ .Y(_2607_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6873_ (.A(\gpio_configure[21][9] ),
+ .Y(_2608_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6874_ (.A(\gpio_configure[24][9] ),
+ .Y(_2609_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6875_ (.A1(_2608_),
+ .A2(_1377_),
+ .B1(_2609_),
+ .B2(_1282_),
+ .X(_2610_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6876_ (.A1(_2606_),
+ .A2(_1406_),
+ .B1(_2607_),
+ .B2(_1396_),
+ .C1(_2610_),
+ .X(_2611_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6877_ (.A(_2593_),
+ .B(_2599_),
+ .C(_2605_),
+ .D(_2611_),
+ .X(_2612_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6878_ (.A(_2571_),
+ .B(_2577_),
+ .C(_2587_),
+ .D(_2612_),
+ .X(_2613_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6879_ (.A(\gpio_configure[10][1] ),
+ .Y(_2614_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6880_ (.A(\gpio_configure[15][1] ),
+ .Y(_2615_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22oi_1 _6881_ (.A1(net47),
+ .A2(_0085_),
+ .B1(net53),
+ .B2(_0081_),
+ .Y(_2616_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6882_ (.A1(_2614_),
+ .A2(_1214_),
+ .B1(_2615_),
+ .B2(_1239_),
+ .C1(_2616_),
+ .X(_2617_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6883_ (.A(\gpio_configure[9][9] ),
+ .Y(_2618_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6884_ (.A(\gpio_configure[36][1] ),
+ .Y(_2619_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6885_ (.A(\gpio_configure[36][9] ),
+ .Y(_2620_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6886_ (.A(net301),
+ .Y(_2621_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6887_ (.A1(_2620_),
+ .A2(_1243_),
+ .B1(_2621_),
+ .B2(_1161_),
+ .X(_2622_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6888_ (.A1(_2618_),
+ .A2(_1241_),
+ .B1(_2619_),
+ .B2(_1251_),
+ .C1(_2622_),
+ .X(_2623_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6889_ (.A(\gpio_configure[7][1] ),
+ .Y(_2624_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6890_ (.A(\gpio_configure[11][1] ),
+ .Y(_2625_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6891_ (.A(\gpio_configure[13][1] ),
+ .Y(_2626_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6892_ (.A(\gpio_configure[34][9] ),
+ .Y(_2627_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6893_ (.A1(_2626_),
+ .A2(_1200_),
+ .B1(_2627_),
+ .B2(_1266_),
+ .X(_2628_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6894_ (.A1(_2624_),
+ .A2(_1149_),
+ .B1(_2625_),
+ .B2(_1188_),
+ .C1(_2628_),
+ .X(_2629_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6895_ (.A(\gpio_configure[16][1] ),
+ .Y(_2630_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6896_ (.A(\gpio_configure[7][9] ),
+ .Y(_2631_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6897_ (.A(\gpio_configure[10][9] ),
+ .Y(_2632_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6898_ (.A(\gpio_configure[17][9] ),
+ .Y(_2633_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6899_ (.A1(_2632_),
+ .A2(_1165_),
+ .B1(_2633_),
+ .B2(_1142_),
+ .X(_2634_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6900_ (.A1(_2630_),
+ .A2(_1222_),
+ .B1(_2631_),
+ .B2(_1179_),
+ .C1(_2634_),
+ .X(_2635_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6901_ (.A(_2617_),
+ .B(_2623_),
+ .C(_2629_),
+ .D(_2635_),
+ .X(_2636_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _6902_ (.A(\gpio_configure[3][9] ),
+ .Y(_2637_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6903_ (.A(net44),
+ .Y(_2638_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6904_ (.A(\gpio_configure[35][9] ),
+ .Y(_2639_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6905_ (.A(\gpio_configure[33][1] ),
+ .Y(_2640_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6906_ (.A1(_2639_),
+ .A2(_1151_),
+ .B1(_2640_),
+ .B2(_1224_),
+ .X(_2641_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6907_ (.A1(_2637_),
+ .A2(_1170_),
+ .B1(_2638_),
+ .B2(_1235_),
+ .C1(_2641_),
+ .X(_2642_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6908_ (.A(\gpio_configure[1][1] ),
+ .Y(_2643_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _6909_ (.A(\gpio_configure[8][9] ),
+ .Y(_2644_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6910_ (.A(\gpio_configure[2][1] ),
+ .Y(_2645_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _6911_ (.A1_N(net62),
+ .A2_N(_1159_),
+ .B1(_2645_),
+ .B2(_1253_),
+ .X(_2646_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6912_ (.A1(_2643_),
+ .A2(_1249_),
+ .B1(_2644_),
+ .B2(_1174_),
+ .C1(_2646_),
+ .X(_2647_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6913_ (.A(\gpio_configure[3][1] ),
+ .Y(_2648_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6914_ (.A(\gpio_configure[37][1] ),
+ .Y(_2649_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6915_ (.A(\gpio_configure[34][1] ),
+ .Y(_2650_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6916_ (.A(\gpio_configure[35][1] ),
+ .Y(_2651_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6917_ (.A1(_2650_),
+ .A2(_1155_),
+ .B1(_2651_),
+ .B2(_1231_),
+ .X(_2652_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6918_ (.A1(_2648_),
+ .A2(_1321_),
+ .B1(_2649_),
+ .B2(_1212_),
+ .C1(_2652_),
+ .X(_2653_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6919_ (.A(\gpio_configure[4][1] ),
+ .Y(_2654_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6920_ (.A(\gpio_configure[8][1] ),
+ .Y(_2655_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6921_ (.A(\gpio_configure[5][1] ),
+ .Y(_2656_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6922_ (.A(\gpio_configure[6][9] ),
+ .Y(_2657_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6923_ (.A1(_2656_),
+ .A2(_1181_),
+ .B1(_2657_),
+ .B2(_1255_),
+ .X(_2658_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6924_ (.A1(_2654_),
+ .A2(_1168_),
+ .B1(_2655_),
+ .B2(_1196_),
+ .C1(_2658_),
+ .X(_2659_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _6925_ (.A(_2642_),
+ .B(_2647_),
+ .C(_2653_),
+ .D(_2659_),
+ .X(_2660_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6926_ (.A(\gpio_configure[14][1] ),
+ .Y(_2661_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6927_ (.A(\gpio_configure[13][9] ),
+ .Y(_2662_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6928_ (.A(\gpio_configure[14][9] ),
+ .Y(_2663_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6929_ (.A(\gpio_configure[4][9] ),
+ .Y(_2664_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6930_ (.A1(_2663_),
+ .A2(_1186_),
+ .B1(_2664_),
+ .B2(_1245_),
+ .X(_2665_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6931_ (.A1(_2661_),
+ .A2(_1206_),
+ .B1(_2662_),
+ .B2(_1209_),
+ .C1(_2665_),
+ .X(_2666_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6932_ (.A(\gpio_configure[11][9] ),
+ .Y(_2667_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6933_ (.A(\gpio_configure[9][1] ),
+ .Y(_2668_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6934_ (.A(\gpio_configure[15][9] ),
+ .Y(_2669_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6935_ (.A(\gpio_configure[12][9] ),
+ .Y(_2670_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6936_ (.A1(_2669_),
+ .A2(_1190_),
+ .B1(_2670_),
+ .B2(_1202_),
+ .X(_2671_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6937_ (.A1(_2667_),
+ .A2(_1192_),
+ .B1(_2668_),
+ .B2(_1220_),
+ .C1(_2671_),
+ .X(_2672_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6938_ (.A(\gpio_configure[16][9] ),
+ .Y(_2673_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6939_ (.A(\gpio_configure[12][1] ),
+ .Y(_2674_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6940_ (.A(\gpio_configure[2][9] ),
+ .Y(_2675_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6941_ (.A(net72),
+ .Y(_2676_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6942_ (.A1(_2675_),
+ .A2(_1157_),
+ .B1(_2676_),
+ .B2(_1218_),
+ .X(_2677_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _6943_ (.A1(_2673_),
+ .A2(_1198_),
+ .B1(_2674_),
+ .B2(_1259_),
+ .C1(_2677_),
+ .X(_2678_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _6944_ (.A(_2666_),
+ .B(_2672_),
+ .C(_2678_),
+ .X(_2679_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_2 _6945_ (.A(_2636_),
+ .B(_2660_),
+ .C(_2679_),
+ .X(_2680_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _6946_ (.A(_2565_),
+ .B(_2613_),
+ .C(_2680_),
+ .Y(\hkspi.idata[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6947_ (.A1(_1933_),
+ .A2(\hkspi.idata[1] ),
+ .B1(net344),
+ .B2(_1934_),
+ .X(_0287_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6948_ (.A1(_1413_),
+ .A2(_1933_),
+ .B1(net343),
+ .B2(_1934_),
+ .X(_0286_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6949_ (.A(\wbbd_state[4] ),
+ .Y(_2681_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _6950_ (.A(_1931_),
+ .B(_2681_),
+ .X(_2682_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _6951_ (.A(_2682_),
+ .X(_2683_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6952_ (.A(_2683_),
+ .Y(_2684_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6953_ (.A1(\hkspi.idata[7] ),
+ .A2(_2683_),
+ .B1(net342),
+ .B2(_2684_),
+ .X(_0285_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6954_ (.A1(\hkspi.idata[6] ),
+ .A2(_2683_),
+ .B1(net341),
+ .B2(_2684_),
+ .X(_0284_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6955_ (.A1(\hkspi.idata[5] ),
+ .A2(_2683_),
+ .B1(net340),
+ .B2(_2684_),
+ .X(_0283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6956_ (.A1(\hkspi.idata[4] ),
+ .A2(_2683_),
+ .B1(net339),
+ .B2(_2684_),
+ .X(_0282_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6957_ (.A1(\hkspi.idata[3] ),
+ .A2(_2683_),
+ .B1(net337),
+ .B2(_2684_),
+ .X(_0281_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6958_ (.A1(\hkspi.idata[2] ),
+ .A2(_2683_),
+ .B1(net336),
+ .B2(_2684_),
+ .X(_0280_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6959_ (.A1(\hkspi.idata[1] ),
+ .A2(_2683_),
+ .B1(net335),
+ .B2(_2684_),
+ .X(_0279_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6960_ (.A1(_1413_),
+ .A2(_2683_),
+ .B1(net334),
+ .B2(_2684_),
+ .X(_0278_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6961_ (.A(\wbbd_state[3] ),
+ .Y(_2685_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _6962_ (.A(_1931_),
+ .B(_2685_),
+ .X(_2686_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _6963_ (.A(_2686_),
+ .X(_2687_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6964_ (.A(_2687_),
+ .Y(_2688_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6965_ (.A1(\hkspi.idata[7] ),
+ .A2(_2687_),
+ .B1(net356),
+ .B2(_2688_),
+ .X(_0277_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6966_ (.A1(\hkspi.idata[6] ),
+ .A2(_2687_),
+ .B1(net355),
+ .B2(_2688_),
+ .X(_0276_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6967_ (.A1(\hkspi.idata[5] ),
+ .A2(_2687_),
+ .B1(net354),
+ .B2(_2688_),
+ .X(_0275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6968_ (.A1(\hkspi.idata[4] ),
+ .A2(_2687_),
+ .B1(net353),
+ .B2(_2688_),
+ .X(_0274_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6969_ (.A1(\hkspi.idata[3] ),
+ .A2(_2687_),
+ .B1(net352),
+ .B2(_2688_),
+ .X(_0273_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6970_ (.A1(\hkspi.idata[2] ),
+ .A2(_2687_),
+ .B1(net349),
+ .B2(_2688_),
+ .X(_0272_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6971_ (.A1(\hkspi.idata[1] ),
+ .A2(_2687_),
+ .B1(net338),
+ .B2(_2688_),
+ .X(_0271_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6972_ (.A1(_1413_),
+ .A2(_2687_),
+ .B1(net327),
+ .B2(_2688_),
+ .X(_0270_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6973_ (.A(\wbbd_state[2] ),
+ .Y(_2689_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _6974_ (.A(_2689_),
+ .B(_1931_),
+ .X(_2690_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _6975_ (.A(_2690_),
+ .X(_2691_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _6976_ (.A(_2691_),
+ .Y(_2692_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6977_ (.A1(\hkspi.idata[7] ),
+ .A2(_2691_),
+ .B1(net333),
+ .B2(_2692_),
+ .X(_0269_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6978_ (.A1(\hkspi.idata[6] ),
+ .A2(_2691_),
+ .B1(net332),
+ .B2(_2692_),
+ .X(_0268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6979_ (.A1(\hkspi.idata[5] ),
+ .A2(_2691_),
+ .B1(net331),
+ .B2(_2692_),
+ .X(_0267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _6980_ (.A1(\hkspi.idata[4] ),
+ .A2(_2691_),
+ .B1(net330),
+ .B2(_2692_),
+ .X(_0266_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6981_ (.A1(\hkspi.idata[3] ),
+ .A2(_2691_),
+ .B1(net329),
+ .B2(_2692_),
+ .X(_0265_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6982_ (.A1(\hkspi.idata[2] ),
+ .A2(_2691_),
+ .B1(net328),
+ .B2(_2692_),
+ .X(_0264_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6983_ (.A1(\hkspi.idata[1] ),
+ .A2(_2691_),
+ .B1(net358),
+ .B2(_2692_),
+ .X(_0263_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _6984_ (.A1(_1413_),
+ .A2(_2691_),
+ .B1(net357),
+ .B2(_2692_),
+ .X(_0262_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_4 _6985_ (.A1(\hkspi.wrstb ),
+ .A2(\hkspi.rdstb ),
+ .B1(_0079_),
+ .Y(_2693_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _6986_ (.A1(_1081_),
+ .A2(_2693_),
+ .B1(_1801_),
+ .Y(_0034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _6987_ (.A1(_1082_),
+ .A2(_2693_),
+ .B1(_2689_),
+ .Y(_0035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _6988_ (.A1(_1083_),
+ .A2(_2693_),
+ .B1(_2685_),
+ .Y(_0036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _6989_ (.A1(_1084_),
+ .A2(_2693_),
+ .B1(_2681_),
+ .Y(_0037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _6990_ (.A1(\hkspi.pre_pass_thru_user ),
+ .A2(_1834_),
+ .A3(_1426_),
+ .B1(\hkspi.state[1] ),
+ .X(_0029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6991_ (.A(serial_xfer),
+ .Y(_2694_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_1 _6992_ (.A1_N(_1666_),
+ .A2_N(_1733_),
+ .B1(\xfer_state[0] ),
+ .B2(_2694_),
+ .X(_0038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_2 _6993_ (.A1(\xfer_state[1] ),
+ .A2(net306),
+ .B1(\xfer_state[1] ),
+ .B2(_1672_),
+ .C1(\xfer_state[2] ),
+ .X(_0039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _6994_ (.A(_1708_),
+ .B(\pad_count_2[4] ),
+ .X(_2695_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _6995_ (.A(\pad_count_2[3] ),
+ .B(_1714_),
+ .C(_1726_),
+ .X(_2696_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _6996_ (.A(_2695_),
+ .B(_2696_),
+ .Y(_2697_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _6997_ (.A(_1665_),
+ .B(net306),
+ .C(_1672_),
+ .X(_2698_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_2 _6998_ (.A1(_1688_),
+ .A2(_2694_),
+ .B1(_2697_),
+ .B2(_2698_),
+ .Y(_0040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _6999__13 (.A(_2698_),
+ .Y(net391),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_2 _7000_ (.A1(\xfer_state[3] ),
+ .A2(_1733_),
+ .B1(_2697_),
+ .B2(net391),
+ .X(_0041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7001_ (.A(\wbbd_state[6] ),
+ .B(_1799_),
+ .X(_2700_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7002_ (.A(_2700_),
+ .X(_0033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_1 _7003_ (.A_N(_1423_),
+ .B_N(_1429_),
+ .C(_1138_),
+ .D(_0091_),
+ .X(_2701_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _7004_ (.A1(_1127_),
+ .A2(_1419_),
+ .A3(_1820_),
+ .B1(_0087_),
+ .B2(_2701_),
+ .X(_2702_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7005_ (.A(_2702_),
+ .Y(_0028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _7006_ (.A1(\hkspi.pre_pass_thru_mgmt ),
+ .A2(_1420_),
+ .A3(\hkspi.state[0] ),
+ .B1(\hkspi.state[4] ),
+ .X(_0032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _7007_ (.A1(_1425_),
+ .A2(_1426_),
+ .A3(_1834_),
+ .B1(\hkspi.state[3] ),
+ .B2(_1419_),
+ .X(_0031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7008_ (.A(_1419_),
+ .B(_1820_),
+ .X(_2703_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _7009_ (.A1(\hkspi.state[3] ),
+ .A2(_1420_),
+ .B1(\hkspi.state[2] ),
+ .B2(_2703_),
+ .X(_0030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7010_ (.A(\hkspi.pass_thru_mgmt_delay ),
+ .B(net75),
+ .Y(net253),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7011_ (.A(\hkspi.pass_thru_mgmt ),
+ .B(net75),
+ .Y(net251),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _7012_ (.A(\hkspi.pass_thru_mgmt_delay ),
+ .B_N(net86),
+ .X(_2704_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7013_ (.A(_2704_),
+ .X(net255),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7014_ (.A(net255),
+ .Y(net256),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7015_ (.A(\hkspi.pass_thru_mgmt ),
+ .B(net88),
+ .X(_2705_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7016_ (.A(_2705_),
+ .X(net259),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7017_ (.A(net259),
+ .Y(net258),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2b_1 _7018_ (.A_N(\hkspi.pass_thru_mgmt_delay ),
+ .B(net73),
+ .X(_2706_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7019_ (.A(_2706_),
+ .X(net312),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2b_1 _7020_ (.A_N(\hkspi.pass_thru_mgmt ),
+ .B(net74),
+ .X(_2707_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _7021_ (.A(_2707_),
+ .X(net313),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _7022_ (.A(net380),
+ .B(_1125_),
+ .Y(_0098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7023_ (.A(\pad_count_2[3] ),
+ .B(\pad_count_2[2] ),
+ .X(_2708_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7024_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_2708_),
+ .D(_2695_),
+ .X(_2709_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7025_ (.A(_2709_),
+ .X(_2710_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7026_ (.A(\pad_count_2[5] ),
+ .B(\pad_count_2[4] ),
+ .X(_2711_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7027_ (.A(_2711_),
+ .X(_2712_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7028_ (.A(_1712_),
+ .B(_2708_),
+ .X(_2713_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7029_ (.A(_2712_),
+ .B(_2713_),
+ .X(_2714_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7030_ (.A(_2714_),
+ .X(_2715_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7031_ (.A(_1727_),
+ .B(_2708_),
+ .X(_2716_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7032_ (.A(_2712_),
+ .B(_2716_),
+ .X(_2717_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7033_ (.A(_2717_),
+ .X(_2718_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7034_ (.A(_1726_),
+ .B(_2708_),
+ .X(_2719_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7035_ (.A(_2719_),
+ .B(_2712_),
+ .X(_2720_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7036_ (.A(_2720_),
+ .X(_2721_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7037_ (.A(_1713_),
+ .B(\pad_count_2[2] ),
+ .X(_2722_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7038_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_2722_),
+ .D(_2712_),
+ .X(_2723_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7039_ (.A(_2723_),
+ .X(_2724_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7040_ (.A(_2715_),
+ .B(_2718_),
+ .C(_2721_),
+ .D(_2724_),
+ .X(_2725_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7041_ (.A(_1716_),
+ .B(_2712_),
+ .X(_2726_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7042_ (.A(_1727_),
+ .B(_2722_),
+ .C(_2712_),
+ .X(_2727_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7043_ (.A(_2727_),
+ .X(_2728_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7044_ (.A(_2695_),
+ .B(_2719_),
+ .X(_2729_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7045_ (.A(_2729_),
+ .X(_2730_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7046_ (.A(_1726_),
+ .B(_2722_),
+ .C(_2712_),
+ .X(_2731_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7047_ (.A(_2731_),
+ .X(_2732_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7048_ (.A(_2726_),
+ .B(_2728_),
+ .C(_2730_),
+ .D(_2732_),
+ .X(_2733_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7049_ (.A(_1715_),
+ .B(_1726_),
+ .C(_2712_),
+ .X(_2734_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7050_ (.A(_2734_),
+ .X(_2735_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7051_ (.A(\pad_count_2[3] ),
+ .B(_1714_),
+ .C(_1727_),
+ .X(_2736_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7052_ (.A(_2695_),
+ .B(_2736_),
+ .X(_2737_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7053_ (.A(_2737_),
+ .X(_2738_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7054_ (.A(_2696_),
+ .B(_2712_),
+ .X(_2739_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7055_ (.A(_2739_),
+ .X(_2740_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7056_ (.A(\pad_count_2[3] ),
+ .B(_1714_),
+ .C(\pad_count_2[1] ),
+ .D(\pad_count_2[0] ),
+ .X(_2741_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7057_ (.A(_2712_),
+ .B(_2741_),
+ .X(_2742_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7058_ (.A(_2742_),
+ .X(_2743_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7059_ (.A(_2735_),
+ .B(_2738_),
+ .C(_2740_),
+ .D(_2743_),
+ .X(_2744_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7060_ (.A(_1712_),
+ .B(_2722_),
+ .C(_2712_),
+ .X(_2745_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7061_ (.A(_2745_),
+ .X(_2746_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7062_ (.A(_2695_),
+ .B(_2741_),
+ .X(_2747_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7063_ (.A(_2747_),
+ .X(_2748_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7064_ (.A(_2695_),
+ .B(_2716_),
+ .X(_2749_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7065_ (.A(_2749_),
+ .X(_2750_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7066_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_1715_),
+ .D(_2712_),
+ .X(_2751_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7067_ (.A(_2751_),
+ .X(_2752_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7068_ (.A(_2746_),
+ .B(_2748_),
+ .C(_2750_),
+ .D(_2752_),
+ .X(_2753_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7069_ (.A(_2712_),
+ .B(_2736_),
+ .X(_2754_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7070_ (.A(_2754_),
+ .X(_2755_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7071_ (.A(_1724_),
+ .B(_2712_),
+ .X(_2756_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7072_ (.A(_2756_),
+ .X(_2757_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7073_ (.A(_1715_),
+ .B(_1727_),
+ .C(_2712_),
+ .X(_2758_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7074_ (.A(_2758_),
+ .X(_2759_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7075_ (.A(_2695_),
+ .B(_2713_),
+ .X(_2760_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7076_ (.A(_2760_),
+ .X(_2761_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7077_ (.A(_2755_),
+ .B(_2757_),
+ .C(_2759_),
+ .D(_2761_),
+ .X(_2762_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7078_ (.A(_2733_),
+ .B(_2744_),
+ .C(_2753_),
+ .D(_2762_),
+ .X(_2763_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7079_ (.A(_1719_),
+ .B(_2710_),
+ .C(_2725_),
+ .D(_2763_),
+ .X(_2764_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7080_ (.A(_2764_),
+ .X(_0100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7081_ (.A(_1715_),
+ .B(_1727_),
+ .C(_1719_),
+ .X(_2765_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7082_ (.A(_2765_),
+ .X(_2766_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7083_ (.A(_1715_),
+ .B(_1726_),
+ .C(_1719_),
+ .X(_2767_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7084_ (.A(_2767_),
+ .X(_2768_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7085_ (.A(_1719_),
+ .B(_2736_),
+ .X(_2769_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7086_ (.A(_2769_),
+ .X(_2770_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7087_ (.A(_1719_),
+ .B(_2741_),
+ .X(_2771_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7088_ (.A(_2771_),
+ .X(_2772_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7089_ (.A1(_1393_),
+ .A2(_2770_),
+ .B1(_1391_),
+ .B2(_2772_),
+ .X(_2773_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7090_ (.A1(_1199_),
+ .A2(_2759_),
+ .B1(_1230_),
+ .B2(_2761_),
+ .C1(_2773_),
+ .X(_2774_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7091_ (.A1(_1333_),
+ .A2(_2766_),
+ .B1(_1328_),
+ .B2(_2768_),
+ .C1(_2774_),
+ .X(_2775_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7092_ (.A1(_1252_),
+ .A2(_2721_),
+ .B1(_1143_),
+ .B2(_2740_),
+ .X(_2776_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7093_ (.A1(_1219_),
+ .A2(_2728_),
+ .B1(_1180_),
+ .B2(_2755_),
+ .C1(_2776_),
+ .X(_2777_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7094_ (.A(_1719_),
+ .B(_2696_),
+ .X(_2778_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7095_ (.A(_2778_),
+ .X(_2779_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7096_ (.A(_1719_),
+ .B(_1724_),
+ .X(_2780_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7097_ (.A(_2780_),
+ .X(_2781_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7098_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_1715_),
+ .D(_1719_),
+ .X(_2782_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7099_ (.A(_2782_),
+ .X(_2783_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7100_ (.A1(_1403_),
+ .A2(_2781_),
+ .B1(_1387_),
+ .B2(_2783_),
+ .X(_2784_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7101_ (.A1(_1374_),
+ .A2(_2779_),
+ .B1(_1258_),
+ .B2(_2752_),
+ .C1(_2784_),
+ .X(_2785_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7102_ (.A1(_1311_),
+ .A2(_2710_),
+ .B1(_1205_),
+ .B2(_2735_),
+ .X(_2786_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7103_ (.A1(_1211_),
+ .A2(_2738_),
+ .B1(_1223_),
+ .B2(_2750_),
+ .C1(_2786_),
+ .X(_2787_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7104_ (.A(_1712_),
+ .B(_2722_),
+ .C(_1719_),
+ .X(_2788_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7105_ (.A(_2788_),
+ .X(_2789_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7106_ (.A1(_1187_),
+ .A2(_2746_),
+ .B1(_1272_),
+ .B2(_2789_),
+ .X(_2790_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7107_ (.A1(_1213_),
+ .A2(_2732_),
+ .B1(_1248_),
+ .B2(_2718_),
+ .C1(_2790_),
+ .X(_2791_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7108_ (.A(_2777_),
+ .B(_2785_),
+ .C(_2787_),
+ .D(_2791_),
+ .X(_2792_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7109_ (.A(_1719_),
+ .B(_2716_),
+ .X(_2793_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7110_ (.A(_2793_),
+ .X(_2794_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _7111_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_2708_),
+ .D(_1719_),
+ .X(_2795_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7112_ (.A(_2795_),
+ .X(_2796_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7113_ (.A1(_1221_),
+ .A2(_2796_),
+ .B1(_1147_),
+ .B2(_2757_),
+ .X(_2797_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7114_ (.A1(_1195_),
+ .A2(_2724_),
+ .B1(_1283_),
+ .B2(_2794_),
+ .C1(_2797_),
+ .X(_2798_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7115_ (.A(_1719_),
+ .B(_2719_),
+ .X(_2799_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7116_ (.A(_2799_),
+ .X(_2800_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7117_ (.A(\pad_count_2[1] ),
+ .B(\pad_count_2[0] ),
+ .C(_2722_),
+ .D(_1719_),
+ .X(_2801_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7118_ (.A(_2801_),
+ .X(_2802_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7119_ (.A1(_1324_),
+ .A2(_2802_),
+ .B1(_1154_),
+ .B2(_2730_),
+ .X(_2803_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7120_ (.A1(_1166_),
+ .A2(_2743_),
+ .B1(_1354_),
+ .B2(_2800_),
+ .C1(_2803_),
+ .X(_2804_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7121_ (.A(_1238_),
+ .B(_2726_),
+ .X(_2805_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7122_ (.A1(_1294_),
+ .A2(_1721_),
+ .B1(_1320_),
+ .B2(_2715_),
+ .C1(_2805_),
+ .X(_2806_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7123_ (.A(_1719_),
+ .B(_2713_),
+ .X(_2807_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7124_ (.A(_2807_),
+ .X(_2808_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7125_ (.A(_1726_),
+ .B(_2722_),
+ .C(_1719_),
+ .X(_2809_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7126_ (.A(_2809_),
+ .X(_2810_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7127_ (.A(_1727_),
+ .B(_2722_),
+ .C(_1719_),
+ .X(_2811_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7128_ (.A(_2811_),
+ .X(_2812_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7129_ (.A1(_1292_),
+ .A2(_2810_),
+ .B1(_1335_),
+ .B2(_2812_),
+ .X(_2813_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7130_ (.A1(_1405_),
+ .A2(_2808_),
+ .B1(_1250_),
+ .B2(_2748_),
+ .C1(_2813_),
+ .X(_2814_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7131_ (.A(_2798_),
+ .B(_2804_),
+ .C(_2806_),
+ .D(_2814_),
+ .X(_2815_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_4 _7132_ (.A(_2775_),
+ .B(_2792_),
+ .C(_2815_),
+ .X(_2816_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7133_ (.A(_2816_),
+ .X(_0101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7134_ (.A1(_2588_),
+ .A2(_2770_),
+ .B1(_2590_),
+ .B2(_2772_),
+ .X(_2817_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7135_ (.A1(_2626_),
+ .A2(_2759_),
+ .B1(_2651_),
+ .B2(_2761_),
+ .C1(_2817_),
+ .X(_2818_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7136_ (.A1(_2560_),
+ .A2(_2766_),
+ .B1(_2522_),
+ .B2(_2768_),
+ .C1(_2818_),
+ .X(_2819_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7137_ (.A1(_2645_),
+ .A2(_2721_),
+ .B1(_2534_),
+ .B2(_2740_),
+ .X(_2820_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7138_ (.A1(_2668_),
+ .A2(_2728_),
+ .B1(_2656_),
+ .B2(_2755_),
+ .C1(_2820_),
+ .X(_2821_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7139_ (.A1(_2589_),
+ .A2(_2781_),
+ .B1(_2567_),
+ .B2(_2783_),
+ .X(_2822_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7140_ (.A1(_2600_),
+ .A2(_2779_),
+ .B1(_2674_),
+ .B2(_2752_),
+ .C1(_2822_),
+ .X(_2823_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7141_ (.A1(_2554_),
+ .A2(_2710_),
+ .B1(_2661_),
+ .B2(_2735_),
+ .X(_2824_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7142_ (.A1(_2649_),
+ .A2(_2738_),
+ .B1(_2640_),
+ .B2(_2750_),
+ .C1(_2824_),
+ .X(_2825_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7143_ (.A1(_2625_),
+ .A2(_2746_),
+ .B1(_2595_),
+ .B2(_2789_),
+ .X(_2826_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7144_ (.A1(_2614_),
+ .A2(_2732_),
+ .B1(_2643_),
+ .B2(_2718_),
+ .C1(_2826_),
+ .X(_2827_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7145_ (.A(_2821_),
+ .B(_2823_),
+ .C(_2825_),
+ .D(_2827_),
+ .X(_2828_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7146_ (.A1(_2630_),
+ .A2(_2796_),
+ .B1(_2624_),
+ .B2(_2757_),
+ .X(_2829_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7147_ (.A1(_2655_),
+ .A2(_2724_),
+ .B1(_2528_),
+ .B2(_2794_),
+ .C1(_2829_),
+ .X(_2830_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7148_ (.A1(_2523_),
+ .A2(_2802_),
+ .B1(_2650_),
+ .B2(_2730_),
+ .X(_2831_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7149_ (.A1(_2654_),
+ .A2(_2743_),
+ .B1(_2594_),
+ .B2(_2800_),
+ .C1(_2831_),
+ .X(_2832_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7150_ (.A(_2615_),
+ .B(_2726_),
+ .X(_2833_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7151_ (.A1(_2553_),
+ .A2(_1721_),
+ .B1(_2648_),
+ .B2(_2715_),
+ .C1(_2833_),
+ .X(_2834_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7152_ (.A1(_2558_),
+ .A2(_2810_),
+ .B1(_2579_),
+ .B2(_2812_),
+ .X(_2835_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7153_ (.A1(_2606_),
+ .A2(_2808_),
+ .B1(_2619_),
+ .B2(_2748_),
+ .C1(_2835_),
+ .X(_2836_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7154_ (.A(_2830_),
+ .B(_2832_),
+ .C(_2834_),
+ .D(_2836_),
+ .X(_2837_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7155_ (.A(_2819_),
+ .B(_2828_),
+ .C(_2837_),
+ .Y(_0103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7156_ (.A1(_2450_),
+ .A2(_2770_),
+ .B1(_2447_),
+ .B2(_2772_),
+ .X(_2838_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7157_ (.A1(_2401_),
+ .A2(_2759_),
+ .B1(_2430_),
+ .B2(_2761_),
+ .C1(_2838_),
+ .X(_2839_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7158_ (.A1(_2454_),
+ .A2(_2766_),
+ .B1(_2441_),
+ .B2(_2768_),
+ .C1(_2839_),
+ .X(_2840_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7159_ (.A1(_2404_),
+ .A2(_2721_),
+ .B1(_2491_),
+ .B2(_2740_),
+ .X(_2841_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7160_ (.A1(_2381_),
+ .A2(_2728_),
+ .B1(_2418_),
+ .B2(_2755_),
+ .C1(_2841_),
+ .X(_2842_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7161_ (.A1(_2497_),
+ .A2(_2781_),
+ .B1(_2472_),
+ .B2(_2783_),
+ .X(_2843_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7162_ (.A1(_2473_),
+ .A2(_2779_),
+ .B1(_2380_),
+ .B2(_2752_),
+ .C1(_2843_),
+ .X(_2844_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7163_ (.A1(_2457_),
+ .A2(_2710_),
+ .B1(_2370_),
+ .B2(_2735_),
+ .X(_2845_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7164_ (.A1(_2485_),
+ .A2(_2738_),
+ .B1(_2490_),
+ .B2(_2750_),
+ .C1(_2845_),
+ .X(_2846_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7165_ (.A1(_2376_),
+ .A2(_2746_),
+ .B1(_2498_),
+ .B2(_2789_),
+ .X(_2847_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7166_ (.A1(_2374_),
+ .A2(_2732_),
+ .B1(_2510_),
+ .B2(_2718_),
+ .C1(_2847_),
+ .X(_2848_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7167_ (.A(_2842_),
+ .B(_2844_),
+ .C(_2846_),
+ .D(_2848_),
+ .X(_2849_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7168_ (.A1(_2398_),
+ .A2(_2796_),
+ .B1(_2492_),
+ .B2(_2757_),
+ .X(_2850_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7169_ (.A1(_2424_),
+ .A2(_2724_),
+ .B1(_2474_),
+ .B2(_2794_),
+ .C1(_2850_),
+ .X(_2851_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7170_ (.A1(_2431_),
+ .A2(_2802_),
+ .B1(_2423_),
+ .B2(_2730_),
+ .X(_2852_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7171_ (.A1(_2512_),
+ .A2(_2743_),
+ .B1(_2461_),
+ .B2(_2800_),
+ .C1(_2852_),
+ .X(_2853_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7172_ (.A(_2368_),
+ .B(_2726_),
+ .X(_2854_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7173_ (.A1(_2500_),
+ .A2(_1721_),
+ .B1(_2410_),
+ .B2(_2715_),
+ .C1(_2854_),
+ .X(_2855_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7174_ (.A1(_2387_),
+ .A2(_2810_),
+ .B1(_2429_),
+ .B2(_2812_),
+ .X(_2856_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7175_ (.A1(_2504_),
+ .A2(_2808_),
+ .B1(_2475_),
+ .B2(_2748_),
+ .C1(_2856_),
+ .X(_2857_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7176_ (.A(_2851_),
+ .B(_2853_),
+ .C(_2855_),
+ .D(_2857_),
+ .X(_2858_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7177_ (.A(_2840_),
+ .B(_2849_),
+ .C(_2858_),
+ .Y(_0105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7178_ (.A1(_4427_),
+ .A2(_2770_),
+ .B1(_4426_),
+ .B2(_2772_),
+ .X(_2859_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7179_ (.A1(_4419_),
+ .A2(_2759_),
+ .B1(_0094_),
+ .B2(_2761_),
+ .C1(_2859_),
+ .X(_2860_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7180_ (.A1(_4435_),
+ .A2(_2766_),
+ .B1(_4436_),
+ .B2(_2768_),
+ .C1(_2860_),
+ .X(_2861_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7181_ (.A1(_4408_),
+ .A2(_2721_),
+ .B1(_4412_),
+ .B2(_2740_),
+ .X(_2862_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7182_ (.A1(_4415_),
+ .A2(_2728_),
+ .B1(_4411_),
+ .B2(_2755_),
+ .C1(_2862_),
+ .X(_2863_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7183_ (.A1(_4429_),
+ .A2(_2781_),
+ .B1(_4434_),
+ .B2(_2783_),
+ .X(_2864_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7184_ (.A1(_4428_),
+ .A2(_2779_),
+ .B1(_4418_),
+ .B2(_2752_),
+ .C1(_2864_),
+ .X(_2865_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7185_ (.A1(_4438_),
+ .A2(_2710_),
+ .B1(_4420_),
+ .B2(_2735_),
+ .X(_2866_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7186_ (.A1(_0092_),
+ .A2(_2738_),
+ .B1(_4439_),
+ .B2(_2750_),
+ .C1(_2866_),
+ .X(_2867_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7187_ (.A1(_4417_),
+ .A2(_2746_),
+ .B1(_4433_),
+ .B2(_2789_),
+ .X(_2868_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7188_ (.A1(_4416_),
+ .A2(_2732_),
+ .B1(_2280_),
+ .B2(_2718_),
+ .C1(_2868_),
+ .X(_2869_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7189_ (.A(_2863_),
+ .B(_2865_),
+ .C(_2867_),
+ .D(_2869_),
+ .X(_2870_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7190_ (.A1(_4422_),
+ .A2(_2796_),
+ .B1(_4413_),
+ .B2(_2757_),
+ .X(_2871_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7191_ (.A1(_4414_),
+ .A2(_2724_),
+ .B1(_4423_),
+ .B2(_2794_),
+ .C1(_2871_),
+ .X(_2872_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7192_ (.A1(_4430_),
+ .A2(_2802_),
+ .B1(_4440_),
+ .B2(_2730_),
+ .X(_2873_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7193_ (.A1(_4410_),
+ .A2(_2743_),
+ .B1(_4424_),
+ .B2(_2800_),
+ .C1(_2873_),
+ .X(_2874_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7194_ (.A(_4421_),
+ .B(_2726_),
+ .X(_2875_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7195_ (.A1(_4437_),
+ .A2(_1721_),
+ .B1(_4409_),
+ .B2(_2715_),
+ .C1(_2875_),
+ .X(_2876_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7196_ (.A1(_4432_),
+ .A2(_2810_),
+ .B1(_4431_),
+ .B2(_2812_),
+ .X(_2877_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7197_ (.A1(_4425_),
+ .A2(_2808_),
+ .B1(_0093_),
+ .B2(_2748_),
+ .C1(_2877_),
+ .X(_2878_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7198_ (.A(_2872_),
+ .B(_2874_),
+ .C(_2876_),
+ .D(_2878_),
+ .X(_2879_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7199_ (.A(_2861_),
+ .B(_2870_),
+ .C(_2879_),
+ .Y(_0107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7200_ (.A1(_2193_),
+ .A2(_2770_),
+ .B1(_2135_),
+ .B2(_2772_),
+ .X(_2880_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7201_ (.A1(_2149_),
+ .A2(_2759_),
+ .B1(_2239_),
+ .B2(_2761_),
+ .C1(_2880_),
+ .X(_2881_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7202_ (.A1(_2205_),
+ .A2(_2766_),
+ .B1(_2168_),
+ .B2(_2768_),
+ .C1(_2881_),
+ .X(_2882_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7203_ (.A1(_2241_),
+ .A2(_2721_),
+ .B1(_2115_),
+ .B2(_2740_),
+ .X(_2883_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7204_ (.A1(_2131_),
+ .A2(_2728_),
+ .B1(_2240_),
+ .B2(_2755_),
+ .C1(_2883_),
+ .X(_2884_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7205_ (.A1(_2107_),
+ .A2(_2781_),
+ .B1(_2127_),
+ .B2(_2783_),
+ .X(_2885_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7206_ (.A1(_2174_),
+ .A2(_2779_),
+ .B1(_2146_),
+ .B2(_2752_),
+ .C1(_2885_),
+ .X(_2886_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7207_ (.A1(_2206_),
+ .A2(_2710_),
+ .B1(_2155_),
+ .B2(_2735_),
+ .X(_2887_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7208_ (.A1(_2134_),
+ .A2(_2738_),
+ .B1(_2170_),
+ .B2(_2750_),
+ .C1(_2887_),
+ .X(_2888_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7209_ (.A1(_2150_),
+ .A2(_2746_),
+ .B1(_2180_),
+ .B2(_2789_),
+ .X(_2889_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7210_ (.A1(_2145_),
+ .A2(_2732_),
+ .B1(_2217_),
+ .B2(_2718_),
+ .C1(_2889_),
+ .X(_2890_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7211_ (.A(_2884_),
+ .B(_2886_),
+ .C(_2888_),
+ .D(_2890_),
+ .X(_2891_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7212_ (.A1(_2138_),
+ .A2(_2796_),
+ .B1(_2246_),
+ .B2(_2757_),
+ .X(_2892_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7213_ (.A1(_2235_),
+ .A2(_2724_),
+ .B1(_2176_),
+ .B2(_2794_),
+ .C1(_2892_),
+ .X(_2893_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7214_ (.A1(_2124_),
+ .A2(_2802_),
+ .B1(_2214_),
+ .B2(_2730_),
+ .X(_2894_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7215_ (.A1(_2234_),
+ .A2(_2743_),
+ .B1(_2199_),
+ .B2(_2800_),
+ .C1(_2894_),
+ .X(_2895_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7216_ (.A(_2158_),
+ .B(_2726_),
+ .X(_2896_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7217_ (.A1(_2200_),
+ .A2(_1721_),
+ .B1(_2112_),
+ .B2(_2715_),
+ .C1(_2896_),
+ .X(_2897_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7218_ (.A1(_2208_),
+ .A2(_2810_),
+ .B1(_2181_),
+ .B2(_2812_),
+ .X(_2898_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7219_ (.A1(_2106_),
+ .A2(_2808_),
+ .B1(_2188_),
+ .B2(_2748_),
+ .C1(_2898_),
+ .X(_2899_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7220_ (.A(_2893_),
+ .B(_2895_),
+ .C(_2897_),
+ .D(_2899_),
+ .X(_2900_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7221_ (.A(_2882_),
+ .B(_2891_),
+ .C(_2900_),
+ .Y(_0109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7222_ (.A1(_2055_),
+ .A2(_2770_),
+ .B1(_2020_),
+ .B2(_2772_),
+ .X(_2901_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7223_ (.A1(_2090_),
+ .A2(_2759_),
+ .B1(_2068_),
+ .B2(_2761_),
+ .C1(_2901_),
+ .X(_2902_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7224_ (.A1(_2025_),
+ .A2(_2766_),
+ .B1(_2037_),
+ .B2(_2768_),
+ .C1(_2902_),
+ .X(_2903_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7225_ (.A1(_2063_),
+ .A2(_2721_),
+ .B1(_2085_),
+ .B2(_2740_),
+ .X(_2904_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7226_ (.A1(_2079_),
+ .A2(_2728_),
+ .B1(_2078_),
+ .B2(_2755_),
+ .C1(_2904_),
+ .X(_2905_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7227_ (.A1(_2021_),
+ .A2(_2781_),
+ .B1(_2052_),
+ .B2(_2783_),
+ .X(_2906_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7228_ (.A1(_2071_),
+ .A2(_2779_),
+ .B1(_2089_),
+ .B2(_2752_),
+ .C1(_2906_),
+ .X(_2907_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7229_ (.A1(_2045_),
+ .A2(_2710_),
+ .B1(_2097_),
+ .B2(_2735_),
+ .X(_2908_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7230_ (.A1(_2077_),
+ .A2(_2738_),
+ .B1(_2091_),
+ .B2(_2750_),
+ .C1(_2908_),
+ .X(_2909_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7231_ (.A1(_2082_),
+ .A2(_2746_),
+ .B1(_2044_),
+ .B2(_2789_),
+ .X(_2910_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7232_ (.A1(_2069_),
+ .A2(_2732_),
+ .B1(_2095_),
+ .B2(_2718_),
+ .C1(_2910_),
+ .X(_2911_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7233_ (.A(_2905_),
+ .B(_2907_),
+ .C(_2909_),
+ .D(_2911_),
+ .X(_2912_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7234_ (.A1(_2101_),
+ .A2(_2796_),
+ .B1(_2083_),
+ .B2(_2757_),
+ .X(_2913_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7235_ (.A1(_2065_),
+ .A2(_2724_),
+ .B1(_2058_),
+ .B2(_2794_),
+ .C1(_2913_),
+ .X(_2914_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7236_ (.A1(_2056_),
+ .A2(_2802_),
+ .B1(_2102_),
+ .B2(_2730_),
+ .X(_2915_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7237_ (.A1(_2096_),
+ .A2(_2743_),
+ .B1(_2057_),
+ .B2(_2800_),
+ .C1(_2915_),
+ .X(_2916_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7238_ (.A(_2064_),
+ .B(_2726_),
+ .X(_2917_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7239_ (.A1(_2027_),
+ .A2(_1721_),
+ .B1(_2084_),
+ .B2(_2715_),
+ .C1(_2917_),
+ .X(_2918_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7240_ (.A1(_2072_),
+ .A2(_2810_),
+ .B1(_2022_),
+ .B2(_2812_),
+ .X(_2919_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7241_ (.A1(_2050_),
+ .A2(_2808_),
+ .B1(_2092_),
+ .B2(_2748_),
+ .C1(_2919_),
+ .X(_2920_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7242_ (.A(_2914_),
+ .B(_2916_),
+ .C(_2918_),
+ .D(_2920_),
+ .X(_2921_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7243_ (.A(_2903_),
+ .B(_2912_),
+ .C(_2921_),
+ .Y(_0111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7244_ (.A1(_1943_),
+ .A2(_2770_),
+ .B1(_2008_),
+ .B2(_2772_),
+ .X(_2922_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7245_ (.A1(_1961_),
+ .A2(_2759_),
+ .B1(_1935_),
+ .B2(_2761_),
+ .C1(_2922_),
+ .X(_2923_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7246_ (.A1(_1944_),
+ .A2(_2766_),
+ .B1(_1978_),
+ .B2(_2768_),
+ .C1(_2923_),
+ .X(_2924_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7247_ (.A1(_2015_),
+ .A2(_2721_),
+ .B1(_2007_),
+ .B2(_2740_),
+ .X(_2925_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7248_ (.A1(_1958_),
+ .A2(_2728_),
+ .B1(_1998_),
+ .B2(_2755_),
+ .C1(_2925_),
+ .X(_2926_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7249_ (.A1(_1952_),
+ .A2(_2781_),
+ .B1(_1951_),
+ .B2(_2783_),
+ .X(_2927_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7250_ (.A1(_1979_),
+ .A2(_2779_),
+ .B1(_1966_),
+ .B2(_2752_),
+ .C1(_2927_),
+ .X(_2928_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7251_ (.A1(_1973_),
+ .A2(_2710_),
+ .B1(_1962_),
+ .B2(_2735_),
+ .X(_2929_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7252_ (.A1(_1953_),
+ .A2(_2738_),
+ .B1(_1984_),
+ .B2(_2750_),
+ .C1(_2929_),
+ .X(_2930_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7253_ (.A1(_1965_),
+ .A2(_2746_),
+ .B1(_1982_),
+ .B2(_2789_),
+ .X(_2931_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7254_ (.A1(_1967_),
+ .A2(_2732_),
+ .B1(_1941_),
+ .B2(_2718_),
+ .C1(_2931_),
+ .X(_2932_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7255_ (.A(_2926_),
+ .B(_2928_),
+ .C(_2930_),
+ .D(_2932_),
+ .X(_2933_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7256_ (.A1(_1959_),
+ .A2(_2796_),
+ .B1(_1995_),
+ .B2(_2757_),
+ .X(_2934_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7257_ (.A1(_1977_),
+ .A2(_2724_),
+ .B1(_1938_),
+ .B2(_2794_),
+ .C1(_2934_),
+ .X(_2935_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7258_ (.A1(_1954_),
+ .A2(_2802_),
+ .B1(_1988_),
+ .B2(_2730_),
+ .X(_2936_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7259_ (.A1(_2001_),
+ .A2(_2743_),
+ .B1(_1936_),
+ .B2(_2800_),
+ .C1(_2936_),
+ .X(_2937_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7260_ (.A(_1964_),
+ .B(_2726_),
+ .X(_2938_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7261_ (.A1(_1983_),
+ .A2(_1721_),
+ .B1(_2013_),
+ .B2(_2715_),
+ .C1(_2938_),
+ .X(_2939_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7262_ (.A1(_1971_),
+ .A2(_2810_),
+ .B1(_1972_),
+ .B2(_2812_),
+ .X(_2940_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7263_ (.A1(_1948_),
+ .A2(_2808_),
+ .B1(_1947_),
+ .B2(_2748_),
+ .C1(_2940_),
+ .X(_2941_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7264_ (.A(_2935_),
+ .B(_2937_),
+ .C(_2939_),
+ .D(_2941_),
+ .X(_2942_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7265_ (.A(_2924_),
+ .B(_2933_),
+ .C(_2942_),
+ .Y(_0113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7266_ (.A1(_1901_),
+ .A2(_2770_),
+ .B1(_1862_),
+ .B2(_2772_),
+ .X(_2943_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7267_ (.A1(_1925_),
+ .A2(_2759_),
+ .B1(_1921_),
+ .B2(_2761_),
+ .C1(_2943_),
+ .X(_2944_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7268_ (.A1(_1861_),
+ .A2(_2766_),
+ .B1(_1902_),
+ .B2(_2768_),
+ .C1(_2944_),
+ .X(_2945_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7269_ (.A1(_1917_),
+ .A2(_2721_),
+ .B1(_1911_),
+ .B2(_2740_),
+ .X(_2946_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7270_ (.A1(_1926_),
+ .A2(_2728_),
+ .B1(_1908_),
+ .B2(_2755_),
+ .C1(_2946_),
+ .X(_2947_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7271_ (.A1(_1898_),
+ .A2(_2781_),
+ .B1(_1867_),
+ .B2(_2783_),
+ .X(_2948_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7272_ (.A1(_1866_),
+ .A2(_2779_),
+ .B1(_1910_),
+ .B2(_2752_),
+ .C1(_2948_),
+ .X(_2949_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7273_ (.A1(_1891_),
+ .A2(_2710_),
+ .B1(_1854_),
+ .B2(_2735_),
+ .X(_2950_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7274_ (.A1(_1855_),
+ .A2(_2738_),
+ .B1(_1868_),
+ .B2(_2750_),
+ .C1(_2950_),
+ .X(_2951_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7275_ (.A1(_1914_),
+ .A2(_2746_),
+ .B1(_1871_),
+ .B2(_2789_),
+ .X(_2952_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7276_ (.A1(_1909_),
+ .A2(_2732_),
+ .B1(_1850_),
+ .B2(_2718_),
+ .C1(_2952_),
+ .X(_2953_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7277_ (.A(_2947_),
+ .B(_2949_),
+ .C(_2951_),
+ .D(_2953_),
+ .X(_2954_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7278_ (.A1(_1927_),
+ .A2(_2796_),
+ .B1(_1916_),
+ .B2(_2757_),
+ .X(_2955_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7279_ (.A1(_1853_),
+ .A2(_2724_),
+ .B1(_1886_),
+ .B2(_2794_),
+ .C1(_2955_),
+ .X(_2956_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7280_ (.A1(_1897_),
+ .A2(_2802_),
+ .B1(_1856_),
+ .B2(_2730_),
+ .X(_2957_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7281_ (.A1(_1915_),
+ .A2(_2743_),
+ .B1(_1879_),
+ .B2(_2800_),
+ .C1(_2957_),
+ .X(_2958_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7282_ (.A(_1924_),
+ .B(_2726_),
+ .X(_2959_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7283_ (.A1(_1860_),
+ .A2(_1721_),
+ .B1(_1847_),
+ .B2(_2715_),
+ .C1(_2959_),
+ .X(_2960_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7284_ (.A1(_1892_),
+ .A2(_2810_),
+ .B1(_1904_),
+ .B2(_2812_),
+ .X(_2961_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7285_ (.A1(_1878_),
+ .A2(_2808_),
+ .B1(_1849_),
+ .B2(_2748_),
+ .C1(_2961_),
+ .X(_2962_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7286_ (.A(_2956_),
+ .B(_2958_),
+ .C(_2960_),
+ .D(_2962_),
+ .X(_2963_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7287_ (.A(_2945_),
+ .B(_2954_),
+ .C(_2963_),
+ .Y(_0115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7288_ (.A1(_1376_),
+ .A2(_2770_),
+ .B1(_1326_),
+ .B2(_2772_),
+ .X(_2964_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7289_ (.A1(_1207_),
+ .A2(_2759_),
+ .B1(_1150_),
+ .B2(_2761_),
+ .C1(_2964_),
+ .X(_2965_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7290_ (.A1(_1365_),
+ .A2(_2766_),
+ .B1(_1343_),
+ .B2(_2768_),
+ .C1(_2965_),
+ .X(_2966_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7291_ (.A1(_1156_),
+ .A2(_2721_),
+ .B1(_1254_),
+ .B2(_2740_),
+ .X(_2967_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7292_ (.A1(_1240_),
+ .A2(_2728_),
+ .B1(_1263_),
+ .B2(_2755_),
+ .C1(_2967_),
+ .X(_2968_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7293_ (.A1(_1407_),
+ .A2(_2781_),
+ .B1(_1360_),
+ .B2(_2783_),
+ .X(_2969_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7294_ (.A1(_1401_),
+ .A2(_2779_),
+ .B1(_1201_),
+ .B2(_2752_),
+ .C1(_2969_),
+ .X(_2970_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7295_ (.A1(_1379_),
+ .A2(_2710_),
+ .B1(_1185_),
+ .B2(_2735_),
+ .X(_2971_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7296_ (.A1(_1228_),
+ .A2(_2738_),
+ .B1(_1367_),
+ .B2(_2750_),
+ .C1(_2971_),
+ .X(_2972_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7297_ (.A1(_1191_),
+ .A2(_2746_),
+ .B1(_1314_),
+ .B2(_2789_),
+ .X(_2973_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7298_ (.A1(_1164_),
+ .A2(_2732_),
+ .B1(_1301_),
+ .B2(_2718_),
+ .C1(_2973_),
+ .X(_2974_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7299_ (.A(_2968_),
+ .B(_2970_),
+ .C(_2972_),
+ .D(_2974_),
+ .X(_2975_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7300_ (.A1(_1197_),
+ .A2(_2796_),
+ .B1(_1178_),
+ .B2(_2757_),
+ .X(_2976_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7301_ (.A1(_1173_),
+ .A2(_2724_),
+ .B1(_1139_),
+ .B2(_2794_),
+ .C1(_2976_),
+ .X(_2977_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7302_ (.A1(_1279_),
+ .A2(_2802_),
+ .B1(_1265_),
+ .B2(_2730_),
+ .X(_2978_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7303_ (.A1(_1244_),
+ .A2(_2743_),
+ .B1(_1397_),
+ .B2(_2800_),
+ .C1(_2978_),
+ .X(_2979_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7304_ (.A(_1189_),
+ .B(_2726_),
+ .X(_2980_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7305_ (.A1(_1336_),
+ .A2(_1721_),
+ .B1(_1169_),
+ .B2(_2715_),
+ .C1(_2980_),
+ .X(_2981_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7306_ (.A1(_1359_),
+ .A2(_2810_),
+ .B1(_1287_),
+ .B2(_2812_),
+ .X(_2982_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7307_ (.A1(_1395_),
+ .A2(_2808_),
+ .B1(_1242_),
+ .B2(_2748_),
+ .C1(_2982_),
+ .X(_2983_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7308_ (.A(_2977_),
+ .B(_2979_),
+ .C(_2981_),
+ .D(_2983_),
+ .X(_2984_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7309_ (.A(_2966_),
+ .B(_2975_),
+ .C(_2984_),
+ .Y(_0117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7310_ (.A1(_2608_),
+ .A2(_2770_),
+ .B1(_2602_),
+ .B2(_2772_),
+ .X(_2985_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7311_ (.A1(_2662_),
+ .A2(_2759_),
+ .B1(_2639_),
+ .B2(_2761_),
+ .C1(_2985_),
+ .X(_2986_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7312_ (.A1(_2583_),
+ .A2(_2766_),
+ .B1(_2559_),
+ .B2(_2768_),
+ .C1(_2986_),
+ .X(_2987_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7313_ (.A1(_2675_),
+ .A2(_2721_),
+ .B1(_2657_),
+ .B2(_2740_),
+ .X(_2988_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7314_ (.A1(_2618_),
+ .A2(_2728_),
+ .B1(_2535_),
+ .B2(_2755_),
+ .C1(_2988_),
+ .X(_2989_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7315_ (.A1(_2578_),
+ .A2(_2781_),
+ .B1(_2580_),
+ .B2(_2783_),
+ .X(_2990_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7316_ (.A1(_2601_),
+ .A2(_2779_),
+ .B1(_2670_),
+ .B2(_2752_),
+ .C1(_2990_),
+ .X(_2991_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7317_ (.A1(_2561_),
+ .A2(_2710_),
+ .B1(_2663_),
+ .B2(_2735_),
+ .X(_2992_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7318_ (.A1(_2537_),
+ .A2(_2738_),
+ .B1(_2575_),
+ .B2(_2750_),
+ .C1(_2992_),
+ .X(_2993_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7319_ (.A1(_2667_),
+ .A2(_2746_),
+ .B1(_2540_),
+ .B2(_2789_),
+ .X(_2994_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7320_ (.A1(_2632_),
+ .A2(_2732_),
+ .B1(_2568_),
+ .B2(_2718_),
+ .C1(_2994_),
+ .X(_2995_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7321_ (.A(_2989_),
+ .B(_2991_),
+ .C(_2993_),
+ .D(_2995_),
+ .X(_2996_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7322_ (.A1(_2673_),
+ .A2(_2796_),
+ .B1(_2631_),
+ .B2(_2757_),
+ .X(_2997_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7323_ (.A1(_2644_),
+ .A2(_2724_),
+ .B1(_2633_),
+ .B2(_2794_),
+ .C1(_2997_),
+ .X(_2998_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7324_ (.A1(_2609_),
+ .A2(_2802_),
+ .B1(_2627_),
+ .B2(_2730_),
+ .X(_2999_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7325_ (.A1(_2664_),
+ .A2(_2743_),
+ .B1(_2536_),
+ .B2(_2800_),
+ .C1(_2999_),
+ .X(_3000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7326_ (.A(_2669_),
+ .B(_2726_),
+ .X(_3001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7327_ (.A1(_2591_),
+ .A2(_1721_),
+ .B1(_2637_),
+ .B2(_2715_),
+ .C1(_3001_),
+ .X(_3002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7328_ (.A1(_2547_),
+ .A2(_2810_),
+ .B1(_2603_),
+ .B2(_2812_),
+ .X(_3003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7329_ (.A1(_2607_),
+ .A2(_2808_),
+ .B1(_2620_),
+ .B2(_2748_),
+ .C1(_3003_),
+ .X(_3004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7330_ (.A(_2998_),
+ .B(_3000_),
+ .C(_3002_),
+ .D(_3004_),
+ .X(_3005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7331_ (.A(_2987_),
+ .B(_2996_),
+ .C(_3005_),
+ .Y(_0119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7332_ (.A1(_2460_),
+ .A2(_2770_),
+ .B1(_2432_),
+ .B2(_2772_),
+ .X(_3006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7333_ (.A1(_2382_),
+ .A2(_2759_),
+ .B1(_2493_),
+ .B2(_2761_),
+ .C1(_3006_),
+ .X(_3007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7334_ (.A1(_2467_),
+ .A2(_2766_),
+ .B1(_2442_),
+ .B2(_2768_),
+ .C1(_3007_),
+ .X(_3008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7335_ (.A1(_2469_),
+ .A2(_2721_),
+ .B1(_2480_),
+ .B2(_2740_),
+ .X(_3009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7336_ (.A1(_2419_),
+ .A2(_2728_),
+ .B1(_2509_),
+ .B2(_2755_),
+ .C1(_3009_),
+ .X(_3010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7337_ (.A1(_2517_),
+ .A2(_2781_),
+ .B1(_2448_),
+ .B2(_2783_),
+ .X(_3011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7338_ (.A1(_2466_),
+ .A2(_2779_),
+ .B1(_2375_),
+ .B2(_2752_),
+ .C1(_3011_),
+ .X(_3012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7339_ (.A1(_2394_),
+ .A2(_2710_),
+ .B1(_2371_),
+ .B2(_2735_),
+ .X(_3013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7340_ (.A1(_2444_),
+ .A2(_2738_),
+ .B1(_2456_),
+ .B2(_2750_),
+ .C1(_3013_),
+ .X(_3014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _7341_ (.A1(_2377_),
+ .A2(_2746_),
+ .B1(_2462_),
+ .B2(_2789_),
+ .X(_3015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7342_ (.A1(_2383_),
+ .A2(_2732_),
+ .B1(_2482_),
+ .B2(_2718_),
+ .C1(_3015_),
+ .X(_3016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7343_ (.A(_3010_),
+ .B(_3012_),
+ .C(_3014_),
+ .D(_3016_),
+ .X(_3017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7344_ (.A1(_2369_),
+ .A2(_2796_),
+ .B1(_2487_),
+ .B2(_2757_),
+ .X(_3018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7345_ (.A1(_2411_),
+ .A2(_2724_),
+ .B1(_2399_),
+ .B2(_2794_),
+ .C1(_3018_),
+ .X(_3019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7346_ (.A1(_2516_),
+ .A2(_2802_),
+ .B1(_2405_),
+ .B2(_2730_),
+ .X(_3020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7347_ (.A1(_2468_),
+ .A2(_2743_),
+ .B1(_2455_),
+ .B2(_2800_),
+ .C1(_3020_),
+ .X(_3021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7348_ (.A(_2400_),
+ .B(_2726_),
+ .X(_3022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7349_ (.A1(_2449_),
+ .A2(_1721_),
+ .B1(_2422_),
+ .B2(_2715_),
+ .C1(_3022_),
+ .X(_3023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7350_ (.A1(_2389_),
+ .A2(_2810_),
+ .B1(_2499_),
+ .B2(_2812_),
+ .X(_3024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7351_ (.A1(_2437_),
+ .A2(_2808_),
+ .B1(_2438_),
+ .B2(_2748_),
+ .C1(_3024_),
+ .X(_3025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7352_ (.A(_3019_),
+ .B(_3021_),
+ .C(_3023_),
+ .D(_3025_),
+ .X(_3026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7353_ (.A(_3008_),
+ .B(_3017_),
+ .C(_3026_),
+ .Y(_0121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7354_ (.A1(_2313_),
+ .A2(_2770_),
+ .B1(_2354_),
+ .B2(_2772_),
+ .X(_3027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7355_ (.A1(_2265_),
+ .A2(_2759_),
+ .B1(_2332_),
+ .B2(_2761_),
+ .C1(_3027_),
+ .X(_3028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7356_ (.A1(_2327_),
+ .A2(_2766_),
+ .B1(_2357_),
+ .B2(_2768_),
+ .C1(_3028_),
+ .X(_3029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7357_ (.A1(_2292_),
+ .A2(_2721_),
+ .B1(_2254_),
+ .B2(_2740_),
+ .X(_3030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7358_ (.A1(_2271_),
+ .A2(_2728_),
+ .B1(_2297_),
+ .B2(_2755_),
+ .C1(_3030_),
+ .X(_3031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7359_ (.A1(_2349_),
+ .A2(_2781_),
+ .B1(_2307_),
+ .B2(_2783_),
+ .X(_3032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7360_ (.A1(_2337_),
+ .A2(_2779_),
+ .B1(_2253_),
+ .B2(_2752_),
+ .C1(_3032_),
+ .X(_3033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7361_ (.A1(_2328_),
+ .A2(_2710_),
+ .B1(_2276_),
+ .B2(_2735_),
+ .X(_3034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7362_ (.A1(_2284_),
+ .A2(_2738_),
+ .B1(_2314_),
+ .B2(_2750_),
+ .C1(_3034_),
+ .X(_3035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7363_ (.A1(_2331_),
+ .A2(_2746_),
+ .B1(_2344_),
+ .B2(_2789_),
+ .X(_3036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7364_ (.A1(_2266_),
+ .A2(_2732_),
+ .B1(_2308_),
+ .B2(_2718_),
+ .C1(_3036_),
+ .X(_3037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7365_ (.A(_3031_),
+ .B(_3033_),
+ .C(_3035_),
+ .D(_3037_),
+ .X(_3038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7366_ (.A1(_2258_),
+ .A2(_2796_),
+ .B1(_2288_),
+ .B2(_2757_),
+ .X(_3039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7367_ (.A1(_2259_),
+ .A2(_2724_),
+ .B1(_2275_),
+ .B2(_2794_),
+ .C1(_3039_),
+ .X(_3040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7368_ (.A1(_2350_),
+ .A2(_2802_),
+ .B1(_2270_),
+ .B2(_2730_),
+ .X(_3041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7369_ (.A1(_2279_),
+ .A2(_2743_),
+ .B1(_2312_),
+ .B2(_2800_),
+ .C1(_3041_),
+ .X(_3042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7370_ (.A(_2264_),
+ .B(_2726_),
+ .X(_3043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7371_ (.A1(_2301_),
+ .A2(_1721_),
+ .B1(_2289_),
+ .B2(_2715_),
+ .C1(_3043_),
+ .X(_3044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7372_ (.A1(_2306_),
+ .A2(_2810_),
+ .B1(_2353_),
+ .B2(_2812_),
+ .X(_3045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7373_ (.A1(_2336_),
+ .A2(_2808_),
+ .B1(_2255_),
+ .B2(_2748_),
+ .C1(_3045_),
+ .X(_3046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7374_ (.A(_3040_),
+ .B(_3042_),
+ .C(_3044_),
+ .D(_3046_),
+ .X(_3047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7375_ (.A(_3029_),
+ .B(_3038_),
+ .C(_3047_),
+ .Y(_0123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7376_ (.A1(_2126_),
+ .A2(_2770_),
+ .B1(_2187_),
+ .B2(_2772_),
+ .X(_3048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7377_ (.A1(_2140_),
+ .A2(_2759_),
+ .B1(_2218_),
+ .B2(_2761_),
+ .C1(_3048_),
+ .X(_3049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7378_ (.A1(_2175_),
+ .A2(_2766_),
+ .B1(_2165_),
+ .B2(_2768_),
+ .C1(_3049_),
+ .X(_3050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7379_ (.A1(_2242_),
+ .A2(_2721_),
+ .B1(_2109_),
+ .B2(_2740_),
+ .X(_3051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7380_ (.A1(_2245_),
+ .A2(_2728_),
+ .B1(_2194_),
+ .B2(_2755_),
+ .C1(_3051_),
+ .X(_3052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7381_ (.A1(_2125_),
+ .A2(_2781_),
+ .B1(_2118_),
+ .B2(_2783_),
+ .X(_3053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7382_ (.A1(_2177_),
+ .A2(_2779_),
+ .B1(_2152_),
+ .B2(_2752_),
+ .C1(_3053_),
+ .X(_3054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7383_ (.A1(_2195_),
+ .A2(_2710_),
+ .B1(_2157_),
+ .B2(_2735_),
+ .X(_3055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7384_ (.A1(_2171_),
+ .A2(_2738_),
+ .B1(_2201_),
+ .B2(_2750_),
+ .C1(_3055_),
+ .X(_3056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7385_ (.A1(_2151_),
+ .A2(_2746_),
+ .B1(_2190_),
+ .B2(_2789_),
+ .X(_3057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7386_ (.A1(_2147_),
+ .A2(_2732_),
+ .B1(_2223_),
+ .B2(_2718_),
+ .C1(_3057_),
+ .X(_3058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7387_ (.A(_3052_),
+ .B(_3054_),
+ .C(_3056_),
+ .D(_3058_),
+ .X(_3059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7388_ (.A1(_2139_),
+ .A2(_2796_),
+ .B1(_2219_),
+ .B2(_2757_),
+ .X(_3060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7389_ (.A1(_2212_),
+ .A2(_2724_),
+ .B1(_2141_),
+ .B2(_2794_),
+ .C1(_3060_),
+ .X(_3061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7390_ (.A1(_2108_),
+ .A2(_2802_),
+ .B1(_2113_),
+ .B2(_2730_),
+ .X(_3062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7391_ (.A1(_2236_),
+ .A2(_2743_),
+ .B1(_2202_),
+ .B2(_2800_),
+ .C1(_3062_),
+ .X(_3063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7392_ (.A(_2156_),
+ .B(_2726_),
+ .X(_3064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7393_ (.A1(_2169_),
+ .A2(_1721_),
+ .B1(_2196_),
+ .B2(_2715_),
+ .C1(_3064_),
+ .X(_3065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7394_ (.A1(_2207_),
+ .A2(_2810_),
+ .B1(_2119_),
+ .B2(_2812_),
+ .X(_3066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7395_ (.A1(_2182_),
+ .A2(_2808_),
+ .B1(_2121_),
+ .B2(_2748_),
+ .C1(_3066_),
+ .X(_3067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7396_ (.A(_3061_),
+ .B(_3063_),
+ .C(_3065_),
+ .D(_3067_),
+ .X(_3068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3_4 _7397_ (.A(_3050_),
+ .B(_3059_),
+ .C(_3068_),
+ .Y(_0125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_4 _7398_ (.A(_1693_),
+ .B(_1692_),
+ .C(\pad_count_1[4] ),
+ .Y(_0127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7399_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_1693_),
+ .D(_1695_),
+ .X(_3069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7400_ (.A(_3069_),
+ .X(_3070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7401_ (.A(\pad_count_1[1] ),
+ .B(_1703_),
+ .X(_3071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7402_ (.A(\pad_count_1[3] ),
+ .Y(_3072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7403_ (.A(_3072_),
+ .B(_1699_),
+ .X(_3073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7404_ (.A(_3071_),
+ .B(_3073_),
+ .C(\pad_count_1[4] ),
+ .X(_3074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7405_ (.A(_3074_),
+ .X(_3075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7406_ (.A(\pad_count_1[3] ),
+ .B(_1699_),
+ .X(_3076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7407_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3076_),
+ .D(_1695_),
+ .X(_3077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7408_ (.A(_3077_),
+ .X(_3078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7409_ (.A(_1693_),
+ .B(_1704_),
+ .C(\pad_count_1[4] ),
+ .X(_3079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7410_ (.A(_3079_),
+ .X(_3080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7411_ (.A1(_1374_),
+ .A2(_3078_),
+ .B1(_1320_),
+ .B2(_3080_),
+ .X(_3081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7412_ (.A1(_1354_),
+ .A2(_3070_),
+ .B1(_1199_),
+ .B2(_3075_),
+ .C1(_3081_),
+ .X(_3082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7413_ (.A(_3072_),
+ .B(\pad_count_1[2] ),
+ .X(_3083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7414_ (.A(_3083_),
+ .B(_1704_),
+ .C(\pad_count_1[4] ),
+ .X(_3084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7415_ (.A(_3084_),
+ .X(_3085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7416_ (.A(_3071_),
+ .B(_3076_),
+ .C(\pad_count_1[4] ),
+ .X(_3086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7417_ (.A(_3086_),
+ .X(_3087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7418_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_1693_),
+ .D(\pad_count_1[4] ),
+ .X(_3088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7419_ (.A(_3088_),
+ .X(_3089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7420_ (.A(_3083_),
+ .B(_3071_),
+ .C(_1695_),
+ .X(_3090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7421_ (.A(_3090_),
+ .X(_3091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7422_ (.A1(_1252_),
+ .A2(_3089_),
+ .B1(_1335_),
+ .B2(_3091_),
+ .X(_3092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7423_ (.A1(_1187_),
+ .A2(_3085_),
+ .B1(_1180_),
+ .B2(_3087_),
+ .C1(_3092_),
+ .X(_3093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7424_ (.A(_1692_),
+ .B(_3076_),
+ .C(\pad_count_1[4] ),
+ .X(_3094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7425_ (.A(_3094_),
+ .X(_3095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7426_ (.A(_1704_),
+ .B(_3073_),
+ .C(_1695_),
+ .X(_3096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7427_ (.A(_3096_),
+ .X(_3097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7428_ (.A1(_1294_),
+ .A2(_3097_),
+ .B1(_1221_),
+ .B2(_1697_),
+ .X(_3098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7429_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3076_),
+ .D(\pad_count_1[4] ),
+ .X(_3099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7430_ (.A(_3099_),
+ .X(_3100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7431_ (.A(_3083_),
+ .B(_1704_),
+ .C(_1695_),
+ .X(_3101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7432_ (.A(_3101_),
+ .X(_3102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7433_ (.A(_1692_),
+ .B(_3083_),
+ .C(_1695_),
+ .X(_3103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7434_ (.A(_3103_),
+ .X(_3104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7435_ (.A(_1704_),
+ .B(_3076_),
+ .C(_1695_),
+ .X(_3105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7436_ (.A(_3105_),
+ .X(_3106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7437_ (.A1(_1324_),
+ .A2(_3104_),
+ .B1(_1403_),
+ .B2(_3106_),
+ .X(_3107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7438_ (.A1(_1143_),
+ .A2(_3100_),
+ .B1(_1272_),
+ .B2(_3102_),
+ .C1(_3107_),
+ .X(_3108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7439_ (.A1(_1166_),
+ .A2(_3095_),
+ .B1(_3098_),
+ .C1(_3108_),
+ .X(_3109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7440_ (.A(_1692_),
+ .B(_3073_),
+ .C(\pad_count_1[4] ),
+ .X(_3110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7441_ (.A(_3110_),
+ .X(_3111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7442_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3073_),
+ .D(_1695_),
+ .X(_3112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7443_ (.A(_3112_),
+ .X(_3113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7444_ (.A(_1692_),
+ .B(_3076_),
+ .C(_1695_),
+ .X(_3114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7445_ (.A(_3114_),
+ .X(_3115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7446_ (.A(_1693_),
+ .B(_1704_),
+ .C(_1695_),
+ .X(_3116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7447_ (.A(_3116_),
+ .X(_3117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7448_ (.A1(_1391_),
+ .A2(_3115_),
+ .B1(_1405_),
+ .B2(_3117_),
+ .X(_3118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7449_ (.A1(_1258_),
+ .A2(_3111_),
+ .B1(_1328_),
+ .B2(_3113_),
+ .C1(_3118_),
+ .X(_3119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7450_ (.A(_3083_),
+ .B(_3071_),
+ .C(\pad_count_1[4] ),
+ .X(_3120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7451_ (.A(_3120_),
+ .X(_3121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7452_ (.A(_3071_),
+ .B(_3076_),
+ .C(_1695_),
+ .X(_3122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7453_ (.A(_3122_),
+ .X(_3123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7454_ (.A(_1693_),
+ .B(_3071_),
+ .C(_1695_),
+ .X(_3124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7455_ (.A(_3124_),
+ .X(_3125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7456_ (.A(_1693_),
+ .B(_3071_),
+ .C(\pad_count_1[4] ),
+ .X(_3126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7457_ (.A(_3126_),
+ .X(_3127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7458_ (.A1(_1283_),
+ .A2(_3125_),
+ .B1(_1248_),
+ .B2(_3127_),
+ .X(_3128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7459_ (.A1(_1219_),
+ .A2(_3121_),
+ .B1(_1393_),
+ .B2(_3123_),
+ .C1(_3128_),
+ .X(_3129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7460_ (.A(_1692_),
+ .B(_3083_),
+ .C(\pad_count_1[4] ),
+ .X(_3130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7461_ (.A(_3130_),
+ .X(_3131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7462_ (.A(_1692_),
+ .B(_3073_),
+ .C(_1695_),
+ .X(_3132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7463_ (.A(_3132_),
+ .X(_3133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7464_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3083_),
+ .D(\pad_count_1[4] ),
+ .X(_3134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7465_ (.A(_3134_),
+ .X(_3135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7466_ (.A(_3071_),
+ .B(_3073_),
+ .C(_1695_),
+ .X(_3136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7467_ (.A(_3136_),
+ .X(_3137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7468_ (.A1(_1213_),
+ .A2(_3135_),
+ .B1(_1333_),
+ .B2(_3137_),
+ .X(_3138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7469_ (.A1(_1195_),
+ .A2(_3131_),
+ .B1(_1387_),
+ .B2(_3133_),
+ .C1(_3138_),
+ .X(_3139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7470_ (.A(_1704_),
+ .B(_3076_),
+ .C(\pad_count_1[4] ),
+ .X(_3140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7471_ (.A(_3140_),
+ .X(_3141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7472_ (.A(_1704_),
+ .B(_3073_),
+ .C(\pad_count_1[4] ),
+ .X(_3142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7473_ (.A(_3142_),
+ .X(_3143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7474_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3083_),
+ .D(_1695_),
+ .X(_3144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7475_ (.A(_3144_),
+ .X(_3145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7476_ (.A(_1702_),
+ .B(\pad_count_1[0] ),
+ .C(_3073_),
+ .D(\pad_count_1[4] ),
+ .X(_3146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7477_ (.A(_3146_),
+ .X(_3147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7478_ (.A1(_1292_),
+ .A2(_3145_),
+ .B1(_1205_),
+ .B2(_3147_),
+ .X(_3148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7479_ (.A1(_1147_),
+ .A2(_3141_),
+ .B1(_1238_),
+ .B2(_3143_),
+ .C1(_3148_),
+ .X(_3149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7480_ (.A(_3119_),
+ .B(_3129_),
+ .C(_3139_),
+ .D(_3149_),
+ .X(_3150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _7481_ (.A(_3082_),
+ .B(_3093_),
+ .C(_3109_),
+ .D(_3150_),
+ .X(_3151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7482_ (.A(_3151_),
+ .X(_0128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7483_ (.A1(_2600_),
+ .A2(_3078_),
+ .B1(_2648_),
+ .B2(_3080_),
+ .X(_3152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7484_ (.A1(_2594_),
+ .A2(_3070_),
+ .B1(_2626_),
+ .B2(_3075_),
+ .C1(_3152_),
+ .X(_3153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7485_ (.A1(_2645_),
+ .A2(_3089_),
+ .B1(_2579_),
+ .B2(_3091_),
+ .X(_3154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7486_ (.A1(_2625_),
+ .A2(_3085_),
+ .B1(_2656_),
+ .B2(_3087_),
+ .C1(_3154_),
+ .X(_3155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7487_ (.A1(_2553_),
+ .A2(_3097_),
+ .B1(_2630_),
+ .B2(_1697_),
+ .X(_3156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7488_ (.A1(_2523_),
+ .A2(_3104_),
+ .B1(_2589_),
+ .B2(_3106_),
+ .X(_3157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7489_ (.A1(_2534_),
+ .A2(_3100_),
+ .B1(_2595_),
+ .B2(_3102_),
+ .C1(_3157_),
+ .X(_3158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7490_ (.A1(_2654_),
+ .A2(_3095_),
+ .B1(_3156_),
+ .C1(_3158_),
+ .X(_3159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7491_ (.A1(_2590_),
+ .A2(_3115_),
+ .B1(_2606_),
+ .B2(_3117_),
+ .X(_3160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7492_ (.A1(_2674_),
+ .A2(_3111_),
+ .B1(_2522_),
+ .B2(_3113_),
+ .C1(_3160_),
+ .X(_3161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7493_ (.A1(_2528_),
+ .A2(_3125_),
+ .B1(_2643_),
+ .B2(_3127_),
+ .X(_3162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7494_ (.A1(_2668_),
+ .A2(_3121_),
+ .B1(_2588_),
+ .B2(_3123_),
+ .C1(_3162_),
+ .X(_3163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7495_ (.A1(_2614_),
+ .A2(_3135_),
+ .B1(_2560_),
+ .B2(_3137_),
+ .X(_3164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7496_ (.A1(_2655_),
+ .A2(_3131_),
+ .B1(_2567_),
+ .B2(_3133_),
+ .C1(_3164_),
+ .X(_3165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7497_ (.A1(_2558_),
+ .A2(_3145_),
+ .B1(_2661_),
+ .B2(_3147_),
+ .X(_3166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7498_ (.A1(_2624_),
+ .A2(_3141_),
+ .B1(_2615_),
+ .B2(_3143_),
+ .C1(_3166_),
+ .X(_3167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7499_ (.A(_3161_),
+ .B(_3163_),
+ .C(_3165_),
+ .D(_3167_),
+ .X(_3168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7500_ (.A(_3153_),
+ .B(_3155_),
+ .C(_3159_),
+ .D(_3168_),
+ .Y(_0130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7501_ (.A1(_2473_),
+ .A2(_3078_),
+ .B1(_2410_),
+ .B2(_3080_),
+ .X(_3169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7502_ (.A1(_2461_),
+ .A2(_3070_),
+ .B1(_2401_),
+ .B2(_3075_),
+ .C1(_3169_),
+ .X(_3170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7503_ (.A1(_2404_),
+ .A2(_3089_),
+ .B1(_2429_),
+ .B2(_3091_),
+ .X(_3171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7504_ (.A1(_2376_),
+ .A2(_3085_),
+ .B1(_2418_),
+ .B2(_3087_),
+ .C1(_3171_),
+ .X(_3172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7505_ (.A1(_2500_),
+ .A2(_3097_),
+ .B1(_2398_),
+ .B2(_1697_),
+ .X(_3173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7506_ (.A1(_2431_),
+ .A2(_3104_),
+ .B1(_2497_),
+ .B2(_3106_),
+ .X(_3174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7507_ (.A1(_2491_),
+ .A2(_3100_),
+ .B1(_2498_),
+ .B2(_3102_),
+ .C1(_3174_),
+ .X(_3175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7508_ (.A1(_2512_),
+ .A2(_3095_),
+ .B1(_3173_),
+ .C1(_3175_),
+ .X(_3176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7509_ (.A1(_2447_),
+ .A2(_3115_),
+ .B1(_2504_),
+ .B2(_3117_),
+ .X(_3177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7510_ (.A1(_2380_),
+ .A2(_3111_),
+ .B1(_2441_),
+ .B2(_3113_),
+ .C1(_3177_),
+ .X(_3178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7511_ (.A1(_2474_),
+ .A2(_3125_),
+ .B1(_2510_),
+ .B2(_3127_),
+ .X(_3179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7512_ (.A1(_2381_),
+ .A2(_3121_),
+ .B1(_2450_),
+ .B2(_3123_),
+ .C1(_3179_),
+ .X(_3180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7513_ (.A1(_2374_),
+ .A2(_3135_),
+ .B1(_2454_),
+ .B2(_3137_),
+ .X(_3181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7514_ (.A1(_2424_),
+ .A2(_3131_),
+ .B1(_2472_),
+ .B2(_3133_),
+ .C1(_3181_),
+ .X(_3182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7515_ (.A1(_2387_),
+ .A2(_3145_),
+ .B1(_2370_),
+ .B2(_3147_),
+ .X(_3183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7516_ (.A1(_2492_),
+ .A2(_3141_),
+ .B1(_2368_),
+ .B2(_3143_),
+ .C1(_3183_),
+ .X(_3184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _7517_ (.A(_3178_),
+ .B(_3180_),
+ .C(_3182_),
+ .D(_3184_),
+ .X(_3185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7518_ (.A(_3170_),
+ .B(_3172_),
+ .C(_3176_),
+ .D(_3185_),
+ .Y(_0132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7519_ (.A1(_4424_),
+ .A2(_3070_),
+ .B1(_4419_),
+ .B2(_3075_),
+ .X(_3186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7520_ (.A1(_4428_),
+ .A2(_3078_),
+ .B1(_4409_),
+ .B2(_3080_),
+ .C1(_3186_),
+ .X(_3187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7521_ (.A1(_4408_),
+ .A2(_3089_),
+ .B1(_4431_),
+ .B2(_3091_),
+ .X(_3188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7522_ (.A1(_4417_),
+ .A2(_3085_),
+ .B1(_4411_),
+ .B2(_3087_),
+ .C1(_3188_),
+ .X(_3189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7523_ (.A1(_4437_),
+ .A2(_3097_),
+ .B1(_4422_),
+ .B2(_1697_),
+ .X(_3190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7524_ (.A1(_4430_),
+ .A2(_3104_),
+ .B1(_4429_),
+ .B2(_3106_),
+ .X(_3191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7525_ (.A1(_4412_),
+ .A2(_3100_),
+ .B1(_4433_),
+ .B2(_3102_),
+ .C1(_3191_),
+ .X(_3192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7526_ (.A1(_4410_),
+ .A2(_3095_),
+ .B1(_3190_),
+ .C1(_3192_),
+ .X(_3193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7527_ (.A1(_4426_),
+ .A2(_3115_),
+ .B1(_4425_),
+ .B2(_3117_),
+ .X(_3194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7528_ (.A1(_4418_),
+ .A2(_3111_),
+ .B1(_4436_),
+ .B2(_3113_),
+ .C1(_3194_),
+ .X(_3195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7529_ (.A1(_4423_),
+ .A2(_3125_),
+ .B1(_2280_),
+ .B2(_3127_),
+ .X(_3196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7530_ (.A1(_4415_),
+ .A2(_3121_),
+ .B1(_4427_),
+ .B2(_3123_),
+ .C1(_3196_),
+ .X(_3197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7531_ (.A1(_4416_),
+ .A2(_3135_),
+ .B1(_4435_),
+ .B2(_3137_),
+ .X(_3198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7532_ (.A1(_4414_),
+ .A2(_3131_),
+ .B1(_4434_),
+ .B2(_3133_),
+ .C1(_3198_),
+ .X(_3199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7533_ (.A1(_4432_),
+ .A2(_3145_),
+ .B1(_4420_),
+ .B2(_3147_),
+ .X(_3200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7534_ (.A1(_4413_),
+ .A2(_3141_),
+ .B1(_4421_),
+ .B2(_3143_),
+ .C1(_3200_),
+ .X(_3201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7535_ (.A(_3195_),
+ .B(_3197_),
+ .C(_3199_),
+ .D(_3201_),
+ .X(_3202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7536_ (.A(_3187_),
+ .B(_3189_),
+ .C(_3193_),
+ .D(_3202_),
+ .Y(_0134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7537_ (.A1(_2174_),
+ .A2(_3078_),
+ .B1(_2112_),
+ .B2(_3080_),
+ .X(_3203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7538_ (.A1(_2199_),
+ .A2(_3070_),
+ .B1(_2149_),
+ .B2(_3075_),
+ .C1(_3203_),
+ .X(_3204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7539_ (.A1(_2241_),
+ .A2(_3089_),
+ .B1(_2181_),
+ .B2(_3091_),
+ .X(_3205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7540_ (.A1(_2150_),
+ .A2(_3085_),
+ .B1(_2240_),
+ .B2(_3087_),
+ .C1(_3205_),
+ .X(_3206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7541_ (.A1(_2200_),
+ .A2(_3097_),
+ .B1(_2138_),
+ .B2(_1697_),
+ .X(_3207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7542_ (.A1(_2124_),
+ .A2(_3104_),
+ .B1(_2107_),
+ .B2(_3106_),
+ .X(_3208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7543_ (.A1(_2115_),
+ .A2(_3100_),
+ .B1(_2180_),
+ .B2(_3102_),
+ .C1(_3208_),
+ .X(_3209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7544_ (.A1(_2234_),
+ .A2(_3095_),
+ .B1(_3207_),
+ .C1(_3209_),
+ .X(_3210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7545_ (.A1(_2135_),
+ .A2(_3115_),
+ .B1(_2106_),
+ .B2(_3117_),
+ .X(_3211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7546_ (.A1(_2146_),
+ .A2(_3111_),
+ .B1(_2168_),
+ .B2(_3113_),
+ .C1(_3211_),
+ .X(_3212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7547_ (.A1(_2176_),
+ .A2(_3125_),
+ .B1(_2217_),
+ .B2(_3127_),
+ .X(_3213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7548_ (.A1(_2131_),
+ .A2(_3121_),
+ .B1(_2193_),
+ .B2(_3123_),
+ .C1(_3213_),
+ .X(_3214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7549_ (.A1(_2145_),
+ .A2(_3135_),
+ .B1(_2205_),
+ .B2(_3137_),
+ .X(_3215_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7550_ (.A1(_2235_),
+ .A2(_3131_),
+ .B1(_2127_),
+ .B2(_3133_),
+ .C1(_3215_),
+ .X(_3216_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7551_ (.A1(_2208_),
+ .A2(_3145_),
+ .B1(_2155_),
+ .B2(_3147_),
+ .X(_3217_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7552_ (.A1(_2246_),
+ .A2(_3141_),
+ .B1(_2158_),
+ .B2(_3143_),
+ .C1(_3217_),
+ .X(_3218_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7553_ (.A(_3212_),
+ .B(_3214_),
+ .C(_3216_),
+ .D(_3218_),
+ .X(_3219_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7554_ (.A(_3204_),
+ .B(_3206_),
+ .C(_3210_),
+ .D(_3219_),
+ .Y(_0136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7555_ (.A1(_2071_),
+ .A2(_3078_),
+ .B1(_2084_),
+ .B2(_3080_),
+ .X(_3220_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7556_ (.A1(_2057_),
+ .A2(_3070_),
+ .B1(_2090_),
+ .B2(_3075_),
+ .C1(_3220_),
+ .X(_3221_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7557_ (.A1(_2063_),
+ .A2(_3089_),
+ .B1(_2022_),
+ .B2(_3091_),
+ .X(_3222_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7558_ (.A1(_2082_),
+ .A2(_3085_),
+ .B1(_2078_),
+ .B2(_3087_),
+ .C1(_3222_),
+ .X(_3223_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7559_ (.A1(_2027_),
+ .A2(_3097_),
+ .B1(_2101_),
+ .B2(_1697_),
+ .X(_3224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7560_ (.A1(_2056_),
+ .A2(_3104_),
+ .B1(_2021_),
+ .B2(_3106_),
+ .X(_3225_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7561_ (.A1(_2085_),
+ .A2(_3100_),
+ .B1(_2044_),
+ .B2(_3102_),
+ .C1(_3225_),
+ .X(_3226_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7562_ (.A1(_2096_),
+ .A2(_3095_),
+ .B1(_3224_),
+ .C1(_3226_),
+ .X(_3227_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7563_ (.A1(_2020_),
+ .A2(_3115_),
+ .B1(_2050_),
+ .B2(_3117_),
+ .X(_3228_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7564_ (.A1(_2089_),
+ .A2(_3111_),
+ .B1(_2037_),
+ .B2(_3113_),
+ .C1(_3228_),
+ .X(_3229_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7565_ (.A1(_2058_),
+ .A2(_3125_),
+ .B1(_2095_),
+ .B2(_3127_),
+ .X(_3230_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7566_ (.A1(_2079_),
+ .A2(_3121_),
+ .B1(_2055_),
+ .B2(_3123_),
+ .C1(_3230_),
+ .X(_3231_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7567_ (.A1(_2069_),
+ .A2(_3135_),
+ .B1(_2025_),
+ .B2(_3137_),
+ .X(_3232_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7568_ (.A1(_2065_),
+ .A2(_3131_),
+ .B1(_2052_),
+ .B2(_3133_),
+ .C1(_3232_),
+ .X(_3233_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7569_ (.A1(_2072_),
+ .A2(_3145_),
+ .B1(_2097_),
+ .B2(_3147_),
+ .X(_3234_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7570_ (.A1(_2083_),
+ .A2(_3141_),
+ .B1(_2064_),
+ .B2(_3143_),
+ .C1(_3234_),
+ .X(_3235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _7571_ (.A(_3229_),
+ .B(_3231_),
+ .C(_3233_),
+ .D(_3235_),
+ .X(_3236_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7572_ (.A(_3221_),
+ .B(_3223_),
+ .C(_3227_),
+ .D(_3236_),
+ .Y(_0138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7573_ (.A1(_1979_),
+ .A2(_3078_),
+ .B1(_2013_),
+ .B2(_3080_),
+ .X(_3237_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7574_ (.A1(_1936_),
+ .A2(_3070_),
+ .B1(_1961_),
+ .B2(_3075_),
+ .C1(_3237_),
+ .X(_3238_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7575_ (.A1(_2015_),
+ .A2(_3089_),
+ .B1(_1972_),
+ .B2(_3091_),
+ .X(_3239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7576_ (.A1(_1965_),
+ .A2(_3085_),
+ .B1(_1998_),
+ .B2(_3087_),
+ .C1(_3239_),
+ .X(_3240_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7577_ (.A1(_1983_),
+ .A2(_3097_),
+ .B1(_1959_),
+ .B2(_1697_),
+ .X(_3241_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7578_ (.A1(_1954_),
+ .A2(_3104_),
+ .B1(_1952_),
+ .B2(_3106_),
+ .X(_3242_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7579_ (.A1(_2007_),
+ .A2(_3100_),
+ .B1(_1982_),
+ .B2(_3102_),
+ .C1(_3242_),
+ .X(_3243_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7580_ (.A1(_2001_),
+ .A2(_3095_),
+ .B1(_3241_),
+ .C1(_3243_),
+ .X(_3244_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7581_ (.A1(_2008_),
+ .A2(_3115_),
+ .B1(_1948_),
+ .B2(_3117_),
+ .X(_3245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7582_ (.A1(_1966_),
+ .A2(_3111_),
+ .B1(_1978_),
+ .B2(_3113_),
+ .C1(_3245_),
+ .X(_3246_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7583_ (.A1(_1938_),
+ .A2(_3125_),
+ .B1(_1941_),
+ .B2(_3127_),
+ .X(_3247_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7584_ (.A1(_1958_),
+ .A2(_3121_),
+ .B1(_1943_),
+ .B2(_3123_),
+ .C1(_3247_),
+ .X(_3248_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7585_ (.A1(_1967_),
+ .A2(_3135_),
+ .B1(_1944_),
+ .B2(_3137_),
+ .X(_3249_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7586_ (.A1(_1977_),
+ .A2(_3131_),
+ .B1(_1951_),
+ .B2(_3133_),
+ .C1(_3249_),
+ .X(_3250_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7587_ (.A1(_1971_),
+ .A2(_3145_),
+ .B1(_1962_),
+ .B2(_3147_),
+ .X(_3251_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7588_ (.A1(_1995_),
+ .A2(_3141_),
+ .B1(_1964_),
+ .B2(_3143_),
+ .C1(_3251_),
+ .X(_3252_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7589_ (.A(_3246_),
+ .B(_3248_),
+ .C(_3250_),
+ .D(_3252_),
+ .X(_3253_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7590_ (.A(_3238_),
+ .B(_3240_),
+ .C(_3244_),
+ .D(_3253_),
+ .Y(_0140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7591_ (.A1(_1866_),
+ .A2(_3078_),
+ .B1(_1847_),
+ .B2(_3080_),
+ .X(_3254_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7592_ (.A1(_1879_),
+ .A2(_3070_),
+ .B1(_1925_),
+ .B2(_3075_),
+ .C1(_3254_),
+ .X(_3255_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7593_ (.A1(_1917_),
+ .A2(_3089_),
+ .B1(_1904_),
+ .B2(_3091_),
+ .X(_3256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7594_ (.A1(_1914_),
+ .A2(_3085_),
+ .B1(_1908_),
+ .B2(_3087_),
+ .C1(_3256_),
+ .X(_3257_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7595_ (.A1(_1860_),
+ .A2(_3097_),
+ .B1(_1927_),
+ .B2(_1697_),
+ .X(_3258_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7596_ (.A1(_1897_),
+ .A2(_3104_),
+ .B1(_1898_),
+ .B2(_3106_),
+ .X(_3259_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7597_ (.A1(_1911_),
+ .A2(_3100_),
+ .B1(_1871_),
+ .B2(_3102_),
+ .C1(_3259_),
+ .X(_3260_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7598_ (.A1(_1915_),
+ .A2(_3095_),
+ .B1(_3258_),
+ .C1(_3260_),
+ .X(_3261_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7599_ (.A1(_1862_),
+ .A2(_3115_),
+ .B1(_1878_),
+ .B2(_3117_),
+ .X(_3262_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7600_ (.A1(_1910_),
+ .A2(_3111_),
+ .B1(_1902_),
+ .B2(_3113_),
+ .C1(_3262_),
+ .X(_3263_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7601_ (.A1(_1886_),
+ .A2(_3125_),
+ .B1(_1850_),
+ .B2(_3127_),
+ .X(_3264_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7602_ (.A1(_1926_),
+ .A2(_3121_),
+ .B1(_1901_),
+ .B2(_3123_),
+ .C1(_3264_),
+ .X(_3265_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7603_ (.A1(_1909_),
+ .A2(_3135_),
+ .B1(_1861_),
+ .B2(_3137_),
+ .X(_3266_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7604_ (.A1(_1853_),
+ .A2(_3131_),
+ .B1(_1867_),
+ .B2(_3133_),
+ .C1(_3266_),
+ .X(_3267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7605_ (.A1(_1892_),
+ .A2(_3145_),
+ .B1(_1854_),
+ .B2(_3147_),
+ .X(_3268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7606_ (.A1(_1916_),
+ .A2(_3141_),
+ .B1(_1924_),
+ .B2(_3143_),
+ .C1(_3268_),
+ .X(_3269_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7607_ (.A(_3263_),
+ .B(_3265_),
+ .C(_3267_),
+ .D(_3269_),
+ .X(_3270_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7608_ (.A(_3255_),
+ .B(_3257_),
+ .C(_3261_),
+ .D(_3270_),
+ .Y(_0142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7609_ (.A1(_1401_),
+ .A2(_3078_),
+ .B1(_1169_),
+ .B2(_3080_),
+ .X(_3271_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7610_ (.A1(_1397_),
+ .A2(_3070_),
+ .B1(_1207_),
+ .B2(_3075_),
+ .C1(_3271_),
+ .X(_3272_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7611_ (.A1(_1156_),
+ .A2(_3089_),
+ .B1(_1287_),
+ .B2(_3091_),
+ .X(_3273_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7612_ (.A1(_1191_),
+ .A2(_3085_),
+ .B1(_1263_),
+ .B2(_3087_),
+ .C1(_3273_),
+ .X(_3274_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _7613_ (.A1(_1336_),
+ .A2(_3097_),
+ .B1(_1197_),
+ .B2(_1697_),
+ .X(_3275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7614_ (.A1(_1279_),
+ .A2(_3104_),
+ .B1(_1407_),
+ .B2(_3106_),
+ .X(_3276_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7615_ (.A1(_1254_),
+ .A2(_3100_),
+ .B1(_1314_),
+ .B2(_3102_),
+ .C1(_3276_),
+ .X(_3277_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7616_ (.A1(_1244_),
+ .A2(_3095_),
+ .B1(_3275_),
+ .C1(_3277_),
+ .X(_3278_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7617_ (.A1(_1326_),
+ .A2(_3115_),
+ .B1(_1395_),
+ .B2(_3117_),
+ .X(_3279_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7618_ (.A1(_1201_),
+ .A2(_3111_),
+ .B1(_1343_),
+ .B2(_3113_),
+ .C1(_3279_),
+ .X(_3280_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7619_ (.A1(_1139_),
+ .A2(_3125_),
+ .B1(_1301_),
+ .B2(_3127_),
+ .X(_3281_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7620_ (.A1(_1240_),
+ .A2(_3121_),
+ .B1(_1376_),
+ .B2(_3123_),
+ .C1(_3281_),
+ .X(_3282_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7621_ (.A1(_1164_),
+ .A2(_3135_),
+ .B1(_1365_),
+ .B2(_3137_),
+ .X(_3283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7622_ (.A1(_1173_),
+ .A2(_3131_),
+ .B1(_1360_),
+ .B2(_3133_),
+ .C1(_3283_),
+ .X(_3284_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7623_ (.A1(_1359_),
+ .A2(_3145_),
+ .B1(_1185_),
+ .B2(_3147_),
+ .X(_3285_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7624_ (.A1(_1178_),
+ .A2(_3141_),
+ .B1(_1189_),
+ .B2(_3143_),
+ .C1(_3285_),
+ .X(_3286_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7625_ (.A(_3280_),
+ .B(_3282_),
+ .C(_3284_),
+ .D(_3286_),
+ .X(_3287_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7626_ (.A(_3272_),
+ .B(_3274_),
+ .C(_3278_),
+ .D(_3287_),
+ .Y(_0144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7627_ (.A1(_2601_),
+ .A2(_3078_),
+ .B1(_2637_),
+ .B2(_3080_),
+ .X(_3288_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7628_ (.A1(_2536_),
+ .A2(_3070_),
+ .B1(_2662_),
+ .B2(_3075_),
+ .C1(_3288_),
+ .X(_3289_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7629_ (.A1(_2675_),
+ .A2(_3089_),
+ .B1(_2603_),
+ .B2(_3091_),
+ .X(_3290_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7630_ (.A1(_2667_),
+ .A2(_3085_),
+ .B1(_2535_),
+ .B2(_3087_),
+ .C1(_3290_),
+ .X(_3291_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7631_ (.A1(_2591_),
+ .A2(_3097_),
+ .B1(_2673_),
+ .B2(_1697_),
+ .X(_3292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7632_ (.A1(_2609_),
+ .A2(_3104_),
+ .B1(_2578_),
+ .B2(_3106_),
+ .X(_3293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7633_ (.A1(_2657_),
+ .A2(_3100_),
+ .B1(_2540_),
+ .B2(_3102_),
+ .C1(_3293_),
+ .X(_3294_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7634_ (.A1(_2664_),
+ .A2(_3095_),
+ .B1(_3292_),
+ .C1(_3294_),
+ .X(_3295_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7635_ (.A1(_2602_),
+ .A2(_3115_),
+ .B1(_2607_),
+ .B2(_3117_),
+ .X(_3296_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7636_ (.A1(_2670_),
+ .A2(_3111_),
+ .B1(_2559_),
+ .B2(_3113_),
+ .C1(_3296_),
+ .X(_3297_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7637_ (.A1(_2633_),
+ .A2(_3125_),
+ .B1(_2568_),
+ .B2(_3127_),
+ .X(_3298_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7638_ (.A1(_2618_),
+ .A2(_3121_),
+ .B1(_2608_),
+ .B2(_3123_),
+ .C1(_3298_),
+ .X(_3299_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7639_ (.A1(_2632_),
+ .A2(_3135_),
+ .B1(_2583_),
+ .B2(_3137_),
+ .X(_3300_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7640_ (.A1(_2644_),
+ .A2(_3131_),
+ .B1(_2580_),
+ .B2(_3133_),
+ .C1(_3300_),
+ .X(_3301_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7641_ (.A1(_2547_),
+ .A2(_3145_),
+ .B1(_2663_),
+ .B2(_3147_),
+ .X(_3302_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7642_ (.A1(_2631_),
+ .A2(_3141_),
+ .B1(_2669_),
+ .B2(_3143_),
+ .C1(_3302_),
+ .X(_3303_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7643_ (.A(_3297_),
+ .B(_3299_),
+ .C(_3301_),
+ .D(_3303_),
+ .X(_3304_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7644_ (.A(_3289_),
+ .B(_3291_),
+ .C(_3295_),
+ .D(_3304_),
+ .Y(_0146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7645_ (.A1(_2466_),
+ .A2(_3078_),
+ .B1(_2422_),
+ .B2(_3080_),
+ .X(_3305_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7646_ (.A1(_2455_),
+ .A2(_3070_),
+ .B1(_2382_),
+ .B2(_3075_),
+ .C1(_3305_),
+ .X(_3306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7647_ (.A1(_2469_),
+ .A2(_3089_),
+ .B1(_2499_),
+ .B2(_3091_),
+ .X(_3307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7648_ (.A1(_2377_),
+ .A2(_3085_),
+ .B1(_2509_),
+ .B2(_3087_),
+ .C1(_3307_),
+ .X(_3308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_2 _7649_ (.A1(_2449_),
+ .A2(_3097_),
+ .B1(_2369_),
+ .B2(_1697_),
+ .X(_3309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7650_ (.A1(_2516_),
+ .A2(_3104_),
+ .B1(_2517_),
+ .B2(_3106_),
+ .X(_3310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7651_ (.A1(_2480_),
+ .A2(_3100_),
+ .B1(_2462_),
+ .B2(_3102_),
+ .C1(_3310_),
+ .X(_3311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7652_ (.A1(_2468_),
+ .A2(_3095_),
+ .B1(_3309_),
+ .C1(_3311_),
+ .X(_3312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7653_ (.A1(_2432_),
+ .A2(_3115_),
+ .B1(_2437_),
+ .B2(_3117_),
+ .X(_3313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7654_ (.A1(_2375_),
+ .A2(_3111_),
+ .B1(_2442_),
+ .B2(_3113_),
+ .C1(_3313_),
+ .X(_3314_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7655_ (.A1(_2399_),
+ .A2(_3125_),
+ .B1(_2482_),
+ .B2(_3127_),
+ .X(_3315_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7656_ (.A1(_2419_),
+ .A2(_3121_),
+ .B1(_2460_),
+ .B2(_3123_),
+ .C1(_3315_),
+ .X(_3316_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7657_ (.A1(_2383_),
+ .A2(_3135_),
+ .B1(_2467_),
+ .B2(_3137_),
+ .X(_3317_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7658_ (.A1(_2411_),
+ .A2(_3131_),
+ .B1(_2448_),
+ .B2(_3133_),
+ .C1(_3317_),
+ .X(_3318_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7659_ (.A1(_2389_),
+ .A2(_3145_),
+ .B1(_2371_),
+ .B2(_3147_),
+ .X(_3319_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7660_ (.A1(_2487_),
+ .A2(_3141_),
+ .B1(_2400_),
+ .B2(_3143_),
+ .C1(_3319_),
+ .X(_3320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _7661_ (.A(_3314_),
+ .B(_3316_),
+ .C(_3318_),
+ .D(_3320_),
+ .X(_3321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7662_ (.A(_3306_),
+ .B(_3308_),
+ .C(_3312_),
+ .D(_3321_),
+ .Y(_0148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7663_ (.A1(_2337_),
+ .A2(_3078_),
+ .B1(_2289_),
+ .B2(_3080_),
+ .X(_3322_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _7664_ (.A1(_2312_),
+ .A2(_3070_),
+ .B1(_2265_),
+ .B2(_3075_),
+ .C1(_3322_),
+ .X(_3323_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7665_ (.A1(_2292_),
+ .A2(_3089_),
+ .B1(_2353_),
+ .B2(_3091_),
+ .X(_3324_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7666_ (.A1(_2331_),
+ .A2(_3085_),
+ .B1(_2297_),
+ .B2(_3087_),
+ .C1(_3324_),
+ .X(_3325_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7667_ (.A1(_2301_),
+ .A2(_3097_),
+ .B1(_2258_),
+ .B2(_1697_),
+ .X(_3326_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7668_ (.A1(_2350_),
+ .A2(_3104_),
+ .B1(_2349_),
+ .B2(_3106_),
+ .X(_3327_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7669_ (.A1(_2254_),
+ .A2(_3100_),
+ .B1(_2344_),
+ .B2(_3102_),
+ .C1(_3327_),
+ .X(_3328_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7670_ (.A1(_2279_),
+ .A2(_3095_),
+ .B1(_3326_),
+ .C1(_3328_),
+ .X(_3329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7671_ (.A1(_2354_),
+ .A2(_3115_),
+ .B1(_2336_),
+ .B2(_3117_),
+ .X(_3330_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7672_ (.A1(_2253_),
+ .A2(_3111_),
+ .B1(_2357_),
+ .B2(_3113_),
+ .C1(_3330_),
+ .X(_3331_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7673_ (.A1(_2275_),
+ .A2(_3125_),
+ .B1(_2308_),
+ .B2(_3127_),
+ .X(_3332_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7674_ (.A1(_2271_),
+ .A2(_3121_),
+ .B1(_2313_),
+ .B2(_3123_),
+ .C1(_3332_),
+ .X(_3333_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7675_ (.A1(_2266_),
+ .A2(_3135_),
+ .B1(_2327_),
+ .B2(_3137_),
+ .X(_3334_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7676_ (.A1(_2259_),
+ .A2(_3131_),
+ .B1(_2307_),
+ .B2(_3133_),
+ .C1(_3334_),
+ .X(_3335_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7677_ (.A1(_2306_),
+ .A2(_3145_),
+ .B1(_2276_),
+ .B2(_3147_),
+ .X(_3336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7678_ (.A1(_2288_),
+ .A2(_3141_),
+ .B1(_2264_),
+ .B2(_3143_),
+ .C1(_3336_),
+ .X(_3337_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_2 _7679_ (.A(_3331_),
+ .B(_3333_),
+ .C(_3335_),
+ .D(_3337_),
+ .X(_3338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7680_ (.A(_3323_),
+ .B(_3325_),
+ .C(_3329_),
+ .D(_3338_),
+ .Y(_0150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7681_ (.A1(_2177_),
+ .A2(_3078_),
+ .B1(_2196_),
+ .B2(_3080_),
+ .X(_3339_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7682_ (.A1(_2202_),
+ .A2(_3070_),
+ .B1(_2140_),
+ .B2(_3075_),
+ .C1(_3339_),
+ .X(_3340_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7683_ (.A1(_2242_),
+ .A2(_3089_),
+ .B1(_2119_),
+ .B2(_3091_),
+ .X(_3341_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7684_ (.A1(_2151_),
+ .A2(_3085_),
+ .B1(_2194_),
+ .B2(_3087_),
+ .C1(_3341_),
+ .X(_3342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7685_ (.A1(_2169_),
+ .A2(_3097_),
+ .B1(_2139_),
+ .B2(_1697_),
+ .X(_3343_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7686_ (.A1(_2108_),
+ .A2(_3104_),
+ .B1(_2125_),
+ .B2(_3106_),
+ .X(_3344_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7687_ (.A1(_2109_),
+ .A2(_3100_),
+ .B1(_2190_),
+ .B2(_3102_),
+ .C1(_3344_),
+ .X(_3345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7688_ (.A1(_2236_),
+ .A2(_3095_),
+ .B1(_3343_),
+ .C1(_3345_),
+ .X(_3346_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7689_ (.A1(_2187_),
+ .A2(_3115_),
+ .B1(_2182_),
+ .B2(_3117_),
+ .X(_3347_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7690_ (.A1(_2152_),
+ .A2(_3111_),
+ .B1(_2165_),
+ .B2(_3113_),
+ .C1(_3347_),
+ .X(_3348_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7691_ (.A1(_2141_),
+ .A2(_3125_),
+ .B1(_2223_),
+ .B2(_3127_),
+ .X(_3349_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7692_ (.A1(_2245_),
+ .A2(_3121_),
+ .B1(_2126_),
+ .B2(_3123_),
+ .C1(_3349_),
+ .X(_3350_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7693_ (.A1(_2147_),
+ .A2(_3135_),
+ .B1(_2175_),
+ .B2(_3137_),
+ .X(_3351_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7694_ (.A1(_2212_),
+ .A2(_3131_),
+ .B1(_2118_),
+ .B2(_3133_),
+ .C1(_3351_),
+ .X(_3352_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7695_ (.A1(_2207_),
+ .A2(_3145_),
+ .B1(_2157_),
+ .B2(_3147_),
+ .X(_3353_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _7696_ (.A1(_2219_),
+ .A2(_3141_),
+ .B1(_2156_),
+ .B2(_3143_),
+ .C1(_3353_),
+ .X(_3354_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4_1 _7697_ (.A(_3348_),
+ .B(_3350_),
+ .C(_3352_),
+ .D(_3354_),
+ .X(_3355_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_4 _7698_ (.A(_3340_),
+ .B(_3342_),
+ .C(_3346_),
+ .D(_3355_),
+ .Y(_0152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7699_ (.A(_4413_),
+ .X(_3356_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7700_ (.A(_3356_),
+ .X(net242),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7701_ (.A(_4412_),
+ .X(_3357_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7702_ (.A(_3357_),
+ .X(net241),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7703_ (.A(_4410_),
+ .X(_3358_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7704_ (.A(_3358_),
+ .X(net239),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7705_ (.A(_4409_),
+ .X(_3359_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7706_ (.A(_3359_),
+ .X(net238),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7707_ (.A(\hkspi.state[1] ),
+ .B(\hkspi.state[4] ),
+ .Y(_0155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _7708_ (.A(\hkspi.addr[0] ),
+ .Y(_0156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7709_ (.A(\hkspi.addr[1] ),
+ .B(\hkspi.addr[0] ),
+ .Y(_3360_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _7710_ (.A1(\hkspi.addr[1] ),
+ .A2(\hkspi.addr[0] ),
+ .B1(_3360_),
+ .X(_0157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7711_ (.A(_3360_),
+ .Y(_3361_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _7712_ (.A1_N(\hkspi.addr[2] ),
+ .A2_N(_3361_),
+ .B1(\hkspi.addr[2] ),
+ .B2(_3361_),
+ .X(_0158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _7713_ (.A(\hkspi.addr[2] ),
+ .B(_3361_),
+ .C(\hkspi.addr[3] ),
+ .X(_3362_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _7714_ (.A1(\hkspi.addr[2] ),
+ .A2(_3361_),
+ .B1(\hkspi.addr[3] ),
+ .Y(_3363_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7715_ (.A(_3362_),
+ .B(_3363_),
+ .Y(_0159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7716_ (.A(\hkspi.addr[4] ),
+ .B(_3362_),
+ .Y(_3364_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _7717_ (.A1(\hkspi.addr[4] ),
+ .A2(_3362_),
+ .B1(_3364_),
+ .X(_0160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7718_ (.A(_3364_),
+ .Y(_3365_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7719_ (.A(\hkspi.addr[5] ),
+ .B(_3365_),
+ .Y(_3366_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _7720_ (.A1(\hkspi.addr[5] ),
+ .A2(_3365_),
+ .B1(_3366_),
+ .X(_0161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7721_ (.A(_3366_),
+ .Y(_3367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7722_ (.A(\hkspi.addr[6] ),
+ .B(_3367_),
+ .Y(_3368_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _7723_ (.A1(\hkspi.addr[6] ),
+ .A2(_3367_),
+ .B1(_3368_),
+ .X(_0162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7724_ (.A(\hkspi.addr[7] ),
+ .Y(_3369_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _7725_ (.A1(\hkspi.addr[6] ),
+ .A2(_3367_),
+ .A3(_3369_),
+ .B1(\hkspi.addr[7] ),
+ .B2(_3368_),
+ .X(_0163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _7726_ (.A(\hkspi.fixed[0] ),
+ .Y(_0164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7727_ (.A(\hkspi.fixed[1] ),
+ .Y(_3370_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _7728_ (.A1(_3370_),
+ .A2(_0164_),
+ .B1(\hkspi.fixed[1] ),
+ .B2(\hkspi.fixed[0] ),
+ .X(_0165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _7729_ (.A1(_3370_),
+ .A2(_0164_),
+ .B1(\hkspi.fixed[2] ),
+ .Y(_3371_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31oi_1 _7730_ (.A1(_3370_),
+ .A2(_0164_),
+ .A3(\hkspi.fixed[2] ),
+ .B1(_3371_),
+ .Y(_0166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7731_ (.A(_1080_),
+ .B(_0169_),
+ .X(_3372_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7732_ (.A(_3372_),
+ .X(_0167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _7733_ (.A(net199),
+ .B(net202),
+ .C(\wbbd_state[7] ),
+ .X(_3373_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _7734_ (.A(net202),
+ .B(net200),
+ .C(\wbbd_state[9] ),
+ .X(_3374_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _7735_ (.A1(\wbbd_state[8] ),
+ .A2(_1472_),
+ .B1(_3373_),
+ .C1(_3374_),
+ .X(_0168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7736_ (.A(\wbbd_state[7] ),
+ .B(net171),
+ .X(_3375_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7737_ (.A1(\wbbd_state[9] ),
+ .A2(net180),
+ .B1(\wbbd_state[8] ),
+ .B2(net194),
+ .C1(_3375_),
+ .X(_0170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7738_ (.A(\wbbd_state[7] ),
+ .B(net172),
+ .X(_3376_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7739_ (.A1(\wbbd_state[9] ),
+ .A2(net181),
+ .B1(\wbbd_state[8] ),
+ .B2(net195),
+ .C1(_3376_),
+ .X(_0171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7740_ (.A(\wbbd_state[7] ),
+ .B(net173),
+ .X(_3377_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7741_ (.A1(\wbbd_state[9] ),
+ .A2(net182),
+ .B1(\wbbd_state[8] ),
+ .B2(net165),
+ .C1(_3377_),
+ .X(_0172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7742_ (.A(\wbbd_state[7] ),
+ .B(net174),
+ .X(_3378_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7743_ (.A1(\wbbd_state[9] ),
+ .A2(net183),
+ .B1(\wbbd_state[8] ),
+ .B2(net166),
+ .C1(_3378_),
+ .X(_0173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7744_ (.A(\wbbd_state[7] ),
+ .B(net176),
+ .X(_3379_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7745_ (.A1(\wbbd_state[9] ),
+ .A2(net184),
+ .B1(\wbbd_state[8] ),
+ .B2(net167),
+ .C1(_3379_),
+ .X(_0174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7746_ (.A(\wbbd_state[7] ),
+ .B(net177),
+ .X(_3380_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7747_ (.A1(\wbbd_state[9] ),
+ .A2(net185),
+ .B1(\wbbd_state[8] ),
+ .B2(net168),
+ .C1(_3380_),
+ .X(_0175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7748_ (.A(\wbbd_state[7] ),
+ .B(net178),
+ .X(_3381_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7749_ (.A1(\wbbd_state[9] ),
+ .A2(net187),
+ .B1(\wbbd_state[8] ),
+ .B2(net169),
+ .C1(_3381_),
+ .X(_0176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7750_ (.A(\wbbd_state[7] ),
+ .B(net179),
+ .X(_3382_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7751_ (.A1(\wbbd_state[9] ),
+ .A2(net188),
+ .B1(\wbbd_state[8] ),
+ .B2(net170),
+ .C1(_3382_),
+ .X(_0177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7752_ (.A(net153),
+ .Y(_3383_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7753_ (.A(net142),
+ .B(net131),
+ .X(_3384_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _7754_ (.A(net156),
+ .B(_3383_),
+ .C(_3384_),
+ .X(_3385_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7755_ (.A(_3385_),
+ .Y(_3386_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7756_ (.A(net144),
+ .B(_1795_),
+ .C(_1791_),
+ .X(_3387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _7757_ (.A(_3387_),
+ .X(_3388_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _7758_ (.A(_3388_),
+ .Y(_3389_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7759_ (.A(net158),
+ .B(net157),
+ .C(net159),
+ .D(net160),
+ .X(_3390_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7760_ (.A(_3390_),
+ .Y(_3391_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_2 _7761_ (.A(_3386_),
+ .B(_3389_),
+ .C(_3391_),
+ .X(_3392_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _7762_ (.A(net156),
+ .Y(_3393_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7763_ (.A(_3393_),
+ .B(net153),
+ .C(_3384_),
+ .X(_3394_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7764_ (.A(_3394_),
+ .X(_3395_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _7765_ (.A(net157),
+ .Y(_3396_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7766_ (.A(_3384_),
+ .Y(_3397_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _7767_ (.A(_3393_),
+ .B(_3383_),
+ .C(_3397_),
+ .X(_3398_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_1 _7768_ (.A(net139),
+ .B(net138),
+ .C(net141),
+ .D(net140),
+ .Y(_3399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _7769_ (.A(net160),
+ .Y(_3400_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7770_ (.A(net137),
+ .B(net136),
+ .Y(_3401_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4_1 _7771_ (.A(net133),
+ .B(net132),
+ .C(net135),
+ .D(net134),
+ .Y(_3402_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7772_ (.A(net159),
+ .Y(_3403_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _7773_ (.A(net158),
+ .Y(_3404_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand4bb_1 _7774_ (.A_N(_3403_),
+ .B_N(_3404_),
+ .C(net162),
+ .D(net161),
+ .Y(_3405_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7775_ (.A(_3400_),
+ .B(_3401_),
+ .C(_3402_),
+ .D(_3405_),
+ .X(_3406_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7776_ (.A(_3396_),
+ .B(_3398_),
+ .C(_3399_),
+ .D(_3406_),
+ .X(_3407_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7777_ (.A(_3407_),
+ .Y(_3408_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7778_ (.A1(_1795_),
+ .A2(_3408_),
+ .B1(net143),
+ .B2(_3407_),
+ .X(_3409_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _7779_ (.A1(net144),
+ .A2(net143),
+ .B1(_1796_),
+ .Y(_3410_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7780_ (.A(_3410_),
+ .Y(_3411_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7781_ (.A(net146),
+ .B(net145),
+ .Y(_3412_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_2 _7782_ (.A1(net144),
+ .A2(net143),
+ .A3(_3412_),
+ .B1(_1791_),
+ .B2(_1796_),
+ .X(_3413_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _7783_ (.A1(_3411_),
+ .A2(_3408_),
+ .B1(net144),
+ .B2(_3407_),
+ .C1(_3413_),
+ .X(_3414_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7784_ (.A(_3409_),
+ .B(_3414_),
+ .X(_3415_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7785_ (.A(_3404_),
+ .B(_3396_),
+ .C(_3398_),
+ .X(_3416_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7786_ (.A(_3416_),
+ .Y(_3417_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7787_ (.A(_3403_),
+ .B(_3416_),
+ .X(_3418_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _7788_ (.A1(net159),
+ .A2(_3417_),
+ .B1(_3418_),
+ .Y(_3419_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _7789_ (.A1(net159),
+ .A2(_3417_),
+ .A3(net160),
+ .B1(_3400_),
+ .B2(_3418_),
+ .X(_3420_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7790_ (.A(_3419_),
+ .B(_3420_),
+ .Y(_3421_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7791_ (.A(_3396_),
+ .B(_3398_),
+ .Y(_3422_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7792_ (.A(net158),
+ .B(_3422_),
+ .Y(_3423_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_2 _7793_ (.A1(_3396_),
+ .A2(_3398_),
+ .B1(_3422_),
+ .X(_3424_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _7794_ (.A1(_3417_),
+ .A2(_3423_),
+ .B1(_3424_),
+ .Y(_3425_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7795_ (.A(_3421_),
+ .B(_3425_),
+ .X(_3426_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7796_ (.A(_3415_),
+ .B(_3426_),
+ .X(_3427_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _7797_ (.A(_3427_),
+ .X(_3428_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _7798_ (.A(_3395_),
+ .B(_3428_),
+ .Y(_3429_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_6 _7799_ (.A(net142),
+ .Y(_3430_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _7800_ (.A(_3430_),
+ .B(net131),
+ .C(net156),
+ .X(_3431_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7801_ (.A(_3383_),
+ .B(_3431_),
+ .X(_3432_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7802_ (.A(_3432_),
+ .X(_3433_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7803_ (.A(_3428_),
+ .B(_3433_),
+ .Y(_3434_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _7804_ (.A(_3430_),
+ .B(_3393_),
+ .C(net153),
+ .X(_3435_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7805_ (.A(net131),
+ .B(_3435_),
+ .X(_3436_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7806_ (.A(_3436_),
+ .X(_3437_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7807_ (.A(_3390_),
+ .B(_3437_),
+ .X(_3438_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _7808_ (.A(_3388_),
+ .B(_3438_),
+ .Y(_3439_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7809_ (.A(net159),
+ .B(net160),
+ .C(net158),
+ .D(_3396_),
+ .X(_3440_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7810_ (.A(_3388_),
+ .B(_3440_),
+ .X(_3441_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_8 _7811_ (.A(_3441_),
+ .X(_3442_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7812_ (.A(net156),
+ .B(net153),
+ .C(_3384_),
+ .X(_3443_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7813_ (.A(_3443_),
+ .X(_3444_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7814_ (.A(_3430_),
+ .B(net131),
+ .C(_3393_),
+ .D(_3383_),
+ .X(_3445_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7815_ (.A(_3445_),
+ .X(_3446_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7816_ (.A(_3442_),
+ .B(_3446_),
+ .X(_3447_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7817_ (.A(_3444_),
+ .Y(_3448_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7818_ (.A(net159),
+ .B(net160),
+ .C(_3404_),
+ .D(net157),
+ .X(_3449_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7819_ (.A(_3449_),
+ .X(_3450_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7820_ (.A(_3450_),
+ .Y(_3451_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _7821_ (.A(_3393_),
+ .B(_3383_),
+ .C(_3384_),
+ .X(_3452_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_4 _7822_ (.A(_3442_),
+ .B(_3452_),
+ .Y(_3453_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _7823_ (.A(_3417_),
+ .B(_3423_),
+ .C_N(_3424_),
+ .X(_3454_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7824_ (.A(_3421_),
+ .B(_3454_),
+ .C(_3415_),
+ .X(_3455_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _7825_ (.A(_3455_),
+ .X(_3456_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7826_ (.A(_3456_),
+ .B(_3452_),
+ .X(_3457_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7827_ (.A(_3457_),
+ .Y(_3458_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7828_ (.A(_3446_),
+ .B(_3450_),
+ .C(_3388_),
+ .X(_3459_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7829_ (.A(_3459_),
+ .Y(_3460_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7830_ (.A(net159),
+ .B(net160),
+ .C(_3404_),
+ .D(_3396_),
+ .X(_3461_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7831_ (.A(_3461_),
+ .Y(_3462_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7832_ (.A(net144),
+ .B(net143),
+ .C(_1791_),
+ .X(_3463_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7833_ (.A(_3463_),
+ .X(_3464_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 _7834_ (.A(_3464_),
+ .X(_3465_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _7835_ (.A(_3465_),
+ .Y(_3466_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _7836_ (.A(_3391_),
+ .B(_3466_),
+ .C(_3448_),
+ .X(_3467_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _7837_ (.A(_1794_),
+ .B(net143),
+ .C(_1791_),
+ .X(_3468_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7838_ (.A(net156),
+ .B(_3384_),
+ .C(_3390_),
+ .D(_3468_),
+ .X(_3469_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7839_ (.A(net131),
+ .Y(_3470_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7840_ (.A(net156),
+ .B(_3383_),
+ .C(net142),
+ .D(_3470_),
+ .X(_3471_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7841_ (.A(_3471_),
+ .X(_3472_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7842_ (.A(_3450_),
+ .B(_3465_),
+ .X(_3473_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7843_ (.A(_3472_),
+ .B(_3473_),
+ .X(_3474_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7844_ (.A(_3393_),
+ .B(net153),
+ .C(net142),
+ .D(_3470_),
+ .X(_3475_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7845_ (.A(_3475_),
+ .X(_3476_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7846_ (.A(_3393_),
+ .B(_3383_),
+ .C(net142),
+ .D(_3470_),
+ .X(_3477_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7847_ (.A(_3477_),
+ .X(_3478_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7848_ (.A(_3473_),
+ .B(_3478_),
+ .X(_3479_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7849_ (.A(net156),
+ .B(net153),
+ .C(net142),
+ .D(_3470_),
+ .X(_3480_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7850_ (.A(_3480_),
+ .X(_3481_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7851_ (.A(_3461_),
+ .B(_3465_),
+ .X(_3482_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 _7852_ (.A(_3482_),
+ .X(_3483_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7853_ (.A(_3481_),
+ .B(_3483_),
+ .X(_3484_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7854_ (.A(_3472_),
+ .B(_3483_),
+ .Y(_3485_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7855_ (.A(_3478_),
+ .B(_3483_),
+ .Y(_3486_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7856_ (.A(net158),
+ .B(net157),
+ .C(_3403_),
+ .D(net160),
+ .X(_3487_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7857_ (.A(_3465_),
+ .B(_3487_),
+ .X(_3488_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 _7858_ (.A(_3488_),
+ .X(_3489_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7859_ (.A(_3481_),
+ .B(_3489_),
+ .Y(_3490_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7860_ (.A(_3472_),
+ .B(_3489_),
+ .Y(_3491_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7861_ (.A(_3476_),
+ .Y(_3492_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7862_ (.A(_3487_),
+ .Y(_3493_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7863_ (.A(_3465_),
+ .B(_3476_),
+ .X(_3494_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7864_ (.A(_3494_),
+ .X(_3495_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7865_ (.A(_3403_),
+ .B(net160),
+ .C(net158),
+ .D(_3396_),
+ .X(_3496_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _7866_ (.A(_3496_),
+ .X(_3497_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7867_ (.A(_3403_),
+ .B(net160),
+ .C(_3404_),
+ .D(net157),
+ .X(_3498_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7868_ (.A(_3498_),
+ .X(_3499_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7869_ (.A(_3464_),
+ .B(_3499_),
+ .X(_3500_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7870_ (.A(_3500_),
+ .X(_3501_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _7871_ (.A(_3472_),
+ .B(_3501_),
+ .Y(_3502_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7872_ (.A(_3404_),
+ .B(_3396_),
+ .C(_3403_),
+ .D(net160),
+ .X(_3503_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _7873_ (.A(_3503_),
+ .X(_3504_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7874_ (.A(_3504_),
+ .B(_3464_),
+ .X(_3505_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _7875_ (.A(net158),
+ .B(net157),
+ .C(net159),
+ .D(_3400_),
+ .X(_3506_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7876_ (.A(_3464_),
+ .B(_3506_),
+ .X(_3507_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7877_ (.A(_3472_),
+ .B(_3507_),
+ .X(_3508_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7878_ (.A(_3440_),
+ .B(_3444_),
+ .X(_3509_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7879_ (.A(_3468_),
+ .B(_3509_),
+ .Y(_3510_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7880_ (.A(_3390_),
+ .B(_3452_),
+ .X(_3511_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7881_ (.A(_3511_),
+ .Y(_3512_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7882_ (.A(_3390_),
+ .B(_3446_),
+ .X(_3513_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7883_ (.A(_3513_),
+ .Y(_3514_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _7884_ (.A(net159),
+ .B(_3400_),
+ .C(_3404_),
+ .X(_3515_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7885_ (.A(_3472_),
+ .B(_3515_),
+ .X(_3516_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4bb_1 _7886_ (.A(_3512_),
+ .B(_3514_),
+ .C_N(_3509_),
+ .D_N(_3516_),
+ .X(_3517_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _7887_ (.A1(_3466_),
+ .A2(_3510_),
+ .B1(_3517_),
+ .Y(_3518_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7888_ (.A(_3465_),
+ .B(_3481_),
+ .X(_3519_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7889_ (.A(net158),
+ .B(_3396_),
+ .C(net159),
+ .D(_3400_),
+ .X(_3520_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _7890_ (.A(_3520_),
+ .X(_3521_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7891_ (.A(_3519_),
+ .B(_3521_),
+ .X(_3522_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _7892_ (.A1(_3472_),
+ .A2(_3476_),
+ .B1(_3465_),
+ .C1(_3521_),
+ .X(_3523_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _7893_ (.A1(_3478_),
+ .A2(_3507_),
+ .B1(_3522_),
+ .C1(_3523_),
+ .X(_3524_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7894_ (.A(_3404_),
+ .B(net157),
+ .C(net159),
+ .D(_3400_),
+ .X(_3525_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_8 _7895_ (.A(_3525_),
+ .X(_3526_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7896_ (.A(_3519_),
+ .B(_3526_),
+ .X(_3527_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7897_ (.A(_3409_),
+ .Y(_3528_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7898_ (.A(_3528_),
+ .B(_3414_),
+ .X(_3529_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7899_ (.A(_3454_),
+ .B(_3529_),
+ .X(_3530_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_2 _7900_ (.A(_3420_),
+ .B_N(_3419_),
+ .X(_3531_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7901_ (.A(_3530_),
+ .B(_3531_),
+ .X(_3532_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7902_ (.A(_3478_),
+ .B(_3532_),
+ .X(_3533_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7903_ (.A(_3404_),
+ .B(_3396_),
+ .C(net159),
+ .D(_3400_),
+ .X(_3534_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7904_ (.A(_3534_),
+ .X(_3535_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _7905_ (.A1(_3465_),
+ .A2(_3478_),
+ .A3(_3526_),
+ .B1(_3519_),
+ .B2(_3535_),
+ .X(_3536_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _7906_ (.A1(_3495_),
+ .A2(_3515_),
+ .B1(_3527_),
+ .C1(_3533_),
+ .D1(_3536_),
+ .X(_3537_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_2 _7907_ (.A1(_3495_),
+ .A2(_3506_),
+ .B1(_3518_),
+ .C1(_3524_),
+ .D1(_3537_),
+ .X(_3538_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7908_ (.A(_3481_),
+ .B(_3507_),
+ .X(_3539_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _7909_ (.A1(_3478_),
+ .A2(_3505_),
+ .B1(_3508_),
+ .C1(_3538_),
+ .D1(_3539_),
+ .X(_3540_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7910_ (.A(_3472_),
+ .B(_3505_),
+ .X(_3541_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7911_ (.A(_3481_),
+ .B(_3505_),
+ .X(_3542_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _7912_ (.A1(_3504_),
+ .A2(_3495_),
+ .B1(_3540_),
+ .C1(_3541_),
+ .D1(_3542_),
+ .X(_3543_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_1 _7913_ (.A1(_3478_),
+ .A2(_3501_),
+ .B1(_3495_),
+ .B2(_3499_),
+ .C1(_3543_),
+ .Y(_3544_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7914_ (.A(_3481_),
+ .B(_3501_),
+ .Y(_3545_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7915_ (.A(_3464_),
+ .B(_3497_),
+ .X(_3546_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7916_ (.A(_3478_),
+ .B(_3546_),
+ .Y(_3547_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_1 _7917_ (.A(_3502_),
+ .B(_3544_),
+ .C(_3545_),
+ .D(_3547_),
+ .Y(_3548_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7918_ (.A(_3472_),
+ .B(_3546_),
+ .X(_3549_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7919_ (.A(_3481_),
+ .B(_3546_),
+ .X(_3550_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _7920_ (.A1(_3495_),
+ .A2(_3497_),
+ .B1(_3548_),
+ .C1(_3549_),
+ .D1(_3550_),
+ .X(_3551_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _7921_ (.A1(_3478_),
+ .A2(_3489_),
+ .B1(_3551_),
+ .Y(_3552_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _7922_ (.A1(_3466_),
+ .A2(_3492_),
+ .A3(_3493_),
+ .B1(_3552_),
+ .X(_3553_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7923_ (.A(_3491_),
+ .B(_3553_),
+ .X(_3554_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7924_ (.A(_3490_),
+ .B(_3554_),
+ .X(_3555_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7925_ (.A(_3486_),
+ .B(_3555_),
+ .Y(_3556_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _7926_ (.A1(_3476_),
+ .A2(_3483_),
+ .B1(_3556_),
+ .Y(_3557_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _7927_ (.A(_3485_),
+ .B(_3557_),
+ .Y(_3558_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7928_ (.A(_3484_),
+ .B(_3558_),
+ .X(_3559_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7929_ (.A(_3479_),
+ .B(_3559_),
+ .Y(_3560_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ba_1 _7930_ (.A1(_3473_),
+ .A2(_3476_),
+ .B1_N(_3560_),
+ .X(_3561_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _7931_ (.A(_3474_),
+ .B(_3561_),
+ .X(_3562_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _7932_ (.A1(_3383_),
+ .A2(_3469_),
+ .B1(_3562_),
+ .Y(_3563_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7933_ (.A(_3467_),
+ .B(_3563_),
+ .X(_3564_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _7934_ (.A1(_3389_),
+ .A2(_3448_),
+ .A3(_3462_),
+ .B1(_3564_),
+ .X(_3565_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7935_ (.A(_3460_),
+ .B(_3565_),
+ .X(_3566_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7936_ (.A(_3458_),
+ .B(_3566_),
+ .X(_3567_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311oi_1 _7937_ (.A1(_3389_),
+ .A2(_3448_),
+ .A3(_3451_),
+ .B1(_3453_),
+ .C1(_3567_),
+ .Y(_3568_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _7938_ (.A(_3447_),
+ .B(_3568_),
+ .Y(_3569_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ba_1 _7939_ (.A1(_3442_),
+ .A2(_3395_),
+ .B1_N(_3569_),
+ .X(_3570_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _7940_ (.A1(_3442_),
+ .A2(_3444_),
+ .B1(_3570_),
+ .Y(_3571_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7941_ (.A(_3439_),
+ .B(_3571_),
+ .X(_3572_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7942_ (.A(_3429_),
+ .B(_3434_),
+ .C(_3572_),
+ .X(_3573_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7943_ (.A(_3392_),
+ .B(_3573_),
+ .X(_3574_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _7944_ (.A(_3574_),
+ .X(_0178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _7945_ (.A1(_3478_),
+ .A2(_3428_),
+ .B1(\wbbd_state[9] ),
+ .Y(_3575_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7946_ (.A(_3430_),
+ .B(_3470_),
+ .X(_3576_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7947_ (.A(net156),
+ .B(net153),
+ .C(_3576_),
+ .X(_3577_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7948_ (.A(_3577_),
+ .X(_3578_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7949_ (.A(_3428_),
+ .B(_3578_),
+ .X(_3579_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7950_ (.A(_3390_),
+ .B(_3472_),
+ .C(_3388_),
+ .X(_3580_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _7951_ (.A(net158),
+ .B(_3424_),
+ .C(_3421_),
+ .D(_3415_),
+ .X(_3581_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7952_ (.A(_3581_),
+ .X(_3582_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7953_ (.A(_3470_),
+ .B(_3435_),
+ .X(_3583_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _7954_ (.A(_3583_),
+ .X(_3584_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _7955_ (.A(_3582_),
+ .B(_3584_),
+ .Y(_3585_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7956_ (.A(_3430_),
+ .B(_3393_),
+ .C(_3383_),
+ .X(_3586_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7957_ (.A(_3404_),
+ .B(_3396_),
+ .C(_3586_),
+ .X(_3587_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7958_ (.A(_3396_),
+ .B(_3586_),
+ .X(_3588_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _7959_ (.A(_3403_),
+ .B(_3404_),
+ .C(_3588_),
+ .X(_3589_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7960_ (.A(_3589_),
+ .Y(_3590_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _7961_ (.A1(_3403_),
+ .A2(_3587_),
+ .B1(_3590_),
+ .Y(_3591_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _7962_ (.A1(net160),
+ .A2(_3590_),
+ .B1(_3400_),
+ .B2(_3589_),
+ .X(_3592_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7963_ (.A(_3591_),
+ .B(_3592_),
+ .X(_3593_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_2 _7964_ (.A1(_3396_),
+ .A2(_3586_),
+ .B1_N(_3588_),
+ .X(_3594_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _7965_ (.A(_3404_),
+ .B(_3594_),
+ .X(_3595_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _7966_ (.A(_3399_),
+ .B(_3588_),
+ .C(_3406_),
+ .X(_3596_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2bb2a_1 _7967_ (.A1_N(_1795_),
+ .A2_N(_3596_),
+ .B1(_1795_),
+ .B2(_3596_),
+ .X(_3597_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7968_ (.A(_3597_),
+ .B(_3413_),
+ .X(_3598_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7969_ (.A(_3411_),
+ .B(_3598_),
+ .X(_3599_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _7970_ (.A(_3599_),
+ .X(_3600_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7971_ (.A(_3595_),
+ .B(_3600_),
+ .X(_3601_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7972_ (.A(_3593_),
+ .B(_3601_),
+ .X(_3602_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7973_ (.A(_3602_),
+ .X(_3603_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7974_ (.A(net153),
+ .B(_3431_),
+ .X(_3604_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _7975_ (.A(_3604_),
+ .X(_3605_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21bo_1 _7976_ (.A1(_3404_),
+ .A2(_3588_),
+ .B1_N(_3587_),
+ .X(_3606_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_4 _7977_ (.A(_3594_),
+ .B(_3606_),
+ .Y(_3607_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7978_ (.A(_3607_),
+ .B(_3600_),
+ .X(_3608_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7979_ (.A(_3591_),
+ .Y(_3609_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _7980_ (.A(net160),
+ .B(_3609_),
+ .X(_3610_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7981_ (.A(_3608_),
+ .B(_3610_),
+ .X(_3611_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7982_ (.A(_3611_),
+ .X(_3612_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _7983_ (.A(_3446_),
+ .Y(_3613_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _7984_ (.A(net158),
+ .B(_3594_),
+ .C(_3600_),
+ .X(_3614_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7985_ (.A(_3614_),
+ .B(_3610_),
+ .X(_3615_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _7986_ (.A(_3615_),
+ .X(_3616_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _7987_ (.A(_3616_),
+ .Y(_3617_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_2 _7988_ (.A(_3606_),
+ .B_N(_3594_),
+ .X(_3618_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7989_ (.A(_3600_),
+ .B(_3618_),
+ .X(_3619_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7990_ (.A(_3619_),
+ .B(_3610_),
+ .X(_3620_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7991_ (.A(_3620_),
+ .X(_3621_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7992_ (.A(_3601_),
+ .B(_3610_),
+ .X(_3622_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _7993_ (.A(_3622_),
+ .X(_3623_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_4 _7994_ (.A(_3609_),
+ .B(_3592_),
+ .Y(_3624_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7995_ (.A(_3624_),
+ .B(_3608_),
+ .X(_3625_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7996_ (.A(_3625_),
+ .X(_3626_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7997_ (.A(_3624_),
+ .B(_3614_),
+ .X(_3627_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 _7998_ (.A(_3627_),
+ .X(_3628_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _7999_ (.A(_3624_),
+ .B(_3619_),
+ .X(_3629_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _8000_ (.A(_3629_),
+ .X(_3630_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8001_ (.A(_3446_),
+ .B(_3630_),
+ .Y(_3631_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8002_ (.A(_3390_),
+ .B(_3478_),
+ .X(_3632_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8003_ (.A(_3632_),
+ .Y(_3633_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8004_ (.A(_3390_),
+ .B(_3584_),
+ .X(_3634_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8005_ (.A(_3634_),
+ .Y(_3635_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _8006_ (.A(_3529_),
+ .Y(_3636_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8007_ (.A1(_3633_),
+ .A2(_3635_),
+ .B1(_3636_),
+ .X(_3637_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _8008_ (.A(_3413_),
+ .B(_3410_),
+ .C(_3528_),
+ .X(_3638_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8009_ (.A(_3632_),
+ .B(_3638_),
+ .X(_3639_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8010_ (.A1(_3495_),
+ .A2(_3426_),
+ .B1(_3639_),
+ .Y(_3640_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8011_ (.A(_3404_),
+ .B(_3424_),
+ .C(_3529_),
+ .X(_3641_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8012_ (.A(_3641_),
+ .B(_3531_),
+ .X(_3642_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8013_ (.A(_3446_),
+ .B(_3642_),
+ .X(_3643_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8014_ (.A1(_3437_),
+ .A2(_3630_),
+ .B1(_3643_),
+ .Y(_3644_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _8015_ (.A1(_3532_),
+ .A2(_3642_),
+ .B1(_3431_),
+ .Y(_3645_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8016_ (.A(_3637_),
+ .B(_3640_),
+ .C(_3644_),
+ .D(_3645_),
+ .X(_3646_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8017_ (.A(_3437_),
+ .B(_3628_),
+ .X(_3647_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8018_ (.A(_3433_),
+ .B(_3628_),
+ .X(_3648_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_1 _8019_ (.A_N(_3631_),
+ .B_N(_3646_),
+ .C(_3647_),
+ .D(_3648_),
+ .X(_3649_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8020_ (.A1(_3628_),
+ .A2(_3605_),
+ .B1(_3446_),
+ .B2(_3628_),
+ .C1(_3649_),
+ .X(_3650_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8021_ (.A(_3437_),
+ .B(_3626_),
+ .X(_3651_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8022_ (.A(_3433_),
+ .B(_3626_),
+ .X(_3652_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8023_ (.A1(_3605_),
+ .A2(_3626_),
+ .B1(_3650_),
+ .C1(_3651_),
+ .D1(_3652_),
+ .X(_3653_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8024_ (.A(_3437_),
+ .B(_3623_),
+ .X(_3654_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8025_ (.A(_3433_),
+ .B(_3623_),
+ .X(_3655_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8026_ (.A1(_3446_),
+ .A2(_3626_),
+ .B1(_3653_),
+ .C1(_3654_),
+ .D1(_3655_),
+ .X(_3656_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8027_ (.A1(_3605_),
+ .A2(_3623_),
+ .B1(_3446_),
+ .B2(_3623_),
+ .C1(_3656_),
+ .X(_3657_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8028_ (.A(_3437_),
+ .B(_3621_),
+ .X(_3658_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8029_ (.A(_3433_),
+ .B(_3621_),
+ .X(_3659_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8030_ (.A1(_3605_),
+ .A2(_3621_),
+ .B1(_3657_),
+ .C1(_3658_),
+ .D1(_3659_),
+ .X(_3660_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8031_ (.A1(_3446_),
+ .A2(_3621_),
+ .B1(_3660_),
+ .Y(_3661_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8032_ (.A(_3437_),
+ .B(_3616_),
+ .Y(_3662_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8033_ (.A(_3661_),
+ .B(_3662_),
+ .Y(_3663_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8034_ (.A(_3433_),
+ .B(_3616_),
+ .X(_3664_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8035_ (.A(_3663_),
+ .B(_3664_),
+ .X(_3665_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8036_ (.A1(_3605_),
+ .A2(_3616_),
+ .B1(_3665_),
+ .Y(_3666_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _8037_ (.A1(_3613_),
+ .A2(_3617_),
+ .B1(_3666_),
+ .Y(_3667_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8038_ (.A(_3437_),
+ .B(_3612_),
+ .X(_3668_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8039_ (.A(_3667_),
+ .B(_3668_),
+ .Y(_3669_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8040_ (.A(_3433_),
+ .B(_3612_),
+ .Y(_3670_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8041_ (.A(_3669_),
+ .B(_3670_),
+ .Y(_3671_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8042_ (.A1(_3605_),
+ .A2(_3612_),
+ .B1(_3671_),
+ .X(_3672_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8043_ (.A1(_3446_),
+ .A2(_3612_),
+ .B1(_3672_),
+ .Y(_3673_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8044_ (.A(_3437_),
+ .B(_3603_),
+ .Y(_3674_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8045_ (.A(_3673_),
+ .B(_3674_),
+ .Y(_3675_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8046_ (.A(_3433_),
+ .B(_3603_),
+ .X(_3676_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8047_ (.A(_3675_),
+ .B(_3676_),
+ .X(_3677_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8048_ (.A1(_3603_),
+ .A2(_3605_),
+ .B1(_3677_),
+ .Y(_3678_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ba_1 _8049_ (.A1(_3446_),
+ .A2(_3603_),
+ .B1_N(_3678_),
+ .X(_3679_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8050_ (.A(_3593_),
+ .B(_3619_),
+ .X(_3680_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 _8051_ (.A(_3680_),
+ .X(_3681_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8052_ (.A(_3437_),
+ .B(_3681_),
+ .X(_3682_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8053_ (.A(_3679_),
+ .B(_3682_),
+ .Y(_3683_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8054_ (.A(_3433_),
+ .B(_3681_),
+ .Y(_3684_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8055_ (.A(_3683_),
+ .B(_3684_),
+ .Y(_3685_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8056_ (.A(_3605_),
+ .B(_3681_),
+ .X(_3686_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8057_ (.A(_3685_),
+ .B(_3686_),
+ .Y(_3687_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8058_ (.A(_3481_),
+ .Y(_3688_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8059_ (.A(_3426_),
+ .Y(_3689_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8060_ (.A(_3638_),
+ .Y(_3690_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8061_ (.A(_3688_),
+ .B(_3689_),
+ .C(_3690_),
+ .X(_3691_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8062_ (.A(_3687_),
+ .B(_3691_),
+ .X(_3692_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _8063_ (.A(_3478_),
+ .Y(_3693_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8064_ (.A(_3693_),
+ .B(_3689_),
+ .C(_3636_),
+ .X(_3694_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8065_ (.A(_3692_),
+ .B(_3694_),
+ .X(_3695_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8066_ (.A(_3451_),
+ .B(_3693_),
+ .C(_3389_),
+ .X(_3696_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8067_ (.A(_3695_),
+ .B(_3696_),
+ .Y(_3697_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8068_ (.A(_3456_),
+ .B(_3584_),
+ .X(_3698_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8069_ (.A(_3697_),
+ .B(_3698_),
+ .Y(_3699_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _8070_ (.A1(_3456_),
+ .A2(_3476_),
+ .B1_N(_3699_),
+ .Y(_3700_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_4 _8071_ (.A(_3442_),
+ .B(_3478_),
+ .Y(_3701_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8072_ (.A(_3476_),
+ .B(_3582_),
+ .Y(_3702_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8073_ (.A(_3701_),
+ .B(_3702_),
+ .X(_3703_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8074_ (.A(_3700_),
+ .B(_3703_),
+ .X(_3704_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8075_ (.A(_3585_),
+ .B(_3704_),
+ .Y(_3705_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8076_ (.A1(_3472_),
+ .A2(_3582_),
+ .B1(_3705_),
+ .Y(_3706_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8077_ (.A(_3478_),
+ .B(_3582_),
+ .Y(_3707_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8078_ (.A(_3706_),
+ .B(_3707_),
+ .Y(_3708_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8079_ (.A(net156),
+ .B(_3383_),
+ .C(_3576_),
+ .X(_3709_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 _8080_ (.A(_3709_),
+ .X(_3710_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8081_ (.A(_3428_),
+ .B(_3710_),
+ .X(_3711_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8082_ (.A(_3708_),
+ .B(_3711_),
+ .X(_3712_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8083_ (.A(_3579_),
+ .B(_3580_),
+ .C(_3712_),
+ .X(_3713_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8084_ (.A(_3415_),
+ .B(_3481_),
+ .X(_3714_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8085_ (.A(_3426_),
+ .B(_3714_),
+ .X(_3715_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8086_ (.A(_3713_),
+ .B(_3715_),
+ .Y(_3716_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _8087_ (.A(_3575_),
+ .B_N(_3716_),
+ .X(_3717_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8088_ (.A(_3428_),
+ .B(_3605_),
+ .Y(_3718_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8089_ (.A0(_3410_),
+ .A1(_1794_),
+ .S(_3596_),
+ .X(_3719_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4bb_4 _8090_ (.A(_3413_),
+ .B(_3593_),
+ .C_N(_3597_),
+ .D_N(_3719_),
+ .X(_3720_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8091_ (.A(net158),
+ .B(_3594_),
+ .C(_3720_),
+ .X(_3721_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8092_ (.A(_3721_),
+ .Y(_3722_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8093_ (.A(_3431_),
+ .B(_3721_),
+ .Y(_3723_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8094_ (.A(_3447_),
+ .Y(_3724_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8095_ (.A(_3437_),
+ .B(_3582_),
+ .Y(_3725_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8096_ (.A(_3607_),
+ .B(_3593_),
+ .X(_3726_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8097_ (.A(_3726_),
+ .B(_3446_),
+ .X(_3727_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8098_ (.A(_3600_),
+ .B(_3727_),
+ .Y(_3728_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8099_ (.A(_3470_),
+ .B(_3586_),
+ .X(_3729_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 _8100_ (.A(_3729_),
+ .X(_3730_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _8101_ (.A(_3730_),
+ .Y(_3731_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8102_ (.A(_3470_),
+ .B(_3596_),
+ .X(_3732_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8103_ (.A(_3732_),
+ .Y(_3733_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a22o_1 _8104_ (.A1(net144),
+ .A2(_3732_),
+ .B1(_3411_),
+ .B2(_3733_),
+ .X(_3734_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _8105_ (.A1(_1795_),
+ .A2(_3733_),
+ .B1(net143),
+ .B2(_3732_),
+ .X(_3735_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8106_ (.A(_3735_),
+ .Y(_3736_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8107_ (.A(_3413_),
+ .B(_3734_),
+ .C(_3736_),
+ .X(_3737_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _8108_ (.A(_3737_),
+ .X(_3738_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8109_ (.A(_3738_),
+ .Y(_3739_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_2 _8110_ (.A(_3731_),
+ .B(_3451_),
+ .C(_3739_),
+ .X(_3740_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _8111_ (.A(_3578_),
+ .Y(_3741_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 _8112_ (.A(_3710_),
+ .Y(_3742_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8113_ (.A(_3628_),
+ .B(_3578_),
+ .Y(_3743_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8114_ (.A(_3584_),
+ .Y(_3744_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8115_ (.A(_3628_),
+ .Y(_3745_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8116_ (.A(_3601_),
+ .B(_3624_),
+ .X(_3746_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_2 _8117_ (.A(_3630_),
+ .B(_3746_),
+ .Y(_3747_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8118_ (.A(_3393_),
+ .B(net153),
+ .C_N(_3630_),
+ .X(_3748_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8119_ (.A(_3438_),
+ .Y(_3749_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _8120_ (.A(_3719_),
+ .B(_3598_),
+ .X(_3750_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8121_ (.A1(_3513_),
+ .A2(_3750_),
+ .B1(_3600_),
+ .Y(_3751_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31a_1 _8122_ (.A1(_3514_),
+ .A2(_3512_),
+ .A3(_3749_),
+ .B1(_3751_),
+ .X(_3752_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a41o_2 _8123_ (.A1(net142),
+ .A2(net131),
+ .A3(_3747_),
+ .A4(_3748_),
+ .B1(_3752_),
+ .X(_3753_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a221o_1 _8124_ (.A1(_3744_),
+ .A2(_3745_),
+ .B1(_3745_),
+ .B2(_3742_),
+ .C1(_3753_),
+ .X(_3754_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8125_ (.A(_3730_),
+ .B(_3628_),
+ .Y(_3755_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8126_ (.A(_3584_),
+ .B(_3626_),
+ .Y(_3756_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8127_ (.A(_3743_),
+ .B(_3754_),
+ .C(_3755_),
+ .D(_3756_),
+ .X(_3757_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8128_ (.A(_3626_),
+ .B(_3710_),
+ .Y(_3758_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8129_ (.A(_3626_),
+ .B(_3578_),
+ .Y(_3759_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8130_ (.A(_3730_),
+ .B(_3626_),
+ .Y(_3760_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8131_ (.A(_3757_),
+ .B(_3758_),
+ .C(_3759_),
+ .D(_3760_),
+ .X(_3761_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8132_ (.A(_3584_),
+ .B(_3623_),
+ .X(_3762_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8133_ (.A(_3762_),
+ .Y(_3763_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8134_ (.A(_3623_),
+ .B(_3710_),
+ .Y(_3764_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8135_ (.A(_3623_),
+ .B(_3578_),
+ .Y(_3765_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8136_ (.A(_3761_),
+ .B(_3763_),
+ .C(_3764_),
+ .D(_3765_),
+ .X(_3766_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8137_ (.A(_3730_),
+ .B(_3623_),
+ .Y(_3767_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8138_ (.A(_3584_),
+ .B(_3621_),
+ .Y(_3768_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8139_ (.A(_3621_),
+ .B(_3710_),
+ .Y(_3769_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8140_ (.A(_3766_),
+ .B(_3767_),
+ .C(_3768_),
+ .D(_3769_),
+ .X(_3770_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8141_ (.A(_3621_),
+ .B(_3578_),
+ .Y(_3771_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8142_ (.A(_3730_),
+ .B(_3621_),
+ .Y(_3772_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8143_ (.A(_3584_),
+ .B(_3616_),
+ .Y(_3773_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8144_ (.A(_3770_),
+ .B(_3771_),
+ .C(_3772_),
+ .D(_3773_),
+ .X(_3774_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _8145_ (.A1(_3617_),
+ .A2(_3742_),
+ .B1(_3774_),
+ .X(_3775_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _8146_ (.A1(_3617_),
+ .A2(_3741_),
+ .B1(_3775_),
+ .X(_3776_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8147_ (.A(_3730_),
+ .B(_3616_),
+ .Y(_3777_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8148_ (.A(_3776_),
+ .B(_3777_),
+ .X(_3778_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8149_ (.A(_3584_),
+ .B(_3612_),
+ .Y(_3779_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8150_ (.A(_3778_),
+ .B(_3779_),
+ .X(_3780_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8151_ (.A(_3612_),
+ .B(_3710_),
+ .Y(_3781_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8152_ (.A(_3780_),
+ .B(_3781_),
+ .X(_3782_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8153_ (.A(_3612_),
+ .B(_3578_),
+ .Y(_3783_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8154_ (.A(_3782_),
+ .B(_3783_),
+ .X(_3784_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8155_ (.A(_3730_),
+ .B(_3612_),
+ .Y(_3785_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8156_ (.A(_3784_),
+ .B(_3785_),
+ .X(_3786_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8157_ (.A(_3584_),
+ .B(_3603_),
+ .Y(_3787_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8158_ (.A(_3786_),
+ .B(_3787_),
+ .X(_3788_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8159_ (.A(_3603_),
+ .B(_3710_),
+ .Y(_3789_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8160_ (.A(_3788_),
+ .B(_3789_),
+ .X(_3790_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8161_ (.A(_3603_),
+ .B(_3578_),
+ .Y(_3791_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8162_ (.A(_3790_),
+ .B(_3791_),
+ .X(_3792_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8163_ (.A(_3740_),
+ .B(_3792_),
+ .X(_3793_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8164_ (.A(_3584_),
+ .B(_3681_),
+ .Y(_3794_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8165_ (.A(_3793_),
+ .B(_3794_),
+ .X(_3795_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8166_ (.A(_3681_),
+ .B(_3710_),
+ .Y(_3796_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8167_ (.A(_3795_),
+ .B(_3796_),
+ .X(_3797_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8168_ (.A(_3681_),
+ .B(_3578_),
+ .X(_3798_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8169_ (.A(_3798_),
+ .Y(_3799_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8170_ (.A(_3726_),
+ .B(_3605_),
+ .X(_3800_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8171_ (.A(_3800_),
+ .B(_3750_),
+ .X(_3801_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8172_ (.A(_3797_),
+ .B(_3799_),
+ .C_N(_3801_),
+ .X(_3802_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8173_ (.A(_3728_),
+ .B(_3802_),
+ .X(_3803_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8174_ (.A(_3460_),
+ .B(_3803_),
+ .Y(_3804_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8175_ (.A(_3457_),
+ .B(_3804_),
+ .Y(_3805_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _8176_ (.A1(_3437_),
+ .A2(_3456_),
+ .B1_N(_3805_),
+ .Y(_3806_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8177_ (.A(_3724_),
+ .B(_3725_),
+ .C(_3806_),
+ .X(_3807_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8178_ (.A(_3453_),
+ .B(_3807_),
+ .X(_3808_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _8179_ (.A1(net153),
+ .A2(_3723_),
+ .B1(_3808_),
+ .X(_3809_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _8180_ (.A1(_3613_),
+ .A2(_3722_),
+ .B1(_3809_),
+ .Y(_3810_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8181_ (.A(_3429_),
+ .B(_3434_),
+ .C(_3392_),
+ .D_N(_3810_),
+ .X(_3811_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8182_ (.A(_3718_),
+ .B(_3811_),
+ .Y(_3812_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o31ai_4 _8183_ (.A1(_3607_),
+ .A2(_3720_),
+ .A3(_3446_),
+ .B1(\wbbd_state[7] ),
+ .Y(_3813_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8184_ (.A(_3812_),
+ .B(_3813_),
+ .X(_3814_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8185_ (.A(_3579_),
+ .Y(_3815_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _8186_ (.A(_3711_),
+ .Y(_3816_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8187_ (.A(_3580_),
+ .Y(_3817_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8188_ (.A(_3476_),
+ .B(_3428_),
+ .Y(_3818_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8189_ (.A(_3396_),
+ .B(_3730_),
+ .Y(_3819_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _8190_ (.A1(_3396_),
+ .A2(_3730_),
+ .B1(_3819_),
+ .Y(_3820_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8191_ (.A(_3820_),
+ .Y(_3821_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8192_ (.A1(_3470_),
+ .A2(_3589_),
+ .B1(_3400_),
+ .X(_3822_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8193_ (.A(_3400_),
+ .B(_3589_),
+ .C(_3470_),
+ .X(_3823_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8194_ (.A(_3823_),
+ .Y(_3824_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8195_ (.A(_3470_),
+ .B(_3587_),
+ .Y(_3825_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_1 _8196_ (.A1_N(net159),
+ .A2_N(_3825_),
+ .B1(net131),
+ .B2(_3590_),
+ .X(_3826_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8197_ (.A1(_3822_),
+ .A2(_3824_),
+ .B1(_3826_),
+ .Y(_3827_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8198_ (.A(net158),
+ .B(_3821_),
+ .C(_3827_),
+ .X(_3828_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinvlp_2 _8199_ (.A(_3828_),
+ .Y(_3829_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8200_ (.A(_3413_),
+ .B(_3734_),
+ .C(_3735_),
+ .X(_3830_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8201_ (.A(_3830_),
+ .Y(_3831_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_4 _8202_ (.A(_3442_),
+ .B(_3730_),
+ .Y(_3832_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8203_ (.A(_3698_),
+ .Y(_3833_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8204_ (.A(_3823_),
+ .B(_3738_),
+ .Y(_3834_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_2 _8205_ (.A(_3395_),
+ .B(_3521_),
+ .C(_3464_),
+ .Y(_3835_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8206_ (.A(_3452_),
+ .B(_3464_),
+ .X(_3836_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _8207_ (.A(_3836_),
+ .X(_3837_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8208_ (.A(_3521_),
+ .B(_3837_),
+ .Y(_3838_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8209_ (.A(_3385_),
+ .B(_3464_),
+ .X(_3839_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 _8210_ (.A(_3839_),
+ .X(_3840_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8211_ (.A(_3526_),
+ .B(_3837_),
+ .X(_3841_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8212_ (.A1(_3526_),
+ .A2(_3840_),
+ .B1(_3841_),
+ .Y(_3842_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8213_ (.A(_3730_),
+ .B(_3828_),
+ .X(_3843_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8214_ (.A(_3843_),
+ .Y(_3844_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8215_ (.A(_3385_),
+ .B(_3535_),
+ .X(_3845_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8216_ (.A(_3395_),
+ .B(_3526_),
+ .X(_3846_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_1 _8217_ (.A1(_3444_),
+ .A2(_3526_),
+ .B1(_3632_),
+ .C1(_3845_),
+ .D1(_3846_),
+ .Y(_3847_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8218_ (.A(_3413_),
+ .B(_3410_),
+ .C(_3736_),
+ .X(_3848_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8219_ (.A(_3848_),
+ .B(_3843_),
+ .Y(_3849_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_2 _8220_ (.A1(_3635_),
+ .A2(_3844_),
+ .A3(_3847_),
+ .B1(_3739_),
+ .B2(_3849_),
+ .X(_3850_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8221_ (.A(_3395_),
+ .B(_3535_),
+ .C(_3738_),
+ .X(_3851_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8222_ (.A(_3444_),
+ .B(_3535_),
+ .C(_3738_),
+ .X(_3852_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8223_ (.A(_3851_),
+ .B(_3852_),
+ .X(_3853_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8224_ (.A(_3838_),
+ .B(_3842_),
+ .C(_3850_),
+ .D_N(_3853_),
+ .X(_3854_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8225_ (.A(_3521_),
+ .B(_3840_),
+ .Y(_3855_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8226_ (.A(_3444_),
+ .B(_3521_),
+ .C(_3464_),
+ .Y(_3856_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8227_ (.A(_3835_),
+ .B(_3854_),
+ .C(_3855_),
+ .D(_3856_),
+ .X(_3857_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8228_ (.A(_3506_),
+ .B(_3837_),
+ .Y(_3858_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8229_ (.A(_3395_),
+ .B(_3507_),
+ .Y(_3859_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8230_ (.A(_3506_),
+ .B(_3840_),
+ .Y(_3860_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8231_ (.A(_3857_),
+ .B(_3858_),
+ .C(_3859_),
+ .D(_3860_),
+ .X(_3861_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8232_ (.A(_3444_),
+ .B(_3507_),
+ .X(_3862_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8233_ (.A(_3862_),
+ .Y(_3863_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8234_ (.A(_3504_),
+ .B(_3837_),
+ .Y(_3864_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8235_ (.A(_3395_),
+ .B(_3505_),
+ .X(_3865_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8236_ (.A(_3865_),
+ .Y(_3866_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8237_ (.A(_3861_),
+ .B(_3863_),
+ .C(_3864_),
+ .D(_3866_),
+ .X(_3867_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8238_ (.A(_3504_),
+ .B(_3840_),
+ .Y(_3868_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8239_ (.A(_3444_),
+ .B(_3505_),
+ .Y(_3869_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8240_ (.A(_3499_),
+ .B(_3837_),
+ .Y(_3870_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8241_ (.A(_3867_),
+ .B(_3868_),
+ .C(_3869_),
+ .D(_3870_),
+ .X(_3871_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8242_ (.A(_3395_),
+ .B(_3501_),
+ .X(_3872_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8243_ (.A(_3872_),
+ .Y(_3873_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8244_ (.A(_3499_),
+ .B(_3840_),
+ .Y(_3874_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8245_ (.A(_3871_),
+ .B(_3873_),
+ .C(_3874_),
+ .X(_3875_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8246_ (.A(_3444_),
+ .B(_3501_),
+ .Y(_3876_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8247_ (.A(_3497_),
+ .B(_3837_),
+ .Y(_3877_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8248_ (.A(_3875_),
+ .B(_3876_),
+ .C(_3877_),
+ .X(_3878_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8249_ (.A(_3395_),
+ .B(_3546_),
+ .X(_3879_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8250_ (.A(_3879_),
+ .Y(_3880_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8251_ (.A(_3878_),
+ .B(_3880_),
+ .X(_3881_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8252_ (.A(_3497_),
+ .B(_3840_),
+ .Y(_3882_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8253_ (.A(_3881_),
+ .B(_3882_),
+ .X(_3883_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8254_ (.A(_3444_),
+ .B(_3546_),
+ .Y(_3884_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8255_ (.A(_3883_),
+ .B(_3884_),
+ .X(_3885_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8256_ (.A(_3487_),
+ .B(_3837_),
+ .Y(_3886_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8257_ (.A(_3885_),
+ .B(_3886_),
+ .X(_3887_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8258_ (.A(_3395_),
+ .B(_3489_),
+ .Y(_3888_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8259_ (.A(_3887_),
+ .B(_3888_),
+ .X(_3889_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8260_ (.A(_3487_),
+ .B(_3840_),
+ .Y(_3890_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8261_ (.A(_3889_),
+ .B(_3890_),
+ .X(_3891_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8262_ (.A(_3444_),
+ .B(_3489_),
+ .Y(_3892_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8263_ (.A(_3891_),
+ .B(_3892_),
+ .X(_3893_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8264_ (.A(_3461_),
+ .B(_3837_),
+ .Y(_3894_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8265_ (.A(_3893_),
+ .B(_3894_),
+ .X(_3895_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8266_ (.A(_3395_),
+ .B(_3483_),
+ .Y(_3896_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8267_ (.A(_3895_),
+ .B(_3896_),
+ .X(_3897_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8268_ (.A(_3385_),
+ .B(_3483_),
+ .Y(_3898_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8269_ (.A(_3897_),
+ .B(_3898_),
+ .X(_3899_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8270_ (.A(_3444_),
+ .B(_3483_),
+ .Y(_3900_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8271_ (.A(_3899_),
+ .B(_3900_),
+ .X(_3901_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8272_ (.A(_3452_),
+ .B(_3450_),
+ .C(_3465_),
+ .Y(_3902_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8273_ (.A(_3901_),
+ .B(_3902_),
+ .X(_3903_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8274_ (.A(_3395_),
+ .B(_3450_),
+ .C(_3465_),
+ .Y(_3904_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8275_ (.A(_3903_),
+ .B(_3904_),
+ .X(_3905_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8276_ (.A(_3385_),
+ .B(_3450_),
+ .C(_3465_),
+ .X(_3906_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_1 _8277_ (.A1(net158),
+ .A2(_3396_),
+ .A3(_3730_),
+ .B1(_3404_),
+ .B2(_3819_),
+ .X(_3907_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8278_ (.A(_3820_),
+ .B(_3827_),
+ .C_N(_3907_),
+ .X(_3908_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8279_ (.A(_3908_),
+ .B(_3578_),
+ .C(_3848_),
+ .X(_3909_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand3b_1 _8280_ (.A_N(_3905_),
+ .B(_3906_),
+ .C(_3909_),
+ .Y(_3910_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8281_ (.A(_3834_),
+ .B(_3910_),
+ .X(_3911_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8282_ (.A(_3731_),
+ .B(_3451_),
+ .C(_3389_),
+ .X(_3912_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8283_ (.A(_3911_),
+ .B(_3912_),
+ .X(_3913_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8284_ (.A(_3696_),
+ .B(_3913_),
+ .X(_3914_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8285_ (.A(_3833_),
+ .B(_3914_),
+ .X(_3915_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8286_ (.A(_3585_),
+ .B(_3832_),
+ .C(_3915_),
+ .X(_3916_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8287_ (.A(_3701_),
+ .B(_3916_),
+ .X(_3917_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8288_ (.A1(_3831_),
+ .A2(_3742_),
+ .A3(_3829_),
+ .B1(_3917_),
+ .X(_3918_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8289_ (.A1(_3731_),
+ .A2(_3829_),
+ .A3(_3831_),
+ .B1(_3918_),
+ .X(_3919_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8290_ (.A(_3818_),
+ .B(_3919_),
+ .X(_3920_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8291_ (.A(_3816_),
+ .B(_3817_),
+ .C(_3920_),
+ .X(_3921_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8292_ (.A(_3815_),
+ .B(_3921_),
+ .Y(_3922_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8293_ (.A1(_3830_),
+ .A2(_3823_),
+ .B1(\wbbd_state[8] ),
+ .Y(_3923_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8294_ (.A(_3922_),
+ .B(_3923_),
+ .X(_3924_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8295_ (.A(_3814_),
+ .B(_3924_),
+ .X(_3925_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8296_ (.A(_3717_),
+ .B(_3925_),
+ .Y(_0179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8297_ (.A(_3429_),
+ .B(_3818_),
+ .X(_3926_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8298_ (.A(_3469_),
+ .Y(_3927_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8299_ (.A(_3386_),
+ .B(_3492_),
+ .Y(_3928_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8300_ (.A(_3465_),
+ .B(_3928_),
+ .X(_3929_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 _8301_ (.A(_3929_),
+ .X(_3930_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8302_ (.A(_3930_),
+ .Y(_3931_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8303_ (.A(_3539_),
+ .Y(_3932_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8304_ (.A(_3932_),
+ .B(_3864_),
+ .Y(_3933_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8305_ (.A(_3476_),
+ .B(_3521_),
+ .X(_3934_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8306_ (.A1(_3481_),
+ .A2(_3515_),
+ .B1(_3934_),
+ .C1(_3845_),
+ .D1(_3513_),
+ .X(_3935_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8307_ (.A1(_3521_),
+ .A2(_3837_),
+ .B1(_3522_),
+ .Y(_3936_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8308_ (.A1(_3391_),
+ .A2(_3386_),
+ .A3(_3466_),
+ .B1(_3510_),
+ .X(_3937_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _8309_ (.A1(_3495_),
+ .A2(_3535_),
+ .B1(_3526_),
+ .B2(_3930_),
+ .X(_3938_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8310_ (.A(_3855_),
+ .B(_3936_),
+ .C(_3937_),
+ .D_N(_3938_),
+ .X(_3939_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8311_ (.A(_3738_),
+ .B(_3843_),
+ .X(_3940_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4bb_1 _8312_ (.A_N(_3939_),
+ .B_N(_3858_),
+ .C(_3940_),
+ .D(_3841_),
+ .X(_3941_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_2 _8313_ (.A1(_3465_),
+ .A2(_3935_),
+ .B1(_3506_),
+ .B2(_3930_),
+ .C1(_3941_),
+ .X(_3942_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8314_ (.A1(_3499_),
+ .A2(_3837_),
+ .B1(_3542_),
+ .X(_3943_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_1 _8315_ (.A1(_3504_),
+ .A2(_3930_),
+ .B1(_3933_),
+ .C1(_3942_),
+ .D1(_3943_),
+ .Y(_3944_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8316_ (.A(_3499_),
+ .B(_3930_),
+ .Y(_3945_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8317_ (.A(_3545_),
+ .B(_3877_),
+ .X(_3946_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8318_ (.A(_3944_),
+ .B(_3945_),
+ .C(_3946_),
+ .X(_3947_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8319_ (.A(_3497_),
+ .B(_3930_),
+ .Y(_3948_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8320_ (.A(_3550_),
+ .Y(_3949_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8321_ (.A(_3949_),
+ .B(_3886_),
+ .X(_3950_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2111o_2 _8322_ (.A1(_3493_),
+ .A2(_3931_),
+ .B1(_3947_),
+ .C1(_3948_),
+ .D1(_3950_),
+ .X(_3951_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8323_ (.A(_3490_),
+ .B(_3894_),
+ .X(_3952_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8324_ (.A(_3461_),
+ .B(_3930_),
+ .Y(_3953_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8325_ (.A(_3484_),
+ .Y(_3954_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8326_ (.A(_3954_),
+ .B(_3902_),
+ .X(_3955_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_2 _8327_ (.A(_3951_),
+ .B(_3952_),
+ .C(_3953_),
+ .D(_3955_),
+ .Y(_3956_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8328_ (.A1(_3473_),
+ .A2(_3928_),
+ .B1(_3956_),
+ .Y(_3957_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8329_ (.A(_3467_),
+ .B(_3927_),
+ .C(_3957_),
+ .X(_3958_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8330_ (.A(_3460_),
+ .B(_3912_),
+ .X(_3959_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8331_ (.A(_3958_),
+ .B(_3959_),
+ .X(_3960_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8332_ (.A1(_3386_),
+ .A2(_3389_),
+ .A3(_3451_),
+ .B1(_3960_),
+ .X(_3961_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8333_ (.A(_3724_),
+ .B(_3701_),
+ .C(_3961_),
+ .X(_3962_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _8334_ (.A1(_3442_),
+ .A2(_3395_),
+ .B1(_3385_),
+ .B2(_3442_),
+ .X(_3963_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _8335_ (.A(_3962_),
+ .B_N(_3963_),
+ .X(_3964_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8336_ (.A(_3926_),
+ .B(_3964_),
+ .X(_3965_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8337_ (.A(_3392_),
+ .B(_3817_),
+ .C(_3965_),
+ .X(_3966_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8338_ (.A(_3966_),
+ .X(_0180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8339_ (.A(_3429_),
+ .B(_3816_),
+ .X(_3967_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_1 _8340_ (.A_N(_3576_),
+ .B(_3829_),
+ .C(_3831_),
+ .D(_3393_),
+ .X(_3968_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8341_ (.A(_3444_),
+ .B(_3526_),
+ .C(_3465_),
+ .Y(_3969_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21o_1 _8342_ (.A1(_3744_),
+ .A2(_3745_),
+ .B1(_3969_),
+ .X(_3970_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8343_ (.A1(_3514_),
+ .A2(_3633_),
+ .B1(_3739_),
+ .Y(_3971_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o32a_2 _8344_ (.A1(_3908_),
+ .A2(_3578_),
+ .A3(_3738_),
+ .B1(_3848_),
+ .B2(_3843_),
+ .X(_3972_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8345_ (.A(_3820_),
+ .B(_3907_),
+ .X(_3973_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8346_ (.A(_3822_),
+ .B(_3824_),
+ .C_N(_3826_),
+ .X(_3974_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8347_ (.A(_3973_),
+ .B(_3974_),
+ .X(_3975_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8348_ (.A1(_3578_),
+ .A2(_3975_),
+ .B1(_3846_),
+ .X(_3976_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8349_ (.A(_3738_),
+ .B(_3976_),
+ .X(_3977_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_4 _8350_ (.A(_3404_),
+ .B(_3821_),
+ .C(_3974_),
+ .X(_3978_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8351_ (.A(_3738_),
+ .B(_3578_),
+ .C(_3978_),
+ .X(_3979_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3_1 _8352_ (.A(_3972_),
+ .B(_3977_),
+ .C(_3979_),
+ .X(_3980_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_4 _8353_ (.A1(_3584_),
+ .A2(_3630_),
+ .B1(_3971_),
+ .C1(_3853_),
+ .D1(_3980_),
+ .Y(_3981_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8354_ (.A(_3743_),
+ .B(_3835_),
+ .X(_3982_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8355_ (.A(_3756_),
+ .B(_3856_),
+ .X(_3983_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8356_ (.A(_3970_),
+ .B(_3981_),
+ .C(_3982_),
+ .D(_3983_),
+ .X(_3984_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8357_ (.A(_3759_),
+ .B(_3859_),
+ .X(_3985_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8358_ (.A(_3763_),
+ .B(_3863_),
+ .X(_3986_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8359_ (.A(_3765_),
+ .B(_3866_),
+ .X(_3987_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8360_ (.A(_3984_),
+ .B(_3985_),
+ .C(_3986_),
+ .D(_3987_),
+ .X(_3988_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8361_ (.A(_3768_),
+ .B(_3869_),
+ .X(_3989_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8362_ (.A(_3771_),
+ .B(_3873_),
+ .X(_3990_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8363_ (.A(_3773_),
+ .B(_3876_),
+ .X(_3991_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8364_ (.A(_3988_),
+ .B(_3989_),
+ .C(_3990_),
+ .D(_3991_),
+ .X(_3992_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8365_ (.A1(_3616_),
+ .A2(_3578_),
+ .B1(_3879_),
+ .Y(_3993_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8366_ (.A(_3779_),
+ .B(_3884_),
+ .X(_3994_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8367_ (.A(_3783_),
+ .B(_3888_),
+ .X(_3995_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8368_ (.A(_3992_),
+ .B(_3993_),
+ .C(_3994_),
+ .D(_3995_),
+ .X(_3996_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8369_ (.A(_3787_),
+ .B(_3892_),
+ .X(_3997_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8370_ (.A(_3791_),
+ .B(_3896_),
+ .X(_3998_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8371_ (.A(_3794_),
+ .B(_3900_),
+ .X(_3999_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8372_ (.A(_3996_),
+ .B(_3997_),
+ .C(_3998_),
+ .D(_3999_),
+ .X(_4000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8373_ (.A(_3799_),
+ .B(_3904_),
+ .X(_4001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8374_ (.A1(_3823_),
+ .A2(_3848_),
+ .B1(_3909_),
+ .Y(_4002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8375_ (.A(_4000_),
+ .B(_4001_),
+ .C(_3834_),
+ .D(_4002_),
+ .X(_4003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8376_ (.A(_3460_),
+ .B(_3696_),
+ .X(_4004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8377_ (.A(_3827_),
+ .B(_3973_),
+ .C(_3830_),
+ .X(_4005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8378_ (.A(_4005_),
+ .B(_3578_),
+ .Y(_4006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and4b_1 _8379_ (.A_N(_3442_),
+ .B(net153),
+ .C(_3430_),
+ .D(net156),
+ .X(_4007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8380_ (.A(_4003_),
+ .B(_4004_),
+ .C(_4006_),
+ .D(_4007_),
+ .X(_4008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8381_ (.A(_3968_),
+ .B(_4008_),
+ .X(_4009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8382_ (.A(_3967_),
+ .B(_4009_),
+ .X(_4010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8383_ (.A(_3392_),
+ .B(_3815_),
+ .X(_4011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8384_ (.A(_4010_),
+ .B(_4011_),
+ .Y(_4012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8385_ (.A(_3923_),
+ .B(_4012_),
+ .X(_4013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8386_ (.A(_3720_),
+ .B(_3618_),
+ .X(_4014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8387_ (.A(_3605_),
+ .B(_4014_),
+ .Y(_4015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8388_ (.A1(_3727_),
+ .A2(_3750_),
+ .B1(_3801_),
+ .Y(_4016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8389_ (.A(_3605_),
+ .Y(_4017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8390_ (.A(_4017_),
+ .B(_3742_),
+ .X(_4018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _8391_ (.A(_4018_),
+ .Y(_4019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8392_ (.A(_3682_),
+ .Y(_4020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8393_ (.A(_3747_),
+ .Y(_4021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8394_ (.A(_3393_),
+ .B(_3383_),
+ .C(net142),
+ .D(_3390_),
+ .X(_4022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8395_ (.A(_3465_),
+ .B(_4022_),
+ .X(_4023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8396_ (.A(_3800_),
+ .Y(_4024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8397_ (.A(_3513_),
+ .B(_3750_),
+ .Y(_4025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8398_ (.A1(_4024_),
+ .A2(_4025_),
+ .B1(_3751_),
+ .Y(_4026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8399_ (.A1(_3730_),
+ .A2(_3746_),
+ .B1(_4023_),
+ .C1(_4026_),
+ .X(_4027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8400_ (.A1(_3437_),
+ .A2(_3630_),
+ .B1(_4021_),
+ .B2(_4019_),
+ .C1(_4027_),
+ .X(_4028_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8401_ (.A(_3628_),
+ .B(_4019_),
+ .X(_4029_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8402_ (.A1(_3730_),
+ .A2(_3630_),
+ .B1(_3647_),
+ .C1(_4028_),
+ .D1(_4029_),
+ .X(_4030_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8403_ (.A(_3651_),
+ .Y(_4031_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8404_ (.A(_4031_),
+ .B(_3755_),
+ .X(_4032_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8405_ (.A(_4032_),
+ .Y(_4033_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8406_ (.A1(_3626_),
+ .A2(_4019_),
+ .B1(_4030_),
+ .C1(_4033_),
+ .X(_4034_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8407_ (.A(_3654_),
+ .Y(_4035_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8408_ (.A(_4035_),
+ .B(_3760_),
+ .Y(_4036_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8409_ (.A1(_3623_),
+ .A2(_4019_),
+ .B1(_4034_),
+ .C1(_4036_),
+ .X(_4037_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8410_ (.A(_3658_),
+ .Y(_4038_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8411_ (.A(_4038_),
+ .B(_3767_),
+ .Y(_4039_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8412_ (.A1(_3621_),
+ .A2(_4019_),
+ .B1(_4037_),
+ .C1(_4039_),
+ .X(_4040_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8413_ (.A(_3662_),
+ .B(_3772_),
+ .X(_4041_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8414_ (.A(_4041_),
+ .Y(_4042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8415_ (.A1(_3616_),
+ .A2(_4019_),
+ .B1(_4040_),
+ .C1(_4042_),
+ .X(_4043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8416_ (.A(_3668_),
+ .Y(_4044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8417_ (.A(_4044_),
+ .B(_3777_),
+ .X(_4045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8418_ (.A(_4045_),
+ .Y(_4046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8419_ (.A1(_3612_),
+ .A2(_4019_),
+ .B1(_4043_),
+ .C1(_4046_),
+ .X(_4047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8420_ (.A(_3674_),
+ .B(_3785_),
+ .X(_4048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8421_ (.A(_4048_),
+ .Y(_4049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8422_ (.A1(_3603_),
+ .A2(_4019_),
+ .B1(_4047_),
+ .C1(_4049_),
+ .X(_4050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8423_ (.A(_4020_),
+ .B(_3740_),
+ .C_N(_4050_),
+ .X(_4051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21bai_1 _8424_ (.A1(_3681_),
+ .A2(_4019_),
+ .B1_N(_4051_),
+ .Y(_4052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8425_ (.A(_3728_),
+ .B(_4016_),
+ .C(_4052_),
+ .X(_4053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8426_ (.A(_3458_),
+ .B(_3696_),
+ .X(_4054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8427_ (.A(_4053_),
+ .B(_4054_),
+ .X(_4055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8428_ (.A(_4015_),
+ .B(_4055_),
+ .X(_4056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8429_ (.A(_3453_),
+ .B(_3585_),
+ .X(_4057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8430_ (.A(_4056_),
+ .B(_4057_),
+ .X(_4058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8431_ (.A(_3723_),
+ .B(_4058_),
+ .X(_4059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8432_ (.A(_3434_),
+ .B(_3816_),
+ .C(_4059_),
+ .X(_4060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8433_ (.A(_3815_),
+ .B(_3718_),
+ .X(_4061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8434_ (.A(_4060_),
+ .B(_4061_),
+ .Y(_4062_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8435_ (.A(_3813_),
+ .B(_4062_),
+ .X(_4063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8436_ (.A(_4013_),
+ .B(_4063_),
+ .Y(_4064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8437_ (.A(_3435_),
+ .B(_3582_),
+ .Y(_4065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8438_ (.A(_3456_),
+ .B(_3481_),
+ .Y(_4066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8439_ (.A1(_3693_),
+ .A2(_3689_),
+ .A3(_3690_),
+ .B1(_3691_),
+ .X(_4067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2bb2o_1 _8440_ (.A1_N(_3495_),
+ .A2_N(_3506_),
+ .B1(_3613_),
+ .B2(_3745_),
+ .X(_4068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8441_ (.A(_3522_),
+ .B(_3648_),
+ .Y(_4069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8442_ (.A1(_3519_),
+ .A2(_3535_),
+ .B1(_3433_),
+ .B2(_3642_),
+ .Y(_4070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8443_ (.A1(_3532_),
+ .A2(_3433_),
+ .B1(_3527_),
+ .Y(_4071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8444_ (.A(_4070_),
+ .B(_4071_),
+ .X(_4072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311o_1 _8445_ (.A1(_3452_),
+ .A2(_3481_),
+ .A3(_3584_),
+ .B1(_3529_),
+ .C1(_3426_),
+ .X(_4073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_2 _8446_ (.A1(_3495_),
+ .A2(_3526_),
+ .B1(_3639_),
+ .C1(_4073_),
+ .D1(_3643_),
+ .Y(_4074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8447_ (.A(_3465_),
+ .B(_3934_),
+ .X(_4075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8448_ (.A(_3631_),
+ .B(_4072_),
+ .C(_4074_),
+ .D_N(_4075_),
+ .X(_4076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8449_ (.A(_4069_),
+ .B(_4076_),
+ .X(_4077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8450_ (.A(_3652_),
+ .Y(_4078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8451_ (.A(_3932_),
+ .B(_4078_),
+ .X(_4079_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8452_ (.A1(_3504_),
+ .A2(_3495_),
+ .B1(_3446_),
+ .B2(_3626_),
+ .Y(_4080_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8453_ (.A(_4068_),
+ .B(_4077_),
+ .C(_4079_),
+ .D(_4080_),
+ .X(_4081_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8454_ (.A(_3542_),
+ .B(_3655_),
+ .Y(_4082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8455_ (.A(_4081_),
+ .B(_4082_),
+ .X(_4083_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8456_ (.A1(_3495_),
+ .A2(_3499_),
+ .B1(_3446_),
+ .B2(_3623_),
+ .Y(_4084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8457_ (.A1(_3481_),
+ .A2(_3501_),
+ .B1(_3659_),
+ .Y(_4085_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8458_ (.A1(_3495_),
+ .A2(_3497_),
+ .B1(_3446_),
+ .B2(_3621_),
+ .Y(_4086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8459_ (.A(_4083_),
+ .B(_4084_),
+ .C(_4085_),
+ .D(_4086_),
+ .X(_4087_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8460_ (.A(_3664_),
+ .Y(_4088_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8461_ (.A(_3949_),
+ .B(_4088_),
+ .X(_4089_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a32o_1 _8462_ (.A1(_3466_),
+ .A2(_3492_),
+ .A3(_3493_),
+ .B1(_3613_),
+ .B2(_3617_),
+ .X(_4090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8463_ (.A(_3490_),
+ .B(_3670_),
+ .X(_4091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8464_ (.A(_4087_),
+ .B(_4089_),
+ .C(_4090_),
+ .D(_4091_),
+ .X(_4092_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8465_ (.A1(_3476_),
+ .A2(_3483_),
+ .B1(_3446_),
+ .B2(_3612_),
+ .Y(_4093_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8466_ (.A(_4092_),
+ .B(_4093_),
+ .X(_4094_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8467_ (.A(_3676_),
+ .Y(_4095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8468_ (.A(_3954_),
+ .B(_4095_),
+ .X(_4096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_1 _8469_ (.A1(_3473_),
+ .A2(_3476_),
+ .B1(_3446_),
+ .B2(_3603_),
+ .Y(_4097_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8470_ (.A(_4094_),
+ .B(_4096_),
+ .C(_4097_),
+ .X(_4098_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _8471_ (.A(_3421_),
+ .Y(_4099_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_2 _8472_ (.A(_3530_),
+ .Y(_4100_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8473_ (.A1(_4099_),
+ .A2(_4100_),
+ .A3(_3688_),
+ .B1(_3684_),
+ .X(_4101_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8474_ (.A(_4098_),
+ .B(_4101_),
+ .X(_4102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8475_ (.A(_3694_),
+ .B(_4067_),
+ .C(_4102_),
+ .X(_4103_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8476_ (.A(_3458_),
+ .B(_3833_),
+ .X(_4104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8477_ (.A(_4103_),
+ .B(_4104_),
+ .X(_4105_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8478_ (.A(_4066_),
+ .B(_4105_),
+ .X(_4106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8479_ (.A(_4065_),
+ .B(_4106_),
+ .X(_4107_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_4 _8480_ (.A1(_3472_),
+ .A2(_3582_),
+ .B1(_3481_),
+ .B2(_3582_),
+ .Y(_4108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8481_ (.A(_4107_),
+ .B(_4108_),
+ .X(_4109_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8482_ (.A(_3434_),
+ .B(_3817_),
+ .X(_4110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8483_ (.A(_4109_),
+ .B(_4110_),
+ .X(_4111_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8484_ (.A1(_3428_),
+ .A2(_3605_),
+ .B1(_3715_),
+ .Y(_4112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8485_ (.A(_4111_),
+ .B(_4112_),
+ .X(_4113_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _8486_ (.A(_3575_),
+ .B_N(_4113_),
+ .X(_4114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _8487_ (.A(_4064_),
+ .B_N(_4114_),
+ .X(_4115_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8488_ (.A(_4115_),
+ .X(_0181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8489_ (.A(_3724_),
+ .B(_3701_),
+ .C(_3453_),
+ .X(_4116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8490_ (.A(_3502_),
+ .B(_3876_),
+ .C(_3945_),
+ .X(_4117_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _8491_ (.A1(_3493_),
+ .A2(_3931_),
+ .B1(_3491_),
+ .C1(_3892_),
+ .X(_4118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8492_ (.A(_3549_),
+ .Y(_4119_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8493_ (.A(_4119_),
+ .B(_3884_),
+ .C(_3948_),
+ .X(_4120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311oi_2 _8494_ (.A1(_3472_),
+ .A2(_3476_),
+ .A3(_3385_),
+ .B1(_3465_),
+ .C1(_3526_),
+ .Y(_4121_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _8495_ (.A1(_3444_),
+ .A2(_3535_),
+ .B1(_3396_),
+ .B2(_3516_),
+ .X(_4122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8496_ (.A(_3465_),
+ .B(_4122_),
+ .Y(_4123_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2b_1 _8497_ (.A(_3937_),
+ .B_N(_4023_),
+ .X(_4124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8498_ (.A(_3535_),
+ .B(_3930_),
+ .Y(_4125_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8499_ (.A(_3855_),
+ .B(_3856_),
+ .X(_4126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8500_ (.A(_4125_),
+ .B(_4126_),
+ .C(_3969_),
+ .D_N(_3523_),
+ .X(_4127_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8501_ (.A(_4121_),
+ .B(_4123_),
+ .C(_4124_),
+ .D(_4127_),
+ .X(_4128_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8502_ (.A1(_3506_),
+ .A2(_3930_),
+ .B1(_3508_),
+ .C1(_3862_),
+ .X(_4129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8503_ (.A1(_3444_),
+ .A2(_3505_),
+ .B1(_3504_),
+ .B2(_3930_),
+ .C1(_3541_),
+ .X(_4130_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and3b_1 _8504_ (.A_N(_4128_),
+ .B(_4129_),
+ .C(_4130_),
+ .X(_4131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_4 _8505_ (.A(_4117_),
+ .B(_4118_),
+ .C(_4120_),
+ .D_N(_4131_),
+ .X(_4132_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8506_ (.A(_3485_),
+ .B(_3900_),
+ .C(_3953_),
+ .X(_4133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_2 _8507_ (.A1(_3468_),
+ .A2(_3511_),
+ .B1(_3473_),
+ .B2(_3928_),
+ .C1(_3474_),
+ .Y(_4134_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a41o_1 _8508_ (.A1(_3389_),
+ .A2(_3462_),
+ .A3(_3393_),
+ .A4(_3397_),
+ .B1(_3959_),
+ .X(_4135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8509_ (.A(_4132_),
+ .B(_4133_),
+ .C(_4134_),
+ .D(_4135_),
+ .X(_4136_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8510_ (.A(_3395_),
+ .B(_3450_),
+ .C(_3388_),
+ .Y(_4137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _8511_ (.A1(_3389_),
+ .A2(_3635_),
+ .B1(_3439_),
+ .C1(_3926_),
+ .X(_4138_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8512_ (.A(_4116_),
+ .B(_4136_),
+ .C(_4137_),
+ .D(_4138_),
+ .X(_4139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8513_ (.A(_4139_),
+ .X(_0182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8514_ (.A(_3815_),
+ .B(_3575_),
+ .C(_4112_),
+ .X(_4140_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8515_ (.A(_3456_),
+ .B(_3472_),
+ .Y(_4141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_4 _8516_ (.A(_3529_),
+ .B(_3425_),
+ .Y(_4142_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8517_ (.A(_3531_),
+ .Y(_4143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_4 _8518_ (.A(_3693_),
+ .B(_4017_),
+ .X(_4144_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8519_ (.A1(_4142_),
+ .A2(_4143_),
+ .A3(_4144_),
+ .B1(_4079_),
+ .X(_4145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8520_ (.A1(_4100_),
+ .A2(_4143_),
+ .A3(_4144_),
+ .B1(_4071_),
+ .X(_4146_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nand2_1 _8521_ (.A(_3437_),
+ .B(_3481_),
+ .Y(_4147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8522_ (.A1(_3636_),
+ .A2(_3689_),
+ .A3(_4147_),
+ .B1(_3640_),
+ .X(_4148_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8523_ (.A(_3641_),
+ .Y(_4149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8524_ (.A1(_4149_),
+ .A2(_4143_),
+ .A3(_4144_),
+ .B1(_4070_),
+ .X(_4150_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_4 _8525_ (.A(net158),
+ .B(_3424_),
+ .C(_3529_),
+ .Y(_4151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8526_ (.A1(_4151_),
+ .A2(_4143_),
+ .A3(_4144_),
+ .B1(_4069_),
+ .X(_4152_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8527_ (.A(_4146_),
+ .B(_4148_),
+ .C(_4150_),
+ .D(_4152_),
+ .X(_4153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_4 _8528_ (.A(net160),
+ .B(_3419_),
+ .Y(_4154_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8529_ (.A1(_4149_),
+ .A2(_4154_),
+ .A3(_4144_),
+ .B1(_4082_),
+ .X(_4155_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8530_ (.A1(_4100_),
+ .A2(_4154_),
+ .A3(_4144_),
+ .B1(_4085_),
+ .X(_4156_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8531_ (.A(_4145_),
+ .B(_4153_),
+ .C(_4155_),
+ .D(_4156_),
+ .X(_4157_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8532_ (.A1(_4154_),
+ .A2(_4151_),
+ .A3(_4144_),
+ .B1(_4089_),
+ .X(_4158_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8533_ (.A1(_4142_),
+ .A2(_4154_),
+ .A3(_4144_),
+ .B1(_4091_),
+ .X(_4159_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8534_ (.A1(_4099_),
+ .A2(_4149_),
+ .A3(_4144_),
+ .B1(_4096_),
+ .X(_4160_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8535_ (.A(_4157_),
+ .B(_4158_),
+ .C(_4159_),
+ .D(_4160_),
+ .X(_4161_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8536_ (.A(_3686_),
+ .Y(_4162_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311o_1 _8537_ (.A1(_3391_),
+ .A2(_3492_),
+ .A3(_3690_),
+ .B1(_4162_),
+ .C1(_4101_),
+ .X(_4163_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8538_ (.A(_3404_),
+ .B(_3424_),
+ .C(_3421_),
+ .D(_3714_),
+ .X(_4164_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_2 _8539_ (.A(_3696_),
+ .B(_4104_),
+ .C_N(_4164_),
+ .X(_4165_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8540_ (.A(_3702_),
+ .B(_4065_),
+ .X(_4166_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_1 _8541_ (.A(_4161_),
+ .B(_4163_),
+ .C(_4165_),
+ .D(_4166_),
+ .Y(_4167_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8542_ (.A(_4141_),
+ .B(_4110_),
+ .C(_3967_),
+ .D_N(_4167_),
+ .X(_4168_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8543_ (.A(_4168_),
+ .Y(_4169_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8544_ (.A(_3613_),
+ .B(_3741_),
+ .C(_4018_),
+ .X(_4170_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkinv_4 _8545_ (.A(_4170_),
+ .Y(_4171_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8546_ (.A(_3749_),
+ .B(_3635_),
+ .Y(_4172_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8547_ (.A1(_3600_),
+ .A2(_4172_),
+ .B1(_4026_),
+ .X(_4173_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8548_ (.A1(_4021_),
+ .A2(_4171_),
+ .B1(_3628_),
+ .B2(_4171_),
+ .C1(_4173_),
+ .X(_4174_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_1 _8549_ (.A1(_3626_),
+ .A2(_4171_),
+ .B1(_3623_),
+ .B2(_4171_),
+ .C1(_4174_),
+ .Y(_4175_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8550_ (.A(_3621_),
+ .B(_4171_),
+ .Y(_4176_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8551_ (.A(_3616_),
+ .B(_4171_),
+ .Y(_4177_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8552_ (.A(_3612_),
+ .B(_4171_),
+ .Y(_4178_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8553_ (.A(_4175_),
+ .B(_4176_),
+ .C(_4177_),
+ .D(_4178_),
+ .X(_4179_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8554_ (.A(_3603_),
+ .B(_4171_),
+ .Y(_4180_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_1 _8555_ (.A1(_3438_),
+ .A2(_3750_),
+ .B1(_3681_),
+ .B2(_4019_),
+ .C1(_3798_),
+ .Y(_4181_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8556_ (.A(_4054_),
+ .Y(_4182_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8557_ (.A1(_3720_),
+ .A2(_3595_),
+ .A3(_3605_),
+ .B1(_3459_),
+ .C1(_4182_),
+ .X(_4183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8558_ (.A(_4183_),
+ .Y(_4184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8559_ (.A(_4179_),
+ .B(_4180_),
+ .C(_4181_),
+ .D(_4184_),
+ .X(_4185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_2 _8560_ (.A(_3725_),
+ .B(_4057_),
+ .X(_4186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8561_ (.A(_3433_),
+ .B(_4014_),
+ .Y(_4187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8562_ (.A(_3434_),
+ .B(_3816_),
+ .C(_3926_),
+ .X(_4188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8563_ (.A(_4185_),
+ .B(_4186_),
+ .C(_4187_),
+ .D(_4188_),
+ .X(_4189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8564_ (.A(_3392_),
+ .B(_3813_),
+ .C(_4061_),
+ .D_N(_4189_),
+ .X(_4190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8565_ (.A(_4005_),
+ .B(_3710_),
+ .Y(_4191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8566_ (.A(_3512_),
+ .B(_3635_),
+ .Y(_4192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8567_ (.A1(_3738_),
+ .A2(_4192_),
+ .B1(_3972_),
+ .Y(_4193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8568_ (.A1(_3730_),
+ .A2(_3978_),
+ .B1(_3845_),
+ .X(_4194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_4 _8569_ (.A1(_3738_),
+ .A2(_4194_),
+ .B1(_3851_),
+ .C1(_3979_),
+ .Y(_4195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_4 _8570_ (.A1(_3730_),
+ .A2(_3630_),
+ .B1(_3526_),
+ .B2(_3840_),
+ .C1(_3977_),
+ .Y(_4196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8571_ (.A(_3755_),
+ .B(_3855_),
+ .C(_3982_),
+ .X(_4197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8572_ (.A(_4193_),
+ .B(_4195_),
+ .C(_4196_),
+ .D(_4197_),
+ .X(_4198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8573_ (.A(_3760_),
+ .B(_3860_),
+ .C(_3985_),
+ .X(_4199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8574_ (.A(_3767_),
+ .B(_3868_),
+ .C(_3987_),
+ .X(_4200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8575_ (.A(_3772_),
+ .B(_3874_),
+ .C(_3990_),
+ .X(_4201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8576_ (.A(_4198_),
+ .B(_4199_),
+ .C(_4200_),
+ .D(_4201_),
+ .X(_4202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8577_ (.A(_3777_),
+ .B(_3882_),
+ .C(_3993_),
+ .X(_4203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8578_ (.A(_3785_),
+ .B(_3890_),
+ .C(_3995_),
+ .X(_4204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8579_ (.A(_3740_),
+ .B(_3898_),
+ .C(_3998_),
+ .X(_4205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8580_ (.A(_4202_),
+ .B(_4203_),
+ .C(_4204_),
+ .D(_4205_),
+ .X(_4206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8581_ (.A1(_3634_),
+ .A2(_3848_),
+ .B1(_3906_),
+ .Y(_4207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8582_ (.A(_4001_),
+ .B(_4207_),
+ .X(_4208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8583_ (.A(_3404_),
+ .B(_3821_),
+ .C(_3827_),
+ .Y(_4209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a311o_1 _8584_ (.A1(_3831_),
+ .A2(_3741_),
+ .A3(_4209_),
+ .B1(_3912_),
+ .C1(_4004_),
+ .X(_4210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8585_ (.A(_4007_),
+ .B(_3585_),
+ .X(_4211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8586_ (.A(_4206_),
+ .B(_4208_),
+ .C(_4210_),
+ .D(_4211_),
+ .X(_4212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8587_ (.A(_3439_),
+ .B(_3818_),
+ .X(_4213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8588_ (.A(_4191_),
+ .B(_4212_),
+ .C(_3967_),
+ .D(_4213_),
+ .X(_4214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8589_ (.A(_3817_),
+ .B(_3923_),
+ .C(_4011_),
+ .D_N(_4214_),
+ .X(_4215_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_1 _8590_ (.A1(_4140_),
+ .A2(_4169_),
+ .B1(_4190_),
+ .C1(_4215_),
+ .Y(_0183_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_1 _8591_ (.A1(_3395_),
+ .A2(_3535_),
+ .B1(_3509_),
+ .C1(_3513_),
+ .Y(_4216_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8592_ (.A(_3940_),
+ .Y(_4217_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _8593_ (.A1(_3466_),
+ .A2(_4216_),
+ .B1(_4217_),
+ .C1(_4124_),
+ .X(_4218_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8594_ (.A(_4121_),
+ .B(_3969_),
+ .C_N(_3527_),
+ .X(_4219_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8595_ (.A(_4219_),
+ .B(_3835_),
+ .C(_3838_),
+ .D_N(_3533_),
+ .X(_4220_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_4 _8596_ (.A1(_3478_),
+ .A2(_3505_),
+ .B1(_3865_),
+ .C1(_3933_),
+ .D1(_4129_),
+ .Y(_4221_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8597_ (.A(_3547_),
+ .B(_3880_),
+ .C(_3946_),
+ .D(_4117_),
+ .X(_4222_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8598_ (.A(_4218_),
+ .B(_4220_),
+ .C(_4221_),
+ .D(_4222_),
+ .X(_4223_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8599_ (.A(_3486_),
+ .B(_3896_),
+ .C(_3952_),
+ .D(_4118_),
+ .X(_4224_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8600_ (.A(_3927_),
+ .B(_4134_),
+ .X(_4225_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8601_ (.A(_4223_),
+ .B(_4224_),
+ .C(_4225_),
+ .D(_4054_),
+ .X(_4226_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_1 _8602_ (.A1(_3442_),
+ .A2(_3444_),
+ .B1(_3388_),
+ .B2(_3511_),
+ .C1(_3963_),
+ .Y(_4227_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8603_ (.A(_4116_),
+ .B(_4226_),
+ .C(_4137_),
+ .D(_4227_),
+ .X(_4228_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8604_ (.A(_4228_),
+ .X(_0184_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8605_ (.A(_4110_),
+ .B(_4140_),
+ .X(_4229_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8606_ (.A(_3707_),
+ .B(_3818_),
+ .X(_4230_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8607_ (.A(_4145_),
+ .B(_4035_),
+ .C(_4080_),
+ .D_N(_3541_),
+ .X(_4231_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8608_ (.A1(_3465_),
+ .A2(_3472_),
+ .A3(_3521_),
+ .B1(_3647_),
+ .C1(_4075_),
+ .X(_4232_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8609_ (.A(_4232_),
+ .Y(_4233_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8610_ (.A1(_3396_),
+ .A2(_3516_),
+ .B1(_3511_),
+ .Y(_4234_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _8611_ (.A1(_3636_),
+ .A2(_4234_),
+ .B1(_3637_),
+ .C1(_4148_),
+ .X(_4235_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8612_ (.A(_3631_),
+ .B(_4146_),
+ .X(_4236_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8613_ (.A(_4233_),
+ .B(_4235_),
+ .C(_4236_),
+ .X(_4237_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8614_ (.A(_4119_),
+ .B(_3662_),
+ .C(_4086_),
+ .D(_4156_),
+ .X(_4238_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8615_ (.A(_3485_),
+ .B(_3674_),
+ .C(_4093_),
+ .D(_4159_),
+ .X(_4239_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8616_ (.A(_4231_),
+ .B(_4237_),
+ .C(_4238_),
+ .D(_4239_),
+ .X(_4240_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8617_ (.A(_4067_),
+ .B(_4163_),
+ .X(_4241_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_2 _8618_ (.A1(_3456_),
+ .A2(_3476_),
+ .B1(_3437_),
+ .B2(_3456_),
+ .Y(_4242_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8619_ (.A(_4240_),
+ .B(_4241_),
+ .C(_4242_),
+ .D(_4166_),
+ .X(_4243_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_1 _8620_ (.A(_4108_),
+ .B(_4230_),
+ .C(_4141_),
+ .D(_4243_),
+ .Y(_4244_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8621_ (.A(_4186_),
+ .Y(_4245_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8622_ (.A1(_3595_),
+ .A2(_3624_),
+ .A3(_3433_),
+ .B1(_3513_),
+ .C1(_4022_),
+ .X(_4246_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_2 _8623_ (.A1(_3600_),
+ .A2(_4246_),
+ .B1(_4173_),
+ .Y(_4247_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8624_ (.A(_3435_),
+ .B(_3433_),
+ .X(_4248_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8625_ (.A(_3731_),
+ .B(_4170_),
+ .Y(_4249_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22ai_2 _8626_ (.A1(_3628_),
+ .A2(_4248_),
+ .B1(_3630_),
+ .B2(_4249_),
+ .Y(_4250_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8627_ (.A(_4088_),
+ .B(_3773_),
+ .C(_4041_),
+ .D(_4176_),
+ .X(_4251_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111a_1 _8628_ (.A1(_3626_),
+ .A2(_4171_),
+ .B1(_3655_),
+ .C1(_3762_),
+ .D1(_4036_),
+ .X(_4252_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8629_ (.A(_4247_),
+ .B(_4250_),
+ .C(_4251_),
+ .D_N(_4252_),
+ .X(_4253_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8630_ (.A(_4095_),
+ .B(_3787_),
+ .C(_4048_),
+ .D(_4178_),
+ .X(_4254_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8631_ (.A(_4016_),
+ .B(_4181_),
+ .X(_4255_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8632_ (.A(_3435_),
+ .B(_4014_),
+ .Y(_4256_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_1 _8633_ (.A(_4253_),
+ .B(_4254_),
+ .C(_4255_),
+ .D(_4256_),
+ .Y(_4257_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a211o_1 _8634_ (.A1(_3613_),
+ .A2(_3722_),
+ .B1(_3439_),
+ .C1(_3723_),
+ .X(_4258_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8635_ (.A(_4187_),
+ .B(_4258_),
+ .Y(_4259_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8636_ (.A(_3392_),
+ .B(_3813_),
+ .C(_4061_),
+ .D(_4188_),
+ .X(_4260_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8637_ (.A1(_4245_),
+ .A2(_4257_),
+ .A3(_4259_),
+ .B1(_4260_),
+ .X(_4261_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8638_ (.A(_4211_),
+ .Y(_4262_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2111o_1 _8639_ (.A1(_3745_),
+ .A2(_3742_),
+ .B1(_3838_),
+ .C1(_3970_),
+ .D1(_4196_),
+ .X(_4263_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8640_ (.A(_3738_),
+ .B(_3710_),
+ .C(_3978_),
+ .Y(_4264_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8641_ (.A(_4217_),
+ .B(_4193_),
+ .C(_4264_),
+ .D_N(_3971_),
+ .X(_4265_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8642_ (.A(_3764_),
+ .B(_3864_),
+ .C(_3986_),
+ .D(_4199_),
+ .X(_4266_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2111o_2 _8643_ (.A1(_3617_),
+ .A2(_3742_),
+ .B1(_3877_),
+ .C1(_3991_),
+ .D1(_4201_),
+ .X(_4267_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8644_ (.A(_4263_),
+ .B(_4265_),
+ .C(_4266_),
+ .D(_4267_),
+ .X(_4268_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8645_ (.A(_3789_),
+ .B(_3894_),
+ .C(_3997_),
+ .D(_4204_),
+ .X(_4269_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8646_ (.A(_4002_),
+ .B(_4208_),
+ .X(_4270_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_1 _8647_ (.A(_4268_),
+ .B(_4269_),
+ .C(_4270_),
+ .D(_4104_),
+ .Y(_4271_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21a_1 _8648_ (.A1(_3635_),
+ .A2(_3844_),
+ .B1(_3831_),
+ .X(_4272_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_1 _8649_ (.A(_3968_),
+ .B(_4272_),
+ .C(_4191_),
+ .Y(_4273_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8650_ (.A(_3816_),
+ .B(_3817_),
+ .C(_3923_),
+ .X(_4274_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8651_ (.A(_3429_),
+ .B(_4011_),
+ .X(_4275_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8652_ (.A(_4213_),
+ .B(_4274_),
+ .C(_4275_),
+ .X(_4276_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8653_ (.A1(_4262_),
+ .A2(_4271_),
+ .A3(_4273_),
+ .B1(_4276_),
+ .X(_4277_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8654_ (.A1(_3967_),
+ .A2(_4229_),
+ .A3(_4244_),
+ .B1(_4261_),
+ .C1(_4277_),
+ .X(_4278_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8655_ (.A(_4278_),
+ .Y(_0185_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8656_ (.A1(_3466_),
+ .A2(_3493_),
+ .A3(_3693_),
+ .B1(_3888_),
+ .X(_4279_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8657_ (.A(_3950_),
+ .B(_4279_),
+ .C(_4120_),
+ .D(_4222_),
+ .X(_4280_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8658_ (.A(_3858_),
+ .B(_3859_),
+ .X(_4281_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8659_ (.A(_4126_),
+ .B(_4281_),
+ .C(_4220_),
+ .D_N(_3524_),
+ .X(_4282_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8660_ (.A(_3385_),
+ .B(_3450_),
+ .C(_3388_),
+ .X(_4283_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8661_ (.A1(_3388_),
+ .A2(_3444_),
+ .A3(_3450_),
+ .B1(_4283_),
+ .C1(_4182_),
+ .X(_4284_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_2 _8662_ (.A(_3467_),
+ .B(_4135_),
+ .C(_4225_),
+ .D_N(_4284_),
+ .X(_4285_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8663_ (.A(_4280_),
+ .B(_4282_),
+ .C(_4285_),
+ .D(_3832_),
+ .X(_4286_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8664_ (.A(_4286_),
+ .X(_0186_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8665_ (.A(_4068_),
+ .B(_4031_),
+ .C_N(_3508_),
+ .X(_4287_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8666_ (.A(_4152_),
+ .B(_4287_),
+ .C(_4233_),
+ .D(_4236_),
+ .X(_4288_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8667_ (.A(_3491_),
+ .B(_4044_),
+ .X(_4289_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8668_ (.A(_4090_),
+ .B(_4289_),
+ .C(_4158_),
+ .D(_4238_),
+ .X(_4290_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8669_ (.A(_3701_),
+ .B(_4066_),
+ .C(_4242_),
+ .X(_4291_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8670_ (.A(_3694_),
+ .B(_4165_),
+ .C(_4291_),
+ .D(_4241_),
+ .X(_4292_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_2 _8671_ (.A(_4288_),
+ .B(_4290_),
+ .C(_4292_),
+ .D(_3453_),
+ .Y(_4293_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8672_ (.A(_4141_),
+ .B(_3707_),
+ .C(_3816_),
+ .X(_4294_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8673_ (.A(_3926_),
+ .B(_4108_),
+ .C(_4294_),
+ .D(_4229_),
+ .X(_4295_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8674_ (.A(_3781_),
+ .B(_3886_),
+ .X(_4296_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8675_ (.A(_3994_),
+ .B(_4296_),
+ .C(_4203_),
+ .D(_4267_),
+ .X(_4297_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8676_ (.A(_3758_),
+ .B(_3858_),
+ .X(_4298_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8677_ (.A(_3983_),
+ .B(_4298_),
+ .C(_4197_),
+ .D(_4263_),
+ .X(_4299_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8678_ (.A(_3834_),
+ .B(_4210_),
+ .C(_4270_),
+ .X(_4300_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8679_ (.A(_3832_),
+ .B(_4006_),
+ .C(_4104_),
+ .D(_4300_),
+ .X(_4301_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor4_2 _8680_ (.A(_4297_),
+ .B(_4299_),
+ .C(_4301_),
+ .D(_3724_),
+ .Y(_4302_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8681_ (.A(_4213_),
+ .B(_4272_),
+ .C(_4275_),
+ .X(_4303_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_4 _8682_ (.A(_4191_),
+ .B(_3968_),
+ .C(_4274_),
+ .D(_4303_),
+ .X(_4304_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8683_ (.A(_4078_),
+ .B(_3756_),
+ .X(_4305_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2111o_2 _8684_ (.A1(_3745_),
+ .A2(_4170_),
+ .B1(_4032_),
+ .C1(_4305_),
+ .D1(_4250_),
+ .X(_4306_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8685_ (.A(_3670_),
+ .B(_3779_),
+ .X(_4307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8686_ (.A(_4045_),
+ .B(_4307_),
+ .C(_4177_),
+ .D(_4251_),
+ .X(_4308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8687_ (.A(_3724_),
+ .B(_4015_),
+ .C(_4256_),
+ .X(_4309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8688_ (.A(_3728_),
+ .B(_4184_),
+ .C(_4255_),
+ .X(_4310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8689_ (.A(_4306_),
+ .B(_4308_),
+ .C(_4309_),
+ .D(_4310_),
+ .X(_4311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8690_ (.A(_4260_),
+ .Y(_4312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_2 _8691_ (.A1(_3701_),
+ .A2(_4311_),
+ .B1(_4259_),
+ .C1(_4312_),
+ .Y(_4313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_4 _8692_ (.A1(_4293_),
+ .A2(_4295_),
+ .B1(_4302_),
+ .B2(_4304_),
+ .C1(_4313_),
+ .Y(_0187_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4b_1 _8693_ (.A(_4133_),
+ .B(_3904_),
+ .C(_3955_),
+ .D_N(_3479_),
+ .X(_4314_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_1 _8694_ (.A1(_3465_),
+ .A2(_3846_),
+ .B1(_3841_),
+ .C1(_3536_),
+ .Y(_4315_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8695_ (.A(_4125_),
+ .B(_4315_),
+ .C(_4123_),
+ .D(_4218_),
+ .X(_4316_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8696_ (.A(_4224_),
+ .B(_4314_),
+ .C(_4280_),
+ .D(_4316_),
+ .X(_4317_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8697_ (.A(_4317_),
+ .X(_0188_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3b_1 _8698_ (.A(_4097_),
+ .B(_4020_),
+ .C_N(_3474_),
+ .X(_4318_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8699_ (.A(_4160_),
+ .B(_4318_),
+ .C(_4239_),
+ .D(_4290_),
+ .X(_4319_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a21oi_1 _8700_ (.A1(_3472_),
+ .A2(_3476_),
+ .B1(_3526_),
+ .Y(_4320_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a2111o_2 _8701_ (.A1(_3636_),
+ .A2(_4320_),
+ .B1(_3644_),
+ .C1(_4150_),
+ .D1(_4235_),
+ .X(_4321_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8702_ (.A(_4319_),
+ .B(_4321_),
+ .Y(_4322_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8703_ (.A(_3453_),
+ .B(_4141_),
+ .C(_3694_),
+ .D(_4066_),
+ .X(_4323_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or2_1 _8704_ (.A(_3703_),
+ .B(_4065_),
+ .X(_4324_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8705_ (.A(_3967_),
+ .B(_4230_),
+ .C(_4324_),
+ .D(_4165_),
+ .X(_4325_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8706_ (.A(_4108_),
+ .B(_4242_),
+ .C(_4323_),
+ .D(_4325_),
+ .X(_4326_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8707_ (.A(_4241_),
+ .B(_4229_),
+ .C(_4326_),
+ .X(_4327_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8708_ (.A(_4020_),
+ .B(_3740_),
+ .C(_3684_),
+ .D(_3794_),
+ .X(_4328_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8709_ (.A(_4180_),
+ .B(_4328_),
+ .C(_4254_),
+ .D(_4308_),
+ .X(_4329_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8710_ (.A(_4247_),
+ .Y(_4330_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_4 _8711_ (.A1(_3630_),
+ .A2(_4248_),
+ .B1(_3746_),
+ .B2(_4249_),
+ .C1(_4330_),
+ .Y(_4331_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8712_ (.A(_4329_),
+ .B(_4331_),
+ .Y(_4332_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8713_ (.A(_3701_),
+ .B(_4187_),
+ .C(_4309_),
+ .D(_4186_),
+ .X(_4333_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8714_ (.A(_4258_),
+ .B(_4333_),
+ .C(_4260_),
+ .D(_4310_),
+ .X(_4334_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8715_ (.A(_3796_),
+ .B(_3902_),
+ .C(_3999_),
+ .X(_4335_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8716_ (.A(_4205_),
+ .B(_4335_),
+ .C(_4269_),
+ .D(_4297_),
+ .X(_4336_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o22a_1 _8717_ (.A1(_3738_),
+ .A2(_3584_),
+ .B1(_3738_),
+ .B2(_3710_),
+ .X(_4337_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_1 _8718_ (.A1(_3975_),
+ .A2(_4337_),
+ .B1(_3852_),
+ .C1(_3841_),
+ .Y(_4338_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_2 _8719_ (.A(_4195_),
+ .B(_4338_),
+ .C(_4265_),
+ .X(_4339_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8720_ (.A(_3724_),
+ .B(_4191_),
+ .C(_4006_),
+ .X(_4340_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8721_ (.A(_3832_),
+ .B(_4211_),
+ .C(_4104_),
+ .D(_4340_),
+ .X(_4341_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or3_1 _8722_ (.A(_3968_),
+ .B(_4274_),
+ .C(_4341_),
+ .X(_4342_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor3_4 _8723_ (.A(_4303_),
+ .B(_4342_),
+ .C(_4300_),
+ .Y(_4343_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o21ai_1 _8724_ (.A1(_4336_),
+ .A2(_4339_),
+ .B1(_4343_),
+ .Y(_4344_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221ai_1 _8725_ (.A1(_4322_),
+ .A2(_4327_),
+ .B1(_4332_),
+ .B2(_4334_),
+ .C1(_4344_),
+ .Y(_0189_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o2111ai_4 _8726_ (.A1(_3478_),
+ .A2(_3501_),
+ .B1(_3872_),
+ .C1(_3943_),
+ .D1(_4130_),
+ .Y(_4345_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8727_ (.A(_4221_),
+ .B(_4345_),
+ .C(_4282_),
+ .D(_4316_),
+ .X(_4346_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8728_ (.A(_4346_),
+ .X(_0190_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8729_ (.A(_4336_),
+ .Y(_4347_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_2 _8730_ (.A(_3769_),
+ .B(_3870_),
+ .C(_3989_),
+ .D(_4200_),
+ .X(_4348_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8731_ (.A(_4266_),
+ .B(_4348_),
+ .C(_4339_),
+ .D(_4299_),
+ .X(_4349_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8732_ (.A(_4319_),
+ .Y(_4350_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8733_ (.A(_4327_),
+ .Y(_4351_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8734_ (.A(_3502_),
+ .B(_4038_),
+ .C(_4084_),
+ .D(_4155_),
+ .X(_4352_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__or4_1 _8735_ (.A(_4231_),
+ .B(_4352_),
+ .C(_4321_),
+ .D(_4288_),
+ .X(_4353_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211a_1 _8736_ (.A1(_3584_),
+ .A2(_3621_),
+ .B1(_3659_),
+ .C1(_4039_),
+ .X(_4354_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o211ai_4 _8737_ (.A1(_3623_),
+ .A2(_4171_),
+ .B1(_4354_),
+ .C1(_4252_),
+ .Y(_4355_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8738_ (.A(_4329_),
+ .Y(_4356_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8739_ (.A(_4334_),
+ .Y(_4357_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o311a_1 _8740_ (.A1(_4331_),
+ .A2(_4355_),
+ .A3(_4306_),
+ .B1(_4356_),
+ .C1(_4357_),
+ .X(_4358_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8741_ (.A1(_4350_),
+ .A2(_4351_),
+ .A3(_4353_),
+ .B1(_4358_),
+ .X(_4359_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__a31o_1 _8742_ (.A1(_4347_),
+ .A2(_4343_),
+ .A3(_4349_),
+ .B1(_4359_),
+ .X(_0191_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8743_ (.A(_4408_),
+ .X(_4360_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8744_ (.A(_4360_),
+ .X(net229),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8745_ (.A(_4411_),
+ .X(_4361_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8746_ (.A(_4361_),
+ .X(net240),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8747_ (.A(_4414_),
+ .X(_4362_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8748_ (.A(_4362_),
+ .X(net243),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8749_ (.A(_4415_),
+ .X(_4363_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8750_ (.A(_4363_),
+ .X(net244),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8751_ (.A(_4416_),
+ .X(_4364_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8752_ (.A(_4364_),
+ .X(net208),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8753_ (.A(_4417_),
+ .X(_4365_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8754_ (.A(_4365_),
+ .X(net209),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8755_ (.A(_4418_),
+ .X(_4366_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8756_ (.A(_4366_),
+ .X(net210),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8757_ (.A(_4419_),
+ .X(_4367_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8758_ (.A(_4367_),
+ .X(net211),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8759_ (.A(_4420_),
+ .X(_4368_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8760_ (.A(_4368_),
+ .X(net212),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8761_ (.A(_4421_),
+ .X(_4369_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8762_ (.A(_4369_),
+ .X(net213),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8763_ (.A(_4422_),
+ .X(_4370_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8764_ (.A(_4370_),
+ .X(net214),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8765_ (.A(_4423_),
+ .X(_4371_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8766_ (.A(_4371_),
+ .X(net215),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8767_ (.A(_4424_),
+ .X(_4372_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8768_ (.A(_4372_),
+ .X(net216),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8769_ (.A(_4425_),
+ .X(_4373_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8770_ (.A(_4373_),
+ .X(net217),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8771_ (.A(_4426_),
+ .X(_4374_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8772_ (.A(_4374_),
+ .X(net219),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8773_ (.A(_4427_),
+ .X(_4375_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8774_ (.A(_4375_),
+ .X(net220),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8775_ (.A(_4428_),
+ .X(_4376_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8776_ (.A(_4376_),
+ .X(net221),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8777_ (.A(_4429_),
+ .X(_4377_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8778_ (.A(_4377_),
+ .X(net222),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8779_ (.A(_4430_),
+ .X(_4378_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8780_ (.A(_4378_),
+ .X(net223),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8781_ (.A(_4431_),
+ .X(_4379_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8782_ (.A(_4379_),
+ .X(net224),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8783_ (.A(_4432_),
+ .X(_4380_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8784_ (.A(_4380_),
+ .X(net225),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8785_ (.A(_4433_),
+ .X(_4381_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8786_ (.A(_4381_),
+ .X(net226),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8787_ (.A(_4434_),
+ .X(_4382_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8788_ (.A(_4382_),
+ .X(net227),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8789_ (.A(_4435_),
+ .X(_4383_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8790_ (.A(_4383_),
+ .X(net228),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8791_ (.A(_4436_),
+ .X(_4384_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8792_ (.A(_4384_),
+ .X(net230),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8793_ (.A(_4437_),
+ .X(_4385_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8794_ (.A(_4385_),
+ .X(net231),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8795_ (.A(_4438_),
+ .X(_4386_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8796_ (.A(_4386_),
+ .X(net232),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8797_ (.A(_4439_),
+ .X(_4387_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8798_ (.A(_4387_),
+ .X(net233),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8799_ (.A(_4440_),
+ .X(_4388_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8800_ (.A(_4388_),
+ .X(net234),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8801_ (.A(net68),
+ .B(net126),
+ .X(_4389_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8802_ (.A(_4389_),
+ .X(net305),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8803_ (.A(net63),
+ .B(net79),
+ .X(_4390_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8804_ (.A(_4390_),
+ .X(net311),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__and2_1 _8805_ (.A(net36),
+ .B(net1),
+ .X(_4391_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8806_ (.A(_4391_),
+ .X(net203),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8807_ (.A(_1303_),
+ .B(_1848_),
+ .Y(net205),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_2 _8808_ (.A(_2597_),
+ .B(_2233_),
+ .Y(net206),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_2 _8809_ (.A(_2693_),
+ .Y(_4392_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8810_ (.A(_1082_),
+ .B(_4392_),
+ .Y(_0027_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8811_ (.A(_1081_),
+ .B(_4392_),
+ .Y(_0026_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8812_ (.A(_1083_),
+ .B(_4392_),
+ .Y(_0025_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__nor2_1 _8813_ (.A(_1084_),
+ .B(_4392_),
+ .Y(_0024_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__o221a_1 _8814_ (.A1(serial_xfer),
+ .A2(_2032_),
+ .B1(net368),
+ .B2(_1032_),
+ .C1(_0063_),
+ .X(_1020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 _8815__378 (.HI(net378),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8816_ (.A(net87),
+ .X(net257),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8817_ (.A(net65),
+ .X(net314),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 _8818_ (.A(net66),
+ .X(net315),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8819_ (.A0(serial_clock_pre),
+ .A1(serial_bb_clock),
+ .S(serial_bb_enable),
+ .X(net306),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8820_ (.A0(serial_load_pre),
+ .A1(serial_bb_load),
+ .S(serial_bb_enable),
+ .X(net309),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8821_ (.A0(serial_resetn_pre),
+ .A1(serial_bb_resetn),
+ .S(serial_bb_enable),
+ .X(net310),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8822_ (.A0(\serial_data_staging_1[12] ),
+ .A1(serial_bb_data_1),
+ .S(serial_bb_enable),
+ .X(net307),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8823_ (.A0(\serial_data_staging_2[12] ),
+ .A1(serial_bb_data_2),
+ .S(serial_bb_enable),
+ .X(net308),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8824_ (.A0(\mgmt_gpio_data[0] ),
+ .A1(net3),
+ .S(net1),
+ .X(net245),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8825_ (.A0(\mgmt_gpio_data[1] ),
+ .A1(\hkspi.SDO ),
+ .S(_0079_),
+ .X(_0095_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8826_ (.A0(_0095_),
+ .A1(net38),
+ .S(\hkspi.pass_thru_user ),
+ .X(_0096_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8827_ (.A0(_0096_),
+ .A1(net74),
+ .S(\hkspi.pass_thru_mgmt ),
+ .X(net246),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8828_ (.A0(\mgmt_gpio_data[35] ),
+ .A1(net81),
+ .S(net79),
+ .X(net247),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8829_ (.A0(\mgmt_gpio_data[36] ),
+ .A1(net89),
+ .S(net76),
+ .X(net248),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8830_ (.A0(\mgmt_gpio_data[37] ),
+ .A1(net91),
+ .S(net76),
+ .X(net249),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8831_ (.A0(_0097_),
+ .A1(net2),
+ .S(net1),
+ .X(net207),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8832_ (.A0(_0097_),
+ .A1(\hkspi.sdoenb ),
+ .S(_0079_),
+ .X(net218),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8833_ (.A0(_0094_),
+ .A1(net82),
+ .S(net79),
+ .X(net235),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8834_ (.A0(_0093_),
+ .A1(net90),
+ .S(net76),
+ .X(net236),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8835_ (.A0(_0092_),
+ .A1(net92),
+ .S(net76),
+ .X(net237),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8836_ (.A0(net84),
+ .A1(net67),
+ .S(\hkspi.pass_thru_mgmt_delay ),
+ .X(net252),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8837_ (.A0(net83),
+ .A1(clknet_2_0_0_mgmt_gpio_in[4]),
+ .S(\hkspi.pass_thru_mgmt ),
+ .X(net250),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8838_ (.A0(net85),
+ .A1(net58),
+ .S(\hkspi.pass_thru_mgmt_delay ),
+ .X(net254),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8839_ (.A0(net58),
+ .A1(\wbbd_data[0] ),
+ .S(wbbd_busy),
+ .X(\cdata[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8840_ (.A0(\hkspi.odata[1] ),
+ .A1(\wbbd_data[1] ),
+ .S(wbbd_busy),
+ .X(\cdata[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8841_ (.A0(\hkspi.odata[2] ),
+ .A1(\wbbd_data[2] ),
+ .S(wbbd_busy),
+ .X(\cdata[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8842_ (.A0(\hkspi.odata[3] ),
+ .A1(\wbbd_data[3] ),
+ .S(wbbd_busy),
+ .X(\cdata[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8843_ (.A0(\hkspi.odata[4] ),
+ .A1(\wbbd_data[4] ),
+ .S(wbbd_busy),
+ .X(\cdata[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8844_ (.A0(\hkspi.odata[5] ),
+ .A1(\wbbd_data[5] ),
+ .S(wbbd_busy),
+ .X(\cdata[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8845_ (.A0(\hkspi.odata[6] ),
+ .A1(\wbbd_data[6] ),
+ .S(wbbd_busy),
+ .X(\cdata[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8846_ (.A0(\hkspi.odata[7] ),
+ .A1(\wbbd_data[7] ),
+ .S(wbbd_busy),
+ .X(\cdata[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8847_ (.A0(_0098_),
+ .A1(wbbd_sck),
+ .S(wbbd_busy),
+ .X(csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8848_ (.A0(\mgmt_gpio_data_buf[16] ),
+ .A1(net368),
+ .S(_0080_),
+ .X(_0208_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8849_ (.A0(\mgmt_gpio_data_buf[0] ),
+ .A1(net368),
+ .S(_0085_),
+ .X(_0192_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8850_ (.A0(_0130_),
+ .A1(\gpio_configure[0][1] ),
+ .S(_0127_),
+ .X(_0131_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8851_ (.A0(_0131_),
+ .A1(\serial_data_staging_1[0] ),
+ .S(\xfer_state[1] ),
+ .X(_0003_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8852_ (.A0(_0132_),
+ .A1(\gpio_configure[0][2] ),
+ .S(_0127_),
+ .X(_0133_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8853_ (.A0(_0133_),
+ .A1(\serial_data_staging_1[1] ),
+ .S(\xfer_state[1] ),
+ .X(_0004_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8854_ (.A0(_0134_),
+ .A1(\gpio_configure[0][3] ),
+ .S(_0127_),
+ .X(_0135_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8855_ (.A0(_0135_),
+ .A1(\serial_data_staging_1[2] ),
+ .S(\xfer_state[1] ),
+ .X(_0005_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8856_ (.A0(_0136_),
+ .A1(\gpio_configure[0][4] ),
+ .S(_0127_),
+ .X(_0137_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8857_ (.A0(_0137_),
+ .A1(\serial_data_staging_1[3] ),
+ .S(\xfer_state[1] ),
+ .X(_0006_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8858_ (.A0(_0138_),
+ .A1(\gpio_configure[0][5] ),
+ .S(_0127_),
+ .X(_0139_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8859_ (.A0(_0139_),
+ .A1(\serial_data_staging_1[4] ),
+ .S(\xfer_state[1] ),
+ .X(_0007_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8860_ (.A0(_0140_),
+ .A1(\gpio_configure[0][6] ),
+ .S(_0127_),
+ .X(_0141_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8861_ (.A0(_0141_),
+ .A1(\serial_data_staging_1[5] ),
+ .S(\xfer_state[1] ),
+ .X(_0008_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8862_ (.A0(_0142_),
+ .A1(\gpio_configure[0][7] ),
+ .S(_0127_),
+ .X(_0143_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8863_ (.A0(_0143_),
+ .A1(\serial_data_staging_1[6] ),
+ .S(\xfer_state[1] ),
+ .X(_0009_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8864_ (.A0(_0144_),
+ .A1(\gpio_configure[0][8] ),
+ .S(_0127_),
+ .X(_0145_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8865_ (.A0(_0145_),
+ .A1(\serial_data_staging_1[7] ),
+ .S(\xfer_state[1] ),
+ .X(_0010_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8866_ (.A0(_0146_),
+ .A1(\gpio_configure[0][9] ),
+ .S(_0127_),
+ .X(_0147_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8867_ (.A0(_0147_),
+ .A1(\serial_data_staging_1[8] ),
+ .S(\xfer_state[1] ),
+ .X(_0011_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8868_ (.A0(_0148_),
+ .A1(\gpio_configure[0][10] ),
+ .S(_0127_),
+ .X(_0149_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8869_ (.A0(_0149_),
+ .A1(\serial_data_staging_1[9] ),
+ .S(\xfer_state[1] ),
+ .X(_0000_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8870_ (.A0(_0150_),
+ .A1(\gpio_configure[0][11] ),
+ .S(_0127_),
+ .X(_0151_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8871_ (.A0(_0151_),
+ .A1(\serial_data_staging_1[10] ),
+ .S(\xfer_state[1] ),
+ .X(_0001_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8872_ (.A0(_0152_),
+ .A1(\gpio_configure[0][12] ),
+ .S(_0127_),
+ .X(_0153_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8873_ (.A0(_0153_),
+ .A1(\serial_data_staging_1[11] ),
+ .S(\xfer_state[1] ),
+ .X(_0002_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8874_ (.A0(_0103_),
+ .A1(\gpio_configure[0][1] ),
+ .S(_0100_),
+ .X(_0104_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8875_ (.A0(_0104_),
+ .A1(\serial_data_staging_2[0] ),
+ .S(\xfer_state[1] ),
+ .X(_0015_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8876_ (.A0(_0105_),
+ .A1(\gpio_configure[0][2] ),
+ .S(_0100_),
+ .X(_0106_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8877_ (.A0(_0106_),
+ .A1(\serial_data_staging_2[1] ),
+ .S(\xfer_state[1] ),
+ .X(_0016_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8878_ (.A0(_0107_),
+ .A1(\gpio_configure[0][3] ),
+ .S(_0100_),
+ .X(_0108_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8879_ (.A0(_0108_),
+ .A1(\serial_data_staging_2[2] ),
+ .S(\xfer_state[1] ),
+ .X(_0017_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8880_ (.A0(_0109_),
+ .A1(\gpio_configure[0][4] ),
+ .S(_0100_),
+ .X(_0110_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8881_ (.A0(_0110_),
+ .A1(\serial_data_staging_2[3] ),
+ .S(\xfer_state[1] ),
+ .X(_0018_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8882_ (.A0(_0111_),
+ .A1(\gpio_configure[0][5] ),
+ .S(_0100_),
+ .X(_0112_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8883_ (.A0(_0112_),
+ .A1(\serial_data_staging_2[4] ),
+ .S(\xfer_state[1] ),
+ .X(_0019_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8884_ (.A0(_0113_),
+ .A1(\gpio_configure[0][6] ),
+ .S(_0100_),
+ .X(_0114_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8885_ (.A0(_0114_),
+ .A1(\serial_data_staging_2[5] ),
+ .S(\xfer_state[1] ),
+ .X(_0020_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8886_ (.A0(_0115_),
+ .A1(\gpio_configure[0][7] ),
+ .S(_0100_),
+ .X(_0116_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8887_ (.A0(_0116_),
+ .A1(\serial_data_staging_2[6] ),
+ .S(\xfer_state[1] ),
+ .X(_0021_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8888_ (.A0(_0117_),
+ .A1(\gpio_configure[0][8] ),
+ .S(_0100_),
+ .X(_0118_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8889_ (.A0(_0118_),
+ .A1(\serial_data_staging_2[7] ),
+ .S(\xfer_state[1] ),
+ .X(_0022_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8890_ (.A0(_0119_),
+ .A1(\gpio_configure[0][9] ),
+ .S(_0100_),
+ .X(_0120_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8891_ (.A0(_0120_),
+ .A1(\serial_data_staging_2[8] ),
+ .S(\xfer_state[1] ),
+ .X(_0023_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8892_ (.A0(_0121_),
+ .A1(\gpio_configure[0][10] ),
+ .S(_0100_),
+ .X(_0122_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8893_ (.A0(_0122_),
+ .A1(\serial_data_staging_2[9] ),
+ .S(\xfer_state[1] ),
+ .X(_0012_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8894_ (.A0(_0123_),
+ .A1(\gpio_configure[0][11] ),
+ .S(_0100_),
+ .X(_0124_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8895_ (.A0(_0124_),
+ .A1(\serial_data_staging_2[10] ),
+ .S(\xfer_state[1] ),
+ .X(_0013_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8896_ (.A0(_0125_),
+ .A1(\gpio_configure[0][12] ),
+ .S(_0100_),
+ .X(_0126_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8897_ (.A0(_0126_),
+ .A1(\serial_data_staging_2[11] ),
+ .S(\xfer_state[1] ),
+ .X(_0014_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8898_ (.A0(\mgmt_gpio_data_buf[15] ),
+ .A1(\cdata[7] ),
+ .S(_0083_),
+ .X(_0207_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8899_ (.A0(_0158_),
+ .A1(\hkspi.addr[1] ),
+ .S(\hkspi.state[3] ),
+ .X(_0049_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8900_ (.A0(_0157_),
+ .A1(\hkspi.addr[0] ),
+ .S(\hkspi.state[3] ),
+ .X(_0048_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8901_ (.A0(_0165_),
+ .A1(\hkspi.fixed[0] ),
+ .S(\hkspi.state[0] ),
+ .X(_0044_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8902_ (.A0(_0156_),
+ .A1(net58),
+ .S(\hkspi.state[3] ),
+ .X(_0047_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8903_ (.A0(\mgmt_gpio_data_buf[1] ),
+ .A1(net366),
+ .S(_0085_),
+ .X(_0193_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8904_ (.A0(\mgmt_gpio_data_buf[6] ),
+ .A1(\cdata[6] ),
+ .S(_0085_),
+ .X(_0198_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8905_ (.A0(\mgmt_gpio_data_buf[10] ),
+ .A1(net364),
+ .S(_0083_),
+ .X(_0202_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8906_ (.A0(\mgmt_gpio_data_buf[12] ),
+ .A1(net360),
+ .S(_0083_),
+ .X(_0204_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8907_ (.A0(_0163_),
+ .A1(\hkspi.addr[6] ),
+ .S(\hkspi.state[3] ),
+ .X(_0054_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8908_ (.A0(_0164_),
+ .A1(net58),
+ .S(\hkspi.state[0] ),
+ .X(_0043_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8909_ (.A0(_0166_),
+ .A1(\hkspi.fixed[1] ),
+ .S(\hkspi.state[0] ),
+ .X(_0045_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8910_ (.A0(_0159_),
+ .A1(\hkspi.addr[2] ),
+ .S(\hkspi.state[3] ),
+ .X(_0050_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8911_ (.A0(_0160_),
+ .A1(\hkspi.addr[3] ),
+ .S(\hkspi.state[3] ),
+ .X(_0051_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8912_ (.A0(_0161_),
+ .A1(\hkspi.addr[4] ),
+ .S(\hkspi.state[3] ),
+ .X(_0052_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8913_ (.A0(_0162_),
+ .A1(\hkspi.addr[5] ),
+ .S(\hkspi.state[3] ),
+ .X(_0053_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8914_ (.A0(\mgmt_gpio_data_buf[7] ),
+ .A1(\cdata[7] ),
+ .S(_0085_),
+ .X(_0199_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8915_ (.A0(\mgmt_gpio_data_buf[5] ),
+ .A1(\cdata[5] ),
+ .S(_0085_),
+ .X(_0197_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8916_ (.A0(\mgmt_gpio_data_buf[8] ),
+ .A1(net368),
+ .S(_0083_),
+ .X(_0200_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8917_ (.A0(\mgmt_gpio_data_buf[23] ),
+ .A1(\cdata[7] ),
+ .S(_0080_),
+ .X(_0215_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8918_ (.A0(\mgmt_gpio_data_buf[22] ),
+ .A1(\cdata[6] ),
+ .S(_0080_),
+ .X(_0214_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8919_ (.A0(\mgmt_gpio_data_buf[17] ),
+ .A1(\cdata[1] ),
+ .S(_0080_),
+ .X(_0209_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8920_ (.A0(\mgmt_gpio_data_buf[4] ),
+ .A1(net360),
+ .S(_0085_),
+ .X(_0196_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8921_ (.A0(\mgmt_gpio_data_buf[21] ),
+ .A1(\cdata[5] ),
+ .S(_0080_),
+ .X(_0213_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8922_ (.A0(\mgmt_gpio_data_buf[18] ),
+ .A1(\cdata[2] ),
+ .S(_0080_),
+ .X(_0210_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8923_ (.A0(\mgmt_gpio_data_buf[3] ),
+ .A1(net362),
+ .S(_0085_),
+ .X(_0195_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8924_ (.A0(\xfer_state[2] ),
+ .A1(net306),
+ .S(\xfer_state[1] ),
+ .X(_0042_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8925_ (.A0(\mgmt_gpio_data_buf[20] ),
+ .A1(net360),
+ .S(_0080_),
+ .X(_0212_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8926_ (.A0(\mgmt_gpio_data_buf[19] ),
+ .A1(\cdata[3] ),
+ .S(_0080_),
+ .X(_0211_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8927_ (.A0(\mgmt_gpio_data_buf[14] ),
+ .A1(\cdata[6] ),
+ .S(_0083_),
+ .X(_0206_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8928_ (.A0(\mgmt_gpio_data_buf[13] ),
+ .A1(\cdata[5] ),
+ .S(_0083_),
+ .X(_0205_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8929_ (.A0(\mgmt_gpio_data_buf[11] ),
+ .A1(net362),
+ .S(_0083_),
+ .X(_0203_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8930_ (.A0(\mgmt_gpio_data_buf[9] ),
+ .A1(net366),
+ .S(_0083_),
+ .X(_0201_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8931_ (.A0(\hkspi.addr[2] ),
+ .A1(\hkspi.addr[1] ),
+ .S(\hkspi.state[3] ),
+ .X(_0068_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8932_ (.A0(_0068_),
+ .A1(\wbbd_addr[2] ),
+ .S(wbbd_busy),
+ .X(_0069_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8933_ (.A0(\hkspi.addr[3] ),
+ .A1(\hkspi.addr[2] ),
+ .S(\hkspi.state[3] ),
+ .X(_0070_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8934_ (.A0(_0070_),
+ .A1(\wbbd_addr[3] ),
+ .S(wbbd_busy),
+ .X(_0071_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8935_ (.A0(\hkspi.addr[4] ),
+ .A1(\hkspi.addr[3] ),
+ .S(\hkspi.state[3] ),
+ .X(_0072_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8936_ (.A0(_0072_),
+ .A1(\wbbd_addr[4] ),
+ .S(wbbd_busy),
+ .X(_0073_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8937_ (.A0(\hkspi.addr[5] ),
+ .A1(\hkspi.addr[4] ),
+ .S(\hkspi.state[3] ),
+ .X(_0074_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8938_ (.A0(_0074_),
+ .A1(\wbbd_addr[5] ),
+ .S(wbbd_busy),
+ .X(_0075_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_8 _8939_ (.A0(\hkspi.wrstb ),
+ .A1(wbbd_write),
+ .S(wbbd_busy),
+ .X(_0063_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8940_ (.A0(\hkspi.addr[6] ),
+ .A1(\hkspi.addr[5] ),
+ .S(\hkspi.state[3] ),
+ .X(_0076_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8941_ (.A0(_0076_),
+ .A1(\wbbd_addr[6] ),
+ .S(wbbd_busy),
+ .X(_0077_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8942_ (.A0(\hkspi.addr[7] ),
+ .A1(\hkspi.addr[6] ),
+ .S(\hkspi.state[3] ),
+ .X(_0078_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8943_ (.A0(\hkspi.addr[0] ),
+ .A1(net58),
+ .S(\hkspi.state[3] ),
+ .X(_0064_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8944_ (.A0(_0064_),
+ .A1(\wbbd_addr[0] ),
+ .S(wbbd_busy),
+ .X(_0065_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8945_ (.A0(\hkspi.addr[1] ),
+ .A1(\hkspi.addr[0] ),
+ .S(\hkspi.state[3] ),
+ .X(_0066_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8946_ (.A0(_0066_),
+ .A1(\wbbd_addr[1] ),
+ .S(wbbd_busy),
+ .X(_0067_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8947_ (.A0(\hkspi.ldata[4] ),
+ .A1(\hkspi.idata[5] ),
+ .S(_0062_),
+ .X(_0059_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8948_ (.A0(net393),
+ .A1(\hkspi.idata[6] ),
+ .S(_0062_),
+ .X(_0060_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8949_ (.A0(\hkspi.ldata[2] ),
+ .A1(\hkspi.idata[3] ),
+ .S(_0062_),
+ .X(_0057_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8950_ (.A0(\hkspi.ldata[3] ),
+ .A1(\hkspi.idata[4] ),
+ .S(_0062_),
+ .X(_0058_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8951_ (.A0(\hkspi.ldata[1] ),
+ .A1(\hkspi.idata[2] ),
+ .S(_0062_),
+ .X(_0056_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8952_ (.A0(\hkspi.ldata[0] ),
+ .A1(\hkspi.idata[1] ),
+ .S(_0062_),
+ .X(_0055_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8953_ (.A0(\hkspi.ldata[6] ),
+ .A1(\hkspi.idata[7] ),
+ .S(_0062_),
+ .X(_0061_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8954_ (.A0(_0155_),
+ .A1(_0154_),
+ .S(\hkspi.state[2] ),
+ .X(_0046_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8955_ (.A0(\mgmt_gpio_data_buf[2] ),
+ .A1(net364),
+ .S(_0085_),
+ .X(_0194_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8956_ (.A0(_0085_),
+ .A1(_0081_),
+ .S(_0079_),
+ .X(_0086_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8957_ (.A0(_0089_),
+ .A1(_0087_),
+ .S(_0062_),
+ .X(_0090_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8958_ (.A0(\hkspi.count[0] ),
+ .A1(\hkspi.count[2] ),
+ .S(\hkspi.count[1] ),
+ .X(_0091_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8959_ (.A0(_0101_),
+ .A1(_0099_),
+ .S(_0100_),
+ .X(_0102_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8960_ (.A0(_0168_),
+ .A1(_0088_),
+ .S(_0167_),
+ .X(_4442_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8961_ (.A0(_0170_),
+ .A1(net164),
+ .S(_0169_),
+ .X(_4393_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8962_ (.A0(_0171_),
+ .A1(net175),
+ .S(_0169_),
+ .X(_4394_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8963_ (.A0(_0172_),
+ .A1(net186),
+ .S(_0169_),
+ .X(_4395_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8964_ (.A0(_0173_),
+ .A1(net189),
+ .S(_0169_),
+ .X(_4396_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8965_ (.A0(_0174_),
+ .A1(net190),
+ .S(_0169_),
+ .X(_4397_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8966_ (.A0(_0175_),
+ .A1(net191),
+ .S(_0169_),
+ .X(_4398_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8967_ (.A0(_0176_),
+ .A1(net192),
+ .S(_0169_),
+ .X(_4399_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8968_ (.A0(_0177_),
+ .A1(net193),
+ .S(_0169_),
+ .X(_4400_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8969_ (.A0(_0179_),
+ .A1(_0178_),
+ .S(_0169_),
+ .X(_4401_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8970_ (.A0(_0181_),
+ .A1(_0180_),
+ .S(_0169_),
+ .X(_4402_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_4 _8971_ (.A0(_0183_),
+ .A1(_0182_),
+ .S(_0169_),
+ .X(_4403_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8972_ (.A0(_0185_),
+ .A1(_0184_),
+ .S(_0169_),
+ .X(_4404_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8973_ (.A0(_0187_),
+ .A1(_0186_),
+ .S(_0169_),
+ .X(_4405_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8974_ (.A0(_0189_),
+ .A1(_0188_),
+ .S(_0169_),
+ .X(_4406_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_2 _8975_ (.A0(_0191_),
+ .A1(_0190_),
+ .S(_0169_),
+ .X(_4407_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8976_ (.A0(_0080_),
+ .A1(_0081_),
+ .S(_0079_),
+ .X(_0082_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8977_ (.A0(_0083_),
+ .A1(_0081_),
+ .S(_0079_),
+ .X(_0084_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__mux2_1 _8978_ (.A0(_0128_),
+ .A1(_0099_),
+ .S(_0127_),
+ .X(_0129_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8979_ (.A(\mgmt_gpio_data[2] ),
+ .TE_B(_4408_),
+ .Z(mgmt_gpio_out[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8980_ (.A(\mgmt_gpio_data[3] ),
+ .TE_B(_4409_),
+ .Z(mgmt_gpio_out[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8981_ (.A(\mgmt_gpio_data[4] ),
+ .TE_B(_4410_),
+ .Z(mgmt_gpio_out[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8982_ (.A(\mgmt_gpio_data[5] ),
+ .TE_B(_4411_),
+ .Z(mgmt_gpio_out[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8983_ (.A(\mgmt_gpio_out_pre[6] ),
+ .TE_B(_4412_),
+ .Z(mgmt_gpio_out[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8984_ (.A(\mgmt_gpio_data[7] ),
+ .TE_B(_4413_),
+ .Z(mgmt_gpio_out[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8985_ (.A(\mgmt_gpio_out_pre[8] ),
+ .TE_B(_4414_),
+ .Z(mgmt_gpio_out[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 _8986_ (.A(\mgmt_gpio_out_pre[9] ),
+ .TE_B(_4415_),
+ .Z(mgmt_gpio_out[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8987_ (.A(\mgmt_gpio_out_pre[10] ),
+ .TE_B(_4416_),
+ .Z(mgmt_gpio_out[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8988_ (.A(\mgmt_gpio_data[11] ),
+ .TE_B(_4417_),
+ .Z(mgmt_gpio_out[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8989_ (.A(\mgmt_gpio_data[12] ),
+ .TE_B(_4418_),
+ .Z(mgmt_gpio_out[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8990_ (.A(\mgmt_gpio_out_pre[13] ),
+ .TE_B(_4419_),
+ .Z(mgmt_gpio_out[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 _8991_ (.A(\mgmt_gpio_out_pre[14] ),
+ .TE_B(_4420_),
+ .Z(mgmt_gpio_out[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_2 _8992_ (.A(\mgmt_gpio_out_pre[15] ),
+ .TE_B(_4421_),
+ .Z(mgmt_gpio_out[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8993_ (.A(\mgmt_gpio_data[16] ),
+ .TE_B(_4422_),
+ .Z(mgmt_gpio_out[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8994_ (.A(\mgmt_gpio_data[17] ),
+ .TE_B(_4423_),
+ .Z(mgmt_gpio_out[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8995_ (.A(\mgmt_gpio_data[18] ),
+ .TE_B(_4424_),
+ .Z(mgmt_gpio_out[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8996_ (.A(\mgmt_gpio_data[19] ),
+ .TE_B(_4425_),
+ .Z(mgmt_gpio_out[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8997_ (.A(\mgmt_gpio_data[20] ),
+ .TE_B(_4426_),
+ .Z(mgmt_gpio_out[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8998_ (.A(\mgmt_gpio_data[21] ),
+ .TE_B(_4427_),
+ .Z(mgmt_gpio_out[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _8999_ (.A(\mgmt_gpio_data[22] ),
+ .TE_B(_4428_),
+ .Z(mgmt_gpio_out[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9000_ (.A(\mgmt_gpio_data[23] ),
+ .TE_B(_4429_),
+ .Z(mgmt_gpio_out[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9001_ (.A(\mgmt_gpio_data[24] ),
+ .TE_B(_4430_),
+ .Z(mgmt_gpio_out[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9002_ (.A(\mgmt_gpio_data[25] ),
+ .TE_B(_4431_),
+ .Z(mgmt_gpio_out[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9003_ (.A(\mgmt_gpio_data[26] ),
+ .TE_B(_4432_),
+ .Z(mgmt_gpio_out[26]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9004_ (.A(\mgmt_gpio_data[27] ),
+ .TE_B(_4433_),
+ .Z(mgmt_gpio_out[27]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9005_ (.A(\mgmt_gpio_data[28] ),
+ .TE_B(_4434_),
+ .Z(mgmt_gpio_out[28]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9006_ (.A(\mgmt_gpio_data[29] ),
+ .TE_B(_4435_),
+ .Z(mgmt_gpio_out[29]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9007_ (.A(\mgmt_gpio_data[30] ),
+ .TE_B(_4436_),
+ .Z(mgmt_gpio_out[30]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9008_ (.A(\mgmt_gpio_data[31] ),
+ .TE_B(_4437_),
+ .Z(mgmt_gpio_out[31]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9009_ (.A(\mgmt_gpio_out_pre[32] ),
+ .TE_B(_4438_),
+ .Z(mgmt_gpio_out[32]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9010_ (.A(\mgmt_gpio_out_pre[33] ),
+ .TE_B(_4439_),
+ .Z(mgmt_gpio_out[33]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__ebufn_8 _9011_ (.A(\mgmt_gpio_data[34] ),
+ .TE_B(_4440_),
+ .Z(mgmt_gpio_out[34]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9012_ (.D(_0262_),
+ .Q(net357),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9013_ (.D(_0263_),
+ .Q(net358),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9014_ (.D(_0264_),
+ .Q(net328),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9015_ (.D(_0265_),
+ .Q(net329),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9016_ (.D(_0266_),
+ .Q(net330),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9017_ (.D(_0267_),
+ .Q(net331),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9018_ (.D(_0268_),
+ .Q(net332),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9019_ (.D(_0269_),
+ .Q(net333),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9020_ (.D(_0270_),
+ .Q(net327),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9021_ (.D(_0271_),
+ .Q(net338),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9022_ (.D(_0272_),
+ .Q(net349),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9023_ (.D(_0273_),
+ .Q(net352),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9024_ (.D(_0274_),
+ .Q(net353),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9025_ (.D(_0275_),
+ .Q(net354),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9026_ (.D(_0276_),
+ .Q(net355),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9027_ (.D(_0277_),
+ .Q(net356),
+ .CLK(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9028_ (.D(_0278_),
+ .Q(net334),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9029_ (.D(_0279_),
+ .Q(net335),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9030_ (.D(_0280_),
+ .Q(net336),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9031_ (.D(_0281_),
+ .Q(net337),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9032_ (.D(_0282_),
+ .Q(net339),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9033_ (.D(_0283_),
+ .Q(net340),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9034_ (.D(_0284_),
+ .Q(net341),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9035_ (.D(_0285_),
+ .Q(net342),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9036_ (.D(_0286_),
+ .Q(net343),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9037_ (.D(_0287_),
+ .Q(net344),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9038_ (.D(_0288_),
+ .Q(net345),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9039_ (.D(_0289_),
+ .Q(net346),
+ .CLK(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9040_ (.D(_0290_),
+ .Q(net347),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9041_ (.D(_0291_),
+ .Q(net348),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9042_ (.D(_0292_),
+ .Q(net350),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9043_ (.D(_0293_),
+ .Q(net351),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9044_ (.D(_0294_),
+ .Q(net300),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9045_ (.D(_0295_),
+ .Q(net301),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9046_ (.D(_0296_),
+ .Q(net302),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfxtp_1 _9047_ (.D(_0297_),
+ .Q(net303),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_4 _9048_ (.D(_0028_),
+ .Q(\hkspi.state[0] ),
+ .SET_B(_0216_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9049_ (.D(_0029_),
+ .Q(\hkspi.state[1] ),
+ .RESET_B(_0217_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9050_ (.D(_0030_),
+ .Q(\hkspi.state[2] ),
+ .RESET_B(_0218_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9051_ (.D(_0031_),
+ .Q(\hkspi.state[3] ),
+ .RESET_B(_0219_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9052_ (.D(_0032_),
+ .Q(\hkspi.state[4] ),
+ .RESET_B(_0220_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9053_ (.D(_0038_),
+ .Q(\xfer_state[0] ),
+ .SET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9054_ (.D(_0039_),
+ .Q(\xfer_state[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9055_ (.D(_0040_),
+ .Q(\xfer_state[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9056_ (.D(_0041_),
+ .Q(\xfer_state[3] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9057_ (.D(net378),
+ .Q(serial_resetn_pre),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9058_ (.D(_0046_),
+ .Q(\hkspi.sdoenb ),
+ .SET_B(_0221_),
+ .CLK(net379),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9059_ (.D(_0033_),
+ .Q(\wbbd_state[0] ),
+ .SET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9060_ (.D(_0024_),
+ .Q(\wbbd_state[1] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9061_ (.D(_0025_),
+ .Q(\wbbd_state[2] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9062_ (.D(_0026_),
+ .Q(\wbbd_state[3] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9063_ (.D(_0027_),
+ .Q(\wbbd_state[4] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9064_ (.D(_0034_),
+ .Q(\wbbd_state[5] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9065_ (.D(\wbbd_state[1] ),
+ .Q(\wbbd_state[6] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9066_ (.D(_0035_),
+ .Q(\wbbd_state[7] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9067_ (.D(_0036_),
+ .Q(\wbbd_state[8] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9068_ (.D(_0037_),
+ .Q(\wbbd_state[9] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9069_ (.D(_0298_),
+ .Q(serial_bb_load),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9070_ (.D(_0299_),
+ .Q(\gpio_configure[26][0] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9071_ (.D(_0300_),
+ .Q(\gpio_configure[26][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9072_ (.D(_0301_),
+ .Q(\gpio_configure[26][2] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9073_ (.D(_0302_),
+ .Q(\gpio_configure[26][3] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9074_ (.D(_0303_),
+ .Q(\gpio_configure[26][4] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9075_ (.D(_0304_),
+ .Q(\gpio_configure[26][5] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9076_ (.D(_0305_),
+ .Q(\gpio_configure[26][6] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9077_ (.D(_0306_),
+ .Q(\gpio_configure[26][7] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9078_ (.D(_0307_),
+ .Q(serial_bb_resetn),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9079_ (.D(_0308_),
+ .Q(serial_bb_data_1),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9080_ (.D(_0309_),
+ .Q(\hkspi.pass_thru_user_delay ),
+ .RESET_B(_0223_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9081_ (.D(_0310_),
+ .Q(trap_output_dest),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9082_ (.D(_0311_),
+ .Q(\hkspi.addr[0] ),
+ .RESET_B(_0224_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9083_ (.D(_0312_),
+ .Q(\hkspi.addr[1] ),
+ .RESET_B(_0225_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9084_ (.D(_0313_),
+ .Q(\hkspi.addr[2] ),
+ .RESET_B(_0226_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9085_ (.D(_0314_),
+ .Q(\hkspi.addr[3] ),
+ .RESET_B(_0227_),
+ .CLK(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9086_ (.D(_0315_),
+ .Q(\hkspi.addr[4] ),
+ .RESET_B(_0228_),
+ .CLK(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9087_ (.D(_0316_),
+ .Q(\hkspi.addr[5] ),
+ .RESET_B(_0229_),
+ .CLK(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9088_ (.D(_0317_),
+ .Q(\hkspi.addr[6] ),
+ .RESET_B(_0230_),
+ .CLK(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9089_ (.D(_0318_),
+ .Q(\hkspi.addr[7] ),
+ .RESET_B(_0231_),
+ .CLK(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9090_ (.D(_0319_),
+ .Q(\hkspi.count[0] ),
+ .RESET_B(_0232_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9091_ (.D(_0320_),
+ .Q(\hkspi.count[1] ),
+ .RESET_B(_0233_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9092_ (.D(_0321_),
+ .Q(\hkspi.count[2] ),
+ .RESET_B(_0234_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9093_ (.D(_0322_),
+ .Q(\gpio_configure[3][0] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9094_ (.D(_0323_),
+ .Q(\gpio_configure[3][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9095_ (.D(_0324_),
+ .Q(\gpio_configure[3][2] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9096_ (.D(_0325_),
+ .Q(\gpio_configure[3][3] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9097_ (.D(_0326_),
+ .Q(\gpio_configure[3][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9098_ (.D(_0327_),
+ .Q(\gpio_configure[3][5] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9099_ (.D(_0328_),
+ .Q(\gpio_configure[3][6] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9100_ (.D(_0329_),
+ .Q(\gpio_configure[3][7] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9101_ (.D(_0330_),
+ .Q(\gpio_configure[4][8] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9102_ (.D(_0331_),
+ .Q(\gpio_configure[4][9] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9103_ (.D(_0332_),
+ .Q(\gpio_configure[4][10] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9104_ (.D(_0333_),
+ .Q(\gpio_configure[4][11] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9105_ (.D(_0334_),
+ .Q(\gpio_configure[4][12] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9106_ (.D(_0335_),
+ .Q(\gpio_configure[4][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9107_ (.D(_0336_),
+ .Q(\gpio_configure[4][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9108_ (.D(_0337_),
+ .Q(\gpio_configure[4][2] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9109_ (.D(_0338_),
+ .Q(\gpio_configure[4][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9110_ (.D(_0339_),
+ .Q(\gpio_configure[4][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9111_ (.D(_0340_),
+ .Q(\gpio_configure[4][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9112_ (.D(_0341_),
+ .Q(\gpio_configure[4][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9113_ (.D(_0342_),
+ .Q(\gpio_configure[4][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9114_ (.D(_0343_),
+ .Q(\gpio_configure[5][8] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9115_ (.D(_0344_),
+ .Q(\gpio_configure[5][9] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_30_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9116_ (.D(_0345_),
+ .Q(\gpio_configure[5][10] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9117_ (.D(_0346_),
+ .Q(\gpio_configure[5][11] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9118_ (.D(_0347_),
+ .Q(\gpio_configure[5][12] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9119_ (.D(_0348_),
+ .Q(net326),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9120_ (.D(_0349_),
+ .Q(\gpio_configure[6][8] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9121_ (.D(_0350_),
+ .Q(\gpio_configure[6][9] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9122_ (.D(_0351_),
+ .Q(\gpio_configure[6][10] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9123_ (.D(_0352_),
+ .Q(\gpio_configure[6][11] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9124_ (.D(_0353_),
+ .Q(\gpio_configure[6][12] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9125_ (.D(_0354_),
+ .Q(\gpio_configure[6][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9126_ (.D(_0355_),
+ .Q(\gpio_configure[6][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_30_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9127_ (.D(_0356_),
+ .Q(\gpio_configure[6][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9128_ (.D(_0357_),
+ .Q(\gpio_configure[6][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9129_ (.D(_0358_),
+ .Q(\gpio_configure[6][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_30_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9130_ (.D(_0359_),
+ .Q(\gpio_configure[6][5] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9131_ (.D(_0360_),
+ .Q(\gpio_configure[6][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9132_ (.D(_0361_),
+ .Q(\gpio_configure[6][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9133_ (.D(_0362_),
+ .Q(\gpio_configure[7][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9134_ (.D(_0363_),
+ .Q(\gpio_configure[7][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9135_ (.D(_0364_),
+ .Q(\gpio_configure[7][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9136_ (.D(_0365_),
+ .Q(\gpio_configure[7][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9137_ (.D(_0366_),
+ .Q(\gpio_configure[7][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9138_ (.D(_0367_),
+ .Q(\serial_data_staging_2[0] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9139_ (.D(_0368_),
+ .Q(\serial_data_staging_2[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9140_ (.D(_0369_),
+ .Q(\serial_data_staging_2[2] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9141_ (.D(_0370_),
+ .Q(\serial_data_staging_2[3] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9142_ (.D(_0371_),
+ .Q(\serial_data_staging_2[4] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9143_ (.D(_0372_),
+ .Q(\serial_data_staging_2[5] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9144_ (.D(_0373_),
+ .Q(\serial_data_staging_2[6] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9145_ (.D(_0374_),
+ .Q(\serial_data_staging_2[7] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9146_ (.D(_0375_),
+ .Q(\serial_data_staging_2[8] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9147_ (.D(_0376_),
+ .Q(\serial_data_staging_2[9] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9148_ (.D(_0377_),
+ .Q(\serial_data_staging_2[10] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9149_ (.D(_0378_),
+ .Q(\serial_data_staging_2[11] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9150_ (.D(_0379_),
+ .Q(\serial_data_staging_2[12] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9151_ (.D(_0380_),
+ .Q(\gpio_configure[7][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9152_ (.D(_0381_),
+ .Q(\gpio_configure[7][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9153_ (.D(_0382_),
+ .Q(\gpio_configure[7][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9154_ (.D(_0383_),
+ .Q(\gpio_configure[7][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9155_ (.D(_0384_),
+ .Q(\gpio_configure[7][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9156_ (.D(_0385_),
+ .Q(\gpio_configure[7][5] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9157_ (.D(_0386_),
+ .Q(\gpio_configure[7][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9158_ (.D(_0387_),
+ .Q(\gpio_configure[7][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9159_ (.D(_0388_),
+ .Q(\gpio_configure[8][8] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9160_ (.D(_0389_),
+ .Q(\gpio_configure[8][9] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9161_ (.D(_0390_),
+ .Q(\gpio_configure[8][10] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9162_ (.D(_0391_),
+ .Q(\gpio_configure[8][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9163_ (.D(_0392_),
+ .Q(\gpio_configure[8][12] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9164_ (.D(_0393_),
+ .Q(\serial_data_staging_1[0] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9165_ (.D(_0394_),
+ .Q(\serial_data_staging_1[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9166_ (.D(_0395_),
+ .Q(\serial_data_staging_1[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9167_ (.D(_0396_),
+ .Q(\serial_data_staging_1[3] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9168_ (.D(_0397_),
+ .Q(\serial_data_staging_1[4] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9169_ (.D(_0398_),
+ .Q(\serial_data_staging_1[5] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9170_ (.D(_0399_),
+ .Q(\serial_data_staging_1[6] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9171_ (.D(_0400_),
+ .Q(\serial_data_staging_1[7] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9172_ (.D(_0401_),
+ .Q(\serial_data_staging_1[8] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9173_ (.D(_0402_),
+ .Q(\serial_data_staging_1[9] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9174_ (.D(_0403_),
+ .Q(\serial_data_staging_1[10] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9175_ (.D(_0404_),
+ .Q(\serial_data_staging_1[11] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9176_ (.D(_0405_),
+ .Q(\serial_data_staging_1[12] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9177_ (.D(_0406_),
+ .Q(\gpio_configure[8][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9178_ (.D(_0407_),
+ .Q(\gpio_configure[8][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9179_ (.D(_0408_),
+ .Q(\gpio_configure[8][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9180_ (.D(_0409_),
+ .Q(\gpio_configure[8][3] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9181_ (.D(_0410_),
+ .Q(\gpio_configure[8][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9182_ (.D(_0411_),
+ .Q(\gpio_configure[8][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9183_ (.D(_0412_),
+ .Q(\gpio_configure[8][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9184_ (.D(_0413_),
+ .Q(\gpio_configure[8][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9185_ (.D(_0414_),
+ .Q(\gpio_configure[9][8] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9186_ (.D(_0415_),
+ .Q(\gpio_configure[9][9] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9187_ (.D(_0416_),
+ .Q(\gpio_configure[9][10] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9188_ (.D(_0417_),
+ .Q(\gpio_configure[9][11] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9189_ (.D(_0418_),
+ .Q(\gpio_configure[9][12] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9190_ (.D(_0419_),
+ .Q(\gpio_configure[9][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9191_ (.D(_0420_),
+ .Q(\gpio_configure[9][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9192_ (.D(_0421_),
+ .Q(\gpio_configure[9][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9193_ (.D(_0422_),
+ .Q(\gpio_configure[9][3] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9194_ (.D(_0423_),
+ .Q(\gpio_configure[9][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9195_ (.D(_0424_),
+ .Q(\gpio_configure[9][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9196_ (.D(_0425_),
+ .Q(\gpio_configure[9][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9197_ (.D(_0426_),
+ .Q(\gpio_configure[9][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9198_ (.D(_0427_),
+ .Q(\gpio_configure[10][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9199_ (.D(_0428_),
+ .Q(\gpio_configure[10][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9200_ (.D(_0429_),
+ .Q(\gpio_configure[10][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9201_ (.D(_0430_),
+ .Q(\gpio_configure[10][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9202_ (.D(_0431_),
+ .Q(\gpio_configure[10][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9203_ (.D(_0432_),
+ .Q(serial_busy),
+ .RESET_B(net376),
+ .CLK(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9204_ (.D(_0433_),
+ .Q(\gpio_configure[10][0] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9205_ (.D(_0434_),
+ .Q(\gpio_configure[10][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9206_ (.D(_0435_),
+ .Q(\gpio_configure[10][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9207_ (.D(_0436_),
+ .Q(\gpio_configure[10][3] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9208_ (.D(_0437_),
+ .Q(\gpio_configure[10][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9209_ (.D(_0438_),
+ .Q(\gpio_configure[10][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9210_ (.D(_0439_),
+ .Q(\gpio_configure[10][6] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9211_ (.D(_0440_),
+ .Q(\gpio_configure[10][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9212_ (.D(_0441_),
+ .Q(\gpio_configure[11][8] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9213_ (.D(_0442_),
+ .Q(\gpio_configure[11][9] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9214_ (.D(_0443_),
+ .Q(\gpio_configure[11][10] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9215_ (.D(_0444_),
+ .Q(\gpio_configure[11][11] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9216_ (.D(_0445_),
+ .Q(\gpio_configure[11][12] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9217_ (.D(_0446_),
+ .Q(serial_load_pre),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9218_ (.D(_0447_),
+ .Q(\gpio_configure[11][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9219_ (.D(_0448_),
+ .Q(\gpio_configure[11][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9220_ (.D(_0449_),
+ .Q(\gpio_configure[11][2] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9221_ (.D(_0450_),
+ .Q(\gpio_configure[11][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9222_ (.D(_0451_),
+ .Q(\gpio_configure[11][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9223_ (.D(_0452_),
+ .Q(\gpio_configure[11][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9224_ (.D(_0453_),
+ .Q(\gpio_configure[11][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9225_ (.D(_0454_),
+ .Q(\gpio_configure[11][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9226_ (.D(_0455_),
+ .Q(\gpio_configure[12][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9227_ (.D(_0456_),
+ .Q(\gpio_configure[12][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9228_ (.D(_0457_),
+ .Q(\gpio_configure[12][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9229_ (.D(_0458_),
+ .Q(\gpio_configure[12][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9230_ (.D(_0459_),
+ .Q(\gpio_configure[12][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9231_ (.D(_0460_),
+ .Q(\gpio_configure[12][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9232_ (.D(_0461_),
+ .Q(\gpio_configure[12][1] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9233_ (.D(_0462_),
+ .Q(\gpio_configure[12][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9234_ (.D(_0463_),
+ .Q(\gpio_configure[12][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9235_ (.D(_0464_),
+ .Q(\gpio_configure[12][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9236_ (.D(_0465_),
+ .Q(\gpio_configure[12][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9237_ (.D(_0466_),
+ .Q(\gpio_configure[12][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9238_ (.D(_0467_),
+ .Q(\gpio_configure[12][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9239_ (.D(_0468_),
+ .Q(serial_clock_pre),
+ .RESET_B(net377),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9240_ (.D(_0469_),
+ .Q(\gpio_configure[13][8] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9241_ (.D(_0470_),
+ .Q(\gpio_configure[13][9] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9242_ (.D(_0471_),
+ .Q(\gpio_configure[13][10] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9243_ (.D(_0472_),
+ .Q(\gpio_configure[13][11] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9244_ (.D(_0473_),
+ .Q(\gpio_configure[13][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_2 _9245_ (.D(_0474_),
+ .Q(\pad_count_2[0] ),
+ .SET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_2 _9246_ (.D(_0475_),
+ .Q(\pad_count_2[1] ),
+ .SET_B(net370),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9247_ (.D(_0476_),
+ .Q(\pad_count_2[2] ),
+ .RESET_B(net370),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9248_ (.D(_0477_),
+ .Q(\pad_count_2[3] ),
+ .RESET_B(net370),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9249_ (.D(_0478_),
+ .Q(\pad_count_2[4] ),
+ .SET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9250_ (.D(_0479_),
+ .Q(\pad_count_2[5] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9251_ (.D(_0480_),
+ .Q(\pad_count_1[0] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9252_ (.D(_0481_),
+ .Q(\pad_count_1[1] ),
+ .SET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9253_ (.D(_0482_),
+ .Q(\pad_count_1[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9254_ (.D(_0483_),
+ .Q(\pad_count_1[3] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_4 _9255_ (.D(_0484_),
+ .Q(\pad_count_1[4] ),
+ .SET_B(net370),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9256_ (.D(_0485_),
+ .Q(\gpio_configure[13][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9257_ (.D(_0486_),
+ .Q(\gpio_configure[13][1] ),
+ .SET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9258_ (.D(_0487_),
+ .Q(\gpio_configure[13][2] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9259_ (.D(_0488_),
+ .Q(\gpio_configure[13][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9260_ (.D(_0489_),
+ .Q(\gpio_configure[13][4] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9261_ (.D(_0490_),
+ .Q(\gpio_configure[13][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9262_ (.D(_0491_),
+ .Q(\gpio_configure[13][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9263_ (.D(_0492_),
+ .Q(\gpio_configure[13][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9264_ (.D(_0493_),
+ .Q(\gpio_configure[14][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9265_ (.D(_0494_),
+ .Q(\gpio_configure[14][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9266_ (.D(_0495_),
+ .Q(\gpio_configure[14][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9267_ (.D(_0496_),
+ .Q(\gpio_configure[14][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9268_ (.D(_0497_),
+ .Q(\gpio_configure[14][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9269_ (.D(_0498_),
+ .Q(\gpio_configure[14][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9270_ (.D(_0499_),
+ .Q(\gpio_configure[14][1] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9271_ (.D(_0500_),
+ .Q(\gpio_configure[14][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9272_ (.D(_0501_),
+ .Q(\gpio_configure[14][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9273_ (.D(_0502_),
+ .Q(\gpio_configure[14][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9274_ (.D(_0503_),
+ .Q(\gpio_configure[14][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9275_ (.D(_0504_),
+ .Q(\gpio_configure[14][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9276_ (.D(_0505_),
+ .Q(\gpio_configure[14][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9277_ (.D(_0506_),
+ .Q(\xfer_count[0] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9278_ (.D(_0507_),
+ .Q(\xfer_count[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9279_ (.D(_0508_),
+ .Q(\xfer_count[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9280_ (.D(_0509_),
+ .Q(\xfer_count[3] ),
+ .RESET_B(net377),
+ .CLK(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9281_ (.D(_0510_),
+ .Q(\gpio_configure[15][8] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9282_ (.D(_0511_),
+ .Q(\gpio_configure[15][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9283_ (.D(_0512_),
+ .Q(\gpio_configure[15][10] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9284_ (.D(_0513_),
+ .Q(\gpio_configure[15][11] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9285_ (.D(_0514_),
+ .Q(\gpio_configure[15][12] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9286_ (.D(_0515_),
+ .Q(\gpio_configure[37][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9287_ (.D(_0516_),
+ .Q(\gpio_configure[37][1] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9288_ (.D(_0517_),
+ .Q(\gpio_configure[37][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9289_ (.D(_0518_),
+ .Q(\gpio_configure[37][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9290_ (.D(_0519_),
+ .Q(\gpio_configure[37][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9291_ (.D(_0520_),
+ .Q(\gpio_configure[37][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9292_ (.D(_0521_),
+ .Q(\gpio_configure[37][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9293_ (.D(_0522_),
+ .Q(\gpio_configure[37][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9294_ (.D(_0523_),
+ .Q(\gpio_configure[15][0] ),
+ .SET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9295_ (.D(_0524_),
+ .Q(\gpio_configure[15][1] ),
+ .SET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9296_ (.D(_0525_),
+ .Q(\gpio_configure[15][2] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9297_ (.D(_0526_),
+ .Q(\gpio_configure[15][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9298_ (.D(_0527_),
+ .Q(\gpio_configure[15][4] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9299_ (.D(_0528_),
+ .Q(\gpio_configure[15][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9300_ (.D(_0529_),
+ .Q(\gpio_configure[15][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9301_ (.D(_0530_),
+ .Q(\gpio_configure[15][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9302_ (.D(_0531_),
+ .Q(\gpio_configure[37][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9303_ (.D(_0532_),
+ .Q(\gpio_configure[37][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9304_ (.D(_0533_),
+ .Q(\gpio_configure[37][10] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9305_ (.D(_0534_),
+ .Q(\gpio_configure[37][11] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9306_ (.D(_0535_),
+ .Q(\gpio_configure[37][12] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9307_ (.D(_0536_),
+ .Q(\gpio_configure[16][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9308_ (.D(_0537_),
+ .Q(\gpio_configure[16][9] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9309_ (.D(_0538_),
+ .Q(\gpio_configure[16][10] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9310_ (.D(_0539_),
+ .Q(\gpio_configure[16][11] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9311_ (.D(_0540_),
+ .Q(\gpio_configure[16][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9312_ (.D(_0541_),
+ .Q(\gpio_configure[36][0] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9313_ (.D(_0542_),
+ .Q(\gpio_configure[36][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9314_ (.D(_0543_),
+ .Q(\gpio_configure[36][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9315_ (.D(_0544_),
+ .Q(\gpio_configure[36][3] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9316_ (.D(_0545_),
+ .Q(\gpio_configure[36][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9317_ (.D(_0546_),
+ .Q(\gpio_configure[36][5] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9318_ (.D(_0547_),
+ .Q(\gpio_configure[36][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9319_ (.D(_0548_),
+ .Q(\gpio_configure[36][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9320_ (.D(_0549_),
+ .Q(\gpio_configure[16][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9321_ (.D(_0550_),
+ .Q(\gpio_configure[16][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9322_ (.D(_0551_),
+ .Q(\gpio_configure[16][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9323_ (.D(_0552_),
+ .Q(\gpio_configure[16][3] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9324_ (.D(_0553_),
+ .Q(\gpio_configure[16][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9325_ (.D(_0554_),
+ .Q(\gpio_configure[16][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9326_ (.D(_0555_),
+ .Q(\gpio_configure[16][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9327_ (.D(_0556_),
+ .Q(\gpio_configure[16][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9328_ (.D(_0557_),
+ .Q(\gpio_configure[36][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_4_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9329_ (.D(_0558_),
+ .Q(\gpio_configure[36][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_2_0_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9330_ (.D(_0559_),
+ .Q(\gpio_configure[36][10] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9331_ (.D(_0560_),
+ .Q(\gpio_configure[36][11] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9332_ (.D(_0561_),
+ .Q(\gpio_configure[36][12] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9333_ (.D(_0562_),
+ .Q(\gpio_configure[17][8] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9334_ (.D(_0563_),
+ .Q(\gpio_configure[17][9] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9335_ (.D(_0564_),
+ .Q(\gpio_configure[17][10] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9336_ (.D(_0565_),
+ .Q(\gpio_configure[17][11] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9337_ (.D(_0566_),
+ .Q(\gpio_configure[17][12] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9338_ (.D(_0567_),
+ .Q(\gpio_configure[35][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9339_ (.D(_0568_),
+ .Q(\gpio_configure[35][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9340_ (.D(_0569_),
+ .Q(\gpio_configure[35][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9341_ (.D(_0570_),
+ .Q(\gpio_configure[35][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9342_ (.D(_0571_),
+ .Q(\gpio_configure[35][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9343_ (.D(_0572_),
+ .Q(\gpio_configure[35][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9344_ (.D(_0573_),
+ .Q(\gpio_configure[35][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9345_ (.D(_0574_),
+ .Q(\gpio_configure[35][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9346_ (.D(_0575_),
+ .Q(\gpio_configure[17][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9347_ (.D(_0576_),
+ .Q(\gpio_configure[17][1] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9348_ (.D(_0577_),
+ .Q(\gpio_configure[17][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9349_ (.D(_0578_),
+ .Q(\gpio_configure[17][3] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9350_ (.D(_0579_),
+ .Q(\gpio_configure[17][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9351_ (.D(_0580_),
+ .Q(\gpio_configure[17][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9352_ (.D(_0581_),
+ .Q(\gpio_configure[17][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9353_ (.D(_0582_),
+ .Q(\gpio_configure[17][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9354_ (.D(_0583_),
+ .Q(\gpio_configure[35][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9355_ (.D(_0584_),
+ .Q(\gpio_configure[35][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9356_ (.D(_0585_),
+ .Q(\gpio_configure[35][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9357_ (.D(_0586_),
+ .Q(\gpio_configure[35][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9358_ (.D(_0587_),
+ .Q(\gpio_configure[35][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9359_ (.D(_0588_),
+ .Q(\gpio_configure[18][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9360_ (.D(_0589_),
+ .Q(\gpio_configure[18][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9361_ (.D(_0590_),
+ .Q(\gpio_configure[18][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9362_ (.D(_0591_),
+ .Q(\gpio_configure[18][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9363_ (.D(_0592_),
+ .Q(\gpio_configure[18][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9364_ (.D(_0593_),
+ .Q(\gpio_configure[34][0] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9365_ (.D(_0594_),
+ .Q(\gpio_configure[34][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9366_ (.D(_0595_),
+ .Q(\gpio_configure[34][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9367_ (.D(_0596_),
+ .Q(\gpio_configure[34][3] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9368_ (.D(_0597_),
+ .Q(\gpio_configure[34][4] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9369_ (.D(_0598_),
+ .Q(\gpio_configure[34][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9370_ (.D(_0599_),
+ .Q(\gpio_configure[34][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9371_ (.D(_0600_),
+ .Q(\gpio_configure[34][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9372_ (.D(_0601_),
+ .Q(\gpio_configure[18][0] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9373_ (.D(_0602_),
+ .Q(\gpio_configure[18][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9374_ (.D(_0603_),
+ .Q(\gpio_configure[18][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9375_ (.D(_0604_),
+ .Q(\gpio_configure[18][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9376_ (.D(_0605_),
+ .Q(\gpio_configure[18][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9377_ (.D(_0606_),
+ .Q(\gpio_configure[18][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9378_ (.D(_0607_),
+ .Q(\gpio_configure[18][6] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9379_ (.D(_0608_),
+ .Q(\gpio_configure[18][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9380_ (.D(_0609_),
+ .Q(\gpio_configure[34][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_4_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9381_ (.D(_0610_),
+ .Q(\gpio_configure[34][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9382_ (.D(_0611_),
+ .Q(\gpio_configure[34][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9383_ (.D(_0612_),
+ .Q(\gpio_configure[34][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9384_ (.D(_0613_),
+ .Q(\gpio_configure[34][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9385_ (.D(_0614_),
+ .Q(\gpio_configure[19][8] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9386_ (.D(_0615_),
+ .Q(\gpio_configure[19][9] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9387_ (.D(_0616_),
+ .Q(\gpio_configure[19][10] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9388_ (.D(_0617_),
+ .Q(\gpio_configure[19][11] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9389_ (.D(_0618_),
+ .Q(\gpio_configure[19][12] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9390_ (.D(_0619_),
+ .Q(\gpio_configure[33][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9391_ (.D(_0620_),
+ .Q(\gpio_configure[33][1] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9392_ (.D(_0621_),
+ .Q(\gpio_configure[33][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9393_ (.D(_0622_),
+ .Q(\gpio_configure[33][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9394_ (.D(_0623_),
+ .Q(\gpio_configure[33][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9395_ (.D(_0624_),
+ .Q(\gpio_configure[33][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9396_ (.D(_0625_),
+ .Q(\gpio_configure[33][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9397_ (.D(_0626_),
+ .Q(\gpio_configure[33][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9398_ (.D(_0627_),
+ .Q(\gpio_configure[19][0] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9399_ (.D(_0628_),
+ .Q(\gpio_configure[19][1] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9400_ (.D(_0629_),
+ .Q(\gpio_configure[19][2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9401_ (.D(_0630_),
+ .Q(\gpio_configure[19][3] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9402_ (.D(_0631_),
+ .Q(\gpio_configure[19][4] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9403_ (.D(_0632_),
+ .Q(\gpio_configure[19][5] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9404_ (.D(_0633_),
+ .Q(\gpio_configure[19][6] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9405_ (.D(_0634_),
+ .Q(\gpio_configure[19][7] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9406_ (.D(_0635_),
+ .Q(\gpio_configure[33][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9407_ (.D(_0636_),
+ .Q(\gpio_configure[33][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9408_ (.D(_0637_),
+ .Q(\gpio_configure[33][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9409_ (.D(_0638_),
+ .Q(\gpio_configure[33][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9410_ (.D(_0639_),
+ .Q(\gpio_configure[33][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9411_ (.D(_0640_),
+ .Q(\gpio_configure[20][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9412_ (.D(_0641_),
+ .Q(\gpio_configure[20][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9413_ (.D(_0642_),
+ .Q(\gpio_configure[20][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9414_ (.D(_0643_),
+ .Q(\gpio_configure[20][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9415_ (.D(_0644_),
+ .Q(\gpio_configure[20][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9416_ (.D(_0645_),
+ .Q(\gpio_configure[32][0] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9417_ (.D(_0646_),
+ .Q(\gpio_configure[32][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9418_ (.D(_0647_),
+ .Q(\gpio_configure[32][2] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9419_ (.D(_0648_),
+ .Q(\gpio_configure[32][3] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9420_ (.D(_0649_),
+ .Q(\gpio_configure[32][4] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9421_ (.D(_0650_),
+ .Q(\gpio_configure[32][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9422_ (.D(_0651_),
+ .Q(\gpio_configure[32][6] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9423_ (.D(_0652_),
+ .Q(\gpio_configure[32][7] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9424_ (.D(_0653_),
+ .Q(\gpio_configure[20][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9425_ (.D(_0654_),
+ .Q(\gpio_configure[20][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9426_ (.D(_0655_),
+ .Q(\gpio_configure[20][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9427_ (.D(_0656_),
+ .Q(\gpio_configure[20][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9428_ (.D(_0657_),
+ .Q(\gpio_configure[20][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9429_ (.D(_0658_),
+ .Q(\gpio_configure[20][5] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9430_ (.D(_0659_),
+ .Q(\gpio_configure[20][6] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9431_ (.D(_0660_),
+ .Q(\gpio_configure[20][7] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9432_ (.D(_0661_),
+ .Q(\gpio_configure[32][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9433_ (.D(_0662_),
+ .Q(\gpio_configure[32][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9434_ (.D(_0663_),
+ .Q(\gpio_configure[32][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9435_ (.D(_0664_),
+ .Q(\gpio_configure[32][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9436_ (.D(_0665_),
+ .Q(\gpio_configure[32][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9437_ (.D(_0666_),
+ .Q(\gpio_configure[21][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9438_ (.D(_0667_),
+ .Q(\gpio_configure[21][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9439_ (.D(_0668_),
+ .Q(\gpio_configure[21][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9440_ (.D(_0669_),
+ .Q(\gpio_configure[21][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9441_ (.D(_0670_),
+ .Q(\gpio_configure[21][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9442_ (.D(_0671_),
+ .Q(\gpio_configure[31][0] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9443_ (.D(_0672_),
+ .Q(\gpio_configure[31][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9444_ (.D(_0673_),
+ .Q(\gpio_configure[31][2] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9445_ (.D(_0674_),
+ .Q(\gpio_configure[31][3] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9446_ (.D(_0675_),
+ .Q(\gpio_configure[31][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9447_ (.D(_0676_),
+ .Q(\gpio_configure[31][5] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9448_ (.D(_0677_),
+ .Q(\gpio_configure[31][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9449_ (.D(_0678_),
+ .Q(\gpio_configure[31][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9450_ (.D(_0679_),
+ .Q(\gpio_configure[21][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9451_ (.D(_0680_),
+ .Q(\gpio_configure[21][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9452_ (.D(_0681_),
+ .Q(\gpio_configure[21][2] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9453_ (.D(_0682_),
+ .Q(\gpio_configure[21][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9454_ (.D(_0683_),
+ .Q(\gpio_configure[21][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9455_ (.D(_0684_),
+ .Q(\gpio_configure[21][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9456_ (.D(_0685_),
+ .Q(\gpio_configure[21][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9457_ (.D(_0686_),
+ .Q(\gpio_configure[21][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9458_ (.D(_0687_),
+ .Q(\gpio_configure[31][8] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9459_ (.D(_0688_),
+ .Q(\gpio_configure[31][9] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9460_ (.D(_0689_),
+ .Q(\gpio_configure[31][10] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9461_ (.D(_0690_),
+ .Q(\gpio_configure[31][11] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9462_ (.D(_0691_),
+ .Q(\gpio_configure[31][12] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9463_ (.D(_0692_),
+ .Q(\gpio_configure[22][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9464_ (.D(_0693_),
+ .Q(\gpio_configure[22][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9465_ (.D(_0694_),
+ .Q(\gpio_configure[22][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9466_ (.D(_0695_),
+ .Q(\gpio_configure[22][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9467_ (.D(_0696_),
+ .Q(\gpio_configure[22][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9468_ (.D(_0697_),
+ .Q(\gpio_configure[30][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9469_ (.D(_0698_),
+ .Q(\gpio_configure[30][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9470_ (.D(_0699_),
+ .Q(\gpio_configure[30][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9471_ (.D(_0700_),
+ .Q(\gpio_configure[30][3] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9472_ (.D(_0701_),
+ .Q(\gpio_configure[30][4] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9473_ (.D(_0702_),
+ .Q(\gpio_configure[30][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9474_ (.D(_0703_),
+ .Q(\gpio_configure[30][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9475_ (.D(_0704_),
+ .Q(\gpio_configure[30][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9476_ (.D(_0705_),
+ .Q(\gpio_configure[22][0] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9477_ (.D(_0706_),
+ .Q(\gpio_configure[22][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9478_ (.D(_0707_),
+ .Q(\gpio_configure[22][2] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9479_ (.D(_0708_),
+ .Q(\gpio_configure[22][3] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9480_ (.D(_0709_),
+ .Q(\gpio_configure[22][4] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9481_ (.D(_0710_),
+ .Q(\gpio_configure[22][5] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9482_ (.D(_0711_),
+ .Q(\gpio_configure[22][6] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9483_ (.D(_0712_),
+ .Q(\gpio_configure[22][7] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9484_ (.D(_0713_),
+ .Q(\gpio_configure[30][8] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9485_ (.D(_0714_),
+ .Q(\gpio_configure[30][9] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9486_ (.D(_0715_),
+ .Q(\gpio_configure[30][10] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9487_ (.D(_0716_),
+ .Q(\gpio_configure[30][11] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9488_ (.D(_0717_),
+ .Q(\gpio_configure[30][12] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9489_ (.D(_0718_),
+ .Q(\gpio_configure[23][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9490_ (.D(_0719_),
+ .Q(\gpio_configure[23][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9491_ (.D(_0720_),
+ .Q(\gpio_configure[23][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9492_ (.D(_0721_),
+ .Q(\gpio_configure[23][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9493_ (.D(_0722_),
+ .Q(\gpio_configure[23][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9494_ (.D(_0723_),
+ .Q(\gpio_configure[29][0] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9495_ (.D(_0724_),
+ .Q(\gpio_configure[29][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9496_ (.D(_0725_),
+ .Q(\gpio_configure[29][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9497_ (.D(_0726_),
+ .Q(\gpio_configure[29][3] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9498_ (.D(_0727_),
+ .Q(\gpio_configure[29][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9499_ (.D(_0728_),
+ .Q(\gpio_configure[29][5] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9500_ (.D(_0729_),
+ .Q(\gpio_configure[29][6] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9501_ (.D(_0730_),
+ .Q(\gpio_configure[29][7] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9502_ (.D(_0731_),
+ .Q(\gpio_configure[23][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9503_ (.D(_0732_),
+ .Q(\gpio_configure[23][1] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9504_ (.D(_0733_),
+ .Q(\gpio_configure[23][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9505_ (.D(_0734_),
+ .Q(\gpio_configure[23][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9506_ (.D(_0735_),
+ .Q(\gpio_configure[23][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9507_ (.D(_0736_),
+ .Q(\gpio_configure[23][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9508_ (.D(_0737_),
+ .Q(\gpio_configure[23][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9509_ (.D(_0738_),
+ .Q(\gpio_configure[23][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9510_ (.D(_0739_),
+ .Q(\gpio_configure[29][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9511_ (.D(_0740_),
+ .Q(\gpio_configure[29][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9512_ (.D(_0741_),
+ .Q(\gpio_configure[29][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9513_ (.D(_0742_),
+ .Q(\gpio_configure[29][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9514_ (.D(_0743_),
+ .Q(\gpio_configure[29][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9515_ (.D(_0744_),
+ .Q(\gpio_configure[24][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9516_ (.D(_0745_),
+ .Q(\gpio_configure[24][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9517_ (.D(_0746_),
+ .Q(\gpio_configure[24][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9518_ (.D(_0747_),
+ .Q(\gpio_configure[24][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9519_ (.D(_0748_),
+ .Q(\gpio_configure[24][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9520_ (.D(_0749_),
+ .Q(\gpio_configure[28][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9521_ (.D(_0750_),
+ .Q(\gpio_configure[28][1] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9522_ (.D(_0751_),
+ .Q(\gpio_configure[28][2] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9523_ (.D(_0752_),
+ .Q(\gpio_configure[28][3] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9524_ (.D(_0753_),
+ .Q(\gpio_configure[28][4] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9525_ (.D(_0754_),
+ .Q(\gpio_configure[28][5] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9526_ (.D(_0755_),
+ .Q(\gpio_configure[28][6] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9527_ (.D(_0756_),
+ .Q(\gpio_configure[28][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9528_ (.D(_0757_),
+ .Q(\gpio_configure[24][0] ),
+ .SET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9529_ (.D(_0758_),
+ .Q(\gpio_configure[24][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9530_ (.D(_0759_),
+ .Q(\gpio_configure[24][2] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9531_ (.D(_0760_),
+ .Q(\gpio_configure[24][3] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9532_ (.D(_0761_),
+ .Q(\gpio_configure[24][4] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9533_ (.D(_0762_),
+ .Q(\gpio_configure[24][5] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9534_ (.D(_0763_),
+ .Q(\gpio_configure[24][6] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9535_ (.D(_0764_),
+ .Q(\gpio_configure[24][7] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9536_ (.D(_0765_),
+ .Q(\gpio_configure[28][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9537_ (.D(_0766_),
+ .Q(\gpio_configure[28][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9538_ (.D(_0767_),
+ .Q(\gpio_configure[28][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9539_ (.D(_0768_),
+ .Q(\gpio_configure[28][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9540_ (.D(_0769_),
+ .Q(\gpio_configure[28][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9541_ (.D(_0770_),
+ .Q(\gpio_configure[25][8] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9542_ (.D(_0771_),
+ .Q(\gpio_configure[25][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9543_ (.D(_0772_),
+ .Q(\gpio_configure[25][10] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9544_ (.D(_0773_),
+ .Q(\gpio_configure[25][11] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9545_ (.D(_0774_),
+ .Q(\gpio_configure[25][12] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9546_ (.D(_0775_),
+ .Q(\gpio_configure[27][0] ),
+ .SET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9547_ (.D(_0776_),
+ .Q(\gpio_configure[27][1] ),
+ .SET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9548_ (.D(_0777_),
+ .Q(\gpio_configure[27][2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9549_ (.D(_0778_),
+ .Q(\gpio_configure[27][3] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9550_ (.D(_0779_),
+ .Q(\gpio_configure[27][4] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9551_ (.D(_0780_),
+ .Q(\gpio_configure[27][5] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9552_ (.D(_0781_),
+ .Q(\gpio_configure[27][6] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9553_ (.D(_0782_),
+ .Q(\gpio_configure[27][7] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9554_ (.D(_0783_),
+ .Q(\gpio_configure[27][8] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9555_ (.D(_0784_),
+ .Q(\gpio_configure[27][9] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9556_ (.D(_0785_),
+ .Q(\gpio_configure[27][10] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9557_ (.D(_0786_),
+ .Q(\gpio_configure[27][11] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9558_ (.D(_0787_),
+ .Q(\gpio_configure[27][12] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9559_ (.D(_0788_),
+ .Q(irq_1_inputsrc),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9560_ (.D(_0789_),
+ .Q(irq_2_inputsrc),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9561_ (.D(_0790_),
+ .Q(\mgmt_gpio_data[16] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9562_ (.D(_0791_),
+ .Q(\mgmt_gpio_data[17] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9563_ (.D(_0792_),
+ .Q(\mgmt_gpio_data[18] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9564_ (.D(_0793_),
+ .Q(\mgmt_gpio_data[19] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9565_ (.D(_0794_),
+ .Q(\mgmt_gpio_data[20] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9566_ (.D(_0795_),
+ .Q(\mgmt_gpio_data[21] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9567_ (.D(_0796_),
+ .Q(\mgmt_gpio_data[22] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9568_ (.D(_0797_),
+ .Q(\mgmt_gpio_data[23] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9569_ (.D(_0798_),
+ .Q(\hkspi.rdstb ),
+ .RESET_B(_0235_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9570_ (.D(_0799_),
+ .Q(\mgmt_gpio_data[8] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9571_ (.D(_0800_),
+ .Q(\mgmt_gpio_data[9] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9572_ (.D(_0801_),
+ .Q(\mgmt_gpio_data[10] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9573_ (.D(_0802_),
+ .Q(\mgmt_gpio_data[11] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9574_ (.D(_0803_),
+ .Q(\mgmt_gpio_data[12] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9575_ (.D(_0804_),
+ .Q(\mgmt_gpio_data[13] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9576_ (.D(_0805_),
+ .Q(\mgmt_gpio_data[14] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9577_ (.D(_0806_),
+ .Q(\mgmt_gpio_data[15] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9578_ (.D(_0807_),
+ .Q(\mgmt_gpio_data[0] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9579_ (.D(_0808_),
+ .Q(\mgmt_gpio_data[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9580_ (.D(_0809_),
+ .Q(\mgmt_gpio_data[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_34_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9581_ (.D(_0810_),
+ .Q(\mgmt_gpio_data[3] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_34_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9582_ (.D(_0811_),
+ .Q(\mgmt_gpio_data[4] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9583_ (.D(_0812_),
+ .Q(\mgmt_gpio_data[5] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9584_ (.D(_0813_),
+ .Q(\mgmt_gpio_data[6] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9585_ (.D(_0814_),
+ .Q(\mgmt_gpio_data[7] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9586_ (.D(_0815_),
+ .Q(\hkspi.pass_thru_mgmt ),
+ .RESET_B(_0236_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9587_ (.D(_0816_),
+ .Q(wbbd_busy),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9588_ (.D(_0817_),
+ .Q(\mgmt_gpio_data[32] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9589_ (.D(_0818_),
+ .Q(\mgmt_gpio_data[33] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9590_ (.D(_0819_),
+ .Q(\mgmt_gpio_data[34] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9591_ (.D(_0820_),
+ .Q(\mgmt_gpio_data[35] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9592_ (.D(_0821_),
+ .Q(\mgmt_gpio_data[36] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9593_ (.D(_0822_),
+ .Q(\mgmt_gpio_data[37] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9594_ (.D(_0823_),
+ .Q(\mgmt_gpio_data[24] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9595_ (.D(_0824_),
+ .Q(\mgmt_gpio_data[25] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9596_ (.D(_0825_),
+ .Q(\mgmt_gpio_data[26] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9597_ (.D(_0826_),
+ .Q(\mgmt_gpio_data[27] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9598_ (.D(_0827_),
+ .Q(\mgmt_gpio_data[28] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9599_ (.D(_0828_),
+ .Q(\mgmt_gpio_data[29] ),
+ .RESET_B(net372),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9600_ (.D(_0829_),
+ .Q(\mgmt_gpio_data[30] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9601_ (.D(_0830_),
+ .Q(\mgmt_gpio_data[31] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9602_ (.D(_0831_),
+ .Q(\mgmt_gpio_data_buf[16] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9603_ (.D(_0832_),
+ .Q(\mgmt_gpio_data_buf[17] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9604_ (.D(_0833_),
+ .Q(\mgmt_gpio_data_buf[18] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9605_ (.D(_0834_),
+ .Q(\mgmt_gpio_data_buf[19] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9606_ (.D(_0835_),
+ .Q(\mgmt_gpio_data_buf[20] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9607_ (.D(_0836_),
+ .Q(\mgmt_gpio_data_buf[21] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9608_ (.D(_0837_),
+ .Q(\mgmt_gpio_data_buf[22] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9609_ (.D(_0838_),
+ .Q(\mgmt_gpio_data_buf[23] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9610_ (.D(_0839_),
+ .Q(\mgmt_gpio_data_buf[8] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9611_ (.D(_0840_),
+ .Q(\mgmt_gpio_data_buf[9] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9612_ (.D(_0841_),
+ .Q(\mgmt_gpio_data_buf[10] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9613_ (.D(_0842_),
+ .Q(\mgmt_gpio_data_buf[11] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9614_ (.D(_0843_),
+ .Q(\mgmt_gpio_data_buf[12] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9615_ (.D(_0844_),
+ .Q(\mgmt_gpio_data_buf[13] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9616_ (.D(_0845_),
+ .Q(\mgmt_gpio_data_buf[14] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9617_ (.D(_0846_),
+ .Q(\mgmt_gpio_data_buf[15] ),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9618_ (.D(_0847_),
+ .Q(\mgmt_gpio_data_buf[0] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9619_ (.D(_0848_),
+ .Q(\mgmt_gpio_data_buf[1] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9620_ (.D(_0849_),
+ .Q(\mgmt_gpio_data_buf[2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_34_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9621_ (.D(_0850_),
+ .Q(\mgmt_gpio_data_buf[3] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9622_ (.D(_0851_),
+ .Q(\mgmt_gpio_data_buf[4] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9623_ (.D(_0852_),
+ .Q(\mgmt_gpio_data_buf[5] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9624_ (.D(_0853_),
+ .Q(\mgmt_gpio_data_buf[6] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9625_ (.D(_0854_),
+ .Q(\mgmt_gpio_data_buf[7] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9626_ (.D(_0855_),
+ .Q(\hkspi.pass_thru_mgmt_delay ),
+ .RESET_B(_0237_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9627_ (.D(_0856_),
+ .Q(\gpio_configure[0][8] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9628_ (.D(_0857_),
+ .Q(\gpio_configure[0][9] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9629_ (.D(_0858_),
+ .Q(\gpio_configure[0][10] ),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9630_ (.D(_0859_),
+ .Q(\gpio_configure[0][11] ),
+ .SET_B(net377),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9631_ (.D(_0860_),
+ .Q(\gpio_configure[0][12] ),
+ .SET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9632_ (.D(_0861_),
+ .Q(\gpio_configure[0][0] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9633_ (.D(_0862_),
+ .Q(\gpio_configure[0][1] ),
+ .SET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9634_ (.D(_0863_),
+ .Q(\gpio_configure[0][2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9635_ (.D(_0864_),
+ .Q(\gpio_configure[0][3] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9636_ (.D(_0865_),
+ .Q(\gpio_configure[0][4] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9637_ (.D(_0866_),
+ .Q(\gpio_configure[0][5] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9638_ (.D(_0867_),
+ .Q(\gpio_configure[0][6] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9639_ (.D(_0868_),
+ .Q(\gpio_configure[0][7] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9640_ (.D(_0869_),
+ .Q(wbbd_sck),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9641_ (.D(_0870_),
+ .Q(\gpio_configure[1][8] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9642_ (.D(_0871_),
+ .Q(\gpio_configure[1][9] ),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9643_ (.D(_0872_),
+ .Q(\gpio_configure[1][10] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9644_ (.D(_0873_),
+ .Q(\gpio_configure[1][11] ),
+ .SET_B(net375),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9645_ (.D(_0874_),
+ .Q(\gpio_configure[1][12] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9646_ (.D(_0875_),
+ .Q(\gpio_configure[1][0] ),
+ .SET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9647_ (.D(_0876_),
+ .Q(\gpio_configure[1][1] ),
+ .SET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9648_ (.D(_0877_),
+ .Q(\gpio_configure[1][2] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9649_ (.D(_0878_),
+ .Q(\gpio_configure[1][3] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9650_ (.D(_0879_),
+ .Q(\gpio_configure[1][4] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9651_ (.D(_0880_),
+ .Q(\gpio_configure[1][5] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9652_ (.D(_0881_),
+ .Q(\gpio_configure[1][6] ),
+ .RESET_B(net373),
+ .CLK(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9653_ (.D(_0882_),
+ .Q(\gpio_configure[1][7] ),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9654_ (.D(_0883_),
+ .Q(\gpio_configure[2][8] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9655_ (.D(_0884_),
+ .Q(\gpio_configure[2][9] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9656_ (.D(_0885_),
+ .Q(\gpio_configure[2][10] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9657_ (.D(_0886_),
+ .Q(\gpio_configure[2][11] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9658_ (.D(_0887_),
+ .Q(\gpio_configure[2][12] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9659_ (.D(_0888_),
+ .Q(\wbbd_data[0] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9660_ (.D(_0889_),
+ .Q(\wbbd_data[1] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9661_ (.D(_0890_),
+ .Q(\wbbd_data[2] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9662_ (.D(_0891_),
+ .Q(\wbbd_data[3] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9663_ (.D(_0892_),
+ .Q(\wbbd_data[4] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9664_ (.D(_0893_),
+ .Q(\wbbd_data[5] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9665_ (.D(_0894_),
+ .Q(\wbbd_data[6] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9666_ (.D(_0895_),
+ .Q(\wbbd_data[7] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9667_ (.D(_0896_),
+ .Q(\gpio_configure[2][0] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9668_ (.D(_0897_),
+ .Q(\gpio_configure[2][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9669_ (.D(_0898_),
+ .Q(\gpio_configure[2][2] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9670_ (.D(_0899_),
+ .Q(\gpio_configure[2][3] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9671_ (.D(_0900_),
+ .Q(\gpio_configure[2][4] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9672_ (.D(_0901_),
+ .Q(\gpio_configure[2][5] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9673_ (.D(_0902_),
+ .Q(\gpio_configure[2][6] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9674_ (.D(_0903_),
+ .Q(\gpio_configure[2][7] ),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9675_ (.D(_0904_),
+ .Q(\wbbd_addr[0] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9676_ (.D(_0905_),
+ .Q(\wbbd_addr[1] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9677_ (.D(_0906_),
+ .Q(\wbbd_addr[2] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9678_ (.D(_0907_),
+ .Q(\wbbd_addr[3] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9679_ (.D(_0908_),
+ .Q(\wbbd_addr[4] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9680_ (.D(_0909_),
+ .Q(\wbbd_addr[5] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9681_ (.D(_0910_),
+ .Q(\wbbd_addr[6] ),
+ .RESET_B(net196),
+ .CLK(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9682_ (.D(_0911_),
+ .Q(\hkspi.pass_thru_user ),
+ .RESET_B(_0238_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9683_ (.D(_0912_),
+ .Q(\gpio_configure[3][8] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9684_ (.D(_0913_),
+ .Q(\gpio_configure[3][9] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9685_ (.D(_0914_),
+ .Q(\gpio_configure[3][10] ),
+ .SET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9686_ (.D(_0915_),
+ .Q(\gpio_configure[3][11] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9687_ (.D(_0916_),
+ .Q(\gpio_configure[3][12] ),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9688_ (.D(_0917_),
+ .Q(\gpio_configure[5][0] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9689_ (.D(_0918_),
+ .Q(\gpio_configure[5][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9690_ (.D(_0919_),
+ .Q(\gpio_configure[5][2] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9691_ (.D(_0920_),
+ .Q(\gpio_configure[5][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9692_ (.D(_0921_),
+ .Q(\gpio_configure[5][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9693_ (.D(_0922_),
+ .Q(\gpio_configure[5][5] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9694_ (.D(_0923_),
+ .Q(\gpio_configure[5][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9695_ (.D(_0924_),
+ .Q(\gpio_configure[5][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9696_ (.D(_0925_),
+ .Q(\hkspi.writemode ),
+ .RESET_B(_0239_),
+ .CLK(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9697_ (.D(_0926_),
+ .Q(\hkspi.readmode ),
+ .RESET_B(_0240_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9698_ (.D(_0927_),
+ .Q(\hkspi.fixed[0] ),
+ .RESET_B(_0241_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9699_ (.D(_0928_),
+ .Q(\hkspi.fixed[1] ),
+ .RESET_B(_0242_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9700_ (.D(_0929_),
+ .Q(\hkspi.fixed[2] ),
+ .RESET_B(_0243_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9701_ (.D(_0930_),
+ .Q(\hkspi.odata[1] ),
+ .RESET_B(_0244_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9702_ (.D(_0931_),
+ .Q(\hkspi.odata[2] ),
+ .RESET_B(_0245_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9703_ (.D(_0932_),
+ .Q(\hkspi.odata[3] ),
+ .RESET_B(_0246_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9704_ (.D(_0933_),
+ .Q(\hkspi.odata[4] ),
+ .RESET_B(_0247_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9705_ (.D(_0934_),
+ .Q(\hkspi.odata[5] ),
+ .RESET_B(_0248_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9706_ (.D(_0935_),
+ .Q(\hkspi.odata[6] ),
+ .RESET_B(_0249_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9707_ (.D(_0936_),
+ .Q(\hkspi.odata[7] ),
+ .RESET_B(_0250_),
+ .CLK(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9708_ (.D(_0937_),
+ .Q(\hkspi.pre_pass_thru_mgmt ),
+ .RESET_B(_0251_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9709_ (.D(_0938_),
+ .Q(\hkspi.pre_pass_thru_user ),
+ .RESET_B(_0252_),
+ .CLK(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9710_ (.D(_0939_),
+ .Q(\hkspi.wrstb ),
+ .RESET_B(_0253_),
+ .CLK_N(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9711_ (.D(_0940_),
+ .Q(\hkspi.ldata[0] ),
+ .RESET_B(_0254_),
+ .CLK_N(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9712_ (.D(_0941_),
+ .Q(\hkspi.ldata[1] ),
+ .RESET_B(_0255_),
+ .CLK_N(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9713_ (.D(_0942_),
+ .Q(\hkspi.ldata[2] ),
+ .RESET_B(_0256_),
+ .CLK_N(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9714_ (.D(_0943_),
+ .Q(\hkspi.ldata[3] ),
+ .RESET_B(_0257_),
+ .CLK_N(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9715_ (.D(_0944_),
+ .Q(\hkspi.ldata[4] ),
+ .RESET_B(_0258_),
+ .CLK_N(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9716_ (.D(_0945_),
+ .Q(\hkspi.ldata[5] ),
+ .RESET_B(_0259_),
+ .CLK_N(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9717_ (.D(net394),
+ .Q(\hkspi.ldata[6] ),
+ .RESET_B(_0260_),
+ .CLK_N(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtn_1 _9718_ (.D(_0947_),
+ .Q(\hkspi.SDO ),
+ .RESET_B(_0261_),
+ .CLK_N(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9719_ (.D(_0948_),
+ .Q(net270),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9720_ (.D(_0949_),
+ .Q(net264),
+ .SET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9721_ (.D(_0950_),
+ .Q(net265),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9722_ (.D(_0951_),
+ .Q(net266),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9723_ (.D(_0952_),
+ .Q(net267),
+ .SET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9724_ (.D(_0953_),
+ .Q(net268),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9725_ (.D(_0954_),
+ .Q(net269),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9726_ (.D(_0955_),
+ .Q(net271),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9727_ (.D(_0956_),
+ .Q(net272),
+ .SET_B(net75),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9728_ (.D(_0957_),
+ .Q(net273),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9729_ (.D(_0958_),
+ .Q(net260),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_2 _9730_ (.D(_0959_),
+ .Q(net261),
+ .SET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9731_ (.D(_0960_),
+ .Q(net262),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9732_ (.D(_0961_),
+ .Q(net274),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9733_ (.D(_0962_),
+ .Q(net285),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9734_ (.D(_0963_),
+ .Q(net292),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9735_ (.D(_0964_),
+ .Q(net293),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9736_ (.D(_0965_),
+ .Q(net294),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9737_ (.D(_0966_),
+ .Q(net295),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9738_ (.D(_0967_),
+ .Q(net296),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9739_ (.D(_0968_),
+ .Q(net297),
+ .SET_B(net377),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9740_ (.D(_0969_),
+ .Q(net298),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9741_ (.D(_0970_),
+ .Q(net299),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9742_ (.D(_0971_),
+ .Q(net275),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9743_ (.D(_0972_),
+ .Q(net276),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9744_ (.D(_0973_),
+ .Q(net277),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9745_ (.D(_0974_),
+ .Q(net278),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9746_ (.D(_0975_),
+ .Q(net279),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9747_ (.D(_0976_),
+ .Q(net280),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9748_ (.D(_0977_),
+ .Q(net281),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9749_ (.D(_0978_),
+ .Q(net282),
+ .SET_B(net377),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9750_ (.D(_0979_),
+ .Q(net283),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9751_ (.D(_0980_),
+ .Q(net284),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9752_ (.D(_0981_),
+ .Q(net286),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9753_ (.D(_0982_),
+ .Q(net287),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9754_ (.D(_0983_),
+ .Q(net288),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9755_ (.D(_0984_),
+ .Q(net289),
+ .SET_B(net377),
+ .CLK(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9756_ (.D(_0985_),
+ .Q(net290),
+ .SET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9757_ (.D(_0986_),
+ .Q(net291),
+ .SET_B(net377),
+ .CLK(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9758_ (.D(_0987_),
+ .Q(net263),
+ .SET_B(net75),
+ .CLK(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9759_ (.D(_0988_),
+ .Q(wbbd_write),
+ .RESET_B(net196),
+ .CLK(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9760_ (.D(_0989_),
+ .Q(net324),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_2 _9761_ (.D(_0990_),
+ .Q(net325),
+ .SET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9762_ (.D(_0991_),
+ .Q(net316),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9763_ (.D(_0992_),
+ .Q(net317),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9764_ (.D(_0993_),
+ .Q(net318),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9765_ (.D(_0994_),
+ .Q(net319),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9766_ (.D(_0995_),
+ .Q(net320),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9767_ (.D(_0996_),
+ .Q(net321),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9768_ (.D(_0997_),
+ .Q(net322),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9769_ (.D(_0998_),
+ .Q(net323),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9770_ (.D(_0999_),
+ .Q(reset_reg),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9771_ (.D(_1000_),
+ .Q(net204),
+ .RESET_B(net375),
+ .CLK(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9772_ (.D(_1001_),
+ .Q(serial_bb_clock),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9773_ (.D(_1002_),
+ .Q(\gpio_configure[26][8] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9774_ (.D(_1003_),
+ .Q(\gpio_configure[26][9] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9775_ (.D(_1004_),
+ .Q(\gpio_configure[26][10] ),
+ .SET_B(net75),
+ .CLK(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9776_ (.D(_1005_),
+ .Q(\gpio_configure[26][11] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9777_ (.D(_1006_),
+ .Q(\gpio_configure[26][12] ),
+ .RESET_B(net75),
+ .CLK(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9778_ (.D(_1007_),
+ .Q(\gpio_configure[25][0] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfstp_1 _9779_ (.D(_1008_),
+ .Q(\gpio_configure[25][1] ),
+ .SET_B(net370),
+ .CLK(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9780_ (.D(_1009_),
+ .Q(\gpio_configure[25][2] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9781_ (.D(_1010_),
+ .Q(\gpio_configure[25][3] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9782_ (.D(_1011_),
+ .Q(\gpio_configure[25][4] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9783_ (.D(_1012_),
+ .Q(\gpio_configure[25][5] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9784_ (.D(_1013_),
+ .Q(\gpio_configure[25][6] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9785_ (.D(_1014_),
+ .Q(\gpio_configure[25][7] ),
+ .RESET_B(net370),
+ .CLK(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9786_ (.D(_1015_),
+ .Q(clk2_output_dest),
+ .RESET_B(net371),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_4 _9787_ (.D(_1016_),
+ .Q(serial_bb_enable),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_2 _9788_ (.D(_1017_),
+ .Q(clk1_output_dest),
+ .RESET_B(net369),
+ .CLK(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9789_ (.D(_1018_),
+ .Q(hkspi_disable),
+ .RESET_B(net374),
+ .CLK(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9790_ (.D(_1019_),
+ .Q(serial_bb_data_2),
+ .RESET_B(net377),
+ .CLK(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dfrtp_1 _9791_ (.D(_1020_),
+ .Q(serial_xfer),
+ .RESET_B(net376),
+ .CLK(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_csclk (.A(csclk),
+ .X(clknet_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 \clkbuf_0_mgmt_gpio_in[4] (.A(mgmt_gpio_in[4]),
+ .X(clknet_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_0_wb_clk_i (.A(wb_clk_i),
+ .X(clknet_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_csclk (.A(clknet_0_csclk),
+ .X(clknet_1_0_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_1_0_0_mgmt_gpio_in[4] (.A(clknet_0_mgmt_gpio_in[4]),
+ .X(clknet_1_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_0_wb_clk_i (.A(clknet_0_wb_clk_i),
+ .X(clknet_1_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_1_csclk (.A(clknet_1_0_0_csclk),
+ .X(clknet_1_0_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_1_0_1_mgmt_gpio_in[4] (.A(clknet_1_0_0_mgmt_gpio_in[4]),
+ .X(clknet_1_0_1_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_0_1_wb_clk_i (.A(clknet_1_0_0_wb_clk_i),
+ .X(clknet_1_0_1_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_csclk (.A(clknet_0_csclk),
+ .X(clknet_1_1_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_1_1_0_mgmt_gpio_in[4] (.A(clknet_0_mgmt_gpio_in[4]),
+ .X(clknet_1_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_0_wb_clk_i (.A(clknet_0_wb_clk_i),
+ .X(clknet_1_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_1_csclk (.A(clknet_1_1_0_csclk),
+ .X(clknet_1_1_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_1_1_1_mgmt_gpio_in[4] (.A(clknet_1_1_0_mgmt_gpio_in[4]),
+ .X(clknet_1_1_1_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_1_1_1_wb_clk_i (.A(clknet_1_1_0_wb_clk_i),
+ .X(clknet_1_1_1_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_0_0_csclk (.A(clknet_1_0_1_csclk),
+ .X(clknet_2_0_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_2_0_0_mgmt_gpio_in[4] (.A(clknet_1_0_1_mgmt_gpio_in[4]),
+ .X(clknet_2_0_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_0_0_wb_clk_i (.A(clknet_1_0_1_wb_clk_i),
+ .X(clknet_2_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_1_0_csclk (.A(clknet_1_0_1_csclk),
+ .X(clknet_2_1_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_2_1_0_mgmt_gpio_in[4] (.A(clknet_1_0_1_mgmt_gpio_in[4]),
+ .X(clknet_2_1_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_1_0_wb_clk_i (.A(clknet_1_0_1_wb_clk_i),
+ .X(clknet_2_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_2_0_csclk (.A(clknet_1_1_1_csclk),
+ .X(clknet_2_2_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_2_2_0_mgmt_gpio_in[4] (.A(clknet_1_1_1_mgmt_gpio_in[4]),
+ .X(clknet_2_2_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_2_0_wb_clk_i (.A(clknet_1_1_1_wb_clk_i),
+ .X(clknet_2_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_3_0_csclk (.A(clknet_1_1_1_csclk),
+ .X(clknet_2_3_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 \clkbuf_2_3_0_mgmt_gpio_in[4] (.A(clknet_1_1_1_mgmt_gpio_in[4]),
+ .X(clknet_2_3_0_mgmt_gpio_in[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_2_3_0_wb_clk_i (.A(clknet_1_1_1_wb_clk_i),
+ .X(clknet_2_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_0_0_wb_clk_i (.A(clknet_2_0_0_wb_clk_i),
+ .X(clknet_3_0_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_1_0_wb_clk_i (.A(clknet_2_0_0_wb_clk_i),
+ .X(clknet_3_1_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_2_0_wb_clk_i (.A(clknet_2_1_0_wb_clk_i),
+ .X(clknet_3_2_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_3_0_wb_clk_i (.A(clknet_2_1_0_wb_clk_i),
+ .X(clknet_3_3_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_4_0_wb_clk_i (.A(clknet_2_2_0_wb_clk_i),
+ .X(clknet_3_4_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_5_0_wb_clk_i (.A(clknet_2_2_0_wb_clk_i),
+ .X(clknet_3_5_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_6_0_wb_clk_i (.A(clknet_2_3_0_wb_clk_i),
+ .X(clknet_3_6_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 clkbuf_3_7_0_wb_clk_i (.A(clknet_2_3_0_wb_clk_i),
+ .X(clknet_3_7_0_wb_clk_i),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_0_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_10_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_10_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_11_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_11_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_12_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_12_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_13_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_13_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_14_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_14_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_15_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_15_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_16_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_16_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_17_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_17_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_18_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_18_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_19_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_19_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_1_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_1_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_20_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_20_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_21_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_21_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_22_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_22_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_23_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_23_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_24_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_24_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_25_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_25_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_26_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_26_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_27_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_27_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_28_csclk (.A(clknet_opt_6_0_csclk),
+ .X(clknet_leaf_28_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_29_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_leaf_29_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_2_csclk (.A(clknet_opt_1_0_csclk),
+ .X(clknet_leaf_2_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_30_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_30_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_31_csclk (.A(clknet_opt_2_0_csclk),
+ .X(clknet_leaf_31_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_32_csclk (.A(clknet_opt_3_0_csclk),
+ .X(clknet_leaf_32_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_33_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_33_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_34_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_34_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_35_csclk (.A(clknet_opt_4_0_csclk),
+ .X(clknet_leaf_35_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_36_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_36_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_37_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_37_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_38_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_38_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_39_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_39_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_3_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_3_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_40_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_40_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_41_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_leaf_41_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_43_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_43_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_44_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_44_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_45_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_45_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_46_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_46_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_47_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_47_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_48_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_48_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_49_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_49_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_4_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_4_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_50_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_50_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_51_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_leaf_51_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_5_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_5_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_6_csclk (.A(clknet_opt_5_0_csclk),
+ .X(clknet_leaf_6_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_7_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_7_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_8_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_8_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_leaf_9_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_leaf_9_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_1_0_csclk (.A(clknet_2_0_0_csclk),
+ .X(clknet_opt_1_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_2_0_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_opt_2_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_3_0_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_opt_3_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_4_0_csclk (.A(clknet_2_1_0_csclk),
+ .X(clknet_opt_4_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_5_0_csclk (.A(clknet_2_2_0_csclk),
+ .X(clknet_opt_5_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_16 clkbuf_opt_6_0_csclk (.A(clknet_2_3_0_csclk),
+ .X(clknet_opt_6_0_csclk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(\hkspi.ldata[5] ),
+ .X(net393),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkdlybuf4s25_1 hold2 (.A(_0946_),
+ .X(net394),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input1 (.A(debug_mode),
+ .X(net1),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input10 (.A(mask_rev_in[15]),
+ .X(net10),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input100 (.A(sram_ro_data[16]),
+ .X(net100),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input101 (.A(sram_ro_data[17]),
+ .X(net101),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input102 (.A(sram_ro_data[18]),
+ .X(net102),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input103 (.A(sram_ro_data[19]),
+ .X(net103),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input104 (.A(sram_ro_data[1]),
+ .X(net104),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input105 (.A(sram_ro_data[20]),
+ .X(net105),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input106 (.A(sram_ro_data[21]),
+ .X(net106),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input107 (.A(sram_ro_data[22]),
+ .X(net107),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input108 (.A(sram_ro_data[23]),
+ .X(net108),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input109 (.A(sram_ro_data[24]),
+ .X(net109),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input11 (.A(mask_rev_in[16]),
+ .X(net11),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input110 (.A(sram_ro_data[25]),
+ .X(net110),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input111 (.A(sram_ro_data[26]),
+ .X(net111),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input112 (.A(sram_ro_data[27]),
+ .X(net112),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input113 (.A(sram_ro_data[28]),
+ .X(net113),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input114 (.A(sram_ro_data[29]),
+ .X(net114),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input115 (.A(sram_ro_data[2]),
+ .X(net115),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input116 (.A(sram_ro_data[30]),
+ .X(net116),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input117 (.A(sram_ro_data[31]),
+ .X(net117),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input118 (.A(sram_ro_data[3]),
+ .X(net118),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input119 (.A(sram_ro_data[4]),
+ .X(net119),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input12 (.A(mask_rev_in[17]),
+ .X(net12),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input120 (.A(sram_ro_data[5]),
+ .X(net120),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input121 (.A(sram_ro_data[6]),
+ .X(net121),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input122 (.A(sram_ro_data[7]),
+ .X(net122),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input123 (.A(sram_ro_data[8]),
+ .X(net123),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input124 (.A(sram_ro_data[9]),
+ .X(net124),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input125 (.A(trap),
+ .X(net125),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input126 (.A(uart_enabled),
+ .X(net126),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input127 (.A(usr1_vcc_pwrgood),
+ .X(net127),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input128 (.A(usr1_vdd_pwrgood),
+ .X(net128),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input129 (.A(usr2_vcc_pwrgood),
+ .X(net129),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input13 (.A(mask_rev_in[18]),
+ .X(net13),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input130 (.A(usr2_vdd_pwrgood),
+ .X(net130),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input131 (.A(wb_adr_i[0]),
+ .X(net131),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input132 (.A(wb_adr_i[10]),
+ .X(net132),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input133 (.A(wb_adr_i[11]),
+ .X(net133),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input134 (.A(wb_adr_i[12]),
+ .X(net134),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input135 (.A(wb_adr_i[13]),
+ .X(net135),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input136 (.A(wb_adr_i[14]),
+ .X(net136),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input137 (.A(wb_adr_i[15]),
+ .X(net137),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input138 (.A(wb_adr_i[16]),
+ .X(net138),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input139 (.A(wb_adr_i[17]),
+ .X(net139),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input14 (.A(mask_rev_in[19]),
+ .X(net14),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input140 (.A(wb_adr_i[18]),
+ .X(net140),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input141 (.A(wb_adr_i[19]),
+ .X(net141),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input142 (.A(wb_adr_i[1]),
+ .X(net142),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input143 (.A(wb_adr_i[20]),
+ .X(net143),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input144 (.A(wb_adr_i[21]),
+ .X(net144),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input145 (.A(wb_adr_i[22]),
+ .X(net145),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input146 (.A(wb_adr_i[23]),
+ .X(net146),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input147 (.A(wb_adr_i[24]),
+ .X(net147),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input148 (.A(wb_adr_i[25]),
+ .X(net148),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input149 (.A(wb_adr_i[26]),
+ .X(net149),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input15 (.A(mask_rev_in[1]),
+ .X(net15),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input150 (.A(wb_adr_i[27]),
+ .X(net150),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input151 (.A(wb_adr_i[28]),
+ .X(net151),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input152 (.A(wb_adr_i[29]),
+ .X(net152),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input153 (.A(wb_adr_i[2]),
+ .X(net153),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input154 (.A(wb_adr_i[30]),
+ .X(net154),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input155 (.A(wb_adr_i[31]),
+ .X(net155),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input156 (.A(wb_adr_i[3]),
+ .X(net156),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input157 (.A(wb_adr_i[4]),
+ .X(net157),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input158 (.A(wb_adr_i[5]),
+ .X(net158),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input159 (.A(wb_adr_i[6]),
+ .X(net159),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input16 (.A(mask_rev_in[20]),
+ .X(net16),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input160 (.A(wb_adr_i[7]),
+ .X(net160),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input161 (.A(wb_adr_i[8]),
+ .X(net161),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input162 (.A(wb_adr_i[9]),
+ .X(net162),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input163 (.A(wb_cyc_i),
+ .X(net163),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input164 (.A(wb_dat_i[0]),
+ .X(net164),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input165 (.A(wb_dat_i[10]),
+ .X(net165),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input166 (.A(wb_dat_i[11]),
+ .X(net166),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input167 (.A(wb_dat_i[12]),
+ .X(net167),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input168 (.A(wb_dat_i[13]),
+ .X(net168),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input169 (.A(wb_dat_i[14]),
+ .X(net169),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input17 (.A(mask_rev_in[21]),
+ .X(net17),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input170 (.A(wb_dat_i[15]),
+ .X(net170),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input171 (.A(wb_dat_i[16]),
+ .X(net171),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input172 (.A(wb_dat_i[17]),
+ .X(net172),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input173 (.A(wb_dat_i[18]),
+ .X(net173),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input174 (.A(wb_dat_i[19]),
+ .X(net174),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input175 (.A(wb_dat_i[1]),
+ .X(net175),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input176 (.A(wb_dat_i[20]),
+ .X(net176),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input177 (.A(wb_dat_i[21]),
+ .X(net177),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input178 (.A(wb_dat_i[22]),
+ .X(net178),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input179 (.A(wb_dat_i[23]),
+ .X(net179),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input18 (.A(mask_rev_in[22]),
+ .X(net18),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input180 (.A(wb_dat_i[24]),
+ .X(net180),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input181 (.A(wb_dat_i[25]),
+ .X(net181),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input182 (.A(wb_dat_i[26]),
+ .X(net182),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input183 (.A(wb_dat_i[27]),
+ .X(net183),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input184 (.A(wb_dat_i[28]),
+ .X(net184),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input185 (.A(wb_dat_i[29]),
+ .X(net185),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input186 (.A(wb_dat_i[2]),
+ .X(net186),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input187 (.A(wb_dat_i[30]),
+ .X(net187),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input188 (.A(wb_dat_i[31]),
+ .X(net188),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input189 (.A(wb_dat_i[3]),
+ .X(net189),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input19 (.A(mask_rev_in[23]),
+ .X(net19),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input190 (.A(wb_dat_i[4]),
+ .X(net190),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input191 (.A(wb_dat_i[5]),
+ .X(net191),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input192 (.A(wb_dat_i[6]),
+ .X(net192),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input193 (.A(wb_dat_i[7]),
+ .X(net193),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input194 (.A(wb_dat_i[8]),
+ .X(net194),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input195 (.A(wb_dat_i[9]),
+ .X(net195),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 input196 (.A(wb_rstn_i),
+ .X(net196),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input197 (.A(wb_sel_i[0]),
+ .X(net197),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input198 (.A(wb_sel_i[1]),
+ .X(net198),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input199 (.A(wb_sel_i[2]),
+ .X(net199),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input2 (.A(debug_oeb),
+ .X(net2),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input20 (.A(mask_rev_in[24]),
+ .X(net20),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input200 (.A(wb_sel_i[3]),
+ .X(net200),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input201 (.A(wb_stb_i),
+ .X(net201),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 input202 (.A(wb_we_i),
+ .X(net202),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input21 (.A(mask_rev_in[25]),
+ .X(net21),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input22 (.A(mask_rev_in[26]),
+ .X(net22),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input23 (.A(mask_rev_in[27]),
+ .X(net23),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input24 (.A(mask_rev_in[28]),
+ .X(net24),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input25 (.A(mask_rev_in[29]),
+ .X(net25),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input26 (.A(mask_rev_in[2]),
+ .X(net26),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input27 (.A(mask_rev_in[30]),
+ .X(net27),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input28 (.A(mask_rev_in[31]),
+ .X(net28),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input29 (.A(mask_rev_in[3]),
+ .X(net29),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input3 (.A(debug_out),
+ .X(net3),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input30 (.A(mask_rev_in[4]),
+ .X(net30),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input31 (.A(mask_rev_in[5]),
+ .X(net31),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input32 (.A(mask_rev_in[6]),
+ .X(net32),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input33 (.A(mask_rev_in[7]),
+ .X(net33),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input34 (.A(mask_rev_in[8]),
+ .X(net34),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input35 (.A(mask_rev_in[9]),
+ .X(net35),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_8 input36 (.A(mgmt_gpio_in[0]),
+ .X(net36),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input37 (.A(mgmt_gpio_in[10]),
+ .X(net37),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input38 (.A(mgmt_gpio_in[11]),
+ .X(net38),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input39 (.A(mgmt_gpio_in[12]),
+ .X(net39),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input4 (.A(mask_rev_in[0]),
+ .X(net4),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input40 (.A(mgmt_gpio_in[13]),
+ .X(net40),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input41 (.A(mgmt_gpio_in[14]),
+ .X(net41),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input42 (.A(mgmt_gpio_in[15]),
+ .X(net42),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input43 (.A(mgmt_gpio_in[16]),
+ .X(net43),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input44 (.A(mgmt_gpio_in[17]),
+ .X(net44),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input45 (.A(mgmt_gpio_in[18]),
+ .X(net45),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input46 (.A(mgmt_gpio_in[19]),
+ .X(net46),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input47 (.A(mgmt_gpio_in[1]),
+ .X(net47),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 input48 (.A(mgmt_gpio_in[20]),
+ .X(net48),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input49 (.A(mgmt_gpio_in[21]),
+ .X(net49),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input5 (.A(mask_rev_in[10]),
+ .X(net5),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input50 (.A(mgmt_gpio_in[22]),
+ .X(net50),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 input51 (.A(mgmt_gpio_in[23]),
+ .X(net51),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input52 (.A(mgmt_gpio_in[24]),
+ .X(net52),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input53 (.A(mgmt_gpio_in[25]),
+ .X(net53),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input54 (.A(mgmt_gpio_in[26]),
+ .X(net54),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input55 (.A(mgmt_gpio_in[27]),
+ .X(net55),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input56 (.A(mgmt_gpio_in[28]),
+ .X(net56),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input57 (.A(mgmt_gpio_in[29]),
+ .X(net57),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 input58 (.A(mgmt_gpio_in[2]),
+ .X(net58),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input59 (.A(mgmt_gpio_in[30]),
+ .X(net59),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input6 (.A(mask_rev_in[11]),
+ .X(net6),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input60 (.A(mgmt_gpio_in[31]),
+ .X(net60),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input61 (.A(mgmt_gpio_in[32]),
+ .X(net61),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input62 (.A(mgmt_gpio_in[33]),
+ .X(net62),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input63 (.A(mgmt_gpio_in[34]),
+ .X(net63),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input64 (.A(mgmt_gpio_in[35]),
+ .X(net64),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input65 (.A(mgmt_gpio_in[36]),
+ .X(net65),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input66 (.A(mgmt_gpio_in[37]),
+ .X(net66),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 input67 (.A(mgmt_gpio_in[3]),
+ .X(net67),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input68 (.A(mgmt_gpio_in[5]),
+ .X(net68),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input69 (.A(mgmt_gpio_in[6]),
+ .X(net69),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input7 (.A(mask_rev_in[12]),
+ .X(net7),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input70 (.A(mgmt_gpio_in[7]),
+ .X(net70),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 input71 (.A(mgmt_gpio_in[8]),
+ .X(net71),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input72 (.A(mgmt_gpio_in[9]),
+ .X(net72),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input73 (.A(pad_flash_io0_di),
+ .X(net73),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input74 (.A(pad_flash_io1_di),
+ .X(net74),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 input75 (.A(porb),
+ .X(net75),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input76 (.A(qspi_enabled),
+ .X(net76),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input77 (.A(ser_tx),
+ .X(net77),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input78 (.A(spi_csb),
+ .X(net78),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input79 (.A(spi_enabled),
+ .X(net79),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input8 (.A(mask_rev_in[13]),
+ .X(net8),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input80 (.A(spi_sck),
+ .X(net80),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input81 (.A(spi_sdo),
+ .X(net81),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input82 (.A(spi_sdoenb),
+ .X(net82),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input83 (.A(spimemio_flash_clk),
+ .X(net83),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input84 (.A(spimemio_flash_csb),
+ .X(net84),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_4 input85 (.A(spimemio_flash_io0_do),
+ .X(net85),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input86 (.A(spimemio_flash_io0_oeb),
+ .X(net86),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input87 (.A(spimemio_flash_io1_do),
+ .X(net87),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_6 input88 (.A(spimemio_flash_io1_oeb),
+ .X(net88),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input89 (.A(spimemio_flash_io2_do),
+ .X(net89),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input9 (.A(mask_rev_in[14]),
+ .X(net9),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_2 input90 (.A(spimemio_flash_io2_oeb),
+ .X(net90),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_4 input91 (.A(spimemio_flash_io3_do),
+ .X(net91),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 input92 (.A(spimemio_flash_io3_oeb),
+ .X(net92),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input93 (.A(sram_ro_data[0]),
+ .X(net93),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input94 (.A(sram_ro_data[10]),
+ .X(net94),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input95 (.A(sram_ro_data[11]),
+ .X(net95),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input96 (.A(sram_ro_data[12]),
+ .X(net96),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input97 (.A(sram_ro_data[13]),
+ .X(net97),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input98 (.A(sram_ro_data[14]),
+ .X(net98),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 input99 (.A(sram_ro_data[15]),
+ .X(net99),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 net299_2 (.A(clknet_2_3_0_mgmt_gpio_in[4]),
+ .Y(net380),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__inv_4 net299_3 (.A(clknet_2_0_0_mgmt_gpio_in[4]),
+ .Y(net381),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output203 (.A(net203),
+ .X(debug_in),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output204 (.A(net204),
+ .X(irq[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output205 (.A(net205),
+ .X(irq[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output206 (.A(net206),
+ .X(irq[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output207 (.A(net207),
+ .X(mgmt_gpio_oeb[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output208 (.A(net208),
+ .X(mgmt_gpio_oeb[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output209 (.A(net209),
+ .X(mgmt_gpio_oeb[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output210 (.A(net210),
+ .X(mgmt_gpio_oeb[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output211 (.A(net211),
+ .X(mgmt_gpio_oeb[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output212 (.A(net212),
+ .X(mgmt_gpio_oeb[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output213 (.A(net213),
+ .X(mgmt_gpio_oeb[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output214 (.A(net214),
+ .X(mgmt_gpio_oeb[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output215 (.A(net215),
+ .X(mgmt_gpio_oeb[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output216 (.A(net216),
+ .X(mgmt_gpio_oeb[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output217 (.A(net217),
+ .X(mgmt_gpio_oeb[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output218 (.A(net218),
+ .X(mgmt_gpio_oeb[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output219 (.A(net219),
+ .X(mgmt_gpio_oeb[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output220 (.A(net220),
+ .X(mgmt_gpio_oeb[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output221 (.A(net221),
+ .X(mgmt_gpio_oeb[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output222 (.A(net222),
+ .X(mgmt_gpio_oeb[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output223 (.A(net223),
+ .X(mgmt_gpio_oeb[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output224 (.A(net224),
+ .X(mgmt_gpio_oeb[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output225 (.A(net225),
+ .X(mgmt_gpio_oeb[26]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output226 (.A(net226),
+ .X(mgmt_gpio_oeb[27]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output227 (.A(net227),
+ .X(mgmt_gpio_oeb[28]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output228 (.A(net228),
+ .X(mgmt_gpio_oeb[29]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output229 (.A(net229),
+ .X(mgmt_gpio_oeb[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output230 (.A(net230),
+ .X(mgmt_gpio_oeb[30]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output231 (.A(net231),
+ .X(mgmt_gpio_oeb[31]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output232 (.A(net232),
+ .X(mgmt_gpio_oeb[32]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output233 (.A(net233),
+ .X(mgmt_gpio_oeb[33]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output234 (.A(net234),
+ .X(mgmt_gpio_oeb[34]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output235 (.A(net235),
+ .X(mgmt_gpio_oeb[35]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output236 (.A(net236),
+ .X(mgmt_gpio_oeb[36]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output237 (.A(net237),
+ .X(mgmt_gpio_oeb[37]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output238 (.A(net238),
+ .X(mgmt_gpio_oeb[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output239 (.A(net239),
+ .X(mgmt_gpio_oeb[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output240 (.A(net240),
+ .X(mgmt_gpio_oeb[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output241 (.A(net241),
+ .X(mgmt_gpio_oeb[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output242 (.A(net242),
+ .X(mgmt_gpio_oeb[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output243 (.A(net243),
+ .X(mgmt_gpio_oeb[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output244 (.A(net244),
+ .X(mgmt_gpio_oeb[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output245 (.A(net245),
+ .X(mgmt_gpio_out[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output246 (.A(net246),
+ .X(mgmt_gpio_out[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output247 (.A(net247),
+ .X(mgmt_gpio_out[35]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output248 (.A(net248),
+ .X(mgmt_gpio_out[36]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output249 (.A(net249),
+ .X(mgmt_gpio_out[37]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 output250 (.A(net250),
+ .X(pad_flash_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output251 (.A(net251),
+ .X(pad_flash_clk_oeb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output252 (.A(net252),
+ .X(pad_flash_csb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output253 (.A(net253),
+ .X(pad_flash_csb_oeb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output254 (.A(net254),
+ .X(pad_flash_io0_do),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output255 (.A(net255),
+ .X(pad_flash_io0_ieb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output256 (.A(net256),
+ .X(pad_flash_io0_oeb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output257 (.A(net257),
+ .X(pad_flash_io1_do),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output258 (.A(net258),
+ .X(pad_flash_io1_ieb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output259 (.A(net259),
+ .X(pad_flash_io1_oeb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output260 (.A(net260),
+ .X(pll90_sel[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output261 (.A(net261),
+ .X(pll90_sel[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output262 (.A(net262),
+ .X(pll90_sel[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output263 (.A(net263),
+ .X(pll_bypass),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output264 (.A(net264),
+ .X(pll_dco_ena),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output265 (.A(net265),
+ .X(pll_div[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output266 (.A(net266),
+ .X(pll_div[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output267 (.A(net267),
+ .X(pll_div[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output268 (.A(net268),
+ .X(pll_div[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output269 (.A(net269),
+ .X(pll_div[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output270 (.A(net270),
+ .X(pll_ena),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output271 (.A(net271),
+ .X(pll_sel[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output272 (.A(net272),
+ .X(pll_sel[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output273 (.A(net273),
+ .X(pll_sel[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output274 (.A(net274),
+ .X(pll_trim[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output275 (.A(net275),
+ .X(pll_trim[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output276 (.A(net276),
+ .X(pll_trim[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output277 (.A(net277),
+ .X(pll_trim[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output278 (.A(net278),
+ .X(pll_trim[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output279 (.A(net279),
+ .X(pll_trim[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output280 (.A(net280),
+ .X(pll_trim[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output281 (.A(net281),
+ .X(pll_trim[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output282 (.A(net282),
+ .X(pll_trim[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output283 (.A(net283),
+ .X(pll_trim[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output284 (.A(net284),
+ .X(pll_trim[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output285 (.A(net285),
+ .X(pll_trim[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output286 (.A(net286),
+ .X(pll_trim[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output287 (.A(net287),
+ .X(pll_trim[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output288 (.A(net288),
+ .X(pll_trim[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output289 (.A(net289),
+ .X(pll_trim[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output290 (.A(net290),
+ .X(pll_trim[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output291 (.A(net291),
+ .X(pll_trim[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output292 (.A(net292),
+ .X(pll_trim[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output293 (.A(net293),
+ .X(pll_trim[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output294 (.A(net294),
+ .X(pll_trim[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output295 (.A(net295),
+ .X(pll_trim[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output296 (.A(net296),
+ .X(pll_trim[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output297 (.A(net297),
+ .X(pll_trim[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output298 (.A(net298),
+ .X(pll_trim[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output299 (.A(net299),
+ .X(pll_trim[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output300 (.A(net300),
+ .X(pwr_ctrl_out[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output301 (.A(net301),
+ .X(pwr_ctrl_out[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output302 (.A(net302),
+ .X(pwr_ctrl_out[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output303 (.A(net303),
+ .X(pwr_ctrl_out[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output304 (.A(net304),
+ .X(reset),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output305 (.A(net305),
+ .X(ser_rx),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__clkbuf_1 output306 (.A(net306),
+ .X(serial_clock),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output307 (.A(net307),
+ .X(serial_data_1),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output308 (.A(net308),
+ .X(serial_data_2),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output309 (.A(net309),
+ .X(serial_load),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output310 (.A(net310),
+ .X(serial_resetn),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output311 (.A(net311),
+ .X(spi_sdi),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output312 (.A(net312),
+ .X(spimemio_flash_io0_di),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output313 (.A(net313),
+ .X(spimemio_flash_io1_di),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output314 (.A(net314),
+ .X(spimemio_flash_io2_di),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output315 (.A(net315),
+ .X(spimemio_flash_io3_di),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output316 (.A(net316),
+ .X(sram_ro_addr[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output317 (.A(net317),
+ .X(sram_ro_addr[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output318 (.A(net318),
+ .X(sram_ro_addr[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output319 (.A(net319),
+ .X(sram_ro_addr[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output320 (.A(net320),
+ .X(sram_ro_addr[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output321 (.A(net321),
+ .X(sram_ro_addr[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output322 (.A(net322),
+ .X(sram_ro_addr[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output323 (.A(net323),
+ .X(sram_ro_addr[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output324 (.A(net324),
+ .X(sram_ro_clk),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output325 (.A(net325),
+ .X(sram_ro_csb),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output326 (.A(net326),
+ .X(wb_ack_o),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output327 (.A(net327),
+ .X(wb_dat_o[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output328 (.A(net328),
+ .X(wb_dat_o[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output329 (.A(net329),
+ .X(wb_dat_o[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output330 (.A(net330),
+ .X(wb_dat_o[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output331 (.A(net331),
+ .X(wb_dat_o[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output332 (.A(net332),
+ .X(wb_dat_o[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output333 (.A(net333),
+ .X(wb_dat_o[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output334 (.A(net334),
+ .X(wb_dat_o[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output335 (.A(net335),
+ .X(wb_dat_o[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output336 (.A(net336),
+ .X(wb_dat_o[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output337 (.A(net337),
+ .X(wb_dat_o[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output338 (.A(net338),
+ .X(wb_dat_o[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output339 (.A(net339),
+ .X(wb_dat_o[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output340 (.A(net340),
+ .X(wb_dat_o[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output341 (.A(net341),
+ .X(wb_dat_o[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output342 (.A(net342),
+ .X(wb_dat_o[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output343 (.A(net343),
+ .X(wb_dat_o[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output344 (.A(net344),
+ .X(wb_dat_o[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output345 (.A(net345),
+ .X(wb_dat_o[26]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output346 (.A(net346),
+ .X(wb_dat_o[27]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output347 (.A(net347),
+ .X(wb_dat_o[28]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output348 (.A(net348),
+ .X(wb_dat_o[29]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output349 (.A(net349),
+ .X(wb_dat_o[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output350 (.A(net350),
+ .X(wb_dat_o[30]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output351 (.A(net351),
+ .X(wb_dat_o[31]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output352 (.A(net352),
+ .X(wb_dat_o[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output353 (.A(net353),
+ .X(wb_dat_o[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output354 (.A(net354),
+ .X(wb_dat_o[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output355 (.A(net355),
+ .X(wb_dat_o[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output356 (.A(net356),
+ .X(wb_dat_o[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output357 (.A(net357),
+ .X(wb_dat_o[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_2 output358 (.A(net358),
+ .X(wb_dat_o[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater359 (.A(\cdata[4] ),
+ .X(net359),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater360 (.A(\cdata[4] ),
+ .X(net360),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater361 (.A(\cdata[3] ),
+ .X(net361),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater362 (.A(\cdata[3] ),
+ .X(net362),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater363 (.A(\cdata[2] ),
+ .X(net363),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater364 (.A(\cdata[2] ),
+ .X(net364),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater365 (.A(\cdata[1] ),
+ .X(net365),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater366 (.A(\cdata[1] ),
+ .X(net366),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater367 (.A(\cdata[0] ),
+ .X(net367),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater368 (.A(\cdata[0] ),
+ .X(net368),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater369 (.A(net370),
+ .X(net369),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater370 (.A(net75),
+ .X(net370),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater371 (.A(net373),
+ .X(net371),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater372 (.A(net373),
+ .X(net372),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater373 (.A(net374),
+ .X(net373),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater374 (.A(net375),
+ .X(net374),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater375 (.A(net75),
+ .X(net375),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater376 (.A(net377),
+ .X(net376),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__buf_12 repeater377 (.A(net75),
+ .X(net377),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+endmodule
diff --git a/caravel/verilog/gl/mgmt_protect.v b/caravel/verilog/gl/mgmt_protect.v
new file mode 100644
index 0000000..97e8571
--- /dev/null
+++ b/caravel/verilog/gl/mgmt_protect.v
@@ -0,0 +1,88037 @@
+module mgmt_protect (caravel_clk,
+ caravel_clk2,
+ caravel_rstn,
+ mprj_ack_i_core,
+ mprj_ack_i_user,
+ mprj_cyc_o_core,
+ mprj_cyc_o_user,
+ mprj_iena_wb,
+ mprj_stb_o_core,
+ mprj_stb_o_user,
+ mprj_we_o_core,
+ mprj_we_o_user,
+ user1_vcc_powergood,
+ user1_vdd_powergood,
+ user2_vcc_powergood,
+ user2_vdd_powergood,
+ user_clock,
+ user_clock2,
+ user_reset,
+ vccd,
+ vccd1,
+ vccd2,
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vssd,
+ vssd1,
+ vssd2,
+ la_data_in_core,
+ la_data_in_mprj,
+ la_data_out_core,
+ la_data_out_mprj,
+ la_iena_mprj,
+ la_oenb_core,
+ la_oenb_mprj,
+ mprj_adr_o_core,
+ mprj_adr_o_user,
+ mprj_dat_i_core,
+ mprj_dat_i_user,
+ mprj_dat_o_core,
+ mprj_dat_o_user,
+ mprj_sel_o_core,
+ mprj_sel_o_user,
+ user_irq,
+ user_irq_core,
+ user_irq_ena);
+ input caravel_clk;
+ input caravel_clk2;
+ input caravel_rstn;
+ output mprj_ack_i_core;
+ input mprj_ack_i_user;
+ input mprj_cyc_o_core;
+ output mprj_cyc_o_user;
+ input mprj_iena_wb;
+ input mprj_stb_o_core;
+ output mprj_stb_o_user;
+ input mprj_we_o_core;
+ output mprj_we_o_user;
+ output user1_vcc_powergood;
+ output user1_vdd_powergood;
+ output user2_vcc_powergood;
+ output user2_vdd_powergood;
+ output user_clock;
+ output user_clock2;
+ output user_reset;
+ input vccd;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd;
+ input vssd1;
+ input vssd2;
+ output [127:0] la_data_in_core;
+ output [127:0] la_data_in_mprj;
+ input [127:0] la_data_out_core;
+ input [127:0] la_data_out_mprj;
+ input [127:0] la_iena_mprj;
+ output [127:0] la_oenb_core;
+ input [127:0] la_oenb_mprj;
+ input [31:0] mprj_adr_o_core;
+ output [31:0] mprj_adr_o_user;
+ output [31:0] mprj_dat_i_core;
+ input [31:0] mprj_dat_i_user;
+ input [31:0] mprj_dat_o_core;
+ output [31:0] mprj_dat_o_user;
+ input [3:0] mprj_sel_o_core;
+ output [3:0] mprj_sel_o_user;
+ output [2:0] user_irq;
+ input [2:0] user_irq_core;
+ input [2:0] user_irq_ena;
+
+ wire _000_;
+ wire _001_;
+ wire _002_;
+ wire _003_;
+ wire _004_;
+ wire _005_;
+ wire _006_;
+ wire _007_;
+ wire _008_;
+ wire _009_;
+ wire _010_;
+ wire _011_;
+ wire _012_;
+ wire _013_;
+ wire _014_;
+ wire _015_;
+ wire _016_;
+ wire _017_;
+ wire _018_;
+ wire _019_;
+ wire _020_;
+ wire _021_;
+ wire _022_;
+ wire _023_;
+ wire _024_;
+ wire _025_;
+ wire _026_;
+ wire _027_;
+ wire _028_;
+ wire _029_;
+ wire _030_;
+ wire _031_;
+ wire _032_;
+ wire _033_;
+ wire _034_;
+ wire _035_;
+ wire _036_;
+ wire _037_;
+ wire _038_;
+ wire _039_;
+ wire _040_;
+ wire _041_;
+ wire _042_;
+ wire _043_;
+ wire _044_;
+ wire _045_;
+ wire _046_;
+ wire _047_;
+ wire _048_;
+ wire _049_;
+ wire _050_;
+ wire _051_;
+ wire _052_;
+ wire _053_;
+ wire _054_;
+ wire _055_;
+ wire _056_;
+ wire _057_;
+ wire _058_;
+ wire _059_;
+ wire _060_;
+ wire _061_;
+ wire _062_;
+ wire _063_;
+ wire _064_;
+ wire _065_;
+ wire _066_;
+ wire _067_;
+ wire _068_;
+ wire _069_;
+ wire _070_;
+ wire _071_;
+ wire _072_;
+ wire _073_;
+ wire _074_;
+ wire _075_;
+ wire _076_;
+ wire _077_;
+ wire _078_;
+ wire _079_;
+ wire _080_;
+ wire _081_;
+ wire _082_;
+ wire _083_;
+ wire _084_;
+ wire _085_;
+ wire _086_;
+ wire _087_;
+ wire _088_;
+ wire _089_;
+ wire _090_;
+ wire _091_;
+ wire _092_;
+ wire _093_;
+ wire _094_;
+ wire _095_;
+ wire _096_;
+ wire _097_;
+ wire _098_;
+ wire _099_;
+ wire _100_;
+ wire _101_;
+ wire _102_;
+ wire _103_;
+ wire _104_;
+ wire _105_;
+ wire _106_;
+ wire _107_;
+ wire _108_;
+ wire _109_;
+ wire _110_;
+ wire _111_;
+ wire _112_;
+ wire _113_;
+ wire _114_;
+ wire _115_;
+ wire _116_;
+ wire _117_;
+ wire _118_;
+ wire _119_;
+ wire _120_;
+ wire _121_;
+ wire _122_;
+ wire _123_;
+ wire _124_;
+ wire _125_;
+ wire _126_;
+ wire _127_;
+ wire _128_;
+ wire _129_;
+ wire _130_;
+ wire _131_;
+ wire _132_;
+ wire _133_;
+ wire _134_;
+ wire _135_;
+ wire _136_;
+ wire _137_;
+ wire _138_;
+ wire _139_;
+ wire _140_;
+ wire _141_;
+ wire _142_;
+ wire _143_;
+ wire _144_;
+ wire _145_;
+ wire _146_;
+ wire _147_;
+ wire _148_;
+ wire _149_;
+ wire _150_;
+ wire _151_;
+ wire _152_;
+ wire _153_;
+ wire _154_;
+ wire _155_;
+ wire _156_;
+ wire _157_;
+ wire _158_;
+ wire _159_;
+ wire _160_;
+ wire _161_;
+ wire _162_;
+ wire _163_;
+ wire _164_;
+ wire _165_;
+ wire _166_;
+ wire _167_;
+ wire _168_;
+ wire _169_;
+ wire _170_;
+ wire _171_;
+ wire _172_;
+ wire _173_;
+ wire _174_;
+ wire _175_;
+ wire _176_;
+ wire _177_;
+ wire _178_;
+ wire _179_;
+ wire _180_;
+ wire _181_;
+ wire _182_;
+ wire _183_;
+ wire _184_;
+ wire _185_;
+ wire _186_;
+ wire _187_;
+ wire _188_;
+ wire _189_;
+ wire _190_;
+ wire _191_;
+ wire _192_;
+ wire _193_;
+ wire _194_;
+ wire _195_;
+ wire _196_;
+ wire _197_;
+ wire _198_;
+ wire _199_;
+ wire _200_;
+ wire _201_;
+ wire _202_;
+ wire _203_;
+ wire _204_;
+ wire _205_;
+ wire _206_;
+ wire _207_;
+ wire _208_;
+ wire _209_;
+ wire _210_;
+ wire _211_;
+ wire _212_;
+ wire _213_;
+ wire _214_;
+ wire _215_;
+ wire _216_;
+ wire _217_;
+ wire _218_;
+ wire _219_;
+ wire _220_;
+ wire _221_;
+ wire _222_;
+ wire _223_;
+ wire _224_;
+ wire _225_;
+ wire _226_;
+ wire _227_;
+ wire _228_;
+ wire _229_;
+ wire _230_;
+ wire _231_;
+ wire _232_;
+ wire _233_;
+ wire _234_;
+ wire _235_;
+ wire _236_;
+ wire _237_;
+ wire _238_;
+ wire _239_;
+ wire _240_;
+ wire _241_;
+ wire _242_;
+ wire _243_;
+ wire _244_;
+ wire _245_;
+ wire _246_;
+ wire _247_;
+ wire _248_;
+ wire _249_;
+ wire _250_;
+ wire _251_;
+ wire _252_;
+ wire _253_;
+ wire _254_;
+ wire _255_;
+ wire _256_;
+ wire _257_;
+ wire _258_;
+ wire _259_;
+ wire _260_;
+ wire _261_;
+ wire _262_;
+ wire _263_;
+ wire _264_;
+ wire _265_;
+ wire _266_;
+ wire _267_;
+ wire _268_;
+ wire _269_;
+ wire _270_;
+ wire _271_;
+ wire _272_;
+ wire _273_;
+ wire _274_;
+ wire _275_;
+ wire _276_;
+ wire _277_;
+ wire _278_;
+ wire _279_;
+ wire _280_;
+ wire _281_;
+ wire _282_;
+ wire _283_;
+ wire _284_;
+ wire _285_;
+ wire _286_;
+ wire _287_;
+ wire _288_;
+ wire _289_;
+ wire _290_;
+ wire _291_;
+ wire _292_;
+ wire _293_;
+ wire _294_;
+ wire _295_;
+ wire _296_;
+ wire _297_;
+ wire _298_;
+ wire _299_;
+ wire _300_;
+ wire _301_;
+ wire _302_;
+ wire _303_;
+ wire _304_;
+ wire _305_;
+ wire _306_;
+ wire _307_;
+ wire _308_;
+ wire _309_;
+ wire _310_;
+ wire _311_;
+ wire _312_;
+ wire _313_;
+ wire _314_;
+ wire _315_;
+ wire _316_;
+ wire _317_;
+ wire _318_;
+ wire _319_;
+ wire _320_;
+ wire _321_;
+ wire _322_;
+ wire _323_;
+ wire _324_;
+ wire _325_;
+ wire _326_;
+ wire _327_;
+ wire _328_;
+ wire \la_data_in_enable[0] ;
+ wire \la_data_in_enable[100] ;
+ wire \la_data_in_enable[101] ;
+ wire \la_data_in_enable[102] ;
+ wire \la_data_in_enable[103] ;
+ wire \la_data_in_enable[104] ;
+ wire \la_data_in_enable[105] ;
+ wire \la_data_in_enable[106] ;
+ wire \la_data_in_enable[107] ;
+ wire \la_data_in_enable[108] ;
+ wire \la_data_in_enable[109] ;
+ wire \la_data_in_enable[10] ;
+ wire \la_data_in_enable[110] ;
+ wire \la_data_in_enable[111] ;
+ wire \la_data_in_enable[112] ;
+ wire \la_data_in_enable[113] ;
+ wire \la_data_in_enable[114] ;
+ wire \la_data_in_enable[115] ;
+ wire \la_data_in_enable[116] ;
+ wire \la_data_in_enable[117] ;
+ wire \la_data_in_enable[118] ;
+ wire \la_data_in_enable[119] ;
+ wire \la_data_in_enable[11] ;
+ wire \la_data_in_enable[120] ;
+ wire \la_data_in_enable[121] ;
+ wire \la_data_in_enable[122] ;
+ wire \la_data_in_enable[123] ;
+ wire \la_data_in_enable[124] ;
+ wire \la_data_in_enable[125] ;
+ wire \la_data_in_enable[126] ;
+ wire \la_data_in_enable[127] ;
+ wire \la_data_in_enable[12] ;
+ wire \la_data_in_enable[13] ;
+ wire \la_data_in_enable[14] ;
+ wire \la_data_in_enable[15] ;
+ wire \la_data_in_enable[16] ;
+ wire \la_data_in_enable[17] ;
+ wire \la_data_in_enable[18] ;
+ wire \la_data_in_enable[19] ;
+ wire \la_data_in_enable[1] ;
+ wire \la_data_in_enable[20] ;
+ wire \la_data_in_enable[21] ;
+ wire \la_data_in_enable[22] ;
+ wire \la_data_in_enable[23] ;
+ wire \la_data_in_enable[24] ;
+ wire \la_data_in_enable[25] ;
+ wire \la_data_in_enable[26] ;
+ wire \la_data_in_enable[27] ;
+ wire \la_data_in_enable[28] ;
+ wire \la_data_in_enable[29] ;
+ wire \la_data_in_enable[2] ;
+ wire \la_data_in_enable[30] ;
+ wire \la_data_in_enable[31] ;
+ wire \la_data_in_enable[32] ;
+ wire \la_data_in_enable[33] ;
+ wire \la_data_in_enable[34] ;
+ wire \la_data_in_enable[35] ;
+ wire \la_data_in_enable[36] ;
+ wire \la_data_in_enable[37] ;
+ wire \la_data_in_enable[38] ;
+ wire \la_data_in_enable[39] ;
+ wire \la_data_in_enable[3] ;
+ wire \la_data_in_enable[40] ;
+ wire \la_data_in_enable[41] ;
+ wire \la_data_in_enable[42] ;
+ wire \la_data_in_enable[43] ;
+ wire \la_data_in_enable[44] ;
+ wire \la_data_in_enable[45] ;
+ wire \la_data_in_enable[46] ;
+ wire \la_data_in_enable[47] ;
+ wire \la_data_in_enable[48] ;
+ wire \la_data_in_enable[49] ;
+ wire \la_data_in_enable[4] ;
+ wire \la_data_in_enable[50] ;
+ wire \la_data_in_enable[51] ;
+ wire \la_data_in_enable[52] ;
+ wire \la_data_in_enable[53] ;
+ wire \la_data_in_enable[54] ;
+ wire \la_data_in_enable[55] ;
+ wire \la_data_in_enable[56] ;
+ wire \la_data_in_enable[57] ;
+ wire \la_data_in_enable[58] ;
+ wire \la_data_in_enable[59] ;
+ wire \la_data_in_enable[5] ;
+ wire \la_data_in_enable[60] ;
+ wire \la_data_in_enable[61] ;
+ wire \la_data_in_enable[62] ;
+ wire \la_data_in_enable[63] ;
+ wire \la_data_in_enable[64] ;
+ wire \la_data_in_enable[65] ;
+ wire \la_data_in_enable[66] ;
+ wire \la_data_in_enable[67] ;
+ wire \la_data_in_enable[68] ;
+ wire \la_data_in_enable[69] ;
+ wire \la_data_in_enable[6] ;
+ wire \la_data_in_enable[70] ;
+ wire \la_data_in_enable[71] ;
+ wire \la_data_in_enable[72] ;
+ wire \la_data_in_enable[73] ;
+ wire \la_data_in_enable[74] ;
+ wire \la_data_in_enable[75] ;
+ wire \la_data_in_enable[76] ;
+ wire \la_data_in_enable[77] ;
+ wire \la_data_in_enable[78] ;
+ wire \la_data_in_enable[79] ;
+ wire \la_data_in_enable[7] ;
+ wire \la_data_in_enable[80] ;
+ wire \la_data_in_enable[81] ;
+ wire \la_data_in_enable[82] ;
+ wire \la_data_in_enable[83] ;
+ wire \la_data_in_enable[84] ;
+ wire \la_data_in_enable[85] ;
+ wire \la_data_in_enable[86] ;
+ wire \la_data_in_enable[87] ;
+ wire \la_data_in_enable[88] ;
+ wire \la_data_in_enable[89] ;
+ wire \la_data_in_enable[8] ;
+ wire \la_data_in_enable[90] ;
+ wire \la_data_in_enable[91] ;
+ wire \la_data_in_enable[92] ;
+ wire \la_data_in_enable[93] ;
+ wire \la_data_in_enable[94] ;
+ wire \la_data_in_enable[95] ;
+ wire \la_data_in_enable[96] ;
+ wire \la_data_in_enable[97] ;
+ wire \la_data_in_enable[98] ;
+ wire \la_data_in_enable[99] ;
+ wire \la_data_in_enable[9] ;
+ wire \la_data_in_mprj_bar[0] ;
+ wire \la_data_in_mprj_bar[100] ;
+ wire \la_data_in_mprj_bar[101] ;
+ wire \la_data_in_mprj_bar[102] ;
+ wire \la_data_in_mprj_bar[103] ;
+ wire \la_data_in_mprj_bar[104] ;
+ wire \la_data_in_mprj_bar[105] ;
+ wire \la_data_in_mprj_bar[106] ;
+ wire \la_data_in_mprj_bar[107] ;
+ wire \la_data_in_mprj_bar[108] ;
+ wire \la_data_in_mprj_bar[109] ;
+ wire \la_data_in_mprj_bar[10] ;
+ wire \la_data_in_mprj_bar[110] ;
+ wire \la_data_in_mprj_bar[111] ;
+ wire \la_data_in_mprj_bar[112] ;
+ wire \la_data_in_mprj_bar[113] ;
+ wire \la_data_in_mprj_bar[114] ;
+ wire \la_data_in_mprj_bar[115] ;
+ wire \la_data_in_mprj_bar[116] ;
+ wire \la_data_in_mprj_bar[117] ;
+ wire \la_data_in_mprj_bar[118] ;
+ wire \la_data_in_mprj_bar[119] ;
+ wire \la_data_in_mprj_bar[11] ;
+ wire \la_data_in_mprj_bar[120] ;
+ wire \la_data_in_mprj_bar[121] ;
+ wire \la_data_in_mprj_bar[122] ;
+ wire \la_data_in_mprj_bar[123] ;
+ wire \la_data_in_mprj_bar[124] ;
+ wire \la_data_in_mprj_bar[125] ;
+ wire \la_data_in_mprj_bar[126] ;
+ wire \la_data_in_mprj_bar[127] ;
+ wire \la_data_in_mprj_bar[12] ;
+ wire \la_data_in_mprj_bar[13] ;
+ wire \la_data_in_mprj_bar[14] ;
+ wire \la_data_in_mprj_bar[15] ;
+ wire \la_data_in_mprj_bar[16] ;
+ wire \la_data_in_mprj_bar[17] ;
+ wire \la_data_in_mprj_bar[18] ;
+ wire \la_data_in_mprj_bar[19] ;
+ wire \la_data_in_mprj_bar[1] ;
+ wire \la_data_in_mprj_bar[20] ;
+ wire \la_data_in_mprj_bar[21] ;
+ wire \la_data_in_mprj_bar[22] ;
+ wire \la_data_in_mprj_bar[23] ;
+ wire \la_data_in_mprj_bar[24] ;
+ wire \la_data_in_mprj_bar[25] ;
+ wire \la_data_in_mprj_bar[26] ;
+ wire \la_data_in_mprj_bar[27] ;
+ wire \la_data_in_mprj_bar[28] ;
+ wire \la_data_in_mprj_bar[29] ;
+ wire \la_data_in_mprj_bar[2] ;
+ wire \la_data_in_mprj_bar[30] ;
+ wire \la_data_in_mprj_bar[31] ;
+ wire \la_data_in_mprj_bar[32] ;
+ wire \la_data_in_mprj_bar[33] ;
+ wire \la_data_in_mprj_bar[34] ;
+ wire \la_data_in_mprj_bar[35] ;
+ wire \la_data_in_mprj_bar[36] ;
+ wire \la_data_in_mprj_bar[37] ;
+ wire \la_data_in_mprj_bar[38] ;
+ wire \la_data_in_mprj_bar[39] ;
+ wire \la_data_in_mprj_bar[3] ;
+ wire \la_data_in_mprj_bar[40] ;
+ wire \la_data_in_mprj_bar[41] ;
+ wire \la_data_in_mprj_bar[42] ;
+ wire \la_data_in_mprj_bar[43] ;
+ wire \la_data_in_mprj_bar[44] ;
+ wire \la_data_in_mprj_bar[45] ;
+ wire \la_data_in_mprj_bar[46] ;
+ wire \la_data_in_mprj_bar[47] ;
+ wire \la_data_in_mprj_bar[48] ;
+ wire \la_data_in_mprj_bar[49] ;
+ wire \la_data_in_mprj_bar[4] ;
+ wire \la_data_in_mprj_bar[50] ;
+ wire \la_data_in_mprj_bar[51] ;
+ wire \la_data_in_mprj_bar[52] ;
+ wire \la_data_in_mprj_bar[53] ;
+ wire \la_data_in_mprj_bar[54] ;
+ wire \la_data_in_mprj_bar[55] ;
+ wire \la_data_in_mprj_bar[56] ;
+ wire \la_data_in_mprj_bar[57] ;
+ wire \la_data_in_mprj_bar[58] ;
+ wire \la_data_in_mprj_bar[59] ;
+ wire \la_data_in_mprj_bar[5] ;
+ wire \la_data_in_mprj_bar[60] ;
+ wire \la_data_in_mprj_bar[61] ;
+ wire \la_data_in_mprj_bar[62] ;
+ wire \la_data_in_mprj_bar[63] ;
+ wire \la_data_in_mprj_bar[64] ;
+ wire \la_data_in_mprj_bar[65] ;
+ wire \la_data_in_mprj_bar[66] ;
+ wire \la_data_in_mprj_bar[67] ;
+ wire \la_data_in_mprj_bar[68] ;
+ wire \la_data_in_mprj_bar[69] ;
+ wire \la_data_in_mprj_bar[6] ;
+ wire \la_data_in_mprj_bar[70] ;
+ wire \la_data_in_mprj_bar[71] ;
+ wire \la_data_in_mprj_bar[72] ;
+ wire \la_data_in_mprj_bar[73] ;
+ wire \la_data_in_mprj_bar[74] ;
+ wire \la_data_in_mprj_bar[75] ;
+ wire \la_data_in_mprj_bar[76] ;
+ wire \la_data_in_mprj_bar[77] ;
+ wire \la_data_in_mprj_bar[78] ;
+ wire \la_data_in_mprj_bar[79] ;
+ wire \la_data_in_mprj_bar[7] ;
+ wire \la_data_in_mprj_bar[80] ;
+ wire \la_data_in_mprj_bar[81] ;
+ wire \la_data_in_mprj_bar[82] ;
+ wire \la_data_in_mprj_bar[83] ;
+ wire \la_data_in_mprj_bar[84] ;
+ wire \la_data_in_mprj_bar[85] ;
+ wire \la_data_in_mprj_bar[86] ;
+ wire \la_data_in_mprj_bar[87] ;
+ wire \la_data_in_mprj_bar[88] ;
+ wire \la_data_in_mprj_bar[89] ;
+ wire \la_data_in_mprj_bar[8] ;
+ wire \la_data_in_mprj_bar[90] ;
+ wire \la_data_in_mprj_bar[91] ;
+ wire \la_data_in_mprj_bar[92] ;
+ wire \la_data_in_mprj_bar[93] ;
+ wire \la_data_in_mprj_bar[94] ;
+ wire \la_data_in_mprj_bar[95] ;
+ wire \la_data_in_mprj_bar[96] ;
+ wire \la_data_in_mprj_bar[97] ;
+ wire \la_data_in_mprj_bar[98] ;
+ wire \la_data_in_mprj_bar[99] ;
+ wire \la_data_in_mprj_bar[9] ;
+ wire \la_data_out_enable[0] ;
+ wire \la_data_out_enable[100] ;
+ wire \la_data_out_enable[101] ;
+ wire \la_data_out_enable[102] ;
+ wire \la_data_out_enable[103] ;
+ wire \la_data_out_enable[104] ;
+ wire \la_data_out_enable[105] ;
+ wire \la_data_out_enable[106] ;
+ wire \la_data_out_enable[107] ;
+ wire \la_data_out_enable[108] ;
+ wire \la_data_out_enable[109] ;
+ wire \la_data_out_enable[10] ;
+ wire \la_data_out_enable[110] ;
+ wire \la_data_out_enable[111] ;
+ wire \la_data_out_enable[112] ;
+ wire \la_data_out_enable[113] ;
+ wire \la_data_out_enable[114] ;
+ wire \la_data_out_enable[115] ;
+ wire \la_data_out_enable[116] ;
+ wire \la_data_out_enable[117] ;
+ wire \la_data_out_enable[118] ;
+ wire \la_data_out_enable[119] ;
+ wire \la_data_out_enable[11] ;
+ wire \la_data_out_enable[120] ;
+ wire \la_data_out_enable[121] ;
+ wire \la_data_out_enable[122] ;
+ wire \la_data_out_enable[123] ;
+ wire \la_data_out_enable[124] ;
+ wire \la_data_out_enable[125] ;
+ wire \la_data_out_enable[126] ;
+ wire \la_data_out_enable[127] ;
+ wire \la_data_out_enable[12] ;
+ wire \la_data_out_enable[13] ;
+ wire \la_data_out_enable[14] ;
+ wire \la_data_out_enable[15] ;
+ wire \la_data_out_enable[16] ;
+ wire \la_data_out_enable[17] ;
+ wire \la_data_out_enable[18] ;
+ wire \la_data_out_enable[19] ;
+ wire \la_data_out_enable[1] ;
+ wire \la_data_out_enable[20] ;
+ wire \la_data_out_enable[21] ;
+ wire \la_data_out_enable[22] ;
+ wire \la_data_out_enable[23] ;
+ wire \la_data_out_enable[24] ;
+ wire \la_data_out_enable[25] ;
+ wire \la_data_out_enable[26] ;
+ wire \la_data_out_enable[27] ;
+ wire \la_data_out_enable[28] ;
+ wire \la_data_out_enable[29] ;
+ wire \la_data_out_enable[2] ;
+ wire \la_data_out_enable[30] ;
+ wire \la_data_out_enable[31] ;
+ wire \la_data_out_enable[32] ;
+ wire \la_data_out_enable[33] ;
+ wire \la_data_out_enable[34] ;
+ wire \la_data_out_enable[35] ;
+ wire \la_data_out_enable[36] ;
+ wire \la_data_out_enable[37] ;
+ wire \la_data_out_enable[38] ;
+ wire \la_data_out_enable[39] ;
+ wire \la_data_out_enable[3] ;
+ wire \la_data_out_enable[40] ;
+ wire \la_data_out_enable[41] ;
+ wire \la_data_out_enable[42] ;
+ wire \la_data_out_enable[43] ;
+ wire \la_data_out_enable[44] ;
+ wire \la_data_out_enable[45] ;
+ wire \la_data_out_enable[46] ;
+ wire \la_data_out_enable[47] ;
+ wire \la_data_out_enable[48] ;
+ wire \la_data_out_enable[49] ;
+ wire \la_data_out_enable[4] ;
+ wire \la_data_out_enable[50] ;
+ wire \la_data_out_enable[51] ;
+ wire \la_data_out_enable[52] ;
+ wire \la_data_out_enable[53] ;
+ wire \la_data_out_enable[54] ;
+ wire \la_data_out_enable[55] ;
+ wire \la_data_out_enable[56] ;
+ wire \la_data_out_enable[57] ;
+ wire \la_data_out_enable[58] ;
+ wire \la_data_out_enable[59] ;
+ wire \la_data_out_enable[5] ;
+ wire \la_data_out_enable[60] ;
+ wire \la_data_out_enable[61] ;
+ wire \la_data_out_enable[62] ;
+ wire \la_data_out_enable[63] ;
+ wire \la_data_out_enable[64] ;
+ wire \la_data_out_enable[65] ;
+ wire \la_data_out_enable[66] ;
+ wire \la_data_out_enable[67] ;
+ wire \la_data_out_enable[68] ;
+ wire \la_data_out_enable[69] ;
+ wire \la_data_out_enable[6] ;
+ wire \la_data_out_enable[70] ;
+ wire \la_data_out_enable[71] ;
+ wire \la_data_out_enable[72] ;
+ wire \la_data_out_enable[73] ;
+ wire \la_data_out_enable[74] ;
+ wire \la_data_out_enable[75] ;
+ wire \la_data_out_enable[76] ;
+ wire \la_data_out_enable[77] ;
+ wire \la_data_out_enable[78] ;
+ wire \la_data_out_enable[79] ;
+ wire \la_data_out_enable[7] ;
+ wire \la_data_out_enable[80] ;
+ wire \la_data_out_enable[81] ;
+ wire \la_data_out_enable[82] ;
+ wire \la_data_out_enable[83] ;
+ wire \la_data_out_enable[84] ;
+ wire \la_data_out_enable[85] ;
+ wire \la_data_out_enable[86] ;
+ wire \la_data_out_enable[87] ;
+ wire \la_data_out_enable[88] ;
+ wire \la_data_out_enable[89] ;
+ wire \la_data_out_enable[8] ;
+ wire \la_data_out_enable[90] ;
+ wire \la_data_out_enable[91] ;
+ wire \la_data_out_enable[92] ;
+ wire \la_data_out_enable[93] ;
+ wire \la_data_out_enable[94] ;
+ wire \la_data_out_enable[95] ;
+ wire \la_data_out_enable[96] ;
+ wire \la_data_out_enable[97] ;
+ wire \la_data_out_enable[98] ;
+ wire \la_data_out_enable[99] ;
+ wire \la_data_out_enable[9] ;
+ wire mprj2_logic1;
+ wire mprj2_vdd_logic1;
+ wire mprj_ack_i_core_bar;
+ wire \mprj_dat_i_core_bar[0] ;
+ wire \mprj_dat_i_core_bar[10] ;
+ wire \mprj_dat_i_core_bar[11] ;
+ wire \mprj_dat_i_core_bar[12] ;
+ wire \mprj_dat_i_core_bar[13] ;
+ wire \mprj_dat_i_core_bar[14] ;
+ wire \mprj_dat_i_core_bar[15] ;
+ wire \mprj_dat_i_core_bar[16] ;
+ wire \mprj_dat_i_core_bar[17] ;
+ wire \mprj_dat_i_core_bar[18] ;
+ wire \mprj_dat_i_core_bar[19] ;
+ wire \mprj_dat_i_core_bar[1] ;
+ wire \mprj_dat_i_core_bar[20] ;
+ wire \mprj_dat_i_core_bar[21] ;
+ wire \mprj_dat_i_core_bar[22] ;
+ wire \mprj_dat_i_core_bar[23] ;
+ wire \mprj_dat_i_core_bar[24] ;
+ wire \mprj_dat_i_core_bar[25] ;
+ wire \mprj_dat_i_core_bar[26] ;
+ wire \mprj_dat_i_core_bar[27] ;
+ wire \mprj_dat_i_core_bar[28] ;
+ wire \mprj_dat_i_core_bar[29] ;
+ wire \mprj_dat_i_core_bar[2] ;
+ wire \mprj_dat_i_core_bar[30] ;
+ wire \mprj_dat_i_core_bar[31] ;
+ wire \mprj_dat_i_core_bar[3] ;
+ wire \mprj_dat_i_core_bar[4] ;
+ wire \mprj_dat_i_core_bar[5] ;
+ wire \mprj_dat_i_core_bar[6] ;
+ wire \mprj_dat_i_core_bar[7] ;
+ wire \mprj_dat_i_core_bar[8] ;
+ wire \mprj_dat_i_core_bar[9] ;
+ wire \mprj_logic1[0] ;
+ wire \mprj_logic1[100] ;
+ wire \mprj_logic1[101] ;
+ wire \mprj_logic1[102] ;
+ wire \mprj_logic1[103] ;
+ wire \mprj_logic1[104] ;
+ wire \mprj_logic1[105] ;
+ wire \mprj_logic1[106] ;
+ wire \mprj_logic1[107] ;
+ wire \mprj_logic1[108] ;
+ wire \mprj_logic1[109] ;
+ wire \mprj_logic1[10] ;
+ wire \mprj_logic1[110] ;
+ wire \mprj_logic1[111] ;
+ wire \mprj_logic1[112] ;
+ wire \mprj_logic1[113] ;
+ wire \mprj_logic1[114] ;
+ wire \mprj_logic1[115] ;
+ wire \mprj_logic1[116] ;
+ wire \mprj_logic1[117] ;
+ wire \mprj_logic1[118] ;
+ wire \mprj_logic1[119] ;
+ wire \mprj_logic1[11] ;
+ wire \mprj_logic1[120] ;
+ wire \mprj_logic1[121] ;
+ wire \mprj_logic1[122] ;
+ wire \mprj_logic1[123] ;
+ wire \mprj_logic1[124] ;
+ wire \mprj_logic1[125] ;
+ wire \mprj_logic1[126] ;
+ wire \mprj_logic1[127] ;
+ wire \mprj_logic1[128] ;
+ wire \mprj_logic1[129] ;
+ wire \mprj_logic1[12] ;
+ wire \mprj_logic1[130] ;
+ wire \mprj_logic1[131] ;
+ wire \mprj_logic1[132] ;
+ wire \mprj_logic1[133] ;
+ wire \mprj_logic1[134] ;
+ wire \mprj_logic1[135] ;
+ wire \mprj_logic1[136] ;
+ wire \mprj_logic1[137] ;
+ wire \mprj_logic1[138] ;
+ wire \mprj_logic1[139] ;
+ wire \mprj_logic1[13] ;
+ wire \mprj_logic1[140] ;
+ wire \mprj_logic1[141] ;
+ wire \mprj_logic1[142] ;
+ wire \mprj_logic1[143] ;
+ wire \mprj_logic1[144] ;
+ wire \mprj_logic1[145] ;
+ wire \mprj_logic1[146] ;
+ wire \mprj_logic1[147] ;
+ wire \mprj_logic1[148] ;
+ wire \mprj_logic1[149] ;
+ wire \mprj_logic1[14] ;
+ wire \mprj_logic1[150] ;
+ wire \mprj_logic1[151] ;
+ wire \mprj_logic1[152] ;
+ wire \mprj_logic1[153] ;
+ wire \mprj_logic1[154] ;
+ wire \mprj_logic1[155] ;
+ wire \mprj_logic1[156] ;
+ wire \mprj_logic1[157] ;
+ wire \mprj_logic1[158] ;
+ wire \mprj_logic1[159] ;
+ wire \mprj_logic1[15] ;
+ wire \mprj_logic1[160] ;
+ wire \mprj_logic1[161] ;
+ wire \mprj_logic1[162] ;
+ wire \mprj_logic1[163] ;
+ wire \mprj_logic1[164] ;
+ wire \mprj_logic1[165] ;
+ wire \mprj_logic1[166] ;
+ wire \mprj_logic1[167] ;
+ wire \mprj_logic1[168] ;
+ wire \mprj_logic1[169] ;
+ wire \mprj_logic1[16] ;
+ wire \mprj_logic1[170] ;
+ wire \mprj_logic1[171] ;
+ wire \mprj_logic1[172] ;
+ wire \mprj_logic1[173] ;
+ wire \mprj_logic1[174] ;
+ wire \mprj_logic1[175] ;
+ wire \mprj_logic1[176] ;
+ wire \mprj_logic1[177] ;
+ wire \mprj_logic1[178] ;
+ wire \mprj_logic1[179] ;
+ wire \mprj_logic1[17] ;
+ wire \mprj_logic1[180] ;
+ wire \mprj_logic1[181] ;
+ wire \mprj_logic1[182] ;
+ wire \mprj_logic1[183] ;
+ wire \mprj_logic1[184] ;
+ wire \mprj_logic1[185] ;
+ wire \mprj_logic1[186] ;
+ wire \mprj_logic1[187] ;
+ wire \mprj_logic1[188] ;
+ wire \mprj_logic1[189] ;
+ wire \mprj_logic1[18] ;
+ wire \mprj_logic1[190] ;
+ wire \mprj_logic1[191] ;
+ wire \mprj_logic1[192] ;
+ wire \mprj_logic1[193] ;
+ wire \mprj_logic1[194] ;
+ wire \mprj_logic1[195] ;
+ wire \mprj_logic1[196] ;
+ wire \mprj_logic1[197] ;
+ wire \mprj_logic1[198] ;
+ wire \mprj_logic1[199] ;
+ wire \mprj_logic1[19] ;
+ wire \mprj_logic1[1] ;
+ wire \mprj_logic1[200] ;
+ wire \mprj_logic1[201] ;
+ wire \mprj_logic1[202] ;
+ wire \mprj_logic1[203] ;
+ wire \mprj_logic1[204] ;
+ wire \mprj_logic1[205] ;
+ wire \mprj_logic1[206] ;
+ wire \mprj_logic1[207] ;
+ wire \mprj_logic1[208] ;
+ wire \mprj_logic1[209] ;
+ wire \mprj_logic1[20] ;
+ wire \mprj_logic1[210] ;
+ wire \mprj_logic1[211] ;
+ wire \mprj_logic1[212] ;
+ wire \mprj_logic1[213] ;
+ wire \mprj_logic1[214] ;
+ wire \mprj_logic1[215] ;
+ wire \mprj_logic1[216] ;
+ wire \mprj_logic1[217] ;
+ wire \mprj_logic1[218] ;
+ wire \mprj_logic1[219] ;
+ wire \mprj_logic1[21] ;
+ wire \mprj_logic1[220] ;
+ wire \mprj_logic1[221] ;
+ wire \mprj_logic1[222] ;
+ wire \mprj_logic1[223] ;
+ wire \mprj_logic1[224] ;
+ wire \mprj_logic1[225] ;
+ wire \mprj_logic1[226] ;
+ wire \mprj_logic1[227] ;
+ wire \mprj_logic1[228] ;
+ wire \mprj_logic1[229] ;
+ wire \mprj_logic1[22] ;
+ wire \mprj_logic1[230] ;
+ wire \mprj_logic1[231] ;
+ wire \mprj_logic1[232] ;
+ wire \mprj_logic1[233] ;
+ wire \mprj_logic1[234] ;
+ wire \mprj_logic1[235] ;
+ wire \mprj_logic1[236] ;
+ wire \mprj_logic1[237] ;
+ wire \mprj_logic1[238] ;
+ wire \mprj_logic1[239] ;
+ wire \mprj_logic1[23] ;
+ wire \mprj_logic1[240] ;
+ wire \mprj_logic1[241] ;
+ wire \mprj_logic1[242] ;
+ wire \mprj_logic1[243] ;
+ wire \mprj_logic1[244] ;
+ wire \mprj_logic1[245] ;
+ wire \mprj_logic1[246] ;
+ wire \mprj_logic1[247] ;
+ wire \mprj_logic1[248] ;
+ wire \mprj_logic1[249] ;
+ wire \mprj_logic1[24] ;
+ wire \mprj_logic1[250] ;
+ wire \mprj_logic1[251] ;
+ wire \mprj_logic1[252] ;
+ wire \mprj_logic1[253] ;
+ wire \mprj_logic1[254] ;
+ wire \mprj_logic1[255] ;
+ wire \mprj_logic1[256] ;
+ wire \mprj_logic1[257] ;
+ wire \mprj_logic1[258] ;
+ wire \mprj_logic1[259] ;
+ wire \mprj_logic1[25] ;
+ wire \mprj_logic1[260] ;
+ wire \mprj_logic1[261] ;
+ wire \mprj_logic1[262] ;
+ wire \mprj_logic1[263] ;
+ wire \mprj_logic1[264] ;
+ wire \mprj_logic1[265] ;
+ wire \mprj_logic1[266] ;
+ wire \mprj_logic1[267] ;
+ wire \mprj_logic1[268] ;
+ wire \mprj_logic1[269] ;
+ wire \mprj_logic1[26] ;
+ wire \mprj_logic1[270] ;
+ wire \mprj_logic1[271] ;
+ wire \mprj_logic1[272] ;
+ wire \mprj_logic1[273] ;
+ wire \mprj_logic1[274] ;
+ wire \mprj_logic1[275] ;
+ wire \mprj_logic1[276] ;
+ wire \mprj_logic1[277] ;
+ wire \mprj_logic1[278] ;
+ wire \mprj_logic1[279] ;
+ wire \mprj_logic1[27] ;
+ wire \mprj_logic1[280] ;
+ wire \mprj_logic1[281] ;
+ wire \mprj_logic1[282] ;
+ wire \mprj_logic1[283] ;
+ wire \mprj_logic1[284] ;
+ wire \mprj_logic1[285] ;
+ wire \mprj_logic1[286] ;
+ wire \mprj_logic1[287] ;
+ wire \mprj_logic1[288] ;
+ wire \mprj_logic1[289] ;
+ wire \mprj_logic1[28] ;
+ wire \mprj_logic1[290] ;
+ wire \mprj_logic1[291] ;
+ wire \mprj_logic1[292] ;
+ wire \mprj_logic1[293] ;
+ wire \mprj_logic1[294] ;
+ wire \mprj_logic1[295] ;
+ wire \mprj_logic1[296] ;
+ wire \mprj_logic1[297] ;
+ wire \mprj_logic1[298] ;
+ wire \mprj_logic1[299] ;
+ wire \mprj_logic1[29] ;
+ wire \mprj_logic1[2] ;
+ wire \mprj_logic1[300] ;
+ wire \mprj_logic1[301] ;
+ wire \mprj_logic1[302] ;
+ wire \mprj_logic1[303] ;
+ wire \mprj_logic1[304] ;
+ wire \mprj_logic1[305] ;
+ wire \mprj_logic1[306] ;
+ wire \mprj_logic1[307] ;
+ wire \mprj_logic1[308] ;
+ wire \mprj_logic1[309] ;
+ wire \mprj_logic1[30] ;
+ wire \mprj_logic1[310] ;
+ wire \mprj_logic1[311] ;
+ wire \mprj_logic1[312] ;
+ wire \mprj_logic1[313] ;
+ wire \mprj_logic1[314] ;
+ wire \mprj_logic1[315] ;
+ wire \mprj_logic1[316] ;
+ wire \mprj_logic1[317] ;
+ wire \mprj_logic1[318] ;
+ wire \mprj_logic1[319] ;
+ wire \mprj_logic1[31] ;
+ wire \mprj_logic1[320] ;
+ wire \mprj_logic1[321] ;
+ wire \mprj_logic1[322] ;
+ wire \mprj_logic1[323] ;
+ wire \mprj_logic1[324] ;
+ wire \mprj_logic1[325] ;
+ wire \mprj_logic1[326] ;
+ wire \mprj_logic1[327] ;
+ wire \mprj_logic1[328] ;
+ wire \mprj_logic1[329] ;
+ wire \mprj_logic1[32] ;
+ wire \mprj_logic1[330] ;
+ wire \mprj_logic1[331] ;
+ wire \mprj_logic1[332] ;
+ wire \mprj_logic1[333] ;
+ wire \mprj_logic1[334] ;
+ wire \mprj_logic1[335] ;
+ wire \mprj_logic1[336] ;
+ wire \mprj_logic1[337] ;
+ wire \mprj_logic1[338] ;
+ wire \mprj_logic1[339] ;
+ wire \mprj_logic1[33] ;
+ wire \mprj_logic1[340] ;
+ wire \mprj_logic1[341] ;
+ wire \mprj_logic1[342] ;
+ wire \mprj_logic1[343] ;
+ wire \mprj_logic1[344] ;
+ wire \mprj_logic1[345] ;
+ wire \mprj_logic1[346] ;
+ wire \mprj_logic1[347] ;
+ wire \mprj_logic1[348] ;
+ wire \mprj_logic1[349] ;
+ wire \mprj_logic1[34] ;
+ wire \mprj_logic1[350] ;
+ wire \mprj_logic1[351] ;
+ wire \mprj_logic1[352] ;
+ wire \mprj_logic1[353] ;
+ wire \mprj_logic1[354] ;
+ wire \mprj_logic1[355] ;
+ wire \mprj_logic1[356] ;
+ wire \mprj_logic1[357] ;
+ wire \mprj_logic1[358] ;
+ wire \mprj_logic1[359] ;
+ wire \mprj_logic1[35] ;
+ wire \mprj_logic1[360] ;
+ wire \mprj_logic1[361] ;
+ wire \mprj_logic1[362] ;
+ wire \mprj_logic1[363] ;
+ wire \mprj_logic1[364] ;
+ wire \mprj_logic1[365] ;
+ wire \mprj_logic1[366] ;
+ wire \mprj_logic1[367] ;
+ wire \mprj_logic1[368] ;
+ wire \mprj_logic1[369] ;
+ wire \mprj_logic1[36] ;
+ wire \mprj_logic1[370] ;
+ wire \mprj_logic1[371] ;
+ wire \mprj_logic1[372] ;
+ wire \mprj_logic1[373] ;
+ wire \mprj_logic1[374] ;
+ wire \mprj_logic1[375] ;
+ wire \mprj_logic1[376] ;
+ wire \mprj_logic1[377] ;
+ wire \mprj_logic1[378] ;
+ wire \mprj_logic1[379] ;
+ wire \mprj_logic1[37] ;
+ wire \mprj_logic1[380] ;
+ wire \mprj_logic1[381] ;
+ wire \mprj_logic1[382] ;
+ wire \mprj_logic1[383] ;
+ wire \mprj_logic1[384] ;
+ wire \mprj_logic1[385] ;
+ wire \mprj_logic1[386] ;
+ wire \mprj_logic1[387] ;
+ wire \mprj_logic1[388] ;
+ wire \mprj_logic1[389] ;
+ wire \mprj_logic1[38] ;
+ wire \mprj_logic1[390] ;
+ wire \mprj_logic1[391] ;
+ wire \mprj_logic1[392] ;
+ wire \mprj_logic1[393] ;
+ wire \mprj_logic1[394] ;
+ wire \mprj_logic1[395] ;
+ wire \mprj_logic1[396] ;
+ wire \mprj_logic1[397] ;
+ wire \mprj_logic1[398] ;
+ wire \mprj_logic1[399] ;
+ wire \mprj_logic1[39] ;
+ wire \mprj_logic1[3] ;
+ wire \mprj_logic1[400] ;
+ wire \mprj_logic1[401] ;
+ wire \mprj_logic1[402] ;
+ wire \mprj_logic1[403] ;
+ wire \mprj_logic1[404] ;
+ wire \mprj_logic1[405] ;
+ wire \mprj_logic1[406] ;
+ wire \mprj_logic1[407] ;
+ wire \mprj_logic1[408] ;
+ wire \mprj_logic1[409] ;
+ wire \mprj_logic1[40] ;
+ wire \mprj_logic1[410] ;
+ wire \mprj_logic1[411] ;
+ wire \mprj_logic1[412] ;
+ wire \mprj_logic1[413] ;
+ wire \mprj_logic1[414] ;
+ wire \mprj_logic1[415] ;
+ wire \mprj_logic1[416] ;
+ wire \mprj_logic1[417] ;
+ wire \mprj_logic1[418] ;
+ wire \mprj_logic1[419] ;
+ wire \mprj_logic1[41] ;
+ wire \mprj_logic1[420] ;
+ wire \mprj_logic1[421] ;
+ wire \mprj_logic1[422] ;
+ wire \mprj_logic1[423] ;
+ wire \mprj_logic1[424] ;
+ wire \mprj_logic1[425] ;
+ wire \mprj_logic1[426] ;
+ wire \mprj_logic1[427] ;
+ wire \mprj_logic1[428] ;
+ wire \mprj_logic1[429] ;
+ wire \mprj_logic1[42] ;
+ wire \mprj_logic1[430] ;
+ wire \mprj_logic1[431] ;
+ wire \mprj_logic1[432] ;
+ wire \mprj_logic1[433] ;
+ wire \mprj_logic1[434] ;
+ wire \mprj_logic1[435] ;
+ wire \mprj_logic1[436] ;
+ wire \mprj_logic1[437] ;
+ wire \mprj_logic1[438] ;
+ wire \mprj_logic1[439] ;
+ wire \mprj_logic1[43] ;
+ wire \mprj_logic1[440] ;
+ wire \mprj_logic1[441] ;
+ wire \mprj_logic1[442] ;
+ wire \mprj_logic1[443] ;
+ wire \mprj_logic1[444] ;
+ wire \mprj_logic1[445] ;
+ wire \mprj_logic1[446] ;
+ wire \mprj_logic1[447] ;
+ wire \mprj_logic1[448] ;
+ wire \mprj_logic1[449] ;
+ wire \mprj_logic1[44] ;
+ wire \mprj_logic1[450] ;
+ wire \mprj_logic1[451] ;
+ wire \mprj_logic1[452] ;
+ wire \mprj_logic1[453] ;
+ wire \mprj_logic1[454] ;
+ wire \mprj_logic1[455] ;
+ wire \mprj_logic1[456] ;
+ wire \mprj_logic1[457] ;
+ wire \mprj_logic1[458] ;
+ wire \mprj_logic1[459] ;
+ wire \mprj_logic1[45] ;
+ wire \mprj_logic1[460] ;
+ wire \mprj_logic1[461] ;
+ wire \mprj_logic1[462] ;
+ wire \mprj_logic1[46] ;
+ wire \mprj_logic1[47] ;
+ wire \mprj_logic1[48] ;
+ wire \mprj_logic1[49] ;
+ wire \mprj_logic1[4] ;
+ wire \mprj_logic1[50] ;
+ wire \mprj_logic1[51] ;
+ wire \mprj_logic1[52] ;
+ wire \mprj_logic1[53] ;
+ wire \mprj_logic1[54] ;
+ wire \mprj_logic1[55] ;
+ wire \mprj_logic1[56] ;
+ wire \mprj_logic1[57] ;
+ wire \mprj_logic1[58] ;
+ wire \mprj_logic1[59] ;
+ wire \mprj_logic1[5] ;
+ wire \mprj_logic1[60] ;
+ wire \mprj_logic1[61] ;
+ wire \mprj_logic1[62] ;
+ wire \mprj_logic1[63] ;
+ wire \mprj_logic1[64] ;
+ wire \mprj_logic1[65] ;
+ wire \mprj_logic1[66] ;
+ wire \mprj_logic1[67] ;
+ wire \mprj_logic1[68] ;
+ wire \mprj_logic1[69] ;
+ wire \mprj_logic1[6] ;
+ wire \mprj_logic1[70] ;
+ wire \mprj_logic1[71] ;
+ wire \mprj_logic1[72] ;
+ wire \mprj_logic1[73] ;
+ wire \mprj_logic1[74] ;
+ wire \mprj_logic1[75] ;
+ wire \mprj_logic1[76] ;
+ wire \mprj_logic1[77] ;
+ wire \mprj_logic1[78] ;
+ wire \mprj_logic1[79] ;
+ wire \mprj_logic1[7] ;
+ wire \mprj_logic1[80] ;
+ wire \mprj_logic1[81] ;
+ wire \mprj_logic1[82] ;
+ wire \mprj_logic1[83] ;
+ wire \mprj_logic1[84] ;
+ wire \mprj_logic1[85] ;
+ wire \mprj_logic1[86] ;
+ wire \mprj_logic1[87] ;
+ wire \mprj_logic1[88] ;
+ wire \mprj_logic1[89] ;
+ wire \mprj_logic1[8] ;
+ wire \mprj_logic1[90] ;
+ wire \mprj_logic1[91] ;
+ wire \mprj_logic1[92] ;
+ wire \mprj_logic1[93] ;
+ wire \mprj_logic1[94] ;
+ wire \mprj_logic1[95] ;
+ wire \mprj_logic1[96] ;
+ wire \mprj_logic1[97] ;
+ wire \mprj_logic1[98] ;
+ wire \mprj_logic1[99] ;
+ wire \mprj_logic1[9] ;
+ wire mprj_vdd_logic1;
+ wire net1;
+ wire net10;
+ wire net100;
+ wire net1000;
+ wire net1001;
+ wire net1002;
+ wire net1003;
+ wire net1004;
+ wire net1005;
+ wire net1006;
+ wire net1007;
+ wire net1008;
+ wire net1009;
+ wire net101;
+ wire net1010;
+ wire net1011;
+ wire net1012;
+ wire net1013;
+ wire net1014;
+ wire net1015;
+ wire net1016;
+ wire net1017;
+ wire net1018;
+ wire net1019;
+ wire net102;
+ wire net1020;
+ wire net1021;
+ wire net1022;
+ wire net1023;
+ wire net1024;
+ wire net1025;
+ wire net1026;
+ wire net1027;
+ wire net1028;
+ wire net1029;
+ wire net103;
+ wire net1030;
+ wire net1031;
+ wire net1032;
+ wire net1033;
+ wire net1034;
+ wire net1035;
+ wire net1036;
+ wire net1037;
+ wire net1038;
+ wire net1039;
+ wire net104;
+ wire net1040;
+ wire net1041;
+ wire net1042;
+ wire net1043;
+ wire net1044;
+ wire net1045;
+ wire net1046;
+ wire net1047;
+ wire net1048;
+ wire net1049;
+ wire net105;
+ wire net1050;
+ wire net1051;
+ wire net1052;
+ wire net1053;
+ wire net1054;
+ wire net1055;
+ wire net1056;
+ wire net1057;
+ wire net1058;
+ wire net1059;
+ wire net106;
+ wire net1060;
+ wire net1061;
+ wire net1062;
+ wire net1063;
+ wire net1064;
+ wire net1065;
+ wire net1066;
+ wire net1067;
+ wire net1068;
+ wire net1069;
+ wire net107;
+ wire net1070;
+ wire net1071;
+ wire net1072;
+ wire net1073;
+ wire net1074;
+ wire net1075;
+ wire net1076;
+ wire net1077;
+ wire net1078;
+ wire net1079;
+ wire net108;
+ wire net1080;
+ wire net1081;
+ wire net1082;
+ wire net1083;
+ wire net1084;
+ wire net1085;
+ wire net1086;
+ wire net1087;
+ wire net1088;
+ wire net1089;
+ wire net109;
+ wire net1090;
+ wire net1091;
+ wire net1092;
+ wire net1093;
+ wire net1094;
+ wire net1095;
+ wire net1096;
+ wire net1097;
+ wire net1098;
+ wire net1099;
+ wire net11;
+ wire net110;
+ wire net1100;
+ wire net1101;
+ wire net1102;
+ wire net1103;
+ wire net1104;
+ wire net1105;
+ wire net1106;
+ wire net1107;
+ wire net1108;
+ wire net1109;
+ wire net111;
+ wire net1110;
+ wire net1111;
+ wire net1112;
+ wire net1113;
+ wire net1114;
+ wire net1115;
+ wire net1116;
+ wire net1117;
+ wire net1118;
+ wire net1119;
+ wire net112;
+ wire net1120;
+ wire net1121;
+ wire net1122;
+ wire net1123;
+ wire net1124;
+ wire net1125;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net12;
+ wire net120;
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+ wire net122;
+ wire net123;
+ wire net124;
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+ wire net14;
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+ wire net147;
+ wire net148;
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+ wire net15;
+ wire net150;
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+ wire net166;
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+ wire net178;
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+ wire net188;
+ wire net189;
+ wire net19;
+ wire net190;
+ wire net191;
+ wire net192;
+ wire net193;
+ wire net194;
+ wire net195;
+ wire net196;
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+ wire net198;
+ wire net199;
+ wire net2;
+ wire net20;
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+ wire net202;
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+ wire net208;
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+ wire net21;
+ wire net210;
+ wire net211;
+ wire net212;
+ wire net213;
+ wire net214;
+ wire net215;
+ wire net216;
+ wire net217;
+ wire net218;
+ wire net219;
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+ wire net223;
+ wire net224;
+ wire net225;
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+ wire net230;
+ wire net231;
+ wire net232;
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+ wire net234;
+ wire net235;
+ wire net236;
+ wire net237;
+ wire net238;
+ wire net239;
+ wire net24;
+ wire net240;
+ wire net241;
+ wire net242;
+ wire net243;
+ wire net244;
+ wire net245;
+ wire net246;
+ wire net247;
+ wire net248;
+ wire net249;
+ wire net25;
+ wire net250;
+ wire net251;
+ wire net252;
+ wire net253;
+ wire net254;
+ wire net255;
+ wire net256;
+ wire net257;
+ wire net258;
+ wire net259;
+ wire net26;
+ wire net260;
+ wire net261;
+ wire net262;
+ wire net263;
+ wire net264;
+ wire net265;
+ wire net266;
+ wire net267;
+ wire net268;
+ wire net269;
+ wire net27;
+ wire net270;
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+ wire net272;
+ wire net273;
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+ wire net276;
+ wire net277;
+ wire net278;
+ wire net279;
+ wire net28;
+ wire net280;
+ wire net281;
+ wire net282;
+ wire net283;
+ wire net284;
+ wire net285;
+ wire net286;
+ wire net287;
+ wire net288;
+ wire net289;
+ wire net29;
+ wire net290;
+ wire net291;
+ wire net292;
+ wire net293;
+ wire net294;
+ wire net295;
+ wire net296;
+ wire net297;
+ wire net298;
+ wire net299;
+ wire net3;
+ wire net30;
+ wire net300;
+ wire net301;
+ wire net302;
+ wire net303;
+ wire net304;
+ wire net305;
+ wire net306;
+ wire net307;
+ wire net308;
+ wire net309;
+ wire net31;
+ wire net310;
+ wire net311;
+ wire net312;
+ wire net313;
+ wire net314;
+ wire net315;
+ wire net316;
+ wire net317;
+ wire net318;
+ wire net319;
+ wire net32;
+ wire net320;
+ wire net321;
+ wire net322;
+ wire net323;
+ wire net324;
+ wire net325;
+ wire net326;
+ wire net327;
+ wire net328;
+ wire net329;
+ wire net33;
+ wire net330;
+ wire net331;
+ wire net332;
+ wire net333;
+ wire net334;
+ wire net335;
+ wire net336;
+ wire net337;
+ wire net338;
+ wire net339;
+ wire net34;
+ wire net340;
+ wire net341;
+ wire net342;
+ wire net343;
+ wire net344;
+ wire net345;
+ wire net346;
+ wire net347;
+ wire net348;
+ wire net349;
+ wire net35;
+ wire net350;
+ wire net351;
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+ wire net353;
+ wire net354;
+ wire net355;
+ wire net356;
+ wire net357;
+ wire net358;
+ wire net359;
+ wire net36;
+ wire net360;
+ wire net361;
+ wire net362;
+ wire net363;
+ wire net364;
+ wire net365;
+ wire net366;
+ wire net367;
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+ wire net37;
+ wire net370;
+ wire net371;
+ wire net372;
+ wire net373;
+ wire net374;
+ wire net375;
+ wire net376;
+ wire net377;
+ wire net378;
+ wire net379;
+ wire net38;
+ wire net380;
+ wire net381;
+ wire net382;
+ wire net383;
+ wire net384;
+ wire net385;
+ wire net386;
+ wire net387;
+ wire net388;
+ wire net389;
+ wire net39;
+ wire net390;
+ wire net391;
+ wire net392;
+ wire net393;
+ wire net394;
+ wire net395;
+ wire net396;
+ wire net397;
+ wire net398;
+ wire net399;
+ wire net4;
+ wire net40;
+ wire net400;
+ wire net401;
+ wire net402;
+ wire net403;
+ wire net404;
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+ wire net406;
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+ wire net41;
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+ wire net411;
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+ wire net423;
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+ wire net425;
+ wire net426;
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+ wire net428;
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+ wire net43;
+ wire net430;
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+ wire net44;
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+ wire net444;
+ wire net445;
+ wire net446;
+ wire net447;
+ wire net448;
+ wire net449;
+ wire net45;
+ wire net450;
+ wire net451;
+ wire net452;
+ wire net453;
+ wire net454;
+ wire net455;
+ wire net456;
+ wire net457;
+ wire net458;
+ wire net459;
+ wire net46;
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+ wire net461;
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+ wire net47;
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+ wire net472;
+ wire net473;
+ wire net474;
+ wire net475;
+ wire net476;
+ wire net477;
+ wire net478;
+ wire net479;
+ wire net48;
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+ wire net484;
+ wire net485;
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+ wire net49;
+ wire net490;
+ wire net491;
+ wire net492;
+ wire net493;
+ wire net494;
+ wire net495;
+ wire net496;
+ wire net497;
+ wire net498;
+ wire net499;
+ wire net5;
+ wire net50;
+ wire net500;
+ wire net501;
+ wire net502;
+ wire net503;
+ wire net504;
+ wire net505;
+ wire net506;
+ wire net507;
+ wire net508;
+ wire net509;
+ wire net51;
+ wire net510;
+ wire net511;
+ wire net512;
+ wire net513;
+ wire net514;
+ wire net515;
+ wire net516;
+ wire net517;
+ wire net518;
+ wire net519;
+ wire net52;
+ wire net520;
+ wire net521;
+ wire net522;
+ wire net523;
+ wire net524;
+ wire net525;
+ wire net526;
+ wire net527;
+ wire net528;
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+ wire net530;
+ wire net531;
+ wire net532;
+ wire net533;
+ wire net534;
+ wire net535;
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+ wire net537;
+ wire net538;
+ wire net539;
+ wire net54;
+ wire net540;
+ wire net541;
+ wire net542;
+ wire net543;
+ wire net544;
+ wire net545;
+ wire net546;
+ wire net547;
+ wire net548;
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+ wire net562;
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+ wire net566;
+ wire net567;
+ wire net568;
+ wire net569;
+ wire net57;
+ wire net570;
+ wire net571;
+ wire net572;
+ wire net573;
+ wire net574;
+ wire net575;
+ wire net576;
+ wire net577;
+ wire net578;
+ wire net579;
+ wire net58;
+ wire net580;
+ wire net581;
+ wire net582;
+ wire net583;
+ wire net584;
+ wire net585;
+ wire net586;
+ wire net587;
+ wire net588;
+ wire net589;
+ wire net59;
+ wire net590;
+ wire net591;
+ wire net592;
+ wire net593;
+ wire net594;
+ wire net595;
+ wire net596;
+ wire net597;
+ wire net598;
+ wire net599;
+ wire net6;
+ wire net60;
+ wire net600;
+ wire net601;
+ wire net602;
+ wire net603;
+ wire net604;
+ wire net605;
+ wire net606;
+ wire net607;
+ wire net608;
+ wire net609;
+ wire net61;
+ wire net610;
+ wire net611;
+ wire net612;
+ wire net613;
+ wire net614;
+ wire net615;
+ wire net616;
+ wire net617;
+ wire net618;
+ wire net619;
+ wire net62;
+ wire net620;
+ wire net621;
+ wire net622;
+ wire net623;
+ wire net624;
+ wire net625;
+ wire net626;
+ wire net627;
+ wire net628;
+ wire net629;
+ wire net63;
+ wire net630;
+ wire net631;
+ wire net632;
+ wire net633;
+ wire net634;
+ wire net635;
+ wire net636;
+ wire net637;
+ wire net638;
+ wire net639;
+ wire net64;
+ wire net640;
+ wire net641;
+ wire net642;
+ wire net643;
+ wire net644;
+ wire net645;
+ wire net646;
+ wire net647;
+ wire net648;
+ wire net649;
+ wire net65;
+ wire net650;
+ wire net651;
+ wire net652;
+ wire net653;
+ wire net654;
+ wire net655;
+ wire net656;
+ wire net657;
+ wire net658;
+ wire net659;
+ wire net66;
+ wire net660;
+ wire net661;
+ wire net662;
+ wire net663;
+ wire net664;
+ wire net665;
+ wire net666;
+ wire net667;
+ wire net668;
+ wire net669;
+ wire net67;
+ wire net670;
+ wire net671;
+ wire net672;
+ wire net673;
+ wire net674;
+ wire net675;
+ wire net676;
+ wire net677;
+ wire net678;
+ wire net679;
+ wire net68;
+ wire net680;
+ wire net681;
+ wire net682;
+ wire net683;
+ wire net684;
+ wire net685;
+ wire net686;
+ wire net687;
+ wire net688;
+ wire net689;
+ wire net69;
+ wire net690;
+ wire net691;
+ wire net692;
+ wire net693;
+ wire net694;
+ wire net695;
+ wire net696;
+ wire net697;
+ wire net698;
+ wire net699;
+ wire net7;
+ wire net70;
+ wire net700;
+ wire net701;
+ wire net702;
+ wire net703;
+ wire net704;
+ wire net705;
+ wire net706;
+ wire net707;
+ wire net708;
+ wire net709;
+ wire net71;
+ wire net710;
+ wire net711;
+ wire net712;
+ wire net713;
+ wire net714;
+ wire net715;
+ wire net716;
+ wire net717;
+ wire net718;
+ wire net719;
+ wire net72;
+ wire net720;
+ wire net721;
+ wire net722;
+ wire net723;
+ wire net724;
+ wire net725;
+ wire net726;
+ wire net727;
+ wire net728;
+ wire net729;
+ wire net73;
+ wire net730;
+ wire net731;
+ wire net732;
+ wire net733;
+ wire net734;
+ wire net735;
+ wire net736;
+ wire net737;
+ wire net738;
+ wire net739;
+ wire net74;
+ wire net740;
+ wire net741;
+ wire net742;
+ wire net743;
+ wire net744;
+ wire net745;
+ wire net746;
+ wire net747;
+ wire net748;
+ wire net749;
+ wire net75;
+ wire net750;
+ wire net751;
+ wire net752;
+ wire net753;
+ wire net754;
+ wire net755;
+ wire net756;
+ wire net757;
+ wire net758;
+ wire net759;
+ wire net76;
+ wire net760;
+ wire net761;
+ wire net762;
+ wire net763;
+ wire net764;
+ wire net765;
+ wire net766;
+ wire net767;
+ wire net768;
+ wire net769;
+ wire net77;
+ wire net770;
+ wire net771;
+ wire net772;
+ wire net773;
+ wire net774;
+ wire net775;
+ wire net776;
+ wire net777;
+ wire net778;
+ wire net779;
+ wire net78;
+ wire net780;
+ wire net781;
+ wire net782;
+ wire net783;
+ wire net784;
+ wire net785;
+ wire net786;
+ wire net787;
+ wire net788;
+ wire net789;
+ wire net79;
+ wire net790;
+ wire net791;
+ wire net792;
+ wire net793;
+ wire net794;
+ wire net795;
+ wire net796;
+ wire net797;
+ wire net798;
+ wire net799;
+ wire net8;
+ wire net80;
+ wire net800;
+ wire net801;
+ wire net802;
+ wire net803;
+ wire net804;
+ wire net805;
+ wire net806;
+ wire net807;
+ wire net808;
+ wire net809;
+ wire net81;
+ wire net810;
+ wire net811;
+ wire net812;
+ wire net813;
+ wire net814;
+ wire net815;
+ wire net816;
+ wire net817;
+ wire net818;
+ wire net819;
+ wire net82;
+ wire net820;
+ wire net821;
+ wire net822;
+ wire net823;
+ wire net824;
+ wire net825;
+ wire net826;
+ wire net827;
+ wire net828;
+ wire net829;
+ wire net83;
+ wire net830;
+ wire net831;
+ wire net832;
+ wire net833;
+ wire net834;
+ wire net835;
+ wire net836;
+ wire net837;
+ wire net838;
+ wire net839;
+ wire net84;
+ wire net840;
+ wire net841;
+ wire net842;
+ wire net843;
+ wire net844;
+ wire net845;
+ wire net846;
+ wire net847;
+ wire net848;
+ wire net849;
+ wire net85;
+ wire net850;
+ wire net851;
+ wire net852;
+ wire net853;
+ wire net854;
+ wire net855;
+ wire net856;
+ wire net857;
+ wire net858;
+ wire net859;
+ wire net86;
+ wire net860;
+ wire net861;
+ wire net862;
+ wire net863;
+ wire net864;
+ wire net865;
+ wire net866;
+ wire net867;
+ wire net868;
+ wire net869;
+ wire net87;
+ wire net870;
+ wire net871;
+ wire net872;
+ wire net873;
+ wire net874;
+ wire net875;
+ wire net876;
+ wire net877;
+ wire net878;
+ wire net879;
+ wire net88;
+ wire net880;
+ wire net881;
+ wire net882;
+ wire net883;
+ wire net884;
+ wire net885;
+ wire net886;
+ wire net887;
+ wire net888;
+ wire net889;
+ wire net89;
+ wire net890;
+ wire net891;
+ wire net892;
+ wire net893;
+ wire net894;
+ wire net895;
+ wire net896;
+ wire net897;
+ wire net898;
+ wire net899;
+ wire net9;
+ wire net90;
+ wire net900;
+ wire net901;
+ wire net902;
+ wire net903;
+ wire net904;
+ wire net905;
+ wire net906;
+ wire net907;
+ wire net908;
+ wire net909;
+ wire net91;
+ wire net910;
+ wire net911;
+ wire net912;
+ wire net913;
+ wire net914;
+ wire net915;
+ wire net916;
+ wire net917;
+ wire net918;
+ wire net919;
+ wire net92;
+ wire net920;
+ wire net921;
+ wire net922;
+ wire net923;
+ wire net924;
+ wire net925;
+ wire net926;
+ wire net927;
+ wire net928;
+ wire net929;
+ wire net93;
+ wire net930;
+ wire net931;
+ wire net932;
+ wire net933;
+ wire net934;
+ wire net935;
+ wire net936;
+ wire net937;
+ wire net938;
+ wire net939;
+ wire net94;
+ wire net940;
+ wire net941;
+ wire net942;
+ wire net943;
+ wire net944;
+ wire net945;
+ wire net946;
+ wire net947;
+ wire net948;
+ wire net949;
+ wire net95;
+ wire net950;
+ wire net951;
+ wire net952;
+ wire net953;
+ wire net954;
+ wire net955;
+ wire net956;
+ wire net957;
+ wire net958;
+ wire net959;
+ wire net96;
+ wire net960;
+ wire net961;
+ wire net962;
+ wire net963;
+ wire net964;
+ wire net965;
+ wire net966;
+ wire net967;
+ wire net968;
+ wire net969;
+ wire net97;
+ wire net970;
+ wire net971;
+ wire net972;
+ wire net973;
+ wire net974;
+ wire net975;
+ wire net976;
+ wire net977;
+ wire net978;
+ wire net979;
+ wire net98;
+ wire net980;
+ wire net981;
+ wire net982;
+ wire net983;
+ wire net984;
+ wire net985;
+ wire net986;
+ wire net987;
+ wire net988;
+ wire net989;
+ wire net99;
+ wire net990;
+ wire net991;
+ wire net992;
+ wire net993;
+ wire net994;
+ wire net995;
+ wire net996;
+ wire net997;
+ wire net998;
+ wire net999;
+ wire \user_irq_bar[0] ;
+ wire \user_irq_bar[1] ;
+ wire \user_irq_bar[2] ;
+ wire \user_irq_enable[0] ;
+ wire \user_irq_enable[1] ;
+ wire \user_irq_enable[2] ;
+ wire wb_in_enable;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA__329__A (.DIODE(net478),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__330__A (.DIODE(net479),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__331__A (.DIODE(net480),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__332__A (.DIODE(net481),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__333__A (.DIODE(net483),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__334__A (.DIODE(net484),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__335__A (.DIODE(net485),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__336__A (.DIODE(net486),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__337__A (.DIODE(net487),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__338__A (.DIODE(net488),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__339__A (.DIODE(net489),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__340__A (.DIODE(net490),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__341__A (.DIODE(net491),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__342__A (.DIODE(net492),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__343__A (.DIODE(net494),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__344__A (.DIODE(net495),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__345__A (.DIODE(net496),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__346__A (.DIODE(net497),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__347__A (.DIODE(net498),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__348__A (.DIODE(net499),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__349__A (.DIODE(net500),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__350__A (.DIODE(net501),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__351__A (.DIODE(net502),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__352__A (.DIODE(net503),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__353__A (.DIODE(net505),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__354__A (.DIODE(net506),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__355__A (.DIODE(net507),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__356__A (.DIODE(net508),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__357__A (.DIODE(net509),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__358__A (.DIODE(net510),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__359__A (.DIODE(net511),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__360__A (.DIODE(net512),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__361__A (.DIODE(net513),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__362__A (.DIODE(net514),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__363__A (.DIODE(net389),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__364__A (.DIODE(net390),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__365__A (.DIODE(net391),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__366__A (.DIODE(net392),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__367__A (.DIODE(net393),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__368__A (.DIODE(net394),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__369__A (.DIODE(net395),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__370__A (.DIODE(net396),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__371__A (.DIODE(net397),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__372__A (.DIODE(net398),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__373__A (.DIODE(net400),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__374__A (.DIODE(net401),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__375__A (.DIODE(net402),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__376__A (.DIODE(net403),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__377__A (.DIODE(net404),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__378__A (.DIODE(net405),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__379__A (.DIODE(net406),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__380__A (.DIODE(net407),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__381__A (.DIODE(net408),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__382__A (.DIODE(net409),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__383__A (.DIODE(net411),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__384__A (.DIODE(net412),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__385__A (.DIODE(net413),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__386__A (.DIODE(net414),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__387__A (.DIODE(net415),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__388__A (.DIODE(net416),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__389__A (.DIODE(net417),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__390__A (.DIODE(net418),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__391__A (.DIODE(net1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__392__A (.DIODE(net2),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__393__A (.DIODE(net549),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__394__A (.DIODE(net619),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__395__A (.DIODE(net620),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__396__A (.DIODE(net615),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__397__A (.DIODE(net616),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__398__A (.DIODE(net617),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__399__A (.DIODE(net618),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__400__A (.DIODE(net517),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__401__A (.DIODE(net528),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__402__A (.DIODE(net539),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__403__A (.DIODE(net542),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__404__A (.DIODE(net543),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__405__A (.DIODE(net544),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__406__A (.DIODE(net545),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__407__A (.DIODE(net546),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__408__A (.DIODE(net547),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__409__A (.DIODE(net548),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__410__A (.DIODE(net518),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__411__A (.DIODE(net519),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__412__A (.DIODE(net520),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__413__A (.DIODE(net521),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__414__A (.DIODE(net522),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__415__A (.DIODE(net523),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__416__A (.DIODE(net524),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__417__A (.DIODE(net525),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__418__A (.DIODE(net526),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__419__A (.DIODE(net527),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__420__A (.DIODE(net529),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__421__A (.DIODE(net530),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__422__A (.DIODE(net531),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__423__A (.DIODE(net532),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__424__A (.DIODE(net533),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__425__A (.DIODE(net534),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__426__A (.DIODE(net535),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__427__A (.DIODE(net536),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__428__A (.DIODE(net537),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__429__A (.DIODE(net538),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__430__A (.DIODE(net540),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__431__A (.DIODE(net541),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__432__A (.DIODE(net582),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__433__A (.DIODE(net593),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__434__A (.DIODE(net604),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__435__A (.DIODE(net607),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__436__A (.DIODE(net608),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__437__A (.DIODE(net609),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__438__A (.DIODE(net610),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__439__A (.DIODE(net611),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__440__A (.DIODE(net612),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__441__A (.DIODE(net613),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__442__A (.DIODE(net583),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__443__A (.DIODE(net584),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__444__A (.DIODE(net585),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__445__A (.DIODE(net586),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__446__A (.DIODE(net587),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__447__A (.DIODE(net588),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__448__A (.DIODE(net589),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__449__A (.DIODE(net590),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__450__A (.DIODE(net591),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__451__A (.DIODE(net592),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__452__A (.DIODE(net594),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__453__A (.DIODE(net595),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__454__A (.DIODE(net596),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__455__A (.DIODE(net597),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__456__A (.DIODE(net598),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__457__A (.DIODE(net599),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__458__A (.DIODE(net600),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__459__A (.DIODE(net601),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__460__A (.DIODE(net602),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__461__A (.DIODE(net603),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__462__A (.DIODE(net605),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__463__A (.DIODE(net606),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__464__A (.DIODE(net132),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__465__A (.DIODE(net171),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__466__A (.DIODE(net182),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__467__A (.DIODE(net193),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__468__A (.DIODE(net204),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__469__A (.DIODE(net215),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__470__A (.DIODE(net226),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__471__A (.DIODE(net237),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__472__A (.DIODE(net248),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__473__A (.DIODE(net259),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__474__A (.DIODE(net143),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__475__A (.DIODE(net154),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__476__A (.DIODE(net163),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__477__A (.DIODE(net164),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__478__A (.DIODE(net165),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__479__A (.DIODE(net166),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__480__A (.DIODE(net167),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__481__A (.DIODE(net168),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__482__A (.DIODE(net169),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__483__A (.DIODE(net170),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__484__A (.DIODE(net172),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__485__A (.DIODE(net173),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__486__A (.DIODE(net174),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__487__A (.DIODE(net175),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__488__A (.DIODE(net176),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__489__A (.DIODE(net177),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__490__A (.DIODE(net178),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__491__A (.DIODE(net179),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__492__A (.DIODE(net180),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__493__A (.DIODE(net181),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__494__A (.DIODE(net183),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__495__A (.DIODE(net184),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__496__A (.DIODE(net185),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__497__A (.DIODE(net186),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__498__A (.DIODE(net187),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__499__A (.DIODE(net188),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__500__A (.DIODE(net189),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__501__A (.DIODE(net190),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__502__A (.DIODE(net191),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__503__A (.DIODE(net192),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__504__A (.DIODE(net194),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__505__A (.DIODE(net195),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__506__A (.DIODE(net196),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__507__A (.DIODE(net197),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__508__A (.DIODE(net198),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__509__A (.DIODE(net199),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__510__A (.DIODE(net200),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__511__A (.DIODE(net201),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__512__A (.DIODE(net202),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__513__A (.DIODE(net203),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__514__A (.DIODE(net205),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__515__A (.DIODE(net206),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__516__A (.DIODE(net207),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__517__A (.DIODE(net208),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__518__A (.DIODE(net209),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__519__A (.DIODE(net210),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__520__A (.DIODE(net211),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__521__A (.DIODE(net212),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__522__A (.DIODE(net213),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__523__A (.DIODE(net214),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__524__A (.DIODE(net216),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__525__A (.DIODE(net217),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__526__A (.DIODE(net218),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__527__A (.DIODE(net219),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__528__A (.DIODE(net220),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__529__A (.DIODE(net221),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__530__A (.DIODE(net222),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__531__A (.DIODE(net223),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__532__A (.DIODE(net224),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__533__A (.DIODE(net225),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__534__A (.DIODE(net227),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__535__A (.DIODE(net228),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__536__A (.DIODE(net229),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__537__A (.DIODE(net230),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__538__A (.DIODE(net231),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__539__A (.DIODE(net232),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__540__A (.DIODE(net233),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__541__A (.DIODE(net234),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__542__A (.DIODE(net235),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__543__A (.DIODE(net236),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__544__A (.DIODE(net238),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__545__A (.DIODE(net239),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__546__A (.DIODE(net240),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__547__A (.DIODE(net241),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__548__A (.DIODE(net242),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__549__A (.DIODE(net243),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__550__A (.DIODE(net244),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__551__A (.DIODE(net245),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__552__A (.DIODE(net246),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__553__A (.DIODE(net247),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__554__A (.DIODE(net249),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__555__A (.DIODE(net250),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__556__A (.DIODE(net251),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__557__A (.DIODE(net252),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__558__A (.DIODE(net253),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__559__A (.DIODE(net254),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__560__A (.DIODE(net255),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__561__A (.DIODE(net256),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__562__A (.DIODE(net257),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__563__A (.DIODE(net258),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__564__A (.DIODE(net133),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__565__A (.DIODE(net134),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__566__A (.DIODE(net135),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__567__A (.DIODE(net136),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__568__A (.DIODE(net137),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__569__A (.DIODE(net138),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__570__A (.DIODE(net139),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__571__A (.DIODE(net140),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__572__A (.DIODE(net141),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__573__A (.DIODE(net142),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__574__A (.DIODE(net144),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__575__A (.DIODE(net145),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__576__A (.DIODE(net146),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__577__A (.DIODE(net147),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__578__A (.DIODE(net148),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__579__A (.DIODE(net149),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__580__A (.DIODE(net150),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__581__A (.DIODE(net151),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__582__A (.DIODE(net152),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__583__A (.DIODE(net153),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__584__A (.DIODE(net155),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__585__A (.DIODE(net156),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__586__A (.DIODE(net157),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__587__A (.DIODE(net158),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__588__A (.DIODE(net159),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__589__A (.DIODE(net160),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__590__A (.DIODE(net161),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__591__A (.DIODE(net162),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__592__A (.DIODE(net388),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__593__A (.DIODE(net427),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__594__A (.DIODE(net438),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__595__A (.DIODE(net449),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__596__A (.DIODE(net460),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__597__A (.DIODE(net471),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__598__A (.DIODE(net482),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__599__A (.DIODE(net493),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__600__A (.DIODE(net504),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__601__A (.DIODE(net515),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__602__A (.DIODE(net399),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__603__A (.DIODE(net410),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__604__A (.DIODE(net419),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__605__A (.DIODE(net420),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__606__A (.DIODE(net421),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__607__A (.DIODE(net422),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__608__A (.DIODE(net423),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__609__A (.DIODE(net424),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__610__A (.DIODE(net425),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__611__A (.DIODE(net426),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__612__A (.DIODE(net428),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__613__A (.DIODE(net429),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__614__A (.DIODE(net430),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__615__A (.DIODE(net431),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__616__A (.DIODE(net432),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__617__A (.DIODE(net433),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__618__A (.DIODE(net434),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__619__A (.DIODE(net435),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__620__A (.DIODE(net436),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__621__A (.DIODE(net437),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__622__A (.DIODE(net439),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__623__A (.DIODE(net440),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__624__A (.DIODE(net441),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__625__A (.DIODE(net442),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__626__A (.DIODE(net443),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__627__A (.DIODE(net444),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__628__A (.DIODE(net445),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__629__A (.DIODE(net446),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__630__A (.DIODE(net447),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__631__A (.DIODE(net448),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__632__A (.DIODE(net450),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__633__A (.DIODE(net451),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__634__A (.DIODE(net452),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__635__A (.DIODE(net453),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__636__A (.DIODE(net454),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__637__A (.DIODE(net455),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__638__A (.DIODE(net456),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__639__A (.DIODE(net457),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__640__A (.DIODE(net458),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__641__A (.DIODE(net459),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__642__A (.DIODE(net461),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__643__A (.DIODE(net462),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__644__A (.DIODE(net463),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__645__A (.DIODE(net464),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__646__A (.DIODE(net465),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__647__A (.DIODE(net466),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__648__A (.DIODE(net467),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__649__A (.DIODE(net468),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__650__A (.DIODE(net469),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__651__A (.DIODE(net470),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__652__A (.DIODE(net472),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__653__A (.DIODE(net473),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__654__A (.DIODE(net474),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__655__A (.DIODE(net475),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__656__A (.DIODE(net476),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA__657__A (.DIODE(net477),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input100_A (.DIODE(la_data_out_core[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input101_A (.DIODE(la_data_out_core[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input102_A (.DIODE(la_data_out_core[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input103_A (.DIODE(la_data_out_core[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input104_A (.DIODE(la_data_out_core[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input105_A (.DIODE(la_data_out_core[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input106_A (.DIODE(la_data_out_core[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input107_A (.DIODE(la_data_out_core[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input108_A (.DIODE(la_data_out_core[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input109_A (.DIODE(la_data_out_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input10_A (.DIODE(la_data_out_core[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input110_A (.DIODE(la_data_out_core[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input111_A (.DIODE(la_data_out_core[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input112_A (.DIODE(la_data_out_core[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input113_A (.DIODE(la_data_out_core[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input114_A (.DIODE(la_data_out_core[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input115_A (.DIODE(la_data_out_core[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input116_A (.DIODE(la_data_out_core[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input117_A (.DIODE(la_data_out_core[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input118_A (.DIODE(la_data_out_core[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input119_A (.DIODE(la_data_out_core[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input11_A (.DIODE(la_data_out_core[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input120_A (.DIODE(la_data_out_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input121_A (.DIODE(la_data_out_core[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input122_A (.DIODE(la_data_out_core[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input123_A (.DIODE(la_data_out_core[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input124_A (.DIODE(la_data_out_core[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input125_A (.DIODE(la_data_out_core[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input126_A (.DIODE(la_data_out_core[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input127_A (.DIODE(la_data_out_core[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input128_A (.DIODE(la_data_out_core[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input129_A (.DIODE(la_data_out_core[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input12_A (.DIODE(la_data_out_core[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input130_A (.DIODE(la_data_out_core[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input131_A (.DIODE(la_data_out_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input132_A (.DIODE(la_data_out_mprj[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input133_A (.DIODE(la_data_out_mprj[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input134_A (.DIODE(la_data_out_mprj[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input135_A (.DIODE(la_data_out_mprj[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input136_A (.DIODE(la_data_out_mprj[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input137_A (.DIODE(la_data_out_mprj[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input138_A (.DIODE(la_data_out_mprj[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input139_A (.DIODE(la_data_out_mprj[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input13_A (.DIODE(la_data_out_core[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input140_A (.DIODE(la_data_out_mprj[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input141_A (.DIODE(la_data_out_mprj[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input142_A (.DIODE(la_data_out_mprj[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input143_A (.DIODE(la_data_out_mprj[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input144_A (.DIODE(la_data_out_mprj[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input145_A (.DIODE(la_data_out_mprj[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input146_A (.DIODE(la_data_out_mprj[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input147_A (.DIODE(la_data_out_mprj[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input148_A (.DIODE(la_data_out_mprj[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input149_A (.DIODE(la_data_out_mprj[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input14_A (.DIODE(la_data_out_core[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input150_A (.DIODE(la_data_out_mprj[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input151_A (.DIODE(la_data_out_mprj[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input152_A (.DIODE(la_data_out_mprj[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input153_A (.DIODE(la_data_out_mprj[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input154_A (.DIODE(la_data_out_mprj[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input155_A (.DIODE(la_data_out_mprj[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input156_A (.DIODE(la_data_out_mprj[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input157_A (.DIODE(la_data_out_mprj[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input158_A (.DIODE(la_data_out_mprj[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input159_A (.DIODE(la_data_out_mprj[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input15_A (.DIODE(la_data_out_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input160_A (.DIODE(la_data_out_mprj[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input161_A (.DIODE(la_data_out_mprj[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input162_A (.DIODE(la_data_out_mprj[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input163_A (.DIODE(la_data_out_mprj[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input164_A (.DIODE(la_data_out_mprj[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input165_A (.DIODE(la_data_out_mprj[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input166_A (.DIODE(la_data_out_mprj[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input167_A (.DIODE(la_data_out_mprj[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input168_A (.DIODE(la_data_out_mprj[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input169_A (.DIODE(la_data_out_mprj[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input16_A (.DIODE(la_data_out_core[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input170_A (.DIODE(la_data_out_mprj[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input171_A (.DIODE(la_data_out_mprj[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input172_A (.DIODE(la_data_out_mprj[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input173_A (.DIODE(la_data_out_mprj[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input174_A (.DIODE(la_data_out_mprj[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input175_A (.DIODE(la_data_out_mprj[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input176_A (.DIODE(la_data_out_mprj[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input177_A (.DIODE(la_data_out_mprj[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input178_A (.DIODE(la_data_out_mprj[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input179_A (.DIODE(la_data_out_mprj[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input17_A (.DIODE(la_data_out_core[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input180_A (.DIODE(la_data_out_mprj[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input181_A (.DIODE(la_data_out_mprj[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input182_A (.DIODE(la_data_out_mprj[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input183_A (.DIODE(la_data_out_mprj[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input184_A (.DIODE(la_data_out_mprj[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input185_A (.DIODE(la_data_out_mprj[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input186_A (.DIODE(la_data_out_mprj[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input187_A (.DIODE(la_data_out_mprj[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input188_A (.DIODE(la_data_out_mprj[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input189_A (.DIODE(la_data_out_mprj[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input18_A (.DIODE(la_data_out_core[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input190_A (.DIODE(la_data_out_mprj[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input191_A (.DIODE(la_data_out_mprj[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input192_A (.DIODE(la_data_out_mprj[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input193_A (.DIODE(la_data_out_mprj[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input194_A (.DIODE(la_data_out_mprj[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input195_A (.DIODE(la_data_out_mprj[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input196_A (.DIODE(la_data_out_mprj[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input197_A (.DIODE(la_data_out_mprj[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input198_A (.DIODE(la_data_out_mprj[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input199_A (.DIODE(la_data_out_mprj[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input19_A (.DIODE(la_data_out_core[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(caravel_clk),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input200_A (.DIODE(la_data_out_mprj[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input201_A (.DIODE(la_data_out_mprj[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input202_A (.DIODE(la_data_out_mprj[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input203_A (.DIODE(la_data_out_mprj[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input204_A (.DIODE(la_data_out_mprj[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input205_A (.DIODE(la_data_out_mprj[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input206_A (.DIODE(la_data_out_mprj[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input207_A (.DIODE(la_data_out_mprj[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input208_A (.DIODE(la_data_out_mprj[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input209_A (.DIODE(la_data_out_mprj[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input20_A (.DIODE(la_data_out_core[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input210_A (.DIODE(la_data_out_mprj[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input211_A (.DIODE(la_data_out_mprj[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input212_A (.DIODE(la_data_out_mprj[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input213_A (.DIODE(la_data_out_mprj[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input214_A (.DIODE(la_data_out_mprj[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input215_A (.DIODE(la_data_out_mprj[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input216_A (.DIODE(la_data_out_mprj[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input217_A (.DIODE(la_data_out_mprj[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input218_A (.DIODE(la_data_out_mprj[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input219_A (.DIODE(la_data_out_mprj[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input21_A (.DIODE(la_data_out_core[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input220_A (.DIODE(la_data_out_mprj[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input221_A (.DIODE(la_data_out_mprj[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input222_A (.DIODE(la_data_out_mprj[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input223_A (.DIODE(la_data_out_mprj[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input224_A (.DIODE(la_data_out_mprj[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input225_A (.DIODE(la_data_out_mprj[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input226_A (.DIODE(la_data_out_mprj[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input227_A (.DIODE(la_data_out_mprj[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input228_A (.DIODE(la_data_out_mprj[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input229_A (.DIODE(la_data_out_mprj[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input22_A (.DIODE(la_data_out_core[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input230_A (.DIODE(la_data_out_mprj[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input231_A (.DIODE(la_data_out_mprj[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input232_A (.DIODE(la_data_out_mprj[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input233_A (.DIODE(la_data_out_mprj[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input234_A (.DIODE(la_data_out_mprj[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input235_A (.DIODE(la_data_out_mprj[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input236_A (.DIODE(la_data_out_mprj[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input237_A (.DIODE(la_data_out_mprj[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input238_A (.DIODE(la_data_out_mprj[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input239_A (.DIODE(la_data_out_mprj[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input23_A (.DIODE(la_data_out_core[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input240_A (.DIODE(la_data_out_mprj[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input241_A (.DIODE(la_data_out_mprj[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input242_A (.DIODE(la_data_out_mprj[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input243_A (.DIODE(la_data_out_mprj[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input244_A (.DIODE(la_data_out_mprj[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input245_A (.DIODE(la_data_out_mprj[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input246_A (.DIODE(la_data_out_mprj[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input247_A (.DIODE(la_data_out_mprj[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input248_A (.DIODE(la_data_out_mprj[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input249_A (.DIODE(la_data_out_mprj[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input24_A (.DIODE(la_data_out_core[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input250_A (.DIODE(la_data_out_mprj[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input251_A (.DIODE(la_data_out_mprj[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input252_A (.DIODE(la_data_out_mprj[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input253_A (.DIODE(la_data_out_mprj[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input254_A (.DIODE(la_data_out_mprj[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input255_A (.DIODE(la_data_out_mprj[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input256_A (.DIODE(la_data_out_mprj[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input257_A (.DIODE(la_data_out_mprj[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input258_A (.DIODE(la_data_out_mprj[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input259_A (.DIODE(la_data_out_mprj[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input25_A (.DIODE(la_data_out_core[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input260_A (.DIODE(la_iena_mprj[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input261_A (.DIODE(la_iena_mprj[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input262_A (.DIODE(la_iena_mprj[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input263_A (.DIODE(la_iena_mprj[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input264_A (.DIODE(la_iena_mprj[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input265_A (.DIODE(la_iena_mprj[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input266_A (.DIODE(la_iena_mprj[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input267_A (.DIODE(la_iena_mprj[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input268_A (.DIODE(la_iena_mprj[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input269_A (.DIODE(la_iena_mprj[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input26_A (.DIODE(la_data_out_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input270_A (.DIODE(la_iena_mprj[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input271_A (.DIODE(la_iena_mprj[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input272_A (.DIODE(la_iena_mprj[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input273_A (.DIODE(la_iena_mprj[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input274_A (.DIODE(la_iena_mprj[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input275_A (.DIODE(la_iena_mprj[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input276_A (.DIODE(la_iena_mprj[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input277_A (.DIODE(la_iena_mprj[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input278_A (.DIODE(la_iena_mprj[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input279_A (.DIODE(la_iena_mprj[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input27_A (.DIODE(la_data_out_core[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input280_A (.DIODE(la_iena_mprj[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input281_A (.DIODE(la_iena_mprj[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input282_A (.DIODE(la_iena_mprj[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input283_A (.DIODE(la_iena_mprj[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input284_A (.DIODE(la_iena_mprj[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input285_A (.DIODE(la_iena_mprj[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input286_A (.DIODE(la_iena_mprj[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input287_A (.DIODE(la_iena_mprj[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input288_A (.DIODE(la_iena_mprj[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input289_A (.DIODE(la_iena_mprj[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input28_A (.DIODE(la_data_out_core[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input290_A (.DIODE(la_iena_mprj[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input291_A (.DIODE(la_iena_mprj[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input292_A (.DIODE(la_iena_mprj[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input293_A (.DIODE(la_iena_mprj[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input294_A (.DIODE(la_iena_mprj[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input295_A (.DIODE(la_iena_mprj[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input296_A (.DIODE(la_iena_mprj[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input297_A (.DIODE(la_iena_mprj[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input298_A (.DIODE(la_iena_mprj[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input299_A (.DIODE(la_iena_mprj[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input29_A (.DIODE(la_data_out_core[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(caravel_clk2),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input300_A (.DIODE(la_iena_mprj[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input301_A (.DIODE(la_iena_mprj[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input302_A (.DIODE(la_iena_mprj[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input303_A (.DIODE(la_iena_mprj[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input304_A (.DIODE(la_iena_mprj[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input305_A (.DIODE(la_iena_mprj[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input306_A (.DIODE(la_iena_mprj[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input307_A (.DIODE(la_iena_mprj[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input308_A (.DIODE(la_iena_mprj[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input309_A (.DIODE(la_iena_mprj[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input30_A (.DIODE(la_data_out_core[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input310_A (.DIODE(la_iena_mprj[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input311_A (.DIODE(la_iena_mprj[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input312_A (.DIODE(la_iena_mprj[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input313_A (.DIODE(la_iena_mprj[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input314_A (.DIODE(la_iena_mprj[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input315_A (.DIODE(la_iena_mprj[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input316_A (.DIODE(la_iena_mprj[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input317_A (.DIODE(la_iena_mprj[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input318_A (.DIODE(la_iena_mprj[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input319_A (.DIODE(la_iena_mprj[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input31_A (.DIODE(la_data_out_core[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input320_A (.DIODE(la_iena_mprj[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input321_A (.DIODE(la_iena_mprj[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input322_A (.DIODE(la_iena_mprj[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input323_A (.DIODE(la_iena_mprj[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input324_A (.DIODE(la_iena_mprj[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input325_A (.DIODE(la_iena_mprj[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input326_A (.DIODE(la_iena_mprj[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input327_A (.DIODE(la_iena_mprj[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input328_A (.DIODE(la_iena_mprj[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input329_A (.DIODE(la_iena_mprj[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input32_A (.DIODE(la_data_out_core[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input330_A (.DIODE(la_iena_mprj[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input331_A (.DIODE(la_iena_mprj[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input332_A (.DIODE(la_iena_mprj[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input333_A (.DIODE(la_iena_mprj[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input334_A (.DIODE(la_iena_mprj[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input335_A (.DIODE(la_iena_mprj[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input336_A (.DIODE(la_iena_mprj[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input337_A (.DIODE(la_iena_mprj[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input338_A (.DIODE(la_iena_mprj[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input339_A (.DIODE(la_iena_mprj[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input33_A (.DIODE(la_data_out_core[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input340_A (.DIODE(la_iena_mprj[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input341_A (.DIODE(la_iena_mprj[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input342_A (.DIODE(la_iena_mprj[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input343_A (.DIODE(la_iena_mprj[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input344_A (.DIODE(la_iena_mprj[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input345_A (.DIODE(la_iena_mprj[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input346_A (.DIODE(la_iena_mprj[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input347_A (.DIODE(la_iena_mprj[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input348_A (.DIODE(la_iena_mprj[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input349_A (.DIODE(la_iena_mprj[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input34_A (.DIODE(la_data_out_core[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input350_A (.DIODE(la_iena_mprj[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input351_A (.DIODE(la_iena_mprj[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input352_A (.DIODE(la_iena_mprj[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input353_A (.DIODE(la_iena_mprj[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input354_A (.DIODE(la_iena_mprj[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input355_A (.DIODE(la_iena_mprj[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input356_A (.DIODE(la_iena_mprj[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input357_A (.DIODE(la_iena_mprj[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input358_A (.DIODE(la_iena_mprj[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input359_A (.DIODE(la_iena_mprj[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input35_A (.DIODE(la_data_out_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input360_A (.DIODE(la_iena_mprj[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input361_A (.DIODE(la_iena_mprj[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input362_A (.DIODE(la_iena_mprj[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input363_A (.DIODE(la_iena_mprj[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input364_A (.DIODE(la_iena_mprj[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input365_A (.DIODE(la_iena_mprj[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input366_A (.DIODE(la_iena_mprj[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input367_A (.DIODE(la_iena_mprj[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input368_A (.DIODE(la_iena_mprj[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input369_A (.DIODE(la_iena_mprj[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input36_A (.DIODE(la_data_out_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input370_A (.DIODE(la_iena_mprj[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input371_A (.DIODE(la_iena_mprj[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input372_A (.DIODE(la_iena_mprj[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input373_A (.DIODE(la_iena_mprj[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input374_A (.DIODE(la_iena_mprj[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input375_A (.DIODE(la_iena_mprj[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input376_A (.DIODE(la_iena_mprj[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input377_A (.DIODE(la_iena_mprj[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input378_A (.DIODE(la_iena_mprj[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input379_A (.DIODE(la_iena_mprj[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input37_A (.DIODE(la_data_out_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input380_A (.DIODE(la_iena_mprj[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input381_A (.DIODE(la_iena_mprj[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input382_A (.DIODE(la_iena_mprj[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input383_A (.DIODE(la_iena_mprj[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input384_A (.DIODE(la_iena_mprj[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input385_A (.DIODE(la_iena_mprj[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input386_A (.DIODE(la_iena_mprj[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input387_A (.DIODE(la_iena_mprj[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input388_A (.DIODE(la_oenb_mprj[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input389_A (.DIODE(la_oenb_mprj[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input38_A (.DIODE(la_data_out_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input390_A (.DIODE(la_oenb_mprj[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input391_A (.DIODE(la_oenb_mprj[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input392_A (.DIODE(la_oenb_mprj[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input393_A (.DIODE(la_oenb_mprj[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input394_A (.DIODE(la_oenb_mprj[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input395_A (.DIODE(la_oenb_mprj[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input396_A (.DIODE(la_oenb_mprj[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input397_A (.DIODE(la_oenb_mprj[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input398_A (.DIODE(la_oenb_mprj[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input399_A (.DIODE(la_oenb_mprj[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input39_A (.DIODE(la_data_out_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(caravel_rstn),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input400_A (.DIODE(la_oenb_mprj[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input401_A (.DIODE(la_oenb_mprj[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input402_A (.DIODE(la_oenb_mprj[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input403_A (.DIODE(la_oenb_mprj[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input404_A (.DIODE(la_oenb_mprj[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input405_A (.DIODE(la_oenb_mprj[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input406_A (.DIODE(la_oenb_mprj[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input407_A (.DIODE(la_oenb_mprj[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input408_A (.DIODE(la_oenb_mprj[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input409_A (.DIODE(la_oenb_mprj[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input40_A (.DIODE(la_data_out_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input410_A (.DIODE(la_oenb_mprj[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input411_A (.DIODE(la_oenb_mprj[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input412_A (.DIODE(la_oenb_mprj[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input413_A (.DIODE(la_oenb_mprj[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input414_A (.DIODE(la_oenb_mprj[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input415_A (.DIODE(la_oenb_mprj[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input416_A (.DIODE(la_oenb_mprj[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input417_A (.DIODE(la_oenb_mprj[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input418_A (.DIODE(la_oenb_mprj[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input419_A (.DIODE(la_oenb_mprj[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input41_A (.DIODE(la_data_out_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input420_A (.DIODE(la_oenb_mprj[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input421_A (.DIODE(la_oenb_mprj[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input422_A (.DIODE(la_oenb_mprj[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input423_A (.DIODE(la_oenb_mprj[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input424_A (.DIODE(la_oenb_mprj[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input425_A (.DIODE(la_oenb_mprj[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input426_A (.DIODE(la_oenb_mprj[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input427_A (.DIODE(la_oenb_mprj[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input428_A (.DIODE(la_oenb_mprj[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input429_A (.DIODE(la_oenb_mprj[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input42_A (.DIODE(la_data_out_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input430_A (.DIODE(la_oenb_mprj[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input431_A (.DIODE(la_oenb_mprj[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input432_A (.DIODE(la_oenb_mprj[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input433_A (.DIODE(la_oenb_mprj[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input434_A (.DIODE(la_oenb_mprj[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input435_A (.DIODE(la_oenb_mprj[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input436_A (.DIODE(la_oenb_mprj[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input437_A (.DIODE(la_oenb_mprj[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input438_A (.DIODE(la_oenb_mprj[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input439_A (.DIODE(la_oenb_mprj[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input43_A (.DIODE(la_data_out_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input440_A (.DIODE(la_oenb_mprj[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input441_A (.DIODE(la_oenb_mprj[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input442_A (.DIODE(la_oenb_mprj[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input443_A (.DIODE(la_oenb_mprj[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input444_A (.DIODE(la_oenb_mprj[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input445_A (.DIODE(la_oenb_mprj[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input446_A (.DIODE(la_oenb_mprj[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input447_A (.DIODE(la_oenb_mprj[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input448_A (.DIODE(la_oenb_mprj[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input449_A (.DIODE(la_oenb_mprj[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input44_A (.DIODE(la_data_out_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input450_A (.DIODE(la_oenb_mprj[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input451_A (.DIODE(la_oenb_mprj[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input452_A (.DIODE(la_oenb_mprj[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input453_A (.DIODE(la_oenb_mprj[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input454_A (.DIODE(la_oenb_mprj[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input455_A (.DIODE(la_oenb_mprj[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input456_A (.DIODE(la_oenb_mprj[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input457_A (.DIODE(la_oenb_mprj[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input458_A (.DIODE(la_oenb_mprj[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input459_A (.DIODE(la_oenb_mprj[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input45_A (.DIODE(la_data_out_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input460_A (.DIODE(la_oenb_mprj[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input461_A (.DIODE(la_oenb_mprj[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input462_A (.DIODE(la_oenb_mprj[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input463_A (.DIODE(la_oenb_mprj[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input464_A (.DIODE(la_oenb_mprj[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input465_A (.DIODE(la_oenb_mprj[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input466_A (.DIODE(la_oenb_mprj[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input467_A (.DIODE(la_oenb_mprj[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input468_A (.DIODE(la_oenb_mprj[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input469_A (.DIODE(la_oenb_mprj[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input46_A (.DIODE(la_data_out_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input470_A (.DIODE(la_oenb_mprj[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input471_A (.DIODE(la_oenb_mprj[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input472_A (.DIODE(la_oenb_mprj[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input473_A (.DIODE(la_oenb_mprj[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input474_A (.DIODE(la_oenb_mprj[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input475_A (.DIODE(la_oenb_mprj[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input476_A (.DIODE(la_oenb_mprj[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input477_A (.DIODE(la_oenb_mprj[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input478_A (.DIODE(la_oenb_mprj[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input479_A (.DIODE(la_oenb_mprj[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input47_A (.DIODE(la_data_out_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input480_A (.DIODE(la_oenb_mprj[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input481_A (.DIODE(la_oenb_mprj[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input482_A (.DIODE(la_oenb_mprj[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input483_A (.DIODE(la_oenb_mprj[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input484_A (.DIODE(la_oenb_mprj[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input485_A (.DIODE(la_oenb_mprj[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input486_A (.DIODE(la_oenb_mprj[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input487_A (.DIODE(la_oenb_mprj[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input488_A (.DIODE(la_oenb_mprj[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input489_A (.DIODE(la_oenb_mprj[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input48_A (.DIODE(la_data_out_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input490_A (.DIODE(la_oenb_mprj[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input491_A (.DIODE(la_oenb_mprj[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input492_A (.DIODE(la_oenb_mprj[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input493_A (.DIODE(la_oenb_mprj[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input494_A (.DIODE(la_oenb_mprj[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input495_A (.DIODE(la_oenb_mprj[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input496_A (.DIODE(la_oenb_mprj[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input497_A (.DIODE(la_oenb_mprj[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input498_A (.DIODE(la_oenb_mprj[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input499_A (.DIODE(la_oenb_mprj[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input49_A (.DIODE(la_data_out_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(la_data_out_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input500_A (.DIODE(la_oenb_mprj[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input501_A (.DIODE(la_oenb_mprj[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input502_A (.DIODE(la_oenb_mprj[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input503_A (.DIODE(la_oenb_mprj[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input504_A (.DIODE(la_oenb_mprj[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input505_A (.DIODE(la_oenb_mprj[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input506_A (.DIODE(la_oenb_mprj[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input507_A (.DIODE(la_oenb_mprj[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input508_A (.DIODE(la_oenb_mprj[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input509_A (.DIODE(la_oenb_mprj[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input50_A (.DIODE(la_data_out_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input510_A (.DIODE(la_oenb_mprj[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input511_A (.DIODE(la_oenb_mprj[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input512_A (.DIODE(la_oenb_mprj[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input513_A (.DIODE(la_oenb_mprj[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input514_A (.DIODE(la_oenb_mprj[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input515_A (.DIODE(la_oenb_mprj[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input516_A (.DIODE(mprj_ack_i_user),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input517_A (.DIODE(mprj_adr_o_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input518_A (.DIODE(mprj_adr_o_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input519_A (.DIODE(mprj_adr_o_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input51_A (.DIODE(la_data_out_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input520_A (.DIODE(mprj_adr_o_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input521_A (.DIODE(mprj_adr_o_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input522_A (.DIODE(mprj_adr_o_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input523_A (.DIODE(mprj_adr_o_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input524_A (.DIODE(mprj_adr_o_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input525_A (.DIODE(mprj_adr_o_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input526_A (.DIODE(mprj_adr_o_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input527_A (.DIODE(mprj_adr_o_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input528_A (.DIODE(mprj_adr_o_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input529_A (.DIODE(mprj_adr_o_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input52_A (.DIODE(la_data_out_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input530_A (.DIODE(mprj_adr_o_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input531_A (.DIODE(mprj_adr_o_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input532_A (.DIODE(mprj_adr_o_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input533_A (.DIODE(mprj_adr_o_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input534_A (.DIODE(mprj_adr_o_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input535_A (.DIODE(mprj_adr_o_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input536_A (.DIODE(mprj_adr_o_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input537_A (.DIODE(mprj_adr_o_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input538_A (.DIODE(mprj_adr_o_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input539_A (.DIODE(mprj_adr_o_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input53_A (.DIODE(la_data_out_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input540_A (.DIODE(mprj_adr_o_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input541_A (.DIODE(mprj_adr_o_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input542_A (.DIODE(mprj_adr_o_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input543_A (.DIODE(mprj_adr_o_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input544_A (.DIODE(mprj_adr_o_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input545_A (.DIODE(mprj_adr_o_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input546_A (.DIODE(mprj_adr_o_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input547_A (.DIODE(mprj_adr_o_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input548_A (.DIODE(mprj_adr_o_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input549_A (.DIODE(mprj_cyc_o_core),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input54_A (.DIODE(la_data_out_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input550_A (.DIODE(mprj_dat_i_user[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input551_A (.DIODE(mprj_dat_i_user[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input552_A (.DIODE(mprj_dat_i_user[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input553_A (.DIODE(mprj_dat_i_user[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input554_A (.DIODE(mprj_dat_i_user[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input555_A (.DIODE(mprj_dat_i_user[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input556_A (.DIODE(mprj_dat_i_user[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input557_A (.DIODE(mprj_dat_i_user[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input558_A (.DIODE(mprj_dat_i_user[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input559_A (.DIODE(mprj_dat_i_user[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input55_A (.DIODE(la_data_out_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input560_A (.DIODE(mprj_dat_i_user[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input561_A (.DIODE(mprj_dat_i_user[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input562_A (.DIODE(mprj_dat_i_user[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input563_A (.DIODE(mprj_dat_i_user[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input564_A (.DIODE(mprj_dat_i_user[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input565_A (.DIODE(mprj_dat_i_user[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input566_A (.DIODE(mprj_dat_i_user[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input567_A (.DIODE(mprj_dat_i_user[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input568_A (.DIODE(mprj_dat_i_user[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input569_A (.DIODE(mprj_dat_i_user[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input56_A (.DIODE(la_data_out_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input570_A (.DIODE(mprj_dat_i_user[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input571_A (.DIODE(mprj_dat_i_user[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input572_A (.DIODE(mprj_dat_i_user[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input573_A (.DIODE(mprj_dat_i_user[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input574_A (.DIODE(mprj_dat_i_user[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input575_A (.DIODE(mprj_dat_i_user[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input576_A (.DIODE(mprj_dat_i_user[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input577_A (.DIODE(mprj_dat_i_user[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input578_A (.DIODE(mprj_dat_i_user[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input579_A (.DIODE(mprj_dat_i_user[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input57_A (.DIODE(la_data_out_core[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input580_A (.DIODE(mprj_dat_i_user[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input581_A (.DIODE(mprj_dat_i_user[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input582_A (.DIODE(mprj_dat_o_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input583_A (.DIODE(mprj_dat_o_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input584_A (.DIODE(mprj_dat_o_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input585_A (.DIODE(mprj_dat_o_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input586_A (.DIODE(mprj_dat_o_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input587_A (.DIODE(mprj_dat_o_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input588_A (.DIODE(mprj_dat_o_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input589_A (.DIODE(mprj_dat_o_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input58_A (.DIODE(la_data_out_core[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input590_A (.DIODE(mprj_dat_o_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input591_A (.DIODE(mprj_dat_o_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input592_A (.DIODE(mprj_dat_o_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input593_A (.DIODE(mprj_dat_o_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input594_A (.DIODE(mprj_dat_o_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input595_A (.DIODE(mprj_dat_o_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input596_A (.DIODE(mprj_dat_o_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input597_A (.DIODE(mprj_dat_o_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input598_A (.DIODE(mprj_dat_o_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input599_A (.DIODE(mprj_dat_o_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input59_A (.DIODE(la_data_out_core[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(la_data_out_core[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input600_A (.DIODE(mprj_dat_o_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input601_A (.DIODE(mprj_dat_o_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input602_A (.DIODE(mprj_dat_o_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input603_A (.DIODE(mprj_dat_o_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input604_A (.DIODE(mprj_dat_o_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input605_A (.DIODE(mprj_dat_o_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input606_A (.DIODE(mprj_dat_o_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input607_A (.DIODE(mprj_dat_o_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input608_A (.DIODE(mprj_dat_o_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input609_A (.DIODE(mprj_dat_o_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input60_A (.DIODE(la_data_out_core[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input610_A (.DIODE(mprj_dat_o_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input611_A (.DIODE(mprj_dat_o_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input612_A (.DIODE(mprj_dat_o_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input613_A (.DIODE(mprj_dat_o_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input614_A (.DIODE(mprj_iena_wb),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input615_A (.DIODE(mprj_sel_o_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input616_A (.DIODE(mprj_sel_o_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input617_A (.DIODE(mprj_sel_o_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input618_A (.DIODE(mprj_sel_o_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input619_A (.DIODE(mprj_stb_o_core),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input61_A (.DIODE(la_data_out_core[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input620_A (.DIODE(mprj_we_o_core),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input621_A (.DIODE(user_irq_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input622_A (.DIODE(user_irq_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input623_A (.DIODE(user_irq_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input624_A (.DIODE(user_irq_ena[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input625_A (.DIODE(user_irq_ena[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input626_A (.DIODE(user_irq_ena[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input62_A (.DIODE(la_data_out_core[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input63_A (.DIODE(la_data_out_core[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input64_A (.DIODE(la_data_out_core[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input65_A (.DIODE(la_data_out_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input66_A (.DIODE(la_data_out_core[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input67_A (.DIODE(la_data_out_core[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input68_A (.DIODE(la_data_out_core[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input69_A (.DIODE(la_data_out_core[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input6_A (.DIODE(la_data_out_core[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input70_A (.DIODE(la_data_out_core[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input71_A (.DIODE(la_data_out_core[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input72_A (.DIODE(la_data_out_core[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input73_A (.DIODE(la_data_out_core[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input74_A (.DIODE(la_data_out_core[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input75_A (.DIODE(la_data_out_core[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input76_A (.DIODE(la_data_out_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input77_A (.DIODE(la_data_out_core[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input78_A (.DIODE(la_data_out_core[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input79_A (.DIODE(la_data_out_core[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input7_A (.DIODE(la_data_out_core[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input80_A (.DIODE(la_data_out_core[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input81_A (.DIODE(la_data_out_core[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input82_A (.DIODE(la_data_out_core[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input83_A (.DIODE(la_data_out_core[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input84_A (.DIODE(la_data_out_core[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input85_A (.DIODE(la_data_out_core[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input86_A (.DIODE(la_data_out_core[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input87_A (.DIODE(la_data_out_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input88_A (.DIODE(la_data_out_core[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input89_A (.DIODE(la_data_out_core[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input8_A (.DIODE(la_data_out_core[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input90_A (.DIODE(la_data_out_core[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input91_A (.DIODE(la_data_out_core[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input92_A (.DIODE(la_data_out_core[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input93_A (.DIODE(la_data_out_core[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input94_A (.DIODE(la_data_out_core[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input95_A (.DIODE(la_data_out_core[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input96_A (.DIODE(la_data_out_core[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input97_A (.DIODE(la_data_out_core[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input98_A (.DIODE(la_data_out_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input99_A (.DIODE(la_data_out_core[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input9_A (.DIODE(la_data_out_core[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[0]_A (.DIODE(_073_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[0]_TE (.DIODE(\la_data_out_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[100]_A (.DIODE(_074_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[100]_TE (.DIODE(\la_data_out_enable[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[101]_A (.DIODE(_075_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[101]_TE (.DIODE(\la_data_out_enable[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[102]_A (.DIODE(_076_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[102]_TE (.DIODE(\la_data_out_enable[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[103]_A (.DIODE(_077_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[103]_TE (.DIODE(\la_data_out_enable[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[104]_A (.DIODE(_078_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[104]_TE (.DIODE(\la_data_out_enable[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[105]_A (.DIODE(_079_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[105]_TE (.DIODE(\la_data_out_enable[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[106]_A (.DIODE(_080_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[106]_TE (.DIODE(\la_data_out_enable[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[107]_A (.DIODE(_081_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[107]_TE (.DIODE(\la_data_out_enable[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[108]_A (.DIODE(_082_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[108]_TE (.DIODE(\la_data_out_enable[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[109]_A (.DIODE(_083_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[109]_TE (.DIODE(\la_data_out_enable[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[10]_A (.DIODE(_084_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[10]_TE (.DIODE(\la_data_out_enable[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[110]_A (.DIODE(_085_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[110]_TE (.DIODE(\la_data_out_enable[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[111]_A (.DIODE(_086_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[111]_TE (.DIODE(\la_data_out_enable[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[112]_A (.DIODE(_087_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[112]_TE (.DIODE(\la_data_out_enable[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[113]_A (.DIODE(_088_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[113]_TE (.DIODE(\la_data_out_enable[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[114]_A (.DIODE(_089_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[114]_TE (.DIODE(\la_data_out_enable[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[115]_A (.DIODE(_090_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[115]_TE (.DIODE(\la_data_out_enable[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[116]_A (.DIODE(_091_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[116]_TE (.DIODE(\la_data_out_enable[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[117]_A (.DIODE(_092_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[117]_TE (.DIODE(\la_data_out_enable[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[118]_A (.DIODE(_093_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[118]_TE (.DIODE(\la_data_out_enable[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[119]_A (.DIODE(_094_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[119]_TE (.DIODE(\la_data_out_enable[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[11]_A (.DIODE(_095_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[11]_TE (.DIODE(\la_data_out_enable[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[120]_A (.DIODE(_096_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[120]_TE (.DIODE(\la_data_out_enable[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[121]_A (.DIODE(_097_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[121]_TE (.DIODE(\la_data_out_enable[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[122]_A (.DIODE(_098_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[122]_TE (.DIODE(\la_data_out_enable[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[123]_A (.DIODE(_099_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[123]_TE (.DIODE(\la_data_out_enable[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[124]_A (.DIODE(_100_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[124]_TE (.DIODE(\la_data_out_enable[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[125]_A (.DIODE(_101_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[125]_TE (.DIODE(\la_data_out_enable[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[126]_A (.DIODE(_102_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[126]_TE (.DIODE(\la_data_out_enable[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[127]_A (.DIODE(_103_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[127]_TE (.DIODE(\la_data_out_enable[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[12]_A (.DIODE(_104_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[12]_TE (.DIODE(\la_data_out_enable[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[13]_A (.DIODE(_105_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[13]_TE (.DIODE(\la_data_out_enable[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[14]_A (.DIODE(_106_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[14]_TE (.DIODE(\la_data_out_enable[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[15]_A (.DIODE(_107_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[15]_TE (.DIODE(\la_data_out_enable[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[16]_A (.DIODE(_108_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[16]_TE (.DIODE(\la_data_out_enable[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[17]_A (.DIODE(_109_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[17]_TE (.DIODE(\la_data_out_enable[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[18]_A (.DIODE(_110_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[18]_TE (.DIODE(\la_data_out_enable[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[19]_A (.DIODE(_111_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[19]_TE (.DIODE(\la_data_out_enable[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[1]_A (.DIODE(_112_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[1]_TE (.DIODE(\la_data_out_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[20]_A (.DIODE(_113_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[20]_TE (.DIODE(\la_data_out_enable[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[21]_A (.DIODE(_114_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[21]_TE (.DIODE(\la_data_out_enable[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[22]_A (.DIODE(_115_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[22]_TE (.DIODE(\la_data_out_enable[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[23]_A (.DIODE(_116_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[23]_TE (.DIODE(\la_data_out_enable[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[24]_A (.DIODE(_117_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[24]_TE (.DIODE(\la_data_out_enable[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[25]_A (.DIODE(_118_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[25]_TE (.DIODE(\la_data_out_enable[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[26]_A (.DIODE(_119_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[26]_TE (.DIODE(\la_data_out_enable[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[27]_A (.DIODE(_120_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[27]_TE (.DIODE(\la_data_out_enable[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[28]_A (.DIODE(_121_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[28]_TE (.DIODE(\la_data_out_enable[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[29]_A (.DIODE(_122_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[29]_TE (.DIODE(\la_data_out_enable[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[2]_A (.DIODE(_123_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[2]_TE (.DIODE(\la_data_out_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[30]_A (.DIODE(_124_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[30]_TE (.DIODE(\la_data_out_enable[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[31]_A (.DIODE(_125_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[31]_TE (.DIODE(\la_data_out_enable[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[32]_A (.DIODE(_126_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[32]_TE (.DIODE(\la_data_out_enable[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[33]_A (.DIODE(_127_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[33]_TE (.DIODE(\la_data_out_enable[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[34]_A (.DIODE(_128_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[34]_TE (.DIODE(\la_data_out_enable[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[35]_A (.DIODE(_129_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[35]_TE (.DIODE(\la_data_out_enable[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[36]_A (.DIODE(_130_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[36]_TE (.DIODE(\la_data_out_enable[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[37]_A (.DIODE(_131_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[37]_TE (.DIODE(\la_data_out_enable[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[38]_A (.DIODE(_132_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[38]_TE (.DIODE(\la_data_out_enable[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[39]_A (.DIODE(_133_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[39]_TE (.DIODE(\la_data_out_enable[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[3]_A (.DIODE(_134_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[3]_TE (.DIODE(\la_data_out_enable[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[40]_A (.DIODE(_135_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[40]_TE (.DIODE(\la_data_out_enable[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[41]_A (.DIODE(_136_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[41]_TE (.DIODE(\la_data_out_enable[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[42]_A (.DIODE(_137_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[42]_TE (.DIODE(\la_data_out_enable[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[43]_A (.DIODE(_138_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[43]_TE (.DIODE(\la_data_out_enable[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[44]_A (.DIODE(_139_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[44]_TE (.DIODE(\la_data_out_enable[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[45]_A (.DIODE(_140_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[45]_TE (.DIODE(\la_data_out_enable[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[46]_A (.DIODE(_141_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[46]_TE (.DIODE(\la_data_out_enable[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[47]_A (.DIODE(_142_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[47]_TE (.DIODE(\la_data_out_enable[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[48]_A (.DIODE(_143_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[48]_TE (.DIODE(\la_data_out_enable[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[49]_A (.DIODE(_144_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[49]_TE (.DIODE(\la_data_out_enable[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[4]_A (.DIODE(_145_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[4]_TE (.DIODE(\la_data_out_enable[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[50]_A (.DIODE(_146_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[50]_TE (.DIODE(\la_data_out_enable[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[51]_A (.DIODE(_147_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[51]_TE (.DIODE(\la_data_out_enable[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[52]_A (.DIODE(_148_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[52]_TE (.DIODE(\la_data_out_enable[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[53]_A (.DIODE(_149_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[53]_TE (.DIODE(\la_data_out_enable[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[54]_A (.DIODE(_150_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[54]_TE (.DIODE(\la_data_out_enable[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[55]_A (.DIODE(_151_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[55]_TE (.DIODE(\la_data_out_enable[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[56]_A (.DIODE(_152_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[56]_TE (.DIODE(\la_data_out_enable[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[57]_A (.DIODE(_153_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[57]_TE (.DIODE(\la_data_out_enable[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[58]_A (.DIODE(_154_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[58]_TE (.DIODE(\la_data_out_enable[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[59]_A (.DIODE(_155_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[59]_TE (.DIODE(\la_data_out_enable[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[5]_A (.DIODE(_156_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[5]_TE (.DIODE(\la_data_out_enable[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[60]_A (.DIODE(_157_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[60]_TE (.DIODE(\la_data_out_enable[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[61]_A (.DIODE(_158_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[61]_TE (.DIODE(\la_data_out_enable[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[62]_A (.DIODE(_159_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[62]_TE (.DIODE(\la_data_out_enable[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[63]_A (.DIODE(_160_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[63]_TE (.DIODE(\la_data_out_enable[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[64]_A (.DIODE(_161_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[64]_TE (.DIODE(\la_data_out_enable[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[65]_A (.DIODE(_162_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[65]_TE (.DIODE(\la_data_out_enable[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[66]_A (.DIODE(_163_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[66]_TE (.DIODE(\la_data_out_enable[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[67]_A (.DIODE(_164_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[67]_TE (.DIODE(\la_data_out_enable[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[68]_A (.DIODE(_165_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[68]_TE (.DIODE(\la_data_out_enable[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[69]_A (.DIODE(_166_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[69]_TE (.DIODE(\la_data_out_enable[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[6]_A (.DIODE(_167_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[6]_TE (.DIODE(\la_data_out_enable[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[70]_A (.DIODE(_168_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[70]_TE (.DIODE(\la_data_out_enable[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[71]_A (.DIODE(_169_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[71]_TE (.DIODE(\la_data_out_enable[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[72]_A (.DIODE(_170_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[72]_TE (.DIODE(\la_data_out_enable[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[73]_A (.DIODE(_171_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[73]_TE (.DIODE(\la_data_out_enable[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[74]_A (.DIODE(_172_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[74]_TE (.DIODE(\la_data_out_enable[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[75]_A (.DIODE(_173_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[75]_TE (.DIODE(\la_data_out_enable[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[76]_A (.DIODE(_174_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[76]_TE (.DIODE(\la_data_out_enable[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[77]_A (.DIODE(_175_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[77]_TE (.DIODE(\la_data_out_enable[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[78]_A (.DIODE(_176_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[78]_TE (.DIODE(\la_data_out_enable[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[79]_A (.DIODE(_177_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[79]_TE (.DIODE(\la_data_out_enable[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[7]_A (.DIODE(_178_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[7]_TE (.DIODE(\la_data_out_enable[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[80]_A (.DIODE(_179_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[80]_TE (.DIODE(\la_data_out_enable[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[81]_A (.DIODE(_180_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[81]_TE (.DIODE(\la_data_out_enable[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[82]_A (.DIODE(_181_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[82]_TE (.DIODE(\la_data_out_enable[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[83]_A (.DIODE(_182_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[83]_TE (.DIODE(\la_data_out_enable[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[84]_A (.DIODE(_183_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[84]_TE (.DIODE(\la_data_out_enable[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[85]_A (.DIODE(_184_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[85]_TE (.DIODE(\la_data_out_enable[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[86]_A (.DIODE(_185_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[86]_TE (.DIODE(\la_data_out_enable[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[87]_A (.DIODE(_186_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[87]_TE (.DIODE(\la_data_out_enable[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[88]_A (.DIODE(_187_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[88]_TE (.DIODE(\la_data_out_enable[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[89]_A (.DIODE(_188_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[89]_TE (.DIODE(\la_data_out_enable[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[8]_A (.DIODE(_189_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[8]_TE (.DIODE(\la_data_out_enable[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[90]_A (.DIODE(_190_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[90]_TE (.DIODE(\la_data_out_enable[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[91]_A (.DIODE(_191_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[91]_TE (.DIODE(\la_data_out_enable[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[92]_A (.DIODE(_192_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[92]_TE (.DIODE(\la_data_out_enable[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[93]_A (.DIODE(_193_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[93]_TE (.DIODE(\la_data_out_enable[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[94]_A (.DIODE(_194_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[94]_TE (.DIODE(\la_data_out_enable[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[95]_A (.DIODE(_195_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[95]_TE (.DIODE(\la_data_out_enable[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[96]_A (.DIODE(_196_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[96]_TE (.DIODE(\la_data_out_enable[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[97]_A (.DIODE(_197_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[97]_TE (.DIODE(\la_data_out_enable[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[98]_A (.DIODE(_198_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[98]_TE (.DIODE(\la_data_out_enable[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[99]_A (.DIODE(_199_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[99]_TE (.DIODE(\la_data_out_enable[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[9]_A (.DIODE(_200_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf[9]_TE (.DIODE(\la_data_out_enable[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[0]_A_N (.DIODE(net388),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[0]_B (.DIODE(\mprj_logic1[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[100]_A_N (.DIODE(net389),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[100]_B (.DIODE(\mprj_logic1[174] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[101]_A_N (.DIODE(net390),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[101]_B (.DIODE(\mprj_logic1[175] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[102]_A_N (.DIODE(net391),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[102]_B (.DIODE(\mprj_logic1[176] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[103]_A_N (.DIODE(net392),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[103]_B (.DIODE(\mprj_logic1[177] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[104]_A_N (.DIODE(net393),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[104]_B (.DIODE(\mprj_logic1[178] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[105]_A_N (.DIODE(net394),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[105]_B (.DIODE(\mprj_logic1[179] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[106]_A_N (.DIODE(net395),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[106]_B (.DIODE(\mprj_logic1[180] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[107]_A_N (.DIODE(net396),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[107]_B (.DIODE(\mprj_logic1[181] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[108]_A_N (.DIODE(net397),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[108]_B (.DIODE(\mprj_logic1[182] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[109]_A_N (.DIODE(net398),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[109]_B (.DIODE(\mprj_logic1[183] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[10]_A_N (.DIODE(net399),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[10]_B (.DIODE(\mprj_logic1[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[110]_A_N (.DIODE(net400),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[110]_B (.DIODE(\mprj_logic1[184] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[111]_A_N (.DIODE(net401),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[111]_B (.DIODE(\mprj_logic1[185] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[112]_A_N (.DIODE(net402),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[112]_B (.DIODE(\mprj_logic1[186] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[113]_A_N (.DIODE(net403),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[113]_B (.DIODE(\mprj_logic1[187] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[114]_A_N (.DIODE(net404),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[114]_B (.DIODE(\mprj_logic1[188] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[115]_A_N (.DIODE(net405),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[115]_B (.DIODE(\mprj_logic1[189] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[116]_A_N (.DIODE(net406),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[116]_B (.DIODE(\mprj_logic1[190] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[117]_A_N (.DIODE(net407),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[117]_B (.DIODE(\mprj_logic1[191] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[118]_A_N (.DIODE(net408),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[118]_B (.DIODE(\mprj_logic1[192] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[119]_A_N (.DIODE(net409),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[119]_B (.DIODE(\mprj_logic1[193] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[11]_A_N (.DIODE(net410),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[11]_B (.DIODE(\mprj_logic1[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[120]_A_N (.DIODE(net411),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[120]_B (.DIODE(\mprj_logic1[194] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[121]_A_N (.DIODE(net412),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[121]_B (.DIODE(\mprj_logic1[195] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[122]_A_N (.DIODE(net413),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[122]_B (.DIODE(\mprj_logic1[196] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[123]_A_N (.DIODE(net414),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[123]_B (.DIODE(\mprj_logic1[197] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[124]_A_N (.DIODE(net415),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[124]_B (.DIODE(\mprj_logic1[198] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[125]_A_N (.DIODE(net416),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[125]_B (.DIODE(\mprj_logic1[199] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[126]_A_N (.DIODE(net417),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[126]_B (.DIODE(\mprj_logic1[200] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[127]_A_N (.DIODE(net418),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[127]_B (.DIODE(\mprj_logic1[201] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[12]_A_N (.DIODE(net419),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[12]_B (.DIODE(\mprj_logic1[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[13]_A_N (.DIODE(net420),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[13]_B (.DIODE(\mprj_logic1[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[14]_A_N (.DIODE(net421),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[14]_B (.DIODE(\mprj_logic1[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[15]_A_N (.DIODE(net422),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[15]_B (.DIODE(\mprj_logic1[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[16]_A_N (.DIODE(net423),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[16]_B (.DIODE(\mprj_logic1[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[17]_A_N (.DIODE(net424),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[17]_B (.DIODE(\mprj_logic1[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[18]_A_N (.DIODE(net425),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[18]_B (.DIODE(\mprj_logic1[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[19]_A_N (.DIODE(net426),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[19]_B (.DIODE(\mprj_logic1[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[1]_A_N (.DIODE(net427),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[1]_B (.DIODE(\mprj_logic1[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[20]_A_N (.DIODE(net428),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[20]_B (.DIODE(\mprj_logic1[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[21]_A_N (.DIODE(net429),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[21]_B (.DIODE(\mprj_logic1[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[22]_A_N (.DIODE(net430),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[22]_B (.DIODE(\mprj_logic1[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[23]_A_N (.DIODE(net431),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[23]_B (.DIODE(\mprj_logic1[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[24]_A_N (.DIODE(net432),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[24]_B (.DIODE(\mprj_logic1[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[25]_A_N (.DIODE(net433),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[25]_B (.DIODE(\mprj_logic1[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[26]_A_N (.DIODE(net434),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[26]_B (.DIODE(\mprj_logic1[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[27]_A_N (.DIODE(net435),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[27]_B (.DIODE(\mprj_logic1[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[28]_A_N (.DIODE(net436),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[28]_B (.DIODE(\mprj_logic1[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[29]_A_N (.DIODE(net437),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[29]_B (.DIODE(\mprj_logic1[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[2]_A_N (.DIODE(net438),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[2]_B (.DIODE(\mprj_logic1[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[30]_A_N (.DIODE(net439),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[30]_B (.DIODE(\mprj_logic1[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[31]_A_N (.DIODE(net440),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[31]_B (.DIODE(\mprj_logic1[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[32]_A_N (.DIODE(net441),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[32]_B (.DIODE(\mprj_logic1[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[33]_A_N (.DIODE(net442),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[33]_B (.DIODE(\mprj_logic1[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[34]_A_N (.DIODE(net443),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[34]_B (.DIODE(\mprj_logic1[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[35]_A_N (.DIODE(net444),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[35]_B (.DIODE(\mprj_logic1[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[36]_A_N (.DIODE(net445),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[36]_B (.DIODE(\mprj_logic1[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[37]_A_N (.DIODE(net446),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[37]_B (.DIODE(\mprj_logic1[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[38]_A_N (.DIODE(net447),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[38]_B (.DIODE(\mprj_logic1[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[39]_A_N (.DIODE(net448),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[39]_B (.DIODE(\mprj_logic1[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[3]_A_N (.DIODE(net449),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[3]_B (.DIODE(\mprj_logic1[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[40]_A_N (.DIODE(net450),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[40]_B (.DIODE(\mprj_logic1[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[41]_A_N (.DIODE(net451),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[41]_B (.DIODE(\mprj_logic1[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[42]_A_N (.DIODE(net452),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[42]_B (.DIODE(\mprj_logic1[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[43]_A_N (.DIODE(net453),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[43]_B (.DIODE(\mprj_logic1[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[44]_A_N (.DIODE(net454),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[44]_B (.DIODE(\mprj_logic1[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[45]_A_N (.DIODE(net455),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[45]_B (.DIODE(\mprj_logic1[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[46]_A_N (.DIODE(net456),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[46]_B (.DIODE(\mprj_logic1[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[47]_A_N (.DIODE(net457),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[47]_B (.DIODE(\mprj_logic1[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[48]_A_N (.DIODE(net458),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[48]_B (.DIODE(\mprj_logic1[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[49]_A_N (.DIODE(net459),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[49]_B (.DIODE(\mprj_logic1[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[4]_A_N (.DIODE(net460),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[4]_B (.DIODE(\mprj_logic1[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[50]_A_N (.DIODE(net461),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[50]_B (.DIODE(\mprj_logic1[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[51]_A_N (.DIODE(net462),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[51]_B (.DIODE(\mprj_logic1[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[52]_A_N (.DIODE(net463),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[52]_B (.DIODE(\mprj_logic1[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[53]_A_N (.DIODE(net464),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[53]_B (.DIODE(\mprj_logic1[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[54]_A_N (.DIODE(net465),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[54]_B (.DIODE(\mprj_logic1[128] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[55]_A_N (.DIODE(net466),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[55]_B (.DIODE(\mprj_logic1[129] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[56]_A_N (.DIODE(net467),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[56]_B (.DIODE(\mprj_logic1[130] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[57]_A_N (.DIODE(net468),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[57]_B (.DIODE(\mprj_logic1[131] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[58]_A_N (.DIODE(net469),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[58]_B (.DIODE(\mprj_logic1[132] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[59]_A_N (.DIODE(net470),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[59]_B (.DIODE(\mprj_logic1[133] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[5]_A_N (.DIODE(net471),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[5]_B (.DIODE(\mprj_logic1[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[60]_A_N (.DIODE(net472),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[60]_B (.DIODE(\mprj_logic1[134] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[61]_A_N (.DIODE(net473),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[61]_B (.DIODE(\mprj_logic1[135] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[62]_A_N (.DIODE(net474),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[62]_B (.DIODE(\mprj_logic1[136] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[63]_A_N (.DIODE(net475),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[63]_B (.DIODE(\mprj_logic1[137] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[64]_A_N (.DIODE(net476),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[64]_B (.DIODE(\mprj_logic1[138] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[65]_A_N (.DIODE(net477),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[65]_B (.DIODE(\mprj_logic1[139] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[66]_A_N (.DIODE(net478),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[66]_B (.DIODE(\mprj_logic1[140] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[67]_A_N (.DIODE(net479),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[67]_B (.DIODE(\mprj_logic1[141] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[68]_A_N (.DIODE(net480),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[68]_B (.DIODE(\mprj_logic1[142] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[69]_A_N (.DIODE(net481),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[69]_B (.DIODE(\mprj_logic1[143] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[6]_A_N (.DIODE(net482),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[6]_B (.DIODE(\mprj_logic1[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[70]_A_N (.DIODE(net483),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[70]_B (.DIODE(\mprj_logic1[144] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[71]_A_N (.DIODE(net484),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[71]_B (.DIODE(\mprj_logic1[145] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[72]_A_N (.DIODE(net485),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[72]_B (.DIODE(\mprj_logic1[146] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[73]_A_N (.DIODE(net486),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[73]_B (.DIODE(\mprj_logic1[147] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[74]_A_N (.DIODE(net487),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[74]_B (.DIODE(\mprj_logic1[148] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[75]_A_N (.DIODE(net488),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[75]_B (.DIODE(\mprj_logic1[149] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[76]_A_N (.DIODE(net489),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[76]_B (.DIODE(\mprj_logic1[150] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[77]_A_N (.DIODE(net490),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[77]_B (.DIODE(\mprj_logic1[151] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[78]_A_N (.DIODE(net491),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[78]_B (.DIODE(\mprj_logic1[152] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[79]_A_N (.DIODE(net492),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[79]_B (.DIODE(\mprj_logic1[153] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[7]_A_N (.DIODE(net493),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[7]_B (.DIODE(\mprj_logic1[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[80]_A_N (.DIODE(net494),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[80]_B (.DIODE(\mprj_logic1[154] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[81]_A_N (.DIODE(net495),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[81]_B (.DIODE(\mprj_logic1[155] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[82]_A_N (.DIODE(net496),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[82]_B (.DIODE(\mprj_logic1[156] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[83]_A_N (.DIODE(net497),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[83]_B (.DIODE(\mprj_logic1[157] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[84]_A_N (.DIODE(net498),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[84]_B (.DIODE(\mprj_logic1[158] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[85]_A_N (.DIODE(net499),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[85]_B (.DIODE(\mprj_logic1[159] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[86]_A_N (.DIODE(net500),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[86]_B (.DIODE(\mprj_logic1[160] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[87]_A_N (.DIODE(net501),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[87]_B (.DIODE(\mprj_logic1[161] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[88]_A_N (.DIODE(net502),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[88]_B (.DIODE(\mprj_logic1[162] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[89]_A_N (.DIODE(net503),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[89]_B (.DIODE(\mprj_logic1[163] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[8]_A_N (.DIODE(net504),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[8]_B (.DIODE(\mprj_logic1[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[90]_A_N (.DIODE(net505),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[90]_B (.DIODE(\mprj_logic1[164] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[91]_A_N (.DIODE(net506),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[91]_B (.DIODE(\mprj_logic1[165] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[92]_A_N (.DIODE(net507),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[92]_B (.DIODE(\mprj_logic1[166] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[93]_A_N (.DIODE(net508),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[93]_B (.DIODE(\mprj_logic1[167] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[94]_A_N (.DIODE(net509),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[94]_B (.DIODE(\mprj_logic1[168] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[95]_A_N (.DIODE(net510),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[95]_B (.DIODE(\mprj_logic1[169] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[96]_A_N (.DIODE(net511),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[96]_B (.DIODE(\mprj_logic1[170] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[97]_A_N (.DIODE(net512),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[97]_B (.DIODE(\mprj_logic1[171] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[98]_A_N (.DIODE(net513),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[98]_B (.DIODE(\mprj_logic1[172] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[99]_A_N (.DIODE(net514),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[99]_B (.DIODE(\mprj_logic1[173] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[9]_A_N (.DIODE(net515),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_la_buf_enable[9]_B (.DIODE(\mprj_logic1[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj2_pwrgood_A (.DIODE(mprj2_logic1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj2_vdd_pwrgood_A (.DIODE(mprj2_vdd_logic1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[0]_A (.DIODE(_009_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[0]_TE (.DIODE(\mprj_logic1[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[10]_A (.DIODE(_010_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[10]_TE (.DIODE(\mprj_logic1[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[11]_A (.DIODE(_011_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[11]_TE (.DIODE(\mprj_logic1[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[12]_A (.DIODE(_012_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[12]_TE (.DIODE(\mprj_logic1[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[13]_A (.DIODE(_013_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[13]_TE (.DIODE(\mprj_logic1[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[14]_A (.DIODE(_014_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[14]_TE (.DIODE(\mprj_logic1[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[15]_A (.DIODE(_015_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[15]_TE (.DIODE(\mprj_logic1[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[16]_A (.DIODE(_016_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[16]_TE (.DIODE(\mprj_logic1[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[17]_A (.DIODE(_017_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[17]_TE (.DIODE(\mprj_logic1[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[18]_A (.DIODE(_018_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[18]_TE (.DIODE(\mprj_logic1[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[19]_A (.DIODE(_019_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[19]_TE (.DIODE(\mprj_logic1[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[1]_A (.DIODE(_020_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[1]_TE (.DIODE(\mprj_logic1[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[20]_A (.DIODE(_021_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[20]_TE (.DIODE(\mprj_logic1[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[21]_A (.DIODE(_022_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[21]_TE (.DIODE(\mprj_logic1[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[22]_A (.DIODE(_023_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[22]_TE (.DIODE(\mprj_logic1[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[23]_A (.DIODE(_024_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[23]_TE (.DIODE(\mprj_logic1[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[24]_A (.DIODE(_025_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[24]_TE (.DIODE(\mprj_logic1[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[25]_A (.DIODE(_026_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[25]_TE (.DIODE(\mprj_logic1[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[26]_A (.DIODE(_027_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[26]_TE (.DIODE(\mprj_logic1[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[27]_A (.DIODE(_028_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[27]_TE (.DIODE(\mprj_logic1[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[28]_A (.DIODE(_029_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[28]_TE (.DIODE(\mprj_logic1[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[29]_A (.DIODE(_030_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[29]_TE (.DIODE(\mprj_logic1[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[2]_A (.DIODE(_031_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[2]_TE (.DIODE(\mprj_logic1[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[30]_A (.DIODE(_032_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[30]_TE (.DIODE(\mprj_logic1[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[31]_A (.DIODE(_033_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[31]_TE (.DIODE(\mprj_logic1[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[3]_A (.DIODE(_034_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[3]_TE (.DIODE(\mprj_logic1[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[4]_A (.DIODE(_035_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[4]_TE (.DIODE(\mprj_logic1[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[5]_A (.DIODE(_036_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[5]_TE (.DIODE(\mprj_logic1[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[6]_A (.DIODE(_037_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[6]_TE (.DIODE(\mprj_logic1[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[7]_A (.DIODE(_038_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[7]_TE (.DIODE(\mprj_logic1[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[8]_A (.DIODE(_039_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[8]_TE (.DIODE(\mprj_logic1[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[9]_A (.DIODE(_040_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_adr_buf[9]_TE (.DIODE(\mprj_logic1[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_clk2_buf_A (.DIODE(_001_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_clk2_buf_TE (.DIODE(\mprj_logic1[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_clk_buf_A (.DIODE(_000_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_clk_buf_TE (.DIODE(\mprj_logic1[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_cyc_buf_A (.DIODE(_002_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_cyc_buf_TE (.DIODE(\mprj_logic1[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[0]_A (.DIODE(_041_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[0]_TE (.DIODE(\mprj_logic1[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[10]_A (.DIODE(_042_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[10]_TE (.DIODE(\mprj_logic1[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[11]_A (.DIODE(_043_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[11]_TE (.DIODE(\mprj_logic1[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[12]_A (.DIODE(_044_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[12]_TE (.DIODE(\mprj_logic1[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[13]_A (.DIODE(_045_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[13]_TE (.DIODE(\mprj_logic1[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[14]_A (.DIODE(_046_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[14]_TE (.DIODE(\mprj_logic1[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[15]_A (.DIODE(_047_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[15]_TE (.DIODE(\mprj_logic1[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[16]_A (.DIODE(_048_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[16]_TE (.DIODE(\mprj_logic1[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[17]_A (.DIODE(_049_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[17]_TE (.DIODE(\mprj_logic1[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[18]_A (.DIODE(_050_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[18]_TE (.DIODE(\mprj_logic1[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[19]_A (.DIODE(_051_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[19]_TE (.DIODE(\mprj_logic1[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[1]_A (.DIODE(_052_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[1]_TE (.DIODE(\mprj_logic1[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[20]_A (.DIODE(_053_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[20]_TE (.DIODE(\mprj_logic1[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[21]_A (.DIODE(_054_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[21]_TE (.DIODE(\mprj_logic1[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[22]_A (.DIODE(_055_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[22]_TE (.DIODE(\mprj_logic1[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[23]_A (.DIODE(_056_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[23]_TE (.DIODE(\mprj_logic1[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[24]_A (.DIODE(_057_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[24]_TE (.DIODE(\mprj_logic1[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[25]_A (.DIODE(_058_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[25]_TE (.DIODE(\mprj_logic1[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[26]_A (.DIODE(_059_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[26]_TE (.DIODE(\mprj_logic1[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[27]_A (.DIODE(_060_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[27]_TE (.DIODE(\mprj_logic1[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[28]_A (.DIODE(_061_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[28]_TE (.DIODE(\mprj_logic1[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[29]_A (.DIODE(_062_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[29]_TE (.DIODE(\mprj_logic1[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[2]_A (.DIODE(_063_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[2]_TE (.DIODE(\mprj_logic1[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[30]_A (.DIODE(_064_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[30]_TE (.DIODE(\mprj_logic1[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[31]_A (.DIODE(_065_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[31]_TE (.DIODE(\mprj_logic1[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[3]_A (.DIODE(_066_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[3]_TE (.DIODE(\mprj_logic1[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[4]_A (.DIODE(_067_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[4]_TE (.DIODE(\mprj_logic1[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[5]_A (.DIODE(_068_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[5]_TE (.DIODE(\mprj_logic1[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[6]_A (.DIODE(_069_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[6]_TE (.DIODE(\mprj_logic1[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[7]_A (.DIODE(_070_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[7]_TE (.DIODE(\mprj_logic1[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[8]_A (.DIODE(_071_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[8]_TE (.DIODE(\mprj_logic1[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[9]_A (.DIODE(_072_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_dat_buf[9]_TE (.DIODE(\mprj_logic1[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_pwrgood_A (.DIODE(\mprj_logic1[461] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_rstn_buf_A (.DIODE(net3),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_rstn_buf_TE (.DIODE(\mprj_logic1[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[0]_A (.DIODE(_005_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[0]_TE (.DIODE(\mprj_logic1[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[1]_A (.DIODE(_006_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[1]_TE (.DIODE(\mprj_logic1[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[2]_A (.DIODE(_007_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[2]_TE (.DIODE(\mprj_logic1[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[3]_A (.DIODE(_008_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_mprj_sel_buf[3]_TE (.DIODE(\mprj_logic1[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_stb_buf_A (.DIODE(_003_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_stb_buf_TE (.DIODE(\mprj_logic1[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_vdd_pwrgood_A (.DIODE(mprj_vdd_logic1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_we_buf_A (.DIODE(_004_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_mprj_we_buf_TE (.DIODE(\mprj_logic1[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1000_A (.DIODE(net1000),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1001_A (.DIODE(net1001),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1002_A (.DIODE(net1002),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1003_A (.DIODE(net1003),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1004_A (.DIODE(net1004),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1005_A (.DIODE(net1005),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1006_A (.DIODE(net1006),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1007_A (.DIODE(net1007),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1008_A (.DIODE(net1008),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1009_A (.DIODE(net1009),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1010_A (.DIODE(net1010),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1011_A (.DIODE(net1011),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1012_A (.DIODE(net1012),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1013_A (.DIODE(net1013),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1014_A (.DIODE(net1014),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1015_A (.DIODE(net1015),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1016_A (.DIODE(net1016),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1017_A (.DIODE(net1017),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1018_A (.DIODE(net1018),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1019_A (.DIODE(net1019),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1020_A (.DIODE(net1020),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1021_A (.DIODE(net1021),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1022_A (.DIODE(net1022),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1023_A (.DIODE(net1023),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1024_A (.DIODE(net1024),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1025_A (.DIODE(net1025),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1026_A (.DIODE(net1026),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1027_A (.DIODE(net1027),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1028_A (.DIODE(net1028),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1029_A (.DIODE(net1029),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1030_A (.DIODE(net1030),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1031_A (.DIODE(net1031),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1032_A (.DIODE(net1032),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1033_A (.DIODE(net1033),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1034_A (.DIODE(net1034),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1035_A (.DIODE(net1035),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1036_A (.DIODE(net1036),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1037_A (.DIODE(net1037),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1038_A (.DIODE(net1038),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1039_A (.DIODE(net1039),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1040_A (.DIODE(net1040),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1041_A (.DIODE(net1041),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1042_A (.DIODE(net1042),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1043_A (.DIODE(net1043),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1044_A (.DIODE(net1044),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1045_A (.DIODE(net1045),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1046_A (.DIODE(net1046),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1047_A (.DIODE(net1047),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1048_A (.DIODE(net1048),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1049_A (.DIODE(net1049),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1050_A (.DIODE(net1050),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1051_A (.DIODE(net1051),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1052_A (.DIODE(net1052),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1053_A (.DIODE(net1053),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1054_A (.DIODE(net1054),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1055_A (.DIODE(net1055),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1056_A (.DIODE(net1056),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1057_A (.DIODE(net1057),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1058_A (.DIODE(net1058),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1059_A (.DIODE(net1059),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1060_A (.DIODE(net1060),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1061_A (.DIODE(net1061),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1062_A (.DIODE(net1062),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1063_A (.DIODE(net1063),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1064_A (.DIODE(net1064),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1065_A (.DIODE(net1065),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1066_A (.DIODE(net1066),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1067_A (.DIODE(net1067),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1068_A (.DIODE(net1068),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1069_A (.DIODE(net1069),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1070_A (.DIODE(net1070),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1071_A (.DIODE(net1071),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1072_A (.DIODE(net1072),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1073_A (.DIODE(net1073),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1074_A (.DIODE(net1074),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1075_A (.DIODE(net1075),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1076_A (.DIODE(net1076),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1077_A (.DIODE(net1077),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1078_A (.DIODE(net1078),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1079_A (.DIODE(net1079),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1080_A (.DIODE(net1080),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1081_A (.DIODE(net1081),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1082_A (.DIODE(net1082),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1083_A (.DIODE(net1083),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1084_A (.DIODE(net1084),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1085_A (.DIODE(net1085),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1086_A (.DIODE(net1086),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1087_A (.DIODE(net1087),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1088_A (.DIODE(net1088),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1089_A (.DIODE(net1089),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1090_A (.DIODE(net1090),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1091_A (.DIODE(net1091),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1092_A (.DIODE(net1092),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1093_A (.DIODE(net1093),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1094_A (.DIODE(net1094),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1095_A (.DIODE(net1095),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1096_A (.DIODE(net1096),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1097_A (.DIODE(net1097),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1098_A (.DIODE(net1098),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1099_A (.DIODE(net1099),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1100_A (.DIODE(net1100),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1101_A (.DIODE(net1101),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1102_A (.DIODE(net1102),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1103_A (.DIODE(net1103),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1104_A (.DIODE(net1104),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1105_A (.DIODE(net1105),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1106_A (.DIODE(net1106),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1107_A (.DIODE(net1107),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1108_A (.DIODE(net1108),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1109_A (.DIODE(net1109),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1110_A (.DIODE(net1110),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1111_A (.DIODE(net1111),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1112_A (.DIODE(net1112),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1113_A (.DIODE(net1113),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1114_A (.DIODE(net1114),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1115_A (.DIODE(net1115),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1116_A (.DIODE(net1116),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1117_A (.DIODE(net1117),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1118_A (.DIODE(net1118),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1119_A (.DIODE(net1119),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1120_A (.DIODE(net1120),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1121_A (.DIODE(net1121),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1122_A (.DIODE(net1122),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1123_A (.DIODE(net1123),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output1124_A (.DIODE(net1124),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output627_A (.DIODE(net627),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output628_A (.DIODE(net628),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output629_A (.DIODE(net629),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output630_A (.DIODE(net630),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output631_A (.DIODE(net631),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output632_A (.DIODE(net632),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output633_A (.DIODE(net633),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output634_A (.DIODE(net634),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output635_A (.DIODE(net635),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output636_A (.DIODE(net636),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output637_A (.DIODE(net637),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output638_A (.DIODE(net638),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output639_A (.DIODE(net639),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output640_A (.DIODE(net640),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output641_A (.DIODE(net641),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output642_A (.DIODE(net642),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output643_A (.DIODE(net643),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output644_A (.DIODE(net644),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output645_A (.DIODE(net645),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output646_A (.DIODE(net646),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output647_A (.DIODE(net647),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output648_A (.DIODE(net648),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output649_A (.DIODE(net649),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output650_A (.DIODE(net650),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output651_A (.DIODE(net651),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output652_A (.DIODE(net652),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output653_A (.DIODE(net653),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output654_A (.DIODE(net654),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output655_A (.DIODE(net655),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output656_A (.DIODE(net656),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output657_A (.DIODE(net657),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output658_A (.DIODE(net658),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output659_A (.DIODE(net659),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output660_A (.DIODE(net660),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output661_A (.DIODE(net661),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output662_A (.DIODE(net662),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output663_A (.DIODE(net663),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output664_A (.DIODE(net664),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output665_A (.DIODE(net665),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output666_A (.DIODE(net666),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output667_A (.DIODE(net667),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output668_A (.DIODE(net668),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output669_A (.DIODE(net669),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output670_A (.DIODE(net670),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output671_A (.DIODE(net671),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output672_A (.DIODE(net672),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output673_A (.DIODE(net673),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output674_A (.DIODE(net674),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output675_A (.DIODE(net675),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output676_A (.DIODE(net676),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output677_A (.DIODE(net677),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output678_A (.DIODE(net678),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output679_A (.DIODE(net679),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output680_A (.DIODE(net680),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output681_A (.DIODE(net681),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output682_A (.DIODE(net682),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output683_A (.DIODE(net683),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output684_A (.DIODE(net684),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output685_A (.DIODE(net685),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output686_A (.DIODE(net686),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output687_A (.DIODE(net687),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output688_A (.DIODE(net688),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output689_A (.DIODE(net689),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output690_A (.DIODE(net690),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output691_A (.DIODE(net691),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output692_A (.DIODE(net692),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output693_A (.DIODE(net693),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output694_A (.DIODE(net694),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output695_A (.DIODE(net695),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output696_A (.DIODE(net696),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output697_A (.DIODE(net697),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output698_A (.DIODE(net698),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output699_A (.DIODE(net699),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output700_A (.DIODE(net700),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output701_A (.DIODE(net701),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output702_A (.DIODE(net702),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output703_A (.DIODE(net703),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output704_A (.DIODE(net704),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output705_A (.DIODE(net705),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output706_A (.DIODE(net706),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output707_A (.DIODE(net707),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output708_A (.DIODE(net708),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output709_A (.DIODE(net709),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output710_A (.DIODE(net710),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output711_A (.DIODE(net711),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output712_A (.DIODE(net712),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output713_A (.DIODE(net713),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output714_A (.DIODE(net714),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output715_A (.DIODE(net715),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output716_A (.DIODE(net716),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output717_A (.DIODE(net717),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output718_A (.DIODE(net718),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output719_A (.DIODE(net719),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output720_A (.DIODE(net720),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output721_A (.DIODE(net721),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output722_A (.DIODE(net722),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output723_A (.DIODE(net723),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output724_A (.DIODE(net724),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output725_A (.DIODE(net725),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output726_A (.DIODE(net726),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output727_A (.DIODE(net727),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output728_A (.DIODE(net728),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output729_A (.DIODE(net729),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output730_A (.DIODE(net730),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output731_A (.DIODE(net731),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output732_A (.DIODE(net732),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output733_A (.DIODE(net733),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output734_A (.DIODE(net734),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output735_A (.DIODE(net735),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output736_A (.DIODE(net736),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output737_A (.DIODE(net737),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output738_A (.DIODE(net738),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output739_A (.DIODE(net739),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output740_A (.DIODE(net740),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output741_A (.DIODE(net741),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output742_A (.DIODE(net742),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output743_A (.DIODE(net743),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output744_A (.DIODE(net744),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output745_A (.DIODE(net745),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output746_A (.DIODE(net746),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output747_A (.DIODE(net747),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output748_A (.DIODE(net748),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output749_A (.DIODE(net749),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output750_A (.DIODE(net750),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output751_A (.DIODE(net751),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output752_A (.DIODE(net752),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output753_A (.DIODE(net753),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output754_A (.DIODE(net754),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output755_A (.DIODE(net755),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output756_A (.DIODE(net756),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output757_A (.DIODE(net757),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output758_A (.DIODE(net758),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output759_A (.DIODE(net759),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output760_A (.DIODE(net760),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output761_A (.DIODE(net761),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output762_A (.DIODE(net762),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output763_A (.DIODE(net763),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output764_A (.DIODE(net764),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output765_A (.DIODE(net765),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output766_A (.DIODE(net766),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output767_A (.DIODE(net767),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output768_A (.DIODE(net768),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output769_A (.DIODE(net769),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output770_A (.DIODE(net770),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output771_A (.DIODE(net771),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output772_A (.DIODE(net772),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output773_A (.DIODE(net773),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output774_A (.DIODE(net774),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output775_A (.DIODE(net775),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output776_A (.DIODE(net776),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output777_A (.DIODE(net777),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output778_A (.DIODE(net778),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output779_A (.DIODE(net779),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output780_A (.DIODE(net780),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output781_A (.DIODE(net781),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output782_A (.DIODE(net782),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output783_A (.DIODE(net783),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output784_A (.DIODE(net784),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output785_A (.DIODE(net785),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output786_A (.DIODE(net786),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output787_A (.DIODE(net787),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output788_A (.DIODE(net788),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output789_A (.DIODE(net789),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output790_A (.DIODE(net790),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output791_A (.DIODE(net791),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output792_A (.DIODE(net792),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output793_A (.DIODE(net793),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output794_A (.DIODE(net794),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output795_A (.DIODE(net795),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output796_A (.DIODE(net796),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output797_A (.DIODE(net797),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output798_A (.DIODE(net798),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output799_A (.DIODE(net799),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output800_A (.DIODE(net800),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output801_A (.DIODE(net801),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output802_A (.DIODE(net802),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output803_A (.DIODE(net803),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output804_A (.DIODE(net804),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output805_A (.DIODE(net805),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output806_A (.DIODE(net806),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output807_A (.DIODE(net807),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output808_A (.DIODE(net808),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output809_A (.DIODE(net809),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output810_A (.DIODE(net810),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output811_A (.DIODE(net811),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output812_A (.DIODE(net812),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output813_A (.DIODE(net813),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output814_A (.DIODE(net814),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output815_A (.DIODE(net815),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output816_A (.DIODE(net816),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output817_A (.DIODE(net817),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output818_A (.DIODE(net818),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output819_A (.DIODE(net819),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output820_A (.DIODE(net820),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output821_A (.DIODE(net821),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output822_A (.DIODE(net822),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output823_A (.DIODE(net823),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output824_A (.DIODE(net824),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output825_A (.DIODE(net825),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output826_A (.DIODE(net826),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output827_A (.DIODE(net827),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output828_A (.DIODE(net828),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output829_A (.DIODE(net829),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output830_A (.DIODE(net830),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output831_A (.DIODE(net831),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output832_A (.DIODE(net832),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output833_A (.DIODE(net833),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output834_A (.DIODE(net834),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output835_A (.DIODE(net835),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output836_A (.DIODE(net836),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output837_A (.DIODE(net837),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output838_A (.DIODE(net838),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output839_A (.DIODE(net839),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output840_A (.DIODE(net840),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output841_A (.DIODE(net841),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output842_A (.DIODE(net842),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output843_A (.DIODE(net843),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output844_A (.DIODE(net844),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output845_A (.DIODE(net845),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output846_A (.DIODE(net846),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output847_A (.DIODE(net847),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output848_A (.DIODE(net848),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output849_A (.DIODE(net849),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output850_A (.DIODE(net850),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output851_A (.DIODE(net851),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output852_A (.DIODE(net852),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output853_A (.DIODE(net853),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output854_A (.DIODE(net854),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output855_A (.DIODE(net855),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output856_A (.DIODE(net856),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output857_A (.DIODE(net857),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output858_A (.DIODE(net858),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output859_A (.DIODE(net859),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output860_A (.DIODE(net860),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output861_A (.DIODE(net861),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output862_A (.DIODE(net862),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output863_A (.DIODE(net863),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output864_A (.DIODE(net864),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output865_A (.DIODE(net865),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output866_A (.DIODE(net866),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output867_A (.DIODE(net867),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output868_A (.DIODE(net868),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output869_A (.DIODE(net869),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output870_A (.DIODE(net870),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output871_A (.DIODE(net871),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output872_A (.DIODE(net872),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output873_A (.DIODE(net873),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output874_A (.DIODE(net874),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output875_A (.DIODE(net875),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output876_A (.DIODE(net876),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output877_A (.DIODE(net877),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output878_A (.DIODE(net878),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output879_A (.DIODE(net879),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output880_A (.DIODE(net880),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output881_A (.DIODE(net881),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output882_A (.DIODE(net882),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output883_A (.DIODE(net883),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output884_A (.DIODE(net884),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output885_A (.DIODE(net885),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output886_A (.DIODE(net886),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output887_A (.DIODE(net887),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output888_A (.DIODE(net888),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output889_A (.DIODE(net889),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output890_A (.DIODE(net890),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output891_A (.DIODE(net891),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output892_A (.DIODE(net892),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output893_A (.DIODE(net893),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output894_A (.DIODE(net894),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output895_A (.DIODE(net895),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output896_A (.DIODE(net896),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output897_A (.DIODE(net897),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output898_A (.DIODE(net898),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output899_A (.DIODE(net899),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output900_A (.DIODE(net900),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output901_A (.DIODE(net901),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output902_A (.DIODE(net902),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output903_A (.DIODE(net903),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output904_A (.DIODE(net904),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output905_A (.DIODE(net905),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output906_A (.DIODE(net906),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output907_A (.DIODE(net907),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output908_A (.DIODE(net908),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output909_A (.DIODE(net909),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output910_A (.DIODE(net910),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output911_A (.DIODE(net911),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output912_A (.DIODE(net912),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output913_A (.DIODE(net913),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output914_A (.DIODE(net914),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output915_A (.DIODE(net915),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output916_A (.DIODE(net916),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output917_A (.DIODE(net917),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output918_A (.DIODE(net918),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output919_A (.DIODE(net919),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output920_A (.DIODE(net920),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output921_A (.DIODE(net921),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output922_A (.DIODE(net922),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output923_A (.DIODE(net923),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output924_A (.DIODE(net924),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output925_A (.DIODE(net925),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output926_A (.DIODE(net926),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output927_A (.DIODE(net927),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output928_A (.DIODE(net928),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output929_A (.DIODE(net929),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output930_A (.DIODE(net930),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output931_A (.DIODE(net931),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output932_A (.DIODE(net932),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output933_A (.DIODE(net933),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output934_A (.DIODE(net934),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output935_A (.DIODE(net935),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output936_A (.DIODE(net936),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output937_A (.DIODE(net937),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output938_A (.DIODE(net938),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output939_A (.DIODE(net939),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output940_A (.DIODE(net940),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output941_A (.DIODE(net941),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output942_A (.DIODE(net942),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output943_A (.DIODE(net943),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output944_A (.DIODE(net944),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output945_A (.DIODE(net945),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output946_A (.DIODE(net946),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output947_A (.DIODE(net947),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output948_A (.DIODE(net948),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output949_A (.DIODE(net949),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output950_A (.DIODE(net950),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output951_A (.DIODE(net951),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output952_A (.DIODE(net952),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output953_A (.DIODE(net953),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output954_A (.DIODE(net954),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output955_A (.DIODE(net955),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output956_A (.DIODE(net956),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output957_A (.DIODE(net957),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output958_A (.DIODE(net958),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output959_A (.DIODE(net959),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output960_A (.DIODE(net960),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output961_A (.DIODE(net961),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output962_A (.DIODE(net962),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output963_A (.DIODE(net963),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output964_A (.DIODE(net964),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output965_A (.DIODE(net965),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output966_A (.DIODE(net966),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output967_A (.DIODE(net967),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output968_A (.DIODE(net968),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output969_A (.DIODE(net969),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output970_A (.DIODE(net970),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output971_A (.DIODE(net971),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output972_A (.DIODE(net972),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output973_A (.DIODE(net973),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output974_A (.DIODE(net974),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output975_A (.DIODE(net975),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output976_A (.DIODE(net976),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output977_A (.DIODE(net977),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output978_A (.DIODE(net978),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output979_A (.DIODE(net979),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output980_A (.DIODE(net980),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output981_A (.DIODE(net981),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output982_A (.DIODE(net982),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output983_A (.DIODE(net983),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output984_A (.DIODE(net984),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output985_A (.DIODE(net985),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output986_A (.DIODE(net986),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output987_A (.DIODE(net987),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output988_A (.DIODE(net988),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output989_A (.DIODE(net989),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output990_A (.DIODE(net990),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output991_A (.DIODE(net991),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output992_A (.DIODE(net992),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output993_A (.DIODE(net993),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output994_A (.DIODE(net994),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output995_A (.DIODE(net995),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output996_A (.DIODE(net996),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output997_A (.DIODE(net997),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output998_A (.DIODE(net998),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_output999_A (.DIODE(net999),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_repeater1125_A (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_buffers[0]_A (.DIODE(\user_irq_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_buffers[1]_A (.DIODE(\user_irq_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_buffers[2]_A (.DIODE(\user_irq_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[0]_A (.DIODE(net624),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[0]_B (.DIODE(\mprj_logic1[458] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[1]_A (.DIODE(net625),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[1]_B (.DIODE(\mprj_logic1[459] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[2]_A (.DIODE(net626),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_ena_buf[2]_B (.DIODE(\mprj_logic1[460] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[0]_A (.DIODE(net621),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[0]_B (.DIODE(\user_irq_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[1]_A (.DIODE(net622),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[1]_B (.DIODE(\user_irq_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[2]_A (.DIODE(net623),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_irq_gates[2]_B (.DIODE(\user_irq_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[0]_A (.DIODE(\la_data_in_mprj_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[100]_A (.DIODE(\la_data_in_mprj_bar[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[101]_A (.DIODE(\la_data_in_mprj_bar[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[102]_A (.DIODE(\la_data_in_mprj_bar[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[103]_A (.DIODE(\la_data_in_mprj_bar[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[104]_A (.DIODE(\la_data_in_mprj_bar[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[105]_A (.DIODE(\la_data_in_mprj_bar[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[106]_A (.DIODE(\la_data_in_mprj_bar[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[107]_A (.DIODE(\la_data_in_mprj_bar[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[108]_A (.DIODE(\la_data_in_mprj_bar[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[109]_A (.DIODE(\la_data_in_mprj_bar[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[10]_A (.DIODE(\la_data_in_mprj_bar[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[110]_A (.DIODE(\la_data_in_mprj_bar[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[111]_A (.DIODE(\la_data_in_mprj_bar[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[112]_A (.DIODE(\la_data_in_mprj_bar[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[113]_A (.DIODE(\la_data_in_mprj_bar[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[114]_A (.DIODE(\la_data_in_mprj_bar[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[115]_A (.DIODE(\la_data_in_mprj_bar[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[116]_A (.DIODE(\la_data_in_mprj_bar[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[117]_A (.DIODE(\la_data_in_mprj_bar[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[118]_A (.DIODE(\la_data_in_mprj_bar[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[119]_A (.DIODE(\la_data_in_mprj_bar[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[11]_A (.DIODE(\la_data_in_mprj_bar[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[120]_A (.DIODE(\la_data_in_mprj_bar[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[121]_A (.DIODE(\la_data_in_mprj_bar[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[122]_A (.DIODE(\la_data_in_mprj_bar[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[123]_A (.DIODE(\la_data_in_mprj_bar[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[124]_A (.DIODE(\la_data_in_mprj_bar[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[125]_A (.DIODE(\la_data_in_mprj_bar[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[126]_A (.DIODE(\la_data_in_mprj_bar[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[127]_A (.DIODE(\la_data_in_mprj_bar[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[12]_A (.DIODE(\la_data_in_mprj_bar[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[13]_A (.DIODE(\la_data_in_mprj_bar[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[14]_A (.DIODE(\la_data_in_mprj_bar[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[15]_A (.DIODE(\la_data_in_mprj_bar[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[16]_A (.DIODE(\la_data_in_mprj_bar[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[17]_A (.DIODE(\la_data_in_mprj_bar[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[18]_A (.DIODE(\la_data_in_mprj_bar[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[19]_A (.DIODE(\la_data_in_mprj_bar[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[1]_A (.DIODE(\la_data_in_mprj_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[20]_A (.DIODE(\la_data_in_mprj_bar[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[21]_A (.DIODE(\la_data_in_mprj_bar[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[22]_A (.DIODE(\la_data_in_mprj_bar[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[23]_A (.DIODE(\la_data_in_mprj_bar[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[24]_A (.DIODE(\la_data_in_mprj_bar[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[25]_A (.DIODE(\la_data_in_mprj_bar[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[26]_A (.DIODE(\la_data_in_mprj_bar[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[27]_A (.DIODE(\la_data_in_mprj_bar[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[28]_A (.DIODE(\la_data_in_mprj_bar[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[29]_A (.DIODE(\la_data_in_mprj_bar[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[2]_A (.DIODE(\la_data_in_mprj_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[30]_A (.DIODE(\la_data_in_mprj_bar[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[31]_A (.DIODE(\la_data_in_mprj_bar[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[32]_A (.DIODE(\la_data_in_mprj_bar[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[33]_A (.DIODE(\la_data_in_mprj_bar[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[34]_A (.DIODE(\la_data_in_mprj_bar[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[35]_A (.DIODE(\la_data_in_mprj_bar[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[36]_A (.DIODE(\la_data_in_mprj_bar[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[37]_A (.DIODE(\la_data_in_mprj_bar[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[38]_A (.DIODE(\la_data_in_mprj_bar[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[39]_A (.DIODE(\la_data_in_mprj_bar[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[3]_A (.DIODE(\la_data_in_mprj_bar[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[40]_A (.DIODE(\la_data_in_mprj_bar[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[41]_A (.DIODE(\la_data_in_mprj_bar[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[42]_A (.DIODE(\la_data_in_mprj_bar[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[43]_A (.DIODE(\la_data_in_mprj_bar[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[44]_A (.DIODE(\la_data_in_mprj_bar[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[45]_A (.DIODE(\la_data_in_mprj_bar[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[46]_A (.DIODE(\la_data_in_mprj_bar[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[47]_A (.DIODE(\la_data_in_mprj_bar[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[48]_A (.DIODE(\la_data_in_mprj_bar[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[49]_A (.DIODE(\la_data_in_mprj_bar[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[4]_A (.DIODE(\la_data_in_mprj_bar[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[50]_A (.DIODE(\la_data_in_mprj_bar[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[51]_A (.DIODE(\la_data_in_mprj_bar[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[52]_A (.DIODE(\la_data_in_mprj_bar[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[53]_A (.DIODE(\la_data_in_mprj_bar[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[54]_A (.DIODE(\la_data_in_mprj_bar[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[55]_A (.DIODE(\la_data_in_mprj_bar[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[56]_A (.DIODE(\la_data_in_mprj_bar[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[57]_A (.DIODE(\la_data_in_mprj_bar[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[58]_A (.DIODE(\la_data_in_mprj_bar[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[59]_A (.DIODE(\la_data_in_mprj_bar[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[5]_A (.DIODE(\la_data_in_mprj_bar[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[60]_A (.DIODE(\la_data_in_mprj_bar[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[61]_A (.DIODE(\la_data_in_mprj_bar[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[62]_A (.DIODE(\la_data_in_mprj_bar[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[63]_A (.DIODE(\la_data_in_mprj_bar[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[64]_A (.DIODE(\la_data_in_mprj_bar[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[65]_A (.DIODE(\la_data_in_mprj_bar[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[66]_A (.DIODE(\la_data_in_mprj_bar[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[67]_A (.DIODE(\la_data_in_mprj_bar[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[68]_A (.DIODE(\la_data_in_mprj_bar[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[69]_A (.DIODE(\la_data_in_mprj_bar[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[6]_A (.DIODE(\la_data_in_mprj_bar[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[70]_A (.DIODE(\la_data_in_mprj_bar[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[71]_A (.DIODE(\la_data_in_mprj_bar[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[72]_A (.DIODE(\la_data_in_mprj_bar[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[73]_A (.DIODE(\la_data_in_mprj_bar[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[74]_A (.DIODE(\la_data_in_mprj_bar[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[75]_A (.DIODE(\la_data_in_mprj_bar[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[76]_A (.DIODE(\la_data_in_mprj_bar[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[77]_A (.DIODE(\la_data_in_mprj_bar[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[78]_A (.DIODE(\la_data_in_mprj_bar[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[79]_A (.DIODE(\la_data_in_mprj_bar[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[7]_A (.DIODE(\la_data_in_mprj_bar[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[80]_A (.DIODE(\la_data_in_mprj_bar[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[81]_A (.DIODE(\la_data_in_mprj_bar[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[82]_A (.DIODE(\la_data_in_mprj_bar[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[83]_A (.DIODE(\la_data_in_mprj_bar[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[84]_A (.DIODE(\la_data_in_mprj_bar[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[85]_A (.DIODE(\la_data_in_mprj_bar[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[86]_A (.DIODE(\la_data_in_mprj_bar[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[87]_A (.DIODE(\la_data_in_mprj_bar[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[88]_A (.DIODE(\la_data_in_mprj_bar[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[89]_A (.DIODE(\la_data_in_mprj_bar[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[8]_A (.DIODE(\la_data_in_mprj_bar[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[90]_A (.DIODE(\la_data_in_mprj_bar[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[91]_A (.DIODE(\la_data_in_mprj_bar[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[92]_A (.DIODE(\la_data_in_mprj_bar[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[93]_A (.DIODE(\la_data_in_mprj_bar[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[94]_A (.DIODE(\la_data_in_mprj_bar[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[95]_A (.DIODE(\la_data_in_mprj_bar[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[96]_A (.DIODE(\la_data_in_mprj_bar[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[97]_A (.DIODE(\la_data_in_mprj_bar[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[98]_A (.DIODE(\la_data_in_mprj_bar[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[99]_A (.DIODE(\la_data_in_mprj_bar[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_buffers[9]_A (.DIODE(\la_data_in_mprj_bar[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[0]_A (.DIODE(net260),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[0]_B (.DIODE(\mprj_logic1[330] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[100]_A (.DIODE(net261),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[100]_B (.DIODE(\mprj_logic1[430] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[101]_A (.DIODE(net262),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[101]_B (.DIODE(\mprj_logic1[431] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[102]_A (.DIODE(net263),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[102]_B (.DIODE(\mprj_logic1[432] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[103]_A (.DIODE(net264),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[103]_B (.DIODE(\mprj_logic1[433] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[104]_A (.DIODE(net265),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[104]_B (.DIODE(\mprj_logic1[434] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[105]_A (.DIODE(net266),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[105]_B (.DIODE(\mprj_logic1[435] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[106]_A (.DIODE(net267),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[106]_B (.DIODE(\mprj_logic1[436] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[107]_A (.DIODE(net268),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[107]_B (.DIODE(\mprj_logic1[437] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[108]_A (.DIODE(net269),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[108]_B (.DIODE(\mprj_logic1[438] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[109]_A (.DIODE(net270),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[109]_B (.DIODE(\mprj_logic1[439] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[10]_A (.DIODE(net271),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[10]_B (.DIODE(\mprj_logic1[340] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[110]_A (.DIODE(net272),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[110]_B (.DIODE(\mprj_logic1[440] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[111]_A (.DIODE(net273),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[111]_B (.DIODE(\mprj_logic1[441] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[112]_A (.DIODE(net274),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[112]_B (.DIODE(\mprj_logic1[442] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[113]_A (.DIODE(net275),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[113]_B (.DIODE(\mprj_logic1[443] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[114]_A (.DIODE(net276),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[114]_B (.DIODE(\mprj_logic1[444] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[115]_A (.DIODE(net277),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[115]_B (.DIODE(\mprj_logic1[445] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[116]_A (.DIODE(net278),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[116]_B (.DIODE(\mprj_logic1[446] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[117]_A (.DIODE(net279),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[117]_B (.DIODE(\mprj_logic1[447] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[118]_A (.DIODE(net280),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[118]_B (.DIODE(\mprj_logic1[448] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[119]_A (.DIODE(net281),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[119]_B (.DIODE(\mprj_logic1[449] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[11]_A (.DIODE(net282),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[11]_B (.DIODE(\mprj_logic1[341] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[120]_A (.DIODE(net283),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[120]_B (.DIODE(\mprj_logic1[450] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[121]_A (.DIODE(net284),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[121]_B (.DIODE(\mprj_logic1[451] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[122]_A (.DIODE(net285),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[122]_B (.DIODE(\mprj_logic1[452] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[123]_A (.DIODE(net286),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[123]_B (.DIODE(\mprj_logic1[453] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[124]_A (.DIODE(net287),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[124]_B (.DIODE(\mprj_logic1[454] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[125]_A (.DIODE(net288),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[125]_B (.DIODE(\mprj_logic1[455] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[126]_A (.DIODE(net289),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[126]_B (.DIODE(\mprj_logic1[456] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[127]_A (.DIODE(net290),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[127]_B (.DIODE(\mprj_logic1[457] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[12]_A (.DIODE(net291),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[12]_B (.DIODE(\mprj_logic1[342] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[13]_A (.DIODE(net292),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[13]_B (.DIODE(\mprj_logic1[343] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[14]_A (.DIODE(net293),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[14]_B (.DIODE(\mprj_logic1[344] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[15]_A (.DIODE(net294),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[15]_B (.DIODE(\mprj_logic1[345] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[16]_A (.DIODE(net295),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[16]_B (.DIODE(\mprj_logic1[346] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[17]_A (.DIODE(net296),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[17]_B (.DIODE(\mprj_logic1[347] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[18]_A (.DIODE(net297),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[18]_B (.DIODE(\mprj_logic1[348] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[19]_A (.DIODE(net298),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[19]_B (.DIODE(\mprj_logic1[349] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[1]_A (.DIODE(net299),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[1]_B (.DIODE(\mprj_logic1[331] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[20]_A (.DIODE(net300),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[20]_B (.DIODE(\mprj_logic1[350] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[21]_A (.DIODE(net301),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[21]_B (.DIODE(\mprj_logic1[351] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[22]_A (.DIODE(net302),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[22]_B (.DIODE(\mprj_logic1[352] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[23]_A (.DIODE(net303),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[23]_B (.DIODE(\mprj_logic1[353] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[24]_A (.DIODE(net304),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[24]_B (.DIODE(\mprj_logic1[354] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[25]_A (.DIODE(net305),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[25]_B (.DIODE(\mprj_logic1[355] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[26]_A (.DIODE(net306),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[26]_B (.DIODE(\mprj_logic1[356] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[27]_A (.DIODE(net307),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[27]_B (.DIODE(\mprj_logic1[357] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[28]_A (.DIODE(net308),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[28]_B (.DIODE(\mprj_logic1[358] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[29]_A (.DIODE(net309),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[29]_B (.DIODE(\mprj_logic1[359] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[2]_A (.DIODE(net310),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[2]_B (.DIODE(\mprj_logic1[332] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[30]_A (.DIODE(net311),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[30]_B (.DIODE(\mprj_logic1[360] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[31]_A (.DIODE(net312),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[31]_B (.DIODE(\mprj_logic1[361] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[32]_A (.DIODE(net313),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[32]_B (.DIODE(\mprj_logic1[362] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[33]_A (.DIODE(net314),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[33]_B (.DIODE(\mprj_logic1[363] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[34]_A (.DIODE(net315),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[34]_B (.DIODE(\mprj_logic1[364] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[35]_A (.DIODE(net316),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[35]_B (.DIODE(\mprj_logic1[365] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[36]_A (.DIODE(net317),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[36]_B (.DIODE(\mprj_logic1[366] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[37]_A (.DIODE(net318),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[37]_B (.DIODE(\mprj_logic1[367] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[38]_A (.DIODE(net319),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[38]_B (.DIODE(\mprj_logic1[368] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[39]_A (.DIODE(net320),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[39]_B (.DIODE(\mprj_logic1[369] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[3]_A (.DIODE(net321),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[3]_B (.DIODE(\mprj_logic1[333] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[40]_A (.DIODE(net322),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[40]_B (.DIODE(\mprj_logic1[370] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[41]_A (.DIODE(net323),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[41]_B (.DIODE(\mprj_logic1[371] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[42]_A (.DIODE(net324),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[42]_B (.DIODE(\mprj_logic1[372] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[43]_A (.DIODE(net325),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[43]_B (.DIODE(\mprj_logic1[373] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[44]_A (.DIODE(net326),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[44]_B (.DIODE(\mprj_logic1[374] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[45]_A (.DIODE(net327),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[45]_B (.DIODE(\mprj_logic1[375] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[46]_A (.DIODE(net328),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[46]_B (.DIODE(\mprj_logic1[376] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[47]_A (.DIODE(net329),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[47]_B (.DIODE(\mprj_logic1[377] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[48]_A (.DIODE(net330),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[48]_B (.DIODE(\mprj_logic1[378] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[49]_A (.DIODE(net331),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[49]_B (.DIODE(\mprj_logic1[379] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[4]_A (.DIODE(net332),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[4]_B (.DIODE(\mprj_logic1[334] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[50]_A (.DIODE(net333),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[50]_B (.DIODE(\mprj_logic1[380] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[51]_A (.DIODE(net334),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[51]_B (.DIODE(\mprj_logic1[381] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[52]_A (.DIODE(net335),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[52]_B (.DIODE(\mprj_logic1[382] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[53]_A (.DIODE(net336),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[53]_B (.DIODE(\mprj_logic1[383] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[54]_A (.DIODE(net337),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[54]_B (.DIODE(\mprj_logic1[384] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[55]_A (.DIODE(net338),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[55]_B (.DIODE(\mprj_logic1[385] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[56]_A (.DIODE(net339),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[56]_B (.DIODE(\mprj_logic1[386] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[57]_A (.DIODE(net340),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[57]_B (.DIODE(\mprj_logic1[387] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[58]_A (.DIODE(net341),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[58]_B (.DIODE(\mprj_logic1[388] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[59]_A (.DIODE(net342),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[59]_B (.DIODE(\mprj_logic1[389] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[5]_A (.DIODE(net343),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[5]_B (.DIODE(\mprj_logic1[335] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[60]_A (.DIODE(net344),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[60]_B (.DIODE(\mprj_logic1[390] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[61]_A (.DIODE(net345),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[61]_B (.DIODE(\mprj_logic1[391] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[62]_A (.DIODE(net346),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[62]_B (.DIODE(\mprj_logic1[392] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[63]_A (.DIODE(net347),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[63]_B (.DIODE(\mprj_logic1[393] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[64]_A (.DIODE(net348),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[64]_B (.DIODE(\mprj_logic1[394] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[65]_A (.DIODE(net349),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[65]_B (.DIODE(\mprj_logic1[395] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[66]_A (.DIODE(net350),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[66]_B (.DIODE(\mprj_logic1[396] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[67]_A (.DIODE(net351),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[67]_B (.DIODE(\mprj_logic1[397] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[68]_A (.DIODE(net352),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[68]_B (.DIODE(\mprj_logic1[398] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[69]_A (.DIODE(net353),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[69]_B (.DIODE(\mprj_logic1[399] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[6]_A (.DIODE(net354),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[6]_B (.DIODE(\mprj_logic1[336] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[70]_A (.DIODE(net355),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[70]_B (.DIODE(\mprj_logic1[400] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[71]_A (.DIODE(net356),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[71]_B (.DIODE(\mprj_logic1[401] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[72]_A (.DIODE(net357),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[72]_B (.DIODE(\mprj_logic1[402] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[73]_A (.DIODE(net358),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[73]_B (.DIODE(\mprj_logic1[403] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[74]_A (.DIODE(net359),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[74]_B (.DIODE(\mprj_logic1[404] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[75]_A (.DIODE(net360),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[75]_B (.DIODE(\mprj_logic1[405] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[76]_A (.DIODE(net361),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[76]_B (.DIODE(\mprj_logic1[406] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[77]_A (.DIODE(net362),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[77]_B (.DIODE(\mprj_logic1[407] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[78]_A (.DIODE(net363),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[78]_B (.DIODE(\mprj_logic1[408] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[79]_A (.DIODE(net364),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[79]_B (.DIODE(\mprj_logic1[409] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[7]_A (.DIODE(net365),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[7]_B (.DIODE(\mprj_logic1[337] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[80]_A (.DIODE(net366),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[80]_B (.DIODE(\mprj_logic1[410] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[81]_A (.DIODE(net367),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[81]_B (.DIODE(\mprj_logic1[411] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[82]_A (.DIODE(net368),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[82]_B (.DIODE(\mprj_logic1[412] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[83]_A (.DIODE(net369),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[83]_B (.DIODE(\mprj_logic1[413] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[84]_A (.DIODE(net370),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[84]_B (.DIODE(\mprj_logic1[414] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[85]_A (.DIODE(net371),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[85]_B (.DIODE(\mprj_logic1[415] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[86]_A (.DIODE(net372),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[86]_B (.DIODE(\mprj_logic1[416] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[87]_A (.DIODE(net373),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[87]_B (.DIODE(\mprj_logic1[417] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[88]_A (.DIODE(net374),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[88]_B (.DIODE(\mprj_logic1[418] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[89]_A (.DIODE(net375),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[89]_B (.DIODE(\mprj_logic1[419] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[8]_A (.DIODE(net376),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[8]_B (.DIODE(\mprj_logic1[338] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[90]_A (.DIODE(net377),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[90]_B (.DIODE(\mprj_logic1[420] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[91]_A (.DIODE(net378),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[91]_B (.DIODE(\mprj_logic1[421] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[92]_A (.DIODE(net379),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[92]_B (.DIODE(\mprj_logic1[422] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[93]_A (.DIODE(net380),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[93]_B (.DIODE(\mprj_logic1[423] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[94]_A (.DIODE(net381),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[94]_B (.DIODE(\mprj_logic1[424] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[95]_A (.DIODE(net382),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[95]_B (.DIODE(\mprj_logic1[425] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[96]_A (.DIODE(net383),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[96]_B (.DIODE(\mprj_logic1[426] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[97]_A (.DIODE(net384),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[97]_B (.DIODE(\mprj_logic1[427] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[98]_A (.DIODE(net385),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[98]_B (.DIODE(\mprj_logic1[428] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[99]_A (.DIODE(net386),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[99]_B (.DIODE(\mprj_logic1[429] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[9]_A (.DIODE(net387),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_ena_buf[9]_B (.DIODE(\mprj_logic1[339] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[0]_A (.DIODE(net4),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[0]_B (.DIODE(\la_data_in_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[100]_A (.DIODE(net5),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[100]_B (.DIODE(\la_data_in_enable[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[101]_A (.DIODE(net6),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[101]_B (.DIODE(\la_data_in_enable[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[102]_A (.DIODE(net7),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[102]_B (.DIODE(\la_data_in_enable[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[103]_A (.DIODE(net8),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[103]_B (.DIODE(\la_data_in_enable[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[104]_A (.DIODE(net9),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[104]_B (.DIODE(\la_data_in_enable[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[105]_A (.DIODE(net10),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[105]_B (.DIODE(\la_data_in_enable[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[106]_A (.DIODE(net11),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[106]_B (.DIODE(\la_data_in_enable[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[107]_A (.DIODE(net12),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[107]_B (.DIODE(\la_data_in_enable[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[108]_A (.DIODE(net13),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[108]_B (.DIODE(\la_data_in_enable[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[109]_A (.DIODE(net14),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[109]_B (.DIODE(\la_data_in_enable[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[10]_A (.DIODE(net15),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[10]_B (.DIODE(\la_data_in_enable[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[110]_A (.DIODE(net16),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[110]_B (.DIODE(\la_data_in_enable[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[111]_A (.DIODE(net17),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[111]_B (.DIODE(\la_data_in_enable[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[112]_A (.DIODE(net18),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[112]_B (.DIODE(\la_data_in_enable[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[113]_A (.DIODE(net19),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[113]_B (.DIODE(\la_data_in_enable[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[114]_A (.DIODE(net20),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[114]_B (.DIODE(\la_data_in_enable[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[115]_A (.DIODE(net21),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[115]_B (.DIODE(\la_data_in_enable[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[116]_A (.DIODE(net22),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[116]_B (.DIODE(\la_data_in_enable[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[117]_A (.DIODE(net23),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[117]_B (.DIODE(\la_data_in_enable[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[118]_A (.DIODE(net24),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[118]_B (.DIODE(\la_data_in_enable[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[119]_A (.DIODE(net25),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[119]_B (.DIODE(\la_data_in_enable[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[11]_A (.DIODE(net26),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[11]_B (.DIODE(\la_data_in_enable[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[120]_A (.DIODE(net27),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[120]_B (.DIODE(\la_data_in_enable[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[121]_A (.DIODE(net28),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[121]_B (.DIODE(\la_data_in_enable[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[122]_A (.DIODE(net29),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[122]_B (.DIODE(\la_data_in_enable[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[123]_A (.DIODE(net30),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[123]_B (.DIODE(\la_data_in_enable[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[124]_A (.DIODE(net31),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[124]_B (.DIODE(\la_data_in_enable[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[125]_A (.DIODE(net32),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[125]_B (.DIODE(\la_data_in_enable[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[126]_A (.DIODE(net33),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[126]_B (.DIODE(\la_data_in_enable[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[127]_A (.DIODE(net34),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[127]_B (.DIODE(\la_data_in_enable[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[12]_A (.DIODE(net35),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[12]_B (.DIODE(\la_data_in_enable[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[13]_A (.DIODE(net36),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[13]_B (.DIODE(\la_data_in_enable[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[14]_A (.DIODE(net37),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[14]_B (.DIODE(\la_data_in_enable[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[15]_A (.DIODE(net38),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[15]_B (.DIODE(\la_data_in_enable[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[16]_A (.DIODE(net39),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[16]_B (.DIODE(\la_data_in_enable[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[17]_A (.DIODE(net40),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[17]_B (.DIODE(\la_data_in_enable[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[18]_A (.DIODE(net41),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[18]_B (.DIODE(\la_data_in_enable[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[19]_A (.DIODE(net42),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[19]_B (.DIODE(\la_data_in_enable[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[1]_A (.DIODE(net43),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[1]_B (.DIODE(\la_data_in_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[20]_A (.DIODE(net44),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[20]_B (.DIODE(\la_data_in_enable[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[21]_A (.DIODE(net45),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[21]_B (.DIODE(\la_data_in_enable[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[22]_A (.DIODE(net46),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[22]_B (.DIODE(\la_data_in_enable[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[23]_A (.DIODE(net47),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[23]_B (.DIODE(\la_data_in_enable[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[24]_A (.DIODE(net48),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[24]_B (.DIODE(\la_data_in_enable[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[25]_A (.DIODE(net49),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[25]_B (.DIODE(\la_data_in_enable[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[26]_A (.DIODE(net50),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[26]_B (.DIODE(\la_data_in_enable[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[27]_A (.DIODE(net51),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[27]_B (.DIODE(\la_data_in_enable[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[28]_A (.DIODE(net52),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[28]_B (.DIODE(\la_data_in_enable[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[29]_A (.DIODE(net53),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[29]_B (.DIODE(\la_data_in_enable[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[2]_A (.DIODE(net54),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[2]_B (.DIODE(\la_data_in_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[30]_A (.DIODE(net55),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[30]_B (.DIODE(\la_data_in_enable[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[31]_A (.DIODE(net56),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[31]_B (.DIODE(\la_data_in_enable[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[32]_A (.DIODE(net57),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[32]_B (.DIODE(\la_data_in_enable[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[33]_A (.DIODE(net58),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[33]_B (.DIODE(\la_data_in_enable[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[34]_A (.DIODE(net59),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[34]_B (.DIODE(\la_data_in_enable[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[35]_A (.DIODE(net60),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[35]_B (.DIODE(\la_data_in_enable[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[36]_A (.DIODE(net61),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[36]_B (.DIODE(\la_data_in_enable[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[37]_A (.DIODE(net62),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[37]_B (.DIODE(\la_data_in_enable[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[38]_A (.DIODE(net63),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[38]_B (.DIODE(\la_data_in_enable[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[39]_A (.DIODE(net64),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[39]_B (.DIODE(\la_data_in_enable[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[3]_A (.DIODE(net65),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[3]_B (.DIODE(\la_data_in_enable[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[40]_A (.DIODE(net66),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[40]_B (.DIODE(\la_data_in_enable[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[41]_A (.DIODE(net67),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[41]_B (.DIODE(\la_data_in_enable[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[42]_A (.DIODE(net68),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[42]_B (.DIODE(\la_data_in_enable[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[43]_A (.DIODE(net69),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[43]_B (.DIODE(\la_data_in_enable[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[44]_A (.DIODE(net70),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[44]_B (.DIODE(\la_data_in_enable[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[45]_A (.DIODE(net71),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[45]_B (.DIODE(\la_data_in_enable[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[46]_A (.DIODE(net72),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[46]_B (.DIODE(\la_data_in_enable[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[47]_A (.DIODE(net73),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[47]_B (.DIODE(\la_data_in_enable[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[48]_A (.DIODE(net74),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[48]_B (.DIODE(\la_data_in_enable[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[49]_A (.DIODE(net75),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[49]_B (.DIODE(\la_data_in_enable[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[4]_A (.DIODE(net76),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[4]_B (.DIODE(\la_data_in_enable[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[50]_A (.DIODE(net77),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[50]_B (.DIODE(\la_data_in_enable[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[51]_A (.DIODE(net78),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[51]_B (.DIODE(\la_data_in_enable[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[52]_A (.DIODE(net79),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[52]_B (.DIODE(\la_data_in_enable[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[53]_A (.DIODE(net80),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[53]_B (.DIODE(\la_data_in_enable[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[54]_A (.DIODE(net81),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[54]_B (.DIODE(\la_data_in_enable[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[55]_A (.DIODE(net82),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[55]_B (.DIODE(\la_data_in_enable[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[56]_A (.DIODE(net83),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[56]_B (.DIODE(\la_data_in_enable[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[57]_A (.DIODE(net84),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[57]_B (.DIODE(\la_data_in_enable[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[58]_A (.DIODE(net85),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[58]_B (.DIODE(\la_data_in_enable[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[59]_A (.DIODE(net86),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[59]_B (.DIODE(\la_data_in_enable[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[5]_A (.DIODE(net87),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[5]_B (.DIODE(\la_data_in_enable[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[60]_A (.DIODE(net88),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[60]_B (.DIODE(\la_data_in_enable[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[61]_A (.DIODE(net89),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[61]_B (.DIODE(\la_data_in_enable[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[62]_A (.DIODE(net90),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[62]_B (.DIODE(\la_data_in_enable[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[63]_A (.DIODE(net91),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[63]_B (.DIODE(\la_data_in_enable[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[64]_A (.DIODE(net92),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[64]_B (.DIODE(\la_data_in_enable[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[65]_A (.DIODE(net93),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[65]_B (.DIODE(\la_data_in_enable[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[66]_A (.DIODE(net94),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[66]_B (.DIODE(\la_data_in_enable[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[67]_A (.DIODE(net95),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[67]_B (.DIODE(\la_data_in_enable[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[68]_A (.DIODE(net96),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[68]_B (.DIODE(\la_data_in_enable[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[69]_A (.DIODE(net97),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[69]_B (.DIODE(\la_data_in_enable[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[6]_A (.DIODE(net98),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[6]_B (.DIODE(\la_data_in_enable[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[70]_A (.DIODE(net99),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[70]_B (.DIODE(\la_data_in_enable[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[71]_A (.DIODE(net100),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[71]_B (.DIODE(\la_data_in_enable[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[72]_A (.DIODE(net101),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[72]_B (.DIODE(\la_data_in_enable[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[73]_A (.DIODE(net102),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[73]_B (.DIODE(\la_data_in_enable[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[74]_A (.DIODE(net103),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[74]_B (.DIODE(\la_data_in_enable[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[75]_A (.DIODE(net104),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[75]_B (.DIODE(\la_data_in_enable[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[76]_A (.DIODE(net105),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[76]_B (.DIODE(\la_data_in_enable[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[77]_A (.DIODE(net106),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[77]_B (.DIODE(\la_data_in_enable[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[78]_A (.DIODE(net107),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[78]_B (.DIODE(\la_data_in_enable[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[79]_A (.DIODE(net108),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[79]_B (.DIODE(\la_data_in_enable[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[7]_A (.DIODE(net109),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[7]_B (.DIODE(\la_data_in_enable[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[80]_A (.DIODE(net110),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[80]_B (.DIODE(\la_data_in_enable[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[81]_A (.DIODE(net111),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[81]_B (.DIODE(\la_data_in_enable[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[82]_A (.DIODE(net112),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[82]_B (.DIODE(\la_data_in_enable[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[83]_A (.DIODE(net113),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[83]_B (.DIODE(\la_data_in_enable[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[84]_A (.DIODE(net114),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[84]_B (.DIODE(\la_data_in_enable[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[85]_A (.DIODE(net115),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[85]_B (.DIODE(\la_data_in_enable[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[86]_A (.DIODE(net116),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[86]_B (.DIODE(\la_data_in_enable[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[87]_A (.DIODE(net117),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[87]_B (.DIODE(\la_data_in_enable[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[88]_A (.DIODE(net118),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[88]_B (.DIODE(\la_data_in_enable[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[89]_A (.DIODE(net119),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[89]_B (.DIODE(\la_data_in_enable[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[8]_A (.DIODE(net120),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[8]_B (.DIODE(\la_data_in_enable[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[90]_A (.DIODE(net121),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[90]_B (.DIODE(\la_data_in_enable[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[91]_A (.DIODE(net122),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[91]_B (.DIODE(\la_data_in_enable[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[92]_A (.DIODE(net123),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[92]_B (.DIODE(\la_data_in_enable[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[93]_A (.DIODE(net124),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[93]_B (.DIODE(\la_data_in_enable[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[94]_A (.DIODE(net125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[94]_B (.DIODE(\la_data_in_enable[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[95]_A (.DIODE(net126),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[95]_B (.DIODE(\la_data_in_enable[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[96]_A (.DIODE(net127),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[96]_B (.DIODE(\la_data_in_enable[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[97]_A (.DIODE(net128),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[97]_B (.DIODE(\la_data_in_enable[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[98]_A (.DIODE(net129),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[98]_B (.DIODE(\la_data_in_enable[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[99]_A (.DIODE(net130),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[99]_B (.DIODE(\la_data_in_enable[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[9]_A (.DIODE(net131),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_in_gates[9]_B (.DIODE(\la_data_in_enable[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[0]_A (.DIODE(_201_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[0]_TE (.DIODE(\mprj_logic1[202] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[100]_A (.DIODE(_202_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[100]_TE (.DIODE(\mprj_logic1[302] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[101]_A (.DIODE(_203_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[101]_TE (.DIODE(\mprj_logic1[303] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[102]_A (.DIODE(_204_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[102]_TE (.DIODE(\mprj_logic1[304] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[103]_A (.DIODE(_205_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[103]_TE (.DIODE(\mprj_logic1[305] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[104]_A (.DIODE(_206_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[104]_TE (.DIODE(\mprj_logic1[306] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[105]_A (.DIODE(_207_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[105]_TE (.DIODE(\mprj_logic1[307] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[106]_A (.DIODE(_208_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[106]_TE (.DIODE(\mprj_logic1[308] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[107]_A (.DIODE(_209_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[107]_TE (.DIODE(\mprj_logic1[309] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[108]_A (.DIODE(_210_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[108]_TE (.DIODE(\mprj_logic1[310] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[109]_A (.DIODE(_211_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[109]_TE (.DIODE(\mprj_logic1[311] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[10]_A (.DIODE(_212_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[10]_TE (.DIODE(\mprj_logic1[212] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[110]_A (.DIODE(_213_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[110]_TE (.DIODE(\mprj_logic1[312] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[111]_A (.DIODE(_214_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[111]_TE (.DIODE(\mprj_logic1[313] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[112]_A (.DIODE(_215_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[112]_TE (.DIODE(\mprj_logic1[314] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[113]_A (.DIODE(_216_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[113]_TE (.DIODE(\mprj_logic1[315] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[114]_A (.DIODE(_217_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[114]_TE (.DIODE(\mprj_logic1[316] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[115]_A (.DIODE(_218_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[115]_TE (.DIODE(\mprj_logic1[317] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[116]_A (.DIODE(_219_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[116]_TE (.DIODE(\mprj_logic1[318] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[117]_A (.DIODE(_220_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[117]_TE (.DIODE(\mprj_logic1[319] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[118]_A (.DIODE(_221_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[118]_TE (.DIODE(\mprj_logic1[320] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[119]_A (.DIODE(_222_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[119]_TE (.DIODE(\mprj_logic1[321] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[11]_A (.DIODE(_223_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[11]_TE (.DIODE(\mprj_logic1[213] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[120]_A (.DIODE(_224_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[120]_TE (.DIODE(\mprj_logic1[322] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[121]_A (.DIODE(_225_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[121]_TE (.DIODE(\mprj_logic1[323] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[122]_A (.DIODE(_226_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[122]_TE (.DIODE(\mprj_logic1[324] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[123]_A (.DIODE(_227_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[123]_TE (.DIODE(\mprj_logic1[325] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[124]_A (.DIODE(_228_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[124]_TE (.DIODE(\mprj_logic1[326] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[125]_A (.DIODE(_229_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[125]_TE (.DIODE(\mprj_logic1[327] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[126]_A (.DIODE(_230_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[126]_TE (.DIODE(\mprj_logic1[328] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[127]_A (.DIODE(_231_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[127]_TE (.DIODE(\mprj_logic1[329] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[12]_A (.DIODE(_232_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[12]_TE (.DIODE(\mprj_logic1[214] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[13]_A (.DIODE(_233_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[13]_TE (.DIODE(\mprj_logic1[215] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[14]_A (.DIODE(_234_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[14]_TE (.DIODE(\mprj_logic1[216] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[15]_A (.DIODE(_235_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[15]_TE (.DIODE(\mprj_logic1[217] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[16]_A (.DIODE(_236_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[16]_TE (.DIODE(\mprj_logic1[218] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[17]_A (.DIODE(_237_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[17]_TE (.DIODE(\mprj_logic1[219] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[18]_A (.DIODE(_238_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[18]_TE (.DIODE(\mprj_logic1[220] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[19]_A (.DIODE(_239_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[19]_TE (.DIODE(\mprj_logic1[221] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[1]_A (.DIODE(_240_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[1]_TE (.DIODE(\mprj_logic1[203] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[20]_A (.DIODE(_241_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[20]_TE (.DIODE(\mprj_logic1[222] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[21]_A (.DIODE(_242_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[21]_TE (.DIODE(\mprj_logic1[223] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[22]_A (.DIODE(_243_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[22]_TE (.DIODE(\mprj_logic1[224] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[23]_A (.DIODE(_244_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[23]_TE (.DIODE(\mprj_logic1[225] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[24]_A (.DIODE(_245_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[24]_TE (.DIODE(\mprj_logic1[226] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[25]_A (.DIODE(_246_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[25]_TE (.DIODE(\mprj_logic1[227] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[26]_A (.DIODE(_247_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[26]_TE (.DIODE(\mprj_logic1[228] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[27]_A (.DIODE(_248_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[27]_TE (.DIODE(\mprj_logic1[229] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[28]_A (.DIODE(_249_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[28]_TE (.DIODE(\mprj_logic1[230] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[29]_A (.DIODE(_250_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[29]_TE (.DIODE(\mprj_logic1[231] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[2]_A (.DIODE(_251_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[2]_TE (.DIODE(\mprj_logic1[204] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[30]_A (.DIODE(_252_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[30]_TE (.DIODE(\mprj_logic1[232] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[31]_A (.DIODE(_253_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[31]_TE (.DIODE(\mprj_logic1[233] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[32]_A (.DIODE(_254_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[32]_TE (.DIODE(\mprj_logic1[234] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[33]_A (.DIODE(_255_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[33]_TE (.DIODE(\mprj_logic1[235] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[34]_A (.DIODE(_256_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[34]_TE (.DIODE(\mprj_logic1[236] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[35]_A (.DIODE(_257_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[35]_TE (.DIODE(\mprj_logic1[237] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[36]_A (.DIODE(_258_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[36]_TE (.DIODE(\mprj_logic1[238] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[37]_A (.DIODE(_259_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[37]_TE (.DIODE(\mprj_logic1[239] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[38]_A (.DIODE(_260_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[38]_TE (.DIODE(\mprj_logic1[240] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[39]_A (.DIODE(_261_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[39]_TE (.DIODE(\mprj_logic1[241] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[3]_A (.DIODE(_262_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[3]_TE (.DIODE(\mprj_logic1[205] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[40]_A (.DIODE(_263_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[40]_TE (.DIODE(\mprj_logic1[242] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[41]_A (.DIODE(_264_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[41]_TE (.DIODE(\mprj_logic1[243] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[42]_A (.DIODE(_265_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[42]_TE (.DIODE(\mprj_logic1[244] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[43]_A (.DIODE(_266_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[43]_TE (.DIODE(\mprj_logic1[245] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[44]_A (.DIODE(_267_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[44]_TE (.DIODE(\mprj_logic1[246] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[45]_A (.DIODE(_268_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[45]_TE (.DIODE(\mprj_logic1[247] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[46]_A (.DIODE(_269_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[46]_TE (.DIODE(\mprj_logic1[248] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[47]_A (.DIODE(_270_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[47]_TE (.DIODE(\mprj_logic1[249] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[48]_A (.DIODE(_271_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[48]_TE (.DIODE(\mprj_logic1[250] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[49]_A (.DIODE(_272_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[49]_TE (.DIODE(\mprj_logic1[251] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[4]_A (.DIODE(_273_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[4]_TE (.DIODE(\mprj_logic1[206] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[50]_A (.DIODE(_274_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[50]_TE (.DIODE(\mprj_logic1[252] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[51]_A (.DIODE(_275_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[51]_TE (.DIODE(\mprj_logic1[253] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[52]_A (.DIODE(_276_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[52]_TE (.DIODE(\mprj_logic1[254] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[53]_A (.DIODE(_277_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[53]_TE (.DIODE(\mprj_logic1[255] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[54]_A (.DIODE(_278_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[54]_TE (.DIODE(\mprj_logic1[256] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[55]_A (.DIODE(_279_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[55]_TE (.DIODE(\mprj_logic1[257] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[56]_A (.DIODE(_280_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[56]_TE (.DIODE(\mprj_logic1[258] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[57]_A (.DIODE(_281_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[57]_TE (.DIODE(\mprj_logic1[259] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[58]_A (.DIODE(_282_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[58]_TE (.DIODE(\mprj_logic1[260] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[59]_A (.DIODE(_283_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[59]_TE (.DIODE(\mprj_logic1[261] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[5]_A (.DIODE(_284_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[5]_TE (.DIODE(\mprj_logic1[207] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[60]_A (.DIODE(_285_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[60]_TE (.DIODE(\mprj_logic1[262] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[61]_A (.DIODE(_286_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[61]_TE (.DIODE(\mprj_logic1[263] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[62]_A (.DIODE(_287_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[62]_TE (.DIODE(\mprj_logic1[264] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[63]_A (.DIODE(_288_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[63]_TE (.DIODE(\mprj_logic1[265] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[64]_A (.DIODE(_289_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[64]_TE (.DIODE(\mprj_logic1[266] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[65]_A (.DIODE(_290_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[65]_TE (.DIODE(\mprj_logic1[267] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[66]_A (.DIODE(_291_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[66]_TE (.DIODE(\mprj_logic1[268] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[67]_A (.DIODE(_292_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[67]_TE (.DIODE(\mprj_logic1[269] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[68]_A (.DIODE(_293_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[68]_TE (.DIODE(\mprj_logic1[270] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[69]_A (.DIODE(_294_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[69]_TE (.DIODE(\mprj_logic1[271] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[6]_A (.DIODE(_295_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[6]_TE (.DIODE(\mprj_logic1[208] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[70]_A (.DIODE(_296_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[70]_TE (.DIODE(\mprj_logic1[272] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[71]_A (.DIODE(_297_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[71]_TE (.DIODE(\mprj_logic1[273] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[72]_A (.DIODE(_298_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[72]_TE (.DIODE(\mprj_logic1[274] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[73]_A (.DIODE(_299_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[73]_TE (.DIODE(\mprj_logic1[275] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[74]_A (.DIODE(_300_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[74]_TE (.DIODE(\mprj_logic1[276] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[75]_A (.DIODE(_301_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[75]_TE (.DIODE(\mprj_logic1[277] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[76]_A (.DIODE(_302_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[76]_TE (.DIODE(\mprj_logic1[278] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[77]_A (.DIODE(_303_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[77]_TE (.DIODE(\mprj_logic1[279] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[78]_A (.DIODE(_304_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[78]_TE (.DIODE(\mprj_logic1[280] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[79]_A (.DIODE(_305_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[79]_TE (.DIODE(\mprj_logic1[281] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[7]_A (.DIODE(_306_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[7]_TE (.DIODE(\mprj_logic1[209] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[80]_A (.DIODE(_307_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[80]_TE (.DIODE(\mprj_logic1[282] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[81]_A (.DIODE(_308_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[81]_TE (.DIODE(\mprj_logic1[283] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[82]_A (.DIODE(_309_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[82]_TE (.DIODE(\mprj_logic1[284] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[83]_A (.DIODE(_310_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[83]_TE (.DIODE(\mprj_logic1[285] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[84]_A (.DIODE(_311_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[84]_TE (.DIODE(\mprj_logic1[286] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[85]_A (.DIODE(_312_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[85]_TE (.DIODE(\mprj_logic1[287] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[86]_A (.DIODE(_313_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[86]_TE (.DIODE(\mprj_logic1[288] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[87]_A (.DIODE(_314_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[87]_TE (.DIODE(\mprj_logic1[289] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[88]_A (.DIODE(_315_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[88]_TE (.DIODE(\mprj_logic1[290] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[89]_A (.DIODE(_316_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[89]_TE (.DIODE(\mprj_logic1[291] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[8]_A (.DIODE(_317_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[8]_TE (.DIODE(\mprj_logic1[210] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[90]_A (.DIODE(_318_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[90]_TE (.DIODE(\mprj_logic1[292] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[91]_A (.DIODE(_319_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[91]_TE (.DIODE(\mprj_logic1[293] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[92]_A (.DIODE(_320_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[92]_TE (.DIODE(\mprj_logic1[294] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[93]_A (.DIODE(_321_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[93]_TE (.DIODE(\mprj_logic1[295] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[94]_A (.DIODE(_322_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[94]_TE (.DIODE(\mprj_logic1[296] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[95]_A (.DIODE(_323_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[95]_TE (.DIODE(\mprj_logic1[297] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[96]_A (.DIODE(_324_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[96]_TE (.DIODE(\mprj_logic1[298] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[97]_A (.DIODE(_325_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[97]_TE (.DIODE(\mprj_logic1[299] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[98]_A (.DIODE(_326_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[98]_TE (.DIODE(\mprj_logic1[300] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[99]_A (.DIODE(_327_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[99]_TE (.DIODE(\mprj_logic1[301] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[9]_A (.DIODE(_328_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_to_mprj_oen_buffers[9]_TE (.DIODE(\mprj_logic1[211] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_user_to_mprj_wb_ena_buf_A (.DIODE(net614),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_user_to_mprj_wb_ena_buf_B (.DIODE(\mprj_logic1[462] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_user_wb_ack_buffer_A (.DIODE(mprj_ack_i_core_bar),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_user_wb_ack_gate_A (.DIODE(net516),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 ANTENNA_user_wb_ack_gate_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[0]_A (.DIODE(\mprj_dat_i_core_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[10]_A (.DIODE(\mprj_dat_i_core_bar[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[11]_A (.DIODE(\mprj_dat_i_core_bar[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[12]_A (.DIODE(\mprj_dat_i_core_bar[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[13]_A (.DIODE(\mprj_dat_i_core_bar[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[14]_A (.DIODE(\mprj_dat_i_core_bar[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[15]_A (.DIODE(\mprj_dat_i_core_bar[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[16]_A (.DIODE(\mprj_dat_i_core_bar[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[17]_A (.DIODE(\mprj_dat_i_core_bar[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[18]_A (.DIODE(\mprj_dat_i_core_bar[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[19]_A (.DIODE(\mprj_dat_i_core_bar[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[1]_A (.DIODE(\mprj_dat_i_core_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[20]_A (.DIODE(\mprj_dat_i_core_bar[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[21]_A (.DIODE(\mprj_dat_i_core_bar[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[22]_A (.DIODE(\mprj_dat_i_core_bar[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[23]_A (.DIODE(\mprj_dat_i_core_bar[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[24]_A (.DIODE(\mprj_dat_i_core_bar[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[25]_A (.DIODE(\mprj_dat_i_core_bar[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[26]_A (.DIODE(\mprj_dat_i_core_bar[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[27]_A (.DIODE(\mprj_dat_i_core_bar[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[28]_A (.DIODE(\mprj_dat_i_core_bar[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[29]_A (.DIODE(\mprj_dat_i_core_bar[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[2]_A (.DIODE(\mprj_dat_i_core_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[30]_A (.DIODE(\mprj_dat_i_core_bar[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[31]_A (.DIODE(\mprj_dat_i_core_bar[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[3]_A (.DIODE(\mprj_dat_i_core_bar[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[4]_A (.DIODE(\mprj_dat_i_core_bar[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[5]_A (.DIODE(\mprj_dat_i_core_bar[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[6]_A (.DIODE(\mprj_dat_i_core_bar[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[7]_A (.DIODE(\mprj_dat_i_core_bar[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[8]_A (.DIODE(\mprj_dat_i_core_bar[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_buffers[9]_A (.DIODE(\mprj_dat_i_core_bar[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[0]_A (.DIODE(net550),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[0]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[10]_A (.DIODE(net551),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[10]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[11]_A (.DIODE(net552),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[11]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[12]_A (.DIODE(net553),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[12]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[13]_A (.DIODE(net554),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[13]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[14]_A (.DIODE(net555),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[14]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[15]_A (.DIODE(net556),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[15]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[16]_A (.DIODE(net557),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[16]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[17]_A (.DIODE(net558),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[17]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[18]_A (.DIODE(net559),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[18]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[19]_A (.DIODE(net560),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[19]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[1]_A (.DIODE(net561),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[1]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[20]_A (.DIODE(net562),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[20]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[21]_A (.DIODE(net563),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[21]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[22]_A (.DIODE(net564),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[22]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[23]_A (.DIODE(net565),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[23]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[24]_A (.DIODE(net566),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[24]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[25]_A (.DIODE(net567),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[25]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[26]_A (.DIODE(net568),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[26]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[27]_A (.DIODE(net569),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[27]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[28]_A (.DIODE(net570),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[28]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[29]_A (.DIODE(net571),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[29]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[2]_A (.DIODE(net572),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[2]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[30]_A (.DIODE(net573),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[30]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[31]_A (.DIODE(net574),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[31]_B (.DIODE(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[3]_A (.DIODE(net575),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[3]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[4]_A (.DIODE(net576),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[4]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[5]_A (.DIODE(net577),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[5]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[6]_A (.DIODE(net578),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[6]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[7]_A (.DIODE(net579),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[7]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[8]_A (.DIODE(net580),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[8]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[9]_A (.DIODE(net581),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__diode_2 \ANTENNA_user_wb_dat_gates[9]_B (.DIODE(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1030 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_1044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1224 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1270 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1286 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1356 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1534 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1580 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1588 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_162 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1650 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1728 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1790 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_1881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_1952 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2042 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2142 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2290 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_2311 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_240 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_348 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_519 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_658 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_736 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_0_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1022 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1047 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1059 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1075 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_1111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1311 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1386 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1422 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1434 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_1446 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1491 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1508 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1535 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1606 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1610 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_1835 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_400 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_404 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_428 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_452 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_460 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_472 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_484 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_548 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_556 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_846 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_850 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_858 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_862 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_10_886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1046 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1054 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1075 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1159 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1206 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1311 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1339 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1367 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_11_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1424 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_11_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1508 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1850 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_1854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1858 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_1870 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_514 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_11_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_11_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_11_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_844 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_11_976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_1602 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1606 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_12_1630 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_12_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_1702 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_1706 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1710 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_1795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_1851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_1907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_12_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_12_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_12_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_12_554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_12_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_12_605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_12_639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_12_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_656 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_12_660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_664 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_12_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_12_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_12_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_12_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_1655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_13_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_13_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_13_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_13_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_13_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_13_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_13_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_1879 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_13_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1975 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_13_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_13_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_13_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_13_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_13_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_13_636 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_13_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_13_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_13_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_13_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_13_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_14_1575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1616 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_14_1620 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_14_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_14_1687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1732 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_14_1736 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_1795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_14_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_14_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_1907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_14_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1975 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_14_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_14_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_14_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_668 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_14_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_14_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_14_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_14_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_14_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1556 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1560 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1564 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1576 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1588 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_15_1600 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_15_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_15_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_15_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1710 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1714 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_15_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1879 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_15_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_2005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_2008 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_15_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_15_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_519 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_15_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_15_577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_15_599 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_15_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_15_631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_15_639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_652 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_656 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_668 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_680 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_15_692 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_15_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_15_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_15_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_15_730 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_16_1574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1588 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1600 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_1627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_16_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_16_1723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_1795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_16_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_16_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_16_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1888 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1904 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1908 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1940 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1944 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_16_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_16_534 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_16_639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_16_647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_16_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_16_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_16_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_17_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_17_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_1639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_17_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_17_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1750 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_17_1766 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_1878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_17_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_17_558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_17_575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_17_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_17_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_17_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_654 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_17_658 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_662 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_686 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_17_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_17_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_17_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_18_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1598 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1602 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1614 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_1626 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1706 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1710 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_18_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1724 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1738 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_18_1742 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1824 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1828 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1840 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1896 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_1912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1963 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_2003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_367 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_18_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_420 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_570 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_594 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_606 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_18_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_18_661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_18_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_18_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_18_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_18_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_18_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_18_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1932 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_19_1936 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1948 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1952 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_19_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_19_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_19_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_19_546 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_19_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_19_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_19_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_19_680 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_684 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_19_696 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_19_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_19_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_19_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1004 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1014 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1019 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1028 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1047 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1054 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1058 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1096 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1150 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1274 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1376 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1395 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1406 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1410 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1422 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1426 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1430 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1434 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1438 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1442 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1448 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1452 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1488 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1492 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1504 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1508 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1520 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1535 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1566 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1590 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1606 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1612 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1616 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1620 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1652 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1678 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1712 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1730 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1748 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1752 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1784 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1802 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1826 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1830 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1842 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1864 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_1881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1914 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1918 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1922 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1926 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1938 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2036 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_204 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2059 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2082 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2086 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2140 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2170 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2214 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_2326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2330 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_2350 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_272 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_330 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_350 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_36 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_376 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_40 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_412 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_43 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_430 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_434 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_476 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_490 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_516 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_570 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_578 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_614 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_620 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_624 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_628 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_636 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_682 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_686 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_71 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_732 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_75 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_818 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_862 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_866 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_870 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_880 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_888 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_89 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_892 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_904 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_908 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_934 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_938 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_950 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_984 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_988 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_1_999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_159 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_1608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_1786 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1842 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_20_1854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_186 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1898 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_20_1910 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1924 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_1928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1936 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_1960 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_232 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_236 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_20_248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_20_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_502 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_506 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_518 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_20_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_20_563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_578 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_58 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_20_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_20_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_20_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_20_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_20_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_21_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_140 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1656 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_1711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1742 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1746 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1758 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_176 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_1770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1786 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_1790 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_1798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1824 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1828 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_21_1835 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_1840 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_21_1865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_1878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1963 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_1976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_1980 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_1992 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_2003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_234 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_262 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_274 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_519 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_21_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_590 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_594 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_606 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_614 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_628 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_21_632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_652 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_656 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_21_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_21_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_21_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_21_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_21_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_21_89 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_1627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_170 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_174 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1758 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1762 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1774 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_178 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1786 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1864 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1868 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_1898 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1902 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_1912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_1963 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_2008 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_206 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_214 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_260 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_22_264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_272 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_282 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_22_294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_22_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_22_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_370 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_402 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_414 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_460 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_472 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_22_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_22_565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_22_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_22_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_22_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_22_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_22_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_22_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_22_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_22_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_159 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_1598 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1678 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1702 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_23_1714 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_1767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_23_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1840 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_23_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_2006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_23_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_362 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_23_388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_402 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_406 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_430 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_442 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_462 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_466 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_470 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_502 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_519 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_23_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_23_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_23_73 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_23_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_23_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_23_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_1781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_1919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_1948 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1952 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_1964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2023 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2032 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2059 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_2063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2080 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2095 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_2111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_2235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_2299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_2324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_2328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_2335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_2347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_24_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_518 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_24_705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_24_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_24_733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_24_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_24_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_24_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_146 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1692 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1834 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_1838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1846 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_1928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1950 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_1958 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_1993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2023 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_2051 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_2070 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_2076 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2080 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2084 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2096 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2122 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_2215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_2230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_2255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_2263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_2270 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_2326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_2347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_376 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_408 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_412 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_428 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_432 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_516 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_520 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_532 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_544 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_556 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_25_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_25_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_25_647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_25_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_25_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_25_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_25_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_1575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_1627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1768 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_1792 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1800 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_1848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1856 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_1947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_1962 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_1966 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_2023 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_2039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_2046 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_2111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_2119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_2133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_2187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_2231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_2242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_2251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_2330 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_2346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_2358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_292 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_407 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_412 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_26_416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_452 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_468 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_492 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_564 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_568 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_58 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_580 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_26_639 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_26_691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_26_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_26_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_730 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_26_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_26_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_13 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1686 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_1710 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1738 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_1742 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1772 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1856 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1868 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1880 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_1955 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2028 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2032 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_2044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2052 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_2079 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2088 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2092 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_2104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_2123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_2215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_2219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_2275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_2303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_2326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_2347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_2359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_25 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_311 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_37 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_423 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_49 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_540 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_544 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_27_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_27_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_27_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_27_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_27_722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_74 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_27_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_86 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_27_98 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1048 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1052 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1507 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_1976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_1980 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_2091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_2119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_2148 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_2196 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_2200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_2301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_2329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_2341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_486 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_490 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_502 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_28_780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_834 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_28_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_28_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_28_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_28_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_28_964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_28_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1367 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1394 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1507 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1724 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1759 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1826 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1879 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2028 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2040 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2052 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_2064 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_2100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_2226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_2232 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_2287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_2308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_2312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_2318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_2334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_2346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_414 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_424 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_508 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_564 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_568 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_572 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_596 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_638 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_642 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_654 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_74 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_746 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_774 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_29_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_29_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_29_824 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_830 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_29_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_29_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_29_95 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_29_99 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1004 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1022 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1026 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1031 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1074 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1078 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1082 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1116 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1186 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_120 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1214 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1244 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1292 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_130 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1338 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_134 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1342 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1360 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1364 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_138 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1392 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1395 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_1404 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1426 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1440 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1468 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_1472 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1492 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1504 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1516 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1610 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1622 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1628 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1636 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1644 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1678 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1684 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_176 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1762 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1796 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1802 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1810 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1814 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1858 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1864 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1868 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1880 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1888 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1920 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1970 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1975 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1984 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_1993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_1996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_2000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2016 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2020 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2028 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2031 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2042 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_2058 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2079 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2106 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2116 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_2122 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_2139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2182 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2186 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2232 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_2236 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2244 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_2248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_2256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_2306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_2329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_2347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_24 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_274 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_330 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_338 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_342 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_392 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_43 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_440 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_444 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_448 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_452 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_498 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_506 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_514 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_518 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_564 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_578 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_626 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_68 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_730 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_748 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_752 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_764 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_768 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_802 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_810 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_822 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_826 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_830 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_844 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_856 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_992 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1018 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1030 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1159 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1182 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1186 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_1254 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_1307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1352 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1356 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_1368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_168 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_1700 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1800 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_1816 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1835 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2022 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2026 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_2038 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2058 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2074 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2086 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_2149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_2259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_2280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_2320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_316 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_342 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_395 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_398 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_410 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_432 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_436 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_448 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_460 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_472 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_491 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_506 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_30_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_611 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_622 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_634 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_642 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_67 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_786 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_790 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_835 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_906 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_910 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_30_922 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_30_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_30_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_30_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_30_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_30_994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1206 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1224 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1454 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1700 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_1728 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1748 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1752 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1768 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1772 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_1784 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_1881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_204 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2070 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_2114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_2271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_2279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_424 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_432 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_612 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_67 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_788 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_792 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_80 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_812 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_824 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_31_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_31_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_88 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_31_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_31_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_31_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_31_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_31_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1018 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1030 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1054 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1070 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1082 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_130 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1395 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1407 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1438 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1450 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1462 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1474 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1646 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1650 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1675 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1800 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1816 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_1921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1962 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_1966 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_1972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2031 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_2094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_2116 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_2296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_2300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_2314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_407 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_414 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_49 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_58 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_672 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_684 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_696 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_32_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_32_873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_89 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_32_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_32_978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_32_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_32_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_32_994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_1113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_1157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1168 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_1227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1370 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1392 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_1396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1507 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1590 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1594 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1598 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1610 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1622 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_1996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_2012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_2033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_2102 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_2114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_2159 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_216 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_2273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_552 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_556 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_33_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_712 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_73 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_796 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_800 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_816 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_828 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_33_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_856 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_872 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_33_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_963 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_33_967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_33_971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_33_978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_982 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_33_994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1086 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1158 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1162 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1174 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1246 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1258 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1286 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1290 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1572 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1576 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1588 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1664 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1832 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_1872 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_1912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_1928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_1974 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_1977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2078 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2096 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_2231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_2303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_2319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_282 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_386 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_398 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_410 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_614 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_34_618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_62 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_628 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_658 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_682 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_34_694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_738 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_840 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_852 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_34_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_34_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_922 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_34_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_34_987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_34_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1004 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1095 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_1284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_1977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_1993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_2005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2032 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2036 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2048 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_2060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2095 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_2116 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_212 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_276 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_292 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_340 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_356 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_548 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_552 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_706 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_718 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_75 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_752 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_764 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_79 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_35_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_87 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_35_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_906 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_35_918 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_926 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_35_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_35_96 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_35_983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_35_987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1019 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1031 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1158 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1162 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1174 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1186 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1234 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1244 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_1252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_1305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1496 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_1586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1612 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1624 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1636 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1648 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1672 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_1700 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1748 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1948 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1952 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_1956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1992 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_1996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_2036 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2092 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_2096 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_2145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_2231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2234 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2246 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_2258 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_2291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_2319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_362 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_408 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_463 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_518 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_600 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_616 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_624 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_36_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_80 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_835 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_36_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_36_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_36_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_36_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_36_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_36_995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1002 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1206 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1262 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_1278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1394 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1491 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1580 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1596 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_1620 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1712 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_1728 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_1947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1958 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_1994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_1998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_2010 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_2065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_2117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_2143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_2147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_2236 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_2304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_2332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_2344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_438 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_442 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_37_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_532 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_540 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_614 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_758 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_816 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_820 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_832 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_37_889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_37_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_37_931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_37_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_37_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_37_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1010 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1022 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1034 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1122 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1138 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1146 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1420 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1424 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1732 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1872 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_1921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2016 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2020 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_2036 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_2217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_2231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_2257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_680 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_687 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_708 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_712 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_724 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_736 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_748 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_38_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_788 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_792 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_38_889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_38_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_906 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_918 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_38_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_38_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_38_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_986 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_38_998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1031 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1051 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1056 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_1060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1075 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1096 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1566 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1668 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1672 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1692 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1728 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1872 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1880 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1888 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_1935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_2124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_39_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_634 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_638 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_650 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_662 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_39_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_39_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_39_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_39_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_39_912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_940 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_39_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1002 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1048 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1056 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1148 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1272 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1282 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1286 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1339 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1370 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1382 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1394 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1423 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1442 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1466 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1470 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1506 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_1726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1914 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_1926 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_1977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1980 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_1992 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_2004 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2008 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_2011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2051 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2059 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2070 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_2104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_2122 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2170 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2174 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2182 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_2218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_2234 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_2287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_2348 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_374 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_390 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_423 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_45 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_64 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_68 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_80 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_866 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_890 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_3_968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_984 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_3_996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1078 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1356 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_40_1368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1376 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1392 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1404 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1416 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_1517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_1585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_40_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_2089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_2150 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_2154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_672 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_736 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_40_752 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_40_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_790 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_794 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_40_806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_820 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_824 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_848 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_890 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_40_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_40_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_40_941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_958 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_40_970 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_40_978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_40_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1006 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_41_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_1279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1356 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1360 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_1503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_1920 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_41_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_2316 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_2332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_2344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_41_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_700 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_708 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_41_887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_41_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_41_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_908 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_924 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_936 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_950 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_41_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_41_970 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_974 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_41_986 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_41_998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_42_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1162 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1166 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1178 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1451 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_42_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_42_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_42_745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_42_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_42_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_42_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_42_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_42_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_42_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_42_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_42_997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_43_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_43_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_43_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1076 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_1088 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_43_1109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_43_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_43_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_1383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2059 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_2063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_43_2067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_43_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_43_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_43_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_43_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_43_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_43_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_43_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_43_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_43_905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_43_912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_928 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_940 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_43_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_44_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_44_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_44_1114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1176 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_44_1200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1254 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_44_1268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1280 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_44_1308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_1450 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1454 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1466 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1478 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_2093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_2149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_44_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_44_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_44_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_44_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_44_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_826 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_830 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_842 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_854 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_866 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_44_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_44_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_44_936 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_940 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_952 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_44_976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_44_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_45_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_1132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1148 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_45_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_45_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_2062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2066 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_45_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_45_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_2320 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_2324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_2340 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_45_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_45_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_45_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_45_889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_904 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_45_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_45_947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_45_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_45_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_1104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1120 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_1127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_1272 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1276 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1300 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_1440 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1444 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1468 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_1480 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_2094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_2149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_46_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_2285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_46_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_46_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_2341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_46_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_46_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_46_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_46_887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_46_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_46_933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_46_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_46_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_46_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_47_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1084 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1088 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_47_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1150 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_1166 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1174 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_1336 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2048 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2222 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_47_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_47_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_46 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_47_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_47_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_47_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_47_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_47_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_47_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1682 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1706 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_48_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_48_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1794 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1818 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_1964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_48_1980 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_48_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2064 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2076 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2088 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_48_2130 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_2149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2254 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_48_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_50 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_48_507 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_48_523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_78 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_48_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_48_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_48_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1554 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1566 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_49_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_1769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1890 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1902 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_1921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_1949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_2030 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_2034 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2038 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_2050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_2089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_2117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_2302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_2339 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_2361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_491 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_49_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_49_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_548 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_49_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_49_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_49_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_49_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_49_989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1027 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_1042 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1047 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1079 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1244 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1292 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1450 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1462 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_1535 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1620 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1692 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1716 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1732 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1857 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2068 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2080 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_2092 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_2148 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_2240 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_2257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_2359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_407 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_546 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_56 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_60 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_654 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_658 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_682 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_694 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_738 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_742 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_75 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_750 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_790 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_802 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_810 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_89 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_4_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_4_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1526 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1678 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1774 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1784 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1788 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1810 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1818 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_182 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_1869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2016 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2020 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_2049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_2055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_2075 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2095 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2142 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_2146 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2179 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_50_2203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_2261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_2341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_2357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_2360 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_284 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_296 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_342 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_354 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_484 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_488 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_492 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_514 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_518 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_50_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_50_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_546 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_574 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_50_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_50_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_50_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_50_993 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1040 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1056 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1102 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_1114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_1170 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1184 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1196 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_120 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1275 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1302 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1326 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_1370 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_1378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1432 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1436 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1448 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1504 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1508 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1523 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1532 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1544 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1576 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1588 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1611 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_164 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1644 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1648 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1672 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1750 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1760 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1764 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1780 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1784 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1828 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1840 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1858 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_188 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1890 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_1930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1938 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_1968 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_198 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1980 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_1991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_1998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_2002 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2008 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2026 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_2030 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2036 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2040 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_2044 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_2054 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_2089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2142 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_2154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_2162 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2201 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2216 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_2230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_2328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_2336 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_2348 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_274 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_318 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_324 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_358 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_362 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_366 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_37 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_376 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_380 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_386 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_45 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_458 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_470 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_478 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_48 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_486 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_52 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_542 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_546 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_594 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_600 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_632 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_644 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_656 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_668 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_71 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_768 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_792 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_804 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_51_836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_87 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_51_894 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_90 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_938 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_95 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_51_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_51_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_966 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_51_986 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_51_992 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_51_995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1011 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_52_1020 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1026 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1058 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1062 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1078 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1082 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1102 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1142 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1146 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1156 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1171 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1180 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1200 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1214 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1252 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1258 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1272 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1276 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_130 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1330 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1334 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1339 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1354 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1368 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1388 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1392 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1407 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_52_1412 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1450 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1454 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1470 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1474 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1490 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1494 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1534 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1548 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1552 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1572 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1592 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1626 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1630 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1644 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1650 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1658 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1662 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1680 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1684 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1722 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1726 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1746 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1774 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1782 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1806 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1810 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1814 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1842 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1846 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1862 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1866 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1870 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1886 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1891 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1908 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1918 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1926 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1930 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1946 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1950 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_1958 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_1964 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1969 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1984 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_1998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2002 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2042 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2050 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2056 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2060 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2076 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2080 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2094 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2138 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_2161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2191 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_52_2196 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2244 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2254 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2263 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2274 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_2283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2312 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_2316 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_232 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2322 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2332 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2336 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_2341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2346 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_2350 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_278 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_290 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_33 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_336 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_348 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_372 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_38 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_382 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_396 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_400 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_410 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_434 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_52_444 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_450 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_463 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_468 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_472 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_488 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_566 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_599 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_604 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_628 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_64 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_642 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_666 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_682 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_686 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_690 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_706 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_710 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_715 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_744 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_750 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_764 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_768 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_788 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_802 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_808 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_822 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_826 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_860 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_866 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_880 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_884 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_9 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_91 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_913 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_918 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_932 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_936 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_947 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_96 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_962 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_52_971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_52_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_52_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_52_996 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1016 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1023 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1034 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1052 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1146 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1168 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1226 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1248 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1306 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1328 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1342 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1350 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1364 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1386 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1408 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1426 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1444 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1502 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1519 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1538 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1547 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1575 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1611 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1698 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1720 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1734 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1742 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1756 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1771 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1800 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1818 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1836 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1894 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1911 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1916 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1967 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_1974 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_1981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2010 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2032 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2054 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2083 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2134 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2148 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2170 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_2228 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2245 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2308 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_2331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_362 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_406 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_430 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_440 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_458 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_464 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_474 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_487 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_493 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_498 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_522 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_551 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_558 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_580 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_602 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_62 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_624 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_638 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_662 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_696 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_718 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_740 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_75 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_798 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_834 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_856 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_914 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_950 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_958 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_53_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_53_987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_53_994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1005 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_106 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1154 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1160 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1172 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1192 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1196 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1246 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1256 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1262 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1266 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1270 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1282 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1354 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1474 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1478 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1482 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1486 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1490 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1502 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1510 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1540 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1563 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1566 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1593 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1605 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1661 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1773 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_181 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1823 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1879 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1882 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_1894 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_1902 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_1953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_1997 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2071 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2073 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2085 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2097 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2209 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2221 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2239 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_2249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_2260 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2276 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_2288 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_2333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_2345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_2359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_381 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_384 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_641 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_754 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_758 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_762 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_770 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_829 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_5_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_90 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_94 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_5_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_5_977 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_994 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_5_998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1000 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1024 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1048 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1089 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1251 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1340 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1344 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_1348 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1352 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_1367 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1437 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1446 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1521 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1548 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1568 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1572 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1608 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1612 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1616 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1622 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1626 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1630 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1642 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1650 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1677 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1703 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1801 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1885 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_1965 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_197 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_1975 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_1979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2025 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_2037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_206 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2081 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_2093 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_2136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2140 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_2152 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2178 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_218 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_2202 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_2210 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2235 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2247 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_2259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_230 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_2317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_2359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_2363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_250 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_289 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_301 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_345 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_409 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_469 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_581 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_637 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_640 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_657 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_681 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_745 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_769 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_781 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_896 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_900 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_6_904 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_920 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_941 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_956 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_960 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_6_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_972 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_6_985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_988 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1021 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1033 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1037 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1049 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1065 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1077 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1088 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1102 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1106 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1145 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1149 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1161 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_7_1189 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1203 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1217 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1233 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_1249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1257 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1273 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1294 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1298 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1304 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1310 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1314 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1317 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1329 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1357 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1373 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1385 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1401 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1413 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1422 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1426 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1429 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1442 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1446 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1454 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1457 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_1473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1481 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1485 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1497 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1513 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1553 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1562 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_1569 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1577 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1582 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1586 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1590 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1597 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1609 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1618 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1625 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1633 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_165 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1653 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1665 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_1671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_1674 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_1688 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1692 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_7_1704 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1709 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1721 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1737 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1749 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1765 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_177 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1777 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1789 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1793 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1805 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1817 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1821 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1833 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1849 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1861 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1877 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1889 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1905 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1917 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1929 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1933 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_194 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1945 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_1985 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_1989 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2001 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2013 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2017 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2045 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2057 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_2061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2069 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_207 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2086 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_2090 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2098 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2141 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2153 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2157 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_2169 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_2183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_2185 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2193 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2213 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_2225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_223 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2241 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2269 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2297 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2325 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_2337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_2353 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_237 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_249 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_281 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_293 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_305 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_309 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_321 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_337 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_349 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_365 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_377 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_393 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_405 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_421 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_433 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_449 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_461 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_477 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_489 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_49 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_501 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_505 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_529 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_533 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_573 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_585 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_589 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_601 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_617 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_629 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_642 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_645 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_701 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_713 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_73 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_741 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_757 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_772 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_776 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_785 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_797 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_813 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_825 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_837 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_841 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_853 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_865 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_869 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_88 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_881 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_897 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_909 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_7_921 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_925 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_937 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_949 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_96 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_970 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_7_974 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_981 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_7_995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1015 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1019 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_1023 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1029 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1041 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1053 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1061 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1063 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1075 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1099 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1143 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1155 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1167 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1173 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1205 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1208 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_8_1220 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_1225 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1229 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1243 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1255 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1267 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1285 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1287 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1299 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1311 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1323 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1341 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1367 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1379 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1397 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1430 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1434 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1455 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1467 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1479 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1491 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1509 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1517 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1525 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1528 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1534 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1537 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_1561 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1565 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1603 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1621 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1647 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1676 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_8_1679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1689 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1693 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1717 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_1729 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1733 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_1779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_8_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1815 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1827 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1845 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1859 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1871 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1883 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1901 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1903 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1915 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1927 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1939 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_1951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_1957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1971 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1983 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_1995 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_265 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_277 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_279 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_291 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_333 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_335 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_347 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_359 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_371 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_389 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_391 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_403 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_415 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_439 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_445 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_459 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_471 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_484 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_488 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_503 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_515 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_527 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_541 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_545 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_549 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_557 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_559 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_571 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_583 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_613 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_615 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_627 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_655 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_659 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_669 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_671 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_683 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_695 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_725 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_727 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_739 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_751 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_774 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_778 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_783 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_795 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_807 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_816 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_820 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_832 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_839 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_893 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_895 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_907 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_919 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_931 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_8_943 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_948 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_951 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_8_959 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_962 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_974 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_982 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_986 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_8_998 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1003 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1009 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1012 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1022 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1035 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1039 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1043 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1055 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1067 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1079 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1087 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1091 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1144 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1147 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1151 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1163 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1175 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1183 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1187 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1190 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1195 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1199 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1211 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1215 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1219 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1227 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1231 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1238 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1242 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1246 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1259 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1313 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1315 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1327 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1339 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1351 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1369 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1378 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1382 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1394 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1406 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1418 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1422 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1425 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1427 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1435 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1443 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1447 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1456 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1460 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1464 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1476 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1483 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_1495 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1499 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1507 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1511 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1516 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1520 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1530 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1536 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1539 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1543 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1555 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1567 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1579 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_1591 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1595 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1607 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1619 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1631 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1649 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1651 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1660 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1664 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1670 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1673 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1685 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1705 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1707 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1719 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1731 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1743 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1761 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1763 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1775 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1787 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1799 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1808 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1812 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1831 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1867 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_1873 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1875 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1887 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1899 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1908 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1912 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_1924 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1934 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_1938 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1942 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1954 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1966 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1978 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_1987 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_1999 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_2007 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_253 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_261 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_264 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_268 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_271 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_283 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_295 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_303 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_307 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_319 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_331 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_343 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_355 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_361 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_363 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_375 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_383 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_387 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_399 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_411 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_417 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_419 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_431 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_441 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_453 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_465 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_473 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_475 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_484 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_488 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_500 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_512 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_524 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_531 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_535 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_550 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_556 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_560 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_564 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_576 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_584 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_587 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_599 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_611 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_623 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_635 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_638 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_643 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_663 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_667 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_679 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_691 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_697 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_699 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_711 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_723 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_735 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_747 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_753 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_755 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_767 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_779 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_791 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_803 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_809 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_811 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_819 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_828 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_832 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_838 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_843 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_847 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_851 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_855 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_863 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_874 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_878 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_890 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_902 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_914 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_923 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_935 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_953 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_957 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_961 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_973 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_9_976 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_979 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_991 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_100 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_101 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_102 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_103 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_104 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_105 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_106 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_107 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_108 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_109 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_110 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_111 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_112 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_113 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_114 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_115 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_116 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_117 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_118 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_119 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_120 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_121 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_122 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_123 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_124 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_125 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_126 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_127 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_128 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_129 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_130 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_131 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_132 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_133 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_134 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_135 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_136 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_137 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_138 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_139 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_43 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_46 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_48 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_49 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_50 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_52 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_56 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_58 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_60 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_62 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_64 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_65 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_67 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_68 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_70 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_71 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_72 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_73 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_74 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_75 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_76 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_77 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_78 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_79 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_80 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_81 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_82 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_83 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_84 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_85 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_86 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_87 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_88 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_89 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_90 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_91 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_92 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_93 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_94 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_95 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_96 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_97 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_98 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_99 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1000 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1001 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1002 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1003 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1004 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1005 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1006 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1007 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1008 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1009 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1010 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1011 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1012 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1013 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1014 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1015 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1016 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1017 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1018 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1019 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1020 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1021 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1022 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1023 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1024 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1025 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1026 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1027 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1028 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1029 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1030 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1031 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1032 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1033 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1034 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1035 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1036 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1037 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1038 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1039 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1040 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1041 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1042 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1043 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1044 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1045 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1046 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1047 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1048 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1049 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1050 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1051 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1052 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1053 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1054 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1055 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1056 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1057 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1058 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1059 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1060 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1061 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1062 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1063 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1064 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1065 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1066 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1067 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1068 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1069 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1070 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1071 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1072 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1073 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1074 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1075 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1076 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1077 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1078 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1079 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1080 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1081 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1082 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1083 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1084 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1085 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1086 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1087 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1088 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1089 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1090 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1091 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1092 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1093 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1094 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1095 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1096 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1097 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1098 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1099 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1100 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1101 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1102 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1103 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1104 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1105 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1106 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1107 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1108 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1109 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1110 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1111 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1112 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1113 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1114 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1115 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1116 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1117 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1118 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1119 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1120 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1121 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1122 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1123 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1124 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1125 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1126 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1127 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1128 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1129 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1130 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1131 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1132 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1133 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1134 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1135 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1136 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1137 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1138 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1139 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1140 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1141 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1142 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1143 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1144 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1145 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1146 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1147 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1148 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1149 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1150 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1151 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1152 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1153 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1154 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1155 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1156 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1157 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1158 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1159 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1160 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1161 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1162 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1163 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1164 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1165 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1166 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1167 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1168 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1169 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1170 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1171 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1172 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1173 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1174 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1175 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1176 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1177 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1178 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1179 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1180 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1181 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1182 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1183 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1184 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1185 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1186 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1187 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1188 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1189 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1190 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1191 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1192 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1193 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1194 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1195 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1196 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1197 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1198 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1199 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1200 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1201 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1202 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1203 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1204 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1205 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1206 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1207 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1208 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1209 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1210 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1211 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1212 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1213 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1214 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1215 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1216 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1217 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1218 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1219 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1220 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1221 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1222 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1223 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1224 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1225 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1226 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1227 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1228 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1229 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1230 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1231 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1232 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1233 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1234 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1235 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1236 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1237 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1238 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1239 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1240 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1241 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1242 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1243 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1244 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1245 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1246 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1247 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1248 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1249 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1250 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1251 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1252 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1253 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1254 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1255 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1256 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1257 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1258 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1259 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1260 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1261 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1262 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1263 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1264 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1265 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1266 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1267 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1268 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1269 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1270 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1271 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1272 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1273 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1274 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1275 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1276 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1277 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1278 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1279 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1280 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1281 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1282 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1283 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1284 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1285 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1286 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1287 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1288 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1289 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1290 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1291 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1292 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1293 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1294 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1295 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1296 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1297 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1298 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1299 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1300 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1301 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1302 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1303 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1304 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1305 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1306 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1307 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1308 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1309 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1310 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1311 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1312 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1313 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1314 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1315 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1316 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1317 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1318 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1319 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1320 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1321 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1322 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1323 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1324 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1325 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1326 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1327 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1328 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1329 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1330 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1331 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1332 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1333 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1334 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1335 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1336 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1337 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1338 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1339 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1340 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1341 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1342 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1343 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1344 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1345 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1346 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1347 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1348 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1349 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1350 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1351 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1352 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1353 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1354 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1355 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1356 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1357 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1358 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1359 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1360 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1361 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1362 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1363 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1364 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1365 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1366 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1367 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1368 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1369 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1370 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1371 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1372 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1373 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1374 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1375 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1376 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1377 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1378 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1379 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1380 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1381 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1382 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1383 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1384 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1385 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1386 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1387 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1388 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1389 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1390 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1391 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1392 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1393 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1394 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1395 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1396 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1397 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1398 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1399 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_140 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1400 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1401 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1402 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1403 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1404 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1405 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1406 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1407 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1408 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1409 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_141 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1410 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1411 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1412 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1413 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1414 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1415 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1416 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1417 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1418 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1419 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_142 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1420 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1421 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1422 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1423 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1424 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1425 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1426 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1427 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1428 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1429 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_143 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1430 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1431 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1432 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1433 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1434 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1435 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1436 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1437 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1438 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1439 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_144 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1440 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1441 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1442 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1443 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1444 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1445 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1446 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1447 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1448 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1449 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_145 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1450 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1451 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1452 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1453 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1454 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1455 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1456 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1457 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1458 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1459 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_146 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1460 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1461 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1462 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1463 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1464 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1465 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1466 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1467 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1468 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1469 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_147 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1470 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1471 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1472 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1473 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1474 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1475 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1476 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1477 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1478 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1479 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_148 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1480 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1481 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1482 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1483 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1484 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1485 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1486 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1487 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1488 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1489 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_149 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1490 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1491 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1492 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1493 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1494 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1495 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1496 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1497 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1498 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1499 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_150 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1500 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1501 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1502 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1503 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1504 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1505 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1506 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1507 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1508 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1509 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_151 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1510 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1511 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1512 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1513 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1514 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1515 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1516 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1517 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1518 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1519 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_152 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1520 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1521 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1522 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1523 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1524 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1525 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1526 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1527 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1528 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1529 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_153 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1530 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1531 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1532 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1533 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1534 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1535 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1536 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1537 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1538 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1539 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_154 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1540 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1541 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1542 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1543 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1544 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1545 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1546 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1547 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1548 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1549 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_155 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1550 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1551 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1552 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1553 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1554 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1555 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1556 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1557 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1558 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1559 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_156 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1560 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1561 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1562 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1563 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1564 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1565 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1566 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1567 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1568 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1569 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_157 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1570 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1571 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1572 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1573 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1574 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1575 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1576 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1577 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1578 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1579 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_158 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1580 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1581 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1582 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1583 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1584 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1585 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1586 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1587 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1588 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1589 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_159 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1590 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1591 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1592 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1593 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1594 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1595 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1596 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1597 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1598 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1599 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_160 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1600 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1601 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1602 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1603 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1604 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1605 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1606 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1607 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1608 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1609 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_161 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1610 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1611 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1612 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1613 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1614 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1615 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1616 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1617 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1618 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1619 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_162 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1620 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1621 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1622 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1623 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1624 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1625 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1626 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1627 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1628 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1629 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_163 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1630 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1631 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1632 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1633 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1634 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1635 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1636 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1637 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1638 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1639 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_164 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1640 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1641 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1642 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1643 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1644 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1645 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1646 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1647 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1648 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1649 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_165 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1650 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1651 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1652 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1653 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1654 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1655 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1656 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1657 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1658 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1659 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_166 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1660 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1661 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1662 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1663 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1664 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1665 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1666 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1667 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1668 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1669 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_167 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1670 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1671 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1672 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1673 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1674 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1675 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1676 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1677 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1678 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1679 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_168 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1680 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1681 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1682 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1683 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1684 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1685 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1686 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1687 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1688 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1689 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_169 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1690 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1691 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1692 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1693 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1694 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1695 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1696 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1697 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1698 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1699 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_170 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1700 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1701 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1702 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1703 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1704 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1705 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1706 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1707 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1708 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1709 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_171 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1710 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1711 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1712 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1713 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1714 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1715 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1716 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1717 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1718 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1719 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_172 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1720 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1721 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1722 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1723 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1724 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1725 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1726 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1727 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1728 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1729 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_173 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1730 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1731 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1732 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1733 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1734 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1735 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1736 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1737 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1738 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1739 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_174 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1740 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1741 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1742 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1743 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1744 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1745 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1746 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1747 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1748 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1749 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_175 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1750 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1751 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1752 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1753 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1754 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1755 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1756 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1757 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1758 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1759 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_176 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1760 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1761 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1762 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1763 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1764 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1765 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1766 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1767 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1768 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1769 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_177 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1770 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1771 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1772 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1773 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1774 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1775 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1776 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1777 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1778 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1779 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_178 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1780 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1781 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1782 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1783 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1784 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1785 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1786 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1787 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1788 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1789 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_179 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1790 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1791 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1792 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1793 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1794 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1795 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1796 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1797 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1798 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1799 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_180 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1800 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1801 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1802 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1803 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1804 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1805 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1806 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1807 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1808 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1809 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_181 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1810 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1811 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1812 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1813 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1814 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1815 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1816 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1817 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1818 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1819 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_182 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1820 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1821 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1822 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1823 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1824 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1825 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1826 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1827 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1828 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1829 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_183 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1830 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1831 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1832 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1833 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1834 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1835 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1836 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1837 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1838 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1839 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_184 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1840 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1841 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1842 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1843 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1844 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1845 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1846 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1847 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1848 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1849 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_185 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1850 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1851 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1852 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1853 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1854 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1855 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1856 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1857 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1858 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1859 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_186 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1860 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1861 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1862 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1863 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1864 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1865 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1866 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1867 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1868 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1869 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_187 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1870 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1871 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1872 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1873 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1874 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1875 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1876 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1877 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1878 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1879 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_188 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1880 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1881 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1882 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1883 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1884 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1885 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1886 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1887 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1888 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1889 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_189 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1890 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1891 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1892 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1893 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1894 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1895 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1896 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1897 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1898 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1899 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_190 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1900 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1901 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1902 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1903 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1904 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1905 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1906 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1907 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1908 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1909 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_191 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1910 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1911 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1912 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1913 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1914 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1915 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1916 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1917 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1918 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1919 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_192 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1920 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1921 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1922 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1923 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1924 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1925 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1926 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1927 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1928 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1929 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_193 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1930 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1931 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1932 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1933 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1934 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1935 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1936 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1937 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1938 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1939 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_194 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1940 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1941 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1942 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1943 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1944 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1945 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1946 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1947 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1948 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1949 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_195 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1950 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1951 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1952 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1953 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1954 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1955 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1956 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1957 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1958 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1959 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_196 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1960 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1961 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1962 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1963 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1964 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1965 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1966 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1967 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1968 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1969 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_197 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1970 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1971 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1972 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1973 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1974 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1975 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1976 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1977 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1978 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1979 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_198 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1980 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1981 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1982 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1983 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1984 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1985 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1986 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1987 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1988 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1989 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_199 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1990 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1991 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1992 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1993 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1994 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1995 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1996 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1997 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1998 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_1999 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_200 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2000 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2001 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2002 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2003 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2004 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2005 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2006 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2007 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2008 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2009 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_201 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2010 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2011 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2012 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2013 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2014 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2015 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2016 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2017 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2018 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2019 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_202 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2020 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2021 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2022 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2023 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2024 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2025 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2026 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2027 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2028 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2029 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_203 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2030 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2031 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2032 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2033 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2034 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2035 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2036 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2037 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2038 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2039 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_204 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2040 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2041 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2042 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2043 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2044 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2045 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2046 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2047 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2048 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2049 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_205 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2050 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2051 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2052 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2053 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2054 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2055 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2056 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2057 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2058 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2059 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_206 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2060 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2061 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2062 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2063 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2064 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2065 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2066 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2067 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2068 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2069 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_207 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2070 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2071 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2072 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2073 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2074 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2075 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2076 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2077 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2078 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2079 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_208 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2080 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2081 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2082 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2083 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2084 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2085 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2086 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2087 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2088 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2089 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_209 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2090 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2091 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2092 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2093 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2094 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2095 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2096 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2097 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2098 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2099 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_210 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2100 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2101 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2102 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2103 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2104 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2105 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2106 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2107 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2108 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2109 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_211 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2110 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2111 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2112 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2113 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2114 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2115 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2116 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2117 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2118 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2119 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_212 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2120 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2121 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2122 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2123 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2124 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2125 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2126 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2127 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2128 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2129 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_213 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2130 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2131 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2132 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2133 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2134 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2135 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2136 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2137 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2138 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2139 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_214 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2140 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2141 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2142 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2143 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2144 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2145 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2146 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2147 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2148 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2149 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_215 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2150 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2151 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2152 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2153 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2154 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2155 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2156 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2157 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2158 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2159 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_216 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2160 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2161 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2162 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2163 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2164 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2165 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2166 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2167 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2168 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2169 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_217 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2170 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2171 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2172 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2173 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2174 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2175 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2176 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2177 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2178 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2179 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_218 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2180 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2181 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2182 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2183 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2184 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2185 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2186 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2187 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2188 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2189 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_219 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2190 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2191 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2192 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2193 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2194 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2195 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2196 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2197 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2198 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2199 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_220 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2200 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2201 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2202 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2203 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2204 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2205 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2206 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2207 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2208 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2209 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_221 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2210 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2211 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2212 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2213 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2214 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2215 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2216 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2217 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2218 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2219 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_222 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2220 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2221 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2222 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2223 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2224 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2225 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2226 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2227 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2228 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2229 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_223 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2230 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2231 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2232 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2233 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2234 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2235 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2236 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2237 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2238 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2239 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_224 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2240 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2241 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2242 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2243 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2244 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2245 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2246 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2247 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2248 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2249 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_225 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2250 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2251 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2252 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2253 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2254 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2255 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2256 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2257 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2258 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2259 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_226 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2260 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2261 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2262 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2263 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2264 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2265 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2266 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2267 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2268 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_2269 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_227 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_228 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_229 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_230 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_231 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_232 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_233 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_234 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_235 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_236 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_237 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_238 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_239 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_240 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_241 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_242 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_243 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_244 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_245 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_246 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_247 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_248 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_249 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_250 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_251 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_252 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_253 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_254 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_255 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_256 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_257 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_258 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_259 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_260 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_261 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_262 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_263 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_264 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_265 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_266 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_267 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_268 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_269 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_270 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_271 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_272 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_273 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_274 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_275 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_276 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_277 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_278 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_279 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_280 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_281 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_282 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_283 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_284 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_285 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_286 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_287 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_288 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_289 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_290 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_291 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_292 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_293 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_294 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_295 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_296 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_297 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_298 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_299 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_300 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_301 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_302 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_303 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_304 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_305 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_306 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_307 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_308 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_309 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_310 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_311 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_312 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_313 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_314 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_315 (.VGND(vssd),
+ .VPWR(vccd));
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+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_317 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_318 (.VGND(vssd),
+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_491 (.VGND(vssd),
+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
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+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_495 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_496 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_497 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_498 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_499 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_500 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_501 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_502 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_503 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_504 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_505 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_506 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_507 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_508 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_509 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_510 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_511 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_512 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_513 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_514 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_515 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_516 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_517 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_518 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_519 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_520 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_521 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_522 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_523 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_524 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_525 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_526 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_527 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_528 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_529 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_530 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_531 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_532 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_533 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_534 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_535 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_536 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_537 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_538 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_539 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_540 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_541 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_542 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_543 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_544 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_545 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_546 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_547 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_548 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_549 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_550 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_551 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_552 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_553 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_554 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_555 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_556 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_557 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_558 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_559 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_560 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_561 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_562 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_563 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_564 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_565 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_566 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_567 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_568 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_569 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_570 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_571 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_572 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_573 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_574 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_575 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_576 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_577 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_578 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_579 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_580 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_581 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_582 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_583 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_584 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_585 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_586 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_587 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_588 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_589 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_590 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_591 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_592 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_593 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_594 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_595 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_596 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_597 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_598 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_599 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_600 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_601 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_602 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_603 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_604 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_605 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_606 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_607 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_608 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_609 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_610 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_611 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_612 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_613 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_614 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_615 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_616 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_617 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_618 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_619 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_620 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_621 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_622 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_623 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_624 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_625 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_626 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_627 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_628 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_629 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_630 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_631 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_632 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_633 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_634 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_635 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_636 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_637 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_638 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_639 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_640 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_641 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_642 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_643 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_644 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_645 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_646 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_647 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_648 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_649 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_650 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_651 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_652 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_653 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_654 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_655 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_656 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_657 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_658 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_659 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_660 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_661 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_662 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_663 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_664 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_665 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_666 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_667 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_668 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_669 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_670 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_671 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_672 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_673 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_674 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_675 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_676 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_677 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_678 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_679 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_680 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_681 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_682 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_683 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_684 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_685 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_686 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_687 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_688 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_689 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_690 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_691 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_692 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_693 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_694 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_695 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_696 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_697 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_698 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_699 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_700 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_701 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_702 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_703 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_704 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_705 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_706 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_707 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_708 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_709 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_710 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_711 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_712 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_713 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_714 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_715 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_716 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_717 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_718 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_719 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_720 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_721 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_722 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_723 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_724 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_725 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_726 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_727 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_728 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_729 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_730 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_731 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_732 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_733 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_734 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_735 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_736 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_737 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_738 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_739 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_740 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_741 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_742 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_743 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_744 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_745 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_746 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_747 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_748 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_749 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_750 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_751 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_752 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_753 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_754 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_755 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_756 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_757 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_758 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_759 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_760 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_761 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_762 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_763 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_764 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_765 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_766 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_767 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_768 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_769 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_770 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_771 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_772 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_773 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_774 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_775 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_776 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_777 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_778 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_779 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_780 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_781 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_782 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_783 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_784 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_785 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_786 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_787 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_788 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_789 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_790 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_791 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_792 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_793 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_794 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_795 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_796 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_797 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_798 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_799 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_800 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_801 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_802 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_803 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_804 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_805 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_806 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_807 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_808 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_809 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_810 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_811 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_812 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_813 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_814 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_815 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_816 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_817 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_818 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_819 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_820 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_821 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_822 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_823 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_824 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_825 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_826 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_827 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_828 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_829 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_830 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_831 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_832 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_833 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_834 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_835 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_836 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_837 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_838 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_839 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_840 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_841 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_842 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_843 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_844 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_845 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_846 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_847 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_848 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_849 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_850 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_851 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_852 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_853 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_854 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_855 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_856 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_857 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_858 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_859 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_860 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_861 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_862 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_863 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_864 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_865 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_866 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_867 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_868 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_869 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_870 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_871 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_872 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_873 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_874 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_875 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_876 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_877 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_878 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_879 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_880 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_881 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_882 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_883 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_884 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_885 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_886 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_887 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_888 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_889 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_890 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_891 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_892 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_893 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_894 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_895 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_896 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_897 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_898 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_899 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_900 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_901 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_902 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_903 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_904 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_905 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_906 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_907 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_908 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_909 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_910 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_911 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_912 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_913 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_914 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_915 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_916 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_917 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_918 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_919 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_920 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_921 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_922 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_923 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_924 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_925 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_926 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_927 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_928 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_929 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_930 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_931 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_932 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_933 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_934 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_935 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_936 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_937 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_938 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_939 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_940 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_941 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_942 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_943 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_944 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_945 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_946 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_947 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_948 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_949 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_950 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_951 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_952 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_953 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_954 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_955 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_956 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_957 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_958 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_959 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_960 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_961 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_962 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_963 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_964 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_965 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_966 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_967 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_968 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_969 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_970 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_971 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_972 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_973 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_974 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_975 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_976 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_977 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_978 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_979 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_980 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_981 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_982 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_983 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_984 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_985 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_986 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_987 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_988 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_989 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_990 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_991 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_992 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_993 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_994 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_995 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_996 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_997 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_998 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_999 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _329_ (.A(net478),
+ .Y(_291_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _330_ (.A(net479),
+ .Y(_292_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _331_ (.A(net480),
+ .Y(_293_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _332_ (.A(net481),
+ .Y(_294_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _333_ (.A(net483),
+ .Y(_296_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _334_ (.A(net484),
+ .Y(_297_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _335_ (.A(net485),
+ .Y(_298_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _336_ (.A(net486),
+ .Y(_299_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _337_ (.A(net487),
+ .Y(_300_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _338_ (.A(net488),
+ .Y(_301_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _339_ (.A(net489),
+ .Y(_302_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _340_ (.A(net490),
+ .Y(_303_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _341_ (.A(net491),
+ .Y(_304_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _342_ (.A(net492),
+ .Y(_305_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _343_ (.A(net494),
+ .Y(_307_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _344_ (.A(net495),
+ .Y(_308_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _345_ (.A(net496),
+ .Y(_309_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _346_ (.A(net497),
+ .Y(_310_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _347_ (.A(net498),
+ .Y(_311_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _348_ (.A(net499),
+ .Y(_312_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _349_ (.A(net500),
+ .Y(_313_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _350_ (.A(net501),
+ .Y(_314_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _351_ (.A(net502),
+ .Y(_315_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _352_ (.A(net503),
+ .Y(_316_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _353_ (.A(net505),
+ .Y(_318_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _354_ (.A(net506),
+ .Y(_319_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _355_ (.A(net507),
+ .Y(_320_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _356_ (.A(net508),
+ .Y(_321_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _357_ (.A(net509),
+ .Y(_322_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _358_ (.A(net510),
+ .Y(_323_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _359_ (.A(net511),
+ .Y(_324_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _360_ (.A(net512),
+ .Y(_325_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _361_ (.A(net513),
+ .Y(_326_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _362_ (.A(net514),
+ .Y(_327_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _363_ (.A(net389),
+ .Y(_202_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _364_ (.A(net390),
+ .Y(_203_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _365_ (.A(net391),
+ .Y(_204_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _366_ (.A(net392),
+ .Y(_205_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _367_ (.A(net393),
+ .Y(_206_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _368_ (.A(net394),
+ .Y(_207_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _369_ (.A(net395),
+ .Y(_208_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _370_ (.A(net396),
+ .Y(_209_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _371_ (.A(net397),
+ .Y(_210_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _372_ (.A(net398),
+ .Y(_211_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _373_ (.A(net400),
+ .Y(_213_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _374_ (.A(net401),
+ .Y(_214_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _375_ (.A(net402),
+ .Y(_215_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _376_ (.A(net403),
+ .Y(_216_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _377_ (.A(net404),
+ .Y(_217_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _378_ (.A(net405),
+ .Y(_218_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _379_ (.A(net406),
+ .Y(_219_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _380_ (.A(net407),
+ .Y(_220_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _381_ (.A(net408),
+ .Y(_221_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _382_ (.A(net409),
+ .Y(_222_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _383_ (.A(net411),
+ .Y(_224_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _384_ (.A(net412),
+ .Y(_225_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _385_ (.A(net413),
+ .Y(_226_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _386_ (.A(net414),
+ .Y(_227_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _387_ (.A(net415),
+ .Y(_228_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _388_ (.A(net416),
+ .Y(_229_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _389_ (.A(net417),
+ .Y(_230_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _390_ (.A(net418),
+ .Y(_231_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _391_ (.A(net1),
+ .Y(_000_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _392_ (.A(net2),
+ .Y(_001_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _393_ (.A(net549),
+ .Y(_002_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _394_ (.A(net619),
+ .Y(_003_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _395_ (.A(net620),
+ .Y(_004_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _396_ (.A(net615),
+ .Y(_005_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _397_ (.A(net616),
+ .Y(_006_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _398_ (.A(net617),
+ .Y(_007_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _399_ (.A(net618),
+ .Y(_008_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _400_ (.A(net517),
+ .Y(_009_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _401_ (.A(net528),
+ .Y(_020_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _402_ (.A(net539),
+ .Y(_031_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _403_ (.A(net542),
+ .Y(_034_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _404_ (.A(net543),
+ .Y(_035_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _405_ (.A(net544),
+ .Y(_036_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _406_ (.A(net545),
+ .Y(_037_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _407_ (.A(net546),
+ .Y(_038_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _408_ (.A(net547),
+ .Y(_039_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _409_ (.A(net548),
+ .Y(_040_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _410_ (.A(net518),
+ .Y(_010_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _411_ (.A(net519),
+ .Y(_011_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _412_ (.A(net520),
+ .Y(_012_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _413_ (.A(net521),
+ .Y(_013_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _414_ (.A(net522),
+ .Y(_014_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _415_ (.A(net523),
+ .Y(_015_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _416_ (.A(net524),
+ .Y(_016_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _417_ (.A(net525),
+ .Y(_017_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _418_ (.A(net526),
+ .Y(_018_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _419_ (.A(net527),
+ .Y(_019_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _420_ (.A(net529),
+ .Y(_021_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _421_ (.A(net530),
+ .Y(_022_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _422_ (.A(net531),
+ .Y(_023_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _423_ (.A(net532),
+ .Y(_024_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_12 _424_ (.A(net533),
+ .Y(_025_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _425_ (.A(net534),
+ .Y(_026_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _426_ (.A(net535),
+ .Y(_027_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _427_ (.A(net536),
+ .Y(_028_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 _428_ (.A(net537),
+ .Y(_029_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _429_ (.A(net538),
+ .Y(_030_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _430_ (.A(net540),
+ .Y(_032_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 _431_ (.A(net541),
+ .Y(_033_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _432_ (.A(net582),
+ .Y(_041_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _433_ (.A(net593),
+ .Y(_052_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _434_ (.A(net604),
+ .Y(_063_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _435_ (.A(net607),
+ .Y(_066_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _436_ (.A(net608),
+ .Y(_067_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _437_ (.A(net609),
+ .Y(_068_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _438_ (.A(net610),
+ .Y(_069_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _439_ (.A(net611),
+ .Y(_070_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _440_ (.A(net612),
+ .Y(_071_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _441_ (.A(net613),
+ .Y(_072_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _442_ (.A(net583),
+ .Y(_042_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _443_ (.A(net584),
+ .Y(_043_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _444_ (.A(net585),
+ .Y(_044_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _445_ (.A(net586),
+ .Y(_045_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _446_ (.A(net587),
+ .Y(_046_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _447_ (.A(net588),
+ .Y(_047_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _448_ (.A(net589),
+ .Y(_048_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _449_ (.A(net590),
+ .Y(_049_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _450_ (.A(net591),
+ .Y(_050_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _451_ (.A(net592),
+ .Y(_051_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _452_ (.A(net594),
+ .Y(_053_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _453_ (.A(net595),
+ .Y(_054_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _454_ (.A(net596),
+ .Y(_055_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _455_ (.A(net597),
+ .Y(_056_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _456_ (.A(net598),
+ .Y(_057_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _457_ (.A(net599),
+ .Y(_058_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 _458_ (.A(net600),
+ .Y(_059_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _459_ (.A(net601),
+ .Y(_060_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _460_ (.A(net602),
+ .Y(_061_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _461_ (.A(net603),
+ .Y(_062_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_4 _462_ (.A(net605),
+ .Y(_064_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 _463_ (.A(net606),
+ .Y(_065_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _464_ (.A(net132),
+ .Y(_073_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _465_ (.A(net171),
+ .Y(_112_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _466_ (.A(net182),
+ .Y(_123_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _467_ (.A(net193),
+ .Y(_134_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _468_ (.A(net204),
+ .Y(_145_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _469_ (.A(net215),
+ .Y(_156_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _470_ (.A(net226),
+ .Y(_167_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _471_ (.A(net237),
+ .Y(_178_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _472_ (.A(net248),
+ .Y(_189_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _473_ (.A(net259),
+ .Y(_200_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _474_ (.A(net143),
+ .Y(_084_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _475_ (.A(net154),
+ .Y(_095_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _476_ (.A(net163),
+ .Y(_104_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _477_ (.A(net164),
+ .Y(_105_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _478_ (.A(net165),
+ .Y(_106_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _479_ (.A(net166),
+ .Y(_107_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _480_ (.A(net167),
+ .Y(_108_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _481_ (.A(net168),
+ .Y(_109_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _482_ (.A(net169),
+ .Y(_110_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _483_ (.A(net170),
+ .Y(_111_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _484_ (.A(net172),
+ .Y(_113_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _485_ (.A(net173),
+ .Y(_114_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _486_ (.A(net174),
+ .Y(_115_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _487_ (.A(net175),
+ .Y(_116_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _488_ (.A(net176),
+ .Y(_117_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _489_ (.A(net177),
+ .Y(_118_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _490_ (.A(net178),
+ .Y(_119_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _491_ (.A(net179),
+ .Y(_120_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _492_ (.A(net180),
+ .Y(_121_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _493_ (.A(net181),
+ .Y(_122_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _494_ (.A(net183),
+ .Y(_124_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _495_ (.A(net184),
+ .Y(_125_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _496_ (.A(net185),
+ .Y(_126_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _497_ (.A(net186),
+ .Y(_127_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _498_ (.A(net187),
+ .Y(_128_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _499_ (.A(net188),
+ .Y(_129_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _500_ (.A(net189),
+ .Y(_130_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _501_ (.A(net190),
+ .Y(_131_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _502_ (.A(net191),
+ .Y(_132_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _503_ (.A(net192),
+ .Y(_133_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _504_ (.A(net194),
+ .Y(_135_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _505_ (.A(net195),
+ .Y(_136_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _506_ (.A(net196),
+ .Y(_137_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _507_ (.A(net197),
+ .Y(_138_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _508_ (.A(net198),
+ .Y(_139_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _509_ (.A(net199),
+ .Y(_140_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _510_ (.A(net200),
+ .Y(_141_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _511_ (.A(net201),
+ .Y(_142_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _512_ (.A(net202),
+ .Y(_143_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _513_ (.A(net203),
+ .Y(_144_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _514_ (.A(net205),
+ .Y(_146_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _515_ (.A(net206),
+ .Y(_147_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _516_ (.A(net207),
+ .Y(_148_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _517_ (.A(net208),
+ .Y(_149_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _518_ (.A(net209),
+ .Y(_150_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _519_ (.A(net210),
+ .Y(_151_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _520_ (.A(net211),
+ .Y(_152_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _521_ (.A(net212),
+ .Y(_153_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _522_ (.A(net213),
+ .Y(_154_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _523_ (.A(net214),
+ .Y(_155_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _524_ (.A(net216),
+ .Y(_157_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _525_ (.A(net217),
+ .Y(_158_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _526_ (.A(net218),
+ .Y(_159_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _527_ (.A(net219),
+ .Y(_160_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _528_ (.A(net220),
+ .Y(_161_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _529_ (.A(net221),
+ .Y(_162_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _530_ (.A(net222),
+ .Y(_163_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _531_ (.A(net223),
+ .Y(_164_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _532_ (.A(net224),
+ .Y(_165_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _533_ (.A(net225),
+ .Y(_166_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _534_ (.A(net227),
+ .Y(_168_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _535_ (.A(net228),
+ .Y(_169_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _536_ (.A(net229),
+ .Y(_170_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _537_ (.A(net230),
+ .Y(_171_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _538_ (.A(net231),
+ .Y(_172_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _539_ (.A(net232),
+ .Y(_173_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _540_ (.A(net233),
+ .Y(_174_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _541_ (.A(net234),
+ .Y(_175_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _542_ (.A(net235),
+ .Y(_176_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _543_ (.A(net236),
+ .Y(_177_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _544_ (.A(net238),
+ .Y(_179_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _545_ (.A(net239),
+ .Y(_180_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _546_ (.A(net240),
+ .Y(_181_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _547_ (.A(net241),
+ .Y(_182_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _548_ (.A(net242),
+ .Y(_183_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _549_ (.A(net243),
+ .Y(_184_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _550_ (.A(net244),
+ .Y(_185_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _551_ (.A(net245),
+ .Y(_186_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _552_ (.A(net246),
+ .Y(_187_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _553_ (.A(net247),
+ .Y(_188_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _554_ (.A(net249),
+ .Y(_190_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _555_ (.A(net250),
+ .Y(_191_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _556_ (.A(net251),
+ .Y(_192_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _557_ (.A(net252),
+ .Y(_193_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _558_ (.A(net253),
+ .Y(_194_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _559_ (.A(net254),
+ .Y(_195_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _560_ (.A(net255),
+ .Y(_196_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _561_ (.A(net256),
+ .Y(_197_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _562_ (.A(net257),
+ .Y(_198_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _563_ (.A(net258),
+ .Y(_199_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _564_ (.A(net133),
+ .Y(_074_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _565_ (.A(net134),
+ .Y(_075_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _566_ (.A(net135),
+ .Y(_076_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _567_ (.A(net136),
+ .Y(_077_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _568_ (.A(net137),
+ .Y(_078_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _569_ (.A(net138),
+ .Y(_079_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _570_ (.A(net139),
+ .Y(_080_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _571_ (.A(net140),
+ .Y(_081_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _572_ (.A(net141),
+ .Y(_082_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _573_ (.A(net142),
+ .Y(_083_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _574_ (.A(net144),
+ .Y(_085_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _575_ (.A(net145),
+ .Y(_086_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _576_ (.A(net146),
+ .Y(_087_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _577_ (.A(net147),
+ .Y(_088_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _578_ (.A(net148),
+ .Y(_089_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _579_ (.A(net149),
+ .Y(_090_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _580_ (.A(net150),
+ .Y(_091_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _581_ (.A(net151),
+ .Y(_092_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _582_ (.A(net152),
+ .Y(_093_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _583_ (.A(net153),
+ .Y(_094_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _584_ (.A(net155),
+ .Y(_096_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _585_ (.A(net156),
+ .Y(_097_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _586_ (.A(net157),
+ .Y(_098_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _587_ (.A(net158),
+ .Y(_099_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _588_ (.A(net159),
+ .Y(_100_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _589_ (.A(net160),
+ .Y(_101_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _590_ (.A(net161),
+ .Y(_102_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _591_ (.A(net162),
+ .Y(_103_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _592_ (.A(net388),
+ .Y(_201_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _593_ (.A(net427),
+ .Y(_240_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _594_ (.A(net438),
+ .Y(_251_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _595_ (.A(net449),
+ .Y(_262_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _596_ (.A(net460),
+ .Y(_273_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _597_ (.A(net471),
+ .Y(_284_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _598_ (.A(net482),
+ .Y(_295_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _599_ (.A(net493),
+ .Y(_306_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _600_ (.A(net504),
+ .Y(_317_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _601_ (.A(net515),
+ .Y(_328_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _602_ (.A(net399),
+ .Y(_212_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _603_ (.A(net410),
+ .Y(_223_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _604_ (.A(net419),
+ .Y(_232_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _605_ (.A(net420),
+ .Y(_233_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _606_ (.A(net421),
+ .Y(_234_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _607_ (.A(net422),
+ .Y(_235_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _608_ (.A(net423),
+ .Y(_236_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _609_ (.A(net424),
+ .Y(_237_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _610_ (.A(net425),
+ .Y(_238_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _611_ (.A(net426),
+ .Y(_239_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _612_ (.A(net428),
+ .Y(_241_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _613_ (.A(net429),
+ .Y(_242_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _614_ (.A(net430),
+ .Y(_243_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _615_ (.A(net431),
+ .Y(_244_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _616_ (.A(net432),
+ .Y(_245_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _617_ (.A(net433),
+ .Y(_246_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _618_ (.A(net434),
+ .Y(_247_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _619_ (.A(net435),
+ .Y(_248_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _620_ (.A(net436),
+ .Y(_249_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _621_ (.A(net437),
+ .Y(_250_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _622_ (.A(net439),
+ .Y(_252_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _623_ (.A(net440),
+ .Y(_253_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _624_ (.A(net441),
+ .Y(_254_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _625_ (.A(net442),
+ .Y(_255_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _626_ (.A(net443),
+ .Y(_256_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _627_ (.A(net444),
+ .Y(_257_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _628_ (.A(net445),
+ .Y(_258_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _629_ (.A(net446),
+ .Y(_259_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _630_ (.A(net447),
+ .Y(_260_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _631_ (.A(net448),
+ .Y(_261_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _632_ (.A(net450),
+ .Y(_263_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _633_ (.A(net451),
+ .Y(_264_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _634_ (.A(net452),
+ .Y(_265_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _635_ (.A(net453),
+ .Y(_266_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _636_ (.A(net454),
+ .Y(_267_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _637_ (.A(net455),
+ .Y(_268_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _638_ (.A(net456),
+ .Y(_269_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _639_ (.A(net457),
+ .Y(_270_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _640_ (.A(net458),
+ .Y(_271_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _641_ (.A(net459),
+ .Y(_272_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _642_ (.A(net461),
+ .Y(_274_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _643_ (.A(net462),
+ .Y(_275_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _644_ (.A(net463),
+ .Y(_276_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _645_ (.A(net464),
+ .Y(_277_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _646_ (.A(net465),
+ .Y(_278_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _647_ (.A(net466),
+ .Y(_279_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _648_ (.A(net467),
+ .Y(_280_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _649_ (.A(net468),
+ .Y(_281_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _650_ (.A(net469),
+ .Y(_282_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _651_ (.A(net470),
+ .Y(_283_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _652_ (.A(net472),
+ .Y(_285_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _653_ (.A(net473),
+ .Y(_286_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _654_ (.A(net474),
+ .Y(_287_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 _655_ (.A(net475),
+ .Y(_288_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _656_ (.A(net476),
+ .Y(_289_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 _657_ (.A(net477),
+ .Y(_290_),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input1 (.A(caravel_clk),
+ .X(net1),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input10 (.A(la_data_out_core[105]),
+ .X(net10),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input100 (.A(la_data_out_core[71]),
+ .X(net100),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input101 (.A(la_data_out_core[72]),
+ .X(net101),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input102 (.A(la_data_out_core[73]),
+ .X(net102),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input103 (.A(la_data_out_core[74]),
+ .X(net103),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input104 (.A(la_data_out_core[75]),
+ .X(net104),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input105 (.A(la_data_out_core[76]),
+ .X(net105),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input106 (.A(la_data_out_core[77]),
+ .X(net106),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input107 (.A(la_data_out_core[78]),
+ .X(net107),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input108 (.A(la_data_out_core[79]),
+ .X(net108),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input109 (.A(la_data_out_core[7]),
+ .X(net109),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input11 (.A(la_data_out_core[106]),
+ .X(net11),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input110 (.A(la_data_out_core[80]),
+ .X(net110),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input111 (.A(la_data_out_core[81]),
+ .X(net111),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input112 (.A(la_data_out_core[82]),
+ .X(net112),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input113 (.A(la_data_out_core[83]),
+ .X(net113),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input114 (.A(la_data_out_core[84]),
+ .X(net114),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input115 (.A(la_data_out_core[85]),
+ .X(net115),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input116 (.A(la_data_out_core[86]),
+ .X(net116),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input117 (.A(la_data_out_core[87]),
+ .X(net117),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input118 (.A(la_data_out_core[88]),
+ .X(net118),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input119 (.A(la_data_out_core[89]),
+ .X(net119),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input12 (.A(la_data_out_core[107]),
+ .X(net12),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input120 (.A(la_data_out_core[8]),
+ .X(net120),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input121 (.A(la_data_out_core[90]),
+ .X(net121),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input122 (.A(la_data_out_core[91]),
+ .X(net122),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input123 (.A(la_data_out_core[92]),
+ .X(net123),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input124 (.A(la_data_out_core[93]),
+ .X(net124),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input125 (.A(la_data_out_core[94]),
+ .X(net125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input126 (.A(la_data_out_core[95]),
+ .X(net126),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input127 (.A(la_data_out_core[96]),
+ .X(net127),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input128 (.A(la_data_out_core[97]),
+ .X(net128),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input129 (.A(la_data_out_core[98]),
+ .X(net129),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input13 (.A(la_data_out_core[108]),
+ .X(net13),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input130 (.A(la_data_out_core[99]),
+ .X(net130),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input131 (.A(la_data_out_core[9]),
+ .X(net131),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input132 (.A(la_data_out_mprj[0]),
+ .X(net132),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input133 (.A(la_data_out_mprj[100]),
+ .X(net133),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input134 (.A(la_data_out_mprj[101]),
+ .X(net134),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input135 (.A(la_data_out_mprj[102]),
+ .X(net135),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input136 (.A(la_data_out_mprj[103]),
+ .X(net136),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input137 (.A(la_data_out_mprj[104]),
+ .X(net137),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input138 (.A(la_data_out_mprj[105]),
+ .X(net138),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input139 (.A(la_data_out_mprj[106]),
+ .X(net139),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input14 (.A(la_data_out_core[109]),
+ .X(net14),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input140 (.A(la_data_out_mprj[107]),
+ .X(net140),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input141 (.A(la_data_out_mprj[108]),
+ .X(net141),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input142 (.A(la_data_out_mprj[109]),
+ .X(net142),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input143 (.A(la_data_out_mprj[10]),
+ .X(net143),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input144 (.A(la_data_out_mprj[110]),
+ .X(net144),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input145 (.A(la_data_out_mprj[111]),
+ .X(net145),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input146 (.A(la_data_out_mprj[112]),
+ .X(net146),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input147 (.A(la_data_out_mprj[113]),
+ .X(net147),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input148 (.A(la_data_out_mprj[114]),
+ .X(net148),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input149 (.A(la_data_out_mprj[115]),
+ .X(net149),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input15 (.A(la_data_out_core[10]),
+ .X(net15),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input150 (.A(la_data_out_mprj[116]),
+ .X(net150),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input151 (.A(la_data_out_mprj[117]),
+ .X(net151),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input152 (.A(la_data_out_mprj[118]),
+ .X(net152),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input153 (.A(la_data_out_mprj[119]),
+ .X(net153),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input154 (.A(la_data_out_mprj[11]),
+ .X(net154),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input155 (.A(la_data_out_mprj[120]),
+ .X(net155),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input156 (.A(la_data_out_mprj[121]),
+ .X(net156),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input157 (.A(la_data_out_mprj[122]),
+ .X(net157),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input158 (.A(la_data_out_mprj[123]),
+ .X(net158),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input159 (.A(la_data_out_mprj[124]),
+ .X(net159),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input16 (.A(la_data_out_core[110]),
+ .X(net16),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input160 (.A(la_data_out_mprj[125]),
+ .X(net160),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input161 (.A(la_data_out_mprj[126]),
+ .X(net161),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input162 (.A(la_data_out_mprj[127]),
+ .X(net162),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input163 (.A(la_data_out_mprj[12]),
+ .X(net163),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input164 (.A(la_data_out_mprj[13]),
+ .X(net164),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input165 (.A(la_data_out_mprj[14]),
+ .X(net165),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input166 (.A(la_data_out_mprj[15]),
+ .X(net166),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input167 (.A(la_data_out_mprj[16]),
+ .X(net167),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input168 (.A(la_data_out_mprj[17]),
+ .X(net168),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input169 (.A(la_data_out_mprj[18]),
+ .X(net169),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input17 (.A(la_data_out_core[111]),
+ .X(net17),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input170 (.A(la_data_out_mprj[19]),
+ .X(net170),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input171 (.A(la_data_out_mprj[1]),
+ .X(net171),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input172 (.A(la_data_out_mprj[20]),
+ .X(net172),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input173 (.A(la_data_out_mprj[21]),
+ .X(net173),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input174 (.A(la_data_out_mprj[22]),
+ .X(net174),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input175 (.A(la_data_out_mprj[23]),
+ .X(net175),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input176 (.A(la_data_out_mprj[24]),
+ .X(net176),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input177 (.A(la_data_out_mprj[25]),
+ .X(net177),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input178 (.A(la_data_out_mprj[26]),
+ .X(net178),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input179 (.A(la_data_out_mprj[27]),
+ .X(net179),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input18 (.A(la_data_out_core[112]),
+ .X(net18),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input180 (.A(la_data_out_mprj[28]),
+ .X(net180),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input181 (.A(la_data_out_mprj[29]),
+ .X(net181),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input182 (.A(la_data_out_mprj[2]),
+ .X(net182),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input183 (.A(la_data_out_mprj[30]),
+ .X(net183),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input184 (.A(la_data_out_mprj[31]),
+ .X(net184),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input185 (.A(la_data_out_mprj[32]),
+ .X(net185),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input186 (.A(la_data_out_mprj[33]),
+ .X(net186),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input187 (.A(la_data_out_mprj[34]),
+ .X(net187),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input188 (.A(la_data_out_mprj[35]),
+ .X(net188),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input189 (.A(la_data_out_mprj[36]),
+ .X(net189),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input19 (.A(la_data_out_core[113]),
+ .X(net19),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input190 (.A(la_data_out_mprj[37]),
+ .X(net190),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input191 (.A(la_data_out_mprj[38]),
+ .X(net191),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input192 (.A(la_data_out_mprj[39]),
+ .X(net192),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input193 (.A(la_data_out_mprj[3]),
+ .X(net193),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input194 (.A(la_data_out_mprj[40]),
+ .X(net194),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input195 (.A(la_data_out_mprj[41]),
+ .X(net195),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input196 (.A(la_data_out_mprj[42]),
+ .X(net196),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input197 (.A(la_data_out_mprj[43]),
+ .X(net197),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input198 (.A(la_data_out_mprj[44]),
+ .X(net198),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input199 (.A(la_data_out_mprj[45]),
+ .X(net199),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input2 (.A(caravel_clk2),
+ .X(net2),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input20 (.A(la_data_out_core[114]),
+ .X(net20),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input200 (.A(la_data_out_mprj[46]),
+ .X(net200),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input201 (.A(la_data_out_mprj[47]),
+ .X(net201),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input202 (.A(la_data_out_mprj[48]),
+ .X(net202),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input203 (.A(la_data_out_mprj[49]),
+ .X(net203),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input204 (.A(la_data_out_mprj[4]),
+ .X(net204),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input205 (.A(la_data_out_mprj[50]),
+ .X(net205),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input206 (.A(la_data_out_mprj[51]),
+ .X(net206),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input207 (.A(la_data_out_mprj[52]),
+ .X(net207),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input208 (.A(la_data_out_mprj[53]),
+ .X(net208),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input209 (.A(la_data_out_mprj[54]),
+ .X(net209),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input21 (.A(la_data_out_core[115]),
+ .X(net21),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input210 (.A(la_data_out_mprj[55]),
+ .X(net210),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input211 (.A(la_data_out_mprj[56]),
+ .X(net211),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input212 (.A(la_data_out_mprj[57]),
+ .X(net212),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input213 (.A(la_data_out_mprj[58]),
+ .X(net213),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input214 (.A(la_data_out_mprj[59]),
+ .X(net214),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input215 (.A(la_data_out_mprj[5]),
+ .X(net215),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input216 (.A(la_data_out_mprj[60]),
+ .X(net216),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input217 (.A(la_data_out_mprj[61]),
+ .X(net217),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input218 (.A(la_data_out_mprj[62]),
+ .X(net218),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input219 (.A(la_data_out_mprj[63]),
+ .X(net219),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input22 (.A(la_data_out_core[116]),
+ .X(net22),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input220 (.A(la_data_out_mprj[64]),
+ .X(net220),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input221 (.A(la_data_out_mprj[65]),
+ .X(net221),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input222 (.A(la_data_out_mprj[66]),
+ .X(net222),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input223 (.A(la_data_out_mprj[67]),
+ .X(net223),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input224 (.A(la_data_out_mprj[68]),
+ .X(net224),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input225 (.A(la_data_out_mprj[69]),
+ .X(net225),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input226 (.A(la_data_out_mprj[6]),
+ .X(net226),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input227 (.A(la_data_out_mprj[70]),
+ .X(net227),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input228 (.A(la_data_out_mprj[71]),
+ .X(net228),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input229 (.A(la_data_out_mprj[72]),
+ .X(net229),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input23 (.A(la_data_out_core[117]),
+ .X(net23),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input230 (.A(la_data_out_mprj[73]),
+ .X(net230),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input231 (.A(la_data_out_mprj[74]),
+ .X(net231),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input232 (.A(la_data_out_mprj[75]),
+ .X(net232),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input233 (.A(la_data_out_mprj[76]),
+ .X(net233),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input234 (.A(la_data_out_mprj[77]),
+ .X(net234),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input235 (.A(la_data_out_mprj[78]),
+ .X(net235),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input236 (.A(la_data_out_mprj[79]),
+ .X(net236),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input237 (.A(la_data_out_mprj[7]),
+ .X(net237),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input238 (.A(la_data_out_mprj[80]),
+ .X(net238),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input239 (.A(la_data_out_mprj[81]),
+ .X(net239),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input24 (.A(la_data_out_core[118]),
+ .X(net24),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input240 (.A(la_data_out_mprj[82]),
+ .X(net240),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input241 (.A(la_data_out_mprj[83]),
+ .X(net241),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input242 (.A(la_data_out_mprj[84]),
+ .X(net242),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input243 (.A(la_data_out_mprj[85]),
+ .X(net243),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input244 (.A(la_data_out_mprj[86]),
+ .X(net244),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input245 (.A(la_data_out_mprj[87]),
+ .X(net245),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input246 (.A(la_data_out_mprj[88]),
+ .X(net246),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input247 (.A(la_data_out_mprj[89]),
+ .X(net247),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input248 (.A(la_data_out_mprj[8]),
+ .X(net248),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input249 (.A(la_data_out_mprj[90]),
+ .X(net249),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input25 (.A(la_data_out_core[119]),
+ .X(net25),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input250 (.A(la_data_out_mprj[91]),
+ .X(net250),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input251 (.A(la_data_out_mprj[92]),
+ .X(net251),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input252 (.A(la_data_out_mprj[93]),
+ .X(net252),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input253 (.A(la_data_out_mprj[94]),
+ .X(net253),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input254 (.A(la_data_out_mprj[95]),
+ .X(net254),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input255 (.A(la_data_out_mprj[96]),
+ .X(net255),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input256 (.A(la_data_out_mprj[97]),
+ .X(net256),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input257 (.A(la_data_out_mprj[98]),
+ .X(net257),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input258 (.A(la_data_out_mprj[99]),
+ .X(net258),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input259 (.A(la_data_out_mprj[9]),
+ .X(net259),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input26 (.A(la_data_out_core[11]),
+ .X(net26),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input260 (.A(la_iena_mprj[0]),
+ .X(net260),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input261 (.A(la_iena_mprj[100]),
+ .X(net261),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input262 (.A(la_iena_mprj[101]),
+ .X(net262),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input263 (.A(la_iena_mprj[102]),
+ .X(net263),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input264 (.A(la_iena_mprj[103]),
+ .X(net264),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input265 (.A(la_iena_mprj[104]),
+ .X(net265),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input266 (.A(la_iena_mprj[105]),
+ .X(net266),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input267 (.A(la_iena_mprj[106]),
+ .X(net267),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input268 (.A(la_iena_mprj[107]),
+ .X(net268),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input269 (.A(la_iena_mprj[108]),
+ .X(net269),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input27 (.A(la_data_out_core[120]),
+ .X(net27),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input270 (.A(la_iena_mprj[109]),
+ .X(net270),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input271 (.A(la_iena_mprj[10]),
+ .X(net271),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input272 (.A(la_iena_mprj[110]),
+ .X(net272),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input273 (.A(la_iena_mprj[111]),
+ .X(net273),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input274 (.A(la_iena_mprj[112]),
+ .X(net274),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input275 (.A(la_iena_mprj[113]),
+ .X(net275),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input276 (.A(la_iena_mprj[114]),
+ .X(net276),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input277 (.A(la_iena_mprj[115]),
+ .X(net277),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input278 (.A(la_iena_mprj[116]),
+ .X(net278),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input279 (.A(la_iena_mprj[117]),
+ .X(net279),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input28 (.A(la_data_out_core[121]),
+ .X(net28),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input280 (.A(la_iena_mprj[118]),
+ .X(net280),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input281 (.A(la_iena_mprj[119]),
+ .X(net281),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input282 (.A(la_iena_mprj[11]),
+ .X(net282),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input283 (.A(la_iena_mprj[120]),
+ .X(net283),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input284 (.A(la_iena_mprj[121]),
+ .X(net284),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input285 (.A(la_iena_mprj[122]),
+ .X(net285),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input286 (.A(la_iena_mprj[123]),
+ .X(net286),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input287 (.A(la_iena_mprj[124]),
+ .X(net287),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input288 (.A(la_iena_mprj[125]),
+ .X(net288),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input289 (.A(la_iena_mprj[126]),
+ .X(net289),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input29 (.A(la_data_out_core[122]),
+ .X(net29),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input290 (.A(la_iena_mprj[127]),
+ .X(net290),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input291 (.A(la_iena_mprj[12]),
+ .X(net291),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input292 (.A(la_iena_mprj[13]),
+ .X(net292),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input293 (.A(la_iena_mprj[14]),
+ .X(net293),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input294 (.A(la_iena_mprj[15]),
+ .X(net294),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input295 (.A(la_iena_mprj[16]),
+ .X(net295),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input296 (.A(la_iena_mprj[17]),
+ .X(net296),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input297 (.A(la_iena_mprj[18]),
+ .X(net297),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input298 (.A(la_iena_mprj[19]),
+ .X(net298),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input299 (.A(la_iena_mprj[1]),
+ .X(net299),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input3 (.A(caravel_rstn),
+ .X(net3),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input30 (.A(la_data_out_core[123]),
+ .X(net30),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input300 (.A(la_iena_mprj[20]),
+ .X(net300),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input301 (.A(la_iena_mprj[21]),
+ .X(net301),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input302 (.A(la_iena_mprj[22]),
+ .X(net302),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input303 (.A(la_iena_mprj[23]),
+ .X(net303),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input304 (.A(la_iena_mprj[24]),
+ .X(net304),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input305 (.A(la_iena_mprj[25]),
+ .X(net305),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input306 (.A(la_iena_mprj[26]),
+ .X(net306),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input307 (.A(la_iena_mprj[27]),
+ .X(net307),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input308 (.A(la_iena_mprj[28]),
+ .X(net308),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input309 (.A(la_iena_mprj[29]),
+ .X(net309),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input31 (.A(la_data_out_core[124]),
+ .X(net31),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input310 (.A(la_iena_mprj[2]),
+ .X(net310),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input311 (.A(la_iena_mprj[30]),
+ .X(net311),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input312 (.A(la_iena_mprj[31]),
+ .X(net312),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input313 (.A(la_iena_mprj[32]),
+ .X(net313),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input314 (.A(la_iena_mprj[33]),
+ .X(net314),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input315 (.A(la_iena_mprj[34]),
+ .X(net315),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input316 (.A(la_iena_mprj[35]),
+ .X(net316),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input317 (.A(la_iena_mprj[36]),
+ .X(net317),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input318 (.A(la_iena_mprj[37]),
+ .X(net318),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input319 (.A(la_iena_mprj[38]),
+ .X(net319),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input32 (.A(la_data_out_core[125]),
+ .X(net32),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input320 (.A(la_iena_mprj[39]),
+ .X(net320),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input321 (.A(la_iena_mprj[3]),
+ .X(net321),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input322 (.A(la_iena_mprj[40]),
+ .X(net322),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input323 (.A(la_iena_mprj[41]),
+ .X(net323),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input324 (.A(la_iena_mprj[42]),
+ .X(net324),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input325 (.A(la_iena_mprj[43]),
+ .X(net325),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input326 (.A(la_iena_mprj[44]),
+ .X(net326),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input327 (.A(la_iena_mprj[45]),
+ .X(net327),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input328 (.A(la_iena_mprj[46]),
+ .X(net328),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input329 (.A(la_iena_mprj[47]),
+ .X(net329),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input33 (.A(la_data_out_core[126]),
+ .X(net33),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input330 (.A(la_iena_mprj[48]),
+ .X(net330),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input331 (.A(la_iena_mprj[49]),
+ .X(net331),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input332 (.A(la_iena_mprj[4]),
+ .X(net332),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input333 (.A(la_iena_mprj[50]),
+ .X(net333),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input334 (.A(la_iena_mprj[51]),
+ .X(net334),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input335 (.A(la_iena_mprj[52]),
+ .X(net335),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input336 (.A(la_iena_mprj[53]),
+ .X(net336),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input337 (.A(la_iena_mprj[54]),
+ .X(net337),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input338 (.A(la_iena_mprj[55]),
+ .X(net338),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input339 (.A(la_iena_mprj[56]),
+ .X(net339),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input34 (.A(la_data_out_core[127]),
+ .X(net34),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input340 (.A(la_iena_mprj[57]),
+ .X(net340),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input341 (.A(la_iena_mprj[58]),
+ .X(net341),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input342 (.A(la_iena_mprj[59]),
+ .X(net342),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input343 (.A(la_iena_mprj[5]),
+ .X(net343),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input344 (.A(la_iena_mprj[60]),
+ .X(net344),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input345 (.A(la_iena_mprj[61]),
+ .X(net345),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input346 (.A(la_iena_mprj[62]),
+ .X(net346),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input347 (.A(la_iena_mprj[63]),
+ .X(net347),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input348 (.A(la_iena_mprj[64]),
+ .X(net348),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input349 (.A(la_iena_mprj[65]),
+ .X(net349),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input35 (.A(la_data_out_core[12]),
+ .X(net35),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input350 (.A(la_iena_mprj[66]),
+ .X(net350),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input351 (.A(la_iena_mprj[67]),
+ .X(net351),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input352 (.A(la_iena_mprj[68]),
+ .X(net352),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input353 (.A(la_iena_mprj[69]),
+ .X(net353),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input354 (.A(la_iena_mprj[6]),
+ .X(net354),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input355 (.A(la_iena_mprj[70]),
+ .X(net355),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input356 (.A(la_iena_mprj[71]),
+ .X(net356),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input357 (.A(la_iena_mprj[72]),
+ .X(net357),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input358 (.A(la_iena_mprj[73]),
+ .X(net358),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input359 (.A(la_iena_mprj[74]),
+ .X(net359),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input36 (.A(la_data_out_core[13]),
+ .X(net36),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input360 (.A(la_iena_mprj[75]),
+ .X(net360),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input361 (.A(la_iena_mprj[76]),
+ .X(net361),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input362 (.A(la_iena_mprj[77]),
+ .X(net362),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input363 (.A(la_iena_mprj[78]),
+ .X(net363),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input364 (.A(la_iena_mprj[79]),
+ .X(net364),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input365 (.A(la_iena_mprj[7]),
+ .X(net365),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input366 (.A(la_iena_mprj[80]),
+ .X(net366),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input367 (.A(la_iena_mprj[81]),
+ .X(net367),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input368 (.A(la_iena_mprj[82]),
+ .X(net368),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input369 (.A(la_iena_mprj[83]),
+ .X(net369),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input37 (.A(la_data_out_core[14]),
+ .X(net37),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input370 (.A(la_iena_mprj[84]),
+ .X(net370),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input371 (.A(la_iena_mprj[85]),
+ .X(net371),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input372 (.A(la_iena_mprj[86]),
+ .X(net372),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input373 (.A(la_iena_mprj[87]),
+ .X(net373),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input374 (.A(la_iena_mprj[88]),
+ .X(net374),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input375 (.A(la_iena_mprj[89]),
+ .X(net375),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input376 (.A(la_iena_mprj[8]),
+ .X(net376),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input377 (.A(la_iena_mprj[90]),
+ .X(net377),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input378 (.A(la_iena_mprj[91]),
+ .X(net378),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input379 (.A(la_iena_mprj[92]),
+ .X(net379),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input38 (.A(la_data_out_core[15]),
+ .X(net38),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input380 (.A(la_iena_mprj[93]),
+ .X(net380),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input381 (.A(la_iena_mprj[94]),
+ .X(net381),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input382 (.A(la_iena_mprj[95]),
+ .X(net382),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input383 (.A(la_iena_mprj[96]),
+ .X(net383),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input384 (.A(la_iena_mprj[97]),
+ .X(net384),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input385 (.A(la_iena_mprj[98]),
+ .X(net385),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input386 (.A(la_iena_mprj[99]),
+ .X(net386),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input387 (.A(la_iena_mprj[9]),
+ .X(net387),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input388 (.A(la_oenb_mprj[0]),
+ .X(net388),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input389 (.A(la_oenb_mprj[100]),
+ .X(net389),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input39 (.A(la_data_out_core[16]),
+ .X(net39),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input390 (.A(la_oenb_mprj[101]),
+ .X(net390),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input391 (.A(la_oenb_mprj[102]),
+ .X(net391),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input392 (.A(la_oenb_mprj[103]),
+ .X(net392),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input393 (.A(la_oenb_mprj[104]),
+ .X(net393),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input394 (.A(la_oenb_mprj[105]),
+ .X(net394),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input395 (.A(la_oenb_mprj[106]),
+ .X(net395),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input396 (.A(la_oenb_mprj[107]),
+ .X(net396),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input397 (.A(la_oenb_mprj[108]),
+ .X(net397),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input398 (.A(la_oenb_mprj[109]),
+ .X(net398),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input399 (.A(la_oenb_mprj[10]),
+ .X(net399),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input4 (.A(la_data_out_core[0]),
+ .X(net4),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input40 (.A(la_data_out_core[17]),
+ .X(net40),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input400 (.A(la_oenb_mprj[110]),
+ .X(net400),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input401 (.A(la_oenb_mprj[111]),
+ .X(net401),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input402 (.A(la_oenb_mprj[112]),
+ .X(net402),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input403 (.A(la_oenb_mprj[113]),
+ .X(net403),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input404 (.A(la_oenb_mprj[114]),
+ .X(net404),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input405 (.A(la_oenb_mprj[115]),
+ .X(net405),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input406 (.A(la_oenb_mprj[116]),
+ .X(net406),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input407 (.A(la_oenb_mprj[117]),
+ .X(net407),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input408 (.A(la_oenb_mprj[118]),
+ .X(net408),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input409 (.A(la_oenb_mprj[119]),
+ .X(net409),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input41 (.A(la_data_out_core[18]),
+ .X(net41),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input410 (.A(la_oenb_mprj[11]),
+ .X(net410),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input411 (.A(la_oenb_mprj[120]),
+ .X(net411),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input412 (.A(la_oenb_mprj[121]),
+ .X(net412),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input413 (.A(la_oenb_mprj[122]),
+ .X(net413),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input414 (.A(la_oenb_mprj[123]),
+ .X(net414),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input415 (.A(la_oenb_mprj[124]),
+ .X(net415),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input416 (.A(la_oenb_mprj[125]),
+ .X(net416),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input417 (.A(la_oenb_mprj[126]),
+ .X(net417),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input418 (.A(la_oenb_mprj[127]),
+ .X(net418),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input419 (.A(la_oenb_mprj[12]),
+ .X(net419),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input42 (.A(la_data_out_core[19]),
+ .X(net42),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input420 (.A(la_oenb_mprj[13]),
+ .X(net420),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input421 (.A(la_oenb_mprj[14]),
+ .X(net421),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input422 (.A(la_oenb_mprj[15]),
+ .X(net422),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input423 (.A(la_oenb_mprj[16]),
+ .X(net423),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input424 (.A(la_oenb_mprj[17]),
+ .X(net424),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input425 (.A(la_oenb_mprj[18]),
+ .X(net425),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input426 (.A(la_oenb_mprj[19]),
+ .X(net426),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input427 (.A(la_oenb_mprj[1]),
+ .X(net427),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input428 (.A(la_oenb_mprj[20]),
+ .X(net428),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input429 (.A(la_oenb_mprj[21]),
+ .X(net429),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input43 (.A(la_data_out_core[1]),
+ .X(net43),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input430 (.A(la_oenb_mprj[22]),
+ .X(net430),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input431 (.A(la_oenb_mprj[23]),
+ .X(net431),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input432 (.A(la_oenb_mprj[24]),
+ .X(net432),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input433 (.A(la_oenb_mprj[25]),
+ .X(net433),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input434 (.A(la_oenb_mprj[26]),
+ .X(net434),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input435 (.A(la_oenb_mprj[27]),
+ .X(net435),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input436 (.A(la_oenb_mprj[28]),
+ .X(net436),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input437 (.A(la_oenb_mprj[29]),
+ .X(net437),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input438 (.A(la_oenb_mprj[2]),
+ .X(net438),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input439 (.A(la_oenb_mprj[30]),
+ .X(net439),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input44 (.A(la_data_out_core[20]),
+ .X(net44),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input440 (.A(la_oenb_mprj[31]),
+ .X(net440),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input441 (.A(la_oenb_mprj[32]),
+ .X(net441),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input442 (.A(la_oenb_mprj[33]),
+ .X(net442),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input443 (.A(la_oenb_mprj[34]),
+ .X(net443),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input444 (.A(la_oenb_mprj[35]),
+ .X(net444),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input445 (.A(la_oenb_mprj[36]),
+ .X(net445),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input446 (.A(la_oenb_mprj[37]),
+ .X(net446),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input447 (.A(la_oenb_mprj[38]),
+ .X(net447),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input448 (.A(la_oenb_mprj[39]),
+ .X(net448),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input449 (.A(la_oenb_mprj[3]),
+ .X(net449),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input45 (.A(la_data_out_core[21]),
+ .X(net45),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input450 (.A(la_oenb_mprj[40]),
+ .X(net450),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input451 (.A(la_oenb_mprj[41]),
+ .X(net451),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input452 (.A(la_oenb_mprj[42]),
+ .X(net452),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input453 (.A(la_oenb_mprj[43]),
+ .X(net453),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input454 (.A(la_oenb_mprj[44]),
+ .X(net454),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input455 (.A(la_oenb_mprj[45]),
+ .X(net455),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input456 (.A(la_oenb_mprj[46]),
+ .X(net456),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input457 (.A(la_oenb_mprj[47]),
+ .X(net457),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input458 (.A(la_oenb_mprj[48]),
+ .X(net458),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input459 (.A(la_oenb_mprj[49]),
+ .X(net459),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input46 (.A(la_data_out_core[22]),
+ .X(net46),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input460 (.A(la_oenb_mprj[4]),
+ .X(net460),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input461 (.A(la_oenb_mprj[50]),
+ .X(net461),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input462 (.A(la_oenb_mprj[51]),
+ .X(net462),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input463 (.A(la_oenb_mprj[52]),
+ .X(net463),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input464 (.A(la_oenb_mprj[53]),
+ .X(net464),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input465 (.A(la_oenb_mprj[54]),
+ .X(net465),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input466 (.A(la_oenb_mprj[55]),
+ .X(net466),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input467 (.A(la_oenb_mprj[56]),
+ .X(net467),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input468 (.A(la_oenb_mprj[57]),
+ .X(net468),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input469 (.A(la_oenb_mprj[58]),
+ .X(net469),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input47 (.A(la_data_out_core[23]),
+ .X(net47),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input470 (.A(la_oenb_mprj[59]),
+ .X(net470),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input471 (.A(la_oenb_mprj[5]),
+ .X(net471),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input472 (.A(la_oenb_mprj[60]),
+ .X(net472),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input473 (.A(la_oenb_mprj[61]),
+ .X(net473),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input474 (.A(la_oenb_mprj[62]),
+ .X(net474),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input475 (.A(la_oenb_mprj[63]),
+ .X(net475),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input476 (.A(la_oenb_mprj[64]),
+ .X(net476),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input477 (.A(la_oenb_mprj[65]),
+ .X(net477),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input478 (.A(la_oenb_mprj[66]),
+ .X(net478),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input479 (.A(la_oenb_mprj[67]),
+ .X(net479),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input48 (.A(la_data_out_core[24]),
+ .X(net48),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input480 (.A(la_oenb_mprj[68]),
+ .X(net480),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input481 (.A(la_oenb_mprj[69]),
+ .X(net481),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input482 (.A(la_oenb_mprj[6]),
+ .X(net482),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input483 (.A(la_oenb_mprj[70]),
+ .X(net483),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input484 (.A(la_oenb_mprj[71]),
+ .X(net484),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input485 (.A(la_oenb_mprj[72]),
+ .X(net485),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input486 (.A(la_oenb_mprj[73]),
+ .X(net486),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input487 (.A(la_oenb_mprj[74]),
+ .X(net487),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input488 (.A(la_oenb_mprj[75]),
+ .X(net488),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input489 (.A(la_oenb_mprj[76]),
+ .X(net489),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input49 (.A(la_data_out_core[25]),
+ .X(net49),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input490 (.A(la_oenb_mprj[77]),
+ .X(net490),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input491 (.A(la_oenb_mprj[78]),
+ .X(net491),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input492 (.A(la_oenb_mprj[79]),
+ .X(net492),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input493 (.A(la_oenb_mprj[7]),
+ .X(net493),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input494 (.A(la_oenb_mprj[80]),
+ .X(net494),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input495 (.A(la_oenb_mprj[81]),
+ .X(net495),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input496 (.A(la_oenb_mprj[82]),
+ .X(net496),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input497 (.A(la_oenb_mprj[83]),
+ .X(net497),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input498 (.A(la_oenb_mprj[84]),
+ .X(net498),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input499 (.A(la_oenb_mprj[85]),
+ .X(net499),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input5 (.A(la_data_out_core[100]),
+ .X(net5),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input50 (.A(la_data_out_core[26]),
+ .X(net50),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input500 (.A(la_oenb_mprj[86]),
+ .X(net500),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input501 (.A(la_oenb_mprj[87]),
+ .X(net501),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input502 (.A(la_oenb_mprj[88]),
+ .X(net502),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input503 (.A(la_oenb_mprj[89]),
+ .X(net503),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input504 (.A(la_oenb_mprj[8]),
+ .X(net504),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input505 (.A(la_oenb_mprj[90]),
+ .X(net505),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input506 (.A(la_oenb_mprj[91]),
+ .X(net506),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input507 (.A(la_oenb_mprj[92]),
+ .X(net507),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input508 (.A(la_oenb_mprj[93]),
+ .X(net508),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input509 (.A(la_oenb_mprj[94]),
+ .X(net509),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input51 (.A(la_data_out_core[27]),
+ .X(net51),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input510 (.A(la_oenb_mprj[95]),
+ .X(net510),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input511 (.A(la_oenb_mprj[96]),
+ .X(net511),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input512 (.A(la_oenb_mprj[97]),
+ .X(net512),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input513 (.A(la_oenb_mprj[98]),
+ .X(net513),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input514 (.A(la_oenb_mprj[99]),
+ .X(net514),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input515 (.A(la_oenb_mprj[9]),
+ .X(net515),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input516 (.A(mprj_ack_i_user),
+ .X(net516),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input517 (.A(mprj_adr_o_core[0]),
+ .X(net517),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input518 (.A(mprj_adr_o_core[10]),
+ .X(net518),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input519 (.A(mprj_adr_o_core[11]),
+ .X(net519),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input52 (.A(la_data_out_core[28]),
+ .X(net52),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input520 (.A(mprj_adr_o_core[12]),
+ .X(net520),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input521 (.A(mprj_adr_o_core[13]),
+ .X(net521),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input522 (.A(mprj_adr_o_core[14]),
+ .X(net522),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input523 (.A(mprj_adr_o_core[15]),
+ .X(net523),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input524 (.A(mprj_adr_o_core[16]),
+ .X(net524),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input525 (.A(mprj_adr_o_core[17]),
+ .X(net525),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input526 (.A(mprj_adr_o_core[18]),
+ .X(net526),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input527 (.A(mprj_adr_o_core[19]),
+ .X(net527),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input528 (.A(mprj_adr_o_core[1]),
+ .X(net528),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input529 (.A(mprj_adr_o_core[20]),
+ .X(net529),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input53 (.A(la_data_out_core[29]),
+ .X(net53),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input530 (.A(mprj_adr_o_core[21]),
+ .X(net530),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input531 (.A(mprj_adr_o_core[22]),
+ .X(net531),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input532 (.A(mprj_adr_o_core[23]),
+ .X(net532),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input533 (.A(mprj_adr_o_core[24]),
+ .X(net533),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input534 (.A(mprj_adr_o_core[25]),
+ .X(net534),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input535 (.A(mprj_adr_o_core[26]),
+ .X(net535),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input536 (.A(mprj_adr_o_core[27]),
+ .X(net536),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input537 (.A(mprj_adr_o_core[28]),
+ .X(net537),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input538 (.A(mprj_adr_o_core[29]),
+ .X(net538),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input539 (.A(mprj_adr_o_core[2]),
+ .X(net539),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input54 (.A(la_data_out_core[2]),
+ .X(net54),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input540 (.A(mprj_adr_o_core[30]),
+ .X(net540),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input541 (.A(mprj_adr_o_core[31]),
+ .X(net541),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input542 (.A(mprj_adr_o_core[3]),
+ .X(net542),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input543 (.A(mprj_adr_o_core[4]),
+ .X(net543),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input544 (.A(mprj_adr_o_core[5]),
+ .X(net544),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input545 (.A(mprj_adr_o_core[6]),
+ .X(net545),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input546 (.A(mprj_adr_o_core[7]),
+ .X(net546),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input547 (.A(mprj_adr_o_core[8]),
+ .X(net547),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input548 (.A(mprj_adr_o_core[9]),
+ .X(net548),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input549 (.A(mprj_cyc_o_core),
+ .X(net549),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input55 (.A(la_data_out_core[30]),
+ .X(net55),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input550 (.A(mprj_dat_i_user[0]),
+ .X(net550),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input551 (.A(mprj_dat_i_user[10]),
+ .X(net551),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input552 (.A(mprj_dat_i_user[11]),
+ .X(net552),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input553 (.A(mprj_dat_i_user[12]),
+ .X(net553),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input554 (.A(mprj_dat_i_user[13]),
+ .X(net554),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input555 (.A(mprj_dat_i_user[14]),
+ .X(net555),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input556 (.A(mprj_dat_i_user[15]),
+ .X(net556),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input557 (.A(mprj_dat_i_user[16]),
+ .X(net557),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input558 (.A(mprj_dat_i_user[17]),
+ .X(net558),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input559 (.A(mprj_dat_i_user[18]),
+ .X(net559),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input56 (.A(la_data_out_core[31]),
+ .X(net56),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input560 (.A(mprj_dat_i_user[19]),
+ .X(net560),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 input561 (.A(mprj_dat_i_user[1]),
+ .X(net561),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 input562 (.A(mprj_dat_i_user[20]),
+ .X(net562),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_8 input563 (.A(mprj_dat_i_user[21]),
+ .X(net563),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_8 input564 (.A(mprj_dat_i_user[22]),
+ .X(net564),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_6 input565 (.A(mprj_dat_i_user[23]),
+ .X(net565),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input566 (.A(mprj_dat_i_user[24]),
+ .X(net566),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input567 (.A(mprj_dat_i_user[25]),
+ .X(net567),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input568 (.A(mprj_dat_i_user[26]),
+ .X(net568),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input569 (.A(mprj_dat_i_user[27]),
+ .X(net569),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input57 (.A(la_data_out_core[32]),
+ .X(net57),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input570 (.A(mprj_dat_i_user[28]),
+ .X(net570),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input571 (.A(mprj_dat_i_user[29]),
+ .X(net571),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_8 input572 (.A(mprj_dat_i_user[2]),
+ .X(net572),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input573 (.A(mprj_dat_i_user[30]),
+ .X(net573),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input574 (.A(mprj_dat_i_user[31]),
+ .X(net574),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_8 input575 (.A(mprj_dat_i_user[3]),
+ .X(net575),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 input576 (.A(mprj_dat_i_user[4]),
+ .X(net576),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input577 (.A(mprj_dat_i_user[5]),
+ .X(net577),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_12 input578 (.A(mprj_dat_i_user[6]),
+ .X(net578),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_8 input579 (.A(mprj_dat_i_user[7]),
+ .X(net579),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input58 (.A(la_data_out_core[33]),
+ .X(net58),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 input580 (.A(mprj_dat_i_user[8]),
+ .X(net580),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_16 input581 (.A(mprj_dat_i_user[9]),
+ .X(net581),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input582 (.A(mprj_dat_o_core[0]),
+ .X(net582),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input583 (.A(mprj_dat_o_core[10]),
+ .X(net583),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input584 (.A(mprj_dat_o_core[11]),
+ .X(net584),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input585 (.A(mprj_dat_o_core[12]),
+ .X(net585),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input586 (.A(mprj_dat_o_core[13]),
+ .X(net586),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input587 (.A(mprj_dat_o_core[14]),
+ .X(net587),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input588 (.A(mprj_dat_o_core[15]),
+ .X(net588),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input589 (.A(mprj_dat_o_core[16]),
+ .X(net589),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input59 (.A(la_data_out_core[34]),
+ .X(net59),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input590 (.A(mprj_dat_o_core[17]),
+ .X(net590),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input591 (.A(mprj_dat_o_core[18]),
+ .X(net591),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input592 (.A(mprj_dat_o_core[19]),
+ .X(net592),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input593 (.A(mprj_dat_o_core[1]),
+ .X(net593),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input594 (.A(mprj_dat_o_core[20]),
+ .X(net594),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input595 (.A(mprj_dat_o_core[21]),
+ .X(net595),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input596 (.A(mprj_dat_o_core[22]),
+ .X(net596),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input597 (.A(mprj_dat_o_core[23]),
+ .X(net597),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input598 (.A(mprj_dat_o_core[24]),
+ .X(net598),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input599 (.A(mprj_dat_o_core[25]),
+ .X(net599),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input6 (.A(la_data_out_core[101]),
+ .X(net6),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input60 (.A(la_data_out_core[35]),
+ .X(net60),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input600 (.A(mprj_dat_o_core[26]),
+ .X(net600),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input601 (.A(mprj_dat_o_core[27]),
+ .X(net601),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input602 (.A(mprj_dat_o_core[28]),
+ .X(net602),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input603 (.A(mprj_dat_o_core[29]),
+ .X(net603),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input604 (.A(mprj_dat_o_core[2]),
+ .X(net604),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input605 (.A(mprj_dat_o_core[30]),
+ .X(net605),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input606 (.A(mprj_dat_o_core[31]),
+ .X(net606),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input607 (.A(mprj_dat_o_core[3]),
+ .X(net607),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input608 (.A(mprj_dat_o_core[4]),
+ .X(net608),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input609 (.A(mprj_dat_o_core[5]),
+ .X(net609),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input61 (.A(la_data_out_core[36]),
+ .X(net61),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input610 (.A(mprj_dat_o_core[6]),
+ .X(net610),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input611 (.A(mprj_dat_o_core[7]),
+ .X(net611),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input612 (.A(mprj_dat_o_core[8]),
+ .X(net612),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input613 (.A(mprj_dat_o_core[9]),
+ .X(net613),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_6 input614 (.A(mprj_iena_wb),
+ .X(net614),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dlymetal6s2s_1 input615 (.A(mprj_sel_o_core[0]),
+ .X(net615),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input616 (.A(mprj_sel_o_core[1]),
+ .X(net616),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 input617 (.A(mprj_sel_o_core[2]),
+ .X(net617),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input618 (.A(mprj_sel_o_core[3]),
+ .X(net618),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input619 (.A(mprj_stb_o_core),
+ .X(net619),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input62 (.A(la_data_out_core[37]),
+ .X(net62),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_2 input620 (.A(mprj_we_o_core),
+ .X(net620),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input621 (.A(user_irq_core[0]),
+ .X(net621),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input622 (.A(user_irq_core[1]),
+ .X(net622),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input623 (.A(user_irq_core[2]),
+ .X(net623),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input624 (.A(user_irq_ena[0]),
+ .X(net624),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input625 (.A(user_irq_ena[1]),
+ .X(net625),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_1 input626 (.A(user_irq_ena[2]),
+ .X(net626),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input63 (.A(la_data_out_core[38]),
+ .X(net63),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input64 (.A(la_data_out_core[39]),
+ .X(net64),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input65 (.A(la_data_out_core[3]),
+ .X(net65),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input66 (.A(la_data_out_core[40]),
+ .X(net66),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input67 (.A(la_data_out_core[41]),
+ .X(net67),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input68 (.A(la_data_out_core[42]),
+ .X(net68),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input69 (.A(la_data_out_core[43]),
+ .X(net69),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input7 (.A(la_data_out_core[102]),
+ .X(net7),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input70 (.A(la_data_out_core[44]),
+ .X(net70),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input71 (.A(la_data_out_core[45]),
+ .X(net71),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input72 (.A(la_data_out_core[46]),
+ .X(net72),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input73 (.A(la_data_out_core[47]),
+ .X(net73),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input74 (.A(la_data_out_core[48]),
+ .X(net74),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input75 (.A(la_data_out_core[49]),
+ .X(net75),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input76 (.A(la_data_out_core[4]),
+ .X(net76),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input77 (.A(la_data_out_core[50]),
+ .X(net77),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input78 (.A(la_data_out_core[51]),
+ .X(net78),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input79 (.A(la_data_out_core[52]),
+ .X(net79),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input8 (.A(la_data_out_core[103]),
+ .X(net8),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input80 (.A(la_data_out_core[53]),
+ .X(net80),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input81 (.A(la_data_out_core[54]),
+ .X(net81),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input82 (.A(la_data_out_core[55]),
+ .X(net82),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input83 (.A(la_data_out_core[56]),
+ .X(net83),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input84 (.A(la_data_out_core[57]),
+ .X(net84),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input85 (.A(la_data_out_core[58]),
+ .X(net85),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input86 (.A(la_data_out_core[59]),
+ .X(net86),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input87 (.A(la_data_out_core[5]),
+ .X(net87),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input88 (.A(la_data_out_core[60]),
+ .X(net88),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input89 (.A(la_data_out_core[61]),
+ .X(net89),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkbuf_4 input9 (.A(la_data_out_core[104]),
+ .X(net9),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input90 (.A(la_data_out_core[62]),
+ .X(net90),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input91 (.A(la_data_out_core[63]),
+ .X(net91),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input92 (.A(la_data_out_core[64]),
+ .X(net92),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input93 (.A(la_data_out_core[65]),
+ .X(net93),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input94 (.A(la_data_out_core[66]),
+ .X(net94),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input95 (.A(la_data_out_core[67]),
+ .X(net95),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input96 (.A(la_data_out_core[68]),
+ .X(net96),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input97 (.A(la_data_out_core[69]),
+ .X(net97),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input98 (.A(la_data_out_core[6]),
+ .X(net98),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_4 input99 (.A(la_data_out_core[70]),
+ .X(net99),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[0] (.A(_073_),
+ .TE(\la_data_out_enable[0] ),
+ .Z(net627),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[100] (.A(_074_),
+ .TE(\la_data_out_enable[100] ),
+ .Z(net628),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[101] (.A(_075_),
+ .TE(\la_data_out_enable[101] ),
+ .Z(net629),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[102] (.A(_076_),
+ .TE(\la_data_out_enable[102] ),
+ .Z(net630),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[103] (.A(_077_),
+ .TE(\la_data_out_enable[103] ),
+ .Z(net631),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[104] (.A(_078_),
+ .TE(\la_data_out_enable[104] ),
+ .Z(net632),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[105] (.A(_079_),
+ .TE(\la_data_out_enable[105] ),
+ .Z(net633),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[106] (.A(_080_),
+ .TE(\la_data_out_enable[106] ),
+ .Z(net634),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[107] (.A(_081_),
+ .TE(\la_data_out_enable[107] ),
+ .Z(net635),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[108] (.A(_082_),
+ .TE(\la_data_out_enable[108] ),
+ .Z(net636),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[109] (.A(_083_),
+ .TE(\la_data_out_enable[109] ),
+ .Z(net637),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[10] (.A(_084_),
+ .TE(\la_data_out_enable[10] ),
+ .Z(net638),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[110] (.A(_085_),
+ .TE(\la_data_out_enable[110] ),
+ .Z(net639),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[111] (.A(_086_),
+ .TE(\la_data_out_enable[111] ),
+ .Z(net640),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[112] (.A(_087_),
+ .TE(\la_data_out_enable[112] ),
+ .Z(net641),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[113] (.A(_088_),
+ .TE(\la_data_out_enable[113] ),
+ .Z(net642),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[114] (.A(_089_),
+ .TE(\la_data_out_enable[114] ),
+ .Z(net643),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[115] (.A(_090_),
+ .TE(\la_data_out_enable[115] ),
+ .Z(net644),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[116] (.A(_091_),
+ .TE(\la_data_out_enable[116] ),
+ .Z(net645),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[117] (.A(_092_),
+ .TE(\la_data_out_enable[117] ),
+ .Z(net646),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[118] (.A(_093_),
+ .TE(\la_data_out_enable[118] ),
+ .Z(net647),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[119] (.A(_094_),
+ .TE(\la_data_out_enable[119] ),
+ .Z(net648),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[11] (.A(_095_),
+ .TE(\la_data_out_enable[11] ),
+ .Z(net649),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[120] (.A(_096_),
+ .TE(\la_data_out_enable[120] ),
+ .Z(net650),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[121] (.A(_097_),
+ .TE(\la_data_out_enable[121] ),
+ .Z(net651),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[122] (.A(_098_),
+ .TE(\la_data_out_enable[122] ),
+ .Z(net652),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[123] (.A(_099_),
+ .TE(\la_data_out_enable[123] ),
+ .Z(net653),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[124] (.A(_100_),
+ .TE(\la_data_out_enable[124] ),
+ .Z(net654),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[125] (.A(_101_),
+ .TE(\la_data_out_enable[125] ),
+ .Z(net655),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[126] (.A(_102_),
+ .TE(\la_data_out_enable[126] ),
+ .Z(net656),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[127] (.A(_103_),
+ .TE(\la_data_out_enable[127] ),
+ .Z(net657),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[12] (.A(_104_),
+ .TE(\la_data_out_enable[12] ),
+ .Z(net658),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[13] (.A(_105_),
+ .TE(\la_data_out_enable[13] ),
+ .Z(net659),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[14] (.A(_106_),
+ .TE(\la_data_out_enable[14] ),
+ .Z(net660),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[15] (.A(_107_),
+ .TE(\la_data_out_enable[15] ),
+ .Z(net661),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[16] (.A(_108_),
+ .TE(\la_data_out_enable[16] ),
+ .Z(net662),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[17] (.A(_109_),
+ .TE(\la_data_out_enable[17] ),
+ .Z(net663),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[18] (.A(_110_),
+ .TE(\la_data_out_enable[18] ),
+ .Z(net664),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[19] (.A(_111_),
+ .TE(\la_data_out_enable[19] ),
+ .Z(net665),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[1] (.A(_112_),
+ .TE(\la_data_out_enable[1] ),
+ .Z(net666),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[20] (.A(_113_),
+ .TE(\la_data_out_enable[20] ),
+ .Z(net667),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[21] (.A(_114_),
+ .TE(\la_data_out_enable[21] ),
+ .Z(net668),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[22] (.A(_115_),
+ .TE(\la_data_out_enable[22] ),
+ .Z(net669),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[23] (.A(_116_),
+ .TE(\la_data_out_enable[23] ),
+ .Z(net670),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[24] (.A(_117_),
+ .TE(\la_data_out_enable[24] ),
+ .Z(net671),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[25] (.A(_118_),
+ .TE(\la_data_out_enable[25] ),
+ .Z(net672),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[26] (.A(_119_),
+ .TE(\la_data_out_enable[26] ),
+ .Z(net673),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[27] (.A(_120_),
+ .TE(\la_data_out_enable[27] ),
+ .Z(net674),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[28] (.A(_121_),
+ .TE(\la_data_out_enable[28] ),
+ .Z(net675),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[29] (.A(_122_),
+ .TE(\la_data_out_enable[29] ),
+ .Z(net676),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[2] (.A(_123_),
+ .TE(\la_data_out_enable[2] ),
+ .Z(net677),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[30] (.A(_124_),
+ .TE(\la_data_out_enable[30] ),
+ .Z(net678),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[31] (.A(_125_),
+ .TE(\la_data_out_enable[31] ),
+ .Z(net679),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[32] (.A(_126_),
+ .TE(\la_data_out_enable[32] ),
+ .Z(net680),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[33] (.A(_127_),
+ .TE(\la_data_out_enable[33] ),
+ .Z(net681),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[34] (.A(_128_),
+ .TE(\la_data_out_enable[34] ),
+ .Z(net682),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[35] (.A(_129_),
+ .TE(\la_data_out_enable[35] ),
+ .Z(net683),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[36] (.A(_130_),
+ .TE(\la_data_out_enable[36] ),
+ .Z(net684),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[37] (.A(_131_),
+ .TE(\la_data_out_enable[37] ),
+ .Z(net685),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[38] (.A(_132_),
+ .TE(\la_data_out_enable[38] ),
+ .Z(net686),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[39] (.A(_133_),
+ .TE(\la_data_out_enable[39] ),
+ .Z(net687),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[3] (.A(_134_),
+ .TE(\la_data_out_enable[3] ),
+ .Z(net688),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[40] (.A(_135_),
+ .TE(\la_data_out_enable[40] ),
+ .Z(net689),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[41] (.A(_136_),
+ .TE(\la_data_out_enable[41] ),
+ .Z(net690),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[42] (.A(_137_),
+ .TE(\la_data_out_enable[42] ),
+ .Z(net691),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[43] (.A(_138_),
+ .TE(\la_data_out_enable[43] ),
+ .Z(net692),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[44] (.A(_139_),
+ .TE(\la_data_out_enable[44] ),
+ .Z(net693),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[45] (.A(_140_),
+ .TE(\la_data_out_enable[45] ),
+ .Z(net694),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[46] (.A(_141_),
+ .TE(\la_data_out_enable[46] ),
+ .Z(net695),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[47] (.A(_142_),
+ .TE(\la_data_out_enable[47] ),
+ .Z(net696),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[48] (.A(_143_),
+ .TE(\la_data_out_enable[48] ),
+ .Z(net697),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[49] (.A(_144_),
+ .TE(\la_data_out_enable[49] ),
+ .Z(net698),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[4] (.A(_145_),
+ .TE(\la_data_out_enable[4] ),
+ .Z(net699),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[50] (.A(_146_),
+ .TE(\la_data_out_enable[50] ),
+ .Z(net700),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[51] (.A(_147_),
+ .TE(\la_data_out_enable[51] ),
+ .Z(net701),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[52] (.A(_148_),
+ .TE(\la_data_out_enable[52] ),
+ .Z(net702),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[53] (.A(_149_),
+ .TE(\la_data_out_enable[53] ),
+ .Z(net703),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[54] (.A(_150_),
+ .TE(\la_data_out_enable[54] ),
+ .Z(net704),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[55] (.A(_151_),
+ .TE(\la_data_out_enable[55] ),
+ .Z(net705),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[56] (.A(_152_),
+ .TE(\la_data_out_enable[56] ),
+ .Z(net706),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[57] (.A(_153_),
+ .TE(\la_data_out_enable[57] ),
+ .Z(net707),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[58] (.A(_154_),
+ .TE(\la_data_out_enable[58] ),
+ .Z(net708),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[59] (.A(_155_),
+ .TE(\la_data_out_enable[59] ),
+ .Z(net709),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[5] (.A(_156_),
+ .TE(\la_data_out_enable[5] ),
+ .Z(net710),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[60] (.A(_157_),
+ .TE(\la_data_out_enable[60] ),
+ .Z(net711),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[61] (.A(_158_),
+ .TE(\la_data_out_enable[61] ),
+ .Z(net712),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[62] (.A(_159_),
+ .TE(\la_data_out_enable[62] ),
+ .Z(net713),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[63] (.A(_160_),
+ .TE(\la_data_out_enable[63] ),
+ .Z(net714),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[64] (.A(_161_),
+ .TE(\la_data_out_enable[64] ),
+ .Z(net715),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[65] (.A(_162_),
+ .TE(\la_data_out_enable[65] ),
+ .Z(net716),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[66] (.A(_163_),
+ .TE(\la_data_out_enable[66] ),
+ .Z(net717),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[67] (.A(_164_),
+ .TE(\la_data_out_enable[67] ),
+ .Z(net718),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[68] (.A(_165_),
+ .TE(\la_data_out_enable[68] ),
+ .Z(net719),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[69] (.A(_166_),
+ .TE(\la_data_out_enable[69] ),
+ .Z(net720),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[6] (.A(_167_),
+ .TE(\la_data_out_enable[6] ),
+ .Z(net721),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[70] (.A(_168_),
+ .TE(\la_data_out_enable[70] ),
+ .Z(net722),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[71] (.A(_169_),
+ .TE(\la_data_out_enable[71] ),
+ .Z(net723),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[72] (.A(_170_),
+ .TE(\la_data_out_enable[72] ),
+ .Z(net724),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[73] (.A(_171_),
+ .TE(\la_data_out_enable[73] ),
+ .Z(net725),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[74] (.A(_172_),
+ .TE(\la_data_out_enable[74] ),
+ .Z(net726),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[75] (.A(_173_),
+ .TE(\la_data_out_enable[75] ),
+ .Z(net727),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[76] (.A(_174_),
+ .TE(\la_data_out_enable[76] ),
+ .Z(net728),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[77] (.A(_175_),
+ .TE(\la_data_out_enable[77] ),
+ .Z(net729),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[78] (.A(_176_),
+ .TE(\la_data_out_enable[78] ),
+ .Z(net730),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[79] (.A(_177_),
+ .TE(\la_data_out_enable[79] ),
+ .Z(net731),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[7] (.A(_178_),
+ .TE(\la_data_out_enable[7] ),
+ .Z(net732),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[80] (.A(_179_),
+ .TE(\la_data_out_enable[80] ),
+ .Z(net733),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[81] (.A(_180_),
+ .TE(\la_data_out_enable[81] ),
+ .Z(net734),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[82] (.A(_181_),
+ .TE(\la_data_out_enable[82] ),
+ .Z(net735),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[83] (.A(_182_),
+ .TE(\la_data_out_enable[83] ),
+ .Z(net736),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[84] (.A(_183_),
+ .TE(\la_data_out_enable[84] ),
+ .Z(net737),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[85] (.A(_184_),
+ .TE(\la_data_out_enable[85] ),
+ .Z(net738),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[86] (.A(_185_),
+ .TE(\la_data_out_enable[86] ),
+ .Z(net739),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[87] (.A(_186_),
+ .TE(\la_data_out_enable[87] ),
+ .Z(net740),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[88] (.A(_187_),
+ .TE(\la_data_out_enable[88] ),
+ .Z(net741),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[89] (.A(_188_),
+ .TE(\la_data_out_enable[89] ),
+ .Z(net742),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[8] (.A(_189_),
+ .TE(\la_data_out_enable[8] ),
+ .Z(net743),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[90] (.A(_190_),
+ .TE(\la_data_out_enable[90] ),
+ .Z(net744),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[91] (.A(_191_),
+ .TE(\la_data_out_enable[91] ),
+ .Z(net745),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[92] (.A(_192_),
+ .TE(\la_data_out_enable[92] ),
+ .Z(net746),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[93] (.A(_193_),
+ .TE(\la_data_out_enable[93] ),
+ .Z(net747),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[94] (.A(_194_),
+ .TE(\la_data_out_enable[94] ),
+ .Z(net748),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[95] (.A(_195_),
+ .TE(\la_data_out_enable[95] ),
+ .Z(net749),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \la_buf[96] (.A(_196_),
+ .TE(\la_data_out_enable[96] ),
+ .Z(net750),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \la_buf[97] (.A(_197_),
+ .TE(\la_data_out_enable[97] ),
+ .Z(net751),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[98] (.A(_198_),
+ .TE(\la_data_out_enable[98] ),
+ .Z(net752),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[99] (.A(_199_),
+ .TE(\la_data_out_enable[99] ),
+ .Z(net753),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \la_buf[9] (.A(_200_),
+ .TE(\la_data_out_enable[9] ),
+ .Z(net754),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[0] (.A_N(net388),
+ .B(\mprj_logic1[74] ),
+ .X(\la_data_out_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[100] (.A_N(net389),
+ .B(\mprj_logic1[174] ),
+ .X(\la_data_out_enable[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[101] (.A_N(net390),
+ .B(\mprj_logic1[175] ),
+ .X(\la_data_out_enable[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[102] (.A_N(net391),
+ .B(\mprj_logic1[176] ),
+ .X(\la_data_out_enable[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[103] (.A_N(net392),
+ .B(\mprj_logic1[177] ),
+ .X(\la_data_out_enable[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[104] (.A_N(net393),
+ .B(\mprj_logic1[178] ),
+ .X(\la_data_out_enable[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[105] (.A_N(net394),
+ .B(\mprj_logic1[179] ),
+ .X(\la_data_out_enable[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[106] (.A_N(net395),
+ .B(\mprj_logic1[180] ),
+ .X(\la_data_out_enable[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[107] (.A_N(net396),
+ .B(\mprj_logic1[181] ),
+ .X(\la_data_out_enable[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[108] (.A_N(net397),
+ .B(\mprj_logic1[182] ),
+ .X(\la_data_out_enable[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[109] (.A_N(net398),
+ .B(\mprj_logic1[183] ),
+ .X(\la_data_out_enable[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[10] (.A_N(net399),
+ .B(\mprj_logic1[84] ),
+ .X(\la_data_out_enable[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[110] (.A_N(net400),
+ .B(\mprj_logic1[184] ),
+ .X(\la_data_out_enable[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[111] (.A_N(net401),
+ .B(\mprj_logic1[185] ),
+ .X(\la_data_out_enable[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[112] (.A_N(net402),
+ .B(\mprj_logic1[186] ),
+ .X(\la_data_out_enable[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[113] (.A_N(net403),
+ .B(\mprj_logic1[187] ),
+ .X(\la_data_out_enable[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[114] (.A_N(net404),
+ .B(\mprj_logic1[188] ),
+ .X(\la_data_out_enable[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[115] (.A_N(net405),
+ .B(\mprj_logic1[189] ),
+ .X(\la_data_out_enable[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[116] (.A_N(net406),
+ .B(\mprj_logic1[190] ),
+ .X(\la_data_out_enable[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[117] (.A_N(net407),
+ .B(\mprj_logic1[191] ),
+ .X(\la_data_out_enable[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[118] (.A_N(net408),
+ .B(\mprj_logic1[192] ),
+ .X(\la_data_out_enable[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[119] (.A_N(net409),
+ .B(\mprj_logic1[193] ),
+ .X(\la_data_out_enable[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[11] (.A_N(net410),
+ .B(\mprj_logic1[85] ),
+ .X(\la_data_out_enable[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[120] (.A_N(net411),
+ .B(\mprj_logic1[194] ),
+ .X(\la_data_out_enable[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[121] (.A_N(net412),
+ .B(\mprj_logic1[195] ),
+ .X(\la_data_out_enable[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[122] (.A_N(net413),
+ .B(\mprj_logic1[196] ),
+ .X(\la_data_out_enable[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[123] (.A_N(net414),
+ .B(\mprj_logic1[197] ),
+ .X(\la_data_out_enable[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[124] (.A_N(net415),
+ .B(\mprj_logic1[198] ),
+ .X(\la_data_out_enable[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[125] (.A_N(net416),
+ .B(\mprj_logic1[199] ),
+ .X(\la_data_out_enable[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[126] (.A_N(net417),
+ .B(\mprj_logic1[200] ),
+ .X(\la_data_out_enable[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[127] (.A_N(net418),
+ .B(\mprj_logic1[201] ),
+ .X(\la_data_out_enable[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[12] (.A_N(net419),
+ .B(\mprj_logic1[86] ),
+ .X(\la_data_out_enable[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[13] (.A_N(net420),
+ .B(\mprj_logic1[87] ),
+ .X(\la_data_out_enable[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[14] (.A_N(net421),
+ .B(\mprj_logic1[88] ),
+ .X(\la_data_out_enable[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[15] (.A_N(net422),
+ .B(\mprj_logic1[89] ),
+ .X(\la_data_out_enable[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[16] (.A_N(net423),
+ .B(\mprj_logic1[90] ),
+ .X(\la_data_out_enable[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[17] (.A_N(net424),
+ .B(\mprj_logic1[91] ),
+ .X(\la_data_out_enable[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[18] (.A_N(net425),
+ .B(\mprj_logic1[92] ),
+ .X(\la_data_out_enable[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[19] (.A_N(net426),
+ .B(\mprj_logic1[93] ),
+ .X(\la_data_out_enable[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[1] (.A_N(net427),
+ .B(\mprj_logic1[75] ),
+ .X(\la_data_out_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[20] (.A_N(net428),
+ .B(\mprj_logic1[94] ),
+ .X(\la_data_out_enable[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[21] (.A_N(net429),
+ .B(\mprj_logic1[95] ),
+ .X(\la_data_out_enable[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[22] (.A_N(net430),
+ .B(\mprj_logic1[96] ),
+ .X(\la_data_out_enable[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[23] (.A_N(net431),
+ .B(\mprj_logic1[97] ),
+ .X(\la_data_out_enable[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[24] (.A_N(net432),
+ .B(\mprj_logic1[98] ),
+ .X(\la_data_out_enable[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[25] (.A_N(net433),
+ .B(\mprj_logic1[99] ),
+ .X(\la_data_out_enable[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[26] (.A_N(net434),
+ .B(\mprj_logic1[100] ),
+ .X(\la_data_out_enable[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[27] (.A_N(net435),
+ .B(\mprj_logic1[101] ),
+ .X(\la_data_out_enable[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[28] (.A_N(net436),
+ .B(\mprj_logic1[102] ),
+ .X(\la_data_out_enable[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[29] (.A_N(net437),
+ .B(\mprj_logic1[103] ),
+ .X(\la_data_out_enable[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[2] (.A_N(net438),
+ .B(\mprj_logic1[76] ),
+ .X(\la_data_out_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[30] (.A_N(net439),
+ .B(\mprj_logic1[104] ),
+ .X(\la_data_out_enable[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[31] (.A_N(net440),
+ .B(\mprj_logic1[105] ),
+ .X(\la_data_out_enable[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[32] (.A_N(net441),
+ .B(\mprj_logic1[106] ),
+ .X(\la_data_out_enable[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[33] (.A_N(net442),
+ .B(\mprj_logic1[107] ),
+ .X(\la_data_out_enable[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[34] (.A_N(net443),
+ .B(\mprj_logic1[108] ),
+ .X(\la_data_out_enable[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[35] (.A_N(net444),
+ .B(\mprj_logic1[109] ),
+ .X(\la_data_out_enable[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[36] (.A_N(net445),
+ .B(\mprj_logic1[110] ),
+ .X(\la_data_out_enable[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[37] (.A_N(net446),
+ .B(\mprj_logic1[111] ),
+ .X(\la_data_out_enable[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[38] (.A_N(net447),
+ .B(\mprj_logic1[112] ),
+ .X(\la_data_out_enable[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[39] (.A_N(net448),
+ .B(\mprj_logic1[113] ),
+ .X(\la_data_out_enable[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[3] (.A_N(net449),
+ .B(\mprj_logic1[77] ),
+ .X(\la_data_out_enable[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[40] (.A_N(net450),
+ .B(\mprj_logic1[114] ),
+ .X(\la_data_out_enable[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[41] (.A_N(net451),
+ .B(\mprj_logic1[115] ),
+ .X(\la_data_out_enable[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[42] (.A_N(net452),
+ .B(\mprj_logic1[116] ),
+ .X(\la_data_out_enable[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[43] (.A_N(net453),
+ .B(\mprj_logic1[117] ),
+ .X(\la_data_out_enable[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[44] (.A_N(net454),
+ .B(\mprj_logic1[118] ),
+ .X(\la_data_out_enable[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[45] (.A_N(net455),
+ .B(\mprj_logic1[119] ),
+ .X(\la_data_out_enable[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[46] (.A_N(net456),
+ .B(\mprj_logic1[120] ),
+ .X(\la_data_out_enable[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[47] (.A_N(net457),
+ .B(\mprj_logic1[121] ),
+ .X(\la_data_out_enable[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[48] (.A_N(net458),
+ .B(\mprj_logic1[122] ),
+ .X(\la_data_out_enable[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[49] (.A_N(net459),
+ .B(\mprj_logic1[123] ),
+ .X(\la_data_out_enable[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[4] (.A_N(net460),
+ .B(\mprj_logic1[78] ),
+ .X(\la_data_out_enable[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[50] (.A_N(net461),
+ .B(\mprj_logic1[124] ),
+ .X(\la_data_out_enable[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[51] (.A_N(net462),
+ .B(\mprj_logic1[125] ),
+ .X(\la_data_out_enable[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[52] (.A_N(net463),
+ .B(\mprj_logic1[126] ),
+ .X(\la_data_out_enable[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[53] (.A_N(net464),
+ .B(\mprj_logic1[127] ),
+ .X(\la_data_out_enable[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[54] (.A_N(net465),
+ .B(\mprj_logic1[128] ),
+ .X(\la_data_out_enable[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[55] (.A_N(net466),
+ .B(\mprj_logic1[129] ),
+ .X(\la_data_out_enable[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[56] (.A_N(net467),
+ .B(\mprj_logic1[130] ),
+ .X(\la_data_out_enable[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[57] (.A_N(net468),
+ .B(\mprj_logic1[131] ),
+ .X(\la_data_out_enable[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[58] (.A_N(net469),
+ .B(\mprj_logic1[132] ),
+ .X(\la_data_out_enable[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[59] (.A_N(net470),
+ .B(\mprj_logic1[133] ),
+ .X(\la_data_out_enable[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[5] (.A_N(net471),
+ .B(\mprj_logic1[79] ),
+ .X(\la_data_out_enable[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[60] (.A_N(net472),
+ .B(\mprj_logic1[134] ),
+ .X(\la_data_out_enable[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[61] (.A_N(net473),
+ .B(\mprj_logic1[135] ),
+ .X(\la_data_out_enable[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[62] (.A_N(net474),
+ .B(\mprj_logic1[136] ),
+ .X(\la_data_out_enable[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[63] (.A_N(net475),
+ .B(\mprj_logic1[137] ),
+ .X(\la_data_out_enable[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[64] (.A_N(net476),
+ .B(\mprj_logic1[138] ),
+ .X(\la_data_out_enable[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[65] (.A_N(net477),
+ .B(\mprj_logic1[139] ),
+ .X(\la_data_out_enable[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[66] (.A_N(net478),
+ .B(\mprj_logic1[140] ),
+ .X(\la_data_out_enable[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[67] (.A_N(net479),
+ .B(\mprj_logic1[141] ),
+ .X(\la_data_out_enable[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[68] (.A_N(net480),
+ .B(\mprj_logic1[142] ),
+ .X(\la_data_out_enable[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[69] (.A_N(net481),
+ .B(\mprj_logic1[143] ),
+ .X(\la_data_out_enable[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[6] (.A_N(net482),
+ .B(\mprj_logic1[80] ),
+ .X(\la_data_out_enable[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[70] (.A_N(net483),
+ .B(\mprj_logic1[144] ),
+ .X(\la_data_out_enable[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[71] (.A_N(net484),
+ .B(\mprj_logic1[145] ),
+ .X(\la_data_out_enable[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[72] (.A_N(net485),
+ .B(\mprj_logic1[146] ),
+ .X(\la_data_out_enable[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[73] (.A_N(net486),
+ .B(\mprj_logic1[147] ),
+ .X(\la_data_out_enable[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[74] (.A_N(net487),
+ .B(\mprj_logic1[148] ),
+ .X(\la_data_out_enable[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[75] (.A_N(net488),
+ .B(\mprj_logic1[149] ),
+ .X(\la_data_out_enable[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[76] (.A_N(net489),
+ .B(\mprj_logic1[150] ),
+ .X(\la_data_out_enable[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[77] (.A_N(net490),
+ .B(\mprj_logic1[151] ),
+ .X(\la_data_out_enable[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[78] (.A_N(net491),
+ .B(\mprj_logic1[152] ),
+ .X(\la_data_out_enable[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[79] (.A_N(net492),
+ .B(\mprj_logic1[153] ),
+ .X(\la_data_out_enable[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[7] (.A_N(net493),
+ .B(\mprj_logic1[81] ),
+ .X(\la_data_out_enable[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[80] (.A_N(net494),
+ .B(\mprj_logic1[154] ),
+ .X(\la_data_out_enable[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[81] (.A_N(net495),
+ .B(\mprj_logic1[155] ),
+ .X(\la_data_out_enable[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[82] (.A_N(net496),
+ .B(\mprj_logic1[156] ),
+ .X(\la_data_out_enable[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[83] (.A_N(net497),
+ .B(\mprj_logic1[157] ),
+ .X(\la_data_out_enable[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[84] (.A_N(net498),
+ .B(\mprj_logic1[158] ),
+ .X(\la_data_out_enable[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[85] (.A_N(net499),
+ .B(\mprj_logic1[159] ),
+ .X(\la_data_out_enable[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[86] (.A_N(net500),
+ .B(\mprj_logic1[160] ),
+ .X(\la_data_out_enable[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[87] (.A_N(net501),
+ .B(\mprj_logic1[161] ),
+ .X(\la_data_out_enable[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[88] (.A_N(net502),
+ .B(\mprj_logic1[162] ),
+ .X(\la_data_out_enable[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[89] (.A_N(net503),
+ .B(\mprj_logic1[163] ),
+ .X(\la_data_out_enable[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[8] (.A_N(net504),
+ .B(\mprj_logic1[82] ),
+ .X(\la_data_out_enable[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[90] (.A_N(net505),
+ .B(\mprj_logic1[164] ),
+ .X(\la_data_out_enable[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[91] (.A_N(net506),
+ .B(\mprj_logic1[165] ),
+ .X(\la_data_out_enable[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[92] (.A_N(net507),
+ .B(\mprj_logic1[166] ),
+ .X(\la_data_out_enable[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[93] (.A_N(net508),
+ .B(\mprj_logic1[167] ),
+ .X(\la_data_out_enable[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[94] (.A_N(net509),
+ .B(\mprj_logic1[168] ),
+ .X(\la_data_out_enable[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[95] (.A_N(net510),
+ .B(\mprj_logic1[169] ),
+ .X(\la_data_out_enable[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[96] (.A_N(net511),
+ .B(\mprj_logic1[170] ),
+ .X(\la_data_out_enable[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[97] (.A_N(net512),
+ .B(\mprj_logic1[171] ),
+ .X(\la_data_out_enable[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[98] (.A_N(net513),
+ .B(\mprj_logic1[172] ),
+ .X(\la_data_out_enable[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[99] (.A_N(net514),
+ .B(\mprj_logic1[173] ),
+ .X(\la_data_out_enable[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2b_1 \la_buf_enable[9] (.A_N(net515),
+ .B(\mprj_logic1[83] ),
+ .X(\la_data_out_enable[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ mprj2_logic_high mprj2_logic_high_inst (.HI(mprj2_logic1),
+ .vccd2(vccd2),
+ .vssd2(vssd2));
+ sky130_fd_sc_hd__buf_12 mprj2_pwrgood (.A(mprj2_logic1),
+ .X(net1117),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_6 mprj2_vdd_pwrgood (.A(mprj2_vdd_logic1),
+ .X(net1118),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[0] (.A(_009_),
+ .TE(\mprj_logic1[10] ),
+ .Z(net1012),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[10] (.A(_010_),
+ .TE(\mprj_logic1[20] ),
+ .Z(net1013),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[11] (.A(_011_),
+ .TE(\mprj_logic1[21] ),
+ .Z(net1014),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[12] (.A(_012_),
+ .TE(\mprj_logic1[22] ),
+ .Z(net1015),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[13] (.A(_013_),
+ .TE(\mprj_logic1[23] ),
+ .Z(net1016),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[14] (.A(_014_),
+ .TE(\mprj_logic1[24] ),
+ .Z(net1017),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[15] (.A(_015_),
+ .TE(\mprj_logic1[25] ),
+ .Z(net1018),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[16] (.A(_016_),
+ .TE(\mprj_logic1[26] ),
+ .Z(net1019),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[17] (.A(_017_),
+ .TE(\mprj_logic1[27] ),
+ .Z(net1020),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[18] (.A(_018_),
+ .TE(\mprj_logic1[28] ),
+ .Z(net1021),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[19] (.A(_019_),
+ .TE(\mprj_logic1[29] ),
+ .Z(net1022),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[1] (.A(_020_),
+ .TE(\mprj_logic1[11] ),
+ .Z(net1023),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[20] (.A(_021_),
+ .TE(\mprj_logic1[30] ),
+ .Z(net1024),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[21] (.A(_022_),
+ .TE(\mprj_logic1[31] ),
+ .Z(net1025),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[22] (.A(_023_),
+ .TE(\mprj_logic1[32] ),
+ .Z(net1026),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[23] (.A(_024_),
+ .TE(\mprj_logic1[33] ),
+ .Z(net1027),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[24] (.A(_025_),
+ .TE(\mprj_logic1[34] ),
+ .Z(net1028),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[25] (.A(_026_),
+ .TE(\mprj_logic1[35] ),
+ .Z(net1029),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[26] (.A(_027_),
+ .TE(\mprj_logic1[36] ),
+ .Z(net1030),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[27] (.A(_028_),
+ .TE(\mprj_logic1[37] ),
+ .Z(net1031),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[28] (.A(_029_),
+ .TE(\mprj_logic1[38] ),
+ .Z(net1032),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[29] (.A(_030_),
+ .TE(\mprj_logic1[39] ),
+ .Z(net1033),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[2] (.A(_031_),
+ .TE(\mprj_logic1[12] ),
+ .Z(net1034),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[30] (.A(_032_),
+ .TE(\mprj_logic1[40] ),
+ .Z(net1035),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[31] (.A(_033_),
+ .TE(\mprj_logic1[41] ),
+ .Z(net1036),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[3] (.A(_034_),
+ .TE(\mprj_logic1[13] ),
+ .Z(net1037),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[4] (.A(_035_),
+ .TE(\mprj_logic1[14] ),
+ .Z(net1038),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[5] (.A(_036_),
+ .TE(\mprj_logic1[15] ),
+ .Z(net1039),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[6] (.A(_037_),
+ .TE(\mprj_logic1[16] ),
+ .Z(net1040),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[7] (.A(_038_),
+ .TE(\mprj_logic1[17] ),
+ .Z(net1041),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \mprj_adr_buf[8] (.A(_039_),
+ .TE(\mprj_logic1[18] ),
+ .Z(net1042),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_adr_buf[9] (.A(_040_),
+ .TE(\mprj_logic1[19] ),
+ .Z(net1043),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (.A(_001_),
+ .TE(\mprj_logic1[2] ),
+ .Z(net1120),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 mprj_clk_buf (.A(_000_),
+ .TE(\mprj_logic1[1] ),
+ .Z(net1119),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (.A(_002_),
+ .TE(\mprj_logic1[3] ),
+ .Z(net1044),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[0] (.A(_041_),
+ .TE(\mprj_logic1[42] ),
+ .Z(net1077),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[10] (.A(_042_),
+ .TE(\mprj_logic1[52] ),
+ .Z(net1078),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[11] (.A(_043_),
+ .TE(\mprj_logic1[53] ),
+ .Z(net1079),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[12] (.A(_044_),
+ .TE(\mprj_logic1[54] ),
+ .Z(net1080),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[13] (.A(_045_),
+ .TE(\mprj_logic1[55] ),
+ .Z(net1081),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[14] (.A(_046_),
+ .TE(\mprj_logic1[56] ),
+ .Z(net1082),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[15] (.A(_047_),
+ .TE(\mprj_logic1[57] ),
+ .Z(net1083),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[16] (.A(_048_),
+ .TE(\mprj_logic1[58] ),
+ .Z(net1084),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[17] (.A(_049_),
+ .TE(\mprj_logic1[59] ),
+ .Z(net1085),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[18] (.A(_050_),
+ .TE(\mprj_logic1[60] ),
+ .Z(net1086),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[19] (.A(_051_),
+ .TE(\mprj_logic1[61] ),
+ .Z(net1087),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[1] (.A(_052_),
+ .TE(\mprj_logic1[43] ),
+ .Z(net1088),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[20] (.A(_053_),
+ .TE(\mprj_logic1[62] ),
+ .Z(net1089),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[21] (.A(_054_),
+ .TE(\mprj_logic1[63] ),
+ .Z(net1090),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[22] (.A(_055_),
+ .TE(\mprj_logic1[64] ),
+ .Z(net1091),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[23] (.A(_056_),
+ .TE(\mprj_logic1[65] ),
+ .Z(net1092),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[24] (.A(_057_),
+ .TE(\mprj_logic1[66] ),
+ .Z(net1093),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[25] (.A(_058_),
+ .TE(\mprj_logic1[67] ),
+ .Z(net1094),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[26] (.A(_059_),
+ .TE(\mprj_logic1[68] ),
+ .Z(net1095),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[27] (.A(_060_),
+ .TE(\mprj_logic1[69] ),
+ .Z(net1096),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[28] (.A(_061_),
+ .TE(\mprj_logic1[70] ),
+ .Z(net1097),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[29] (.A(_062_),
+ .TE(\mprj_logic1[71] ),
+ .Z(net1098),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[2] (.A(_063_),
+ .TE(\mprj_logic1[44] ),
+ .Z(net1099),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[30] (.A(_064_),
+ .TE(\mprj_logic1[72] ),
+ .Z(net1100),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[31] (.A(_065_),
+ .TE(\mprj_logic1[73] ),
+ .Z(net1101),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[3] (.A(_066_),
+ .TE(\mprj_logic1[45] ),
+ .Z(net1102),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[4] (.A(_067_),
+ .TE(\mprj_logic1[46] ),
+ .Z(net1103),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[5] (.A(_068_),
+ .TE(\mprj_logic1[47] ),
+ .Z(net1104),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[6] (.A(_069_),
+ .TE(\mprj_logic1[48] ),
+ .Z(net1105),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[7] (.A(_070_),
+ .TE(\mprj_logic1[49] ),
+ .Z(net1106),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[8] (.A(_071_),
+ .TE(\mprj_logic1[50] ),
+ .Z(net1107),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_dat_buf[9] (.A(_072_),
+ .TE(\mprj_logic1[51] ),
+ .Z(net1108),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ mprj_logic_high mprj_logic_high_inst (.vccd1(vccd1),
+ .vssd1(vssd1),
+ .HI({\mprj_logic1[462] ,
+ \mprj_logic1[461] ,
+ \mprj_logic1[460] ,
+ \mprj_logic1[459] ,
+ \mprj_logic1[458] ,
+ \mprj_logic1[457] ,
+ \mprj_logic1[456] ,
+ \mprj_logic1[455] ,
+ \mprj_logic1[454] ,
+ \mprj_logic1[453] ,
+ \mprj_logic1[452] ,
+ \mprj_logic1[451] ,
+ \mprj_logic1[450] ,
+ \mprj_logic1[449] ,
+ \mprj_logic1[448] ,
+ \mprj_logic1[447] ,
+ \mprj_logic1[446] ,
+ \mprj_logic1[445] ,
+ \mprj_logic1[444] ,
+ \mprj_logic1[443] ,
+ \mprj_logic1[442] ,
+ \mprj_logic1[441] ,
+ \mprj_logic1[440] ,
+ \mprj_logic1[439] ,
+ \mprj_logic1[438] ,
+ \mprj_logic1[437] ,
+ \mprj_logic1[436] ,
+ \mprj_logic1[435] ,
+ \mprj_logic1[434] ,
+ \mprj_logic1[433] ,
+ \mprj_logic1[432] ,
+ \mprj_logic1[431] ,
+ \mprj_logic1[430] ,
+ \mprj_logic1[429] ,
+ \mprj_logic1[428] ,
+ \mprj_logic1[427] ,
+ \mprj_logic1[426] ,
+ \mprj_logic1[425] ,
+ \mprj_logic1[424] ,
+ \mprj_logic1[423] ,
+ \mprj_logic1[422] ,
+ \mprj_logic1[421] ,
+ \mprj_logic1[420] ,
+ \mprj_logic1[419] ,
+ \mprj_logic1[418] ,
+ \mprj_logic1[417] ,
+ \mprj_logic1[416] ,
+ \mprj_logic1[415] ,
+ \mprj_logic1[414] ,
+ \mprj_logic1[413] ,
+ \mprj_logic1[412] ,
+ \mprj_logic1[411] ,
+ \mprj_logic1[410] ,
+ \mprj_logic1[409] ,
+ \mprj_logic1[408] ,
+ \mprj_logic1[407] ,
+ \mprj_logic1[406] ,
+ \mprj_logic1[405] ,
+ \mprj_logic1[404] ,
+ \mprj_logic1[403] ,
+ \mprj_logic1[402] ,
+ \mprj_logic1[401] ,
+ \mprj_logic1[400] ,
+ \mprj_logic1[399] ,
+ \mprj_logic1[398] ,
+ \mprj_logic1[397] ,
+ \mprj_logic1[396] ,
+ \mprj_logic1[395] ,
+ \mprj_logic1[394] ,
+ \mprj_logic1[393] ,
+ \mprj_logic1[392] ,
+ \mprj_logic1[391] ,
+ \mprj_logic1[390] ,
+ \mprj_logic1[389] ,
+ \mprj_logic1[388] ,
+ \mprj_logic1[387] ,
+ \mprj_logic1[386] ,
+ \mprj_logic1[385] ,
+ \mprj_logic1[384] ,
+ \mprj_logic1[383] ,
+ \mprj_logic1[382] ,
+ \mprj_logic1[381] ,
+ \mprj_logic1[380] ,
+ \mprj_logic1[379] ,
+ \mprj_logic1[378] ,
+ \mprj_logic1[377] ,
+ \mprj_logic1[376] ,
+ \mprj_logic1[375] ,
+ \mprj_logic1[374] ,
+ \mprj_logic1[373] ,
+ \mprj_logic1[372] ,
+ \mprj_logic1[371] ,
+ \mprj_logic1[370] ,
+ \mprj_logic1[369] ,
+ \mprj_logic1[368] ,
+ \mprj_logic1[367] ,
+ \mprj_logic1[366] ,
+ \mprj_logic1[365] ,
+ \mprj_logic1[364] ,
+ \mprj_logic1[363] ,
+ \mprj_logic1[362] ,
+ \mprj_logic1[361] ,
+ \mprj_logic1[360] ,
+ \mprj_logic1[359] ,
+ \mprj_logic1[358] ,
+ \mprj_logic1[357] ,
+ \mprj_logic1[356] ,
+ \mprj_logic1[355] ,
+ \mprj_logic1[354] ,
+ \mprj_logic1[353] ,
+ \mprj_logic1[352] ,
+ \mprj_logic1[351] ,
+ \mprj_logic1[350] ,
+ \mprj_logic1[349] ,
+ \mprj_logic1[348] ,
+ \mprj_logic1[347] ,
+ \mprj_logic1[346] ,
+ \mprj_logic1[345] ,
+ \mprj_logic1[344] ,
+ \mprj_logic1[343] ,
+ \mprj_logic1[342] ,
+ \mprj_logic1[341] ,
+ \mprj_logic1[340] ,
+ \mprj_logic1[339] ,
+ \mprj_logic1[338] ,
+ \mprj_logic1[337] ,
+ \mprj_logic1[336] ,
+ \mprj_logic1[335] ,
+ \mprj_logic1[334] ,
+ \mprj_logic1[333] ,
+ \mprj_logic1[332] ,
+ \mprj_logic1[331] ,
+ \mprj_logic1[330] ,
+ \mprj_logic1[329] ,
+ \mprj_logic1[328] ,
+ \mprj_logic1[327] ,
+ \mprj_logic1[326] ,
+ \mprj_logic1[325] ,
+ \mprj_logic1[324] ,
+ \mprj_logic1[323] ,
+ \mprj_logic1[322] ,
+ \mprj_logic1[321] ,
+ \mprj_logic1[320] ,
+ \mprj_logic1[319] ,
+ \mprj_logic1[318] ,
+ \mprj_logic1[317] ,
+ \mprj_logic1[316] ,
+ \mprj_logic1[315] ,
+ \mprj_logic1[314] ,
+ \mprj_logic1[313] ,
+ \mprj_logic1[312] ,
+ \mprj_logic1[311] ,
+ \mprj_logic1[310] ,
+ \mprj_logic1[309] ,
+ \mprj_logic1[308] ,
+ \mprj_logic1[307] ,
+ \mprj_logic1[306] ,
+ \mprj_logic1[305] ,
+ \mprj_logic1[304] ,
+ \mprj_logic1[303] ,
+ \mprj_logic1[302] ,
+ \mprj_logic1[301] ,
+ \mprj_logic1[300] ,
+ \mprj_logic1[299] ,
+ \mprj_logic1[298] ,
+ \mprj_logic1[297] ,
+ \mprj_logic1[296] ,
+ \mprj_logic1[295] ,
+ \mprj_logic1[294] ,
+ \mprj_logic1[293] ,
+ \mprj_logic1[292] ,
+ \mprj_logic1[291] ,
+ \mprj_logic1[290] ,
+ \mprj_logic1[289] ,
+ \mprj_logic1[288] ,
+ \mprj_logic1[287] ,
+ \mprj_logic1[286] ,
+ \mprj_logic1[285] ,
+ \mprj_logic1[284] ,
+ \mprj_logic1[283] ,
+ \mprj_logic1[282] ,
+ \mprj_logic1[281] ,
+ \mprj_logic1[280] ,
+ \mprj_logic1[279] ,
+ \mprj_logic1[278] ,
+ \mprj_logic1[277] ,
+ \mprj_logic1[276] ,
+ \mprj_logic1[275] ,
+ \mprj_logic1[274] ,
+ \mprj_logic1[273] ,
+ \mprj_logic1[272] ,
+ \mprj_logic1[271] ,
+ \mprj_logic1[270] ,
+ \mprj_logic1[269] ,
+ \mprj_logic1[268] ,
+ \mprj_logic1[267] ,
+ \mprj_logic1[266] ,
+ \mprj_logic1[265] ,
+ \mprj_logic1[264] ,
+ \mprj_logic1[263] ,
+ \mprj_logic1[262] ,
+ \mprj_logic1[261] ,
+ \mprj_logic1[260] ,
+ \mprj_logic1[259] ,
+ \mprj_logic1[258] ,
+ \mprj_logic1[257] ,
+ \mprj_logic1[256] ,
+ \mprj_logic1[255] ,
+ \mprj_logic1[254] ,
+ \mprj_logic1[253] ,
+ \mprj_logic1[252] ,
+ \mprj_logic1[251] ,
+ \mprj_logic1[250] ,
+ \mprj_logic1[249] ,
+ \mprj_logic1[248] ,
+ \mprj_logic1[247] ,
+ \mprj_logic1[246] ,
+ \mprj_logic1[245] ,
+ \mprj_logic1[244] ,
+ \mprj_logic1[243] ,
+ \mprj_logic1[242] ,
+ \mprj_logic1[241] ,
+ \mprj_logic1[240] ,
+ \mprj_logic1[239] ,
+ \mprj_logic1[238] ,
+ \mprj_logic1[237] ,
+ \mprj_logic1[236] ,
+ \mprj_logic1[235] ,
+ \mprj_logic1[234] ,
+ \mprj_logic1[233] ,
+ \mprj_logic1[232] ,
+ \mprj_logic1[231] ,
+ \mprj_logic1[230] ,
+ \mprj_logic1[229] ,
+ \mprj_logic1[228] ,
+ \mprj_logic1[227] ,
+ \mprj_logic1[226] ,
+ \mprj_logic1[225] ,
+ \mprj_logic1[224] ,
+ \mprj_logic1[223] ,
+ \mprj_logic1[222] ,
+ \mprj_logic1[221] ,
+ \mprj_logic1[220] ,
+ \mprj_logic1[219] ,
+ \mprj_logic1[218] ,
+ \mprj_logic1[217] ,
+ \mprj_logic1[216] ,
+ \mprj_logic1[215] ,
+ \mprj_logic1[214] ,
+ \mprj_logic1[213] ,
+ \mprj_logic1[212] ,
+ \mprj_logic1[211] ,
+ \mprj_logic1[210] ,
+ \mprj_logic1[209] ,
+ \mprj_logic1[208] ,
+ \mprj_logic1[207] ,
+ \mprj_logic1[206] ,
+ \mprj_logic1[205] ,
+ \mprj_logic1[204] ,
+ \mprj_logic1[203] ,
+ \mprj_logic1[202] ,
+ \mprj_logic1[201] ,
+ \mprj_logic1[200] ,
+ \mprj_logic1[199] ,
+ \mprj_logic1[198] ,
+ \mprj_logic1[197] ,
+ \mprj_logic1[196] ,
+ \mprj_logic1[195] ,
+ \mprj_logic1[194] ,
+ \mprj_logic1[193] ,
+ \mprj_logic1[192] ,
+ \mprj_logic1[191] ,
+ \mprj_logic1[190] ,
+ \mprj_logic1[189] ,
+ \mprj_logic1[188] ,
+ \mprj_logic1[187] ,
+ \mprj_logic1[186] ,
+ \mprj_logic1[185] ,
+ \mprj_logic1[184] ,
+ \mprj_logic1[183] ,
+ \mprj_logic1[182] ,
+ \mprj_logic1[181] ,
+ \mprj_logic1[180] ,
+ \mprj_logic1[179] ,
+ \mprj_logic1[178] ,
+ \mprj_logic1[177] ,
+ \mprj_logic1[176] ,
+ \mprj_logic1[175] ,
+ \mprj_logic1[174] ,
+ \mprj_logic1[173] ,
+ \mprj_logic1[172] ,
+ \mprj_logic1[171] ,
+ \mprj_logic1[170] ,
+ \mprj_logic1[169] ,
+ \mprj_logic1[168] ,
+ \mprj_logic1[167] ,
+ \mprj_logic1[166] ,
+ \mprj_logic1[165] ,
+ \mprj_logic1[164] ,
+ \mprj_logic1[163] ,
+ \mprj_logic1[162] ,
+ \mprj_logic1[161] ,
+ \mprj_logic1[160] ,
+ \mprj_logic1[159] ,
+ \mprj_logic1[158] ,
+ \mprj_logic1[157] ,
+ \mprj_logic1[156] ,
+ \mprj_logic1[155] ,
+ \mprj_logic1[154] ,
+ \mprj_logic1[153] ,
+ \mprj_logic1[152] ,
+ \mprj_logic1[151] ,
+ \mprj_logic1[150] ,
+ \mprj_logic1[149] ,
+ \mprj_logic1[148] ,
+ \mprj_logic1[147] ,
+ \mprj_logic1[146] ,
+ \mprj_logic1[145] ,
+ \mprj_logic1[144] ,
+ \mprj_logic1[143] ,
+ \mprj_logic1[142] ,
+ \mprj_logic1[141] ,
+ \mprj_logic1[140] ,
+ \mprj_logic1[139] ,
+ \mprj_logic1[138] ,
+ \mprj_logic1[137] ,
+ \mprj_logic1[136] ,
+ \mprj_logic1[135] ,
+ \mprj_logic1[134] ,
+ \mprj_logic1[133] ,
+ \mprj_logic1[132] ,
+ \mprj_logic1[131] ,
+ \mprj_logic1[130] ,
+ \mprj_logic1[129] ,
+ \mprj_logic1[128] ,
+ \mprj_logic1[127] ,
+ \mprj_logic1[126] ,
+ \mprj_logic1[125] ,
+ \mprj_logic1[124] ,
+ \mprj_logic1[123] ,
+ \mprj_logic1[122] ,
+ \mprj_logic1[121] ,
+ \mprj_logic1[120] ,
+ \mprj_logic1[119] ,
+ \mprj_logic1[118] ,
+ \mprj_logic1[117] ,
+ \mprj_logic1[116] ,
+ \mprj_logic1[115] ,
+ \mprj_logic1[114] ,
+ \mprj_logic1[113] ,
+ \mprj_logic1[112] ,
+ \mprj_logic1[111] ,
+ \mprj_logic1[110] ,
+ \mprj_logic1[109] ,
+ \mprj_logic1[108] ,
+ \mprj_logic1[107] ,
+ \mprj_logic1[106] ,
+ \mprj_logic1[105] ,
+ \mprj_logic1[104] ,
+ \mprj_logic1[103] ,
+ \mprj_logic1[102] ,
+ \mprj_logic1[101] ,
+ \mprj_logic1[100] ,
+ \mprj_logic1[99] ,
+ \mprj_logic1[98] ,
+ \mprj_logic1[97] ,
+ \mprj_logic1[96] ,
+ \mprj_logic1[95] ,
+ \mprj_logic1[94] ,
+ \mprj_logic1[93] ,
+ \mprj_logic1[92] ,
+ \mprj_logic1[91] ,
+ \mprj_logic1[90] ,
+ \mprj_logic1[89] ,
+ \mprj_logic1[88] ,
+ \mprj_logic1[87] ,
+ \mprj_logic1[86] ,
+ \mprj_logic1[85] ,
+ \mprj_logic1[84] ,
+ \mprj_logic1[83] ,
+ \mprj_logic1[82] ,
+ \mprj_logic1[81] ,
+ \mprj_logic1[80] ,
+ \mprj_logic1[79] ,
+ \mprj_logic1[78] ,
+ \mprj_logic1[77] ,
+ \mprj_logic1[76] ,
+ \mprj_logic1[75] ,
+ \mprj_logic1[74] ,
+ \mprj_logic1[73] ,
+ \mprj_logic1[72] ,
+ \mprj_logic1[71] ,
+ \mprj_logic1[70] ,
+ \mprj_logic1[69] ,
+ \mprj_logic1[68] ,
+ \mprj_logic1[67] ,
+ \mprj_logic1[66] ,
+ \mprj_logic1[65] ,
+ \mprj_logic1[64] ,
+ \mprj_logic1[63] ,
+ \mprj_logic1[62] ,
+ \mprj_logic1[61] ,
+ \mprj_logic1[60] ,
+ \mprj_logic1[59] ,
+ \mprj_logic1[58] ,
+ \mprj_logic1[57] ,
+ \mprj_logic1[56] ,
+ \mprj_logic1[55] ,
+ \mprj_logic1[54] ,
+ \mprj_logic1[53] ,
+ \mprj_logic1[52] ,
+ \mprj_logic1[51] ,
+ \mprj_logic1[50] ,
+ \mprj_logic1[49] ,
+ \mprj_logic1[48] ,
+ \mprj_logic1[47] ,
+ \mprj_logic1[46] ,
+ \mprj_logic1[45] ,
+ \mprj_logic1[44] ,
+ \mprj_logic1[43] ,
+ \mprj_logic1[42] ,
+ \mprj_logic1[41] ,
+ \mprj_logic1[40] ,
+ \mprj_logic1[39] ,
+ \mprj_logic1[38] ,
+ \mprj_logic1[37] ,
+ \mprj_logic1[36] ,
+ \mprj_logic1[35] ,
+ \mprj_logic1[34] ,
+ \mprj_logic1[33] ,
+ \mprj_logic1[32] ,
+ \mprj_logic1[31] ,
+ \mprj_logic1[30] ,
+ \mprj_logic1[29] ,
+ \mprj_logic1[28] ,
+ \mprj_logic1[27] ,
+ \mprj_logic1[26] ,
+ \mprj_logic1[25] ,
+ \mprj_logic1[24] ,
+ \mprj_logic1[23] ,
+ \mprj_logic1[22] ,
+ \mprj_logic1[21] ,
+ \mprj_logic1[20] ,
+ \mprj_logic1[19] ,
+ \mprj_logic1[18] ,
+ \mprj_logic1[17] ,
+ \mprj_logic1[16] ,
+ \mprj_logic1[15] ,
+ \mprj_logic1[14] ,
+ \mprj_logic1[13] ,
+ \mprj_logic1[12] ,
+ \mprj_logic1[11] ,
+ \mprj_logic1[10] ,
+ \mprj_logic1[9] ,
+ \mprj_logic1[8] ,
+ \mprj_logic1[7] ,
+ \mprj_logic1[6] ,
+ \mprj_logic1[5] ,
+ \mprj_logic1[4] ,
+ \mprj_logic1[3] ,
+ \mprj_logic1[2] ,
+ \mprj_logic1[1] ,
+ \mprj_logic1[0] }));
+ sky130_fd_sc_hd__buf_8 mprj_pwrgood (.A(\mprj_logic1[461] ),
+ .X(net1115),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 mprj_rstn_buf (.A(net3),
+ .TE(\mprj_logic1[0] ),
+ .Z(net1124),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_sel_buf[0] (.A(_005_),
+ .TE(\mprj_logic1[6] ),
+ .Z(net1109),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_sel_buf[1] (.A(_006_),
+ .TE(\mprj_logic1[7] ),
+ .Z(net1110),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_sel_buf[2] (.A(_007_),
+ .TE(\mprj_logic1[8] ),
+ .Z(net1111),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \mprj_sel_buf[3] (.A(_008_),
+ .TE(\mprj_logic1[9] ),
+ .Z(net1112),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 mprj_stb_buf (.A(_003_),
+ .TE(\mprj_logic1[4] ),
+ .Z(net1113),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_6 mprj_vdd_pwrgood (.A(mprj_vdd_logic1),
+ .X(net1116),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 mprj_we_buf (.A(_004_),
+ .TE(\mprj_logic1[5] ),
+ .Z(net1114),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1000 (.A(net1000),
+ .X(la_oenb_core[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1001 (.A(net1001),
+ .X(la_oenb_core[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1002 (.A(net1002),
+ .X(la_oenb_core[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1003 (.A(net1003),
+ .X(la_oenb_core[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1004 (.A(net1004),
+ .X(la_oenb_core[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1005 (.A(net1005),
+ .X(la_oenb_core[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1006 (.A(net1006),
+ .X(la_oenb_core[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1007 (.A(net1007),
+ .X(la_oenb_core[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1008 (.A(net1008),
+ .X(la_oenb_core[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1009 (.A(net1009),
+ .X(la_oenb_core[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1010 (.A(net1010),
+ .X(la_oenb_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1011 (.A(net1011),
+ .X(mprj_ack_i_core),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1012 (.A(net1012),
+ .X(mprj_adr_o_user[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1013 (.A(net1013),
+ .X(mprj_adr_o_user[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1014 (.A(net1014),
+ .X(mprj_adr_o_user[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1015 (.A(net1015),
+ .X(mprj_adr_o_user[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1016 (.A(net1016),
+ .X(mprj_adr_o_user[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1017 (.A(net1017),
+ .X(mprj_adr_o_user[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1018 (.A(net1018),
+ .X(mprj_adr_o_user[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1019 (.A(net1019),
+ .X(mprj_adr_o_user[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1020 (.A(net1020),
+ .X(mprj_adr_o_user[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1021 (.A(net1021),
+ .X(mprj_adr_o_user[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1022 (.A(net1022),
+ .X(mprj_adr_o_user[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1023 (.A(net1023),
+ .X(mprj_adr_o_user[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1024 (.A(net1024),
+ .X(mprj_adr_o_user[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1025 (.A(net1025),
+ .X(mprj_adr_o_user[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1026 (.A(net1026),
+ .X(mprj_adr_o_user[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1027 (.A(net1027),
+ .X(mprj_adr_o_user[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1028 (.A(net1028),
+ .X(mprj_adr_o_user[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1029 (.A(net1029),
+ .X(mprj_adr_o_user[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1030 (.A(net1030),
+ .X(mprj_adr_o_user[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1031 (.A(net1031),
+ .X(mprj_adr_o_user[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1032 (.A(net1032),
+ .X(mprj_adr_o_user[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1033 (.A(net1033),
+ .X(mprj_adr_o_user[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1034 (.A(net1034),
+ .X(mprj_adr_o_user[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1035 (.A(net1035),
+ .X(mprj_adr_o_user[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1036 (.A(net1036),
+ .X(mprj_adr_o_user[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1037 (.A(net1037),
+ .X(mprj_adr_o_user[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1038 (.A(net1038),
+ .X(mprj_adr_o_user[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1039 (.A(net1039),
+ .X(mprj_adr_o_user[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1040 (.A(net1040),
+ .X(mprj_adr_o_user[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1041 (.A(net1041),
+ .X(mprj_adr_o_user[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1042 (.A(net1042),
+ .X(mprj_adr_o_user[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1043 (.A(net1043),
+ .X(mprj_adr_o_user[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1044 (.A(net1044),
+ .X(mprj_cyc_o_user),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1045 (.A(net1045),
+ .X(mprj_dat_i_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1046 (.A(net1046),
+ .X(mprj_dat_i_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1047 (.A(net1047),
+ .X(mprj_dat_i_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1048 (.A(net1048),
+ .X(mprj_dat_i_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1049 (.A(net1049),
+ .X(mprj_dat_i_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1050 (.A(net1050),
+ .X(mprj_dat_i_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1051 (.A(net1051),
+ .X(mprj_dat_i_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1052 (.A(net1052),
+ .X(mprj_dat_i_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1053 (.A(net1053),
+ .X(mprj_dat_i_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1054 (.A(net1054),
+ .X(mprj_dat_i_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1055 (.A(net1055),
+ .X(mprj_dat_i_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1056 (.A(net1056),
+ .X(mprj_dat_i_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1057 (.A(net1057),
+ .X(mprj_dat_i_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1058 (.A(net1058),
+ .X(mprj_dat_i_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1059 (.A(net1059),
+ .X(mprj_dat_i_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1060 (.A(net1060),
+ .X(mprj_dat_i_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1061 (.A(net1061),
+ .X(mprj_dat_i_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1062 (.A(net1062),
+ .X(mprj_dat_i_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1063 (.A(net1063),
+ .X(mprj_dat_i_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1064 (.A(net1064),
+ .X(mprj_dat_i_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1065 (.A(net1065),
+ .X(mprj_dat_i_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1066 (.A(net1066),
+ .X(mprj_dat_i_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1067 (.A(net1067),
+ .X(mprj_dat_i_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1068 (.A(net1068),
+ .X(mprj_dat_i_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1069 (.A(net1069),
+ .X(mprj_dat_i_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1070 (.A(net1070),
+ .X(mprj_dat_i_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1071 (.A(net1071),
+ .X(mprj_dat_i_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1072 (.A(net1072),
+ .X(mprj_dat_i_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1073 (.A(net1073),
+ .X(mprj_dat_i_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1074 (.A(net1074),
+ .X(mprj_dat_i_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1075 (.A(net1075),
+ .X(mprj_dat_i_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1076 (.A(net1076),
+ .X(mprj_dat_i_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1077 (.A(net1077),
+ .X(mprj_dat_o_user[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1078 (.A(net1078),
+ .X(mprj_dat_o_user[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1079 (.A(net1079),
+ .X(mprj_dat_o_user[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1080 (.A(net1080),
+ .X(mprj_dat_o_user[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1081 (.A(net1081),
+ .X(mprj_dat_o_user[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1082 (.A(net1082),
+ .X(mprj_dat_o_user[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1083 (.A(net1083),
+ .X(mprj_dat_o_user[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1084 (.A(net1084),
+ .X(mprj_dat_o_user[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1085 (.A(net1085),
+ .X(mprj_dat_o_user[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1086 (.A(net1086),
+ .X(mprj_dat_o_user[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1087 (.A(net1087),
+ .X(mprj_dat_o_user[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1088 (.A(net1088),
+ .X(mprj_dat_o_user[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1089 (.A(net1089),
+ .X(mprj_dat_o_user[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1090 (.A(net1090),
+ .X(mprj_dat_o_user[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1091 (.A(net1091),
+ .X(mprj_dat_o_user[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1092 (.A(net1092),
+ .X(mprj_dat_o_user[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1093 (.A(net1093),
+ .X(mprj_dat_o_user[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1094 (.A(net1094),
+ .X(mprj_dat_o_user[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1095 (.A(net1095),
+ .X(mprj_dat_o_user[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1096 (.A(net1096),
+ .X(mprj_dat_o_user[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1097 (.A(net1097),
+ .X(mprj_dat_o_user[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1098 (.A(net1098),
+ .X(mprj_dat_o_user[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1099 (.A(net1099),
+ .X(mprj_dat_o_user[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1100 (.A(net1100),
+ .X(mprj_dat_o_user[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1101 (.A(net1101),
+ .X(mprj_dat_o_user[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1102 (.A(net1102),
+ .X(mprj_dat_o_user[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1103 (.A(net1103),
+ .X(mprj_dat_o_user[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1104 (.A(net1104),
+ .X(mprj_dat_o_user[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1105 (.A(net1105),
+ .X(mprj_dat_o_user[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1106 (.A(net1106),
+ .X(mprj_dat_o_user[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1107 (.A(net1107),
+ .X(mprj_dat_o_user[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1108 (.A(net1108),
+ .X(mprj_dat_o_user[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1109 (.A(net1109),
+ .X(mprj_sel_o_user[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1110 (.A(net1110),
+ .X(mprj_sel_o_user[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1111 (.A(net1111),
+ .X(mprj_sel_o_user[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1112 (.A(net1112),
+ .X(mprj_sel_o_user[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1113 (.A(net1113),
+ .X(mprj_stb_o_user),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1114 (.A(net1114),
+ .X(mprj_we_o_user),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1115 (.A(net1115),
+ .X(user1_vcc_powergood),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1116 (.A(net1116),
+ .X(user1_vdd_powergood),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1117 (.A(net1117),
+ .X(user2_vcc_powergood),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1118 (.A(net1118),
+ .X(user2_vdd_powergood),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1119 (.A(net1119),
+ .X(user_clock),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1120 (.A(net1120),
+ .X(user_clock2),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1121 (.A(net1121),
+ .X(user_irq[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1122 (.A(net1122),
+ .X(user_irq[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1123 (.A(net1123),
+ .X(user_irq[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output1124 (.A(net1124),
+ .X(user_reset),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output627 (.A(net627),
+ .X(la_data_in_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output628 (.A(net628),
+ .X(la_data_in_core[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output629 (.A(net629),
+ .X(la_data_in_core[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output630 (.A(net630),
+ .X(la_data_in_core[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output631 (.A(net631),
+ .X(la_data_in_core[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output632 (.A(net632),
+ .X(la_data_in_core[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output633 (.A(net633),
+ .X(la_data_in_core[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output634 (.A(net634),
+ .X(la_data_in_core[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output635 (.A(net635),
+ .X(la_data_in_core[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output636 (.A(net636),
+ .X(la_data_in_core[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output637 (.A(net637),
+ .X(la_data_in_core[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output638 (.A(net638),
+ .X(la_data_in_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output639 (.A(net639),
+ .X(la_data_in_core[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output640 (.A(net640),
+ .X(la_data_in_core[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output641 (.A(net641),
+ .X(la_data_in_core[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output642 (.A(net642),
+ .X(la_data_in_core[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output643 (.A(net643),
+ .X(la_data_in_core[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output644 (.A(net644),
+ .X(la_data_in_core[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output645 (.A(net645),
+ .X(la_data_in_core[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output646 (.A(net646),
+ .X(la_data_in_core[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output647 (.A(net647),
+ .X(la_data_in_core[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output648 (.A(net648),
+ .X(la_data_in_core[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output649 (.A(net649),
+ .X(la_data_in_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output650 (.A(net650),
+ .X(la_data_in_core[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output651 (.A(net651),
+ .X(la_data_in_core[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output652 (.A(net652),
+ .X(la_data_in_core[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output653 (.A(net653),
+ .X(la_data_in_core[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output654 (.A(net654),
+ .X(la_data_in_core[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output655 (.A(net655),
+ .X(la_data_in_core[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output656 (.A(net656),
+ .X(la_data_in_core[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output657 (.A(net657),
+ .X(la_data_in_core[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output658 (.A(net658),
+ .X(la_data_in_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output659 (.A(net659),
+ .X(la_data_in_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output660 (.A(net660),
+ .X(la_data_in_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output661 (.A(net661),
+ .X(la_data_in_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output662 (.A(net662),
+ .X(la_data_in_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output663 (.A(net663),
+ .X(la_data_in_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output664 (.A(net664),
+ .X(la_data_in_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output665 (.A(net665),
+ .X(la_data_in_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output666 (.A(net666),
+ .X(la_data_in_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output667 (.A(net667),
+ .X(la_data_in_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output668 (.A(net668),
+ .X(la_data_in_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output669 (.A(net669),
+ .X(la_data_in_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output670 (.A(net670),
+ .X(la_data_in_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output671 (.A(net671),
+ .X(la_data_in_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output672 (.A(net672),
+ .X(la_data_in_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output673 (.A(net673),
+ .X(la_data_in_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output674 (.A(net674),
+ .X(la_data_in_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output675 (.A(net675),
+ .X(la_data_in_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output676 (.A(net676),
+ .X(la_data_in_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output677 (.A(net677),
+ .X(la_data_in_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output678 (.A(net678),
+ .X(la_data_in_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output679 (.A(net679),
+ .X(la_data_in_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output680 (.A(net680),
+ .X(la_data_in_core[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output681 (.A(net681),
+ .X(la_data_in_core[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output682 (.A(net682),
+ .X(la_data_in_core[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output683 (.A(net683),
+ .X(la_data_in_core[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output684 (.A(net684),
+ .X(la_data_in_core[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output685 (.A(net685),
+ .X(la_data_in_core[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output686 (.A(net686),
+ .X(la_data_in_core[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output687 (.A(net687),
+ .X(la_data_in_core[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output688 (.A(net688),
+ .X(la_data_in_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output689 (.A(net689),
+ .X(la_data_in_core[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output690 (.A(net690),
+ .X(la_data_in_core[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output691 (.A(net691),
+ .X(la_data_in_core[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output692 (.A(net692),
+ .X(la_data_in_core[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output693 (.A(net693),
+ .X(la_data_in_core[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output694 (.A(net694),
+ .X(la_data_in_core[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output695 (.A(net695),
+ .X(la_data_in_core[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output696 (.A(net696),
+ .X(la_data_in_core[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output697 (.A(net697),
+ .X(la_data_in_core[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output698 (.A(net698),
+ .X(la_data_in_core[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output699 (.A(net699),
+ .X(la_data_in_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output700 (.A(net700),
+ .X(la_data_in_core[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output701 (.A(net701),
+ .X(la_data_in_core[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output702 (.A(net702),
+ .X(la_data_in_core[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output703 (.A(net703),
+ .X(la_data_in_core[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output704 (.A(net704),
+ .X(la_data_in_core[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output705 (.A(net705),
+ .X(la_data_in_core[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output706 (.A(net706),
+ .X(la_data_in_core[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output707 (.A(net707),
+ .X(la_data_in_core[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output708 (.A(net708),
+ .X(la_data_in_core[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output709 (.A(net709),
+ .X(la_data_in_core[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output710 (.A(net710),
+ .X(la_data_in_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output711 (.A(net711),
+ .X(la_data_in_core[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output712 (.A(net712),
+ .X(la_data_in_core[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output713 (.A(net713),
+ .X(la_data_in_core[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output714 (.A(net714),
+ .X(la_data_in_core[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output715 (.A(net715),
+ .X(la_data_in_core[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output716 (.A(net716),
+ .X(la_data_in_core[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output717 (.A(net717),
+ .X(la_data_in_core[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output718 (.A(net718),
+ .X(la_data_in_core[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output719 (.A(net719),
+ .X(la_data_in_core[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output720 (.A(net720),
+ .X(la_data_in_core[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output721 (.A(net721),
+ .X(la_data_in_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output722 (.A(net722),
+ .X(la_data_in_core[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output723 (.A(net723),
+ .X(la_data_in_core[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output724 (.A(net724),
+ .X(la_data_in_core[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output725 (.A(net725),
+ .X(la_data_in_core[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output726 (.A(net726),
+ .X(la_data_in_core[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output727 (.A(net727),
+ .X(la_data_in_core[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output728 (.A(net728),
+ .X(la_data_in_core[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output729 (.A(net729),
+ .X(la_data_in_core[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output730 (.A(net730),
+ .X(la_data_in_core[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output731 (.A(net731),
+ .X(la_data_in_core[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output732 (.A(net732),
+ .X(la_data_in_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output733 (.A(net733),
+ .X(la_data_in_core[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output734 (.A(net734),
+ .X(la_data_in_core[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output735 (.A(net735),
+ .X(la_data_in_core[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output736 (.A(net736),
+ .X(la_data_in_core[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output737 (.A(net737),
+ .X(la_data_in_core[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output738 (.A(net738),
+ .X(la_data_in_core[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output739 (.A(net739),
+ .X(la_data_in_core[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output740 (.A(net740),
+ .X(la_data_in_core[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output741 (.A(net741),
+ .X(la_data_in_core[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output742 (.A(net742),
+ .X(la_data_in_core[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output743 (.A(net743),
+ .X(la_data_in_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output744 (.A(net744),
+ .X(la_data_in_core[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output745 (.A(net745),
+ .X(la_data_in_core[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output746 (.A(net746),
+ .X(la_data_in_core[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output747 (.A(net747),
+ .X(la_data_in_core[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output748 (.A(net748),
+ .X(la_data_in_core[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output749 (.A(net749),
+ .X(la_data_in_core[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output750 (.A(net750),
+ .X(la_data_in_core[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output751 (.A(net751),
+ .X(la_data_in_core[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output752 (.A(net752),
+ .X(la_data_in_core[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output753 (.A(net753),
+ .X(la_data_in_core[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output754 (.A(net754),
+ .X(la_data_in_core[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output755 (.A(net755),
+ .X(la_data_in_mprj[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output756 (.A(net756),
+ .X(la_data_in_mprj[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output757 (.A(net757),
+ .X(la_data_in_mprj[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output758 (.A(net758),
+ .X(la_data_in_mprj[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output759 (.A(net759),
+ .X(la_data_in_mprj[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output760 (.A(net760),
+ .X(la_data_in_mprj[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output761 (.A(net761),
+ .X(la_data_in_mprj[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output762 (.A(net762),
+ .X(la_data_in_mprj[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output763 (.A(net763),
+ .X(la_data_in_mprj[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output764 (.A(net764),
+ .X(la_data_in_mprj[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output765 (.A(net765),
+ .X(la_data_in_mprj[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output766 (.A(net766),
+ .X(la_data_in_mprj[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output767 (.A(net767),
+ .X(la_data_in_mprj[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output768 (.A(net768),
+ .X(la_data_in_mprj[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output769 (.A(net769),
+ .X(la_data_in_mprj[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output770 (.A(net770),
+ .X(la_data_in_mprj[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output771 (.A(net771),
+ .X(la_data_in_mprj[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output772 (.A(net772),
+ .X(la_data_in_mprj[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output773 (.A(net773),
+ .X(la_data_in_mprj[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output774 (.A(net774),
+ .X(la_data_in_mprj[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output775 (.A(net775),
+ .X(la_data_in_mprj[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output776 (.A(net776),
+ .X(la_data_in_mprj[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output777 (.A(net777),
+ .X(la_data_in_mprj[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output778 (.A(net778),
+ .X(la_data_in_mprj[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output779 (.A(net779),
+ .X(la_data_in_mprj[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output780 (.A(net780),
+ .X(la_data_in_mprj[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output781 (.A(net781),
+ .X(la_data_in_mprj[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output782 (.A(net782),
+ .X(la_data_in_mprj[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output783 (.A(net783),
+ .X(la_data_in_mprj[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output784 (.A(net784),
+ .X(la_data_in_mprj[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output785 (.A(net785),
+ .X(la_data_in_mprj[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output786 (.A(net786),
+ .X(la_data_in_mprj[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output787 (.A(net787),
+ .X(la_data_in_mprj[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output788 (.A(net788),
+ .X(la_data_in_mprj[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output789 (.A(net789),
+ .X(la_data_in_mprj[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output790 (.A(net790),
+ .X(la_data_in_mprj[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output791 (.A(net791),
+ .X(la_data_in_mprj[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output792 (.A(net792),
+ .X(la_data_in_mprj[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output793 (.A(net793),
+ .X(la_data_in_mprj[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output794 (.A(net794),
+ .X(la_data_in_mprj[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output795 (.A(net795),
+ .X(la_data_in_mprj[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output796 (.A(net796),
+ .X(la_data_in_mprj[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output797 (.A(net797),
+ .X(la_data_in_mprj[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output798 (.A(net798),
+ .X(la_data_in_mprj[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output799 (.A(net799),
+ .X(la_data_in_mprj[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output800 (.A(net800),
+ .X(la_data_in_mprj[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output801 (.A(net801),
+ .X(la_data_in_mprj[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output802 (.A(net802),
+ .X(la_data_in_mprj[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output803 (.A(net803),
+ .X(la_data_in_mprj[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output804 (.A(net804),
+ .X(la_data_in_mprj[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output805 (.A(net805),
+ .X(la_data_in_mprj[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output806 (.A(net806),
+ .X(la_data_in_mprj[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output807 (.A(net807),
+ .X(la_data_in_mprj[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output808 (.A(net808),
+ .X(la_data_in_mprj[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output809 (.A(net809),
+ .X(la_data_in_mprj[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output810 (.A(net810),
+ .X(la_data_in_mprj[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output811 (.A(net811),
+ .X(la_data_in_mprj[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output812 (.A(net812),
+ .X(la_data_in_mprj[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output813 (.A(net813),
+ .X(la_data_in_mprj[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output814 (.A(net814),
+ .X(la_data_in_mprj[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output815 (.A(net815),
+ .X(la_data_in_mprj[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output816 (.A(net816),
+ .X(la_data_in_mprj[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output817 (.A(net817),
+ .X(la_data_in_mprj[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output818 (.A(net818),
+ .X(la_data_in_mprj[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output819 (.A(net819),
+ .X(la_data_in_mprj[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output820 (.A(net820),
+ .X(la_data_in_mprj[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output821 (.A(net821),
+ .X(la_data_in_mprj[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output822 (.A(net822),
+ .X(la_data_in_mprj[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output823 (.A(net823),
+ .X(la_data_in_mprj[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output824 (.A(net824),
+ .X(la_data_in_mprj[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output825 (.A(net825),
+ .X(la_data_in_mprj[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output826 (.A(net826),
+ .X(la_data_in_mprj[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output827 (.A(net827),
+ .X(la_data_in_mprj[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output828 (.A(net828),
+ .X(la_data_in_mprj[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output829 (.A(net829),
+ .X(la_data_in_mprj[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output830 (.A(net830),
+ .X(la_data_in_mprj[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output831 (.A(net831),
+ .X(la_data_in_mprj[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output832 (.A(net832),
+ .X(la_data_in_mprj[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output833 (.A(net833),
+ .X(la_data_in_mprj[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output834 (.A(net834),
+ .X(la_data_in_mprj[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output835 (.A(net835),
+ .X(la_data_in_mprj[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output836 (.A(net836),
+ .X(la_data_in_mprj[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output837 (.A(net837),
+ .X(la_data_in_mprj[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output838 (.A(net838),
+ .X(la_data_in_mprj[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output839 (.A(net839),
+ .X(la_data_in_mprj[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output840 (.A(net840),
+ .X(la_data_in_mprj[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output841 (.A(net841),
+ .X(la_data_in_mprj[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output842 (.A(net842),
+ .X(la_data_in_mprj[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output843 (.A(net843),
+ .X(la_data_in_mprj[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output844 (.A(net844),
+ .X(la_data_in_mprj[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output845 (.A(net845),
+ .X(la_data_in_mprj[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output846 (.A(net846),
+ .X(la_data_in_mprj[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output847 (.A(net847),
+ .X(la_data_in_mprj[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output848 (.A(net848),
+ .X(la_data_in_mprj[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output849 (.A(net849),
+ .X(la_data_in_mprj[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output850 (.A(net850),
+ .X(la_data_in_mprj[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output851 (.A(net851),
+ .X(la_data_in_mprj[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output852 (.A(net852),
+ .X(la_data_in_mprj[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output853 (.A(net853),
+ .X(la_data_in_mprj[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output854 (.A(net854),
+ .X(la_data_in_mprj[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output855 (.A(net855),
+ .X(la_data_in_mprj[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output856 (.A(net856),
+ .X(la_data_in_mprj[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output857 (.A(net857),
+ .X(la_data_in_mprj[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output858 (.A(net858),
+ .X(la_data_in_mprj[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output859 (.A(net859),
+ .X(la_data_in_mprj[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output860 (.A(net860),
+ .X(la_data_in_mprj[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output861 (.A(net861),
+ .X(la_data_in_mprj[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output862 (.A(net862),
+ .X(la_data_in_mprj[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output863 (.A(net863),
+ .X(la_data_in_mprj[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output864 (.A(net864),
+ .X(la_data_in_mprj[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output865 (.A(net865),
+ .X(la_data_in_mprj[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output866 (.A(net866),
+ .X(la_data_in_mprj[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output867 (.A(net867),
+ .X(la_data_in_mprj[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output868 (.A(net868),
+ .X(la_data_in_mprj[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output869 (.A(net869),
+ .X(la_data_in_mprj[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output870 (.A(net870),
+ .X(la_data_in_mprj[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output871 (.A(net871),
+ .X(la_data_in_mprj[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output872 (.A(net872),
+ .X(la_data_in_mprj[90]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output873 (.A(net873),
+ .X(la_data_in_mprj[91]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output874 (.A(net874),
+ .X(la_data_in_mprj[92]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output875 (.A(net875),
+ .X(la_data_in_mprj[93]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output876 (.A(net876),
+ .X(la_data_in_mprj[94]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output877 (.A(net877),
+ .X(la_data_in_mprj[95]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output878 (.A(net878),
+ .X(la_data_in_mprj[96]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output879 (.A(net879),
+ .X(la_data_in_mprj[97]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output880 (.A(net880),
+ .X(la_data_in_mprj[98]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output881 (.A(net881),
+ .X(la_data_in_mprj[99]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output882 (.A(net882),
+ .X(la_data_in_mprj[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output883 (.A(net883),
+ .X(la_oenb_core[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output884 (.A(net884),
+ .X(la_oenb_core[100]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output885 (.A(net885),
+ .X(la_oenb_core[101]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output886 (.A(net886),
+ .X(la_oenb_core[102]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output887 (.A(net887),
+ .X(la_oenb_core[103]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output888 (.A(net888),
+ .X(la_oenb_core[104]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output889 (.A(net889),
+ .X(la_oenb_core[105]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output890 (.A(net890),
+ .X(la_oenb_core[106]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output891 (.A(net891),
+ .X(la_oenb_core[107]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output892 (.A(net892),
+ .X(la_oenb_core[108]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output893 (.A(net893),
+ .X(la_oenb_core[109]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output894 (.A(net894),
+ .X(la_oenb_core[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output895 (.A(net895),
+ .X(la_oenb_core[110]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output896 (.A(net896),
+ .X(la_oenb_core[111]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output897 (.A(net897),
+ .X(la_oenb_core[112]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output898 (.A(net898),
+ .X(la_oenb_core[113]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output899 (.A(net899),
+ .X(la_oenb_core[114]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output900 (.A(net900),
+ .X(la_oenb_core[115]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output901 (.A(net901),
+ .X(la_oenb_core[116]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output902 (.A(net902),
+ .X(la_oenb_core[117]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output903 (.A(net903),
+ .X(la_oenb_core[118]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output904 (.A(net904),
+ .X(la_oenb_core[119]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output905 (.A(net905),
+ .X(la_oenb_core[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output906 (.A(net906),
+ .X(la_oenb_core[120]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output907 (.A(net907),
+ .X(la_oenb_core[121]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output908 (.A(net908),
+ .X(la_oenb_core[122]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output909 (.A(net909),
+ .X(la_oenb_core[123]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output910 (.A(net910),
+ .X(la_oenb_core[124]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output911 (.A(net911),
+ .X(la_oenb_core[125]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output912 (.A(net912),
+ .X(la_oenb_core[126]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output913 (.A(net913),
+ .X(la_oenb_core[127]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output914 (.A(net914),
+ .X(la_oenb_core[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output915 (.A(net915),
+ .X(la_oenb_core[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output916 (.A(net916),
+ .X(la_oenb_core[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output917 (.A(net917),
+ .X(la_oenb_core[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output918 (.A(net918),
+ .X(la_oenb_core[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output919 (.A(net919),
+ .X(la_oenb_core[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output920 (.A(net920),
+ .X(la_oenb_core[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output921 (.A(net921),
+ .X(la_oenb_core[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output922 (.A(net922),
+ .X(la_oenb_core[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output923 (.A(net923),
+ .X(la_oenb_core[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output924 (.A(net924),
+ .X(la_oenb_core[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output925 (.A(net925),
+ .X(la_oenb_core[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output926 (.A(net926),
+ .X(la_oenb_core[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output927 (.A(net927),
+ .X(la_oenb_core[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output928 (.A(net928),
+ .X(la_oenb_core[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output929 (.A(net929),
+ .X(la_oenb_core[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output930 (.A(net930),
+ .X(la_oenb_core[27]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output931 (.A(net931),
+ .X(la_oenb_core[28]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output932 (.A(net932),
+ .X(la_oenb_core[29]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output933 (.A(net933),
+ .X(la_oenb_core[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output934 (.A(net934),
+ .X(la_oenb_core[30]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output935 (.A(net935),
+ .X(la_oenb_core[31]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output936 (.A(net936),
+ .X(la_oenb_core[32]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output937 (.A(net937),
+ .X(la_oenb_core[33]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output938 (.A(net938),
+ .X(la_oenb_core[34]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output939 (.A(net939),
+ .X(la_oenb_core[35]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output940 (.A(net940),
+ .X(la_oenb_core[36]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output941 (.A(net941),
+ .X(la_oenb_core[37]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output942 (.A(net942),
+ .X(la_oenb_core[38]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output943 (.A(net943),
+ .X(la_oenb_core[39]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output944 (.A(net944),
+ .X(la_oenb_core[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output945 (.A(net945),
+ .X(la_oenb_core[40]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output946 (.A(net946),
+ .X(la_oenb_core[41]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output947 (.A(net947),
+ .X(la_oenb_core[42]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output948 (.A(net948),
+ .X(la_oenb_core[43]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output949 (.A(net949),
+ .X(la_oenb_core[44]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output950 (.A(net950),
+ .X(la_oenb_core[45]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output951 (.A(net951),
+ .X(la_oenb_core[46]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output952 (.A(net952),
+ .X(la_oenb_core[47]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output953 (.A(net953),
+ .X(la_oenb_core[48]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output954 (.A(net954),
+ .X(la_oenb_core[49]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output955 (.A(net955),
+ .X(la_oenb_core[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output956 (.A(net956),
+ .X(la_oenb_core[50]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output957 (.A(net957),
+ .X(la_oenb_core[51]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output958 (.A(net958),
+ .X(la_oenb_core[52]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output959 (.A(net959),
+ .X(la_oenb_core[53]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output960 (.A(net960),
+ .X(la_oenb_core[54]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output961 (.A(net961),
+ .X(la_oenb_core[55]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output962 (.A(net962),
+ .X(la_oenb_core[56]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output963 (.A(net963),
+ .X(la_oenb_core[57]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output964 (.A(net964),
+ .X(la_oenb_core[58]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output965 (.A(net965),
+ .X(la_oenb_core[59]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output966 (.A(net966),
+ .X(la_oenb_core[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output967 (.A(net967),
+ .X(la_oenb_core[60]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output968 (.A(net968),
+ .X(la_oenb_core[61]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output969 (.A(net969),
+ .X(la_oenb_core[62]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output970 (.A(net970),
+ .X(la_oenb_core[63]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output971 (.A(net971),
+ .X(la_oenb_core[64]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output972 (.A(net972),
+ .X(la_oenb_core[65]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output973 (.A(net973),
+ .X(la_oenb_core[66]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output974 (.A(net974),
+ .X(la_oenb_core[67]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output975 (.A(net975),
+ .X(la_oenb_core[68]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output976 (.A(net976),
+ .X(la_oenb_core[69]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output977 (.A(net977),
+ .X(la_oenb_core[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output978 (.A(net978),
+ .X(la_oenb_core[70]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output979 (.A(net979),
+ .X(la_oenb_core[71]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output980 (.A(net980),
+ .X(la_oenb_core[72]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output981 (.A(net981),
+ .X(la_oenb_core[73]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output982 (.A(net982),
+ .X(la_oenb_core[74]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output983 (.A(net983),
+ .X(la_oenb_core[75]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output984 (.A(net984),
+ .X(la_oenb_core[76]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output985 (.A(net985),
+ .X(la_oenb_core[77]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output986 (.A(net986),
+ .X(la_oenb_core[78]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output987 (.A(net987),
+ .X(la_oenb_core[79]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output988 (.A(net988),
+ .X(la_oenb_core[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output989 (.A(net989),
+ .X(la_oenb_core[80]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output990 (.A(net990),
+ .X(la_oenb_core[81]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output991 (.A(net991),
+ .X(la_oenb_core[82]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output992 (.A(net992),
+ .X(la_oenb_core[83]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output993 (.A(net993),
+ .X(la_oenb_core[84]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output994 (.A(net994),
+ .X(la_oenb_core[85]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output995 (.A(net995),
+ .X(la_oenb_core[86]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output996 (.A(net996),
+ .X(la_oenb_core[87]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output997 (.A(net997),
+ .X(la_oenb_core[88]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output998 (.A(net998),
+ .X(la_oenb_core[89]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__buf_2 output999 (.A(net999),
+ .X(la_oenb_core[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ mgmt_protect_hv powergood_check (.mprj2_vdd_logic1(mprj2_vdd_logic1),
+ .mprj_vdd_logic1(mprj_vdd_logic1),
+ .vccd(vccd),
+ .vssd(vssd),
+ .vdda1(vdda1),
+ .vssa1(vssa1),
+ .vdda2(vdda2),
+ .vssa2(vssa2));
+ sky130_fd_sc_hd__buf_12 repeater1125 (.A(wb_in_enable),
+ .X(net1125),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_irq_buffers[0] (.A(\user_irq_bar[0] ),
+ .Y(net1121),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_irq_buffers[1] (.A(\user_irq_bar[1] ),
+ .Y(net1122),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_irq_buffers[2] (.A(\user_irq_bar[2] ),
+ .Y(net1123),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_irq_ena_buf[0] (.A(net624),
+ .B(\mprj_logic1[458] ),
+ .X(\user_irq_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_irq_ena_buf[1] (.A(net625),
+ .B(\mprj_logic1[459] ),
+ .X(\user_irq_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_irq_ena_buf[2] (.A(net626),
+ .B(\mprj_logic1[460] ),
+ .X(\user_irq_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_irq_gates[0] (.A(net621),
+ .B(\user_irq_enable[0] ),
+ .Y(\user_irq_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_irq_gates[1] (.A(net622),
+ .B(\user_irq_enable[1] ),
+ .Y(\user_irq_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_irq_gates[2] (.A(net623),
+ .B(\user_irq_enable[2] ),
+ .Y(\user_irq_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[0] (.A(\la_data_in_mprj_bar[0] ),
+ .Y(net755),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[100] (.A(\la_data_in_mprj_bar[100] ),
+ .Y(net756),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[101] (.A(\la_data_in_mprj_bar[101] ),
+ .Y(net757),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[102] (.A(\la_data_in_mprj_bar[102] ),
+ .Y(net758),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[103] (.A(\la_data_in_mprj_bar[103] ),
+ .Y(net759),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[104] (.A(\la_data_in_mprj_bar[104] ),
+ .Y(net760),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[105] (.A(\la_data_in_mprj_bar[105] ),
+ .Y(net761),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[106] (.A(\la_data_in_mprj_bar[106] ),
+ .Y(net762),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[107] (.A(\la_data_in_mprj_bar[107] ),
+ .Y(net763),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[108] (.A(\la_data_in_mprj_bar[108] ),
+ .Y(net764),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[109] (.A(\la_data_in_mprj_bar[109] ),
+ .Y(net765),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_to_mprj_in_buffers[10] (.A(\la_data_in_mprj_bar[10] ),
+ .Y(net766),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[110] (.A(\la_data_in_mprj_bar[110] ),
+ .Y(net767),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[111] (.A(\la_data_in_mprj_bar[111] ),
+ .Y(net768),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[112] (.A(\la_data_in_mprj_bar[112] ),
+ .Y(net769),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[113] (.A(\la_data_in_mprj_bar[113] ),
+ .Y(net770),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[114] (.A(\la_data_in_mprj_bar[114] ),
+ .Y(net771),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[115] (.A(\la_data_in_mprj_bar[115] ),
+ .Y(net772),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[116] (.A(\la_data_in_mprj_bar[116] ),
+ .Y(net773),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[117] (.A(\la_data_in_mprj_bar[117] ),
+ .Y(net774),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[118] (.A(\la_data_in_mprj_bar[118] ),
+ .Y(net775),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[119] (.A(\la_data_in_mprj_bar[119] ),
+ .Y(net776),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_to_mprj_in_buffers[11] (.A(\la_data_in_mprj_bar[11] ),
+ .Y(net777),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_to_mprj_in_buffers[120] (.A(\la_data_in_mprj_bar[120] ),
+ .Y(net778),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[121] (.A(\la_data_in_mprj_bar[121] ),
+ .Y(net779),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[122] (.A(\la_data_in_mprj_bar[122] ),
+ .Y(net780),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[123] (.A(\la_data_in_mprj_bar[123] ),
+ .Y(net781),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[124] (.A(\la_data_in_mprj_bar[124] ),
+ .Y(net782),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[125] (.A(\la_data_in_mprj_bar[125] ),
+ .Y(net783),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[126] (.A(\la_data_in_mprj_bar[126] ),
+ .Y(net784),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[127] (.A(\la_data_in_mprj_bar[127] ),
+ .Y(net785),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_to_mprj_in_buffers[12] (.A(\la_data_in_mprj_bar[12] ),
+ .Y(net786),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[13] (.A(\la_data_in_mprj_bar[13] ),
+ .Y(net787),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[14] (.A(\la_data_in_mprj_bar[14] ),
+ .Y(net788),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[15] (.A(\la_data_in_mprj_bar[15] ),
+ .Y(net789),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[16] (.A(\la_data_in_mprj_bar[16] ),
+ .Y(net790),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[17] (.A(\la_data_in_mprj_bar[17] ),
+ .Y(net791),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[18] (.A(\la_data_in_mprj_bar[18] ),
+ .Y(net792),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[19] (.A(\la_data_in_mprj_bar[19] ),
+ .Y(net793),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[1] (.A(\la_data_in_mprj_bar[1] ),
+ .Y(net794),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[20] (.A(\la_data_in_mprj_bar[20] ),
+ .Y(net795),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[21] (.A(\la_data_in_mprj_bar[21] ),
+ .Y(net796),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[22] (.A(\la_data_in_mprj_bar[22] ),
+ .Y(net797),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[23] (.A(\la_data_in_mprj_bar[23] ),
+ .Y(net798),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[24] (.A(\la_data_in_mprj_bar[24] ),
+ .Y(net799),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[25] (.A(\la_data_in_mprj_bar[25] ),
+ .Y(net800),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[26] (.A(\la_data_in_mprj_bar[26] ),
+ .Y(net801),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[27] (.A(\la_data_in_mprj_bar[27] ),
+ .Y(net802),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[28] (.A(\la_data_in_mprj_bar[28] ),
+ .Y(net803),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[29] (.A(\la_data_in_mprj_bar[29] ),
+ .Y(net804),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[2] (.A(\la_data_in_mprj_bar[2] ),
+ .Y(net805),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[30] (.A(\la_data_in_mprj_bar[30] ),
+ .Y(net806),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[31] (.A(\la_data_in_mprj_bar[31] ),
+ .Y(net807),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[32] (.A(\la_data_in_mprj_bar[32] ),
+ .Y(net808),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[33] (.A(\la_data_in_mprj_bar[33] ),
+ .Y(net809),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[34] (.A(\la_data_in_mprj_bar[34] ),
+ .Y(net810),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[35] (.A(\la_data_in_mprj_bar[35] ),
+ .Y(net811),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[36] (.A(\la_data_in_mprj_bar[36] ),
+ .Y(net812),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[37] (.A(\la_data_in_mprj_bar[37] ),
+ .Y(net813),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[38] (.A(\la_data_in_mprj_bar[38] ),
+ .Y(net814),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[39] (.A(\la_data_in_mprj_bar[39] ),
+ .Y(net815),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[3] (.A(\la_data_in_mprj_bar[3] ),
+ .Y(net816),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[40] (.A(\la_data_in_mprj_bar[40] ),
+ .Y(net817),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[41] (.A(\la_data_in_mprj_bar[41] ),
+ .Y(net818),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[42] (.A(\la_data_in_mprj_bar[42] ),
+ .Y(net819),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[43] (.A(\la_data_in_mprj_bar[43] ),
+ .Y(net820),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[44] (.A(\la_data_in_mprj_bar[44] ),
+ .Y(net821),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[45] (.A(\la_data_in_mprj_bar[45] ),
+ .Y(net822),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[46] (.A(\la_data_in_mprj_bar[46] ),
+ .Y(net823),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[47] (.A(\la_data_in_mprj_bar[47] ),
+ .Y(net824),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[48] (.A(\la_data_in_mprj_bar[48] ),
+ .Y(net825),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[49] (.A(\la_data_in_mprj_bar[49] ),
+ .Y(net826),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[4] (.A(\la_data_in_mprj_bar[4] ),
+ .Y(net827),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[50] (.A(\la_data_in_mprj_bar[50] ),
+ .Y(net828),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[51] (.A(\la_data_in_mprj_bar[51] ),
+ .Y(net829),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[52] (.A(\la_data_in_mprj_bar[52] ),
+ .Y(net830),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[53] (.A(\la_data_in_mprj_bar[53] ),
+ .Y(net831),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[54] (.A(\la_data_in_mprj_bar[54] ),
+ .Y(net832),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[55] (.A(\la_data_in_mprj_bar[55] ),
+ .Y(net833),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[56] (.A(\la_data_in_mprj_bar[56] ),
+ .Y(net834),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[57] (.A(\la_data_in_mprj_bar[57] ),
+ .Y(net835),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[58] (.A(\la_data_in_mprj_bar[58] ),
+ .Y(net836),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[59] (.A(\la_data_in_mprj_bar[59] ),
+ .Y(net837),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[5] (.A(\la_data_in_mprj_bar[5] ),
+ .Y(net838),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[60] (.A(\la_data_in_mprj_bar[60] ),
+ .Y(net839),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[61] (.A(\la_data_in_mprj_bar[61] ),
+ .Y(net840),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[62] (.A(\la_data_in_mprj_bar[62] ),
+ .Y(net841),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[63] (.A(\la_data_in_mprj_bar[63] ),
+ .Y(net842),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[64] (.A(\la_data_in_mprj_bar[64] ),
+ .Y(net843),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[65] (.A(\la_data_in_mprj_bar[65] ),
+ .Y(net844),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[66] (.A(\la_data_in_mprj_bar[66] ),
+ .Y(net845),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 \user_to_mprj_in_buffers[67] (.A(\la_data_in_mprj_bar[67] ),
+ .Y(net846),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[68] (.A(\la_data_in_mprj_bar[68] ),
+ .Y(net847),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[69] (.A(\la_data_in_mprj_bar[69] ),
+ .Y(net848),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[6] (.A(\la_data_in_mprj_bar[6] ),
+ .Y(net849),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[70] (.A(\la_data_in_mprj_bar[70] ),
+ .Y(net850),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[71] (.A(\la_data_in_mprj_bar[71] ),
+ .Y(net851),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[72] (.A(\la_data_in_mprj_bar[72] ),
+ .Y(net852),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[73] (.A(\la_data_in_mprj_bar[73] ),
+ .Y(net853),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 \user_to_mprj_in_buffers[74] (.A(\la_data_in_mprj_bar[74] ),
+ .Y(net854),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 \user_to_mprj_in_buffers[75] (.A(\la_data_in_mprj_bar[75] ),
+ .Y(net855),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[76] (.A(\la_data_in_mprj_bar[76] ),
+ .Y(net856),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[77] (.A(\la_data_in_mprj_bar[77] ),
+ .Y(net857),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[78] (.A(\la_data_in_mprj_bar[78] ),
+ .Y(net858),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[79] (.A(\la_data_in_mprj_bar[79] ),
+ .Y(net859),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[7] (.A(\la_data_in_mprj_bar[7] ),
+ .Y(net860),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[80] (.A(\la_data_in_mprj_bar[80] ),
+ .Y(net861),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[81] (.A(\la_data_in_mprj_bar[81] ),
+ .Y(net862),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[82] (.A(\la_data_in_mprj_bar[82] ),
+ .Y(net863),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 \user_to_mprj_in_buffers[83] (.A(\la_data_in_mprj_bar[83] ),
+ .Y(net864),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_2 \user_to_mprj_in_buffers[84] (.A(\la_data_in_mprj_bar[84] ),
+ .Y(net865),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[85] (.A(\la_data_in_mprj_bar[85] ),
+ .Y(net866),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[86] (.A(\la_data_in_mprj_bar[86] ),
+ .Y(net867),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[87] (.A(\la_data_in_mprj_bar[87] ),
+ .Y(net868),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[88] (.A(\la_data_in_mprj_bar[88] ),
+ .Y(net869),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[89] (.A(\la_data_in_mprj_bar[89] ),
+ .Y(net870),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[8] (.A(\la_data_in_mprj_bar[8] ),
+ .Y(net871),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[90] (.A(\la_data_in_mprj_bar[90] ),
+ .Y(net872),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[91] (.A(\la_data_in_mprj_bar[91] ),
+ .Y(net873),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[92] (.A(\la_data_in_mprj_bar[92] ),
+ .Y(net874),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[93] (.A(\la_data_in_mprj_bar[93] ),
+ .Y(net875),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[94] (.A(\la_data_in_mprj_bar[94] ),
+ .Y(net876),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \user_to_mprj_in_buffers[95] (.A(\la_data_in_mprj_bar[95] ),
+ .Y(net877),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[96] (.A(\la_data_in_mprj_bar[96] ),
+ .Y(net878),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[97] (.A(\la_data_in_mprj_bar[97] ),
+ .Y(net879),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[98] (.A(\la_data_in_mprj_bar[98] ),
+ .Y(net880),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_4 \user_to_mprj_in_buffers[99] (.A(\la_data_in_mprj_bar[99] ),
+ .Y(net881),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_to_mprj_in_buffers[9] (.A(\la_data_in_mprj_bar[9] ),
+ .Y(net882),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[0] (.A(net260),
+ .B(\mprj_logic1[330] ),
+ .X(\la_data_in_enable[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[100] (.A(net261),
+ .B(\mprj_logic1[430] ),
+ .X(\la_data_in_enable[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[101] (.A(net262),
+ .B(\mprj_logic1[431] ),
+ .X(\la_data_in_enable[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[102] (.A(net263),
+ .B(\mprj_logic1[432] ),
+ .X(\la_data_in_enable[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[103] (.A(net264),
+ .B(\mprj_logic1[433] ),
+ .X(\la_data_in_enable[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[104] (.A(net265),
+ .B(\mprj_logic1[434] ),
+ .X(\la_data_in_enable[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[105] (.A(net266),
+ .B(\mprj_logic1[435] ),
+ .X(\la_data_in_enable[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[106] (.A(net267),
+ .B(\mprj_logic1[436] ),
+ .X(\la_data_in_enable[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[107] (.A(net268),
+ .B(\mprj_logic1[437] ),
+ .X(\la_data_in_enable[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[108] (.A(net269),
+ .B(\mprj_logic1[438] ),
+ .X(\la_data_in_enable[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[109] (.A(net270),
+ .B(\mprj_logic1[439] ),
+ .X(\la_data_in_enable[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[10] (.A(net271),
+ .B(\mprj_logic1[340] ),
+ .X(\la_data_in_enable[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[110] (.A(net272),
+ .B(\mprj_logic1[440] ),
+ .X(\la_data_in_enable[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[111] (.A(net273),
+ .B(\mprj_logic1[441] ),
+ .X(\la_data_in_enable[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[112] (.A(net274),
+ .B(\mprj_logic1[442] ),
+ .X(\la_data_in_enable[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[113] (.A(net275),
+ .B(\mprj_logic1[443] ),
+ .X(\la_data_in_enable[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[114] (.A(net276),
+ .B(\mprj_logic1[444] ),
+ .X(\la_data_in_enable[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[115] (.A(net277),
+ .B(\mprj_logic1[445] ),
+ .X(\la_data_in_enable[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[116] (.A(net278),
+ .B(\mprj_logic1[446] ),
+ .X(\la_data_in_enable[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[117] (.A(net279),
+ .B(\mprj_logic1[447] ),
+ .X(\la_data_in_enable[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[118] (.A(net280),
+ .B(\mprj_logic1[448] ),
+ .X(\la_data_in_enable[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[119] (.A(net281),
+ .B(\mprj_logic1[449] ),
+ .X(\la_data_in_enable[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[11] (.A(net282),
+ .B(\mprj_logic1[341] ),
+ .X(\la_data_in_enable[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[120] (.A(net283),
+ .B(\mprj_logic1[450] ),
+ .X(\la_data_in_enable[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[121] (.A(net284),
+ .B(\mprj_logic1[451] ),
+ .X(\la_data_in_enable[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[122] (.A(net285),
+ .B(\mprj_logic1[452] ),
+ .X(\la_data_in_enable[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[123] (.A(net286),
+ .B(\mprj_logic1[453] ),
+ .X(\la_data_in_enable[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[124] (.A(net287),
+ .B(\mprj_logic1[454] ),
+ .X(\la_data_in_enable[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[125] (.A(net288),
+ .B(\mprj_logic1[455] ),
+ .X(\la_data_in_enable[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[126] (.A(net289),
+ .B(\mprj_logic1[456] ),
+ .X(\la_data_in_enable[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[127] (.A(net290),
+ .B(\mprj_logic1[457] ),
+ .X(\la_data_in_enable[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[12] (.A(net291),
+ .B(\mprj_logic1[342] ),
+ .X(\la_data_in_enable[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[13] (.A(net292),
+ .B(\mprj_logic1[343] ),
+ .X(\la_data_in_enable[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[14] (.A(net293),
+ .B(\mprj_logic1[344] ),
+ .X(\la_data_in_enable[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[15] (.A(net294),
+ .B(\mprj_logic1[345] ),
+ .X(\la_data_in_enable[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[16] (.A(net295),
+ .B(\mprj_logic1[346] ),
+ .X(\la_data_in_enable[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[17] (.A(net296),
+ .B(\mprj_logic1[347] ),
+ .X(\la_data_in_enable[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[18] (.A(net297),
+ .B(\mprj_logic1[348] ),
+ .X(\la_data_in_enable[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[19] (.A(net298),
+ .B(\mprj_logic1[349] ),
+ .X(\la_data_in_enable[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[1] (.A(net299),
+ .B(\mprj_logic1[331] ),
+ .X(\la_data_in_enable[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[20] (.A(net300),
+ .B(\mprj_logic1[350] ),
+ .X(\la_data_in_enable[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[21] (.A(net301),
+ .B(\mprj_logic1[351] ),
+ .X(\la_data_in_enable[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[22] (.A(net302),
+ .B(\mprj_logic1[352] ),
+ .X(\la_data_in_enable[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[23] (.A(net303),
+ .B(\mprj_logic1[353] ),
+ .X(\la_data_in_enable[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[24] (.A(net304),
+ .B(\mprj_logic1[354] ),
+ .X(\la_data_in_enable[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[25] (.A(net305),
+ .B(\mprj_logic1[355] ),
+ .X(\la_data_in_enable[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[26] (.A(net306),
+ .B(\mprj_logic1[356] ),
+ .X(\la_data_in_enable[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[27] (.A(net307),
+ .B(\mprj_logic1[357] ),
+ .X(\la_data_in_enable[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[28] (.A(net308),
+ .B(\mprj_logic1[358] ),
+ .X(\la_data_in_enable[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[29] (.A(net309),
+ .B(\mprj_logic1[359] ),
+ .X(\la_data_in_enable[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[2] (.A(net310),
+ .B(\mprj_logic1[332] ),
+ .X(\la_data_in_enable[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[30] (.A(net311),
+ .B(\mprj_logic1[360] ),
+ .X(\la_data_in_enable[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[31] (.A(net312),
+ .B(\mprj_logic1[361] ),
+ .X(\la_data_in_enable[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[32] (.A(net313),
+ .B(\mprj_logic1[362] ),
+ .X(\la_data_in_enable[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[33] (.A(net314),
+ .B(\mprj_logic1[363] ),
+ .X(\la_data_in_enable[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[34] (.A(net315),
+ .B(\mprj_logic1[364] ),
+ .X(\la_data_in_enable[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[35] (.A(net316),
+ .B(\mprj_logic1[365] ),
+ .X(\la_data_in_enable[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[36] (.A(net317),
+ .B(\mprj_logic1[366] ),
+ .X(\la_data_in_enable[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[37] (.A(net318),
+ .B(\mprj_logic1[367] ),
+ .X(\la_data_in_enable[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[38] (.A(net319),
+ .B(\mprj_logic1[368] ),
+ .X(\la_data_in_enable[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[39] (.A(net320),
+ .B(\mprj_logic1[369] ),
+ .X(\la_data_in_enable[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[3] (.A(net321),
+ .B(\mprj_logic1[333] ),
+ .X(\la_data_in_enable[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[40] (.A(net322),
+ .B(\mprj_logic1[370] ),
+ .X(\la_data_in_enable[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[41] (.A(net323),
+ .B(\mprj_logic1[371] ),
+ .X(\la_data_in_enable[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[42] (.A(net324),
+ .B(\mprj_logic1[372] ),
+ .X(\la_data_in_enable[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[43] (.A(net325),
+ .B(\mprj_logic1[373] ),
+ .X(\la_data_in_enable[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[44] (.A(net326),
+ .B(\mprj_logic1[374] ),
+ .X(\la_data_in_enable[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[45] (.A(net327),
+ .B(\mprj_logic1[375] ),
+ .X(\la_data_in_enable[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[46] (.A(net328),
+ .B(\mprj_logic1[376] ),
+ .X(\la_data_in_enable[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[47] (.A(net329),
+ .B(\mprj_logic1[377] ),
+ .X(\la_data_in_enable[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[48] (.A(net330),
+ .B(\mprj_logic1[378] ),
+ .X(\la_data_in_enable[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[49] (.A(net331),
+ .B(\mprj_logic1[379] ),
+ .X(\la_data_in_enable[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[4] (.A(net332),
+ .B(\mprj_logic1[334] ),
+ .X(\la_data_in_enable[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[50] (.A(net333),
+ .B(\mprj_logic1[380] ),
+ .X(\la_data_in_enable[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[51] (.A(net334),
+ .B(\mprj_logic1[381] ),
+ .X(\la_data_in_enable[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[52] (.A(net335),
+ .B(\mprj_logic1[382] ),
+ .X(\la_data_in_enable[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[53] (.A(net336),
+ .B(\mprj_logic1[383] ),
+ .X(\la_data_in_enable[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[54] (.A(net337),
+ .B(\mprj_logic1[384] ),
+ .X(\la_data_in_enable[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[55] (.A(net338),
+ .B(\mprj_logic1[385] ),
+ .X(\la_data_in_enable[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[56] (.A(net339),
+ .B(\mprj_logic1[386] ),
+ .X(\la_data_in_enable[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[57] (.A(net340),
+ .B(\mprj_logic1[387] ),
+ .X(\la_data_in_enable[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[58] (.A(net341),
+ .B(\mprj_logic1[388] ),
+ .X(\la_data_in_enable[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[59] (.A(net342),
+ .B(\mprj_logic1[389] ),
+ .X(\la_data_in_enable[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[5] (.A(net343),
+ .B(\mprj_logic1[335] ),
+ .X(\la_data_in_enable[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[60] (.A(net344),
+ .B(\mprj_logic1[390] ),
+ .X(\la_data_in_enable[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[61] (.A(net345),
+ .B(\mprj_logic1[391] ),
+ .X(\la_data_in_enable[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[62] (.A(net346),
+ .B(\mprj_logic1[392] ),
+ .X(\la_data_in_enable[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[63] (.A(net347),
+ .B(\mprj_logic1[393] ),
+ .X(\la_data_in_enable[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[64] (.A(net348),
+ .B(\mprj_logic1[394] ),
+ .X(\la_data_in_enable[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[65] (.A(net349),
+ .B(\mprj_logic1[395] ),
+ .X(\la_data_in_enable[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[66] (.A(net350),
+ .B(\mprj_logic1[396] ),
+ .X(\la_data_in_enable[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[67] (.A(net351),
+ .B(\mprj_logic1[397] ),
+ .X(\la_data_in_enable[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[68] (.A(net352),
+ .B(\mprj_logic1[398] ),
+ .X(\la_data_in_enable[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[69] (.A(net353),
+ .B(\mprj_logic1[399] ),
+ .X(\la_data_in_enable[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[6] (.A(net354),
+ .B(\mprj_logic1[336] ),
+ .X(\la_data_in_enable[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[70] (.A(net355),
+ .B(\mprj_logic1[400] ),
+ .X(\la_data_in_enable[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[71] (.A(net356),
+ .B(\mprj_logic1[401] ),
+ .X(\la_data_in_enable[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[72] (.A(net357),
+ .B(\mprj_logic1[402] ),
+ .X(\la_data_in_enable[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[73] (.A(net358),
+ .B(\mprj_logic1[403] ),
+ .X(\la_data_in_enable[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[74] (.A(net359),
+ .B(\mprj_logic1[404] ),
+ .X(\la_data_in_enable[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[75] (.A(net360),
+ .B(\mprj_logic1[405] ),
+ .X(\la_data_in_enable[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[76] (.A(net361),
+ .B(\mprj_logic1[406] ),
+ .X(\la_data_in_enable[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[77] (.A(net362),
+ .B(\mprj_logic1[407] ),
+ .X(\la_data_in_enable[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[78] (.A(net363),
+ .B(\mprj_logic1[408] ),
+ .X(\la_data_in_enable[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[79] (.A(net364),
+ .B(\mprj_logic1[409] ),
+ .X(\la_data_in_enable[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[7] (.A(net365),
+ .B(\mprj_logic1[337] ),
+ .X(\la_data_in_enable[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[80] (.A(net366),
+ .B(\mprj_logic1[410] ),
+ .X(\la_data_in_enable[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[81] (.A(net367),
+ .B(\mprj_logic1[411] ),
+ .X(\la_data_in_enable[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[82] (.A(net368),
+ .B(\mprj_logic1[412] ),
+ .X(\la_data_in_enable[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[83] (.A(net369),
+ .B(\mprj_logic1[413] ),
+ .X(\la_data_in_enable[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[84] (.A(net370),
+ .B(\mprj_logic1[414] ),
+ .X(\la_data_in_enable[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[85] (.A(net371),
+ .B(\mprj_logic1[415] ),
+ .X(\la_data_in_enable[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[86] (.A(net372),
+ .B(\mprj_logic1[416] ),
+ .X(\la_data_in_enable[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[87] (.A(net373),
+ .B(\mprj_logic1[417] ),
+ .X(\la_data_in_enable[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[88] (.A(net374),
+ .B(\mprj_logic1[418] ),
+ .X(\la_data_in_enable[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[89] (.A(net375),
+ .B(\mprj_logic1[419] ),
+ .X(\la_data_in_enable[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[8] (.A(net376),
+ .B(\mprj_logic1[338] ),
+ .X(\la_data_in_enable[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[90] (.A(net377),
+ .B(\mprj_logic1[420] ),
+ .X(\la_data_in_enable[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[91] (.A(net378),
+ .B(\mprj_logic1[421] ),
+ .X(\la_data_in_enable[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[92] (.A(net379),
+ .B(\mprj_logic1[422] ),
+ .X(\la_data_in_enable[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[93] (.A(net380),
+ .B(\mprj_logic1[423] ),
+ .X(\la_data_in_enable[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[94] (.A(net381),
+ .B(\mprj_logic1[424] ),
+ .X(\la_data_in_enable[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[95] (.A(net382),
+ .B(\mprj_logic1[425] ),
+ .X(\la_data_in_enable[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[96] (.A(net383),
+ .B(\mprj_logic1[426] ),
+ .X(\la_data_in_enable[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[97] (.A(net384),
+ .B(\mprj_logic1[427] ),
+ .X(\la_data_in_enable[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[98] (.A(net385),
+ .B(\mprj_logic1[428] ),
+ .X(\la_data_in_enable[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[99] (.A(net386),
+ .B(\mprj_logic1[429] ),
+ .X(\la_data_in_enable[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_1 \user_to_mprj_in_ena_buf[9] (.A(net387),
+ .B(\mprj_logic1[339] ),
+ .X(\la_data_in_enable[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[0] (.A(net4),
+ .B(\la_data_in_enable[0] ),
+ .Y(\la_data_in_mprj_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[100] (.A(net5),
+ .B(\la_data_in_enable[100] ),
+ .Y(\la_data_in_mprj_bar[100] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[101] (.A(net6),
+ .B(\la_data_in_enable[101] ),
+ .Y(\la_data_in_mprj_bar[101] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[102] (.A(net7),
+ .B(\la_data_in_enable[102] ),
+ .Y(\la_data_in_mprj_bar[102] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[103] (.A(net8),
+ .B(\la_data_in_enable[103] ),
+ .Y(\la_data_in_mprj_bar[103] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[104] (.A(net9),
+ .B(\la_data_in_enable[104] ),
+ .Y(\la_data_in_mprj_bar[104] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[105] (.A(net10),
+ .B(\la_data_in_enable[105] ),
+ .Y(\la_data_in_mprj_bar[105] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[106] (.A(net11),
+ .B(\la_data_in_enable[106] ),
+ .Y(\la_data_in_mprj_bar[106] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[107] (.A(net12),
+ .B(\la_data_in_enable[107] ),
+ .Y(\la_data_in_mprj_bar[107] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[108] (.A(net13),
+ .B(\la_data_in_enable[108] ),
+ .Y(\la_data_in_mprj_bar[108] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[109] (.A(net14),
+ .B(\la_data_in_enable[109] ),
+ .Y(\la_data_in_mprj_bar[109] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[10] (.A(net15),
+ .B(\la_data_in_enable[10] ),
+ .Y(\la_data_in_mprj_bar[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[110] (.A(net16),
+ .B(\la_data_in_enable[110] ),
+ .Y(\la_data_in_mprj_bar[110] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[111] (.A(net17),
+ .B(\la_data_in_enable[111] ),
+ .Y(\la_data_in_mprj_bar[111] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[112] (.A(net18),
+ .B(\la_data_in_enable[112] ),
+ .Y(\la_data_in_mprj_bar[112] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[113] (.A(net19),
+ .B(\la_data_in_enable[113] ),
+ .Y(\la_data_in_mprj_bar[113] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[114] (.A(net20),
+ .B(\la_data_in_enable[114] ),
+ .Y(\la_data_in_mprj_bar[114] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[115] (.A(net21),
+ .B(\la_data_in_enable[115] ),
+ .Y(\la_data_in_mprj_bar[115] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[116] (.A(net22),
+ .B(\la_data_in_enable[116] ),
+ .Y(\la_data_in_mprj_bar[116] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[117] (.A(net23),
+ .B(\la_data_in_enable[117] ),
+ .Y(\la_data_in_mprj_bar[117] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[118] (.A(net24),
+ .B(\la_data_in_enable[118] ),
+ .Y(\la_data_in_mprj_bar[118] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[119] (.A(net25),
+ .B(\la_data_in_enable[119] ),
+ .Y(\la_data_in_mprj_bar[119] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[11] (.A(net26),
+ .B(\la_data_in_enable[11] ),
+ .Y(\la_data_in_mprj_bar[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[120] (.A(net27),
+ .B(\la_data_in_enable[120] ),
+ .Y(\la_data_in_mprj_bar[120] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[121] (.A(net28),
+ .B(\la_data_in_enable[121] ),
+ .Y(\la_data_in_mprj_bar[121] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[122] (.A(net29),
+ .B(\la_data_in_enable[122] ),
+ .Y(\la_data_in_mprj_bar[122] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[123] (.A(net30),
+ .B(\la_data_in_enable[123] ),
+ .Y(\la_data_in_mprj_bar[123] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[124] (.A(net31),
+ .B(\la_data_in_enable[124] ),
+ .Y(\la_data_in_mprj_bar[124] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[125] (.A(net32),
+ .B(\la_data_in_enable[125] ),
+ .Y(\la_data_in_mprj_bar[125] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[126] (.A(net33),
+ .B(\la_data_in_enable[126] ),
+ .Y(\la_data_in_mprj_bar[126] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[127] (.A(net34),
+ .B(\la_data_in_enable[127] ),
+ .Y(\la_data_in_mprj_bar[127] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[12] (.A(net35),
+ .B(\la_data_in_enable[12] ),
+ .Y(\la_data_in_mprj_bar[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[13] (.A(net36),
+ .B(\la_data_in_enable[13] ),
+ .Y(\la_data_in_mprj_bar[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[14] (.A(net37),
+ .B(\la_data_in_enable[14] ),
+ .Y(\la_data_in_mprj_bar[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[15] (.A(net38),
+ .B(\la_data_in_enable[15] ),
+ .Y(\la_data_in_mprj_bar[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[16] (.A(net39),
+ .B(\la_data_in_enable[16] ),
+ .Y(\la_data_in_mprj_bar[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[17] (.A(net40),
+ .B(\la_data_in_enable[17] ),
+ .Y(\la_data_in_mprj_bar[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[18] (.A(net41),
+ .B(\la_data_in_enable[18] ),
+ .Y(\la_data_in_mprj_bar[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[19] (.A(net42),
+ .B(\la_data_in_enable[19] ),
+ .Y(\la_data_in_mprj_bar[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[1] (.A(net43),
+ .B(\la_data_in_enable[1] ),
+ .Y(\la_data_in_mprj_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[20] (.A(net44),
+ .B(\la_data_in_enable[20] ),
+ .Y(\la_data_in_mprj_bar[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[21] (.A(net45),
+ .B(\la_data_in_enable[21] ),
+ .Y(\la_data_in_mprj_bar[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[22] (.A(net46),
+ .B(\la_data_in_enable[22] ),
+ .Y(\la_data_in_mprj_bar[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[23] (.A(net47),
+ .B(\la_data_in_enable[23] ),
+ .Y(\la_data_in_mprj_bar[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[24] (.A(net48),
+ .B(\la_data_in_enable[24] ),
+ .Y(\la_data_in_mprj_bar[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[25] (.A(net49),
+ .B(\la_data_in_enable[25] ),
+ .Y(\la_data_in_mprj_bar[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[26] (.A(net50),
+ .B(\la_data_in_enable[26] ),
+ .Y(\la_data_in_mprj_bar[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[27] (.A(net51),
+ .B(\la_data_in_enable[27] ),
+ .Y(\la_data_in_mprj_bar[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[28] (.A(net52),
+ .B(\la_data_in_enable[28] ),
+ .Y(\la_data_in_mprj_bar[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[29] (.A(net53),
+ .B(\la_data_in_enable[29] ),
+ .Y(\la_data_in_mprj_bar[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[2] (.A(net54),
+ .B(\la_data_in_enable[2] ),
+ .Y(\la_data_in_mprj_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[30] (.A(net55),
+ .B(\la_data_in_enable[30] ),
+ .Y(\la_data_in_mprj_bar[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[31] (.A(net56),
+ .B(\la_data_in_enable[31] ),
+ .Y(\la_data_in_mprj_bar[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[32] (.A(net57),
+ .B(\la_data_in_enable[32] ),
+ .Y(\la_data_in_mprj_bar[32] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[33] (.A(net58),
+ .B(\la_data_in_enable[33] ),
+ .Y(\la_data_in_mprj_bar[33] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[34] (.A(net59),
+ .B(\la_data_in_enable[34] ),
+ .Y(\la_data_in_mprj_bar[34] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[35] (.A(net60),
+ .B(\la_data_in_enable[35] ),
+ .Y(\la_data_in_mprj_bar[35] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[36] (.A(net61),
+ .B(\la_data_in_enable[36] ),
+ .Y(\la_data_in_mprj_bar[36] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[37] (.A(net62),
+ .B(\la_data_in_enable[37] ),
+ .Y(\la_data_in_mprj_bar[37] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[38] (.A(net63),
+ .B(\la_data_in_enable[38] ),
+ .Y(\la_data_in_mprj_bar[38] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[39] (.A(net64),
+ .B(\la_data_in_enable[39] ),
+ .Y(\la_data_in_mprj_bar[39] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[3] (.A(net65),
+ .B(\la_data_in_enable[3] ),
+ .Y(\la_data_in_mprj_bar[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[40] (.A(net66),
+ .B(\la_data_in_enable[40] ),
+ .Y(\la_data_in_mprj_bar[40] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[41] (.A(net67),
+ .B(\la_data_in_enable[41] ),
+ .Y(\la_data_in_mprj_bar[41] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[42] (.A(net68),
+ .B(\la_data_in_enable[42] ),
+ .Y(\la_data_in_mprj_bar[42] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[43] (.A(net69),
+ .B(\la_data_in_enable[43] ),
+ .Y(\la_data_in_mprj_bar[43] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[44] (.A(net70),
+ .B(\la_data_in_enable[44] ),
+ .Y(\la_data_in_mprj_bar[44] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[45] (.A(net71),
+ .B(\la_data_in_enable[45] ),
+ .Y(\la_data_in_mprj_bar[45] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[46] (.A(net72),
+ .B(\la_data_in_enable[46] ),
+ .Y(\la_data_in_mprj_bar[46] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[47] (.A(net73),
+ .B(\la_data_in_enable[47] ),
+ .Y(\la_data_in_mprj_bar[47] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[48] (.A(net74),
+ .B(\la_data_in_enable[48] ),
+ .Y(\la_data_in_mprj_bar[48] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[49] (.A(net75),
+ .B(\la_data_in_enable[49] ),
+ .Y(\la_data_in_mprj_bar[49] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[4] (.A(net76),
+ .B(\la_data_in_enable[4] ),
+ .Y(\la_data_in_mprj_bar[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[50] (.A(net77),
+ .B(\la_data_in_enable[50] ),
+ .Y(\la_data_in_mprj_bar[50] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[51] (.A(net78),
+ .B(\la_data_in_enable[51] ),
+ .Y(\la_data_in_mprj_bar[51] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[52] (.A(net79),
+ .B(\la_data_in_enable[52] ),
+ .Y(\la_data_in_mprj_bar[52] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[53] (.A(net80),
+ .B(\la_data_in_enable[53] ),
+ .Y(\la_data_in_mprj_bar[53] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[54] (.A(net81),
+ .B(\la_data_in_enable[54] ),
+ .Y(\la_data_in_mprj_bar[54] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[55] (.A(net82),
+ .B(\la_data_in_enable[55] ),
+ .Y(\la_data_in_mprj_bar[55] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[56] (.A(net83),
+ .B(\la_data_in_enable[56] ),
+ .Y(\la_data_in_mprj_bar[56] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[57] (.A(net84),
+ .B(\la_data_in_enable[57] ),
+ .Y(\la_data_in_mprj_bar[57] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[58] (.A(net85),
+ .B(\la_data_in_enable[58] ),
+ .Y(\la_data_in_mprj_bar[58] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[59] (.A(net86),
+ .B(\la_data_in_enable[59] ),
+ .Y(\la_data_in_mprj_bar[59] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[5] (.A(net87),
+ .B(\la_data_in_enable[5] ),
+ .Y(\la_data_in_mprj_bar[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[60] (.A(net88),
+ .B(\la_data_in_enable[60] ),
+ .Y(\la_data_in_mprj_bar[60] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[61] (.A(net89),
+ .B(\la_data_in_enable[61] ),
+ .Y(\la_data_in_mprj_bar[61] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[62] (.A(net90),
+ .B(\la_data_in_enable[62] ),
+ .Y(\la_data_in_mprj_bar[62] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[63] (.A(net91),
+ .B(\la_data_in_enable[63] ),
+ .Y(\la_data_in_mprj_bar[63] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[64] (.A(net92),
+ .B(\la_data_in_enable[64] ),
+ .Y(\la_data_in_mprj_bar[64] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[65] (.A(net93),
+ .B(\la_data_in_enable[65] ),
+ .Y(\la_data_in_mprj_bar[65] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[66] (.A(net94),
+ .B(\la_data_in_enable[66] ),
+ .Y(\la_data_in_mprj_bar[66] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[67] (.A(net95),
+ .B(\la_data_in_enable[67] ),
+ .Y(\la_data_in_mprj_bar[67] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[68] (.A(net96),
+ .B(\la_data_in_enable[68] ),
+ .Y(\la_data_in_mprj_bar[68] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[69] (.A(net97),
+ .B(\la_data_in_enable[69] ),
+ .Y(\la_data_in_mprj_bar[69] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[6] (.A(net98),
+ .B(\la_data_in_enable[6] ),
+ .Y(\la_data_in_mprj_bar[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[70] (.A(net99),
+ .B(\la_data_in_enable[70] ),
+ .Y(\la_data_in_mprj_bar[70] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[71] (.A(net100),
+ .B(\la_data_in_enable[71] ),
+ .Y(\la_data_in_mprj_bar[71] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[72] (.A(net101),
+ .B(\la_data_in_enable[72] ),
+ .Y(\la_data_in_mprj_bar[72] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[73] (.A(net102),
+ .B(\la_data_in_enable[73] ),
+ .Y(\la_data_in_mprj_bar[73] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[74] (.A(net103),
+ .B(\la_data_in_enable[74] ),
+ .Y(\la_data_in_mprj_bar[74] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[75] (.A(net104),
+ .B(\la_data_in_enable[75] ),
+ .Y(\la_data_in_mprj_bar[75] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[76] (.A(net105),
+ .B(\la_data_in_enable[76] ),
+ .Y(\la_data_in_mprj_bar[76] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[77] (.A(net106),
+ .B(\la_data_in_enable[77] ),
+ .Y(\la_data_in_mprj_bar[77] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[78] (.A(net107),
+ .B(\la_data_in_enable[78] ),
+ .Y(\la_data_in_mprj_bar[78] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[79] (.A(net108),
+ .B(\la_data_in_enable[79] ),
+ .Y(\la_data_in_mprj_bar[79] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[7] (.A(net109),
+ .B(\la_data_in_enable[7] ),
+ .Y(\la_data_in_mprj_bar[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[80] (.A(net110),
+ .B(\la_data_in_enable[80] ),
+ .Y(\la_data_in_mprj_bar[80] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[81] (.A(net111),
+ .B(\la_data_in_enable[81] ),
+ .Y(\la_data_in_mprj_bar[81] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[82] (.A(net112),
+ .B(\la_data_in_enable[82] ),
+ .Y(\la_data_in_mprj_bar[82] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[83] (.A(net113),
+ .B(\la_data_in_enable[83] ),
+ .Y(\la_data_in_mprj_bar[83] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[84] (.A(net114),
+ .B(\la_data_in_enable[84] ),
+ .Y(\la_data_in_mprj_bar[84] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[85] (.A(net115),
+ .B(\la_data_in_enable[85] ),
+ .Y(\la_data_in_mprj_bar[85] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[86] (.A(net116),
+ .B(\la_data_in_enable[86] ),
+ .Y(\la_data_in_mprj_bar[86] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[87] (.A(net117),
+ .B(\la_data_in_enable[87] ),
+ .Y(\la_data_in_mprj_bar[87] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[88] (.A(net118),
+ .B(\la_data_in_enable[88] ),
+ .Y(\la_data_in_mprj_bar[88] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[89] (.A(net119),
+ .B(\la_data_in_enable[89] ),
+ .Y(\la_data_in_mprj_bar[89] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[8] (.A(net120),
+ .B(\la_data_in_enable[8] ),
+ .Y(\la_data_in_mprj_bar[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[90] (.A(net121),
+ .B(\la_data_in_enable[90] ),
+ .Y(\la_data_in_mprj_bar[90] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[91] (.A(net122),
+ .B(\la_data_in_enable[91] ),
+ .Y(\la_data_in_mprj_bar[91] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[92] (.A(net123),
+ .B(\la_data_in_enable[92] ),
+ .Y(\la_data_in_mprj_bar[92] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[93] (.A(net124),
+ .B(\la_data_in_enable[93] ),
+ .Y(\la_data_in_mprj_bar[93] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[94] (.A(net125),
+ .B(\la_data_in_enable[94] ),
+ .Y(\la_data_in_mprj_bar[94] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[95] (.A(net126),
+ .B(\la_data_in_enable[95] ),
+ .Y(\la_data_in_mprj_bar[95] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[96] (.A(net127),
+ .B(\la_data_in_enable[96] ),
+ .Y(\la_data_in_mprj_bar[96] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[97] (.A(net128),
+ .B(\la_data_in_enable[97] ),
+ .Y(\la_data_in_mprj_bar[97] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[98] (.A(net129),
+ .B(\la_data_in_enable[98] ),
+ .Y(\la_data_in_mprj_bar[98] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_1 \user_to_mprj_in_gates[99] (.A(net130),
+ .B(\la_data_in_enable[99] ),
+ .Y(\la_data_in_mprj_bar[99] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_to_mprj_in_gates[9] (.A(net131),
+ .B(\la_data_in_enable[9] ),
+ .Y(\la_data_in_mprj_bar[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[0] (.A(_201_),
+ .TE(\mprj_logic1[202] ),
+ .Z(net883),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[100] (.A(_202_),
+ .TE(\mprj_logic1[302] ),
+ .Z(net884),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[101] (.A(_203_),
+ .TE(\mprj_logic1[303] ),
+ .Z(net885),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[102] (.A(_204_),
+ .TE(\mprj_logic1[304] ),
+ .Z(net886),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[103] (.A(_205_),
+ .TE(\mprj_logic1[305] ),
+ .Z(net887),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[104] (.A(_206_),
+ .TE(\mprj_logic1[306] ),
+ .Z(net888),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[105] (.A(_207_),
+ .TE(\mprj_logic1[307] ),
+ .Z(net889),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[106] (.A(_208_),
+ .TE(\mprj_logic1[308] ),
+ .Z(net890),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[107] (.A(_209_),
+ .TE(\mprj_logic1[309] ),
+ .Z(net891),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[108] (.A(_210_),
+ .TE(\mprj_logic1[310] ),
+ .Z(net892),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[109] (.A(_211_),
+ .TE(\mprj_logic1[311] ),
+ .Z(net893),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[10] (.A(_212_),
+ .TE(\mprj_logic1[212] ),
+ .Z(net894),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[110] (.A(_213_),
+ .TE(\mprj_logic1[312] ),
+ .Z(net895),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[111] (.A(_214_),
+ .TE(\mprj_logic1[313] ),
+ .Z(net896),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[112] (.A(_215_),
+ .TE(\mprj_logic1[314] ),
+ .Z(net897),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[113] (.A(_216_),
+ .TE(\mprj_logic1[315] ),
+ .Z(net898),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[114] (.A(_217_),
+ .TE(\mprj_logic1[316] ),
+ .Z(net899),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[115] (.A(_218_),
+ .TE(\mprj_logic1[317] ),
+ .Z(net900),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[116] (.A(_219_),
+ .TE(\mprj_logic1[318] ),
+ .Z(net901),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[117] (.A(_220_),
+ .TE(\mprj_logic1[319] ),
+ .Z(net902),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[118] (.A(_221_),
+ .TE(\mprj_logic1[320] ),
+ .Z(net903),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[119] (.A(_222_),
+ .TE(\mprj_logic1[321] ),
+ .Z(net904),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[11] (.A(_223_),
+ .TE(\mprj_logic1[213] ),
+ .Z(net905),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[120] (.A(_224_),
+ .TE(\mprj_logic1[322] ),
+ .Z(net906),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[121] (.A(_225_),
+ .TE(\mprj_logic1[323] ),
+ .Z(net907),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[122] (.A(_226_),
+ .TE(\mprj_logic1[324] ),
+ .Z(net908),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[123] (.A(_227_),
+ .TE(\mprj_logic1[325] ),
+ .Z(net909),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[124] (.A(_228_),
+ .TE(\mprj_logic1[326] ),
+ .Z(net910),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[125] (.A(_229_),
+ .TE(\mprj_logic1[327] ),
+ .Z(net911),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[126] (.A(_230_),
+ .TE(\mprj_logic1[328] ),
+ .Z(net912),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[127] (.A(_231_),
+ .TE(\mprj_logic1[329] ),
+ .Z(net913),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[12] (.A(_232_),
+ .TE(\mprj_logic1[214] ),
+ .Z(net914),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[13] (.A(_233_),
+ .TE(\mprj_logic1[215] ),
+ .Z(net915),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[14] (.A(_234_),
+ .TE(\mprj_logic1[216] ),
+ .Z(net916),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[15] (.A(_235_),
+ .TE(\mprj_logic1[217] ),
+ .Z(net917),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[16] (.A(_236_),
+ .TE(\mprj_logic1[218] ),
+ .Z(net918),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[17] (.A(_237_),
+ .TE(\mprj_logic1[219] ),
+ .Z(net919),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[18] (.A(_238_),
+ .TE(\mprj_logic1[220] ),
+ .Z(net920),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[19] (.A(_239_),
+ .TE(\mprj_logic1[221] ),
+ .Z(net921),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[1] (.A(_240_),
+ .TE(\mprj_logic1[203] ),
+ .Z(net922),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[20] (.A(_241_),
+ .TE(\mprj_logic1[222] ),
+ .Z(net923),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[21] (.A(_242_),
+ .TE(\mprj_logic1[223] ),
+ .Z(net924),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[22] (.A(_243_),
+ .TE(\mprj_logic1[224] ),
+ .Z(net925),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[23] (.A(_244_),
+ .TE(\mprj_logic1[225] ),
+ .Z(net926),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[24] (.A(_245_),
+ .TE(\mprj_logic1[226] ),
+ .Z(net927),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[25] (.A(_246_),
+ .TE(\mprj_logic1[227] ),
+ .Z(net928),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[26] (.A(_247_),
+ .TE(\mprj_logic1[228] ),
+ .Z(net929),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[27] (.A(_248_),
+ .TE(\mprj_logic1[229] ),
+ .Z(net930),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[28] (.A(_249_),
+ .TE(\mprj_logic1[230] ),
+ .Z(net931),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[29] (.A(_250_),
+ .TE(\mprj_logic1[231] ),
+ .Z(net932),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[2] (.A(_251_),
+ .TE(\mprj_logic1[204] ),
+ .Z(net933),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[30] (.A(_252_),
+ .TE(\mprj_logic1[232] ),
+ .Z(net934),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[31] (.A(_253_),
+ .TE(\mprj_logic1[233] ),
+ .Z(net935),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[32] (.A(_254_),
+ .TE(\mprj_logic1[234] ),
+ .Z(net936),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[33] (.A(_255_),
+ .TE(\mprj_logic1[235] ),
+ .Z(net937),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[34] (.A(_256_),
+ .TE(\mprj_logic1[236] ),
+ .Z(net938),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[35] (.A(_257_),
+ .TE(\mprj_logic1[237] ),
+ .Z(net939),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[36] (.A(_258_),
+ .TE(\mprj_logic1[238] ),
+ .Z(net940),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[37] (.A(_259_),
+ .TE(\mprj_logic1[239] ),
+ .Z(net941),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[38] (.A(_260_),
+ .TE(\mprj_logic1[240] ),
+ .Z(net942),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[39] (.A(_261_),
+ .TE(\mprj_logic1[241] ),
+ .Z(net943),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[3] (.A(_262_),
+ .TE(\mprj_logic1[205] ),
+ .Z(net944),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[40] (.A(_263_),
+ .TE(\mprj_logic1[242] ),
+ .Z(net945),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[41] (.A(_264_),
+ .TE(\mprj_logic1[243] ),
+ .Z(net946),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[42] (.A(_265_),
+ .TE(\mprj_logic1[244] ),
+ .Z(net947),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[43] (.A(_266_),
+ .TE(\mprj_logic1[245] ),
+ .Z(net948),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[44] (.A(_267_),
+ .TE(\mprj_logic1[246] ),
+ .Z(net949),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[45] (.A(_268_),
+ .TE(\mprj_logic1[247] ),
+ .Z(net950),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[46] (.A(_269_),
+ .TE(\mprj_logic1[248] ),
+ .Z(net951),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[47] (.A(_270_),
+ .TE(\mprj_logic1[249] ),
+ .Z(net952),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[48] (.A(_271_),
+ .TE(\mprj_logic1[250] ),
+ .Z(net953),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[49] (.A(_272_),
+ .TE(\mprj_logic1[251] ),
+ .Z(net954),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[4] (.A(_273_),
+ .TE(\mprj_logic1[206] ),
+ .Z(net955),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[50] (.A(_274_),
+ .TE(\mprj_logic1[252] ),
+ .Z(net956),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[51] (.A(_275_),
+ .TE(\mprj_logic1[253] ),
+ .Z(net957),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[52] (.A(_276_),
+ .TE(\mprj_logic1[254] ),
+ .Z(net958),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[53] (.A(_277_),
+ .TE(\mprj_logic1[255] ),
+ .Z(net959),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[54] (.A(_278_),
+ .TE(\mprj_logic1[256] ),
+ .Z(net960),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[55] (.A(_279_),
+ .TE(\mprj_logic1[257] ),
+ .Z(net961),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[56] (.A(_280_),
+ .TE(\mprj_logic1[258] ),
+ .Z(net962),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[57] (.A(_281_),
+ .TE(\mprj_logic1[259] ),
+ .Z(net963),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[58] (.A(_282_),
+ .TE(\mprj_logic1[260] ),
+ .Z(net964),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[59] (.A(_283_),
+ .TE(\mprj_logic1[261] ),
+ .Z(net965),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[5] (.A(_284_),
+ .TE(\mprj_logic1[207] ),
+ .Z(net966),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[60] (.A(_285_),
+ .TE(\mprj_logic1[262] ),
+ .Z(net967),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[61] (.A(_286_),
+ .TE(\mprj_logic1[263] ),
+ .Z(net968),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[62] (.A(_287_),
+ .TE(\mprj_logic1[264] ),
+ .Z(net969),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[63] (.A(_288_),
+ .TE(\mprj_logic1[265] ),
+ .Z(net970),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[64] (.A(_289_),
+ .TE(\mprj_logic1[266] ),
+ .Z(net971),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[65] (.A(_290_),
+ .TE(\mprj_logic1[267] ),
+ .Z(net972),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[66] (.A(_291_),
+ .TE(\mprj_logic1[268] ),
+ .Z(net973),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[67] (.A(_292_),
+ .TE(\mprj_logic1[269] ),
+ .Z(net974),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[68] (.A(_293_),
+ .TE(\mprj_logic1[270] ),
+ .Z(net975),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[69] (.A(_294_),
+ .TE(\mprj_logic1[271] ),
+ .Z(net976),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[6] (.A(_295_),
+ .TE(\mprj_logic1[208] ),
+ .Z(net977),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[70] (.A(_296_),
+ .TE(\mprj_logic1[272] ),
+ .Z(net978),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[71] (.A(_297_),
+ .TE(\mprj_logic1[273] ),
+ .Z(net979),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[72] (.A(_298_),
+ .TE(\mprj_logic1[274] ),
+ .Z(net980),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[73] (.A(_299_),
+ .TE(\mprj_logic1[275] ),
+ .Z(net981),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[74] (.A(_300_),
+ .TE(\mprj_logic1[276] ),
+ .Z(net982),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[75] (.A(_301_),
+ .TE(\mprj_logic1[277] ),
+ .Z(net983),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[76] (.A(_302_),
+ .TE(\mprj_logic1[278] ),
+ .Z(net984),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[77] (.A(_303_),
+ .TE(\mprj_logic1[279] ),
+ .Z(net985),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[78] (.A(_304_),
+ .TE(\mprj_logic1[280] ),
+ .Z(net986),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[79] (.A(_305_),
+ .TE(\mprj_logic1[281] ),
+ .Z(net987),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[7] (.A(_306_),
+ .TE(\mprj_logic1[209] ),
+ .Z(net988),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[80] (.A(_307_),
+ .TE(\mprj_logic1[282] ),
+ .Z(net989),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[81] (.A(_308_),
+ .TE(\mprj_logic1[283] ),
+ .Z(net990),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[82] (.A(_309_),
+ .TE(\mprj_logic1[284] ),
+ .Z(net991),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[83] (.A(_310_),
+ .TE(\mprj_logic1[285] ),
+ .Z(net992),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[84] (.A(_311_),
+ .TE(\mprj_logic1[286] ),
+ .Z(net993),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[85] (.A(_312_),
+ .TE(\mprj_logic1[287] ),
+ .Z(net994),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[86] (.A(_313_),
+ .TE(\mprj_logic1[288] ),
+ .Z(net995),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[87] (.A(_314_),
+ .TE(\mprj_logic1[289] ),
+ .Z(net996),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[88] (.A(_315_),
+ .TE(\mprj_logic1[290] ),
+ .Z(net997),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[89] (.A(_316_),
+ .TE(\mprj_logic1[291] ),
+ .Z(net998),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[8] (.A(_317_),
+ .TE(\mprj_logic1[210] ),
+ .Z(net999),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[90] (.A(_318_),
+ .TE(\mprj_logic1[292] ),
+ .Z(net1000),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[91] (.A(_319_),
+ .TE(\mprj_logic1[293] ),
+ .Z(net1001),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[92] (.A(_320_),
+ .TE(\mprj_logic1[294] ),
+ .Z(net1002),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[93] (.A(_321_),
+ .TE(\mprj_logic1[295] ),
+ .Z(net1003),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[94] (.A(_322_),
+ .TE(\mprj_logic1[296] ),
+ .Z(net1004),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[95] (.A(_323_),
+ .TE(\mprj_logic1[297] ),
+ .Z(net1005),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[96] (.A(_324_),
+ .TE(\mprj_logic1[298] ),
+ .Z(net1006),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_2 \user_to_mprj_oen_buffers[97] (.A(_325_),
+ .TE(\mprj_logic1[299] ),
+ .Z(net1007),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[98] (.A(_326_),
+ .TE(\mprj_logic1[300] ),
+ .Z(net1008),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_8 \user_to_mprj_oen_buffers[99] (.A(_327_),
+ .TE(\mprj_logic1[301] ),
+ .Z(net1009),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__einvp_4 \user_to_mprj_oen_buffers[9] (.A(_328_),
+ .TE(\mprj_logic1[211] ),
+ .Z(net1010),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__and2_4 user_to_mprj_wb_ena_buf (.A(net614),
+ .B(\mprj_logic1[462] ),
+ .X(wb_in_enable),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 user_wb_ack_buffer (.A(mprj_ack_i_core_bar),
+ .Y(net1011),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 user_wb_ack_gate (.A(net516),
+ .B(wb_in_enable),
+ .Y(mprj_ack_i_core_bar),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[0] (.A(\mprj_dat_i_core_bar[0] ),
+ .Y(net1045),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[10] (.A(\mprj_dat_i_core_bar[10] ),
+ .Y(net1046),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[11] (.A(\mprj_dat_i_core_bar[11] ),
+ .Y(net1047),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[12] (.A(\mprj_dat_i_core_bar[12] ),
+ .Y(net1048),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[13] (.A(\mprj_dat_i_core_bar[13] ),
+ .Y(net1049),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[14] (.A(\mprj_dat_i_core_bar[14] ),
+ .Y(net1050),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[15] (.A(\mprj_dat_i_core_bar[15] ),
+ .Y(net1051),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[16] (.A(\mprj_dat_i_core_bar[16] ),
+ .Y(net1052),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[17] (.A(\mprj_dat_i_core_bar[17] ),
+ .Y(net1053),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[18] (.A(\mprj_dat_i_core_bar[18] ),
+ .Y(net1054),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[19] (.A(\mprj_dat_i_core_bar[19] ),
+ .Y(net1055),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[1] (.A(\mprj_dat_i_core_bar[1] ),
+ .Y(net1056),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[20] (.A(\mprj_dat_i_core_bar[20] ),
+ .Y(net1057),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[21] (.A(\mprj_dat_i_core_bar[21] ),
+ .Y(net1058),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[22] (.A(\mprj_dat_i_core_bar[22] ),
+ .Y(net1059),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[23] (.A(\mprj_dat_i_core_bar[23] ),
+ .Y(net1060),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[24] (.A(\mprj_dat_i_core_bar[24] ),
+ .Y(net1061),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[25] (.A(\mprj_dat_i_core_bar[25] ),
+ .Y(net1062),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[26] (.A(\mprj_dat_i_core_bar[26] ),
+ .Y(net1063),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[27] (.A(\mprj_dat_i_core_bar[27] ),
+ .Y(net1064),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[28] (.A(\mprj_dat_i_core_bar[28] ),
+ .Y(net1065),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[29] (.A(\mprj_dat_i_core_bar[29] ),
+ .Y(net1066),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[2] (.A(\mprj_dat_i_core_bar[2] ),
+ .Y(net1067),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[30] (.A(\mprj_dat_i_core_bar[30] ),
+ .Y(net1068),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_6 \user_wb_dat_buffers[31] (.A(\mprj_dat_i_core_bar[31] ),
+ .Y(net1069),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[3] (.A(\mprj_dat_i_core_bar[3] ),
+ .Y(net1070),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[4] (.A(\mprj_dat_i_core_bar[4] ),
+ .Y(net1071),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[5] (.A(\mprj_dat_i_core_bar[5] ),
+ .Y(net1072),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[6] (.A(\mprj_dat_i_core_bar[6] ),
+ .Y(net1073),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[7] (.A(\mprj_dat_i_core_bar[7] ),
+ .Y(net1074),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[8] (.A(\mprj_dat_i_core_bar[8] ),
+ .Y(net1075),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__clkinv_8 \user_wb_dat_buffers[9] (.A(\mprj_dat_i_core_bar[9] ),
+ .Y(net1076),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[0] (.A(net550),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[0] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[10] (.A(net551),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[10] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[11] (.A(net552),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[11] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[12] (.A(net553),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[12] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[13] (.A(net554),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[13] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[14] (.A(net555),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[14] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[15] (.A(net556),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[15] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[16] (.A(net557),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[16] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[17] (.A(net558),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[17] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[18] (.A(net559),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[18] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[19] (.A(net560),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[19] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[1] (.A(net561),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[1] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_4 \user_wb_dat_gates[20] (.A(net562),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[20] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[21] (.A(net563),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[21] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[22] (.A(net564),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[22] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[23] (.A(net565),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[23] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[24] (.A(net566),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[24] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[25] (.A(net567),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[25] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[26] (.A(net568),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[26] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[27] (.A(net569),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[27] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[28] (.A(net570),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[28] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[29] (.A(net571),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[29] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[2] (.A(net572),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[2] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[30] (.A(net573),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[30] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_8 \user_wb_dat_gates[31] (.A(net574),
+ .B(net1125),
+ .Y(\mprj_dat_i_core_bar[31] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_4 \user_wb_dat_gates[3] (.A(net575),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[3] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_4 \user_wb_dat_gates[4] (.A(net576),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[4] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[5] (.A(net577),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[5] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[6] (.A(net578),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[6] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[7] (.A(net579),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[7] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[8] (.A(net580),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[8] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \user_wb_dat_gates[9] (.A(net581),
+ .B(wb_in_enable),
+ .Y(\mprj_dat_i_core_bar[9] ),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+endmodule
diff --git a/caravel/verilog/gl/mgmt_protect_hv.v b/caravel/verilog/gl/mgmt_protect_hv.v
new file mode 100644
index 0000000..9b2a462
--- /dev/null
+++ b/caravel/verilog/gl/mgmt_protect_hv.v
@@ -0,0 +1,60 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module mgmt_protect_hv(mprj2_vdd_logic1, mprj_vdd_logic1, vccd, vssd, vdda1, vssa1, vdda2, vssa2);
+ output mprj2_vdd_logic1;
+ wire mprj2_vdd_logic1_h;
+ output mprj_vdd_logic1;
+ wire mprj_vdd_logic1_h;
+ input vccd;
+ input vdda1;
+ input vdda2;
+ input vssa2;
+ input vssa1;
+ input vssd;
+ sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
+ .HI(mprj2_vdd_logic1_h),
+ .VGND(vssa2),
+ .VNB(vssa2),
+ .VPB(vdda2),
+ .VPWR(vdda2)
+ );
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
+ .A(mprj2_vdd_logic1_h),
+ .LVPWR(vccd),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vdda2),
+ .VPWR(vdda2),
+ .X(mprj2_vdd_logic1)
+ );
+ sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+ .HI(mprj_vdd_logic1_h),
+ .VGND(vssa1),
+ .VNB(vssa1),
+ .VPB(vdda1),
+ .VPWR(vdda1)
+ );
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
+ .A(mprj_vdd_logic1_h),
+ .LVPWR(vccd),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vdda1),
+ .VPWR(vdda1),
+ .X(mprj_vdd_logic1)
+ );
+endmodule
\ No newline at end of file
diff --git a/caravel/verilog/gl/mprj2_logic_high.v b/caravel/verilog/gl/mprj2_logic_high.v
new file mode 100644
index 0000000..eeac794
--- /dev/null
+++ b/caravel/verilog/gl/mprj2_logic_high.v
@@ -0,0 +1,258 @@
+module mprj2_logic_high (HI,
+ vccd2,
+ vssd2);
+ output HI;
+ input vccd2;
+ input vssd2;
+
+
+ sky130_fd_sc_hd__decap_3 FILLER_0_109 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_113 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_125 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_0_137 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_141 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_15 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_153 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_0_165 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_169 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_181 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_0_193 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_197 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_4 FILLER_0_209 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_0_213 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_29 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_3 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_41 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_0_53 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_57 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_69 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_0_81 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_85 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_0_97 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_4 FILLER_1_107 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_1_111 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_113 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_125 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_1_137 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_141 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_153 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_1_165 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_169 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_181 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_1_193 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_197 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_4 FILLER_1_209 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_1_213 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_1_27 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_29 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_41 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_1_53 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_57 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_69 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 FILLER_1_81 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_6 FILLER_1_85 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__fill_1 FILLER_1_91 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_12 FILLER_1_95 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_17 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_4 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_5 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(vssd2),
+ .VPWR(vccd2));
+ sky130_fd_sc_hd__conb_1 inst (.HI(HI),
+ .VGND(vssd2),
+ .VNB(vssd2),
+ .VPB(vccd2),
+ .VPWR(vccd2));
+endmodule
diff --git a/caravel/verilog/gl/mprj_logic_high.v b/caravel/verilog/gl/mprj_logic_high.v
new file mode 100644
index 0000000..f503da1
--- /dev/null
+++ b/caravel/verilog/gl/mprj_logic_high.v
@@ -0,0 +1,3364 @@
+module mprj_logic_high (vccd1,
+ vssd1,
+ HI);
+ input vccd1;
+ input vssd1;
+ output [462:0] HI;
+
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_111 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_119 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_139 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_172 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_194 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_228 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_245 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_259 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_279 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_284 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_29 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_306 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_309 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_334 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_421 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_446 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_458 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_474 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_483 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_502 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_57 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_601 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_613 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_617 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_629 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_641 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_645 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_657 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_669 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_67 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_673 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_685 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_697 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_701 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_713 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_725 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_729 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_0_77 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_0_94 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_108 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_113 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_117 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_121 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_133 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_142 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_154 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_172 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_184 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_1_196 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_204 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_209 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_1_221 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_225 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_230 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_242 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_254 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_261 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_273 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_279 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_281 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_1_293 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_1_301 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_307 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_1_319 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_327 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_331 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_335 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_1_337 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_343 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_355 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_367 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_379 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_391 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_393 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_405 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_417 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_429 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_441 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_447 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_449 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_461 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_467 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_1_471 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_479 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_1_484 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_490 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_502 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_505 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_517 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_529 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_541 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_553 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_1_557 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_561 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_573 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_585 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_597 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_609 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_615 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_617 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_629 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_63 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_641 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_653 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_665 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_671 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_673 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_68 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_685 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_697 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_709 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_1_721 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_727 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_1_729 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_80 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_1_92 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_96 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_109 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_11 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_118 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_130 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_138 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_153 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_165 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_177 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_189 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_195 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_197 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_209 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_221 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_233 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_245 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_251 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_253 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_265 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_277 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_289 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_29 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_297 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_302 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_309 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_321 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_333 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_345 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_357 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_363 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_365 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_377 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_386 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_398 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_410 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_418 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_421 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_433 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_442 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_454 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_466 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_470 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_477 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_502 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_514 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_52 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_526 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_533 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_545 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_557 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_569 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_581 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_587 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_589 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_60 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_601 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_613 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_625 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_637 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_643 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_645 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_657 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_669 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_681 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_2_689 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_695 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_710 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_72 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_722 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_2_730 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_85 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_97 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_116 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_3_139 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_3_141 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_166 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_29 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_3_40 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_486 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_3_498 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_3_50 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_3_511 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_530 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_54 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_3_722 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_3_729 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_3_9 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_17 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_18 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_19 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_20 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_21 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_22 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_23 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_24 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_25 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_26 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_27 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_28 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_29 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_30 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_31 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_32 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_33 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_34 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_35 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_36 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_37 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_38 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_39 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_66 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_67 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_68 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_69 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_70 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_71 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_72 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_73 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_74 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_75 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_76 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_77 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_78 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_79 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_80 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_81 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_82 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_83 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_84 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_85 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(vssd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[0] (.HI(HI[0]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[100] (.HI(HI[100]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[101] (.HI(HI[101]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[102] (.HI(HI[102]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[103] (.HI(HI[103]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[104] (.HI(HI[104]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[105] (.HI(HI[105]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[106] (.HI(HI[106]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[107] (.HI(HI[107]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[108] (.HI(HI[108]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[109] (.HI(HI[109]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[10] (.HI(HI[10]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[110] (.HI(HI[110]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[111] (.HI(HI[111]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[112] (.HI(HI[112]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[113] (.HI(HI[113]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[114] (.HI(HI[114]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[115] (.HI(HI[115]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[116] (.HI(HI[116]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[117] (.HI(HI[117]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[118] (.HI(HI[118]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[119] (.HI(HI[119]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[11] (.HI(HI[11]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[120] (.HI(HI[120]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[121] (.HI(HI[121]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[122] (.HI(HI[122]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[123] (.HI(HI[123]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[124] (.HI(HI[124]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[125] (.HI(HI[125]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[126] (.HI(HI[126]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[127] (.HI(HI[127]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[128] (.HI(HI[128]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[129] (.HI(HI[129]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[12] (.HI(HI[12]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[130] (.HI(HI[130]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[131] (.HI(HI[131]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[132] (.HI(HI[132]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[133] (.HI(HI[133]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[134] (.HI(HI[134]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[135] (.HI(HI[135]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[136] (.HI(HI[136]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[137] (.HI(HI[137]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[138] (.HI(HI[138]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[139] (.HI(HI[139]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[13] (.HI(HI[13]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[140] (.HI(HI[140]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[141] (.HI(HI[141]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[142] (.HI(HI[142]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[143] (.HI(HI[143]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[144] (.HI(HI[144]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[145] (.HI(HI[145]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[146] (.HI(HI[146]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[147] (.HI(HI[147]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[148] (.HI(HI[148]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[149] (.HI(HI[149]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[14] (.HI(HI[14]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[150] (.HI(HI[150]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[151] (.HI(HI[151]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[152] (.HI(HI[152]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[153] (.HI(HI[153]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[154] (.HI(HI[154]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[155] (.HI(HI[155]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[156] (.HI(HI[156]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[157] (.HI(HI[157]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[158] (.HI(HI[158]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[159] (.HI(HI[159]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[15] (.HI(HI[15]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[160] (.HI(HI[160]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[161] (.HI(HI[161]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[162] (.HI(HI[162]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[163] (.HI(HI[163]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[164] (.HI(HI[164]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[165] (.HI(HI[165]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[166] (.HI(HI[166]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[167] (.HI(HI[167]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[168] (.HI(HI[168]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[169] (.HI(HI[169]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[16] (.HI(HI[16]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[170] (.HI(HI[170]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[171] (.HI(HI[171]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[172] (.HI(HI[172]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[173] (.HI(HI[173]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[174] (.HI(HI[174]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[175] (.HI(HI[175]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[176] (.HI(HI[176]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[177] (.HI(HI[177]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[178] (.HI(HI[178]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[179] (.HI(HI[179]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[17] (.HI(HI[17]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[180] (.HI(HI[180]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[181] (.HI(HI[181]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[182] (.HI(HI[182]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[183] (.HI(HI[183]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[184] (.HI(HI[184]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[185] (.HI(HI[185]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[186] (.HI(HI[186]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[187] (.HI(HI[187]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[188] (.HI(HI[188]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[189] (.HI(HI[189]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[18] (.HI(HI[18]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[190] (.HI(HI[190]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[191] (.HI(HI[191]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[192] (.HI(HI[192]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[193] (.HI(HI[193]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[194] (.HI(HI[194]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[195] (.HI(HI[195]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[196] (.HI(HI[196]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[197] (.HI(HI[197]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[198] (.HI(HI[198]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[199] (.HI(HI[199]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[19] (.HI(HI[19]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[1] (.HI(HI[1]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[200] (.HI(HI[200]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[201] (.HI(HI[201]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[202] (.HI(HI[202]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[203] (.HI(HI[203]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[204] (.HI(HI[204]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[205] (.HI(HI[205]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[206] (.HI(HI[206]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[207] (.HI(HI[207]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[208] (.HI(HI[208]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[209] (.HI(HI[209]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[20] (.HI(HI[20]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[210] (.HI(HI[210]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[211] (.HI(HI[211]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[212] (.HI(HI[212]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[213] (.HI(HI[213]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[214] (.HI(HI[214]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[215] (.HI(HI[215]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[216] (.HI(HI[216]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[217] (.HI(HI[217]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[218] (.HI(HI[218]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[219] (.HI(HI[219]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[21] (.HI(HI[21]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[220] (.HI(HI[220]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[221] (.HI(HI[221]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[222] (.HI(HI[222]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[223] (.HI(HI[223]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[224] (.HI(HI[224]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[225] (.HI(HI[225]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[226] (.HI(HI[226]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[227] (.HI(HI[227]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[228] (.HI(HI[228]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[229] (.HI(HI[229]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[22] (.HI(HI[22]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[230] (.HI(HI[230]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[231] (.HI(HI[231]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[232] (.HI(HI[232]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[233] (.HI(HI[233]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[234] (.HI(HI[234]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[235] (.HI(HI[235]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[236] (.HI(HI[236]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[237] (.HI(HI[237]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[238] (.HI(HI[238]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[239] (.HI(HI[239]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[23] (.HI(HI[23]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[240] (.HI(HI[240]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[241] (.HI(HI[241]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[242] (.HI(HI[242]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[243] (.HI(HI[243]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[244] (.HI(HI[244]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[245] (.HI(HI[245]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[246] (.HI(HI[246]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[247] (.HI(HI[247]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[248] (.HI(HI[248]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[249] (.HI(HI[249]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[24] (.HI(HI[24]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[250] (.HI(HI[250]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[251] (.HI(HI[251]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[252] (.HI(HI[252]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[253] (.HI(HI[253]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[254] (.HI(HI[254]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[255] (.HI(HI[255]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[256] (.HI(HI[256]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[257] (.HI(HI[257]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[258] (.HI(HI[258]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[259] (.HI(HI[259]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[25] (.HI(HI[25]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[260] (.HI(HI[260]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[261] (.HI(HI[261]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[262] (.HI(HI[262]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[263] (.HI(HI[263]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[264] (.HI(HI[264]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[265] (.HI(HI[265]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[266] (.HI(HI[266]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[267] (.HI(HI[267]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[268] (.HI(HI[268]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[269] (.HI(HI[269]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[26] (.HI(HI[26]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[270] (.HI(HI[270]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[271] (.HI(HI[271]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[272] (.HI(HI[272]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[273] (.HI(HI[273]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[274] (.HI(HI[274]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[275] (.HI(HI[275]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[276] (.HI(HI[276]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[277] (.HI(HI[277]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[278] (.HI(HI[278]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[279] (.HI(HI[279]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[27] (.HI(HI[27]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[280] (.HI(HI[280]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[281] (.HI(HI[281]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[282] (.HI(HI[282]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[283] (.HI(HI[283]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[284] (.HI(HI[284]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[285] (.HI(HI[285]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[286] (.HI(HI[286]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[287] (.HI(HI[287]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[288] (.HI(HI[288]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[289] (.HI(HI[289]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[28] (.HI(HI[28]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[290] (.HI(HI[290]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[291] (.HI(HI[291]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[292] (.HI(HI[292]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[293] (.HI(HI[293]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[294] (.HI(HI[294]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[295] (.HI(HI[295]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[296] (.HI(HI[296]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[297] (.HI(HI[297]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[298] (.HI(HI[298]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[299] (.HI(HI[299]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[29] (.HI(HI[29]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[2] (.HI(HI[2]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[300] (.HI(HI[300]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[301] (.HI(HI[301]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[302] (.HI(HI[302]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[303] (.HI(HI[303]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[304] (.HI(HI[304]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[305] (.HI(HI[305]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[306] (.HI(HI[306]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[307] (.HI(HI[307]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[308] (.HI(HI[308]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[309] (.HI(HI[309]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[30] (.HI(HI[30]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[310] (.HI(HI[310]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[311] (.HI(HI[311]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[312] (.HI(HI[312]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[313] (.HI(HI[313]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[314] (.HI(HI[314]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[315] (.HI(HI[315]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[316] (.HI(HI[316]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[317] (.HI(HI[317]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[318] (.HI(HI[318]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[319] (.HI(HI[319]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[31] (.HI(HI[31]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[320] (.HI(HI[320]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[321] (.HI(HI[321]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[322] (.HI(HI[322]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[323] (.HI(HI[323]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[324] (.HI(HI[324]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[325] (.HI(HI[325]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[326] (.HI(HI[326]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[327] (.HI(HI[327]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[328] (.HI(HI[328]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[329] (.HI(HI[329]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[32] (.HI(HI[32]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[330] (.HI(HI[330]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[331] (.HI(HI[331]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[332] (.HI(HI[332]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[333] (.HI(HI[333]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[334] (.HI(HI[334]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[335] (.HI(HI[335]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[336] (.HI(HI[336]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[337] (.HI(HI[337]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[338] (.HI(HI[338]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[339] (.HI(HI[339]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[33] (.HI(HI[33]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[340] (.HI(HI[340]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[341] (.HI(HI[341]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[342] (.HI(HI[342]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[343] (.HI(HI[343]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[344] (.HI(HI[344]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[345] (.HI(HI[345]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[346] (.HI(HI[346]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[347] (.HI(HI[347]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[348] (.HI(HI[348]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[349] (.HI(HI[349]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[34] (.HI(HI[34]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[350] (.HI(HI[350]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[351] (.HI(HI[351]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[352] (.HI(HI[352]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[353] (.HI(HI[353]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[354] (.HI(HI[354]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[355] (.HI(HI[355]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[356] (.HI(HI[356]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[357] (.HI(HI[357]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[358] (.HI(HI[358]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[359] (.HI(HI[359]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[35] (.HI(HI[35]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[360] (.HI(HI[360]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[361] (.HI(HI[361]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[362] (.HI(HI[362]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[363] (.HI(HI[363]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[364] (.HI(HI[364]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[365] (.HI(HI[365]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[366] (.HI(HI[366]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[367] (.HI(HI[367]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[368] (.HI(HI[368]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[369] (.HI(HI[369]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[36] (.HI(HI[36]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[370] (.HI(HI[370]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[371] (.HI(HI[371]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[372] (.HI(HI[372]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[373] (.HI(HI[373]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[374] (.HI(HI[374]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[375] (.HI(HI[375]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[376] (.HI(HI[376]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[377] (.HI(HI[377]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[378] (.HI(HI[378]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[379] (.HI(HI[379]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[37] (.HI(HI[37]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[380] (.HI(HI[380]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[381] (.HI(HI[381]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[382] (.HI(HI[382]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[383] (.HI(HI[383]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[384] (.HI(HI[384]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[385] (.HI(HI[385]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[386] (.HI(HI[386]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[387] (.HI(HI[387]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[388] (.HI(HI[388]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[389] (.HI(HI[389]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[38] (.HI(HI[38]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[390] (.HI(HI[390]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[391] (.HI(HI[391]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[392] (.HI(HI[392]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[393] (.HI(HI[393]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[394] (.HI(HI[394]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[395] (.HI(HI[395]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[396] (.HI(HI[396]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[397] (.HI(HI[397]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[398] (.HI(HI[398]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[399] (.HI(HI[399]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[39] (.HI(HI[39]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[3] (.HI(HI[3]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[400] (.HI(HI[400]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[401] (.HI(HI[401]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[402] (.HI(HI[402]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[403] (.HI(HI[403]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[404] (.HI(HI[404]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[405] (.HI(HI[405]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[406] (.HI(HI[406]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[407] (.HI(HI[407]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[408] (.HI(HI[408]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[409] (.HI(HI[409]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[40] (.HI(HI[40]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[410] (.HI(HI[410]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[411] (.HI(HI[411]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[412] (.HI(HI[412]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[413] (.HI(HI[413]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[414] (.HI(HI[414]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[415] (.HI(HI[415]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[416] (.HI(HI[416]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[417] (.HI(HI[417]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[418] (.HI(HI[418]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[419] (.HI(HI[419]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[41] (.HI(HI[41]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[420] (.HI(HI[420]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[421] (.HI(HI[421]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[422] (.HI(HI[422]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[423] (.HI(HI[423]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[424] (.HI(HI[424]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[425] (.HI(HI[425]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[426] (.HI(HI[426]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[427] (.HI(HI[427]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[428] (.HI(HI[428]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[429] (.HI(HI[429]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[42] (.HI(HI[42]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[430] (.HI(HI[430]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[431] (.HI(HI[431]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[432] (.HI(HI[432]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[433] (.HI(HI[433]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[434] (.HI(HI[434]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[435] (.HI(HI[435]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[436] (.HI(HI[436]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[437] (.HI(HI[437]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[438] (.HI(HI[438]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[439] (.HI(HI[439]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[43] (.HI(HI[43]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[440] (.HI(HI[440]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[441] (.HI(HI[441]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[442] (.HI(HI[442]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[443] (.HI(HI[443]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[444] (.HI(HI[444]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[445] (.HI(HI[445]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[446] (.HI(HI[446]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[447] (.HI(HI[447]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[448] (.HI(HI[448]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[449] (.HI(HI[449]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[44] (.HI(HI[44]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[450] (.HI(HI[450]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[451] (.HI(HI[451]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[452] (.HI(HI[452]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[453] (.HI(HI[453]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[454] (.HI(HI[454]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[455] (.HI(HI[455]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[456] (.HI(HI[456]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[457] (.HI(HI[457]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[458] (.HI(HI[458]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[459] (.HI(HI[459]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[45] (.HI(HI[45]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[460] (.HI(HI[460]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[461] (.HI(HI[461]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[462] (.HI(HI[462]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[46] (.HI(HI[46]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[47] (.HI(HI[47]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[48] (.HI(HI[48]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[49] (.HI(HI[49]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[4] (.HI(HI[4]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[50] (.HI(HI[50]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[51] (.HI(HI[51]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[52] (.HI(HI[52]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[53] (.HI(HI[53]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[54] (.HI(HI[54]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[55] (.HI(HI[55]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[56] (.HI(HI[56]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[57] (.HI(HI[57]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[58] (.HI(HI[58]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[59] (.HI(HI[59]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[5] (.HI(HI[5]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[60] (.HI(HI[60]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[61] (.HI(HI[61]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[62] (.HI(HI[62]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[63] (.HI(HI[63]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[64] (.HI(HI[64]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[65] (.HI(HI[65]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[66] (.HI(HI[66]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[67] (.HI(HI[67]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[68] (.HI(HI[68]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[69] (.HI(HI[69]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[6] (.HI(HI[6]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[70] (.HI(HI[70]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[71] (.HI(HI[71]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[72] (.HI(HI[72]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[73] (.HI(HI[73]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[74] (.HI(HI[74]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[75] (.HI(HI[75]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[76] (.HI(HI[76]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[77] (.HI(HI[77]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[78] (.HI(HI[78]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[79] (.HI(HI[79]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[7] (.HI(HI[7]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[80] (.HI(HI[80]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[81] (.HI(HI[81]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[82] (.HI(HI[82]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[83] (.HI(HI[83]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[84] (.HI(HI[84]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[85] (.HI(HI[85]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[86] (.HI(HI[86]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[87] (.HI(HI[87]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[88] (.HI(HI[88]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[89] (.HI(HI[89]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[8] (.HI(HI[8]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[90] (.HI(HI[90]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[91] (.HI(HI[91]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[92] (.HI(HI[92]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[93] (.HI(HI[93]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[94] (.HI(HI[94]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[95] (.HI(HI[95]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[96] (.HI(HI[96]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[97] (.HI(HI[97]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[98] (.HI(HI[98]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[99] (.HI(HI[99]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+ sky130_fd_sc_hd__conb_1 \insts[9] (.HI(HI[9]),
+ .VGND(vssd1),
+ .VNB(vssd1),
+ .VPB(vccd1),
+ .VPWR(vccd1));
+endmodule
diff --git a/caravel/verilog/gl/spare_logic_block.v b/caravel/verilog/gl/spare_logic_block.v
new file mode 100644
index 0000000..87182eb
--- /dev/null
+++ b/caravel/verilog/gl/spare_logic_block.v
@@ -0,0 +1,830 @@
+module spare_logic_block (spare_xib,
+ vccd,
+ vssd,
+ spare_xfq,
+ spare_xfqn,
+ spare_xi,
+ spare_xmx,
+ spare_xna,
+ spare_xno,
+ spare_xz);
+ output spare_xib;
+ input vccd;
+ input vssd;
+ output [1:0] spare_xfq;
+ output [1:0] spare_xfqn;
+ output [3:0] spare_xi;
+ output [1:0] spare_xmx;
+ output [1:0] spare_xna;
+ output [1:0] spare_xno;
+ output [26:0] spare_xz;
+
+ wire \spare_logic1[0] ;
+ wire \spare_logic1[10] ;
+ wire \spare_logic1[11] ;
+ wire \spare_logic1[12] ;
+ wire \spare_logic1[13] ;
+ wire \spare_logic1[14] ;
+ wire \spare_logic1[15] ;
+ wire \spare_logic1[16] ;
+ wire \spare_logic1[17] ;
+ wire \spare_logic1[18] ;
+ wire \spare_logic1[19] ;
+ wire \spare_logic1[1] ;
+ wire \spare_logic1[20] ;
+ wire \spare_logic1[21] ;
+ wire \spare_logic1[22] ;
+ wire \spare_logic1[23] ;
+ wire \spare_logic1[24] ;
+ wire \spare_logic1[25] ;
+ wire \spare_logic1[26] ;
+ wire \spare_logic1[2] ;
+ wire \spare_logic1[3] ;
+ wire \spare_logic1[4] ;
+ wire \spare_logic1[5] ;
+ wire \spare_logic1[6] ;
+ wire \spare_logic1[7] ;
+ wire \spare_logic1[8] ;
+ wire \spare_logic1[9] ;
+
+ sky130_fd_sc_hd__decap_6 FILLER_0_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_0_24 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_0_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_0_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_0_42 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_0_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_0_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_0_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_10_21 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_10_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_10_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_10_34 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_10_46 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_52 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_10_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_11_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_11_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_11_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_11_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_11_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_1_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_1_38 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_1_44 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_1_48 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_1_62 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_1_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_2_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_2_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_2_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_2_54 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_2_62 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_2_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_3_35 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_3_47 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_3_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_3_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_3_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_4_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_4_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_4_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_4_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_4_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_12 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_5_31 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_5_43 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_52 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_5_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_6_17 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_25 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_6_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_6_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_59 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_6_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_27 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_7_39 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_7_51 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_55 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_7_61 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_7_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_8_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_29 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_2 FILLER_8_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_41 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_53 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_8_66 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_8_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_24 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_12 FILLER_9_36 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_8 FILLER_9_48 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 FILLER_9_57 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_6 FILLER_9_63 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__fill_1 FILLER_9_69 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_4 FILLER_9_9 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_24 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_25 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_26 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_27 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_28 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_29 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_30 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_31 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_32 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_33 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_34 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_35 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_36 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_37 (.VGND(vssd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_8 spare_logic_biginv (.A(spare_xz[4]),
+ .Y(spare_xib),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[0] (.HI(\spare_logic1[0] ),
+ .LO(spare_xz[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[10] (.HI(\spare_logic1[10] ),
+ .LO(spare_xz[10]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[11] (.HI(\spare_logic1[11] ),
+ .LO(spare_xz[11]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[12] (.HI(\spare_logic1[12] ),
+ .LO(spare_xz[12]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[13] (.HI(\spare_logic1[13] ),
+ .LO(spare_xz[13]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[14] (.HI(\spare_logic1[14] ),
+ .LO(spare_xz[14]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[15] (.HI(\spare_logic1[15] ),
+ .LO(spare_xz[15]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[16] (.HI(\spare_logic1[16] ),
+ .LO(spare_xz[16]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[17] (.HI(\spare_logic1[17] ),
+ .LO(spare_xz[17]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[18] (.HI(\spare_logic1[18] ),
+ .LO(spare_xz[18]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[19] (.HI(\spare_logic1[19] ),
+ .LO(spare_xz[19]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[1] (.HI(\spare_logic1[1] ),
+ .LO(spare_xz[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[20] (.HI(\spare_logic1[20] ),
+ .LO(spare_xz[20]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[21] (.HI(\spare_logic1[21] ),
+ .LO(spare_xz[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[22] (.HI(\spare_logic1[22] ),
+ .LO(spare_xz[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[23] (.HI(\spare_logic1[23] ),
+ .LO(spare_xz[23]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[24] (.HI(\spare_logic1[24] ),
+ .LO(spare_xz[24]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[25] (.HI(\spare_logic1[25] ),
+ .LO(spare_xz[25]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[26] (.HI(\spare_logic1[26] ),
+ .LO(spare_xz[26]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[2] (.HI(\spare_logic1[2] ),
+ .LO(spare_xz[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[3] (.HI(\spare_logic1[3] ),
+ .LO(spare_xz[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[4] (.HI(\spare_logic1[4] ),
+ .LO(spare_xz[4]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[5] (.HI(\spare_logic1[5] ),
+ .LO(spare_xz[5]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[6] (.HI(\spare_logic1[6] ),
+ .LO(spare_xz[6]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[7] (.HI(\spare_logic1[7] ),
+ .LO(spare_xz[7]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[8] (.HI(\spare_logic1[8] ),
+ .LO(spare_xz[8]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__conb_1 \spare_logic_const[9] (.HI(\spare_logic1[9] ),
+ .LO(spare_xz[9]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbp_1 \spare_logic_flop[0] (.D(spare_xz[19]),
+ .Q(spare_xfq[0]),
+ .Q_N(spare_xfqn[0]),
+ .RESET_B(spare_xz[25]),
+ .SET_B(spare_xz[23]),
+ .CLK(spare_xz[21]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__dfbbp_1 \spare_logic_flop[1] (.D(spare_xz[20]),
+ .Q(spare_xfq[1]),
+ .Q_N(spare_xfqn[1]),
+ .RESET_B(spare_xz[26]),
+ .SET_B(spare_xz[24]),
+ .CLK(spare_xz[22]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \spare_logic_inv[0] (.A(spare_xz[0]),
+ .Y(spare_xi[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \spare_logic_inv[1] (.A(spare_xz[1]),
+ .Y(spare_xi[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \spare_logic_inv[2] (.A(spare_xz[2]),
+ .Y(spare_xi[2]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__inv_2 \spare_logic_inv[3] (.A(spare_xz[3]),
+ .Y(spare_xi[3]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_2 \spare_logic_mux[0] (.A0(spare_xz[13]),
+ .A1(spare_xz[15]),
+ .S(spare_xz[17]),
+ .X(spare_xmx[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__mux2_2 \spare_logic_mux[1] (.A0(spare_xz[14]),
+ .A1(spare_xz[16]),
+ .S(spare_xz[18]),
+ .X(spare_xmx[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \spare_logic_nand[0] (.A(spare_xz[5]),
+ .B(spare_xz[7]),
+ .Y(spare_xna[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nand2_2 \spare_logic_nand[1] (.A(spare_xz[6]),
+ .B(spare_xz[8]),
+ .Y(spare_xna[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nor2_2 \spare_logic_nor[0] (.A(spare_xz[9]),
+ .B(spare_xz[11]),
+ .Y(spare_xno[0]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+ sky130_fd_sc_hd__nor2_2 \spare_logic_nor[1] (.A(spare_xz[10]),
+ .B(spare_xz[12]),
+ .Y(spare_xno[1]),
+ .VGND(vssd),
+ .VNB(vssd),
+ .VPB(vccd),
+ .VPWR(vccd));
+endmodule
diff --git a/caravel/verilog/gl/user_id_programming.v b/caravel/verilog/gl/user_id_programming.v
new file mode 100644
index 0000000..0282cfa
--- /dev/null
+++ b/caravel/verilog/gl/user_id_programming.v
@@ -0,0 +1,786 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module user_id_programming(VPWR, VGND, mask_rev);
+ input VGND;
+ input VPWR;
+ output [31:0] mask_rev;
+ wire \user_proj_id_high[0] ;
+ wire \user_proj_id_high[10] ;
+ wire \user_proj_id_high[11] ;
+ wire \user_proj_id_high[12] ;
+ wire \user_proj_id_high[13] ;
+ wire \user_proj_id_high[14] ;
+ wire \user_proj_id_high[15] ;
+ wire \user_proj_id_high[16] ;
+ wire \user_proj_id_high[17] ;
+ wire \user_proj_id_high[18] ;
+ wire \user_proj_id_high[19] ;
+ wire \user_proj_id_high[1] ;
+ wire \user_proj_id_high[20] ;
+ wire \user_proj_id_high[21] ;
+ wire \user_proj_id_high[22] ;
+ wire \user_proj_id_high[23] ;
+ wire \user_proj_id_high[24] ;
+ wire \user_proj_id_high[25] ;
+ wire \user_proj_id_high[26] ;
+ wire \user_proj_id_high[27] ;
+ wire \user_proj_id_high[28] ;
+ wire \user_proj_id_high[29] ;
+ wire \user_proj_id_high[2] ;
+ wire \user_proj_id_high[30] ;
+ wire \user_proj_id_high[31] ;
+ wire \user_proj_id_high[3] ;
+ wire \user_proj_id_high[4] ;
+ wire \user_proj_id_high[5] ;
+ wire \user_proj_id_high[6] ;
+ wire \user_proj_id_high[7] ;
+ wire \user_proj_id_high[8] ;
+ wire \user_proj_id_high[9] ;
+ sky130_fd_sc_hd__decap_3 FILLER_0_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_21 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_0_29 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_0_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_0_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_39 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_0_47 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_7 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_1_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_1_20 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_1_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_1_33 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_1_45 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_1_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_2_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_2_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_2_44 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_18 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_3_42 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_10 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_14 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_4_18 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_26 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_4_35 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_4_41 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_46 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_5_11 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_5_23 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_5_31 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_5_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_5_49 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_5_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_6_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_20 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_6_28 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_6_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_6_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_36 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_6_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_6_48 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_7_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_7_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_7_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_7_36 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_7_42 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_7_46 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_8_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_8_44 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_1 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_10 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_11 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_13 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_14 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_16 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_17 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_2 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_4 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_5 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_7 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_9 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[0] (
+ .HI(\user_proj_id_high[0] ),
+ .LO(mask_rev[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[10] (
+ .HI(\user_proj_id_high[10] ),
+ .LO(mask_rev[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[11] (
+ .HI(\user_proj_id_high[11] ),
+ .LO(mask_rev[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[12] (
+ .HI(\user_proj_id_high[12] ),
+ .LO(mask_rev[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[13] (
+ .HI(\user_proj_id_high[13] ),
+ .LO(mask_rev[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[14] (
+ .HI(\user_proj_id_high[14] ),
+ .LO(mask_rev[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[15] (
+ .HI(\user_proj_id_high[15] ),
+ .LO(mask_rev[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[16] (
+ .HI(\user_proj_id_high[16] ),
+ .LO(mask_rev[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[17] (
+ .HI(\user_proj_id_high[17] ),
+ .LO(mask_rev[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[18] (
+ .HI(\user_proj_id_high[18] ),
+ .LO(mask_rev[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[19] (
+ .HI(\user_proj_id_high[19] ),
+ .LO(mask_rev[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[1] (
+ .HI(\user_proj_id_high[1] ),
+ .LO(mask_rev[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[20] (
+ .HI(\user_proj_id_high[20] ),
+ .LO(mask_rev[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[21] (
+ .HI(\user_proj_id_high[21] ),
+ .LO(mask_rev[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[22] (
+ .HI(\user_proj_id_high[22] ),
+ .LO(mask_rev[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[23] (
+ .HI(\user_proj_id_high[23] ),
+ .LO(mask_rev[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[24] (
+ .HI(\user_proj_id_high[24] ),
+ .LO(mask_rev[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[25] (
+ .HI(\user_proj_id_high[25] ),
+ .LO(mask_rev[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[26] (
+ .HI(\user_proj_id_high[26] ),
+ .LO(mask_rev[26]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[27] (
+ .HI(\user_proj_id_high[27] ),
+ .LO(mask_rev[27]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[28] (
+ .HI(\user_proj_id_high[28] ),
+ .LO(mask_rev[28]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[29] (
+ .HI(\user_proj_id_high[29] ),
+ .LO(mask_rev[29]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[2] (
+ .HI(\user_proj_id_high[2] ),
+ .LO(mask_rev[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[30] (
+ .HI(\user_proj_id_high[30] ),
+ .LO(mask_rev[30]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[31] (
+ .HI(\user_proj_id_high[31] ),
+ .LO(mask_rev[31]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[3] (
+ .HI(\user_proj_id_high[3] ),
+ .LO(mask_rev[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[4] (
+ .HI(\user_proj_id_high[4] ),
+ .LO(mask_rev[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[5] (
+ .HI(\user_proj_id_high[5] ),
+ .LO(mask_rev[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[6] (
+ .HI(\user_proj_id_high[6] ),
+ .LO(mask_rev[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[7] (
+ .HI(\user_proj_id_high[7] ),
+ .LO(mask_rev[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[8] (
+ .HI(\user_proj_id_high[8] ),
+ .LO(mask_rev[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[9] (
+ .HI(\user_proj_id_high[9] ),
+ .LO(mask_rev[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+endmodule
diff --git a/caravel/verilog/gl/xres_buf.v b/caravel/verilog/gl/xres_buf.v
new file mode 100644
index 0000000..ea1f790
--- /dev/null
+++ b/caravel/verilog/gl/xres_buf.v
@@ -0,0 +1,124 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module xres_buf(A, X, VPWR, VGND, LVPWR, LVGND);
+ input A;
+ input LVGND;
+ input LVPWR;
+ input VGND;
+ input VPWR;
+ output X;
+ sky130_fd_sc_hvl__diode_2 ANTENNA_lvlshiftdown_A (
+ .DIODE(A),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_16 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_0_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_2 FILLER_0_28 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_0_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_1_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_1_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_1_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_1_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_2_10 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_2_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_2 FILLER_2_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (
+ .A(A),
+ .LVPWR(LVPWR),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR),
+ .X(X)
+ );
+endmodule
diff --git a/caravel/verilog/rtl/__uprj_analog_netlists.v b/caravel/verilog/rtl/__uprj_analog_netlists.v
new file mode 100644
index 0000000..918b3c4
--- /dev/null
+++ b/caravel/verilog/rtl/__uprj_analog_netlists.v
@@ -0,0 +1,35 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`define USE_POWER_PINS
+
+`include "defines.v"
+
+`ifdef GL
+ `include "gl/__user_analog_project_wrapper.v"
+`else
+ `include "__user_analog_project_wrapper.v"
+`endif
diff --git a/caravel/verilog/rtl/__uprj_netlists.v b/caravel/verilog/rtl/__uprj_netlists.v
new file mode 100644
index 0000000..673a32a
--- /dev/null
+++ b/caravel/verilog/rtl/__uprj_netlists.v
@@ -0,0 +1,35 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`define USE_POWER_PINS
+
+`include "defines.v"
+
+`ifdef GL
+ `include "gl/__user_project_wrapper.v"
+`else
+ `include "__user_project_wrapper.v"
+`endif
\ No newline at end of file
diff --git a/caravel/verilog/rtl/__user_analog_project_wrapper.v b/caravel/verilog/rtl/__user_analog_project_wrapper.v
new file mode 100644
index 0000000..6360f0b
--- /dev/null
+++ b/caravel/verilog/rtl/__user_analog_project_wrapper.v
@@ -0,0 +1,124 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+// Dummy assignment so that we can take it through the openlane flow
+assign io_out = io_in;
+
+endmodule // user_analog_project_wrapper
diff --git a/caravel/verilog/rtl/__user_project_wrapper.v b/caravel/verilog/rtl/__user_project_wrapper.v
new file mode 100644
index 0000000..98ff3a8
--- /dev/null
+++ b/caravel/verilog/rtl/__user_project_wrapper.v
@@ -0,0 +1,90 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+// Dummy assignments so that we can take it through the openlane flow
+`ifdef SIM
+// Needed for running GL simulation
+assign io_out = 0;
+assign io_oeb = 0;
+`else
+assign io_out = io_in;
+`endif
+
+endmodule // user_project_wrapper
diff --git a/caravel/verilog/rtl/caravan.v b/caravel/verilog/rtl/caravan.v
new file mode 100644
index 0000000..bf673a9
--- /dev/null
+++ b/caravel/verilog/rtl/caravan.v
@@ -0,0 +1,1402 @@
+// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravan, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK. caravan is an */
+/* alternative architecture to caravel that has simple straight */
+/* through connections replacing the GPIO pads on the top side */
+/* of the padframe. A total of 11 pads are converted from GPIO */
+/* to analog, leaving 27 GPIO. */
+/* */
+/* Copyright 2021 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+/*--------------------------------------------------------------*/
+/* Derived types for the array bounds on the two digital and */
+/* two analog pad arrays. As defined above, the sections have */
+/* the number of pads as follows: */
+/* */
+/* DIG2 : 13 GPIO pads */
+/* ANA2 : 6 analog pads */
+/* ANA1 : 5 analog pads */
+/* DIG1 : 14 GPIO pads */
+/* */
+/* This makes a total of 38 pads = `MPRJ_IO_PADS */
+/* The pads are still designated as mprj_io[37:0] around the */
+/* padframe. The SoC core remains the same, so the programming */
+/* of the digital signals remains the same, but the values for */
+/* GPIO 15-25 are not used. */
+/*--------------------------------------------------------------*/
+
+`define DIG2_TOP (`MPRJ_IO_PADS - 1)
+`define DIG2_BOT (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2)
+`define ANA2_TOP (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2 - 1)
+`define ANA2_BOT (`MPRJ_IO_PADS_1)
+`define ANA1_TOP (`MPRJ_IO_PADS_1 - 1)
+`define ANA1_BOT (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1)
+`define DIG1_TOP (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1 - 1)
+`define DIG1_BOT (0)
+
+`define MPRJ_DIG_PADS (`MPRJ_IO_PADS - `ANALOG_PADS)
+
+/*--------------------------------------------------------------*/
+/*--------------------------------------------------------------*/
+
+module caravan (
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb,
+
+ // Note that only two pins are available on the flash so dual and
+ // quad flash modes are not available.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00000000;
+
+ /*
+ *---------------------------------------------------------------------
+ * These pins are overlaid on mprj_io space. They have the function
+ * below when the management processor is in reset, or in the default
+ * configuration. They are assigned to uses in the user space by the
+ * configuration program running off of the SPI flash. Note that even
+ * when the user has taken control of these pins, they can be restored
+ * to the original use by setting the resetb pin low. The SPI pins and
+ * UART pins can be connected directly to an FTDI chip as long as the
+ * FTDI chip sets these lines to high impedence (input function) at
+ * all times except when holding the chip in reset.
+ *
+ * JTAG = mprj_io[0] (inout)
+ * SDO = mprj_io[1] (output)
+ * SDI = mprj_io[2] (input)
+ * CSB = mprj_io[3] (input)
+ * SCK = mprj_io[4] (input)
+ * ser_rx = mprj_io[5] (input)
+ * ser_tx = mprj_io[6] (output)
+ * irq = mprj_io[7] (input)
+ *
+ * spi_sck = mprj_io[32] (output)
+ * spi_csb = mprj_io[33] (output)
+ * spi_sdi = mprj_io[34] (input)
+ * spi_sdo = mprj_io[35] (output)
+ * flash_io2 = mprj_io[36] (inout)
+ * flash_io3 = mprj_io[37] (inout)
+ *
+ * These pins are reserved for any project that wants to incorporate
+ * its own processor and flash controller. While a user project can
+ * technically use any available I/O pins for the purpose, these
+ * four pins connect to a pass-through mode from the SPI slave (pins
+ * 1-4 above) so that any SPI flash connected to these specific pins
+ * can be accessed through the SPI slave even when the processor is in
+ * reset.
+ *
+ * user_flash_csb = mprj_io[8]
+ * user_flash_sck = mprj_io[9]
+ * user_flash_io0 = mprj_io[10]
+ * user_flash_io1 = mprj_io[11]
+ *
+ *---------------------------------------------------------------------
+ */
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // 27 GPIO pads with full controls
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_pol;
+ wire [(`MPRJ_IO_PADS-`ANALOG_PADS)*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ // 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in_3v3;
+
+ // 18 direct connections to GPIO for low-frequency, low-voltage analog
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_analog;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_noesd;
+
+ // 3 power supply ESD clamps for user applications
+ wire [2:0] user_clamp_high;
+ wire [2:0] user_clamp_low;
+
+ // 11 core connections to the analog pads
+ wire [`ANALOG_PADS-1:0] user_analog;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_strobe;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_nc; /* no-connects */
+ wire [4:0] mgmt_io_out; /* three-pin interface out */
+ wire [4:0] mgmt_io_oeb; /* three-pin output enable */
+ wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ // Flash SPI communication (managment SoC to housekeeping)
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
+ // Flash SPI communication
+ wire flash_clk_frame;
+ wire flash_csb_frame;
+ wire flash_clk_oeb, flash_csb_oeb;
+ wire flash_clk_ieb, flash_csb_ieb;
+ wire flash_io0_oeb, flash_io1_oeb;
+ wire flash_io0_ieb, flash_io1_ieb;
+ wire flash_io0_do, flash_io1_do;
+ wire flash_io0_di, flash_io1_di;
+
+ chip_io_alt #(
+ .ANALOG_PADS_1(`ANALOG_PADS_1),
+ .ANALOG_PADS_2(`ANALOG_PADS_2)
+ ) padframe (
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_frame),
+ .flash_clk_core(flash_clk_frame),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io1_di_core(flash_io1_di),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_in_3v3(mprj_io_in_3v3),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_gpio_analog(user_gpio_analog),
+ .mprj_gpio_noesd(user_gpio_noesd),
+ .mprj_analog(user_analog),
+ .mprj_clamp_high(user_clamp_high),
+ .mprj_clamp_low(user_clamp_low)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ wire [7:0] spi_ro_config_core;
+
+ // LA signals
+ wire [127:0] la_data_in_user; // From CPU to MPRJ
+ wire [127:0] la_data_in_mprj; // From MPRJ to CPU
+ wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+ wire [127:0] la_data_out_user; // From MPRJ to CPU
+ wire [127:0] la_oenb_user; // From CPU to MPRJ
+ wire [127:0] la_oenb_mprj; // From CPU to MPRJ
+ wire [127:0] la_iena_mprj; // From CPU only
+
+ wire [2:0] user_irq; // From MPRJ to CPU
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+ wire [2:0] irq_spi; // From SPI and external pins
+
+ // Exported Wishbone Bus (processor facing)
+ wire mprj_cyc_o_core;
+ wire mprj_stb_o_core;
+ wire mprj_we_o_core;
+ wire [3:0] mprj_sel_o_core;
+ wire [31:0] mprj_adr_o_core;
+ wire [31:0] mprj_dat_o_core;
+ wire mprj_ack_i_core;
+ wire [31:0] mprj_dat_i_core;
+
+ wire [31:0] hk_dat_i;
+ wire hk_ack_i;
+ wire hk_stb_o;
+ wire hk_cyc_o;
+
+ // Exported Wishbone Bus (user area facing)
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire mprj_ack_i_user;
+ wire [31:0] mprj_dat_i_user;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+
+ // Power monitoring
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // SRAM read-noly access from housekeeping
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire [7:0] hkspi_sram_addr;
+ wire [31:0] hkspi_sram_data;
+
+ // Management processor (wrapper). Any management core
+ // implementation must match this pinout.
+
+ mgmt_core_wrapper soc (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ // Clocks and reset
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+
+ // Exported Wishbone Bus
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .mprj_sel_o(mprj_sel_o_core),
+ .mprj_adr_o(mprj_adr_o_core),
+ .mprj_dat_o(mprj_dat_o_core),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_dat_i(mprj_dat_i_core),
+
+ .hk_stb_o(hk_stb_o),
+ .hk_cyc_o(hk_cyc_o),
+ .hk_dat_i(hk_dat_i),
+ .hk_ack_i(hk_ack_i),
+
+ // IRQ
+ .irq({irq_spi, user_irq}),
+
+ // Module status (these may or may not be implemented)
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ // Module I/O (these may or may not be implemented)
+ // UART
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+ // SPI master
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ // Debug
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+ // Logic analyzer
+ .la_input(la_data_in_mprj),
+ .la_output(la_data_out_mprj),
+ .la_oenb(la_oenb_mprj),
+ .la_iena(la_iena_mprj),
+
+ // SRAM Read-only access from housekeeping
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ // Trap status
+ .trap(trap)
+ );
+
+ /* Clock and reset to user space are passed through a tristate */
+ /* buffer like the above, but since they are intended to be */
+ /* always active, connect the enable to the logic-1 output from */
+ /* the vccd1 domain. */
+
+ mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ .vccd2(vccd2_core),
+ .vssd2(vssd2_core),
+ .vdda1(vdda1_core),
+ .vssa1(vssa1_core),
+ .vdda2(vdda2_core),
+ .vssa2(vssa2_core),
+ `endif
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+ .mprj_dat_i_core(mprj_dat_i_core),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .user_irq_core(user_irq_core),
+ .la_data_out_core(la_data_out_user),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core(la_data_in_user),
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_oenb_core(la_oenb_user),
+ .la_iena_mprj(la_iena_mprj),
+ .user_irq_ena(user_irq_ena),
+
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_reset(mprj_reset),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user(mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+ .mprj_dat_i_user(mprj_dat_i_user),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .user_irq(user_irq),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood)
+ );
+
+
+ /*--------------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*--------------------------------------------------*/
+
+ assign user_io_in_3v3 = mprj_io_in_3v3;
+
+ user_analog_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+
+ // MGMT SoC Wishbone Slave
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user),
+ .wbs_sel_i(mprj_sel_o_user),
+ .wbs_adr_i(mprj_adr_o_user),
+ .wbs_dat_i(mprj_dat_o_user),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_dat_o(mprj_dat_i_user),
+
+ // GPIO pad 3-pin interface (plus analog)
+ .io_in (user_io_in),
+ .io_in_3v3 (user_io_in_3v3),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .io_analog(user_analog),
+ .gpio_analog(user_gpio_analog),
+ .gpio_noesd(user_gpio_noesd),
+
+ // Logic Analyzer
+ .la_data_in(la_data_in_user),
+ .la_data_out(la_data_out_user),
+ .la_oenb(la_oenb_user),
+
+ // User-accessible power supply clamps
+ .io_clamp_high(user_clamp_high),
+ .io_clamp_low(user_clamp_low),
+
+ // Independent clock
+ .user_clock2(mprj_clock2),
+
+ // IRQ
+ .user_irq(user_irq_core)
+ );
+
+ /*--------------------------------------*/
+ /* End user project instantiation */
+ /*--------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1
+ -`ANALOG_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2
+ -`ANALOG_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+ wire [`MPRJ_IO_PADS_1-6:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-7:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-6:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-7:0] gpio_resetn_2_shifted;
+ wire [`MPRJ_IO_PADS_1-6:0] gpio_load_1_shifted;
+ wire [`MPRJ_IO_PADS_2-7:0] gpio_load_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
+ assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
+ mprj_io_loader_strobe};
+ assign gpio_load_2_shifted = {mprj_io_loader_strobe,
+ gpio_load_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
+
+ wire [2:0] spi_pll_sel;
+ wire [2:0] spi_pll90_sel;
+ wire [4:0] spi_pll_div;
+ wire [25:0] spi_pll_trim;
+
+ // Clocking control
+
+ caravel_clocking clocking(
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .ext_clk_sel(ext_clk_sel),
+ .ext_clk(clock_core),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l),
+ .sel(spi_pll_sel),
+ .sel2(spi_pll90_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .resetb_sync(caravel_rstn)
+ );
+
+ // DCO/Digital Locked Loop
+
+ digital_pll pll (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .resetb(rstb_l),
+ .enable(spi_pll_ena),
+ .osc(clock_core),
+ .clockp({pll_clk, pll_clk90}),
+ .div(spi_pll_div),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
+ );
+
+ // Housekeeping interface
+
+ housekeeping housekeeping (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ .wb_clk_i(caravel_clk),
+ .wb_rstn_i(caravel_rstn),
+
+ .wb_adr_i(mprj_adr_o_core),
+ .wb_dat_i(mprj_dat_o_core),
+ .wb_sel_i(mprj_sel_o_core),
+ .wb_we_i(mprj_we_o_core),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_stb_i(hk_stb_o),
+ .wb_ack_o(hk_ack_i),
+ .wb_dat_o(hk_dat_i),
+
+ .porb(porb_l),
+
+ .pll_ena(spi_pll_ena),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div(spi_pll_div),
+ .pll_sel(spi_pll_sel),
+ .pll90_sel(spi_pll90_sel),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ .irq(irq_spi),
+ .reset(ext_reset),
+
+ .serial_clock(mprj_io_loader_clock),
+ .serial_load(mprj_io_loader_strobe),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_1(mprj_io_loader_data_1),
+ .serial_data_2(mprj_io_loader_data_2),
+
+ .mgmt_gpio_in(mgmt_io_in),
+ .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
+ mgmt_io_out[1:0]}),
+ .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
+ mgmt_io_oeb[1:0]}),
+
+ .pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
+
+ .trap(trap),
+
+ .user_clock(caravel_clk2),
+
+ .mask_rev_in(mask_rev),
+
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io1_di(flash_io1_di),
+
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+ );
+
+ /* GPIO defaults (via programmed) */
+ wire [(`MPRJ_IO_PADS - `ANALOG_PADS)*13-1:0] gpio_defaults;
+
+ /* Fixed defaults for the first 5 GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_defaults_block_0 [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[25:0])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_defaults_block_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[64:26])
+ );
+
+ /* Via-programmable defaults for the rest of the GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+ ) gpio_defaults_block_5 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[77:65])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+ ) gpio_defaults_block_6 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[90:78])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+ ) gpio_defaults_block_7 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[103:91])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+ ) gpio_defaults_block_8 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[116:104])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+ ) gpio_defaults_block_9 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[129:117])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+ ) gpio_defaults_block_10 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[142:130])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+ ) gpio_defaults_block_11 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[155:143])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+ ) gpio_defaults_block_12 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[168:156])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+ ) gpio_defaults_block_13 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[181:169])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+ ) gpio_defaults_block_14 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[194:182])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+ ) gpio_defaults_block_26 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[207:195])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+ ) gpio_defaults_block_27 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[220:208])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+ ) gpio_defaults_block_28 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[233:221])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+ ) gpio_defaults_block_29 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[246:234])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+ ) gpio_defaults_block_30 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[259:247])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+ ) gpio_defaults_block_31 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[272:260])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+ ) gpio_defaults_block_32 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[285:273])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+ ) gpio_defaults_block_33 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[298:286])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+ ) gpio_defaults_block_34 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[311:299])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+ ) gpio_defaults_block_35 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[324:312])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+ ) gpio_defaults_block_36 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[337:325])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+ ) gpio_defaults_block_37 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[350:338])
+ );
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+ gpio_control_block gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[25:0]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+ .serial_load(gpio_load_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+ .serial_load_out(gpio_load_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out({sdo_out, jtag_out}),
+ .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1;
+
+ /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+ gpio_control_block gpio_control_in_1a [5:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[103:26]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[7:2]),
+ .serial_clock(gpio_clock_1_shifted[7:2]),
+ .serial_load(gpio_load_1_shifted[7:2]),
+
+ .resetn_out(gpio_resetn_1[7:2]),
+ .serial_clock_out(gpio_clock_1[7:2]),
+ .serial_load_out(gpio_load_1[7:2]),
+
+ .mgmt_gpio_in(mgmt_io_in[7:2]),
+ .mgmt_gpio_out(mgmt_io_in[7:2]),
+ .mgmt_gpio_oeb(one_loop1[5:0]),
+
+ .one(one_loop1[5:0]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[7:2]),
+ .serial_data_out(gpio_serial_link_1[7:2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[7:2]),
+ .user_gpio_oeb(user_io_oeb[7:2]),
+ .user_gpio_in(user_io_in[7:2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+ .pad_gpio_holdover(mprj_io_holdover[7:2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+ .pad_gpio_dm(mprj_io_dm[23:6]),
+ .pad_gpio_outenb(mprj_io_oeb[7:2]),
+ .pad_gpio_out(mprj_io_out[7:2]),
+ .pad_gpio_in(mprj_io_in[7:2])
+ );
+
+ /* Section 1 GPIOs (GPIO 8 to 18) */
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-9:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13-1):104]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ .mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]),
+ .mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]),
+ .mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
+
+ .one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3-1:24]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8])
+ );
+
+ /* Last three GPIOs (spi_sdo, flash_io2 and flash_io3) */
+
+ gpio_control_block gpio_control_bidir_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS)*13-1):((`MPRJ_IO_PADS-`ANALOG_PADS)*13-39)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP):(`DIG2_TOP-2)]),
+ .mgmt_gpio_out(mgmt_io_out[4:2]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_DIG_PADS*3-1):(`MPRJ_DIG_PADS*3-9)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 37) */
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] one_loop2;
+
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS-3)*13-1):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
+ .mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-3):`DIG2_BOT]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-4):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[((`MPRJ_DIG_PADS)*3-10):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-4):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss3v3(vssio_core),
+ .vss1v8(vssd_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ xres_buf rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .LVGND(vssd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+ // Spare logic for metal mask fixes
+ wire [107:0] spare_xz_nc;
+ wire [15:0] spare_xi_nc;
+ wire [3:0] spare_xib_nc;
+ wire [7:0] spare_xna_nc;
+ wire [7:0] spare_xno_nc;
+ wire [7:0] spare_xmx_nc;
+ wire [7:0] spare_xfq_nc;
+ wire [7:0] spare_xfqn_nc;
+
+ spare_logic_block spare_logic [3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ `endif
+ .spare_xz(spare_xz_nc),
+ .spare_xi(spare_xi_nc),
+ .spare_xib(spare_xib_nc),
+ .spare_xna(spare_xna_nc),
+ .spare_xno(spare_xno_nc),
+ .spare_xmx(spare_xmx_nc),
+ .spare_xfq(spare_xfq_nc),
+ .spare_xfqn(spare_xfqn_nc)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/caravan_netlists.v b/caravel/verilog/rtl/caravan_netlists.v
new file mode 100644
index 0000000..5760b26
--- /dev/null
+++ b/caravel/verilog/rtl/caravan_netlists.v
@@ -0,0 +1,96 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`ifdef SIM
+
+ `include "defines.v"
+ `include "user_defines.v"
+ `include "pads.v"
+
+ /* NOTE: Need to pass the PDK root directory to iverilog with option -I */
+ `ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
+ `include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
+ `include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
+
+ `include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
+ `include "libs.ref/verilog/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `else
+ `include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+ `include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `endif
+
+ `ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire
+ // definitions
+ `default_nettype wire
+ `include "gl/digital_pll.v"
+ `include "gl/caravel_clocking.v"
+ `include "gl/user_id_programming.v"
+ `include "gl/chip_io_alt.v"
+ `include "gl/housekeeping.v"
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+ `include "gl/gpio_control_block.v"
+ `include "gl/gpio_defaults_block.v"
+ `include "gl/gpio_defaults_block_0403.v"
+ `include "gl/gpio_defaults_block_1803.v"
+ `include "gl/gpio_logic_high.v"
+ `include "gl/xres_buf.v"
+ `include "gl/spare_logic_block.v"
+ `include "gl/mgmt_core_wrapper.v"
+ `include "gl/caravan.v"
+ `else
+ `include "digital_pll.v"
+ `include "digital_pll_controller.v"
+ `include "ring_osc2x13.v"
+ `include "caravel_clocking.v"
+ `include "user_id_programming.v"
+ `include "clock_div.v"
+ `include "mprj_io.v"
+ `include "chip_io_alt.v"
+ `include "housekeeping_spi.v"
+ `include "housekeeping.v"
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+ `include "gpio_control_block.v"
+ `include "gpio_defaults_block.v"
+ `include "gpio_logic_high.v"
+ `include "xres_buf.v"
+ `include "spare_logic_block.v"
+ `include "mgmt_core_wrapper.v"
+ `include "caravan.v"
+ `endif
+
+ `include "simple_por.v"
+
+`endif
diff --git a/caravel/verilog/rtl/caravan_openframe.v b/caravel/verilog/rtl/caravan_openframe.v
new file mode 100644
index 0000000..5131789
--- /dev/null
+++ b/caravel/verilog/rtl/caravan_openframe.v
@@ -0,0 +1,1231 @@
+// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravan_openframe, a project harness for the Google/SkyWater */
+/* sky130 fabrication process and open source PDK. caravan is */
+/* an alternative architecture to caravel that has simple */
+/* straight through connections replacing the GPIO pads on the */
+/* top side of the padframe. A total of 11 pads are converted */
+/* from GPIO to analog, leaving 27 GPIO. */
+/* */
+/* Copyright 2021 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+/*--------------------------------------------------------------*/
+/* Derived types for the array bounds on the two digital and */
+/* two analog pad arrays. As defined above, the sections have */
+/* the number of pads as follows: */
+/* */
+/* DIG2 : 13 GPIO pads */
+/* ANA2 : 6 analog pads */
+/* ANA1 : 5 analog pads */
+/* DIG1 : 14 GPIO pads */
+/* */
+/* This makes a total of 38 pads = `MPRJ_IO_PADS */
+/* The pads are still designated as mprj_io[37:0] around the */
+/* padframe. The SoC core remains the same, so the programming */
+/* of the digital signals remains the same, but the values for */
+/* GPIO 15-25 are not used. */
+/*--------------------------------------------------------------*/
+
+`define DIG2_TOP (`MPRJ_IO_PADS - 1)
+`define DIG2_BOT (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2)
+`define ANA2_TOP (`MPRJ_IO_PADS_1 + `ANALOG_PADS_2 - 1)
+`define ANA2_BOT (`MPRJ_IO_PADS_1)
+`define ANA1_TOP (`MPRJ_IO_PADS_1 - 1)
+`define ANA1_BOT (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1)
+`define DIG1_TOP (`MPRJ_IO_PADS_1 - `ANALOG_PADS_1 - 1)
+`define DIG1_BOT (0)
+
+`define MPRJ_DIG_PADS (`MPRJ_IO_PADS - `ANALOG_PADS)
+
+/*--------------------------------------------------------------*/
+/*--------------------------------------------------------------*/
+
+module caravan_openframe (
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb,
+
+ // Note that only two pins are available on the flash so dual and
+ // quad flash modes are not available.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00000000;
+
+ /*
+ *---------------------------------------------------------------------
+ * These pins are overlaid on mprj_io space. They have the function
+ * below when the management processor is in reset, or in the default
+ * configuration. They are assigned to uses in the user space by the
+ * configuration program running off of the SPI flash. Note that even
+ * when the user has taken control of these pins, they can be restored
+ * to the original use by setting the resetb pin low. The SPI pins and
+ * UART pins can be connected directly to an FTDI chip as long as the
+ * FTDI chip sets these lines to high impedence (input function) at
+ * all times except when holding the chip in reset.
+ *
+ * JTAG = mprj_io[0] (inout)
+ * SDO = mprj_io[1] (output)
+ * SDI = mprj_io[2] (input)
+ * CSB = mprj_io[3] (input)
+ * SCK = mprj_io[4] (input)
+ * ser_rx = mprj_io[5] (input)
+ * ser_tx = mprj_io[6] (output)
+ * irq = mprj_io[7] (input)
+ *
+ * spi_sck = mprj_io[32] (output)
+ * spi_csb = mprj_io[33] (output)
+ * spi_sdi = mprj_io[34] (input)
+ * spi_sdo = mprj_io[35] (output)
+ * flash_io2 = mprj_io[36] (inout)
+ * flash_io3 = mprj_io[37] (inout)
+ *
+ * These pins are reserved for any project that wants to incorporate
+ * its own processor and flash controller. While a user project can
+ * technically use any available I/O pins for the purpose, these
+ * four pins connect to a pass-through mode from the SPI slave (pins
+ * 1-4 above) so that any SPI flash connected to these specific pins
+ * can be accessed through the SPI slave even when the processor is in
+ * reset.
+ *
+ * user_flash_csb = mprj_io[8]
+ * user_flash_sck = mprj_io[9]
+ * user_flash_io0 = mprj_io[10]
+ * user_flash_io1 = mprj_io[11]
+ *
+ *---------------------------------------------------------------------
+ */
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // 27 GPIO pads with full controls
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_pol;
+ wire [(`MPRJ_IO_PADS-`ANALOG_PADS)*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ // 27 GPIO bidirectional with in/out/oeb and a 3.3V copy of the input
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in_3v3;
+
+ // 18 direct connections to GPIO for low-frequency, low-voltage analog
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_analog;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_noesd;
+
+ // 3 power supply ESD clamps for user applications
+ wire [2:0] user_clamp_high;
+ wire [2:0] user_clamp_low;
+
+ // 11 core connections to the analog pads
+ wire [`ANALOG_PADS-1:0] user_analog;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_nc; /* no-connects */
+ wire [4:0] mgmt_io_out; /* three-pin interface out */
+ wire [4:0] mgmt_io_oeb; /* three-pin output enable */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ // Flash SPI communication (managment SoC to housekeeping)
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
+ // Flash SPI communication
+ wire flash_clk_frame;
+ wire flash_csb_frame;
+ wire flash_clk_oeb, flash_csb_oeb;
+ wire flash_clk_ieb, flash_csb_ieb;
+ wire flash_io0_oeb, flash_io1_oeb;
+ wire flash_io0_ieb, flash_io1_ieb;
+ wire flash_io0_do, flash_io1_do;
+ wire flash_io0_di, flash_io1_di;
+
+ chip_io_alt #(
+ .ANALOG_PADS_1(`ANALOG_PADS_1),
+ .ANALOG_PADS_2(`ANALOG_PADS_2)
+ ) padframe (
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_frame),
+ .flash_clk_core(flash_clk_frame),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io1_di_core(flash_io1_di),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_in_3v3(mprj_io_in_3v3),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_gpio_analog(user_gpio_analog),
+ .mprj_gpio_noesd(user_gpio_noesd),
+ .mprj_analog(user_analog),
+ .mprj_clamp_high(user_clamp_high),
+ .mprj_clamp_low(user_clamp_low)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ wire [7:0] spi_ro_config_core;
+
+ wire [2:0] irq_spi; // From SPI and external pins
+
+ // Exported Wishbone Bus (processor facing)
+ wire mprj_cyc_o;
+ wire mprj_stb_o;
+ wire mprj_we_o;
+ wire [3:0] mprj_sel_o;
+ wire [31:0] mprj_adr_o;
+ wire [31:0] mprj_dat_o;
+ wire mprj_ack_i;
+ wire [31:0] mprj_dat_i;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ // Clock and reset
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+
+ // Power monitoring
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // SRAM read-noly access from housekeeping
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire [7:0] hkspi_sram_addr;
+ wire [31:0] hkspi_sram_data;
+
+ assign user_io_in_3v3 = mprj_io_in_3v3;
+
+ /*--------------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*--------------------------------------------------*/
+
+ mgmt_core_wrapper soc (
+ `ifdef USE_POWER_PINS
+ .vdda(vdda_core),
+ .vssa(vssa_core),
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ // Clocks and reset
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+ .core_clock2(mprj_clock2),
+
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+
+ // GPIO pad 3-pin interface (plus analog)
+ .io_in (user_io_in),
+ .io_in_3v3 (user_io_in_3v3),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .gpio_analog(user_gpio_analog),
+ .gpio_noesd(user_gpio_noesd),
+ .io_analog(user_analog),
+
+ // User-accessible power supply clamps
+ .io_clamp_high(user_clamp_high),
+ .io_clamp_low(user_clamp_low),
+
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+
+ // Exported Wishbone Bus
+ .mprj_cyc_o(mprj_cyc_o),
+ .mprj_stb_o(mprj_stb_o),
+ .mprj_we_o(mprj_we_o),
+ .mprj_sel_o(mprj_sel_o),
+ .mprj_adr_o(mprj_adr_o),
+ .mprj_dat_o(mprj_dat_o),
+ .mprj_ack_i(mprj_ack_i),
+ .mprj_dat_i(mprj_dat_i),
+
+ // IRQ
+ .irq(irq_spi),
+
+ // Module status (these may or may not be implemented)
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ // Module I/O (these may or may not be implemented)
+ // UART
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+ // SPI master
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ // Debug
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ // SRAM Read-only access from housekeeping
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ // Trap status
+ .trap(trap)
+ );
+
+ /*--------------------------------------*/
+ /* End user project instantiation */
+ /*--------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1
+ -`ANALOG_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2
+ -`ANALOG_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-6:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-7:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-6:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-7:0] gpio_resetn_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
+
+ wire [2:0] spi_pll_sel;
+ wire [2:0] spi_pll90_sel;
+ wire [4:0] spi_pll_div;
+ wire [25:0] spi_pll_trim;
+
+ // Clocking control
+
+ caravel_clocking clocking(
+ `ifdef USE_POWER_PINS
+ .vdd1v8(VPWR),
+ .vss(VGND),
+ `endif
+ .ext_clk_sel(ext_clk_sel),
+ .ext_clk(clock),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(resetb),
+ .sel(spi_pll_sel),
+ .sel2(spi_pll90_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .resetb_sync(caravel_rstn)
+ );
+
+ // DCO/Digital Locked Loop
+
+ digital_pll pll (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .resetb(resetb),
+ .enable(spi_pll_ena),
+ .osc(clock),
+ .clockp({pll_clk, pll_clk90}),
+ .div(spi_pll_div),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
+ );
+
+ // Housekeeping interface
+
+ housekeeping housekeeping (
+ `ifdef USE_POWER_PINS
+ .vdd(VPWR),
+ .vss(VGND),
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+
+ .wb_adr_i(mprj_adr_o),
+ .wb_dat_i(mprj_dat_o),
+ .wb_sel_i(mprj_sel_o),
+ .wb_we_i(mprj_we_o),
+ .wb_cyc_i(mprj_cyc_o),
+ .wb_stb_i(mprj_stb_o),
+ .wb_ack_o(mprj_ack_i),
+ .wb_dat_o(mprj_dat_i),
+
+ .porb(porb_l),
+
+ .pll_ena(spi_pll_ena),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div(spi_pll_div),
+ .pll_sel(spi_pll_sel),
+ .pll90_sel(spi_pll90_sel),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ .irq(irq_spi),
+ .reset(ext_reset),
+
+ .serial_clock(mprj_io_loader_clock),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_1(mprj_io_loader_data_1),
+ .serial_data_2(mprj_io_loader_data_2),
+
+ .mgmt_gpio_in(mgmt_io_in),
+ .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
+ mgmt_io_out[1:0]}),
+ .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
+ mgmt_io_oeb[1:0]}),
+
+ .pwr_ctrl_out(), /* Not used in this version */
+
+ .trap(trap),
+
+ .user_clock(user_clock),
+
+ .mask_rev_in(mask_rev),
+
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io1_di(flash_io1_di),
+
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+ );
+
+ /* GPIO defaults (via programmed) */
+ wire [(`MPRJ_IO_PADS - `ANALOG_PADS)*13-1:0] gpio_defaults;
+
+ /* Fixed defaults for the first 5 GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_01_defaults [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[25:0])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_234_defaults [2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[64:26])
+ );
+
+ /* Via-programmable defaults for the rest of the GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+ ) gpio_5_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[77:65])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+ ) gpio_6_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[90:78])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+ ) gpio_7_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[103:91])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+ ) gpio_8_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[116:104])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+ ) gpio_9_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[129:117])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+ ) gpio_10_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[142:130])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+ ) gpio_11_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[155:143])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+ ) gpio_12_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[168:156])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+ ) gpio_13_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[181:169])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+ ) gpio_14_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[194:182])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+ ) gpio_26_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[207:195])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+ ) gpio_27_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[220:208])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+ ) gpio_28_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[233:221])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+ ) gpio_29_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[246:234])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+ ) gpio_30_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[259:247])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+ ) gpio_31_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[272:260])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+ ) gpio_32_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[285:273])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+ ) gpio_33_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[298:286])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+ ) gpio_34_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[311:299])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+ ) gpio_35_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[324:312])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+ ) gpio_36_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[337:325])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+ ) gpio_37_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[350:338])
+ );
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+ gpio_control_block gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[25:0]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out({sdo_out, jtag_out}),
+ .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:0] one_loop1;
+
+ /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+ gpio_control_block gpio_control_in_1a [5:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[103:26]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[7:2]),
+ .serial_clock(gpio_clock_1_shifted[7:2]),
+
+ .resetn_out(gpio_resetn_1[7:2]),
+ .serial_clock_out(gpio_clock_1[7:2]),
+
+ .mgmt_gpio_in(mgmt_io_in[7:2]),
+ .mgmt_gpio_out(mgmt_io_in[7:2]),
+ .mgmt_gpio_oeb(one_loop1[5:0]),
+
+ .one(one_loop1[5:0]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[7:2]),
+ .serial_data_out(gpio_serial_link_1[7:2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[7:2]),
+ .user_gpio_oeb(user_io_oeb[7:2]),
+ .user_gpio_in(user_io_in[7:2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+ .pad_gpio_holdover(mprj_io_holdover[7:2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+ .pad_gpio_dm(mprj_io_dm[23:6]),
+ .pad_gpio_outenb(mprj_io_oeb[7:2]),
+ .pad_gpio_out(mprj_io_out[7:2]),
+ .pad_gpio_in(mprj_io_in[7:2])
+ );
+
+ /* Section 1 GPIOs (GPIO 8 to 18) */
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-9:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13-1):104]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ .mgmt_gpio_in(mgmt_io_in[`DIG1_TOP:8]),
+ .mgmt_gpio_out(mgmt_io_in[`DIG1_TOP:8]),
+ .mgmt_gpio_oeb(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
+
+ .one(one_loop1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-3:6]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3-1:24]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1):8])
+ );
+
+ /* Last three GPIOs (spi_sdo, flash_io2 and flash_io3) */
+
+ gpio_control_block gpio_control_bidir_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS)*13-1):((`MPRJ_IO_PADS-`ANALOG_PADS)*13-39)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP):(`DIG2_TOP-2)]),
+ .mgmt_gpio_out(mgmt_io_out[4:2]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1):(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_DIG_PADS*3-1):(`MPRJ_DIG_PADS*3-9)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-1):(`MPRJ_DIG_PADS-3)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 37) */
+ wire [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3:0] one_loop2;
+
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[((`MPRJ_IO_PADS-`ANALOG_PADS-2)*13-1):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*13)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`DIG2_TOP-2):`DIG2_BOT]),
+ .mgmt_gpio_out(mgmt_io_in[(`DIG2_TOP-2):`DIG2_BOT]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-`ANALOG_PADS_2-3):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[((`MPRJ_DIG_PADS)*3-7):((`MPRJ_IO_PADS_1-`ANALOG_PADS_1)*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_DIG_PADS-3):(`MPRJ_IO_PADS_1-`ANALOG_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss(vssio_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ xres_buf rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .LVGND(vssd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/caravel.v b/caravel/verilog/rtl/caravel.v
new file mode 100644
index 0000000..3b6b9bb
--- /dev/null
+++ b/caravel/verilog/rtl/caravel.v
@@ -0,0 +1,1459 @@
+ `ifdef SIM
+ `default_nettype wire
+ `endif
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/* Updated 10/15/2021: Revised using the housekeeping module */
+/* from housekeeping.v (refactoring a number of functions from */
+/* the management SoC). */
+/* */
+/*--------------------------------------------------------------*/
+
+module caravel (
+
+ // All top-level I/O are package-facing pins
+
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb, // Reset input (sense inverted)
+
+ // Note that only two flash data pins are dedicated to the
+ // management SoC wrapper. The management SoC exports the
+ // quad SPI mode status to make use of the top two mprj_io
+ // pins for io2 and io3.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00000000;
+
+ /*
+ *--------------------------------------------------------------------
+ *
+ * These pins are overlaid on mprj_io space. They have the function
+ * below when the management processor is in reset, or in the default
+ * configuration. They are assigned to uses in the user space by the
+ * configuration program running off of the SPI flash. Note that even
+ * when the user has taken control of these pins, they can be restored
+ * to the original use by setting the resetb pin low. The SPI pins and
+ * UART pins can be connected directly to an FTDI chip as long as the
+ * FTDI chip sets these lines to high impedence (input function) at
+ * all times except when holding the chip in reset.
+ *
+ * JTAG = mprj_io[0] (inout)
+ * SDO = mprj_io[1] (output)
+ * SDI = mprj_io[2] (input)
+ * CSB = mprj_io[3] (input)
+ * SCK = mprj_io[4] (input)
+ * ser_rx = mprj_io[5] (input)
+ * ser_tx = mprj_io[6] (output)
+ * irq = mprj_io[7] (input)
+ *
+ * spi_sck = mprj_io[32] (output)
+ * spi_csb = mprj_io[33] (output)
+ * spi_sdi = mprj_io[34] (input)
+ * spi_sdo = mprj_io[35] (output)
+ * flash_io2 = mprj_io[36] (inout)
+ * flash_io3 = mprj_io[37] (inout)
+ *
+ * These pins are reserved for any project that wants to incorporate
+ * its own processor and flash controller. While a user project can
+ * technically use any available I/O pins for the purpose, these
+ * four pins connect to a pass-through mode from the SPI slave (pins
+ * 1-4 above) so that any SPI flash connected to these specific pins
+ * can be accessed through the SPI slave even when the processor is in
+ * reset.
+ *
+ * user_flash_csb = mprj_io[8]
+ * user_flash_sck = mprj_io[9]
+ * user_flash_io0 = mprj_io[10]
+ * user_flash_io1 = mprj_io[11]
+ *
+ *--------------------------------------------------------------------
+ */
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // User Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_strobe;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
+ wire [`MPRJ_IO_PADS-5:0] mgmt_io_nc; /* no-connects */
+ wire [4:0] mgmt_io_out; /* three-pin interface out */
+ wire [4:0] mgmt_io_oeb; /* three-pin output enable */
+ wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ // Flash SPI communication (management SoC to housekeeping)
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
+ // Flash SPI communication (
+ wire flash_clk_frame;
+ wire flash_csb_frame;
+ wire flash_clk_oeb, flash_csb_oeb;
+ wire flash_clk_ieb, flash_csb_ieb;
+ wire flash_io0_oeb, flash_io1_oeb;
+ wire flash_io0_ieb, flash_io1_ieb;
+ wire flash_io0_do, flash_io1_do;
+ wire flash_io0_di, flash_io1_di;
+
+ chip_io padframe(
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_frame),
+ .flash_clk_core(flash_clk_frame),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io1_di_core(flash_io1_di),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ // Logic analyzer signals
+ wire [127:0] la_data_in_user; // From CPU to MPRJ
+ wire [127:0] la_data_in_mprj; // From MPRJ to CPU
+ wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+ wire [127:0] la_data_out_user; // From MPRJ to CPU
+ wire [127:0] la_oenb_user; // From CPU to MPRJ
+ wire [127:0] la_oenb_mprj; // From CPU to MPRJ
+ wire [127:0] la_iena_mprj; // From CPU only
+
+ wire [2:0] user_irq; // From MRPJ to CPU
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+ wire [2:0] irq_spi; // From SPI and external pins
+
+ // Exported Wishbone Bus (processor facing)
+ wire mprj_iena_wb;
+ wire mprj_cyc_o_core;
+ wire mprj_stb_o_core;
+ wire mprj_we_o_core;
+ wire [3:0] mprj_sel_o_core;
+ wire [31:0] mprj_adr_o_core;
+ wire [31:0] mprj_dat_o_core;
+ wire mprj_ack_i_core;
+ wire [31:0] mprj_dat_i_core;
+
+ wire [31:0] hk_dat_i;
+ wire hk_ack_i;
+ wire hk_stb_o;
+ wire hk_cyc_o;
+
+ // Exported Wishbone Bus (user area facing)
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire [31:0] mprj_dat_i_user;
+ wire mprj_ack_i_user;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+
+ // Power monitoring
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // SRAM read-only access from houskeeping
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire [7:0] hkspi_sram_addr;
+ wire [31:0] hkspi_sram_data;
+
+ // Management processor (wrapper). Any management core
+ // implementation must match this pinout.
+
+ mgmt_core_wrapper soc (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ // Clock and reset
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+
+ // Exported Wishbone Bus
+ .mprj_wb_iena(mprj_iena_wb),
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .mprj_sel_o(mprj_sel_o_core),
+ .mprj_adr_o(mprj_adr_o_core),
+ .mprj_dat_o(mprj_dat_o_core),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_dat_i(mprj_dat_i_core),
+
+ .hk_stb_o(hk_stb_o),
+ .hk_cyc_o(hk_cyc_o),
+ .hk_dat_i(hk_dat_i),
+ .hk_ack_i(hk_ack_i),
+
+ // IRQ
+ .irq({irq_spi, user_irq}),
+ .user_irq_ena(user_irq_ena),
+
+ // Module status (these may or may not be implemented)
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ // Module I/O (these may or may not be implemented)
+ // UART
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+ // SPI master
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ // Debug
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+ // Logic analyzer
+ .la_input(la_data_in_mprj),
+ .la_output(la_data_out_mprj),
+ .la_oenb(la_oenb_mprj),
+ .la_iena(la_iena_mprj),
+
+ // SRAM Read-only access from housekeeping
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ // Trap status
+ .trap(trap)
+ );
+
+ /* Clock and reset to user space are passed through a tristate */
+ /* buffer like the above, but since they are intended to be */
+ /* always active, connect the enable to the logic-1 output from */
+ /* the vccd1 domain. */
+
+ mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ .vccd2(vccd2_core),
+ .vssd2(vssd2_core),
+ .vdda1(vdda1_core),
+ .vssa1(vssa1_core),
+ .vdda2(vdda2_core),
+ .vssa2(vssa2_core),
+ `endif
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .mprj_dat_i_core(mprj_dat_i_core),
+ .user_irq_core(user_irq_core),
+ .user_irq_ena(user_irq_ena),
+ .la_data_out_core(la_data_out_user),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core(la_data_in_user),
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_oenb_core(la_oenb_user),
+ .la_iena_mprj(la_iena_mprj),
+
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_reset(mprj_reset),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user(mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+ .mprj_dat_i_user(mprj_dat_i_user),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .user_irq(user_irq),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood)
+ );
+
+ /*--------------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*--------------------------------------------------*/
+
+ user_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+
+ // Management SoC Wishbone bus (exported)
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user),
+ .wbs_sel_i(mprj_sel_o_user),
+ .wbs_adr_i(mprj_adr_o_user),
+ .wbs_dat_i(mprj_dat_o_user),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_dat_o(mprj_dat_i_user),
+
+ // GPIO pad 3-pin interface (plus analog)
+ .io_in (user_io_in),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
+
+ // Logic analyzer
+ .la_data_in(la_data_in_user),
+ .la_data_out(la_data_out_user),
+ .la_oenb(la_oenb_user),
+
+ // Independent clock
+ .user_clock2(mprj_clock2),
+
+ // IRQ
+ .user_irq(user_irq_core)
+ );
+
+ /*------------------------------------------*/
+ /* End user project instantiation */
+ /*------------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_strobe};
+ assign gpio_load_2_shifted = {mprj_io_loader_strobe,
+ gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
+
+ wire [2:0] spi_pll_sel;
+ wire [2:0] spi_pll90_sel;
+ wire [4:0] spi_pll_div;
+ wire [25:0] spi_pll_trim;
+
+ // Clocking control
+
+ caravel_clocking clocking(
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .ext_clk_sel(ext_clk_sel),
+ .ext_clk(clock_core),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l),
+ .sel(spi_pll_sel),
+ .sel2(spi_pll90_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .resetb_sync(caravel_rstn)
+ );
+
+ // DCO/Digital Locked Loop
+
+ digital_pll pll (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .resetb(rstb_l),
+ .enable(spi_pll_ena),
+ .osc(clock_core),
+ .clockp({pll_clk, pll_clk90}),
+ .div(spi_pll_div),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
+ );
+
+ // Housekeeping interface
+
+ housekeeping housekeeping (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ .wb_clk_i(caravel_clk),
+ .wb_rstn_i(caravel_rstn),
+
+ .wb_adr_i(mprj_adr_o_core),
+ .wb_dat_i(mprj_dat_o_core),
+ .wb_sel_i(mprj_sel_o_core),
+ .wb_we_i(mprj_we_o_core),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_stb_i(hk_stb_o),
+ .wb_ack_o(hk_ack_i),
+ .wb_dat_o(hk_dat_i),
+
+ .porb(porb_l),
+
+ .pll_ena(spi_pll_ena),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div(spi_pll_div),
+ .pll_sel(spi_pll_sel),
+ .pll90_sel(spi_pll90_sel),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ .irq(irq_spi),
+ .reset(ext_reset),
+
+ .serial_clock(mprj_io_loader_clock),
+ .serial_load(mprj_io_loader_strobe),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_1(mprj_io_loader_data_1),
+ .serial_data_2(mprj_io_loader_data_2),
+
+ .mgmt_gpio_in(mgmt_io_in),
+ .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
+ mgmt_io_out[1:0]}),
+ .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
+ mgmt_io_oeb[1:0]}),
+
+ .pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
+
+ .trap(trap),
+
+ .user_clock(caravel_clk2),
+
+ .mask_rev_in(mask_rev),
+
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io1_di(flash_io1_di),
+
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+ );
+
+ /* GPIO defaults (via programmed) */
+ wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+ /* Fixed defaults for the first 5 GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_defaults_block_0 [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[25:0])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_defaults_block_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[64:26])
+ );
+
+ /* Via-programmable defaults for the rest of the GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+ ) gpio_defaults_block_5 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[77:65])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+ ) gpio_defaults_block_6 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[90:78])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+ ) gpio_defaults_block_7 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[103:91])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+ ) gpio_defaults_block_8 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[116:104])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+ ) gpio_defaults_block_9 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[129:117])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+ ) gpio_defaults_block_10 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[142:130])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+ ) gpio_defaults_block_11 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[155:143])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+ ) gpio_defaults_block_12 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[168:156])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+ ) gpio_defaults_block_13 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[181:169])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+ ) gpio_defaults_block_14 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[194:182])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+ ) gpio_defaults_block_15 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[207:195])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+ ) gpio_defaults_block_16 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[220:208])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+ ) gpio_defaults_block_17 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[233:221])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+ ) gpio_defaults_block_18 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[246:234])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+ ) gpio_defaults_block_19 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[259:247])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+ ) gpio_defaults_block_20 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[272:260])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+ ) gpio_defaults_block_21 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[285:273])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+ ) gpio_defaults_block_22 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[298:286])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+ ) gpio_defaults_block_23 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[311:299])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+ ) gpio_defaults_block_24 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[324:312])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+ ) gpio_defaults_block_25 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[337:325])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+ ) gpio_defaults_block_26 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[350:338])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+ ) gpio_defaults_block_27 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[363:351])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+ ) gpio_defaults_block_28 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[376:364])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+ ) gpio_defaults_block_29 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[389:377])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+ ) gpio_defaults_block_30 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[402:390])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+ ) gpio_defaults_block_31 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[415:403])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+ ) gpio_defaults_block_32 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[428:416])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+ ) gpio_defaults_block_33 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[441:429])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+ ) gpio_defaults_block_34 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[454:442])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+ ) gpio_defaults_block_35 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[467:455])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+ ) gpio_defaults_block_36 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[480:468])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+ ) gpio_defaults_block_37 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[493:481])
+ );
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+
+ gpio_control_block gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[25:0]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+ .serial_load(gpio_load_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+ .serial_load_out(gpio_load_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out(mgmt_io_out[1:0]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
+
+ /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+ gpio_control_block gpio_control_in_1a [5:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[103:26]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[7:2]),
+ .serial_clock(gpio_clock_1_shifted[7:2]),
+ .serial_load(gpio_load_1_shifted[7:2]),
+
+ .resetn_out(gpio_resetn_1[7:2]),
+ .serial_clock_out(gpio_clock_1[7:2]),
+ .serial_load_out(gpio_load_1[7:2]),
+
+ .mgmt_gpio_in(mgmt_io_in[7:2]),
+ .mgmt_gpio_out(mgmt_io_in[7:2]),
+ .mgmt_gpio_oeb(one_loop1[7:2]),
+
+ .one(one_loop1[7:2]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[7:2]),
+ .serial_data_out(gpio_serial_link_1[7:2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[7:2]),
+ .user_gpio_oeb(user_io_oeb[7:2]),
+ .user_gpio_in(user_io_in[7:2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+ .pad_gpio_holdover(mprj_io_holdover[7:2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+ .pad_gpio_dm(mprj_io_dm[23:6]),
+ .pad_gpio_outenb(mprj_io_oeb[7:2]),
+ .pad_gpio_out(mprj_io_out[7:2]),
+ .pad_gpio_in(mprj_io_in[7:2])
+ );
+
+ /* Section 1 GPIOs (GPIO 8 to 18) */
+
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+
+ .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+ );
+
+ /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+ gpio_control_block gpio_control_bidir_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .mgmt_gpio_out(mgmt_io_out[4:2]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 34) */
+ wire [`MPRJ_IO_PADS_2-4:0] one_loop2;
+
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss3v3(vssio_core),
+ .vss1v8(vssd_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ xres_buf rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .LVGND(vssd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+ // Spare logic for metal mask fixes
+ wire [107:0] spare_xz_nc;
+ wire [15:0] spare_xi_nc;
+ wire [3:0] spare_xib_nc;
+ wire [7:0] spare_xna_nc;
+ wire [7:0] spare_xno_nc;
+ wire [7:0] spare_xmx_nc;
+ wire [7:0] spare_xfq_nc;
+ wire [7:0] spare_xfqn_nc;
+
+ spare_logic_block spare_logic [3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ `endif
+ .spare_xz(spare_xz_nc),
+ .spare_xi(spare_xi_nc),
+ .spare_xib(spare_xib_nc),
+ .spare_xna(spare_xna_nc),
+ .spare_xno(spare_xno_nc),
+ .spare_xmx(spare_xmx_nc),
+ .spare_xfq(spare_xfq_nc),
+ .spare_xfqn(spare_xfqn_nc)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/caravel_clocking.v b/caravel/verilog/rtl/caravel_clocking.v
new file mode 100644
index 0000000..cd2c7aa
--- /dev/null
+++ b/caravel/verilog/rtl/caravel_clocking.v
@@ -0,0 +1,111 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// This routine synchronizes the
+
+module caravel_clocking(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input resetb, // Master (negative sense) reset
+ input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock
+ input ext_clk, // External pad (slow) clock
+ input pll_clk, // Internal PLL (fast) clock
+ input pll_clk90, // Internal PLL (fast) clock, 90 degree phase
+ input [2:0] sel, // Select clock divider value (0=thru, 1=divide-by-2, etc.)
+ input [2:0] sel2, // Select clock divider value for 90 degree phase divided clock
+ input ext_reset, // Positive sense reset from housekeeping SPI.
+ output core_clk, // Output core clock
+ output user_clk, // Output user (secondary) clock
+ output resetb_sync // Output propagated and buffered reset
+);
+
+ wire pll_clk_sel;
+ wire pll_clk_divided;
+ wire pll_clk90_divided;
+ wire core_ext_clk;
+ reg use_pll_first;
+ reg use_pll_second;
+ reg ext_clk_syncd_pre;
+ reg ext_clk_syncd;
+
+ assign pll_clk_sel = ~ext_clk_sel;
+
+ // Note that this implementation does not guard against switching to
+ // the PLL clock if the PLL clock is not present.
+
+ always @(posedge pll_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ use_pll_first <= 1'b0;
+ use_pll_second <= 1'b0;
+ ext_clk_syncd <= 1'b0;
+ end else begin
+ use_pll_first <= pll_clk_sel;
+ use_pll_second <= use_pll_first;
+ ext_clk_syncd_pre <= ext_clk; // Sync ext_clk to pll_clk
+ ext_clk_syncd <= ext_clk_syncd_pre; // Do this twice (resolve metastability)
+ end
+ end
+
+ // Apply PLL clock divider
+
+ clock_div #(
+ .SIZE(3)
+ ) divider (
+ .in(pll_clk),
+ .out(pll_clk_divided),
+ .N(sel),
+ .resetb(resetb)
+ );
+
+ // Secondary PLL clock divider for user space access
+
+ clock_div #(
+ .SIZE(3)
+ ) divider2 (
+ .in(pll_clk90),
+ .out(pll_clk90_divided),
+ .N(sel2),
+ .resetb(resetb)
+ );
+
+
+ // Multiplex the clock output
+
+ assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
+ assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
+ assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
+
+ // Reset assignment. "reset" comes from POR, while "ext_reset"
+ // comes from standalone SPI (and is normally zero unless
+ // activated from the SPI).
+
+ // Staged-delay reset
+ reg [2:0] reset_delay;
+
+ always @(negedge core_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ reset_delay <= 3'b111;
+ end else begin
+ reset_delay <= {1'b0, reset_delay[2:1]};
+ end
+ end
+
+ assign resetb_sync = ~(reset_delay[0] | ext_reset);
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/caravel_netlists.v b/caravel/verilog/rtl/caravel_netlists.v
new file mode 100644
index 0000000..773bc12
--- /dev/null
+++ b/caravel/verilog/rtl/caravel_netlists.v
@@ -0,0 +1,94 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`ifdef SIM
+
+ `include "defines.v"
+ `include "user_defines.v"
+ `include "pads.v"
+
+ /* NOTE: Need to pass the PDK root directory to iverilog with option -I */
+
+ `ifdef EF_STYLE
+ `include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
+ `include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
+
+ `include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
+ `include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
+ `include "libs.ref/verilog/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `else
+ `include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+ `include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+
+ `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+ `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+ `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+ `endif
+
+ `ifdef GL
+ `include "gl/digital_pll.v"
+ `include "gl/caravel_clocking.v"
+ `include "gl/user_id_programming.v"
+ `include "gl/chip_io.v"
+ `include "gl/housekeeping.v"
+ `include "gl/mprj_logic_high.v"
+ `include "gl/mprj2_logic_high.v"
+ `include "gl/mgmt_protect.v"
+ `include "gl/mgmt_protect_hv.v"
+ `include "gl/gpio_control_block.v"
+ `include "gl/gpio_defaults_block.v"
+ `include "gl/gpio_defaults_block_0403.v"
+ `include "gl/gpio_defaults_block_1803.v"
+ `include "gl/gpio_logic_high.v"
+ `include "gl/xres_buf.v"
+ `include "gl/spare_logic_block.v"
+ `include "gl/mgmt_core_wrapper.v"
+ `include "gl/caravel.v"
+ `else
+ `include "digital_pll.v"
+ `include "digital_pll_controller.v"
+ `include "ring_osc2x13.v"
+ `include "caravel_clocking.v"
+ `include "user_id_programming.v"
+ `include "clock_div.v"
+ `include "mprj_io.v"
+ `include "chip_io.v"
+ `include "housekeeping_spi.v"
+ `include "housekeeping.v"
+ `include "mprj_logic_high.v"
+ `include "mprj2_logic_high.v"
+ `include "mgmt_protect.v"
+ `include "mgmt_protect_hv.v"
+ `include "gpio_control_block.v"
+ `include "gpio_defaults_block.v"
+ `include "gpio_logic_high.v"
+ `include "xres_buf.v"
+ `include "spare_logic_block.v"
+ `include "mgmt_core_wrapper.v"
+ `include "caravel.v"
+ `endif
+
+ `include "simple_por.v"
+
+`endif
diff --git a/caravel/verilog/rtl/caravel_openframe.v b/caravel/verilog/rtl/caravel_openframe.v
new file mode 100644
index 0000000..b619a7e
--- /dev/null
+++ b/caravel/verilog/rtl/caravel_openframe.v
@@ -0,0 +1,1290 @@
+// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel_openframe, a project harness for the Google/SkyWater */
+/* sky130 fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/* Updated 10/15/2021: Revised using the housekeeping module */
+/* from housekeeping.v (refactoring a number of functions from */
+/* the management SoC). */
+/* */
+/* Updated 10/25/2021: Made the open-frame version, which */
+/* replaces the managment SoC wrapper, the user project */
+/* wrapper, and the management protect circuit with a single */
+/* user project wrapper. */
+/* */
+/*--------------------------------------------------------------*/
+
+module caravel_openframe (
+
+ // All top-level I/O are package-facing pins
+
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb, // Reset input (sense inverted)
+
+ // Note that only two flash data pins are dedicated to the
+ // management SoC wrapper. The management SoC exports the
+ // quad SPI mode status to make use of the top two mprj_io
+ // pins for io2 and io3.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00000000;
+
+ /*
+ *--------------------------------------------------------------------
+ *
+ * These pins are overlaid on mprj_io space. They have the function
+ * below when the management processor is in reset, or in the default
+ * configuration. They are assigned to uses in the user space by the
+ * configuration program running off of the SPI flash. Note that even
+ * when the user has taken control of these pins, they can be restored
+ * to the original use by setting the resetb pin low. The SPI pins and
+ * UART pins can be connected directly to an FTDI chip as long as the
+ * FTDI chip sets these lines to high impedence (input function) at
+ * all times except when holding the chip in reset.
+ *
+ * JTAG = mprj_io[0] (inout)
+ * SDO = mprj_io[1] (output)
+ * SDI = mprj_io[2] (input)
+ * CSB = mprj_io[3] (input)
+ * SCK = mprj_io[4] (input)
+ * ser_rx = mprj_io[5] (input)
+ * ser_tx = mprj_io[6] (output)
+ * irq = mprj_io[7] (input)
+ *
+ * spi_sck = mprj_io[32] (output)
+ * spi_csb = mprj_io[33] (output)
+ * spi_sdi = mprj_io[34] (input)
+ * spi_sdo = mprj_io[35] (output)
+ * flash_io2 = mprj_io[36] (inout)
+ * flash_io3 = mprj_io[37] (inout)
+ *
+ * These pins are reserved for any project that wants to incorporate
+ * its own processor and flash controller. While a user project can
+ * technically use any available I/O pins for the purpose, these
+ * four pins connect to a pass-through mode from the SPI slave (pins
+ * 1-4 above) so that any SPI flash connected to these specific pins
+ * can be accessed through the SPI slave even when the processor is in
+ * reset.
+ *
+ * user_flash_csb = mprj_io[8]
+ * user_flash_sck = mprj_io[9]
+ * user_flash_io0 = mprj_io[10]
+ * user_flash_io1 = mprj_io[11]
+ *
+ *--------------------------------------------------------------------
+ */
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // User Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* one- and three-pin data */
+ wire [`MPRJ_IO_PADS-5:0] mgmt_io_nc; /* no-connects */
+ wire [4:0] mgmt_io_out; /* three-pin interface out */
+ wire [4:0] mgmt_io_oeb; /* three-pin output enable */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ // Flash SPI communication (management SoC to housekeeping)
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
+ // Flash SPI communication (
+ wire flash_clk_frame;
+ wire flash_csb_frame;
+ wire flash_clk_oeb, flash_csb_oeb;
+ wire flash_clk_ieb, flash_csb_ieb;
+ wire flash_io0_oeb, flash_io1_oeb;
+ wire flash_io0_ieb, flash_io1_ieb;
+ wire flash_io0_do, flash_io1_do;
+ wire flash_io0_di, flash_io1_di;
+
+ chip_io padframe(
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_frame),
+ .flash_clk_core(flash_clk_frame),
+ .flash_csb_oeb_core(flash_csb_oeb),
+ .flash_clk_oeb_core(flash_clk_oeb),
+ .flash_io0_oeb_core(flash_io0_oeb),
+ .flash_io1_oeb_core(flash_io1_oeb),
+ .flash_csb_ieb_core(flash_csb_ieb),
+ .flash_clk_ieb_core(flash_clk_ieb),
+ .flash_io0_ieb_core(flash_io0_ieb),
+ .flash_io1_ieb_core(flash_io1_ieb),
+ .flash_io0_do_core(flash_io0_do),
+ .flash_io1_do_core(flash_io1_do),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io1_di_core(flash_io1_di),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+ wire [2:0] irq_spi; // From SPI and external pins
+
+ // Wishbone Bus (housekeeping facing)
+ wire mprj_cyc_o;
+ wire mprj_stb_o;
+ wire mprj_we_o;
+ wire [3:0] mprj_sel_o;
+ wire [31:0] mprj_adr_o;
+ wire [31:0] mprj_dat_o;
+ wire mprj_ack_i;
+ wire [31:0] mprj_dat_i;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+
+ // Power monitoring
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // SRAM read-only access from houskeeping
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire [7:0] hkspi_sram_addr;
+ wire [31:0] hkspi_sram_data;
+
+ /*--------------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*--------------------------------------------------*/
+
+ openframe_project_wrapper user_project (
+ `ifdef USE_POWER_PINS
+ .vdda(vdda_core),
+ .vssa(vssa_core),
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ // Clock and reset
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
+ .core_clock2(mprj_clock2),
+
+ // IRQ
+ .irq(irq_spi),
+
+ // Exported Wishbone Bus
+ .mprj_cyc_o(mprj_cyc_o),
+ .mprj_stb_o(mprj_stb_o),
+ .mprj_we_o(mprj_we_o),
+ .mprj_sel_o(mprj_sel_o),
+ .mprj_adr_o(mprj_adr_o),
+ .mprj_dat_o(mprj_dat_o),
+ .mprj_ack_i(mprj_ack_i),
+ .mprj_dat_i(mprj_dat_i),
+
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+
+ // GPIO pad 3-pin interface (plus analog)
+ .io_in (user_io_in),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
+
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+
+ // Module status (these may or may not be implemented)
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ // Module I/O (these may or may not be implemented)
+ // UART
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+ // SPI master
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ // Debug
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ // SRAM Read-only access to housekeeping
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ // Trap status
+ .trap(trap)
+ );
+
+ /*------------------------------------------*/
+ /* End user project instantiation */
+ /*------------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+
+ wire [2:0] spi_pll_sel;
+ wire [2:0] spi_pll90_sel;
+ wire [4:0] spi_pll_div;
+ wire [25:0] spi_pll_trim;
+
+ // Clocking control
+
+ caravel_clocking clocking(
+ `ifdef USE_POWER_PINS
+ .vdd1v8(VPWR),
+ .vss(VGND),
+ `endif
+ .ext_clk_sel(ext_clk_sel),
+ .ext_clk(clock),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(resetb),
+ .sel(spi_pll_sel),
+ .sel2(spi_pll90_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .resetb_sync(caravel_rstn)
+ );
+
+ // DCO/Digital Locked Loop
+
+ digital_pll pll (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .resetb(resetb),
+ .enable(spi_pll_ena),
+ .osc(clock),
+ .clockp({pll_clk, pll_clk90}),
+ .div(spi_pll_div),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
+ );
+
+ // Housekeeping interface
+
+ housekeeping housekeeping (
+ `ifdef USE_POWER_PINS
+ .vdd(VPWR),
+ .vss(VGND),
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+
+ .wb_adr_i(mprj_adr_o),
+ .wb_dat_i(mprj_dat_o),
+ .wb_sel_i(mprj_sel_o),
+ .wb_we_i(mprj_we_o),
+ .wb_cyc_i(mprj_cyc_o),
+ .wb_stb_i(mprj_stb_o),
+ .wb_ack_o(mprj_ack_i),
+ .wb_dat_o(mprj_dat_i),
+
+ .porb(porb_l),
+
+ .pll_ena(spi_pll_ena),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div(spi_pll_div),
+ .pll_sel(spi_pll_sel),
+ .pll90_sel(spi_pll90_sel),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ .irq(irq_spi),
+ .reset(ext_reset),
+
+ .serial_clock(mprj_io_loader_clock),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_1(mprj_io_loader_data_1),
+ .serial_data_2(mprj_io_loader_data_2),
+
+ .mgmt_gpio_in(mgmt_io_in),
+ .mgmt_gpio_out({mgmt_io_out[4:2], mgmt_io_in[`MPRJ_IO_PADS-4:2],
+ mgmt_io_out[1:0]}),
+ .mgmt_gpio_oeb({mgmt_io_oeb[4:2], mgmt_io_nc[`MPRJ_IO_PADS-6:0],
+ mgmt_io_oeb[1:0]}),
+
+ .pwr_ctrl_out(), /* Not used in this version */
+
+ .trap(trap),
+
+ .user_clock(user_clock),
+
+ .mask_rev_in(mask_rev),
+
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io0_di(flash_io0_di),
+ .pad_flash_io1_di(flash_io1_di),
+
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+ );
+
+ /* GPIO defaults (via programmed) */
+ wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+ /* Fixed defaults for the first 5 GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_01_defaults [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[25:0])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_234_defaults [2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[64:26])
+ );
+
+ /* Via-programmable defaults for the rest of the GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+ ) gpio_5_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[77:65])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+ ) gpio_6_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[90:78])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+ ) gpio_7_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[103:91])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+ ) gpio_8_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[116:104])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+ ) gpio_9_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[129:117])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+ ) gpio_10_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[142:130])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+ ) gpio_11_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[155:143])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+ ) gpio_12_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[168:156])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+ ) gpio_13_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[181:169])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+ ) gpio_14_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[194:182])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+ ) gpio_15_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[207:195])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+ ) gpio_16_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[220:208])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+ ) gpio_17_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[233:221])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+ ) gpio_18_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[246:234])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+ ) gpio_19_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[259:247])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+ ) gpio_20_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[272:260])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+ ) gpio_21_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[285:273])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+ ) gpio_22_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[298:286])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+ ) gpio_23_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[311:299])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+ ) gpio_24_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[324:312])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+ ) gpio_25_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[337:325])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+ ) gpio_26_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[350:338])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+ ) gpio_27_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[363:351])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+ ) gpio_28_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[376:364])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+ ) gpio_29_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[389:377])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+ ) gpio_30_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[402:390])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+ ) gpio_31_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[415:403])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+ ) gpio_32_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[428:416])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+ ) gpio_33_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[441:429])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+ ) gpio_34_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[454:442])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+ ) gpio_35_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[467:455])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+ ) gpio_36_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[480:468])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+ ) gpio_37_defaults (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[493:481])
+ );
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+
+ gpio_control_block gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[25:0]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out(mgmt_io_out[1:0]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
+
+ /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+ gpio_control_block gpio_control_in_1a [5:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[103:26]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[7:2]),
+ .serial_clock(gpio_clock_1_shifted[7:2]),
+
+ .resetn_out(gpio_resetn_1[7:2]),
+ .serial_clock_out(gpio_clock_1[7:2]),
+
+ .mgmt_gpio_in(mgmt_io_in[7:2]),
+ .mgmt_gpio_out(mgmt_io_in[7:2]),
+ .mgmt_gpio_oeb(one_loop1[7:2]),
+
+ .one(one_loop1[7:2]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[7:2]),
+ .serial_data_out(gpio_serial_link_1[7:2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[7:2]),
+ .user_gpio_oeb(user_io_oeb[7:2]),
+ .user_gpio_in(user_io_in[7:2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+ .pad_gpio_holdover(mprj_io_holdover[7:2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+ .pad_gpio_dm(mprj_io_dm[23:6]),
+ .pad_gpio_outenb(mprj_io_oeb[7:2]),
+ .pad_gpio_out(mprj_io_out[7:2]),
+ .pad_gpio_in(mprj_io_in[7:2])
+ );
+
+ /* Section 1 GPIOs (GPIO 8 to 18) */
+
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_oeb(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+
+ .one(one_loop1[(`MPRJ_IO_PADS_1-1):8]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+ );
+
+ /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+ gpio_control_block gpio_control_bidir_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .mgmt_gpio_out(mgmt_io_out[4:2]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[4:2]),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 34) */
+ wire [`MPRJ_IO_PADS_2-4:0] one_loop2;
+
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-4):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss(vssio_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ xres_buf rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .LVGND(vssd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/chip_io.v b/caravel/verilog/rtl/chip_io.v
new file mode 100644
index 0000000..8ae69d1
--- /dev/null
+++ b/caravel/verilog/rtl/chip_io.v
@@ -0,0 +1,400 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// `default_nettype none
+module chip_io(
+ // Package Pins
+ inout vddio_pad, // Common padframe/ESD supply
+ inout vddio_pad2,
+ inout vssio_pad, // Common padframe/ESD ground
+ inout vssio_pad2,
+ inout vccd_pad, // Common 1.8V supply
+ inout vssd_pad, // Common digital ground
+ inout vdda_pad, // Management analog 3.3V supply
+ inout vssa_pad, // Management analog ground
+ inout vdda1_pad, // User area 1 3.3V supply
+ inout vdda1_pad2,
+ inout vdda2_pad, // User area 2 3.3V supply
+ inout vssa1_pad, // User area 1 analog ground
+ inout vssa1_pad2,
+ inout vssa2_pad, // User area 2 analog ground
+ inout vccd1_pad, // User area 1 1.8V supply
+ inout vccd2_pad, // User area 2 1.8V supply
+ inout vssd1_pad, // User area 1 digital ground
+ inout vssd2_pad, // User area 2 digital ground
+
+ // Core Side
+ inout vddio, // Common padframe/ESD supply
+ inout vssio, // Common padframe/ESD ground
+ inout vccd, // Common 1.8V supply
+ inout vssd, // Common digital ground
+ inout vdda, // Management analog 3.3V supply
+ inout vssa, // Management analog ground
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8V supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio,
+ input clock,
+ input resetb,
+ output flash_csb,
+ output flash_clk,
+ inout flash_io0,
+ inout flash_io1,
+ // Chip Core Interface
+ input porb_h,
+ input por,
+ output resetb_core_h,
+ output clock_core,
+ input gpio_out_core,
+ output gpio_in_core,
+ input gpio_mode0_core,
+ input gpio_mode1_core,
+ input gpio_outenb_core,
+ input gpio_inenb_core,
+ input flash_csb_core,
+ input flash_clk_core,
+ input flash_csb_oeb_core,
+ input flash_clk_oeb_core,
+ input flash_io0_oeb_core,
+ input flash_io1_oeb_core,
+ input flash_csb_ieb_core, // NOTE: unused, fix me!
+ input flash_clk_ieb_core, // NOTE: unused, fix me!
+ input flash_io0_ieb_core,
+ input flash_io1_ieb_core,
+ input flash_io0_do_core,
+ input flash_io1_do_core,
+ output flash_io0_di_core,
+ output flash_io1_di_core,
+ // User project IOs
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_out,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_oeb,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_holdover,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+ input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+ output [`MPRJ_IO_PADS-1:0] mprj_io_in,
+ // User project direct access to gpio pad connections for analog
+ // (all but the lowest-numbered 7 pads)
+ inout [`MPRJ_IO_PADS-10:0] mprj_analog_io
+);
+
+ // To be considered: Master hold signal on all user pads (?)
+ // For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
+ // and setting enh to porb_h.
+
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
+
+ assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
+ assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
+
+ wire analog_a, analog_b;
+ wire vddio_q, vssio_q;
+
+ // Instantiate power and ground pads for management domain
+ // 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
+ // One each HV and LV clamp.
+
+ // HV clamps connect between one HV power rail and one ground
+ // LV clamps have two clamps connecting between any two LV power
+ // rails and grounds, and one back-to-back diode which connects
+ // between the first LV clamp ground and any other ground.
+
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDIO_PAD(vddio_pad)
+`endif
+ );
+
+ // lies in user area 2
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDIO_PAD(vddio_pad2)
+`endif
+ );
+
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda_pad)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd_pad)
+`endif
+ );
+
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSIO_PAD(vssio_pad)
+`endif
+ );
+
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSIO_PAD(vssio_pad2)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa_pad)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd_pad)
+`endif
+ );
+
+ // Instantiate power and ground pads for user 1 domain
+ // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
+
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda1_pad)
+`endif
+ );
+
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda1_pad2)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
+ `USER1_ABUTMENT_PINS
+ .VCCD1(vccd1),
+ .VSSD1(vssd1),
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd1_pad)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa1_pad)
+`endif
+ );
+
+
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa1_pad2)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
+ `USER1_ABUTMENT_PINS
+ .VCCD1(vccd1),
+ .VSSD1(vssd1),
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd1_pad)
+`endif
+ );
+
+ // Instantiate power and ground pads for user 2 domain
+ // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
+
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda2_pad)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
+ `USER2_ABUTMENT_PINS
+ .VCCD1(vccd2),
+ .VSSD1(vssd2),
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd2_pad)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa2_pad)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
+ `USER2_ABUTMENT_PINS
+ .VCCD1(vccd2),
+ .VSSD1(vssd2),
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd2_pad)
+`endif
+ );
+
+ wire [2:0] dm_all =
+ {gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
+ wire[2:0] flash_io0_mode =
+ {flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
+ wire[2:0] flash_io1_mode =
+ {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
+
+ // Management clock input pad
+ `INPUT_PAD(clock, clock_core);
+
+ // Management GPIO pad
+ `INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
+
+ // Management Flash SPI pads
+ `INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
+
+ `INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
+
+ `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core);
+ `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core);
+
+ // NOTE: The analog_out pad from the raven chip has been replaced by
+ // the digital reset input resetb on caravel due to the lack of an on-board
+ // power-on-reset circuit. The XRES pad is used for providing a glitch-
+ // free reset.
+
+ wire xresloop;
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ `MGMT_ABUTMENT_PINS
+ `ifndef TOP_ROUTING
+ .PAD(resetb),
+ `endif
+ .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .PAD_A_ESD_H(xresloop),
+ .XRES_H_N(resetb_core_h),
+ .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad
+ .ENABLE_H(porb_h), // Power-on-reset
+ .EN_VDDIO_SIG_H(vssio), // No idea.
+ .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input
+ .FILT_IN_H(vssio), // Alternate input for glitch filter
+ .PULLUP_H(vssio), // Pullup connection for alternate filter input
+ .ENABLE_VDDIO(vccd)
+ );
+
+ // Corner cells (These are overlay cells; it is not clear what is normally
+ // supposed to go under them.)
+
+ sky130_ef_io__corner_pad mgmt_corner [1:0] (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa),
+ .VSWITCH(vddio),
+ .VDDA(vdda),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+ sky130_ef_io__corner_pad user1_corner (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa1),
+ .VSWITCH(vddio),
+ .VDDA(vdda1),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+ sky130_ef_io__corner_pad user2_corner (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa2),
+ .VSWITCH(vddio),
+ .VDDA(vdda2),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+
+ mprj_io mprj_pads(
+ .vddio(vddio),
+ .vssio(vssio),
+ .vccd(vccd),
+ .vssd(vssd),
+ .vdda1(vdda1),
+ .vdda2(vdda2),
+ .vssa1(vssa1),
+ .vssa2(vssa2),
+ .vddio_q(vddio_q),
+ .vssio_q(vssio_q),
+ .analog_a(analog_a),
+ .analog_b(analog_b),
+ .porb_h(porb_h),
+ .io(mprj_io),
+ .io_out(mprj_io_out),
+ .oeb(mprj_io_oeb),
+ .hldh_n(mprj_io_hldh_n),
+ .enh(mprj_io_enh),
+ .inp_dis(mprj_io_inp_dis),
+ .ib_mode_sel(mprj_io_ib_mode_sel),
+ .vtrip_sel(mprj_io_vtrip_sel),
+ .holdover(mprj_io_holdover),
+ .slow_sel(mprj_io_slow_sel),
+ .analog_en(mprj_io_analog_en),
+ .analog_sel(mprj_io_analog_sel),
+ .analog_pol(mprj_io_analog_pol),
+ .dm(mprj_io_dm),
+ .io_in(mprj_io_in),
+ .analog_io(mprj_analog_io)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/chip_io_alt.v b/caravel/verilog/rtl/chip_io_alt.v
new file mode 100644
index 0000000..ceaf688
--- /dev/null
+++ b/caravel/verilog/rtl/chip_io_alt.v
@@ -0,0 +1,483 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// `default_nettype none
+
+/* Alternative padframe that removes the GPIO from the top row, */
+/* replacing them with un-overlaid power pads which have a */
+/* direct connection from pad to core. */
+
+/* For convenience, all of the original GPIO signals remain */
+/* defined in the I/O list, although some are not connected. */
+
+/* ANALOG_PADS_1 = Number of GPIO pads in the user 1 section */
+/* that are replaced by straight-through analog */
+/* ANALOG_PADS_2 = Number of GPIO pads in the user 2 section */
+/* that are replaced by straight-through analog */
+
+module chip_io_alt #(
+ parameter ANALOG_PADS_1 = 5,
+ parameter ANALOG_PADS_2 = 6
+) (
+ // Package Pins
+ inout vddio_pad, // Common padframe/ESD supply
+ inout vddio_pad2, // Common padframe/ESD supply
+ inout vssio_pad, // Common padframe/ESD ground
+ inout vssio_pad2, // Common padframe/ESD ground
+ inout vccd_pad, // Common 1.8V supply
+ inout vssd_pad, // Common digital ground
+ inout vdda_pad, // Management analog 3.3V supply
+ inout vssa_pad, // Management analog ground
+ inout vdda1_pad, // User area 1 3.3V supply
+ inout vdda1_pad2, // User area 1 3.3V supply
+ inout vdda2_pad, // User area 2 3.3V supply
+ inout vssa1_pad, // User area 1 analog ground
+ inout vssa1_pad2, // User area 1 analog ground
+ inout vssa2_pad, // User area 2 analog ground
+ inout vccd1_pad, // User area 1 1.8V supply
+ inout vccd2_pad, // User area 2 1.8V supply
+ inout vssd1_pad, // User area 1 digital ground
+ inout vssd2_pad, // User area 2 digital ground
+
+ // Core Side
+ inout vddio, // Common padframe/ESD supply
+ inout vssio, // Common padframe/ESD ground
+ inout vccd, // Common 1.8V supply
+ inout vssd, // Common digital ground
+ inout vdda, // Management analog 3.3V supply
+ inout vssa, // Management analog ground
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8V supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio,
+ input clock,
+ input resetb,
+ output flash_csb,
+ output flash_clk,
+ inout flash_io0,
+ inout flash_io1,
+ // Chip Core Interface
+ input porb_h,
+ input por,
+ output resetb_core_h,
+ output clock_core,
+ input gpio_out_core,
+ output gpio_in_core,
+ input gpio_mode0_core,
+ input gpio_mode1_core,
+ input gpio_outenb_core,
+ input gpio_inenb_core,
+ input flash_csb_core,
+ input flash_clk_core,
+ input flash_csb_oeb_core,
+ input flash_clk_oeb_core,
+ input flash_io0_oeb_core,
+ input flash_io1_oeb_core,
+ input flash_csb_ieb_core,
+ input flash_clk_ieb_core,
+ input flash_io0_ieb_core,
+ input flash_io1_ieb_core,
+ input flash_io0_do_core,
+ input flash_io1_do_core,
+ output flash_io0_di_core,
+ output flash_io1_di_core,
+ // User project IOs
+ // mprj_io is defined for all pads, both digital and analog
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ // The section below is for the digital pads only.
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_out,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_oeb,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_inp_dis,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_ib_mode_sel,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_vtrip_sel,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_slow_sel,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_holdover,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_en,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_sel,
+ input [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_analog_pol,
+ input [(`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2)*3-1:0] mprj_io_dm,
+ output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in,
+ output [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-1:0] mprj_io_in_3v3,
+
+ // User project direct access to gpio pad connections for analog
+ // "analog" connects to the "esd_0" pin of the GPIO pad, and
+ // "analog_noesd" connects to the "noesd" pin of the GPIO pad.
+
+ // User side 1: Connects to all but the first 7 pads;
+ // User side 2: Connects to all but the last 2 pads
+ inout [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-10:0] mprj_gpio_analog,
+ inout [`MPRJ_IO_PADS-ANALOG_PADS_1-ANALOG_PADS_2-10:0] mprj_gpio_noesd,
+
+ // Core connections for the analog signals
+ inout [ANALOG_PADS_1+ANALOG_PADS_2-1:0] mprj_analog,
+
+ // These are clamp connections for the clamps in the analog cells, if
+ // they are used for power supplies.
+ // User side 1: Connects to
+ input [2:0] mprj_clamp_high,
+ input [2:0] mprj_clamp_low
+);
+
+ wire analog_a, analog_b;
+ wire vddio_q, vssio_q;
+
+ // To be considered: Master hold signal on all user pads (?)
+ // For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
+ // and setting enh to porb_h.
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_hldh_n;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_enh;
+
+ assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
+ assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
+
+ // Instantiate power and ground pads for management domain
+ // 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
+ // One each HV and LV clamp.
+
+ // HV clamps connect between one HV power rail and one ground
+ // LV clamps have two clamps connecting between any two LV power
+ // rails and grounds, and one back-to-back diode which connects
+ // between the first LV clamp ground and any other ground.
+
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDIO_PAD(vddio_pad)
+`endif
+ );
+
+ // lies in user area 2
+ sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDIO_PAD(vddio_pad2)
+`endif
+ );
+
+ sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda_pad)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd_pad)
+`endif
+ );
+
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSIO_PAD(vssio_pad)
+`endif
+ );
+
+ sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSIO_PAD(vssio_pad2)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa_pad)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
+ `MGMT_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd_pad)
+`endif
+ );
+
+ // Instantiate power and ground pads for user 1 domain
+ // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
+
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda1_pad)
+`endif
+ );
+
+ sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda1_pad2)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
+ `USER1_ABUTMENT_PINS
+ .VCCD1(vccd1),
+ .VSSD1(vssd1),
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd1_pad)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa1_pad)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa1_pad2)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
+ `USER1_ABUTMENT_PINS
+ .VCCD1(vccd1),
+ .VSSD1(vssd1),
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd1_pad)
+`endif
+ );
+
+ // Instantiate power and ground pads for user 2 domain
+ // 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
+
+ sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VDDA_PAD(vdda2_pad)
+`endif
+ );
+
+ sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
+ `USER2_ABUTMENT_PINS
+ .VCCD1(vccd2),
+ .VSSD1(vssd2),
+`ifndef TOP_ROUTING
+ .VCCD_PAD(vccd2_pad)
+`endif
+ );
+
+ sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .VSSA_PAD(vssa2_pad)
+`endif
+ );
+
+ sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
+ `USER2_ABUTMENT_PINS
+ .VCCD1(vccd2),
+ .VSSD1(vssd2),
+`ifndef TOP_ROUTING
+ .VSSD_PAD(vssd2_pad)
+`endif
+ );
+
+ // Instantiate analog pads in user area 1 using the custom analog pad
+ sky130_ef_io__analog_pad user1_analog_pad [ANALOG_PADS_1-2:0] (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .P_PAD(mprj_io[`MPRJ_IO_PADS_1-2:`MPRJ_IO_PADS_1-ANALOG_PADS_1]),
+`endif
+ .P_CORE(mprj_analog[ANALOG_PADS_1-2:0])
+ );
+
+ // Last analog pad is a power pad, to provide a clamp resource.
+ sky130_ef_io__top_power_hvc user1_analog_pad_with_clamp (
+ `USER1_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .P_PAD(mprj_io[`MPRJ_IO_PADS_1-1]),
+`endif
+ `HVCLAMP_PINS(mprj_clamp_high[0],
+ mprj_clamp_low[0]),
+ .P_CORE(mprj_analog[ANALOG_PADS_1-1])
+ );
+
+ // Instantiate analog pads in user area 2 using the custom analog pad.
+ sky130_ef_io__analog_pad user2_analog_pad [ANALOG_PADS_2-3:0] (
+ `USER2_ABUTMENT_PINS
+`ifndef TOP_ROUTING
+ .P_PAD(mprj_io[`MPRJ_IO_PADS_1+ANALOG_PADS_2-1:`MPRJ_IO_PADS_1+2]),
+`endif
+ .P_CORE(mprj_analog[ANALOG_PADS_2+ANALOG_PADS_1-1:ANALOG_PADS_1+2])
+ );
+
+ // Last two analog pads are power pads, to provide clamp resources.
+ sky130_ef_io__top_power_hvc user2_analog_pad_with_clamp [1:0] (
+`ifndef TOP_ROUTING
+ .P_PAD(mprj_io[`MPRJ_IO_PADS_1+1:`MPRJ_IO_PADS_1]),
+`endif
+ `HVCLAMP_PINS(mprj_clamp_high[2:1], mprj_clamp_low[2:1]),
+ .P_CORE(mprj_analog[`ANALOG_PADS_1+1:ANALOG_PADS_1])
+ );
+
+ wire [2:0] dm_all =
+ {gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
+ wire[2:0] flash_io0_mode =
+ {flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
+ wire[2:0] flash_io1_mode =
+ {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
+
+ // Management clock input pad
+ `INPUT_PAD(clock, clock_core);
+
+ // Management GPIO pad
+ `INOUT_PAD(
+ gpio, gpio_in_core, gpio_out_core,
+ gpio_inenb_core, gpio_outenb_core, dm_all);
+
+ // Management Flash SPI pads
+ `INOUT_PAD(
+ flash_io0, flash_io0_di_core, flash_io0_do_core,
+ flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
+ `INOUT_PAD(
+ flash_io1, flash_io1_di_core, flash_io1_do_core,
+ flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
+
+ `OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core);
+ `OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core);
+
+ // NOTE: The analog_out pad from the raven chip has been replaced by
+ // the digital reset input resetb on caravel due to the lack of an on-board
+ // power-on-reset circuit. The XRES pad is used for providing a glitch-
+ // free reset.
+
+ wire xresloop;
+ sky130_fd_io__top_xres4v2 resetb_pad (
+ `MGMT_ABUTMENT_PINS
+ `ifndef TOP_ROUTING
+ .PAD(resetb),
+ `endif
+ .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(),
+ .PAD_A_ESD_H(xresloop),
+ .XRES_H_N(resetb_core_h),
+ .DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad
+ .ENABLE_H(porb_h), // Power-on-reset
+ .EN_VDDIO_SIG_H(vssio), // No idea.
+ .INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input
+ .FILT_IN_H(vssio), // Alternate input for glitch filter
+ .PULLUP_H(vssio), // Pullup connection for alternate filter input
+ .ENABLE_VDDIO(vccd)
+ );
+
+ // Corner cells (These are overlay cells; it is not clear what is normally
+ // supposed to go under them.)
+
+ sky130_ef_io__corner_pad mgmt_corner [1:0] (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa),
+ .VSWITCH(vddio),
+ .VDDA(vdda),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+
+ sky130_ef_io__corner_pad user1_corner (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa1),
+ .VSWITCH(vddio),
+ .VDDA(vdda1),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+ sky130_ef_io__corner_pad user2_corner (
+`ifndef TOP_ROUTING
+ .VSSIO(vssio),
+ .VDDIO(vddio),
+ .VDDIO_Q(vddio_q),
+ .VSSIO_Q(vssio_q),
+ .AMUXBUS_A(analog_a),
+ .AMUXBUS_B(analog_b),
+ .VSSD(vssd),
+ .VSSA(vssa2),
+ .VSWITCH(vddio),
+ .VDDA(vdda2),
+ .VCCD(vccd),
+ .VCCHIB(vccd)
+`endif
+ );
+
+ mprj_io #(
+ .AREA1PADS(`MPRJ_IO_PADS_1 - ANALOG_PADS_1),
+ .TOTAL_PADS(`MPRJ_IO_PADS - ANALOG_PADS_1 - ANALOG_PADS_2)
+ ) mprj_pads (
+ .vddio(vddio),
+ .vssio(vssio),
+ .vccd(vccd),
+ .vssd(vssd),
+ .vdda1(vdda1),
+ .vdda2(vdda2),
+ .vssa1(vssa1),
+ .vssa2(vssa2),
+ .vddio_q(vddio_q),
+ .vssio_q(vssio_q),
+ .analog_a(analog_a),
+ .analog_b(analog_b),
+ .porb_h(porb_h),
+
+ .io({mprj_io[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS_1+ANALOG_PADS_2],
+ mprj_io[`MPRJ_IO_PADS_1-ANALOG_PADS_1-1:0]}),
+ .io_out(mprj_io_out),
+ .oeb(mprj_io_oeb),
+ .hldh_n(mprj_io_hldh_n),
+ .enh(mprj_io_enh),
+ .inp_dis(mprj_io_inp_dis),
+ .ib_mode_sel(mprj_io_ib_mode_sel),
+ .vtrip_sel(mprj_io_vtrip_sel),
+ .holdover(mprj_io_holdover),
+ .slow_sel(mprj_io_slow_sel),
+ .analog_en(mprj_io_analog_en),
+ .analog_sel(mprj_io_analog_sel),
+ .analog_pol(mprj_io_analog_pol),
+ .dm(mprj_io_dm),
+ .io_in(mprj_io_in),
+ .io_in_3v3(mprj_io_in_3v3),
+ .analog_io(mprj_gpio_analog),
+ .analog_noesd_io(mprj_gpio_noesd)
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/clock_div.v b/caravel/verilog/rtl/clock_div.v
new file mode 100644
index 0000000..a2bbf19
--- /dev/null
+++ b/caravel/verilog/rtl/clock_div.v
@@ -0,0 +1,214 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Integer-N clock divider */
+`default_nettype none
+
+module clock_div #(
+ parameter SIZE = 3 // Number of bits for the divider value
+) (
+ in, out, N, resetb
+);
+ input in; // input clock
+ input [SIZE-1:0] N; // the number to be divided by
+ input resetb; // asynchronous reset (sense negative)
+ output out; // divided output clock
+
+ wire out_odd; // output of odd divider
+ wire out_even; // output of even divider
+ wire not_zero; // signal to find divide by 0 case
+ wire enable_even; // enable of even divider
+ wire enable_odd; // enable of odd divider
+
+ reg [SIZE-1:0] syncN; // N synchronized to output clock
+ reg [SIZE-1:0] syncNp; // N synchronized to output clock
+
+ assign not_zero = | syncN[SIZE-1:1];
+
+ assign out = (out_odd & syncN[0] & not_zero) | (out_even & !syncN[0]);
+ assign enable_odd = syncN[0] & not_zero;
+ assign enable_even = !syncN[0];
+
+ // Divider value synchronization (double-synchronized to avoid metastability)
+ always @(posedge out or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ syncN <= `CLK_DIV; // Default to divide-by-2 on system reset
+ syncNp <= `CLK_DIV; // Default to divide-by-2 on system reset
+ end else begin
+ syncNp <= N;
+ syncN <= syncNp;
+ end
+ end
+
+ // Even divider
+ even even_0(in, out_even, syncN, resetb, not_zero, enable_even);
+ // Odd divider
+ odd odd_0(in, out_odd, syncN, resetb, enable_odd);
+
+endmodule // clock_div
+
+/* Odd divider */
+
+module odd #(
+ parameter SIZE = 3
+) (
+ clk, out, N, resetb, enable
+);
+ input clk; // slow clock
+ output out; // fast output clock
+ input [SIZE-1:0] N; // division factor
+ input resetb; // synchronous reset
+ input enable; // odd enable
+
+ reg [SIZE-1:0] counter; // these 2 counters are used
+ reg [SIZE-1:0] counter2; // to non-overlapping signals
+ reg out_counter; // positive edge triggered counter
+ reg out_counter2; // negative edge triggered counter
+ reg rst_pulse; // pulse generated when vector N changes
+ reg [SIZE-1:0] old_N; // gets set to old N when N is changed
+ wire not_zero; // if !not_zero, we devide by 1
+
+ // xor to generate 50% duty, half-period waves of final output
+ assign out = out_counter2 ^ out_counter;
+
+ // positive edge counter/divider
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ counter <= `CLK_DIV;
+ out_counter <= 1;
+ end else if (rst_pulse) begin
+ counter <= N;
+ out_counter <= 1;
+ end else if (enable) begin
+ if (counter == 1) begin
+ counter <= N;
+ out_counter <= ~out_counter;
+ end else begin
+ counter <= counter - 1'b1;
+ end
+ end
+ end
+
+ reg [SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
+ wire [SIZE:0] interm_3; // from the positive edge counter in order to
+ assign interm_3 = {1'b0, N} + 2'b11; // guarantee 50% duty cycle.
+
+ localparam [SIZE:0] interm_init = {1'b0,`CLK_DIV} + 2'b11;
+
+ // Counter driven by negative edge of clock.
+
+ always @(negedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ // reset the counter at system reset
+ counter2 <= `CLK_DIV;
+ initial_begin <= interm_init[SIZE:1];
+ out_counter2 <= 1;
+ end else if (rst_pulse) begin
+ // reset the counter at change of N.
+ counter2 <= N;
+ initial_begin <= interm_3[SIZE:1];
+ out_counter2 <= 1;
+ end else if ((initial_begin <= 1) && enable) begin
+
+ // Do normal logic after odd calibration.
+ // This is the same as the even counter.
+ if (counter2 == 1) begin
+ counter2 <= N;
+ out_counter2 <= ~out_counter2;
+ end else begin
+ counter2 <= counter2 - 1'b1;
+ end
+ end else if (enable) begin
+ initial_begin <= initial_begin - 1'b1;
+ end
+ end
+
+ //
+ // reset pulse generator:
+ // __ __ __ __ _
+ // clk: __/ \__/ \__/ \__/ \__/
+ // _ __________________________
+ // N: _X__________________________
+ // _____
+ // rst_pulse: __/ \___________________
+ //
+ // This block generates an internal reset for the odd divider in the
+ // form of a single pulse signal when the odd divider is enabled.
+
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ rst_pulse <= 0;
+ end else if (enable) begin
+ if (N != old_N) begin
+ // pulse when reset changes
+ rst_pulse <= 1;
+ end else begin
+ rst_pulse <= 0;
+ end
+ end
+ end
+
+ always @(posedge clk) begin
+ // always save the old N value to guarante reset from
+ // an even-to-odd transition.
+ old_N <= N;
+ end
+
+endmodule // odd
+
+/* Even divider */
+
+module even #(
+ parameter SIZE = 3
+) (
+ clk, out, N, resetb, not_zero, enable
+);
+ input clk; // fast input clock
+ output out; // slower divided clock
+ input [SIZE-1:0] N; // divide by factor 'N'
+ input resetb; // asynchronous reset
+ input not_zero; // if !not_zero divide by 1
+ input enable; // enable the even divider
+
+ reg [SIZE-1:0] counter;
+ reg out_counter;
+ wire [SIZE-1:0] div_2;
+
+ // if N=0 just output the clock, otherwise, divide it.
+ assign out = (clk & !not_zero) | (out_counter & not_zero);
+ assign div_2 = {1'b0, N[SIZE-1:1]};
+
+ // simple flip-flop even divider
+ always @(posedge clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
+ counter <= 1;
+ out_counter <= 1;
+
+ end else if (enable) begin
+ // only use switching power if enabled
+ if (counter == 1) begin
+ // divide after counter has reached bottom
+ // of interval 'N' which will be value '1'
+ counter <= div_2;
+ out_counter <= ~out_counter;
+ end else begin
+ // decrement the counter and wait
+ counter <= counter-1; // to start next transition.
+ end
+ end
+ end
+
+endmodule //even
+`default_nettype wire
diff --git a/caravel/verilog/rtl/defines.v b/caravel/verilog/rtl/defines.v
new file mode 100644
index 0000000..6213b6c
--- /dev/null
+++ b/caravel/verilog/rtl/defines.v
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 1
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO control default mode and enable for most I/Os
+// Most I/Os set to be user input pins on startup.
+// NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
+`define MGMT_INIT 1'b0
+`define OENB_INIT 1'b0
+`define DM_INIT 3'b001
+
+`endif // __GLOBAL_DEFINE_H
diff --git a/caravel/verilog/rtl/digital_pll.v b/caravel/verilog/rtl/digital_pll.v
new file mode 100644
index 0000000..322c254
--- /dev/null
+++ b/caravel/verilog/rtl/digital_pll.v
@@ -0,0 +1,73 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// Digital PLL (ring oscillator + controller)
+// Technically this is a frequency locked loop, not a phase locked loop.
+
+`ifndef SIM
+`include "digital_pll_controller.v"
+`include "ring_osc2x13.v"
+`endif
+
+module digital_pll(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
+ resetb, enable, osc, clockp, div, dco, ext_trim);
+
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
+
+ input resetb; // Sense negative reset
+ input enable; // Enable PLL
+ input osc; // Input oscillator to match
+ input [4:0] div; // PLL feedback division ratio
+ input dco; // Run in DCO mode
+ input [25:0] ext_trim; // External trim for DCO mode
+
+ output [1:0] clockp; // Two 90 degree clock phases
+
+ wire [25:0] itrim; // Internally generated trim bits
+ wire [25:0] otrim; // Trim bits applied to the ring oscillator
+ wire creset; // Controller reset
+ wire ireset; // Internal reset (external reset OR disable)
+
+ assign ireset = ~resetb | ~enable;
+
+ // In DCO mode: Hold controller in reset and apply external trim value
+
+ assign itrim = (dco == 1'b0) ? otrim : ext_trim;
+ assign creset = (dco == 1'b0) ? ireset : 1'b1;
+
+ ring_osc2x13 ringosc (
+ .reset(ireset),
+ .trim(itrim),
+ .clockp(clockp)
+ );
+
+ digital_pll_controller pll_control (
+ .reset(creset),
+ .clock(clockp[0]),
+ .osc(osc),
+ .div(div),
+ .trim(otrim)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/digital_pll_controller.v b/caravel/verilog/rtl/digital_pll_controller.v
new file mode 100644
index 0000000..ae13d9d
--- /dev/null
+++ b/caravel/verilog/rtl/digital_pll_controller.v
@@ -0,0 +1,136 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// (True) digital PLL
+//
+// Output goes to a trimmable ring oscillator (see documentation).
+// Ring oscillator should be trimmable to above and below maximum
+// ranges of the input.
+//
+// Input "osc" comes from a fixed clock source (e.g., crystal oscillator
+// output).
+//
+// Input "div" is the target number of clock cycles per oscillator cycle.
+// e.g., if div == 8 then this is an 8X PLL.
+//
+// Clock "clock" is the PLL output being trimmed.
+// (NOTE: To be done: Pass-through enable)
+//
+// Algorithm:
+//
+// 1) Trim is done by thermometer code. Reset to the highest value
+// in case the fastest rate clock is too fast for the logic.
+//
+// 2) Count the number of contiguous 1s and 0s in "osc"
+// periods of the master clock. If the count maxes out, it does
+// not roll over.
+//
+// 3) Add the two counts together.
+//
+// 4) If the sum is less than div, then the clock is too slow, so
+// decrease the trim code. If the sum is greater than div, the
+// clock is too fast, so increase the trim code. If the sum
+// is equal to div, the the trim code does not change.
+//
+
+module digital_pll_controller(reset, clock, osc, div, trim);
+ input reset;
+ input clock;
+ input osc;
+ input [4:0] div;
+ output [25:0] trim; // Use ring_osc2x13, with 26 trim bits
+
+ wire [25:0] trim;
+ reg [2:0] oscbuf;
+ reg [2:0] prep;
+
+ reg [4:0] count0;
+ reg [4:0] count1;
+ reg [6:0] tval; // Includes 2 bits fractional
+ wire [4:0] tint; // Integer part of the above
+
+ wire [5:0] sum;
+
+ assign sum = count0 + count1;
+
+ // Integer to thermometer code (maybe there's an algorithmic way?)
+ assign tint = tval[6:2];
+ // |<--second-->|<-- first-->|
+ assign trim = (tint == 5'd0) ? 26'b0000000000000_0000000000000 :
+ (tint == 5'd1) ? 26'b0000000000000_0000000000001 :
+ (tint == 5'd2) ? 26'b0000000000000_0000001000001 :
+ (tint == 5'd3) ? 26'b0000000000000_0010001000001 :
+ (tint == 5'd4) ? 26'b0000000000000_0010001001001 :
+ (tint == 5'd5) ? 26'b0000000000000_0010101001001 :
+ (tint == 5'd6) ? 26'b0000000000000_1010101001001 :
+ (tint == 5'd7) ? 26'b0000000000000_1010101101001 :
+ (tint == 5'd8) ? 26'b0000000000000_1010101101101 :
+ (tint == 5'd9) ? 26'b0000000000000_1011101101101 :
+ (tint == 5'd10) ? 26'b0000000000000_1011101111101 :
+ (tint == 5'd11) ? 26'b0000000000000_1111101111101 :
+ (tint == 5'd12) ? 26'b0000000000000_1111101111111 :
+ (tint == 5'd13) ? 26'b0000000000000_1111111111111 :
+ (tint == 5'd14) ? 26'b0000000000001_1111111111111 :
+ (tint == 5'd15) ? 26'b0000001000001_1111111111111 :
+ (tint == 5'd16) ? 26'b0010001000001_1111111111111 :
+ (tint == 5'd17) ? 26'b0010001001001_1111111111111 :
+ (tint == 5'd18) ? 26'b0010101001001_1111111111111 :
+ (tint == 5'd19) ? 26'b1010101001001_1111111111111 :
+ (tint == 5'd20) ? 26'b1010101101001_1111111111111 :
+ (tint == 5'd21) ? 26'b1010101101101_1111111111111 :
+ (tint == 5'd22) ? 26'b1011101101101_1111111111111 :
+ (tint == 5'd23) ? 26'b1011101111101_1111111111111 :
+ (tint == 5'd24) ? 26'b1111101111101_1111111111111 :
+ (tint == 5'd25) ? 26'b1111101111111_1111111111111 :
+ 26'b1111111111111_1111111111111;
+
+ always @(posedge clock or posedge reset) begin
+ if (reset == 1'b1) begin
+ tval <= 7'd0; // Note: trim[0] must be zero for startup to work.
+ oscbuf <= 3'd0;
+ prep <= 3'd0;
+ count0 <= 5'd0;
+ count1 <= 5'd0;
+
+ end else begin
+ oscbuf <= {oscbuf[1:0], osc};
+
+ if (oscbuf[2] != oscbuf[1]) begin
+ count1 <= count0;
+ count0 <= 5'b00001;
+ prep <= {prep[1:0], 1'b1};
+
+ if (prep == 3'b111) begin
+ if (sum > div) begin
+ if (tval < 127) begin
+ tval <= tval + 1;
+ end
+ end else if (sum < div) begin
+ if (tval > 0) begin
+ tval <= tval - 1;
+ end
+ end
+ end
+ end else begin
+ if (count0 != 5'b11111) begin
+ count0 <= count0 + 1;
+ end
+ end
+ end
+ end
+
+endmodule // digital_pll_controller
+`default_nettype wire
diff --git a/caravel/verilog/rtl/gpio_control_block.v b/caravel/verilog/rtl/gpio_control_block.v
new file mode 100644
index 0000000..c2d142f
--- /dev/null
+++ b/caravel/verilog/rtl/gpio_control_block.v
@@ -0,0 +1,260 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *---------------------------------------------------------------------
+ * See gpio_control_block for description. This module is like
+ * gpio_contro_block except that it has an additional two management-
+ * Soc-facing pins, which are the out_enb line and the output line.
+ * If the chip is configured for output with the oeb control
+ * register = 1, then the oeb line is controlled by the additional
+ * signal from the management SoC. If the oeb control register = 0,
+ * then the output is disabled completely. The "io" line is input
+ * only in this module.
+ *
+ *---------------------------------------------------------------------
+ */
+
+/*
+ *---------------------------------------------------------------------
+ *
+ * This module instantiates a shift register chain that passes through
+ * each gpio cell. These are connected end-to-end around the padframe
+ * periphery. The purpose is to avoid a massive number of control
+ * wires between the digital core and I/O, passing through the user area.
+ *
+ * See mprj_ctrl.v for the module that registers the data for each
+ * I/O and drives the input to the shift register.
+ *
+ *---------------------------------------------------------------------
+ */
+
+module gpio_control_block #(
+ parameter PAD_CTRL_BITS = 13
+) (
+ `ifdef USE_POWER_PINS
+ inout vccd,
+ inout vssd,
+ inout vccd1,
+ inout vssd1,
+ `endif
+
+ // Power-on defaults
+ input [PAD_CTRL_BITS-1:0] gpio_defaults,
+
+ // Management Soc-facing signals
+ input resetn, // Global reset, locally propagated
+ output resetn_out,
+ input serial_clock, // Global clock, locally propatated
+ output serial_clock_out,
+ input serial_load, // Register load strobe
+ output serial_load_out,
+
+ output mgmt_gpio_in, // Management from pad (input only)
+ input mgmt_gpio_out, // Management to pad (output only)
+ input mgmt_gpio_oeb, // Management to pad (output only)
+
+ // Serial data chain for pad configuration
+ input serial_data_in,
+ output serial_data_out,
+
+ // User-facing signals
+ input user_gpio_out, // User space to pad
+ input user_gpio_oeb, // Output enable (user)
+ output user_gpio_in, // Pad to user space
+
+ // Pad-facing signals (Pad GPIOv2)
+ output pad_gpio_holdover,
+ output pad_gpio_slow_sel,
+ output pad_gpio_vtrip_sel,
+ output pad_gpio_inenb,
+ output pad_gpio_ib_mode_sel,
+ output pad_gpio_ana_en,
+ output pad_gpio_ana_sel,
+ output pad_gpio_ana_pol,
+ output [2:0] pad_gpio_dm,
+ output pad_gpio_outenb,
+ output pad_gpio_out,
+ input pad_gpio_in,
+
+ // to provide a way to automatically disable/enable output
+ // from the outside with needing a conb cell
+ output one,
+ output zero
+);
+
+ /* Parameters defining the bit offset of each function in the chain */
+ localparam MGMT_EN = 0;
+ localparam OEB = 1;
+ localparam HLDH = 2;
+ localparam INP_DIS = 3;
+ localparam MOD_SEL = 4;
+ localparam AN_EN = 5;
+ localparam AN_SEL = 6;
+ localparam AN_POL = 7;
+ localparam SLOW = 8;
+ localparam TRIP = 9;
+ localparam DM = 10;
+
+ /* Internally registered signals */
+ reg mgmt_ena; // Enable management SoC to access pad
+ reg gpio_holdover;
+ reg gpio_slow_sel;
+ reg gpio_vtrip_sel;
+ reg gpio_inenb;
+ reg gpio_ib_mode_sel;
+ reg gpio_outenb;
+ reg [2:0] gpio_dm;
+ reg gpio_ana_en;
+ reg gpio_ana_sel;
+ reg gpio_ana_pol;
+
+ /* Derived output values */
+ wire pad_gpio_holdover;
+ wire pad_gpio_slow_sel;
+ wire pad_gpio_vtrip_sel;
+ wire pad_gpio_inenb;
+ wire pad_gpio_ib_mode_sel;
+ wire pad_gpio_ana_en;
+ wire pad_gpio_ana_sel;
+ wire pad_gpio_ana_pol;
+ wire [2:0] pad_gpio_dm;
+ wire pad_gpio_outenb;
+ wire pad_gpio_out;
+ wire pad_gpio_in;
+ wire one;
+ wire zero;
+
+ wire user_gpio_in;
+ wire gpio_in_unbuf;
+ wire gpio_logic1;
+ wire serial_data_pre;
+
+ /* Serial shift for the above (latched) values */
+ reg [PAD_CTRL_BITS-1:0] shift_register;
+
+ /* Create internal reset and load signals from input reset and clock */
+ assign serial_data_pre = shift_register[PAD_CTRL_BITS-1];
+
+ /* Propagate the clock and reset signals so that they aren't wired */
+ /* all over the chip, but are just wired between the blocks. */
+ assign serial_clock_out = serial_clock;
+ assign resetn_out = resetn;
+ assign serial_load_out = serial_load;
+
+ /* Serial data should be buffered again to avoid hold violations */
+ assign serial_data_out = serial_data_pre & one;
+
+ always @(posedge serial_clock or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ /* Clear shift register */
+ shift_register <= 'd0;
+ end else begin
+ /* Shift data in */
+ shift_register <= {shift_register[PAD_CTRL_BITS-2:0], serial_data_in};
+ end
+ end
+
+ always @(posedge serial_load or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ /* Initial state on reset depends on applied defaults */
+ mgmt_ena <= gpio_defaults[MGMT_EN];
+ gpio_holdover <= gpio_defaults[HLDH];
+ gpio_slow_sel <= gpio_defaults[SLOW];
+ gpio_vtrip_sel <= gpio_defaults[TRIP];
+ gpio_ib_mode_sel <= gpio_defaults[MOD_SEL];
+ gpio_inenb <= gpio_defaults[INP_DIS];
+ gpio_outenb <= gpio_defaults[OEB];
+ gpio_dm <= gpio_defaults[DM+2:DM];
+ gpio_ana_en <= gpio_defaults[AN_EN];
+ gpio_ana_sel <= gpio_defaults[AN_SEL];
+ gpio_ana_pol <= gpio_defaults[AN_POL];
+ end else begin
+ /* Load data */
+ mgmt_ena <= shift_register[MGMT_EN];
+ gpio_outenb <= shift_register[OEB];
+ gpio_holdover <= shift_register[HLDH];
+ gpio_inenb <= shift_register[INP_DIS];
+ gpio_ib_mode_sel <= shift_register[MOD_SEL];
+ gpio_ana_en <= shift_register[AN_EN];
+ gpio_ana_sel <= shift_register[AN_SEL];
+ gpio_ana_pol <= shift_register[AN_POL];
+ gpio_slow_sel <= shift_register[SLOW];
+ gpio_vtrip_sel <= shift_register[TRIP];
+ gpio_dm <= shift_register[DM+2:DM];
+
+ end
+ end
+
+ /* These pad configuration signals are static and do not change */
+ /* after setup. */
+
+ assign pad_gpio_holdover = gpio_holdover;
+ assign pad_gpio_slow_sel = gpio_slow_sel;
+ assign pad_gpio_vtrip_sel = gpio_vtrip_sel;
+ assign pad_gpio_ib_mode_sel = gpio_ib_mode_sel;
+ assign pad_gpio_ana_en = gpio_ana_en;
+ assign pad_gpio_ana_sel = gpio_ana_sel;
+ assign pad_gpio_ana_pol = gpio_ana_pol;
+ assign pad_gpio_dm = gpio_dm;
+ assign pad_gpio_inenb = gpio_inenb;
+
+ /* Implement pad control behavior depending on state of mgmt_ena */
+
+ assign gpio_in_unbuf = pad_gpio_in;
+ assign mgmt_gpio_in = (gpio_inenb == 1'b0 && gpio_outenb == 1'b1) ?
+ pad_gpio_in : 1'bz;
+ assign pad_gpio_outenb = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
+ gpio_outenb : 1'b0) : user_gpio_oeb;
+ assign pad_gpio_out = (mgmt_ena) ? ((mgmt_gpio_oeb == 1'b1) ?
+ ((gpio_dm[2:1] == 2'b01) ? ~gpio_dm[0] : mgmt_gpio_out) :
+ mgmt_gpio_out) : user_gpio_out;
+
+ /* Buffer user_gpio_in with an enable that is set by the user domain vccd */
+
+ gpio_logic_high gpio_logic_high (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .gpio_logic1(gpio_logic1)
+ );
+
+ sky130_fd_sc_hd__einvp_8 gpio_in_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(user_gpio_in),
+ .A(~gpio_in_unbuf),
+ .TE(gpio_logic1)
+ );
+
+ sky130_fd_sc_hd__conb_1 const_source (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .HI(one),
+ .LO(zero)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/gpio_defaults_block.v b/caravel/verilog/rtl/gpio_defaults_block.v
new file mode 100644
index 0000000..e17b65d
--- /dev/null
+++ b/caravel/verilog/rtl/gpio_defaults_block.v
@@ -0,0 +1,63 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+// This module represents an unprogrammed set of GPIO pad default
+// values that is configured with via programming on the chip top
+// level. This value is passed as a set of parameters (formerly
+// part of gpio_control_block.v).
+
+module gpio_defaults_block #(
+ // Parameterized initial startup state of the pad. The default
+ // parameters if unspecified is for the pad to be a user input
+ // with no pull-up or pull-down, so that it is disconnected
+ // from the outside world. See defs.h for configuration word
+ // definitions.
+ parameter GPIO_CONFIG_INIT = 13'h0402
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ output [12:0] gpio_defaults
+);
+ wire [12:0] gpio_defaults;
+ wire [12:0] gpio_defaults_high;
+ wire [12:0] gpio_defaults_low;
+
+ // For the mask revision input, use an array of digital constant logic cells
+
+ sky130_fd_sc_hd__conb_1 gpio_default_value [12:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VPB(VPWR),
+ .VNB(VGND),
+ .VGND(VGND),
+`endif
+ .HI(gpio_defaults_high),
+ .LO(gpio_defaults_low)
+ );
+
+ genvar i;
+ generate
+ for (i = 0; i < 13; i = i+1) begin
+ assign gpio_defaults[i] = (GPIO_CONFIG_INIT & (13'h0001 << i)) ?
+ gpio_defaults_high[i] : gpio_defaults_low[i];
+ end
+ endgenerate
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/gpio_logic_high.v b/caravel/verilog/rtl/gpio_logic_high.v
new file mode 100644
index 0000000..2e4158e
--- /dev/null
+++ b/caravel/verilog/rtl/gpio_logic_high.v
@@ -0,0 +1,21 @@
+module gpio_logic_high(
+ `ifdef USE_POWER_PINS
+ inout vccd1,
+ inout vssd1,
+ `endif
+
+ output wire gpio_logic1
+);
+
+ sky130_fd_sc_hd__conb_1 gpio_logic_high (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd1),
+ .VGND(vssd1),
+ .VPB(vccd1),
+ .VNB(vssd1),
+`endif
+ .HI(gpio_logic1),
+ .LO()
+ );
+
+endmodule
diff --git a/caravel/verilog/rtl/housekeeping.v b/caravel/verilog/rtl/housekeeping.v
new file mode 100644
index 0000000..bb4e20f
--- /dev/null
+++ b/caravel/verilog/rtl/housekeeping.v
@@ -0,0 +1,1411 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+//-----------------------------------------------------------
+// Housekeeping interface for Caravel
+//-----------------------------------------------------------
+// Written by Tim Edwards
+// efabless, inc. September 27, 2020
+//-----------------------------------------------------------
+
+//-----------------------------------------------------------
+// This is a standalone slave SPI for the caravel chip that is
+// intended to be independent of the picosoc and independent
+// of all IP blocks except the power-on-reset. This SPI has
+// register outputs controlling the functions that critically
+// affect operation of the picosoc and so cannot be accessed
+// from the picosoc itself. This includes the PLL enables,
+// mode, and trim. It also has a general reset for the picosoc,
+// an IRQ input, a bypass for the entire crystal oscillator
+// and PLL chain, the manufacturer and product IDs and product
+// revision number.
+//
+// Updated and revised, 10/13/2021:
+// This module now comprises what was previously split into
+// the housekeeping SPI, the mprj_ctrl block (control over
+// the GPIO), and sysctrl (redirection of certain internal
+// signals to the GPIO); and additionally manages the SPI
+// flash signals and pass-through mode. Essentially all
+// aspects of the system related to the use and configuration
+// of the GPIO has been shifted to this module. This allows
+// GPIO to be configured from either the management SoC
+// through the wishbone interface, or externally through the
+// SPI interface. It allows essentially any processor to
+// take the place of the PicoRV32 as long as that processor
+// can access memory-mapped space via the wishbone bus.
+//-----------------------------------------------------------
+
+//------------------------------------------------------------
+// Caravel defined registers (by SPI address):
+// See: doc/memory_map.txt
+//------------------------------------------------------------
+
+module housekeeping #(
+ parameter GPIO_BASE_ADR = 32'h2600_0000,
+ parameter SPI_BASE_ADR = 32'h2610_0000,
+ parameter SYS_BASE_ADR = 32'h2620_0000,
+ parameter IO_CTRL_BITS = 13
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+
+ // Wishbone interface to management SoC
+ input wb_clk_i,
+ input wb_rstn_i,
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+ output wb_ack_o,
+ output [31:0] wb_dat_o,
+
+ // Primary reset
+ input porb,
+
+ // Clocking control parameters
+ output pll_ena,
+ output pll_dco_ena,
+ output [4:0] pll_div,
+ output [2:0] pll_sel,
+ output [2:0] pll90_sel,
+ output [25:0] pll_trim,
+ output pll_bypass,
+
+ // Module enable status from SoC
+ input qspi_enabled, // Flash SPI is in quad mode
+ input uart_enabled, // UART is enabled
+ input spi_enabled, // SPI master is enabled
+ input debug_mode, // Debug mode enabled
+
+ // UART interface to/from SoC
+ input ser_tx,
+ output ser_rx,
+
+ // SPI master interface to/from SoC
+ output spi_sdi,
+ input spi_csb,
+ input spi_sck,
+ input spi_sdo,
+ input spi_sdoenb,
+
+ // External (originating from SPI and pad) IRQ and reset
+ output [2:0] irq,
+ output reset,
+
+ // GPIO serial loader programming interface
+ output serial_clock,
+ output serial_load,
+ output serial_resetn,
+ output serial_data_1,
+ output serial_data_2,
+
+ // GPIO data management (to padframe)---three-pin interface
+ input [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
+ output [`MPRJ_IO_PADS-1:0] mgmt_gpio_out,
+ output [`MPRJ_IO_PADS-1:0] mgmt_gpio_oeb,
+
+ // Power control output (reserved for future use with LDOs)
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+
+ // CPU trap state status (for system monitoring)
+ input trap,
+
+ // User clock (for system monitoring)
+ input user_clock,
+
+ // Mask revision/User project ID
+ input [31:0] mask_rev_in,
+
+ // SPI flash management (management SoC side)
+ input spimemio_flash_csb,
+ input spimemio_flash_clk,
+ input spimemio_flash_io0_oeb,
+ input spimemio_flash_io1_oeb,
+ input spimemio_flash_io2_oeb,
+ input spimemio_flash_io3_oeb,
+ input spimemio_flash_io0_do,
+ input spimemio_flash_io1_do,
+ input spimemio_flash_io2_do,
+ input spimemio_flash_io3_do,
+ output spimemio_flash_io0_di,
+ output spimemio_flash_io1_di,
+ output spimemio_flash_io2_di,
+ output spimemio_flash_io3_di,
+
+ // Debug interface (routes to first GPIO) from management SoC
+ output debug_in,
+ input debug_out,
+ input debug_oeb,
+
+ // SPI flash management (padframe side)
+ // (io2 and io3 are part of GPIO array, not dedicated pads)
+ output pad_flash_csb,
+ output pad_flash_csb_oeb,
+ output pad_flash_clk,
+ output pad_flash_clk_oeb,
+ output pad_flash_io0_oeb,
+ output pad_flash_io1_oeb,
+ output pad_flash_io0_ieb,
+ output pad_flash_io1_ieb,
+ output pad_flash_io0_do,
+ output pad_flash_io1_do,
+ input pad_flash_io0_di,
+ input pad_flash_io1_di,
+
+ output sram_ro_clk,
+ output sram_ro_csb,
+ output [7:0] sram_ro_addr,
+ input [31:0] sram_ro_data,
+
+ // System signal monitoring
+ input usr1_vcc_pwrgood,
+ input usr2_vcc_pwrgood,
+ input usr1_vdd_pwrgood,
+ input usr2_vdd_pwrgood
+);
+
+ localparam OEB = 1; // Offset of output enable (bar) in shift register
+ localparam INP_DIS = 3; // Offset of input disable in shift register
+
+ reg [25:0] pll_trim;
+ reg [4:0] pll_div;
+ reg [2:0] pll_sel;
+ reg [2:0] pll90_sel;
+ reg pll_dco_ena;
+ reg pll_ena;
+ reg pll_bypass;
+ reg reset_reg;
+ reg irq_spi;
+ reg serial_bb_clock;
+ reg serial_bb_load;
+ reg serial_bb_resetn;
+ reg serial_bb_data_1;
+ reg serial_bb_data_2;
+ reg serial_bb_enable;
+ reg serial_xfer;
+ reg hkspi_disable;
+
+ reg sram_ro_clk;
+ reg sram_ro_csb;
+ reg [7:0] sram_ro_addr;
+
+ reg clk1_output_dest;
+ reg clk2_output_dest;
+ reg trap_output_dest;
+ reg irq_1_inputsrc;
+ reg irq_2_inputsrc;
+
+ reg [IO_CTRL_BITS-1:0] gpio_configure [`MPRJ_IO_PADS-1:0];
+ reg [`MPRJ_IO_PADS-1:0] mgmt_gpio_data;
+ reg [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out;
+
+ /* mgmt_gpio_data_buf holds the lower bits during a back-door
+ * write to GPIO data so that all 32 bits can update at once.
+ */
+ reg [23:0] mgmt_gpio_data_buf;
+
+ wire usr1_vcc_pwrgood;
+ wire usr2_vcc_pwrgood;
+ wire usr1_vdd_pwrgood;
+ wire usr2_vdd_pwrgood;
+
+ wire [7:0] odata;
+ wire [7:0] idata;
+ wire [7:0] iaddr;
+
+ wire [2:0] irq;
+
+ wire trap;
+ wire rdstb;
+ wire wrstb;
+ wire pass_thru_mgmt; // Mode detected by housekeeping_spi
+ wire pass_thru_mgmt_delay;
+ wire pass_thru_user; // Mode detected by housekeeping_spi
+ wire pass_thru_user_delay;
+ wire pass_thru_mgmt_reset;
+ wire pass_thru_user_reset;
+ wire sdo;
+ wire sdo_enb;
+
+ wire [7:0] caddr; // Combination of SPI address and back door address
+ wire [7:0] cdata; // Combination of SPI data and back door data
+ wire cwstb; // Combination of SPI write strobe and back door write strobe
+ wire csclk; // Combination of SPI SCK and back door access trigger
+
+ wire [31:0] sram_ro_data;
+
+ // Housekeeping side 3-wire interface to GPIOs (see below)
+ wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out_pre;
+
+ // Pass-through mode handling. Signals may only be applied when the
+ // core processor is in reset.
+
+ assign reset = (pass_thru_mgmt_reset) ? 1'b1 : reset_reg;
+
+ // Invert wb_rstn_i
+ wire wb_rst_i;
+ assign wb_rst_i = ~wb_rstn_i;
+
+ // Handle the management-side control of the GPIO pins. All but the
+ // first and last three GPIOs (0, 1 and 35 to 37) are one-pin interfaces with
+ // a single I/O pin whose direction is determined by the local OEB signal.
+ // The other five are straight-through connections of the 3-wire interface.
+
+ assign mgmt_gpio_out[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3] =
+ mgmt_gpio_out_pre[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-3];
+ assign mgmt_gpio_out[1:0] = mgmt_gpio_out_pre[1:0];
+
+ genvar i;
+
+ // This implements high-impedence buffers on the GPIO outputs other than
+ // the first and last two GPIOs so that these pins can be tied together
+ // at the top level to create the single-wire interface on those GPIOs.
+ generate
+ for (i = 2; i < `MPRJ_IO_PADS-3; i = i + 1) begin
+ assign mgmt_gpio_out[i] = mgmt_gpio_oeb[i] ? 1'bz : mgmt_gpio_out_pre[i];
+ end
+ endgenerate
+
+ // Pass-through mode. Housekeeping SPI signals get inserted
+ // between the management SoC and the flash SPI I/O.
+
+ assign pad_flash_csb = (pass_thru_mgmt_delay) ? mgmt_gpio_in[3] : spimemio_flash_csb;
+ assign pad_flash_csb_oeb = (pass_thru_mgmt_delay) ? 1'b0 : (~porb ? 1'b1 : 1'b0);
+ assign pad_flash_clk = (pass_thru_mgmt) ? mgmt_gpio_in[4] : spimemio_flash_clk;
+ assign pad_flash_clk_oeb = (pass_thru_mgmt) ? 1'b0 : (~porb ? 1'b1 : 1'b0);
+ assign pad_flash_io0_oeb = (pass_thru_mgmt_delay) ? 1'b0 : spimemio_flash_io0_oeb;
+ assign pad_flash_io1_oeb = (pass_thru_mgmt) ? 1'b1 : spimemio_flash_io1_oeb;
+ assign pad_flash_io0_ieb = (pass_thru_mgmt_delay) ? 1'b1 : ~spimemio_flash_io0_oeb;
+ assign pad_flash_io1_ieb = (pass_thru_mgmt) ? 1'b0 : ~spimemio_flash_io1_oeb;
+ assign pad_flash_io0_do = (pass_thru_mgmt_delay) ? mgmt_gpio_in[2] : spimemio_flash_io0_do;
+ assign pad_flash_io1_do = spimemio_flash_io1_do;
+ assign spimemio_flash_io0_di = (pass_thru_mgmt_delay) ? 1'b0 : pad_flash_io0_di;
+ assign spimemio_flash_io1_di = (pass_thru_mgmt) ? 1'b0 : pad_flash_io1_di;
+
+ // Wishbone bus "back door" to SPI registers. This section of code
+ // (1) Maps SPI byte addresses to memory map 32-bit addresses
+ // (2) Applies signals to the housekeeping SPI to mux in the SPI address,
+ // clock, and write strobe. This is done carefully and slowly to
+ // avoid glitching on the SCK line and to avoid forcing the
+ // housekeeping module to keep up with the core clock timing.
+
+ wire sys_select; // System monitoring memory map address selected
+ wire gpio_select; // GPIO configuration memory map address selected
+ wire spi_select; // SPI back door memory map address selected
+
+ // Wishbone Back Door. This is a simple interface making use of the
+ // housekeeping SPI protocol. The housekeeping SPI uses byte-wide
+ // data, so this interface will stall the processor by holding wb_ack_o
+ // low until all bytes have been transferred between the processor and
+ // housekeeping SPI.
+
+ reg [3:0] wbbd_state;
+ reg [7:0] wbbd_addr; /* SPI address translated from WB */
+ reg [7:0] wbbd_data; /* SPI data translated from WB */
+ reg wbbd_sck; /* wishbone access trigger (back-door clock) */
+ reg wbbd_write; /* wishbone write trigger (back-door strobe) */
+ reg wbbd_busy; /* Raised during a wishbone read or write */
+ reg wb_ack_o; /* acknowledge signal back to wishbone bus */
+ reg [31:0] wb_dat_o; /* data output to wishbone bus */
+
+ // This defines a state machine that accesses the SPI registers through
+ // the back door wishbone interface. The process is relatively slow
+ // since the SPI data are byte-wide, so four individual accesses are
+ // made to read 4 bytes from the SPI to fill data on the wishbone bus
+ // before sending ACK and letting the processor continue.
+
+ `define WBBD_IDLE 4'h0 /* Back door access is idle */
+ `define WBBD_SETUP0 4'h1 /* Apply address and data for byte 1 of 4 */
+ `define WBBD_RW0 4'h2 /* Latch data for byte 1 of 4 */
+ `define WBBD_SETUP1 4'h3 /* Apply address and data for byte 2 of 4 */
+ `define WBBD_RW1 4'h4 /* Latch data for byte 2 of 4 */
+ `define WBBD_SETUP2 4'h5 /* Apply address and data for byte 3 of 4 */
+ `define WBBD_RW2 4'h6 /* Latch data for byte 3 of 4 */
+ `define WBBD_SETUP3 4'h7 /* Apply address and data for byte 4 of 4 */
+ `define WBBD_RW3 4'h8 /* Latch data for byte 4 of 4 */
+ `define WBBD_DONE 4'h9 /* Send ACK back to wishbone */
+
+ assign sys_select = (wb_adr_i[31:8] == SYS_BASE_ADR[31:8]);
+ assign gpio_select = (wb_adr_i[31:8] == GPIO_BASE_ADR[31:8]);
+ assign spi_select = (wb_adr_i[31:8] == SPI_BASE_ADR[31:8]);
+
+ /* Register bit to SPI address mapping */
+
+ function [7:0] fdata(input [7:0] address);
+ begin
+ case (address)
+ /* Housekeeping SPI Protocol */
+ 8'h00 : fdata = 8'h00; // SPI status (fixed)
+
+ /* Status and Identification */
+ 8'h01 : fdata = {4'h0, mfgr_id[11:8]}; // Manufacturer ID (fixed)
+ 8'h02 : fdata = mfgr_id[7:0]; // Manufacturer ID (fixed)
+ 8'h03 : fdata = prod_id; // Product ID (fixed)
+ 8'h04 : fdata = mask_rev[31:24]; // Mask rev (via programmed)
+ 8'h05 : fdata = mask_rev[23:16]; // Mask rev (via programmed)
+ 8'h06 : fdata = mask_rev[15:8]; // Mask rev (via programmed)
+ 8'h07 : fdata = mask_rev[7:0]; // Mask rev (via programmed)
+
+ /* Clocking control */
+ 8'h08 : fdata = {6'b000000, pll_dco_ena, pll_ena};
+ 8'h09 : fdata = {7'b0000000, pll_bypass};
+ 8'h0a : fdata = {7'b0000000, irq_spi};
+ 8'h0b : fdata = {7'b0000000, reset};
+ 8'h0c : fdata = {7'b0000000, trap}; // CPU trap state
+ 8'h0d : fdata = pll_trim[7:0];
+ 8'h0e : fdata = pll_trim[15:8];
+ 8'h0f : fdata = pll_trim[23:16];
+ 8'h10 : fdata = {6'b000000, pll_trim[25:24]};
+ 8'h11 : fdata = {2'b00, pll90_sel, pll_sel};
+ 8'h12 : fdata = {3'b000, pll_div};
+
+ // GPIO Control (bit bang and automatic)
+ // NOTE: "serial_busy" is the read-back signal occupying the same
+ // address/bit as "serial_xfer".
+ 8'h13 : fdata = {1'b0, serial_data_2, serial_data_1, serial_bb_clock,
+ serial_bb_load, serial_bb_resetn, serial_bb_enable,
+ serial_busy};
+
+ /* To be added: SRAM read-only port (registers 14 to 19) */
+ 8'h14 : fdata = {6'b000000, sram_ro_clk, sram_ro_csb};
+ 8'h15 : fdata = sram_ro_addr;
+ 8'h16 : fdata = sram_ro_data[31:24];
+ 8'h17 : fdata = sram_ro_data[23:16];
+ 8'h18 : fdata = sram_ro_data[15:8];
+ 8'h19 : fdata = sram_ro_data[7:0];
+
+ /* System monitoring */
+ 8'h1a : fdata = {4'b0000, usr1_vcc_pwrgood, usr2_vcc_pwrgood,
+ usr1_vdd_pwrgood, usr2_vdd_pwrgood};
+ 8'h1b : fdata = {5'b00000, clk1_output_dest, clk2_output_dest,
+ trap_output_dest};
+ 8'h1c : fdata = {6'b000000, irq_2_inputsrc, irq_1_inputsrc};
+
+ /* GPIO Configuration */
+ 8'h1d : fdata = {3'b000, gpio_configure[0][12:8]};
+ 8'h1e : fdata = gpio_configure[0][7:0];
+ 8'h1f : fdata = {3'b000, gpio_configure[1][12:8]};
+ 8'h20 : fdata = gpio_configure[1][7:0];
+ 8'h21 : fdata = {3'b000, gpio_configure[2][12:8]};
+ 8'h22 : fdata = gpio_configure[2][7:0];
+ 8'h23 : fdata = {3'b000, gpio_configure[3][12:8]};
+ 8'h24 : fdata = gpio_configure[3][7:0];
+ 8'h25 : fdata = {3'b000, gpio_configure[4][12:8]};
+ 8'h26 : fdata = gpio_configure[4][7:0];
+ 8'h27 : fdata = {3'b000, gpio_configure[5][12:8]};
+ 8'h28 : fdata = gpio_configure[5][7:0];
+ 8'h29 : fdata = {3'b000, gpio_configure[6][12:8]};
+ 8'h2a : fdata = gpio_configure[6][7:0];
+ 8'h2b : fdata = {3'b000, gpio_configure[7][12:8]};
+ 8'h2c : fdata = gpio_configure[7][7:0];
+ 8'h2d : fdata = {3'b000, gpio_configure[8][12:8]};
+ 8'h2e : fdata = gpio_configure[8][7:0];
+ 8'h2f : fdata = {3'b000, gpio_configure[9][12:8]};
+ 8'h30 : fdata = gpio_configure[9][7:0];
+ 8'h31 : fdata = {3'b000, gpio_configure[10][12:8]};
+ 8'h32 : fdata = gpio_configure[10][7:0];
+ 8'h33 : fdata = {3'b000, gpio_configure[11][12:8]};
+ 8'h34 : fdata = gpio_configure[11][7:0];
+ 8'h35 : fdata = {3'b000, gpio_configure[12][12:8]};
+ 8'h36 : fdata = gpio_configure[12][7:0];
+ 8'h37 : fdata = {3'b000, gpio_configure[13][12:8]};
+ 8'h38 : fdata = gpio_configure[13][7:0];
+ 8'h39 : fdata = {3'b000, gpio_configure[14][12:8]};
+ 8'h3a : fdata = gpio_configure[14][7:0];
+ 8'h3b : fdata = {3'b000, gpio_configure[15][12:8]};
+ 8'h3c : fdata = gpio_configure[15][7:0];
+ 8'h3d : fdata = {3'b000, gpio_configure[16][12:8]};
+ 8'h3e : fdata = gpio_configure[16][7:0];
+ 8'h3f : fdata = {3'b000, gpio_configure[17][12:8]};
+ 8'h40 : fdata = gpio_configure[17][7:0];
+ 8'h41 : fdata = {3'b000, gpio_configure[18][12:8]};
+ 8'h42 : fdata = gpio_configure[18][7:0];
+ 8'h43 : fdata = {3'b000, gpio_configure[19][12:8]};
+ 8'h44 : fdata = gpio_configure[19][7:0];
+ 8'h45 : fdata = {3'b000, gpio_configure[20][12:8]};
+ 8'h46 : fdata = gpio_configure[20][7:0];
+ 8'h47 : fdata = {3'b000, gpio_configure[21][12:8]};
+ 8'h48 : fdata = gpio_configure[21][7:0];
+ 8'h49 : fdata = {3'b000, gpio_configure[22][12:8]};
+ 8'h4a : fdata = gpio_configure[22][7:0];
+ 8'h4b : fdata = {3'b000, gpio_configure[23][12:8]};
+ 8'h4c : fdata = gpio_configure[23][7:0];
+ 8'h4d : fdata = {3'b000, gpio_configure[24][12:8]};
+ 8'h4e : fdata = gpio_configure[24][7:0];
+ 8'h4f : fdata = {3'b000, gpio_configure[25][12:8]};
+ 8'h50 : fdata = gpio_configure[25][7:0];
+ 8'h51 : fdata = {3'b000, gpio_configure[26][12:8]};
+ 8'h52 : fdata = gpio_configure[26][7:0];
+ 8'h53 : fdata = {3'b000, gpio_configure[27][12:8]};
+ 8'h54 : fdata = gpio_configure[27][7:0];
+ 8'h55 : fdata = {3'b000, gpio_configure[28][12:8]};
+ 8'h56 : fdata = gpio_configure[28][7:0];
+ 8'h57 : fdata = {3'b000, gpio_configure[29][12:8]};
+ 8'h58 : fdata = gpio_configure[29][7:0];
+ 8'h59 : fdata = {3'b000, gpio_configure[30][12:8]};
+ 8'h5a : fdata = gpio_configure[30][7:0];
+ 8'h5b : fdata = {3'b000, gpio_configure[31][12:8]};
+ 8'h5c : fdata = gpio_configure[31][7:0];
+ 8'h5d : fdata = {3'b000, gpio_configure[32][12:8]};
+ 8'h5e : fdata = gpio_configure[32][7:0];
+ 8'h5f : fdata = {3'b000, gpio_configure[33][12:8]};
+ 8'h60 : fdata = gpio_configure[33][7:0];
+ 8'h61 : fdata = {3'b000, gpio_configure[34][12:8]};
+ 8'h62 : fdata = gpio_configure[34][7:0];
+ 8'h63 : fdata = {3'b000, gpio_configure[35][12:8]};
+ 8'h64 : fdata = gpio_configure[35][7:0];
+ 8'h65 : fdata = {3'b000, gpio_configure[36][12:8]};
+ 8'h66 : fdata = gpio_configure[36][7:0];
+ 8'h67 : fdata = {3'b000, gpio_configure[37][12:8]};
+ 8'h68 : fdata = gpio_configure[37][7:0];
+
+ // GPIO Data
+ 8'h69 : fdata = {2'b00, mgmt_gpio_in[`MPRJ_IO_PADS-1:32]};
+ 8'h6a : fdata = mgmt_gpio_in[31:24];
+ 8'h6b : fdata = mgmt_gpio_in[23:16];
+ 8'h6c : fdata = mgmt_gpio_in[15:8];
+ 8'h6d : fdata = mgmt_gpio_in[7:0];
+
+ // Power Control (reserved)
+ 8'h6e : fdata = {4'b0000, pwr_ctrl_out};
+
+ // Housekeeping SPI system disable
+ 8'h6f : fdata = {7'b0000000, hkspi_disable};
+
+ default: fdata = 8'h00;
+ endcase
+ end
+ endfunction
+
+ /* Memory map address to SPI address translation for back door access */
+ /* (see doc/memory_map.txt) */
+
+ wire [11:0] gpio_adr = GPIO_BASE_ADR[23:12];
+ wire [11:0] sys_adr = SYS_BASE_ADR[23:12];
+ wire [11:0] spi_adr = SPI_BASE_ADR[23:12];
+
+ function [7:0] spiaddr(input [31:0] wbaddress);
+ begin
+ /* Address taken from lower 8 bits and upper 4 bits of the 32-bit */
+ /* wishbone address. */
+ case ({wbaddress[23:20], wbaddress[7:0]})
+ spi_adr | 12'h000 : spiaddr = 8'h00; // SPI status (reserved)
+ spi_adr | 12'h004 : spiaddr = 8'h03; // product ID
+ spi_adr | 12'h005 : spiaddr = 8'h02; // Manufacturer ID (low)
+ spi_adr | 12'h006 : spiaddr = 8'h01; // Manufacturer ID (high)
+ spi_adr | 12'h008 : spiaddr = 8'h07; // User project ID (low)
+ spi_adr | 12'h009 : spiaddr = 8'h06; // User project ID .
+ spi_adr | 12'h00a : spiaddr = 8'h05; // User project ID .
+ spi_adr | 12'h00b : spiaddr = 8'h04; // User project ID (high)
+
+ spi_adr | 12'h00c : spiaddr = 8'h08; // PLL enables
+ spi_adr | 12'h010 : spiaddr = 8'h09; // PLL bypass
+ spi_adr | 12'h014 : spiaddr = 8'h0a; // IRQ
+ spi_adr | 12'h018 : spiaddr = 8'h0b; // Reset
+ spi_adr | 12'h028 : spiaddr = 8'h0c; // CPU trap state
+ spi_adr | 12'h01f : spiaddr = 8'h10; // PLL trim
+ spi_adr | 12'h01e : spiaddr = 8'h0f; // PLL trim
+ spi_adr | 12'h01d : spiaddr = 8'h0e; // PLL trim
+ spi_adr | 12'h01c : spiaddr = 8'h0d; // PLL trim
+ spi_adr | 12'h020 : spiaddr = 8'h11; // PLL source
+ spi_adr | 12'h024 : spiaddr = 8'h12; // PLL divider
+
+ spi_adr | 12'h02c : spiaddr = 8'h19; // SRAM read-only data
+ spi_adr | 12'h02d : spiaddr = 8'h18; // SRAM read-only data
+ spi_adr | 12'h02e : spiaddr = 8'h17; // SRAM read-only data
+ spi_adr | 12'h02f : spiaddr = 8'h16; // SRAM read-only data
+ spi_adr | 12'h030 : spiaddr = 8'h15; // SRAM read-only address
+ spi_adr | 12'h034 : spiaddr = 8'h14; // SRAM read-only control
+
+ gpio_adr | 12'h000 : spiaddr = 8'h13; // GPIO control
+
+ /* To be added: SRAM read-only interface */
+
+ sys_adr | 12'h000 : spiaddr = 8'h1a; // Power monitor
+ sys_adr | 12'h004 : spiaddr = 8'h1b; // Output redirect
+ sys_adr | 12'h00c : spiaddr = 8'h1c; // Input redirect
+
+ gpio_adr | 12'h025 : spiaddr = 8'h1d; // GPIO configuration
+ gpio_adr | 12'h024 : spiaddr = 8'h1e;
+ gpio_adr | 12'h029 : spiaddr = 8'h1f;
+ gpio_adr | 12'h028 : spiaddr = 8'h20;
+ gpio_adr | 12'h02d : spiaddr = 8'h21;
+ gpio_adr | 12'h02c : spiaddr = 8'h22;
+ gpio_adr | 12'h031 : spiaddr = 8'h23;
+ gpio_adr | 12'h030 : spiaddr = 8'h24;
+ gpio_adr | 12'h035 : spiaddr = 8'h25;
+ gpio_adr | 12'h034 : spiaddr = 8'h26;
+ gpio_adr | 12'h039 : spiaddr = 8'h27;
+ gpio_adr | 12'h038 : spiaddr = 8'h28;
+ gpio_adr | 12'h03d : spiaddr = 8'h29;
+ gpio_adr | 12'h03c : spiaddr = 8'h2a;
+ gpio_adr | 12'h041 : spiaddr = 8'h2b;
+ gpio_adr | 12'h040 : spiaddr = 8'h2c;
+ gpio_adr | 12'h045 : spiaddr = 8'h2d;
+ gpio_adr | 12'h044 : spiaddr = 8'h2e;
+ gpio_adr | 12'h049 : spiaddr = 8'h2f;
+ gpio_adr | 12'h048 : spiaddr = 8'h30;
+ gpio_adr | 12'h04d : spiaddr = 8'h31;
+ gpio_adr | 12'h04c : spiaddr = 8'h32;
+ gpio_adr | 12'h051 : spiaddr = 8'h33;
+ gpio_adr | 12'h050 : spiaddr = 8'h34;
+ gpio_adr | 12'h055 : spiaddr = 8'h35;
+ gpio_adr | 12'h054 : spiaddr = 8'h36;
+ gpio_adr | 12'h059 : spiaddr = 8'h37;
+ gpio_adr | 12'h058 : spiaddr = 8'h38;
+ gpio_adr | 12'h05d : spiaddr = 8'h39;
+ gpio_adr | 12'h05c : spiaddr = 8'h3a;
+ gpio_adr | 12'h061 : spiaddr = 8'h3b;
+ gpio_adr | 12'h060 : spiaddr = 8'h3c;
+ gpio_adr | 12'h065 : spiaddr = 8'h3d;
+ gpio_adr | 12'h064 : spiaddr = 8'h3e;
+ gpio_adr | 12'h069 : spiaddr = 8'h3f;
+ gpio_adr | 12'h068 : spiaddr = 8'h40;
+ gpio_adr | 12'h06d : spiaddr = 8'h41;
+ gpio_adr | 12'h06c : spiaddr = 8'h42;
+ gpio_adr | 12'h071 : spiaddr = 8'h43;
+ gpio_adr | 12'h070 : spiaddr = 8'h44;
+ gpio_adr | 12'h075 : spiaddr = 8'h45;
+ gpio_adr | 12'h074 : spiaddr = 8'h46;
+ gpio_adr | 12'h079 : spiaddr = 8'h47;
+ gpio_adr | 12'h078 : spiaddr = 8'h48;
+ gpio_adr | 12'h07d : spiaddr = 8'h49;
+ gpio_adr | 12'h07c : spiaddr = 8'h4a;
+ gpio_adr | 12'h081 : spiaddr = 8'h4b;
+ gpio_adr | 12'h080 : spiaddr = 8'h4c;
+ gpio_adr | 12'h085 : spiaddr = 8'h4d;
+ gpio_adr | 12'h084 : spiaddr = 8'h4e;
+ gpio_adr | 12'h089 : spiaddr = 8'h4f;
+ gpio_adr | 12'h088 : spiaddr = 8'h50;
+ gpio_adr | 12'h08d : spiaddr = 8'h51;
+ gpio_adr | 12'h08c : spiaddr = 8'h52;
+ gpio_adr | 12'h091 : spiaddr = 8'h53;
+ gpio_adr | 12'h090 : spiaddr = 8'h54;
+ gpio_adr | 12'h095 : spiaddr = 8'h55;
+ gpio_adr | 12'h094 : spiaddr = 8'h56;
+ gpio_adr | 12'h099 : spiaddr = 8'h57;
+ gpio_adr | 12'h098 : spiaddr = 8'h58;
+ gpio_adr | 12'h09d : spiaddr = 8'h59;
+ gpio_adr | 12'h09c : spiaddr = 8'h5a;
+ gpio_adr | 12'h0a1 : spiaddr = 8'h5b;
+ gpio_adr | 12'h0a0 : spiaddr = 8'h5c;
+ gpio_adr | 12'h0a5 : spiaddr = 8'h5d;
+ gpio_adr | 12'h0a4 : spiaddr = 8'h5e;
+ gpio_adr | 12'h0a9 : spiaddr = 8'h5f;
+ gpio_adr | 12'h0a8 : spiaddr = 8'h60;
+ gpio_adr | 12'h0ad : spiaddr = 8'h61;
+ gpio_adr | 12'h0ac : spiaddr = 8'h62;
+ gpio_adr | 12'h0b1 : spiaddr = 8'h63;
+ gpio_adr | 12'h0b0 : spiaddr = 8'h64;
+ gpio_adr | 12'h0b5 : spiaddr = 8'h65;
+ gpio_adr | 12'h0b4 : spiaddr = 8'h66;
+ gpio_adr | 12'h0b9 : spiaddr = 8'h67;
+ gpio_adr | 12'h0b8 : spiaddr = 8'h68;
+
+ gpio_adr | 12'h010 : spiaddr = 8'h69; // GPIO data (h)
+
+ gpio_adr | 12'h00f : spiaddr = 8'h6a; // GPIO data (l)
+ gpio_adr | 12'h00e : spiaddr = 8'h6b; // GPIO data (l)
+ gpio_adr | 12'h00d : spiaddr = 8'h6c; // GPIO data (l)
+ gpio_adr | 12'h00c : spiaddr = 8'h6d; // GPIO data (l)
+
+ gpio_adr | 12'h004 : spiaddr = 8'h6e; // Power control
+
+ sys_adr | 12'h010 : spiaddr = 8'h6f; // Housekeeping SPI disable
+
+ default : spiaddr = 8'h00;
+ endcase
+ end
+ endfunction
+
+ /* Wishbone back-door state machine and address translation */
+
+ always @(posedge wb_clk_i or posedge wb_rst_i) begin
+ if (wb_rst_i) begin
+ wbbd_sck <= 1'b0;
+ wbbd_write <= 1'b0;
+ wbbd_addr <= 8'd0;
+ wbbd_data <= 8'd0;
+ wbbd_busy <= 1'b0;
+ wb_ack_o <= 1'b0;
+ wbbd_state <= `WBBD_IDLE;
+ end else begin
+ case (wbbd_state)
+ `WBBD_IDLE: begin
+ wbbd_busy <= 1'b0;
+ if ((sys_select | gpio_select | spi_select) &&
+ wb_cyc_i && wb_stb_i) begin
+ wb_ack_o <= 1'b0;
+ wbbd_state <= `WBBD_SETUP0;
+ end
+ end
+ `WBBD_SETUP0: begin
+ wbbd_sck <= 1'b0;
+ wbbd_addr <= spiaddr(wb_adr_i);
+ if (wb_sel_i[0] & wb_we_i) begin
+ wbbd_data <= wb_dat_i[7:0];
+ end
+ wbbd_write <= wb_sel_i[0] & wb_we_i;
+ wbbd_busy <= 1'b1;
+
+ // If the SPI is being accessed and about to read or
+ // write a byte, then stall until the SPI is ready.
+ if (!spi_is_busy) begin
+ wbbd_state <= `WBBD_RW0;
+ end
+ end
+ `WBBD_RW0: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b1;
+ wb_dat_o[7:0] <= odata;
+ wbbd_state <= `WBBD_SETUP1;
+ end
+ `WBBD_SETUP1: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b0;
+ wbbd_addr <= spiaddr(wb_adr_i + 1);
+ if (wb_sel_i[1] & wb_we_i) begin
+ wbbd_data <= wb_dat_i[15:8];
+ end
+ wbbd_write <= wb_sel_i[1] & wb_we_i;
+ if (!spi_is_busy) begin
+ wbbd_state <= `WBBD_RW1;
+ end
+ end
+ `WBBD_RW1: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b1;
+ wb_dat_o[15:8] <= odata;
+ wbbd_state <= `WBBD_SETUP2;
+ end
+ `WBBD_SETUP2: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b0;
+ wbbd_addr <= spiaddr(wb_adr_i + 2);
+ if (wb_sel_i[2] & wb_we_i) begin
+ wbbd_data <= wb_dat_i[23:16];
+ end
+ wbbd_write <= wb_sel_i[2] & wb_we_i;
+ if (!spi_is_busy) begin
+ wbbd_state <= `WBBD_RW2;
+ end
+ end
+ `WBBD_RW2: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b1;
+ wb_dat_o[23:16] <= odata;
+ wbbd_state <= `WBBD_SETUP3;
+ end
+ `WBBD_SETUP3: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b0;
+ wbbd_addr <= spiaddr(wb_adr_i + 3);
+ if (wb_sel_i[3] & wb_we_i) begin
+ wbbd_data <= wb_dat_i[31:24];
+ end
+ wbbd_write <= wb_sel_i[3] & wb_we_i;
+ if (!spi_is_busy) begin
+ wbbd_state <= `WBBD_RW3;
+ end
+ end
+ `WBBD_RW3: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b1;
+ wb_dat_o[31:24] <= odata;
+ wb_ack_o <= 1'b1; // Release hold on wishbone bus
+ wbbd_state <= `WBBD_DONE;
+ end
+ `WBBD_DONE: begin
+ wbbd_busy <= 1'b1;
+ wbbd_sck <= 1'b0;
+ wb_ack_o <= 1'b0; // Reset for next access
+ wbbd_write <= 1'b0;
+ wbbd_state <= `WBBD_IDLE;
+ end
+ endcase
+ end
+ end
+
+ // Instantiate the SPI interface protocol module
+
+ housekeeping_spi hkspi (
+ .reset(~porb),
+ .SCK(mgmt_gpio_in[4]),
+ .SDI(mgmt_gpio_in[2]),
+ .CSB((spi_is_active) ? mgmt_gpio_in[3] : 1'b1),
+ .SDO(sdo),
+ .sdoenb(sdo_enb),
+ .idata(odata),
+ .odata(idata),
+ .oaddr(iaddr),
+ .rdstb(rdstb),
+ .wrstb(wrstb),
+ .pass_thru_mgmt(pass_thru_mgmt),
+ .pass_thru_mgmt_delay(pass_thru_mgmt_delay),
+ .pass_thru_user(pass_thru_user),
+ .pass_thru_user_delay(pass_thru_user_delay),
+ .pass_thru_mgmt_reset(pass_thru_mgmt_reset),
+ .pass_thru_user_reset(pass_thru_user_reset)
+ );
+
+ // SPI is considered active when the GPIO for CSB is set to input and
+ // CSB is low. SPI is considered "busy" when rdstb or wrstb are high,
+ // indicating that the SPI will read or write a byte on the next SCK
+ // transition.
+
+ wire spi_is_enabled = (~gpio_configure[3][INP_DIS]) & (~hkspi_disable);
+ wire spi_is_active = spi_is_enabled && (mgmt_gpio_in[3] == 1'b0);
+ wire spi_is_busy = spi_is_active && (rdstb || wrstb);
+
+ // GPIO data handling to and from the management SoC
+
+ assign mgmt_gpio_out_pre[37] = (qspi_enabled) ? spimemio_flash_io3_do :
+ mgmt_gpio_data[37];
+ assign mgmt_gpio_out_pre[36] = (qspi_enabled) ? spimemio_flash_io2_do :
+ mgmt_gpio_data[36];
+
+ assign mgmt_gpio_oeb[37] = (qspi_enabled) ? spimemio_flash_io3_oeb :
+ ~gpio_configure[37][INP_DIS];
+ assign mgmt_gpio_oeb[36] = (qspi_enabled) ? spimemio_flash_io2_oeb :
+ ~gpio_configure[36][INP_DIS];
+ assign mgmt_gpio_oeb[35] = (spi_enabled) ? spi_sdoenb :
+ ~gpio_configure[35][INP_DIS];
+
+ // NOTE: Ignored by spimemio module when QSPI disabled, so they do not
+ // need any exception when qspi_enabled == 1.
+ assign spimemio_flash_io3_di = mgmt_gpio_in[37];
+ assign spimemio_flash_io2_di = mgmt_gpio_in[36];
+
+ // SPI master is assigned to the other 4 bits of the data high word.
+ assign mgmt_gpio_out_pre[32] = (spi_enabled) ? spi_sck : mgmt_gpio_data[32];
+ assign mgmt_gpio_out_pre[33] = (spi_enabled) ? spi_csb : mgmt_gpio_data[33];
+ assign mgmt_gpio_out_pre[34] = mgmt_gpio_data[34];
+ assign mgmt_gpio_out_pre[35] = (spi_enabled) ? spi_sdo : mgmt_gpio_data[35];
+
+ assign mgmt_gpio_out_pre[31:16] = mgmt_gpio_data[31:16];
+ assign mgmt_gpio_out_pre[12:11] = mgmt_gpio_data[12:11];
+
+ assign mgmt_gpio_out_pre[10] = (pass_thru_user) ? mgmt_gpio_in[2]
+ : mgmt_gpio_data[10];
+ assign mgmt_gpio_out_pre[9] = (pass_thru_user) ? mgmt_gpio_in[4]
+ : mgmt_gpio_data[9];
+ assign mgmt_gpio_out_pre[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3]
+ : mgmt_gpio_data[8];
+
+ assign mgmt_gpio_out_pre[7] = mgmt_gpio_data[7];
+ assign mgmt_gpio_out_pre[6] = (uart_enabled) ? ser_tx : mgmt_gpio_data[6];
+ assign mgmt_gpio_out_pre[5:2] = mgmt_gpio_data[5:2];
+
+ // In pass-through modes, route SDO from the respective flash (user or
+ // management SoC) to the dedicated SDO pin (GPIO[1])
+
+ assign mgmt_gpio_out_pre[1] = (pass_thru_mgmt) ? pad_flash_io1_di :
+ (pass_thru_user) ? mgmt_gpio_in[11] :
+ (spi_is_active) ? sdo : mgmt_gpio_data[1];
+ assign mgmt_gpio_out_pre[0] = (debug_mode) ? debug_out : mgmt_gpio_data[0];
+
+ assign mgmt_gpio_oeb[1] = (spi_is_active) ? sdo_enb : ~gpio_configure[0][INP_DIS];
+ assign mgmt_gpio_oeb[0] = (debug_mode) ? debug_oeb : ~gpio_configure[0][INP_DIS];
+
+ assign ser_rx = (uart_enabled) ? mgmt_gpio_in[5] : 1'b0;
+ assign spi_sdi = (spi_enabled) ? mgmt_gpio_in[34] : 1'b0;
+ assign debug_in = (debug_mode) ? mgmt_gpio_in[0] : 1'b0;
+
+ /* These are disconnected, but apply a meaningful signal anyway */
+ generate
+ for (i = 2; i < `MPRJ_IO_PADS-3; i = i + 1) begin
+ assign mgmt_gpio_oeb[i] = ~gpio_configure[i][INP_DIS];
+ end
+ endgenerate
+
+ // System monitoring. Multiplex the clock and trap
+ // signals to the associated pad, and multiplex the irq signals
+ // from the associated pad, when the redirection is enabled. Note
+ // that the redirection is upstream of the user/managment multiplexing,
+ // so the pad being under control of the user area takes precedence
+ // over the system monitoring function.
+
+ assign mgmt_gpio_out_pre[15] = (clk2_output_dest == 1'b1) ? user_clock
+ : mgmt_gpio_data[15];
+ assign mgmt_gpio_out_pre[14] = (clk1_output_dest == 1'b1) ? wb_clk_i
+ : mgmt_gpio_data[14];
+ assign mgmt_gpio_out_pre[13] = (trap_output_dest == 1'b1) ? trap
+ : mgmt_gpio_data[13];
+
+ assign irq[0] = irq_spi;
+ assign irq[1] = (irq_1_inputsrc == 1'b1) ? mgmt_gpio_in[7] : 1'b0;
+ assign irq[2] = (irq_2_inputsrc == 1'b1) ? mgmt_gpio_in[12] : 1'b0;
+
+ // GPIO serial loader and GPIO management control
+
+`define GPIO_IDLE 2'b00
+`define GPIO_START 2'b01
+`define GPIO_XBYTE 2'b10
+`define GPIO_LOAD 2'b11
+
+ reg [3:0] xfer_count;
+ reg [4:0] pad_count_1;
+ reg [5:0] pad_count_2;
+ reg [1:0] xfer_state;
+
+ reg serial_clock_pre;
+ reg serial_resetn_pre;
+ reg serial_load_pre;
+ reg serial_busy;
+ wire serial_data_1;
+ wire serial_data_2;
+ wire serial_clock;
+ wire serial_resetn;
+ wire serial_load;
+ reg [IO_CTRL_BITS-1:0] serial_data_staging_1;
+ reg [IO_CTRL_BITS-1:0] serial_data_staging_2;
+
+ assign serial_clock = (serial_bb_enable == 1'b1) ?
+ serial_bb_clock : serial_clock_pre;
+ assign serial_resetn = (serial_bb_enable == 1'b1) ?
+ serial_bb_resetn : serial_resetn_pre;
+ assign serial_load = (serial_bb_enable == 1'b1) ?
+ serial_bb_load : serial_load_pre;
+
+ assign serial_data_1 = (serial_bb_enable == 1'b1) ?
+ serial_bb_data_1 : serial_data_staging_1[IO_CTRL_BITS-1];
+ assign serial_data_2 = (serial_bb_enable == 1'b1) ?
+ serial_bb_data_2 : serial_data_staging_2[IO_CTRL_BITS-1];
+
+ always @(posedge wb_clk_i or negedge porb) begin
+ if (porb == 1'b0) begin
+ xfer_state <= `GPIO_IDLE;
+ xfer_count <= 4'd0;
+ /* NOTE: This assumes that MPRJ_IO_PADS_1 and MPRJ_IO_PADS_2 are
+ * equal, because they get clocked the same number of cycles by
+ * the same clock signal. pad_count_2 gates the count for both.
+ */
+ pad_count_1 <= `MPRJ_IO_PADS_1 - 1;
+ pad_count_2 <= `MPRJ_IO_PADS_1;
+ serial_resetn_pre <= 1'b0;
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b0;
+ serial_data_staging_1 <= 0;
+ serial_data_staging_2 <= 0;
+ serial_busy <= 1'b0;
+
+ end else begin
+
+ serial_resetn_pre <= 1'b1;
+ case (xfer_state)
+ `GPIO_IDLE: begin
+ pad_count_1 <= `MPRJ_IO_PADS_1 - 1;
+ pad_count_2 <= `MPRJ_IO_PADS_1;
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b0;
+ if (serial_xfer == 1'b1) begin
+ xfer_state <= `GPIO_START;
+ serial_busy <= 1'b1;
+ end else begin
+ serial_busy <= 1'b0;
+ end
+ end
+ `GPIO_START: begin
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b0;
+ xfer_count <= 6'd0;
+ pad_count_1 <= pad_count_1 - 1;
+ pad_count_2 <= pad_count_2 + 1;
+ xfer_state <= `GPIO_XBYTE;
+ serial_data_staging_1 <= gpio_configure[pad_count_1];
+ serial_data_staging_2 <= gpio_configure[pad_count_2];
+ end
+ `GPIO_XBYTE: begin
+ serial_clock_pre <= ~serial_clock;
+ serial_load_pre <= 1'b0;
+ if (serial_clock == 1'b0) begin
+ if (xfer_count == IO_CTRL_BITS - 1) begin
+ xfer_count <= 4'd0;
+ if (pad_count_2 == `MPRJ_IO_PADS) begin
+ xfer_state <= `GPIO_LOAD;
+ end else begin
+ xfer_state <= `GPIO_START;
+ end
+ end else begin
+ xfer_count <= xfer_count + 1;
+ end
+ end else begin
+ serial_data_staging_1 <=
+ {serial_data_staging_1[IO_CTRL_BITS-2:0], 1'b0};
+ serial_data_staging_2 <=
+ {serial_data_staging_2[IO_CTRL_BITS-2:0], 1'b0};
+ end
+ end
+ `GPIO_LOAD: begin
+ xfer_count <= xfer_count + 1;
+
+ /* Load sequence: Pulse clock for final data shift in;
+ * Pulse the load strobe.
+ * Return to idle mode.
+ */
+ if (xfer_count == 4'd0) begin
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b0;
+ end else if (xfer_count == 4'd1) begin
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b1;
+ end else if (xfer_count == 4'd2) begin
+ serial_busy <= 1'b0;
+ serial_clock_pre <= 1'b0;
+ serial_load_pre <= 1'b0;
+ xfer_state <= `GPIO_IDLE;
+ end
+ end
+ endcase
+ end
+ end
+
+ // SPI Identification
+
+ wire [11:0] mfgr_id;
+ wire [7:0] prod_id;
+ wire [31:0] mask_rev;
+
+ assign mfgr_id = 12'h456; // Hard-coded
+ assign prod_id = 8'h11; // Hard-coded
+ assign mask_rev = mask_rev_in; // Copy in to out.
+
+ // SPI Data transfer protocol. The wishbone back door may only be
+ // used if the front door is closed (CSB is high or the CSB pin is
+ // not an input). The time to apply values for the back door access
+ // is limited to the clock cycle around the read or write from the
+ // wbbd state machine (see below).
+
+ assign caddr = (wbbd_busy) ? wbbd_addr : iaddr;
+ assign csclk = (wbbd_busy) ? wbbd_sck : ((spi_is_active) ? mgmt_gpio_in[4] : 1'b0);
+ assign cdata = (wbbd_busy) ? wbbd_data : idata;
+ assign cwstb = (wbbd_busy) ? wbbd_write : wrstb;
+
+ assign odata = fdata(caddr);
+
+ // Register mapping and I/O to SPI interface module
+
+ integer j;
+
+ always @(posedge csclk or negedge porb) begin
+ if (porb == 1'b0) begin
+ // Set trim for PLL at (almost) slowest rate (~90MHz). However,
+ // pll_trim[12] must be set to zero for proper startup.
+ pll_trim <= 26'b11111111111110111111111111;
+ pll_sel <= 3'b010; // Default output divider divide-by-2
+ pll90_sel <= 3'b010; // Default secondary output divider divide-by-2
+ pll_div <= 5'b00100; // Default feedback divider divide-by-8
+ pll_dco_ena <= 1'b1; // Default free-running PLL
+ pll_ena <= 1'b0; // Default PLL turned off
+ pll_bypass <= 1'b1; // Default bypass mode (don't use PLL)
+ irq_spi <= 1'b0;
+ reset_reg <= 1'b0;
+
+ // System monitoring signals
+ clk1_output_dest <= 1'b0;
+ clk2_output_dest <= 1'b0;
+ trap_output_dest <= 1'b0;
+ irq_1_inputsrc <= 1'b0;
+ irq_2_inputsrc <= 1'b0;
+
+ // GPIO Configuration, Data, and Control
+ // To-do: Get user project pad defaults from external inputs
+ // to be configured by user or at project generation time.
+ // Pads 1 to 4 are the SPI and considered critical startup
+ // infrastructure, and should not be altered from the defaults
+ // below. NOTE: These are not startup values, but they should
+ // match the startup values applied to the GPIO, or else the
+ // GPIO should be always triggered to load at startup.
+
+ for (j = 0; j < `MPRJ_IO_PADS; j=j+1) begin
+ if ((j < 2) || (j >= `MPRJ_IO_PADS - 2)) begin
+ gpio_configure[j] <= 'h1803;
+ end else begin
+ gpio_configure[j] <= 'h0403;
+ end
+ end
+
+ mgmt_gpio_data <= 'd0;
+ mgmt_gpio_data_buf <= 'd0;
+ serial_bb_enable <= 1'b0;
+ serial_bb_load <= 1'b0;
+ serial_bb_data_1 <= 1'b0;
+ serial_bb_data_2 <= 1'b0;
+ serial_bb_clock <= 1'b0;
+ serial_bb_resetn <= 1'b0;
+ serial_xfer <= 1'b0;
+ hkspi_disable <= 1'b0;
+
+ sram_ro_clk <= 1'b0;
+ sram_ro_csb <= 1'b1;
+ sram_ro_addr <= 8'h00;
+
+ end else begin
+ if (cwstb == 1'b1) begin
+ case (caddr)
+ /* Register 8'h00 is reserved for future use */
+ /* Registers 8'h01 to 8'h07 are read-only and cannot be written */
+ 8'h08: begin
+ pll_ena <= cdata[0];
+ pll_dco_ena <= cdata[1];
+ end
+ 8'h09: begin
+ pll_bypass <= cdata[0];
+ end
+ 8'h0a: begin
+ irq_spi <= cdata[0];
+ end
+ 8'h0b: begin
+ reset_reg <= cdata[0];
+ end
+
+ /* Register 0c (trap state) is read-only */
+
+ 8'h0d: begin
+ pll_trim[7:0] <= cdata;
+ end
+ 8'h0e: begin
+ pll_trim[15:8] <= cdata;
+ end
+ 8'h0f: begin
+ pll_trim[23:16] <= cdata;
+ end
+ 8'h10: begin
+ pll_trim[25:24] <= cdata[1:0];
+ end
+ 8'h11: begin
+ pll90_sel <= cdata[5:3];
+ pll_sel <= cdata[2:0];
+ end
+ 8'h12: begin
+ pll_div <= cdata[4:0];
+ end
+ 8'h13: begin
+ serial_bb_data_2 <= cdata[6];
+ serial_bb_data_1 <= cdata[5];
+ serial_bb_clock <= cdata[4];
+ serial_bb_load <= cdata[3];
+ serial_bb_resetn <= cdata[2];
+ serial_bb_enable <= cdata[1];
+ serial_xfer <= cdata[0];
+ end
+
+ /* To be done: Add SRAM read-only interface */
+ 8'h14: begin
+ sram_ro_clk <= cdata[1];
+ sram_ro_csb <= cdata[0];
+ end
+ 8'h15: begin
+ sram_ro_addr <= cdata;
+ end
+
+ /* Registers 16 to 19 (SRAM data) are read-only */
+
+ /* Register 1a (power monitor) is read-only */
+
+ 8'h1b: begin
+ clk1_output_dest <= cdata[2];
+ clk2_output_dest <= cdata[1];
+ trap_output_dest <= cdata[0];
+ end
+ 8'h1c: begin
+ irq_2_inputsrc <= cdata[1];
+ irq_1_inputsrc <= cdata[0];
+ end
+ 8'h1d: begin
+ gpio_configure[0][12:8] <= cdata[4:0];
+ end
+ 8'h1e: begin
+ gpio_configure[0][7:0] <= cdata;
+ end
+ 8'h1f: begin
+ gpio_configure[1][12:8] <= cdata[4:0];
+ end
+ 8'h20: begin
+ gpio_configure[1][7:0] <= cdata;
+ end
+ 8'h21: begin
+ gpio_configure[2][12:8] <= cdata[4:0];
+ end
+ 8'h22: begin
+ gpio_configure[2][7:0] <= cdata;
+ end
+ 8'h23: begin
+ gpio_configure[3][12:8] <= cdata[4:0];
+ end
+ 8'h24: begin
+ gpio_configure[3][7:0] <= cdata;
+ end
+ 8'h25: begin
+ gpio_configure[4][12:8] <= cdata[4:0];
+ end
+ 8'h26: begin
+ gpio_configure[4][7:0] <= cdata;
+ end
+ 8'h27: begin
+ gpio_configure[5][12:8] <= cdata[4:0];
+ end
+ 8'h28: begin
+ gpio_configure[5][7:0] <= cdata;
+ end
+ 8'h29: begin
+ gpio_configure[6][12:8] <= cdata[4:0];
+ end
+ 8'h2a: begin
+ gpio_configure[6][7:0] <= cdata;
+ end
+ 8'h2b: begin
+ gpio_configure[7][12:8] <= cdata[4:0];
+ end
+ 8'h2c: begin
+ gpio_configure[7][7:0] <= cdata;
+ end
+ 8'h2d: begin
+ gpio_configure[8][12:8] <= cdata[4:0];
+ end
+ 8'h2e: begin
+ gpio_configure[8][7:0] <= cdata;
+ end
+ 8'h2f: begin
+ gpio_configure[9][12:8] <= cdata[4:0];
+ end
+ 8'h30: begin
+ gpio_configure[9][7:0] <= cdata;
+ end
+ 8'h31: begin
+ gpio_configure[10][12:8] <= cdata[4:0];
+ end
+ 8'h32: begin
+ gpio_configure[10][7:0] <= cdata;
+ end
+ 8'h33: begin
+ gpio_configure[11][12:8] <= cdata[4:0];
+ end
+ 8'h34: begin
+ gpio_configure[11][7:0] <= cdata;
+ end
+ 8'h35: begin
+ gpio_configure[12][12:8] <= cdata[4:0];
+ end
+ 8'h36: begin
+ gpio_configure[12][7:0] <= cdata;
+ end
+ 8'h37: begin
+ gpio_configure[13][12:8] <= cdata[4:0];
+ end
+ 8'h38: begin
+ gpio_configure[13][7:0] <= cdata;
+ end
+ 8'h39: begin
+ gpio_configure[14][12:8] <= cdata[4:0];
+ end
+ 8'h3a: begin
+ gpio_configure[14][7:0] <= cdata;
+ end
+ 8'h3b: begin
+ gpio_configure[15][12:8] <= cdata[4:0];
+ end
+ 8'h3c: begin
+ gpio_configure[15][7:0] <= cdata;
+ end
+ 8'h3d: begin
+ gpio_configure[16][12:8] <= cdata[4:0];
+ end
+ 8'h3e: begin
+ gpio_configure[16][7:0] <= cdata;
+ end
+ 8'h3f: begin
+ gpio_configure[17][12:8] <= cdata[4:0];
+ end
+ 8'h40: begin
+ gpio_configure[17][7:0] <= cdata;
+ end
+ 8'h41: begin
+ gpio_configure[18][12:8] <= cdata[4:0];
+ end
+ 8'h42: begin
+ gpio_configure[18][7:0] <= cdata;
+ end
+ 8'h43: begin
+ gpio_configure[19][12:8] <= cdata[4:0];
+ end
+ 8'h44: begin
+ gpio_configure[19][7:0] <= cdata;
+ end
+ 8'h45: begin
+ gpio_configure[20][12:8] <= cdata[4:0];
+ end
+ 8'h46: begin
+ gpio_configure[20][7:0] <= cdata;
+ end
+ 8'h47: begin
+ gpio_configure[21][12:8] <= cdata[4:0];
+ end
+ 8'h48: begin
+ gpio_configure[21][7:0] <= cdata;
+ end
+ 8'h49: begin
+ gpio_configure[22][12:8] <= cdata[4:0];
+ end
+ 8'h4a: begin
+ gpio_configure[22][7:0] <= cdata;
+ end
+ 8'h4b: begin
+ gpio_configure[23][12:8] <= cdata[4:0];
+ end
+ 8'h4c: begin
+ gpio_configure[23][7:0] <= cdata;
+ end
+ 8'h4d: begin
+ gpio_configure[24][12:8] <= cdata[4:0];
+ end
+ 8'h4e: begin
+ gpio_configure[24][7:0] <= cdata;
+ end
+ 8'h4f: begin
+ gpio_configure[25][12:8] <= cdata[4:0];
+ end
+ 8'h50: begin
+ gpio_configure[25][7:0] <= cdata;
+ end
+ 8'h51: begin
+ gpio_configure[26][12:8] <= cdata[4:0];
+ end
+ 8'h52: begin
+ gpio_configure[26][7:0] <= cdata;
+ end
+ 8'h53: begin
+ gpio_configure[27][12:8] <= cdata[4:0];
+ end
+ 8'h54: begin
+ gpio_configure[27][7:0] <= cdata;
+ end
+ 8'h55: begin
+ gpio_configure[28][12:8] <= cdata[4:0];
+ end
+ 8'h56: begin
+ gpio_configure[28][7:0] <= cdata;
+ end
+ 8'h57: begin
+ gpio_configure[29][12:8] <= cdata[4:0];
+ end
+ 8'h58: begin
+ gpio_configure[29][7:0] <= cdata;
+ end
+ 8'h59: begin
+ gpio_configure[30][12:8] <= cdata[4:0];
+ end
+ 8'h5a: begin
+ gpio_configure[30][7:0] <= cdata;
+ end
+ 8'h5b: begin
+ gpio_configure[31][12:8] <= cdata[4:0];
+ end
+ 8'h5c: begin
+ gpio_configure[31][7:0] <= cdata;
+ end
+ 8'h5d: begin
+ gpio_configure[32][12:8] <= cdata[4:0];
+ end
+ 8'h5e: begin
+ gpio_configure[32][7:0] <= cdata;
+ end
+ 8'h5f: begin
+ gpio_configure[33][12:8] <= cdata[4:0];
+ end
+ 8'h60: begin
+ gpio_configure[33][7:0] <= cdata;
+ end
+ 8'h61: begin
+ gpio_configure[34][12:8] <= cdata[4:0];
+ end
+ 8'h62: begin
+ gpio_configure[34][7:0] <= cdata;
+ end
+ 8'h63: begin
+ gpio_configure[35][12:8] <= cdata[4:0];
+ end
+ 8'h64: begin
+ gpio_configure[35][7:0] <= cdata;
+ end
+ 8'h65: begin
+ gpio_configure[36][12:8] <= cdata[4:0];
+ end
+ 8'h66: begin
+ gpio_configure[36][7:0] <= cdata;
+ end
+ 8'h67: begin
+ gpio_configure[37][12:8] <= cdata[4:0];
+ end
+ 8'h68: begin
+ gpio_configure[37][7:0] <= cdata;
+ end
+ 8'h69: begin
+ mgmt_gpio_data[37:32] <= cdata[5:0];
+ end
+ 8'h6a: begin
+ /* NOTE: mgmt_gpio_data updates only on the */
+ /* upper byte write when writing through the */
+ /* wishbone back-door. This lets all bits */
+ /* update at the same time. */
+ if (spi_is_active) begin
+ mgmt_gpio_data[31:24] <= cdata;
+ end else begin
+ mgmt_gpio_data[31:0] <= {cdata, mgmt_gpio_data_buf};
+ end
+ end
+ 8'h6b: begin
+ if (spi_is_active) begin
+ mgmt_gpio_data[23:16] <= cdata;
+ end else begin
+ mgmt_gpio_data_buf[23:16] <= cdata;
+ end
+ end
+ 8'h6c: begin
+ if (spi_is_active) begin
+ mgmt_gpio_data[15:8] <= cdata;
+ end else begin
+ mgmt_gpio_data_buf[15:8] <= cdata;
+ end
+ end
+ 8'h6d: begin
+ if (spi_is_active) begin
+ mgmt_gpio_data[7:0] <= cdata;
+ end else begin
+ mgmt_gpio_data_buf[7:0] <= cdata;
+ end
+ end
+ 8'h6e: begin
+ pwr_ctrl_out <= cdata[3:0];
+ end
+ 8'h6f: begin
+ hkspi_disable <= cdata[0];
+ end
+ endcase // (caddr)
+ end else begin
+ serial_xfer <= 1'b0; // Serial transfer is self-resetting
+ irq_spi <= 1'b0; // IRQ is self-resetting
+ end
+ end
+ end
+endmodule // housekeeping
+
+`default_nettype wire
diff --git a/caravel/verilog/rtl/housekeeping_spi.v b/caravel/verilog/rtl/housekeeping_spi.v
new file mode 100644
index 0000000..1a5c737
--- /dev/null
+++ b/caravel/verilog/rtl/housekeeping_spi.v
@@ -0,0 +1,256 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+//-----------------------------------------------------------
+// SPI controller for Caravel
+//-----------------------------------------------------------
+// housekeeping_spi.v
+//------------------------------------------------------
+// General purpose SPI module for the Caravel chip
+//------------------------------------------------------
+// Written by Tim Edwards
+// efabless, inc., September 28, 2020
+//------------------------------------------------
+// This file is distributed free and open source
+//------------------------------------------------
+
+// SCK --- Clock input
+// SDI --- Data input
+// SDO --- Data output
+// CSB --- Chip select (sense negative)
+// idata --- Data from chip to transmit out, in 8 bits
+// odata --- Input data to chip, in 8 bits
+// addr --- Decoded address to upstream circuits
+// rdstb --- Read strobe, tells upstream circuit that data will be latched.
+// wrstb --- Write strobe, tells upstream circuit to latch odata.
+
+// Data format (general purpose):
+// 8 bit format
+// 1st byte: Command word (see below)
+// 2nd byte: Address word (register 0 to 255)
+// 3rd byte: Data word (value 0 to 255)
+
+// Command format:
+// 00000000 No operation
+// 10000000 Write until CSB raised
+// 01000000 Read until CSB raised
+// 11000000 Simultaneous read/write until CSB raised
+// 11000100 Pass-through read/write to management area flash SPI until CSB raised
+// 11000010 Pass-through read/write to user area flash SPI until CSB raised
+// wrnnn000 Read/write as above, for nnn = 1 to 7 bytes, then terminate
+
+// Lower three bits are reserved for future use.
+// All serial bytes are read and written msb first.
+
+// Fixed control and status registers
+
+// Address 0 is reserved and contains flags for SPI mode. This is
+// currently undefined and is always value 0.
+// Address 1 is reserved and contains manufacturer ID low 8 bits.
+// Address 2 is reserved and contains manufacturer ID high 4 bits.
+// Address 3 is reserved and contains product ID (8 bits).
+// Addresses 4 to 7 are reserved and contain the mask ID (32 bits).
+// Addresses 8 to 255 are available for general purpose use.
+
+`define COMMAND 3'b000
+`define ADDRESS 3'b001
+`define DATA 3'b010
+`define USERPASS 3'b100
+`define MGMTPASS 3'b101
+
+module housekeeping_spi(reset, SCK, SDI, CSB, SDO,
+ sdoenb, idata, odata, oaddr, rdstb, wrstb,
+ pass_thru_mgmt, pass_thru_mgmt_delay,
+ pass_thru_user, pass_thru_user_delay,
+ pass_thru_mgmt_reset, pass_thru_user_reset);
+
+ input reset;
+ input SCK;
+ input SDI;
+ input CSB;
+ output SDO;
+ output sdoenb;
+ input [7:0] idata;
+ output [7:0] odata;
+ output [7:0] oaddr;
+ output rdstb;
+ output wrstb;
+ output pass_thru_mgmt;
+ output pass_thru_mgmt_delay;
+ output pass_thru_user;
+ output pass_thru_user_delay;
+ output pass_thru_mgmt_reset;
+ output pass_thru_user_reset;
+
+ reg [7:0] addr;
+ reg wrstb;
+ reg rdstb;
+ reg sdoenb;
+ reg [2:0] state;
+ reg [2:0] count;
+ reg writemode;
+ reg readmode;
+ reg [2:0] fixed;
+ wire [7:0] odata;
+ reg [6:0] predata;
+ wire [7:0] oaddr;
+ reg [7:0] ldata;
+ reg pass_thru_mgmt;
+ reg pass_thru_mgmt_delay;
+ reg pre_pass_thru_mgmt;
+ reg pass_thru_user;
+ reg pass_thru_user_delay;
+ reg pre_pass_thru_user;
+ wire csb_reset;
+
+ assign odata = {predata, SDI};
+ assign oaddr = (state == `ADDRESS) ? {addr[6:0], SDI} : addr;
+ assign SDO = ldata[7];
+ assign csb_reset = CSB | reset;
+ assign pass_thru_mgmt_reset = pass_thru_mgmt_delay | pre_pass_thru_mgmt;
+ assign pass_thru_user_reset = pass_thru_user_delay | pre_pass_thru_user;
+
+ // Readback data is captured on the falling edge of SCK so that
+ // it is guaranteed valid at the next rising edge.
+ always @(negedge SCK or posedge csb_reset) begin
+ if (csb_reset == 1'b1) begin
+ wrstb <= 1'b0;
+ ldata <= 8'b00000000;
+ sdoenb <= 1'b1;
+ end else begin
+
+ // After CSB low, 1st SCK starts command
+
+ if (state == `DATA) begin
+ if (readmode == 1'b1) begin
+ sdoenb <= 1'b0;
+ if (count == 3'b000) begin
+ ldata <= idata;
+ end else begin
+ ldata <= {ldata[6:0], 1'b0}; // Shift out
+ end
+ end else begin
+ sdoenb <= 1'b1;
+ end
+
+ // Apply write strobe on SCK negative edge on the next-to-last
+ // data bit so that it updates data on the rising edge of SCK
+ // on the last data bit.
+
+ if (count == 3'b111) begin
+ if (writemode == 1'b1) begin
+ wrstb <= 1'b1;
+ end
+ end else begin
+ wrstb <= 1'b0;
+ end
+
+ end else if (state == `MGMTPASS || state == `USERPASS) begin
+ wrstb <= 1'b0;
+ sdoenb <= 1'b0;
+ end else begin
+ wrstb <= 1'b0;
+ sdoenb <= 1'b1;
+ end // ! state `DATA
+ end // ! csb_reset
+ end // always @ ~SCK
+
+ always @(posedge SCK or posedge csb_reset) begin
+ if (csb_reset == 1'b1) begin
+ // Default state on reset
+ addr <= 8'h00;
+ rdstb <= 1'b0;
+ predata <= 7'b0000000;
+ state <= `COMMAND;
+ count <= 3'b000;
+ readmode <= 1'b0;
+ writemode <= 1'b0;
+ fixed <= 3'b000;
+ pass_thru_mgmt <= 1'b0;
+ pass_thru_mgmt_delay <= 1'b0;
+ pre_pass_thru_mgmt <= 1'b0;
+ pass_thru_user = 1'b0;
+ pass_thru_user_delay <= 1'b0;
+ pre_pass_thru_user <= 1'b0;
+ end else begin
+ // After csb_reset low, 1st SCK starts command
+ if (state == `COMMAND) begin
+ rdstb <= 1'b0;
+ count <= count + 1;
+ if (count == 3'b000) begin
+ writemode <= SDI;
+ end else if (count == 3'b001) begin
+ readmode <= SDI;
+ end else if (count < 3'b101) begin
+ fixed <= {fixed[1:0], SDI};
+ end else if (count == 3'b101) begin
+ pre_pass_thru_mgmt <= SDI;
+ end else if (count == 3'b110) begin
+ pre_pass_thru_user <= SDI;
+ pass_thru_mgmt_delay <= pre_pass_thru_mgmt;
+ end else if (count == 3'b111) begin
+ pass_thru_user_delay <= pre_pass_thru_user;
+ if (pre_pass_thru_mgmt == 1'b1) begin
+ state <= `MGMTPASS;
+ pre_pass_thru_mgmt <= 1'b0;
+ end else if (pre_pass_thru_user == 1'b1) begin
+ state <= `USERPASS;
+ pre_pass_thru_user <= 1'b0;
+ end else begin
+ state <= `ADDRESS;
+ end
+ end
+ end else if (state == `ADDRESS) begin
+ count <= count + 1;
+ addr <= {addr[6:0], SDI};
+ if (count == 3'b111) begin
+ state <= `DATA;
+ if (readmode == 1'b1) begin
+ rdstb <= 1'b1;
+ end
+ end else begin
+ rdstb <= 1'b0;
+ end
+
+ end else if (state == `DATA) begin
+ predata <= {predata[6:0], SDI};
+ count <= count + 1;
+ if (count == 3'b111) begin
+ if (fixed == 3'b001) begin
+ state <= `COMMAND;
+ end else if (fixed != 3'b000) begin
+ fixed <= fixed - 1;
+ addr <= addr + 1; // Auto increment address (fixed)
+ end else begin
+ addr <= addr + 1; // Auto increment address (streaming)
+ end
+ if (readmode == 1'b1) begin
+ rdstb <= 1'b1;
+ end
+ end else begin
+ rdstb <= 1'b0;
+ end
+ end else if (state == `MGMTPASS) begin
+ pass_thru_mgmt <= 1'b1;
+ end else if (state == `USERPASS) begin
+ pass_thru_user <= 1'b1;
+ end // ! state `DATA | `MGMTPASS | `USERPASS
+ end // ! csb_reset
+ end // always @ SCK
+
+endmodule // housekeeping_spi
+`default_nettype wire
diff --git a/caravel/verilog/rtl/mgmt_protect.v b/caravel/verilog/rtl/mgmt_protect.v
new file mode 100644
index 0000000..dcca8e0
--- /dev/null
+++ b/caravel/verilog/rtl/mgmt_protect.v
@@ -0,0 +1,494 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*----------------------------------------------------------------------*/
+/* Buffers protecting the management region from the user region. */
+/* This mainly consists of tristate buffers that are enabled by a */
+/* "logic 1" output connected to the user's VCCD domain. This ensures */
+/* that the buffer is disabled and the output high-impedence when the */
+/* user 1.8V supply is absent. */
+/*----------------------------------------------------------------------*/
+/* Because there is no tristate buffer with a non-inverted enable, a */
+/* tristate inverter with non-inverted enable is used in series with */
+/* another (normal) inverter. */
+/*----------------------------------------------------------------------*/
+/* For the sake of placement/routing, one conb (logic 1) cell is used */
+/* for every buffer. */
+/*----------------------------------------------------------------------*/
+
+module mgmt_protect (
+`ifdef USE_POWER_PINS
+ inout vccd,
+ inout vssd,
+ inout vccd1,
+ inout vssd1,
+ inout vccd2,
+ inout vssd2,
+ inout vdda1,
+ inout vssa1,
+ inout vdda2,
+ inout vssa2,
+`endif
+
+ input caravel_clk,
+ input caravel_clk2,
+ input caravel_rstn,
+ input mprj_cyc_o_core,
+ input mprj_stb_o_core,
+ input mprj_we_o_core,
+ input [3:0] mprj_sel_o_core,
+ input [31:0] mprj_adr_o_core,
+ input [31:0] mprj_dat_o_core,
+ input [2:0] user_irq_core,
+
+ output [31:0] mprj_dat_i_core,
+ output mprj_ack_i_core,
+
+ input mprj_iena_wb, // Enable wishbone from user project
+
+ // All signal in/out directions are the reverse of the signal
+ // names at the buffer intrface.
+
+ output [127:0] la_data_in_mprj,
+ input [127:0] la_data_out_mprj,
+ input [127:0] la_oenb_mprj,
+ input [127:0] la_iena_mprj,
+
+ input [127:0] la_data_out_core,
+ output [127:0] la_data_in_core,
+ output [127:0] la_oenb_core,
+
+ input [2:0] user_irq_ena,
+
+ output user_clock,
+ output user_clock2,
+ output user_reset,
+ output mprj_cyc_o_user,
+ output mprj_stb_o_user,
+ output mprj_we_o_user,
+ output [3:0] mprj_sel_o_user,
+ output [31:0] mprj_adr_o_user,
+ output [31:0] mprj_dat_o_user,
+ input [31:0] mprj_dat_i_user,
+ input mprj_ack_i_user,
+ output [2:0] user_irq,
+ output user1_vcc_powergood,
+ output user2_vcc_powergood,
+ output user1_vdd_powergood,
+ output user2_vdd_powergood
+);
+
+ wire [462:0] mprj_logic1;
+ wire mprj2_logic1;
+
+ wire mprj_vdd_logic1_h;
+ wire mprj2_vdd_logic1_h;
+ wire mprj_vdd_logic1;
+ wire mprj2_vdd_logic1;
+
+ wire user1_vcc_powergood;
+ wire user2_vcc_powergood;
+ wire user1_vdd_powergood;
+ wire user2_vdd_powergood;
+
+ wire [127:0] la_data_in_mprj_bar;
+ wire [2:0] user_irq_bar;
+
+ wire [127:0] la_data_in_enable;
+ wire [127:0] la_data_out_enable;
+ wire [2:0] user_irq_enable;
+ wire wb_in_enable;
+
+ wire [31:0] mprj_dat_i_core_bar;
+ wire mprj_ack_i_core_bar;
+
+ mprj_logic_high mprj_logic_high_inst (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+`endif
+ .HI(mprj_logic1)
+ );
+
+ mprj2_logic_high mprj2_logic_high_inst (
+`ifdef USE_POWER_PINS
+ .vccd2(vccd2),
+ .vssd2(vssd2),
+`endif
+ .HI(mprj2_logic1)
+ );
+
+ // Logic high in the VDDA (3.3V) domains
+
+ mgmt_protect_hv powergood_check (
+`ifdef USE_POWER_PINS
+ .vccd(vccd),
+ .vssd(vssd),
+ .vdda1(vdda1),
+ .vssa1(vssa1),
+ .vdda2(vdda2),
+ .vssa2(vssa2),
+`endif
+ .mprj_vdd_logic1(mprj_vdd_logic1),
+ .mprj2_vdd_logic1(mprj2_vdd_logic1)
+ );
+
+ // Buffering from the user side to the management side.
+ // NOTE: This is intended to be better protected, by a full
+ // chain of an lv-to-hv buffer followed by an hv-to-lv buffer.
+ // This serves as a placeholder until that configuration is
+ // checked and characterized. The function below forces the
+ // data input to the management core to be a solid logic 0 when
+ // the user project is powered down.
+
+ sky130_fd_sc_hd__and2_1 user_to_mprj_in_ena_buf [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .X(la_data_in_enable),
+ .A(la_iena_mprj),
+ .B(mprj_logic1[457:330])
+ );
+
+ sky130_fd_sc_hd__nand2_4 user_to_mprj_in_gates [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(la_data_in_mprj_bar),
+ .A(la_data_out_core),
+ .B(la_data_in_enable)
+ );
+
+ sky130_fd_sc_hd__inv_8 user_to_mprj_in_buffers [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(la_data_in_mprj),
+ .A(la_data_in_mprj_bar)
+ );
+
+ // Protection, similar to the above, for the three user IRQ lines
+
+ sky130_fd_sc_hd__and2_1 user_irq_ena_buf [2:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .X(user_irq_enable),
+ .A(user_irq_ena),
+ .B(mprj_logic1[460:458])
+ );
+
+ sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(user_irq_bar),
+ .A(user_irq_core),
+ .B(user_irq_enable)
+ );
+
+ sky130_fd_sc_hd__inv_8 user_irq_buffers [2:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(user_irq),
+ .A(user_irq_bar)
+ );
+
+ // Protection, similar to the above, for the return
+ // signals from user area to managment on the wishbone bus
+
+ sky130_fd_sc_hd__and2_1 user_to_mprj_wb_ena_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .X(wb_in_enable),
+ .A(mprj_iena_wb),
+ .B(mprj_logic1[462])
+ );
+
+ sky130_fd_sc_hd__nand2_4 user_wb_dat_gates [31:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(mprj_dat_i_core_bar),
+ .A(mprj_dat_i_user),
+ .B(wb_in_enable)
+ );
+
+ sky130_fd_sc_hd__inv_8 user_wb_dat_buffers [31:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(mprj_dat_i_core),
+ .A(mprj_dat_i_core_bar)
+ );
+
+ sky130_fd_sc_hd__nand2_4 user_wb_ack_gate (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(mprj_ack_i_core_bar),
+ .A(mprj_ack_i_user),
+ .B(wb_in_enable)
+ );
+
+ sky130_fd_sc_hd__inv_8 user_wb_ack_buffer (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Y(mprj_ack_i_core),
+ .A(mprj_ack_i_core_bar)
+ );
+
+ // The remaining circuitry guards against the management
+ // SoC dumping current into the user project area when
+ // the user project area is powered down.
+
+ sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(user_reset),
+ .A(caravel_rstn),
+ .TE(mprj_logic1[0])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(user_clock),
+ .A(~caravel_clk),
+ .TE(mprj_logic1[1])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(user_clock2),
+ .A(~caravel_clk2),
+ .TE(mprj_logic1[2])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_cyc_o_user),
+ .A(~mprj_cyc_o_core),
+ .TE(mprj_logic1[3])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_stb_o_user),
+ .A(~mprj_stb_o_core),
+ .TE(mprj_logic1[4])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_we_buf (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_we_o_user),
+ .A(~mprj_we_o_core),
+ .TE(mprj_logic1[5])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_sel_o_user),
+ .A(~mprj_sel_o_core),
+ .TE(mprj_logic1[9:6])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_adr_o_user),
+ .A(~mprj_adr_o_core),
+ .TE(mprj_logic1[41:10])
+ );
+
+ sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(mprj_dat_o_user),
+ .A(~mprj_dat_o_core),
+ .TE(mprj_logic1[73:42])
+ );
+
+ /* Create signal to tristate the outputs to the user project */
+
+ sky130_fd_sc_hd__and2b_1 la_buf_enable [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .X(la_data_out_enable),
+ .A_N(la_oenb_mprj),
+ .B(mprj_logic1[201:74])
+ );
+
+ /* Project data out from the managment side to the user project */
+ /* area when the user project is powered down. */
+
+ sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(la_data_in_core),
+ .A(~la_data_out_mprj),
+ .TE(la_data_out_enable)
+ );
+
+ /* Project data out enable (bar) from the managment side to the */
+ /* user project area when the user project is powered down. */
+
+ sky130_fd_sc_hd__einvp_8 user_to_mprj_oen_buffers [127:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .Z(la_oenb_core),
+ .A(~la_oenb_mprj),
+ .TE(mprj_logic1[329:202])
+ );
+
+ /* The conb cell output is a resistive connection directly to */
+ /* the power supply, so when returning the user1_powergood */
+ /* signal, make sure that it is buffered properly. */
+
+ sky130_fd_sc_hd__buf_8 mprj_pwrgood (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .A(mprj_logic1[461]),
+ .X(user1_vcc_powergood)
+ );
+
+ sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .A(mprj2_logic1),
+ .X(user2_vcc_powergood)
+ );
+
+ sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .A(mprj_vdd_logic1),
+ .X(user1_vdd_powergood)
+ );
+
+ sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .A(mprj2_vdd_logic1),
+ .X(user2_vdd_powergood)
+ );
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/mgmt_protect_hv.v b/caravel/verilog/rtl/mgmt_protect_hv.v
new file mode 100644
index 0000000..23d9cf6
--- /dev/null
+++ b/caravel/verilog/rtl/mgmt_protect_hv.v
@@ -0,0 +1,103 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*----------------------------------------------------------------------*/
+/* mgmt_protect_hv: */
+/* */
+/* High voltage (3.3V) part of the mgmt_protect module. Split out into */
+/* a separate module and file so that the synthesis tools can handle it */
+/* separately from the rest, since it uses a different standard cell */
+/* library. See the file mgmt_protect.v for a full description of the */
+/* whole management protection method. */
+/*----------------------------------------------------------------------*/
+
+module mgmt_protect_hv (
+`ifdef USE_POWER_PINS
+ inout vccd,
+ inout vssd,
+ inout vdda1,
+ inout vssa1,
+ inout vdda2,
+ inout vssa2,
+`endif
+
+ output mprj_vdd_logic1,
+ output mprj2_vdd_logic1
+
+);
+
+ wire mprj_vdd_logic1_h;
+ wire mprj2_vdd_logic1_h;
+
+`ifdef USE_POWER_PINS
+ // This is to emulate the substrate shorting grounds together for LVS
+ // purposes
+ assign vssa2 = vssa1;
+ assign vssa1 = vssd;
+`endif
+
+ // Logic high in the VDDA (3.3V) domains
+
+ sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda1),
+ .VGND(vssa1),
+ .VPB(vdda1),
+ .VNB(vssa1),
+`endif
+ .HI(mprj_vdd_logic1_h),
+ .LO()
+ );
+
+ sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda2),
+ .VGND(vssa2),
+ .VPB(vdda2),
+ .VNB(vssa2),
+`endif
+ .HI(mprj2_vdd_logic1_h),
+ .LO()
+ );
+
+ // Level shift the logic high signals into the 1.8V domain
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda1),
+ .VGND(vssd),
+ .LVPWR(vccd),
+ .VPB(vdda1),
+ .VNB(vssd),
+`endif
+ .X(mprj_vdd_logic1),
+ .A(mprj_vdd_logic1_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda2),
+ .VGND(vssd),
+ .LVPWR(vccd),
+ .VPB(vdda2),
+ .VNB(vssd),
+`endif
+ .X(mprj2_vdd_logic1),
+ .A(mprj2_vdd_logic1_h)
+ );
+endmodule
+
+`default_nettype wire
diff --git a/caravel/verilog/rtl/mprj2_logic_high.v b/caravel/verilog/rtl/mprj2_logic_high.v
new file mode 100644
index 0000000..e63b1a4
--- /dev/null
+++ b/caravel/verilog/rtl/mprj2_logic_high.v
@@ -0,0 +1,33 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module mprj2_logic_high (
+`ifdef USE_POWER_PINS
+ inout vccd2,
+ inout vssd2,
+`endif
+ output HI
+);
+sky130_fd_sc_hd__conb_1 inst (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd2),
+ .VGND(vssd2),
+ .VPB(vccd2),
+ .VNB(vssd2),
+`endif
+ .HI(HI),
+ .LO()
+ );
+endmodule
diff --git a/caravel/verilog/rtl/mprj_io.v b/caravel/verilog/rtl/mprj_io.v
new file mode 100644
index 0000000..ec4fdf9
--- /dev/null
+++ b/caravel/verilog/rtl/mprj_io.v
@@ -0,0 +1,134 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// `default_nettype none
+
+/* Define the array of GPIO pads. Note that the analog project support
+ * version of caravel (caravan) defines fewer GPIO and replaces them
+ * with analog in the chip_io_alt module. Because the pad signalling
+ * remains the same, `MPRJ_IO_PADS does not change, so a local parameter
+ * is made that can be made smaller than `MPRJ_IO_PADS to accommodate
+ * the analog pads.
+ */
+
+module mprj_io #(
+ parameter AREA1PADS = `MPRJ_IO_PADS_1,
+ parameter TOTAL_PADS = `MPRJ_IO_PADS
+) (
+ inout vddio,
+ inout vssio,
+ inout vdda,
+ inout vssa,
+ inout vccd,
+ inout vssd,
+
+ inout vdda1,
+ inout vdda2,
+ inout vssa1,
+ inout vssa2,
+
+ input vddio_q,
+ input vssio_q,
+ input analog_a,
+ input analog_b,
+ input porb_h,
+ inout [TOTAL_PADS-1:0] io,
+ input [TOTAL_PADS-1:0] io_out,
+ input [TOTAL_PADS-1:0] oeb,
+ input [TOTAL_PADS-1:0] hldh_n,
+ input [TOTAL_PADS-1:0] enh,
+ input [TOTAL_PADS-1:0] inp_dis,
+ input [TOTAL_PADS-1:0] ib_mode_sel,
+ input [TOTAL_PADS-1:0] vtrip_sel,
+ input [TOTAL_PADS-1:0] slow_sel,
+ input [TOTAL_PADS-1:0] holdover,
+ input [TOTAL_PADS-1:0] analog_en,
+ input [TOTAL_PADS-1:0] analog_sel,
+ input [TOTAL_PADS-1:0] analog_pol,
+ input [TOTAL_PADS*3-1:0] dm,
+ output [TOTAL_PADS-1:0] io_in,
+ output [TOTAL_PADS-1:0] io_in_3v3,
+ inout [TOTAL_PADS-10:0] analog_io,
+ inout [TOTAL_PADS-10:0] analog_noesd_io
+);
+
+ wire [TOTAL_PADS-1:0] loop1_io;
+ wire [6:0] no_connect_1a, no_connect_1b;
+ wire [1:0] no_connect_2a, no_connect_2b;
+
+ sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
+ `USER1_ABUTMENT_PINS
+ `ifndef TOP_ROUTING
+ .PAD(io[AREA1PADS - 1:0]),
+ `endif
+ .OUT(io_out[AREA1PADS - 1:0]),
+ .OE_N(oeb[AREA1PADS - 1:0]),
+ .HLD_H_N(hldh_n[AREA1PADS - 1:0]),
+ .ENABLE_H(enh[AREA1PADS - 1:0]),
+ .ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VSWITCH_H(vssio),
+ .ENABLE_VDDIO(vccd),
+ .INP_DIS(inp_dis[AREA1PADS - 1:0]),
+ .IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]),
+ .VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]),
+ .SLOW(slow_sel[AREA1PADS - 1:0]),
+ .HLD_OVR(holdover[AREA1PADS - 1:0]),
+ .ANALOG_EN(analog_en[AREA1PADS - 1:0]),
+ .ANALOG_SEL(analog_sel[AREA1PADS - 1:0]),
+ .ANALOG_POL(analog_pol[AREA1PADS - 1:0]),
+ .DM(dm[AREA1PADS*3 - 1:0]),
+ .PAD_A_NOESD_H({analog_noesd_io[AREA1PADS - 8:0], no_connect_1a}),
+ .PAD_A_ESD_0_H({analog_io[AREA1PADS - 8:0], no_connect_1b}),
+ .PAD_A_ESD_1_H(),
+ .IN(io_in[AREA1PADS - 1:0]),
+ .IN_H(io_in_3v3[AREA1PADS - 1:0]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop1_io[AREA1PADS - 1:0])
+ );
+
+ sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
+ `USER2_ABUTMENT_PINS
+ `ifndef TOP_ROUTING
+ .PAD(io[TOTAL_PADS - 1:AREA1PADS]),
+ `endif
+ .OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
+ .OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),
+ .HLD_H_N(hldh_n[TOTAL_PADS - 1:AREA1PADS]),
+ .ENABLE_H(enh[TOTAL_PADS - 1:AREA1PADS]),
+ .ENABLE_INP_H(loop1_io[TOTAL_PADS - 1:AREA1PADS]),
+ .ENABLE_VDDA_H(porb_h),
+ .ENABLE_VSWITCH_H(vssio),
+ .ENABLE_VDDIO(vccd),
+ .INP_DIS(inp_dis[TOTAL_PADS - 1:AREA1PADS]),
+ .IB_MODE_SEL(ib_mode_sel[TOTAL_PADS - 1:AREA1PADS]),
+ .VTRIP_SEL(vtrip_sel[TOTAL_PADS - 1:AREA1PADS]),
+ .SLOW(slow_sel[TOTAL_PADS - 1:AREA1PADS]),
+ .HLD_OVR(holdover[TOTAL_PADS - 1:AREA1PADS]),
+ .ANALOG_EN(analog_en[TOTAL_PADS - 1:AREA1PADS]),
+ .ANALOG_SEL(analog_sel[TOTAL_PADS - 1:AREA1PADS]),
+ .ANALOG_POL(analog_pol[TOTAL_PADS - 1:AREA1PADS]),
+ .DM(dm[TOTAL_PADS*3 - 1:AREA1PADS*3]),
+ .PAD_A_NOESD_H({no_connect_2a, analog_noesd_io[TOTAL_PADS - 10:AREA1PADS - 7]}),
+ .PAD_A_ESD_0_H({no_connect_2b, analog_io[TOTAL_PADS - 10:AREA1PADS - 7]}),
+ .PAD_A_ESD_1_H(),
+ .IN(io_in[TOTAL_PADS - 1:AREA1PADS]),
+ .IN_H(io_in_3v3[TOTAL_PADS - 1:AREA1PADS]),
+ .TIE_HI_ESD(),
+ .TIE_LO_ESD(loop1_io[TOTAL_PADS - 1:AREA1PADS])
+ );
+
+endmodule
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/mprj_logic_high.v b/caravel/verilog/rtl/mprj_logic_high.v
new file mode 100644
index 0000000..c9e6d17
--- /dev/null
+++ b/caravel/verilog/rtl/mprj_logic_high.v
@@ -0,0 +1,33 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module mprj_logic_high (
+`ifdef USE_POWER_PINS
+ inout vccd1,
+ inout vssd1,
+`endif
+ output [462:0] HI
+);
+sky130_fd_sc_hd__conb_1 insts [462:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd1),
+ .VGND(vssd1),
+ .VPB(vccd1),
+ .VNB(vssd1),
+`endif
+ .HI(HI),
+ .LO()
+ );
+endmodule
diff --git a/caravel/verilog/rtl/pads.v b/caravel/verilog/rtl/pads.v
new file mode 100644
index 0000000..86e0be5
--- /dev/null
+++ b/caravel/verilog/rtl/pads.v
@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// `default_nettype none
+`ifndef TOP_ROUTING
+ `define USER1_ABUTMENT_PINS \
+ .AMUXBUS_A(analog_a),\
+ .AMUXBUS_B(analog_b),\
+ .VSSA(vssa1),\
+ .VDDA(vdda1),\
+ .VSWITCH(vddio),\
+ .VDDIO_Q(vddio_q),\
+ .VCCHIB(vccd),\
+ .VDDIO(vddio),\
+ .VCCD(vccd),\
+ .VSSIO(vssio),\
+ .VSSD(vssd),\
+ .VSSIO_Q(vssio_q),
+
+ `define USER2_ABUTMENT_PINS \
+ .AMUXBUS_A(analog_a),\
+ .AMUXBUS_B(analog_b),\
+ .VSSA(vssa2),\
+ .VDDA(vdda2),\
+ .VSWITCH(vddio),\
+ .VDDIO_Q(vddio_q),\
+ .VCCHIB(vccd),\
+ .VDDIO(vddio),\
+ .VCCD(vccd),\
+ .VSSIO(vssio),\
+ .VSSD(vssd),\
+ .VSSIO_Q(vssio_q),
+
+ `define MGMT_ABUTMENT_PINS \
+ .AMUXBUS_A(analog_a),\
+ .AMUXBUS_B(analog_b),\
+ .VSSA(vssa),\
+ .VDDA(vdda),\
+ .VSWITCH(vddio),\
+ .VDDIO_Q(vddio_q),\
+ .VCCHIB(vccd),\
+ .VDDIO(vddio),\
+ .VCCD(vccd),\
+ .VSSIO(vssio),\
+ .VSSD(vssd),\
+ .VSSIO_Q(vssio_q),
+`else
+ `define USER1_ABUTMENT_PINS
+ `define USER2_ABUTMENT_PINS
+ `define MGMT_ABUTMENT_PINS
+`endif
+
+`define HVCLAMP_PINS(H,L) \
+ .DRN_HVC(H), \
+ .SRC_BDY_HVC(L)
+
+`define LVCLAMP_PINS(H1,L1,H2,L2,L3) \
+ .BDY2_B2B(L3), \
+ .DRN_LVC1(H1), \
+ .DRN_LVC2(H2), \
+ .SRC_BDY_LVC1(L1), \
+ .SRC_BDY_LVC2(L2)
+
+`define INPUT_PAD(X,Y) \
+ wire loop_``X; \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
+ `MGMT_ABUTMENT_PINS \
+ `ifndef TOP_ROUTING \
+ .PAD(X), \
+ `endif \
+ .OUT(vssd), \
+ .OE_N(vccd), \
+ .HLD_H_N(vddio), \
+ .ENABLE_H(porb_h), \
+ .ENABLE_INP_H(loop_``X), \
+ .ENABLE_VDDA_H(porb_h), \
+ .ENABLE_VSWITCH_H(vssa), \
+ .ENABLE_VDDIO(vccd), \
+ .INP_DIS(por), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM({vssd, vssd, vccd}), \
+ .PAD_A_NOESD_H(), \
+ .PAD_A_ESD_0_H(), \
+ .PAD_A_ESD_1_H(), \
+ .IN(Y), \
+ .IN_H(), \
+ .TIE_HI_ESD(), \
+ .TIE_LO_ESD(loop_``X) )
+
+`define OUTPUT_PAD(X,Y,INPUT_DIS,OUT_EN_N) \
+ wire loop_``X; \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
+ `MGMT_ABUTMENT_PINS \
+ `ifndef TOP_ROUTING \
+ .PAD(X), \
+ `endif \
+ .OUT(Y), \
+ .OE_N(OUT_EN_N), \
+ .HLD_H_N(vddio), \
+ .ENABLE_H(porb_h), \
+ .ENABLE_INP_H(loop_``X), \
+ .ENABLE_VDDA_H(porb_h), \
+ .ENABLE_VSWITCH_H(vssa), \
+ .ENABLE_VDDIO(vccd), \
+ .INP_DIS(INPUT_DIS), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM({vccd, vccd, vssd}), \
+ .PAD_A_NOESD_H(), \
+ .PAD_A_ESD_0_H(), \
+ .PAD_A_ESD_1_H(), \
+ .IN(), \
+ .IN_H(), \
+ .TIE_HI_ESD(), \
+ .TIE_LO_ESD(loop_``X))
+
+`define OUTPUT_NO_INP_DIS_PAD(X,Y,OUT_EN_N) \
+ wire loop_``X; \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
+ `MGMT_ABUTMENT_PINS \
+ `ifndef TOP_ROUTING \
+ .PAD(X), \
+ `endif \
+ .OUT(Y), \
+ .OE_N(OUT_EN_N), \
+ .HLD_H_N(vddio), \
+ .ENABLE_H(porb_h), \
+ .ENABLE_INP_H(loop_``X), \
+ .ENABLE_VDDA_H(porb_h), \
+ .ENABLE_VSWITCH_H(vssa), \
+ .ENABLE_VDDIO(vccd), \
+ .INP_DIS(loop_``X), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM({vccd, vccd, vssd}), \
+ .PAD_A_NOESD_H(), \
+ .PAD_A_ESD_0_H(), \
+ .PAD_A_ESD_1_H(), \
+ .IN(), \
+ .IN_H(), \
+ .TIE_HI_ESD(), \
+ .TIE_LO_ESD(loop_``X))
+
+`define INOUT_PAD(X,Y,Y_OUT,INPUT_DIS,OUT_EN_N,MODE) \
+ wire loop_``X; \
+ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
+ `MGMT_ABUTMENT_PINS \
+ `ifndef TOP_ROUTING \
+ .PAD(X), \
+ `endif \
+ .OUT(Y_OUT), \
+ .OE_N(OUT_EN_N), \
+ .HLD_H_N(vddio), \
+ .ENABLE_H(porb_h), \
+ .ENABLE_INP_H(loop_``X), \
+ .ENABLE_VDDA_H(porb_h), \
+ .ENABLE_VSWITCH_H(vssa), \
+ .ENABLE_VDDIO(vccd), \
+ .INP_DIS(INPUT_DIS), \
+ .IB_MODE_SEL(vssd), \
+ .VTRIP_SEL(vssd), \
+ .SLOW(vssd), \
+ .HLD_OVR(vssd), \
+ .ANALOG_EN(vssd), \
+ .ANALOG_SEL(vssd), \
+ .ANALOG_POL(vssd), \
+ .DM(MODE), \
+ .PAD_A_NOESD_H(), \
+ .PAD_A_ESD_0_H(), \
+ .PAD_A_ESD_1_H(), \
+ .IN(Y), \
+ .IN_H(), \
+ .TIE_HI_ESD(), \
+ .TIE_LO_ESD(loop_``X) )
+
+// `default_nettype wire
diff --git a/caravel/verilog/rtl/ring_osc2x13.v b/caravel/verilog/rtl/ring_osc2x13.v
new file mode 100644
index 0000000..f20110e
--- /dev/null
+++ b/caravel/verilog/rtl/ring_osc2x13.v
@@ -0,0 +1,250 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// Tunable ring oscillator---synthesizable (physical) version.
+//
+// NOTE: This netlist cannot be simulated correctly due to lack
+// of accurate timing in the digital cell verilog models.
+
+module delay_stage(in, trim, out);
+ input in;
+ input [1:0] trim;
+ output out;
+
+ wire d0, d1, d2, ts;
+
+ sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
+ .A(in),
+ .X(ts)
+ );
+
+ sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
+ .A(ts),
+ .X(d0)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen1 (
+ .A(d0),
+ .TE(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__einvn_4 delayenb1 (
+ .A(ts),
+ .TE_B(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__clkinv_1 delayint0 (
+ .A(d1),
+ .Y(d2)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen0 (
+ .A(d2),
+ .TE(trim[0]),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvn_8 delayenb0 (
+ .A(ts),
+ .TE_B(trim[0]),
+ .Z(out)
+ );
+
+endmodule
+
+module start_stage(in, trim, reset, out);
+ input in;
+ input [1:0] trim;
+ input reset;
+ output out;
+
+ wire d0, d1, d2, ctrl0, one;
+
+ sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
+ .A(in),
+ .X(d0)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen1 (
+ .A(d0),
+ .TE(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__einvn_4 delayenb1 (
+ .A(in),
+ .TE_B(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__clkinv_1 delayint0 (
+ .A(d1),
+ .Y(d2)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen0 (
+ .A(d2),
+ .TE(trim[0]),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvn_8 delayenb0 (
+ .A(in),
+ .TE_B(ctrl0),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvp_1 reseten0 (
+ .A(one),
+ .TE(reset),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__or2_2 ctrlen0 (
+ .A(reset),
+ .B(trim[0]),
+ .X(ctrl0)
+ );
+
+ sky130_fd_sc_hd__conb_1 const1 (
+ .HI(one),
+ .LO()
+ );
+
+endmodule
+
+// Ring oscillator with 13 stages, each with two trim bits delay
+// (see above). Trim is not binary: For trim[1:0], lower bit
+// trim[0] is primary trim and must be applied first; upper
+// bit trim[1] is secondary trim and should only be applied
+// after the primary trim is applied, or it has no effect.
+//
+// Total effective number of inverter stages in this oscillator
+// ranges from 13 at trim 0 to 65 at trim 24. The intention is
+// to cover a range greater than 2x so that the midrange can be
+// reached over all PVT conditions.
+//
+// Frequency of this ring oscillator under SPICE simulations at
+// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
+
+module ring_osc2x13(reset, trim, clockp);
+ input reset;
+ input [25:0] trim;
+ output[1:0] clockp;
+
+`ifdef FUNCTIONAL // i.e., behavioral model below
+
+ reg [1:0] clockp;
+ reg hiclock;
+ integer i;
+ real delay;
+ wire [5:0] bcount;
+
+ assign bcount = trim[0] + trim[1] + trim[2]
+ + trim[3] + trim[4] + trim[5] + trim[6] + trim[7]
+ + trim[8] + trim[9] + trim[10] + trim[11] + trim[12]
+ + trim[13] + trim[14] + trim[15] + trim[16] + trim[17]
+ + trim[18] + trim[19] + trim[20] + trim[21] + trim[22]
+ + trim[23] + trim[24] + trim[25];
+
+ initial begin
+ hiclock <= 1'b0;
+ delay = 3.0;
+ end
+
+ // Fastest operation is 214 MHz = 4.67ns
+ // Delay per trim is 0.02385
+ // Run "hiclock" at 2x this rate, then use positive and negative
+ // edges to derive the 0 and 90 degree phase clocks.
+
+ always #delay begin
+ hiclock <= (hiclock === 1'b0);
+ end
+
+ always @(trim) begin
+ // Implement trim as a variable delay, one delay per trim bit
+ delay = 1.168 + 0.012 * $itor(bcount);
+ end
+
+ always @(posedge hiclock or posedge reset) begin
+ if (reset == 1'b1) begin
+ clockp[0] <= 1'b0;
+ end else begin
+ clockp[0] <= (clockp[0] === 1'b0);
+ end
+ end
+
+ always @(negedge hiclock or posedge reset) begin
+ if (reset == 1'b1) begin
+ clockp[1] <= 1'b0;
+ end else begin
+ clockp[1] <= (clockp[1] === 1'b0);
+ end
+ end
+
+`else // !FUNCTIONAL; i.e., gate level netlist below
+
+ wire [1:0] clockp;
+ wire [12:0] d;
+ wire [1:0] c;
+
+ // Main oscillator loop stages
+
+ genvar i;
+ generate
+ for (i = 0; i < 12; i = i + 1) begin : dstage
+ delay_stage id (
+ .in(d[i]),
+ .trim({trim[i+13], trim[i]}),
+ .out(d[i+1])
+ );
+ end
+ endgenerate
+
+ // Reset/startup stage
+
+ start_stage iss (
+ .in(d[12]),
+ .trim({trim[25], trim[12]}),
+ .reset(reset),
+ .out(d[0])
+ );
+
+ // Buffered outputs a 0 and 90 degrees phase (approximately)
+
+ sky130_fd_sc_hd__clkinv_2 ibufp00 (
+ .A(d[0]),
+ .Y(c[0])
+ );
+ sky130_fd_sc_hd__clkinv_8 ibufp01 (
+ .A(c[0]),
+ .Y(clockp[0])
+ );
+ sky130_fd_sc_hd__clkinv_2 ibufp10 (
+ .A(d[6]),
+ .Y(c[1])
+ );
+ sky130_fd_sc_hd__clkinv_8 ibufp11 (
+ .A(c[1]),
+ .Y(clockp[1])
+ );
+
+`endif // !FUNCTIONAL
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/simple_por.v b/caravel/verilog/rtl/simple_por.v
new file mode 100644
index 0000000..d5a8a9d
--- /dev/null
+++ b/caravel/verilog/rtl/simple_por.v
@@ -0,0 +1,93 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+module simple_por(
+`ifdef USE_POWER_PINS
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss3v3,
+ inout vss1v8,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss3v3),
+ .VPB(vdd3v3),
+ .VNB(vss3v3),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss3v3),
+ .VPB(vdd3v3),
+ .VNB(vss3v3),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss3v3),
+ .VGND(vss3v3),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/spare_logic_block.v b/caravel/verilog/rtl/spare_logic_block.v
new file mode 100644
index 0000000..e12d0de
--- /dev/null
+++ b/caravel/verilog/rtl/spare_logic_block.v
@@ -0,0 +1,162 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+// Spare logic block. This block can be used for metal mask fixes to
+// a design. It is much larger and more comprehensive than the simple
+// "macro_sparecell" in the HD library, and contains flops, taps, muxes,
+// and diodes in addition to the inverters, NOR, NAND, and constant
+// gates provided by macro_sparecell.
+
+module spare_logic_block (
+ `ifdef USE_POWER_PINS
+ inout vccd,
+ inout vssd,
+ `endif
+
+ output [26:0] spare_xz, // Constant 0 outputs (and block inputs)
+ output [3:0] spare_xi, // Inverter outputs
+ output spare_xib, // Big inverter output
+ output [1:0] spare_xna, // NAND outputs
+ output [1:0] spare_xno, // NOR outputs
+ output [1:0] spare_xmx, // Mux outputs
+ output [1:0] spare_xfq, // Flop noninverted output
+ output [1:0] spare_xfqn // Flop inverted output
+);
+
+ wire [3:0] spare_logic_nc;
+
+ wire [3:0] spare_xi;
+ wire spare_xib;
+ wire [1:0] spare_xna;
+ wire [1:0] spare_xno;
+ wire [1:0] spare_xmx;
+ wire [1:0] spare_xfq;
+ wire [1:0] spare_xfqn;
+
+ wire [26:0] spare_logic1;
+ wire [26:0] spare_logic0;
+ wire [26:0] spare_xz;
+
+ // Rename the logic0 outputs at the block pins.
+ assign spare_xz = spare_logic0;
+
+ sky130_fd_sc_hd__conb_1 spare_logic_const [26:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .HI(spare_logic1),
+ .LO(spare_logic0)
+ );
+
+ sky130_fd_sc_hd__inv_2 spare_logic_inv [3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .Y(spare_xi),
+ .A(spare_logic0[3:0])
+ );
+
+ sky130_fd_sc_hd__inv_8 spare_logic_biginv (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .Y(spare_xib),
+ .A(spare_logic0[4])
+ );
+
+ sky130_fd_sc_hd__nand2_2 spare_logic_nand [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .Y(spare_xna),
+ .A(spare_logic0[6:5]),
+ .B(spare_logic0[8:7])
+ );
+
+ sky130_fd_sc_hd__nor2_2 spare_logic_nor [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .Y(spare_xno),
+ .A(spare_logic0[10:9]),
+ .B(spare_logic0[12:11])
+ );
+
+ sky130_fd_sc_hd__mux2_2 spare_logic_mux [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .X(spare_xmx),
+ .A0(spare_logic0[14:13]),
+ .A1(spare_logic0[16:15]),
+ .S(spare_logic0[18:17])
+ );
+
+ sky130_fd_sc_hd__dfbbp_1 spare_logic_flop [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .Q(spare_xfq),
+ .Q_N(spare_xfqn),
+ .D(spare_logic0[20:19]),
+ .CLK(spare_logic0[22:21]),
+ .SET_B(spare_logic0[24:23]),
+ .RESET_B(spare_logic0[26:25])
+ );
+
+ sky130_fd_sc_hd__tapvpwrvgnd_1 spare_logic_tap [1:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd)
+ `endif
+ );
+
+ sky130_fd_sc_hd__diode_2 spare_logic_diode [3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+ `endif
+ .DIODE(spare_logic_nc)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/user_defines.v b/caravel/verilog/rtl/user_defines.v
new file mode 100644
index 0000000..f74de2b
--- /dev/null
+++ b/caravel/verilog/rtl/user_defines.v
@@ -0,0 +1,87 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __USER_DEFINES_H
+// User GPIO initial configuration parameters
+`define __USER_DEFINES_H
+
+// Useful GPIO mode values. These match the names used in defs.h.
+`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403
+`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0803
+`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0c03
+`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809
+`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801
+`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b
+
+`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402
+`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0802
+`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0c02
+`define GPIO_MODE_USER_STD_OUTPUT 13'h1808
+`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800
+`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802
+`define GPIO_MODE_USER_STD_ANALOG 13'h000a
+
+// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
+// modified (allowing the SPI and debug to always be accessible unless
+// overridden by a flash program).
+
+// The values below can be any of the standard types defined above,
+// or they can be any 13-bit value if the user wants a non-standard
+// startup state for the GPIO. By default, every GPIO from 5 to 37
+// is set to power up as an input controlled by the management SoC.
+// Users may want to redefine these so that the user project powers
+// up in a state that can be used immediately without depending on
+// the management SoC to run a startup program to configure the GPIOs.
+
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+
+// Configurations of GPIO 15 to 25 are used on caravel but not caravan.
+`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+
+`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
+
+`endif // __USER_DEFINES_H
diff --git a/caravel/verilog/rtl/user_id_programming.v b/caravel/verilog/rtl/user_id_programming.v
new file mode 100644
index 0000000..4c8d6c9
--- /dev/null
+++ b/caravel/verilog/rtl/user_id_programming.v
@@ -0,0 +1,57 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// This module represents an unprogrammed mask revision
+// block that is configured with via programming on the
+// chip top level. This value is passed to the block as
+// a parameter
+
+module user_id_programming #(
+ parameter USER_PROJECT_ID = 32'h0
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ output [31:0] mask_rev
+);
+ wire [31:0] mask_rev;
+ wire [31:0] user_proj_id_high;
+ wire [31:0] user_proj_id_low;
+
+ // For the mask revision input, use an array of digital constant logic cells
+
+ sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
+`ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VPB(VPWR),
+ .VNB(VGND),
+ .VGND(VGND),
+`endif
+ .HI(user_proj_id_high),
+ .LO(user_proj_id_low)
+ );
+
+ genvar i;
+ generate
+ for (i = 0; i < 32; i = i+1) begin
+ assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
+ user_proj_id_high[i] : user_proj_id_low[i];
+ end
+ endgenerate
+
+endmodule
+`default_nettype wire
diff --git a/caravel/verilog/rtl/xres_buf.v b/caravel/verilog/rtl/xres_buf.v
new file mode 100644
index 0000000..333d822
--- /dev/null
+++ b/caravel/verilog/rtl/xres_buf.v
@@ -0,0 +1,55 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Module xres_buf is a level-shift buffer between the xres pad (used for
+// digital reset) and the caravel chip core. The xres pad output is in
+// the 3.3V domain while the signal goes to the digital circuitry in the
+// 1.8V domain.
+
+module xres_buf (
+ X ,
+ A ,
+`ifdef USE_POWER_PINS
+ VPWR ,
+ VGND ,
+ LVPWR,
+ LVGND,
+`endif
+);
+
+output X ;
+input A ;
+`ifdef USE_POWER_PINS
+inout VPWR ;
+inout VGND ;
+inout LVPWR;
+inout LVGND;
+`endif
+
+sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (
+`ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VPB(VPWR),
+
+ .LVPWR(LVPWR),
+
+ .VNB(VGND),
+ .VGND(VGND),
+`endif
+ .A(A),
+ .X(X)
+);
+
+endmodule
diff --git a/caravel/verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v b/caravel/verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v
new file mode 100644
index 0000000..87951f2
--- /dev/null
+++ b/caravel/verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v
@@ -0,0 +1,22 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+(* blackbox *)
+module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
+
+endmodule
\ No newline at end of file
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..b5f711d
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,337 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel Analog User Project
+===========================
+
+|License| |User CI| |Caravan Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Install Caravel <#install-caravel>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `User Project: Power on Reset <#user-project-power-on-reset>`_
+ - `Verilog Integration <#verilog-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
+- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the caravan chip (analog version of `caravel <https://github.com/efabless/caravel.git>`__) user space. The user project is a simple power-on-reset that showcases how to make use of caravan's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw **analog** projects.
+
+Install Caravel
+===============
+
+To setup caravel, run the following:
+
+.. code:: bash
+
+ # By default, CARAVEL_ROOT is set to $(pwd)/caravel
+ # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
+ # Disable submodule installation if needed by, run "export SUBMODULE=0"
+
+ git clone https://github.com/efabless/caravel_user_project_analog.git
+ cd caravel_user_project_analog
+ make install
+
+To update the installed caravel to the latest, run:
+
+.. code:: bash
+
+ make update_caravel
+
+To remove caravel, run
+
+.. code:: bash
+
+ make uninstall
+
+By default
+`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
+installed. To install the full version of caravel, run this prior to
+calling make install.
+
+.. code:: bash
+
+ export CARAVEL_LITE=0
+
+Caravel Integration
+=====================
+
+
+User Project: Power on Reset
+----------------------------
+
+This is an example user analog project which breaks out the power-on-reset
+circuit used by the management SoC for power-up behavior so that the circuit
+input and output can be independently controlled and measured.
+
+The power-on-reset circuit itself is a simple, non-temperature-compensated
+analog delay calibrated to 15ms under nominal conditions, with a Schmitt
+trigger inverter to provide hysteresis around the trigger point to provide
+a clean output reset signal.
+
+The circuit provides a single high-voltage (3.3V domain) sense-inverted reset
+signal "porb_h" and complementary low-voltage (1.8V domain) reset signals
+"por_l" and "porb_l".
+
+The only input to the circuit is the 3.3V domain power supply itself.
+
+
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_analog_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_analog_project_wrapper.v>`__.
+The wrapper top module must be named ``user_analog_project_wrapper`` and must
+have the same input and output ports as the analog wrapper template. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+The verilog modules instantiated in the wrapper module should represent
+the analog project; they need not be more than empty blocks, but it is
+encouraged to write a simple behavioral description of the analog circuit
+in standard verilog, using real-valued wires when necessary. This allows
+the whole system to be run in a verilog testbench and verify the connectivity
+to the padframe and management SoC, even if the testbench C code does nothing
+more than set the mode of each GPIO pin. The example top-level verilog code
+emulates the behavior of the power-on-reset delay after applying a valid
+power supply to the circuit.
+
+
+Building the PDK
+================
+
+You have two options for building the pdk:
+
+- Build the pdk natively.
+
+Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ `version 8.3.160 <https://github.com/RTimothyEdwards/magic/tree/8.3.160>`__ installed on your machine before building the pdk.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk
+
+- Build the pdk using openlane's docker image which has magic installed.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk-nonnative
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+To install the simulation environment locally, refer to `README <https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/dv/README.md>`__
+
+Then, run the RTL and GL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=RTL
+ # Run the mprj_por testbench, make verify-mprj_por
+ make verify-<testbench-name>
+
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+
+Analog Design Flow
+===================
+
+The example project uses a very simple analog design flow with schematics
+made with xschem, simulation done using ngspice, layout done with magic,
+and LVS verification done with netgen. Sources for the power-on-reset
+circuit are in the "xschem/" directory, which also includes a schematic
+representing the wrapper with all of its ports, for use in a testbench
+circuit. There are several testbenches in the example, starting from
+tests of the component devices to a full test of the completed project
+inside the wrapper.
+
+There is no automation in this project; the schematic and layout were
+done by hand, including both the power-on-reset block and the power and
+signal routing to the pins on the wrapper.
+
+The power-on-reset circuit itself is simple and is not compensated for
+temperature or voltage variation. When the power supply reaches a
+sufficient level, the voltage divider sets the gate voltage on an nFET
+device to draw a current of nominally 240nA. The testbench
+"threshold_test_tb.spice" does a DC sweep to find the gate voltage that
+produces this value. Next, a cascaded current mirror divides down the
+current by a factor of (roughly) 400. The testbench current_test.spice
+checks the current division value. Finally, the output ~600pA from the
+end of the current mirror is accumulated on a capacitor until the value
+trips the input of the 3.3V Schmitt trigger buffer from the
+sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal
+time to trigger at 15ms. The schematic "example_por_tb.sch" sets up
+the testbench for this timing test.
+
+The output of the Schmitt trigger buffer becomes the high-voltage
+output, and is input to a standard buffer and inverter used as
+level shifters from the 3.3V domain to the 1.8V domain, producing
+complementary low-voltage outputs.
+
+The user project is formed from two power-on-reset circuits, one of
+which is connected to the user area VDDA1 power supply, and the other
+of which is connected to one of the analog I/O pads, used as a power
+supply input and connected to its voltage ESD clamp circuit. The
+3.3V domain outputs are connected directly to GPIO pads through the
+ESD (150 ohm series) connection. The 1.8V domain outputs are connected
+to GPIO pads through the usual I/O connections, with the corresponding
+user output enable (sense inverted) held low to keep the output always
+active.
+
+The C code testbench is in "verilog/dv/mprj_por/mprj_por.c" and only
+sets the GPIO pins used to the correct state (user output function).
+The POR circuit outputs are monitored by the testbench verilog file
+"mprj_por_tb.v" which will fail if the connections are wrong or if
+the behavioral POR verilog does not work as intended.
+
+Note that to properly test this circuit, the GPIO pins have to be
+configured for output to be seen and measured, implying that the
+management SoC power supply must be stable and the C program running
+off of the SPI flash before the user area power supplies are raised.
+
+**NOTE**
+
+ When running spice extraction on the user_analog_project_wrapper layout, it is recommended to use `ext2spice short resistor`.
+ This is to preserve all the different port names in the extracted netlist. In case you have two ports that are electrically shorted
+ in the layout, the `short resistor` option will tell magic not to merge the two shorted ports instead it adds zero-ohm ideal resistors
+ between the net names so that they can be kept as separate nets.
+
+
+Running Open-MPW Precheck Locally
+=================================
+
+You can install the precheck by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+Specify CARAVEL_ROOT before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+ make run-precheck
+
+This will run all the precheck checks on your project and will retain the logs under the ``checks`` directory.
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run compress, uncompress, and run XOR checks on your design.
+
+Compress gds files and any file larger than 100MB (GH file size limit),
+
+.. code:: bash
+
+ make compress
+
+Uncompress files,
+
+.. code:: bash
+
+ make uncompress
+
+
+Specify ``CARAVEL_ROOT`` before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-analog-wrapper
+
+Checklist for Open-MPW Submission
+=================================
+
+
+|:heavy_check_mark:| The project repo adheres to the same directory structure in this repo.
+
+|:heavy_check_mark:| The project repo contain info.yaml at the project root.
+
+|:heavy_check_mark:| Top level macro is named ``user_analog_project_wrapper``.
+
+|:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
+
+|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice
+
+|:heavy_check_mark:| The hardened Macros are LVS and DRC clean
+
+|:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
+
+|:heavy_check_mark:| XOR check passes with zero total difference.
+
+|:heavy_check_mark:| Open-MPW-Precheck tool runs successfully.
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml
+.. |Caravan Build| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..8fe3508
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..563edc0
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "Two Stage CMOS Operational Amplifier"
+ foundry: "SkyWater"
+ git_url: "https://github.com/rohinthram/opamp_tapeout_mpw4"
+ organization: ""
+ organization_url: ""
+ owner: "R.V.Rohinth Ram"
+ process: "SKY130"
+ project_name: "Two Stage CMOS Operational Amplifier"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Test Harness"
+ category: "Test Harness"
+ top_level_netlist: "caravel/spi/lvs/caravan.spice"
+ user_level_netlist: "netgen/user_analog_project_wrapper.spice"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/mag/example_por.mag b/mag/example_por.mag
new file mode 100644
index 0000000..76d1d78
--- /dev/null
+++ b/mag/example_por.mag
@@ -0,0 +1,603 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1620310959
+<< nwell >>
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+<< viali >>
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+rect 4313 6494 5299 6558
+rect 4507 6135 5299 6494
+rect 10851 6615 10879 7755
+rect 11146 6615 11171 7755
+rect 10851 6242 11171 6615
+use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0
+timestamp 1606063140
+transform 1 0 1515 0 1 6769
+box -962 -458 962 458
+use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1
+timestamp 1605994897
+transform -1 0 371 0 1 6769
+box -308 -458 308 458
+use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0
+timestamp 1606063140
+transform 1 0 1657 0 1 7841
+box -1101 -497 1101 497
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3
+timestamp 1606063140
+transform 1 0 408 0 1 7841
+box -338 -497 338 497
+use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0
+timestamp 1606063140
+transform 1 0 2660 0 1 6770
+box -308 -458 308 458
+use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0
+timestamp 1606063140
+transform 1 0 2906 0 1 7841
+box -338 -497 338 497
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0
+timestamp 1606063140
+transform 1 0 3392 0 1 7841
+box -338 -497 338 497
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1
+timestamp 1606063140
+transform 1 0 3878 0 1 7841
+box -338 -497 338 497
+use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0
+timestamp 1606063140
+transform 1 0 5018 0 1 7841
+box -992 -497 992 497
+use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0
+timestamp 1606063140
+transform 1 0 6158 0 1 7841
+box -338 -497 338 497
+use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2
+timestamp 1606063140
+transform 1 0 6644 0 1 7841
+box -338 -497 338 497
+use sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1619722500
+transform 1 0 7467 0 1 6404
+box -66 -43 1122 897
+use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_1 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1619722500
+transform 1 0 7477 0 1 7438
+box -66 -43 1986 897
+use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_0
+timestamp 1619722500
+transform 1 0 8523 0 1 6404
+box -66 -43 1986 897
+use sky130_fd_sc_hvl__fill_4 sky130_fd_sc_hvl__fill_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1619722500
+transform 1 0 10443 0 1 6404
+box -66 -43 450 897
+use sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
+timestamp 1619722500
+transform 1 0 9397 0 1 7438
+box -66 -43 1506 897
+use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0
+timestamp 1606074388
+transform 1 0 5446 0 1 3098
+box -5446 -3098 5446 3098
+use sky130_fd_pr__cap_mim_m3_2_W5U4AW sky130_fd_pr__cap_mim_m3_2_W5U4AW_0
+timestamp 1606502073
+transform 1 0 7970 0 1 3151
+box -3179 -3101 3201 3101
+use sky130_fd_pr__cap_mim_m3_1_WRT4AW sky130_fd_pr__cap_mim_m3_1_WRT4AW_0
+timestamp 1606502073
+transform -1 0 7027 0 1 3151
+box -3136 -3100 3136 3100
+<< labels >>
+flabel metal4 s 38 7965 73 8283 0 FreeSans 320 0 0 0 vdd3v3
+port 0 nsew
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+port 2 nsew
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+port 5 nsew
+flabel metal3 10969 6765 11342 6834 0 FreeSans 320 0 0 0 porb_h
+port 3 nsew
+<< properties >>
+string FIXED_BBOX 0 0 11344 8338
+<< end >>
diff --git a/mag/layout_opamp.ext b/mag/layout_opamp.ext
new file mode 100644
index 0000000..ea6ee76
--- /dev/null
+++ b/mag/layout_opamp.ext
@@ -0,0 +1,58 @@
+timestamp 1635434905
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 1e+06
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__res_generic_nd l=l w=w
+node "in2" 176 138444 506 -110 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33412 868 0 0 14141732 132004 3304077 13654 3167514 7982 4084417 9604 0 0 0 0 0 0
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+node "in1" 160 53465.6 77 -79 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30400 808 0 0 2453824 47862 3119101 12142 3016356 7870 3609264 9026 0 0 0 0 0 0
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+node "out" 18164 117433 962 304 pdif 0 0 0 0 0 0 0 0 660628 12790 710657 12804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9312232 140678 2659970 7614 2659970 7614 3580673 9564 0 0 0 0 0 0
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+cap "in2" "a_n469_n962#" 19.449
+cap "vdd" "a_n541_1558#" 131.294
+device msubckt sky130_fd_pr__nfet_01v8 1249 -2149 1250 -2148 l=100 w=6289 "vss" "a_n349_n973#" 200 0 "out" 6289 0 "vss" 6289 0
+device msubckt sky130_fd_pr__nfet_01v8 278 -2232 279 -2231 l=100 w=2002 "vss" "a_n349_n973#" 200 0 "a_173_n2232#" 2002 0 "vss" 2002 0
+device msubckt sky130_fd_pr__nfet_01v8 -83 -2092 -82 -2091 l=100 w=1001 "vss" "a_n349_n973#" 200 0 "a_n349_n973#" 1001 0 "vss" 1001 0
+device msubckt sky130_fd_pr__nfet_01v8 507 10 508 11 l=100 w=179 "vss" "in2" 200 0 "a_173_n2232#" 179 0 "a_606_306#" 179 0
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+device rsubckt sky130_fd_pr__res_generic_nd -353 -979 -352 -978 l=2494 w=34 "vss" "a_n353_n979#" 0 0 "a_n349_n973#" 120 0 "a_n469_n962#" 116 0
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diff --git a/mag/layout_opamp.mag b/mag/layout_opamp.mag
new file mode 100644
index 0000000..d5e77e1
--- /dev/null
+++ b/mag/layout_opamp.mag
@@ -0,0 +1,1657 @@
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+<< ndiffc >>
+rect -612 1579 -595 1596
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+<< pdiffc >>
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+<< poly >>
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+<< ndiffres >>
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+<< locali >>
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+<< labels >>
+rlabel locali 835 6660 835 6660 1 vdd
+rlabel locali 1192 4386 1192 4386 1 out
+rlabel locali 705 -2384 705 -2384 1 vss
+rlabel locali 551 -39 551 -39 1 in2
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+<< end >>
diff --git a/mag/layout_opamp.spice b/mag/layout_opamp.spice
new file mode 100644
index 0000000..4321095
--- /dev/null
+++ b/mag/layout_opamp.spice
@@ -0,0 +1,20 @@
+* SPICE3 file created from layout_opamp.ext - technology: sky130A
+
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+X3 a_n349_n973# a_n469_n962# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X4 out a_606_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X5 vdd a_n28_306# a_n28_306# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X6 vss a_n349_n973# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X7 vss a_n349_n973# a_n349_n973# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 a_606_306# in2 a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X9 a_n617_n951# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X10 a_n617_n951# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X11 vss a_n349_n973# a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+C0 in2 vss 138.44fF
+C1 in1 vss 53.47fF
+C2 a_n349_n973# vss 3.86fF
+C3 out vss 117.43fF
+C4 a_n469_n962# vss 3.37fF
+C5 vdd vss 162.65fF
diff --git a/mag/layout_opamp_2.ext b/mag/layout_opamp_2.ext
new file mode 100644
index 0000000..84803d2
--- /dev/null
+++ b/mag/layout_opamp_2.ext
@@ -0,0 +1,58 @@
+timestamp 1640402886
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 1e+06
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__res_generic_nd l=l w=w
+node "in2" 175 134367 506 -110 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33412 868 0 0 13827132 125712 3304077 13654 3167514 7982 4368655 10108 0 0 0 0 0 0
+node "a_173_n2232#" 3848 781.212 173 -2232 ndif 0 0 0 0 0 0 0 0 248158 5354 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123266 5132 0 0 0 0 0 0 0 0 0 0 0 0
+node "in1" 177 89568.5 77 -79 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30400 808 0 0 8746696 72690 3119101 12142 3016356 7870 4060203 9894 0 0 0 0 0 0
+node "a_n349_n973#" 7497 3859.01 -349 -973 ndif 0 0 0 0 0 0 0 0 105898 2332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1024752 22400 0 0 50751 2672 0 0 0 0 0 0 0 0 0 0 0 0
+node "out" 18176 71021 962 304 pdif 0 0 0 0 0 0 0 0 660628 12790 710657 12804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6284244 70446 2648430 7606 2648430 7606 4815054 11214 0 0 0 0 0 0
+node "a_n28_306#" 3910 1294.35 -28 306 pdif 0 0 0 0 0 0 0 0 18258 562 105105 2212 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228528 5384 0 0 68802 3064 0 0 0 0 0 0 0 0 0 0 0 0
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+node "vdd" 38590 131431 -52 244 nw 0 0 0 0 7447400 15252 0 0 405478 12830 878846 17230 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4455005 35486 2695497 7658 2695497 7658 3668977 9724 0 0 0 0 0 0
+substrate "vss" 0 0 -734 -1321 ppd 0 0 0 0 0 0 0 0 1049996 19262 962306 25832 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24350923 146594 2639775 7600 2639775 7600 4995204 11364 0 0 0 0 0 0
+cap "a_n28_306#" "in2" 61.5405
+cap "a_n469_n962#" "a_n617_n951#" 134.725
+cap "in1" "a_173_n2232#" 124.143
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+cap "vdd" "a_606_306#" 283.866
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+cap "vdd" "a_173_n2232#" 26.8899
+cap "a_n541_1558#" "vdd" 131.294
+cap "a_173_n2232#" "in2" 166.434
+cap "a_n541_1558#" "a_n469_n962#" 43.6484
+cap "a_606_306#" "a_173_n2232#" 30.2675
+cap "a_n541_1558#" "in2" 27.4564
+cap "out" "vdd" 349.707
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+cap "in1" "vdd" 105.17
+cap "vdd" "a_n28_306#" 474
+cap "a_n469_n962#" "vdd" 50.9351
+cap "in1" "in2" 1719.17
+cap "a_n469_n962#" "a_n349_n973#" 107.489
+device msubckt sky130_fd_pr__nfet_01v8 1249 -2149 1250 -2148 l=100 w=6289 "vss" "a_n349_n973#" 200 0 "out" 6289 0 "vss" 6289 0
+device msubckt sky130_fd_pr__nfet_01v8 278 -2232 279 -2231 l=100 w=2002 "vss" "a_n349_n973#" 200 0 "a_173_n2232#" 2002 0 "vss" 2002 0
+device msubckt sky130_fd_pr__nfet_01v8 -83 -2092 -82 -2091 l=100 w=1001 "vss" "a_n349_n973#" 200 0 "a_n349_n973#" 1001 0 "vss" 1001 0
+device msubckt sky130_fd_pr__nfet_01v8 507 10 508 11 l=100 w=179 "vss" "in2" 200 0 "a_173_n2232#" 179 0 "a_606_306#" 179 0
+device msubckt sky130_fd_pr__nfet_01v8 77 12 78 13 l=100 w=179 "vss" "in1" 200 0 "a_n28_306#" 179 0 "a_173_n2232#" 179 0
+device msubckt sky130_fd_pr__pfet_01v8 862 304 863 305 l=100 w=6289 "vdd" "a_606_306#" 200 0 "vdd" 6289 0 "out" 6289 0
+device msubckt sky130_fd_pr__pfet_01v8 506 306 507 307 l=100 w=1001 "vdd" "a_n28_306#" 200 0 "vdd" 1001 0 "a_606_306#" 1001 0
+device msubckt sky130_fd_pr__pfet_01v8 77 306 78 307 l=100 w=1001 "vdd" "a_n28_306#" 200 0 "a_n28_306#" 1001 0 "vdd" 1001 0
+device rsubckt sky130_fd_pr__res_generic_nd -353 -979 -352 -978 l=2494 w=34 "vss" "a_n353_n979#" 0 0 "a_n349_n973#" 120 0 "a_n469_n962#" 116 0
+device rsubckt sky130_fd_pr__res_generic_nd -474 -968 -473 -967 l=2492 w=27 "vss" "a_n474_n968#" 0 0 "a_n469_n962#" 116 0 "a_n541_1558#" 116 0
+device rsubckt sky130_fd_pr__res_generic_nd -546 -971 -545 -970 l=2492 w=27 "vss" "a_n546_n971#" 0 0 "a_n617_n951#" 116 0 "a_n541_1558#" 116 0
+device rsubckt sky130_fd_pr__res_generic_nd -622 -957 -621 -956 l=2492 w=27 "vss" "a_n622_n957#" 0 0 "a_n617_n951#" 116 0 "vdd" 116 0
diff --git a/mag/layout_opamp_2.mag b/mag/layout_opamp_2.mag
new file mode 100644
index 0000000..dff0a4e
--- /dev/null
+++ b/mag/layout_opamp_2.mag
@@ -0,0 +1,1663 @@
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+<< labels >>
+rlabel locali 835 6660 835 6660 1 vdd
+rlabel locali 1192 4386 1192 4386 1 out
+rlabel locali 705 -2384 705 -2384 1 vss
+rlabel locali 551 -39 551 -39 1 in2
+rlabel locali 124 -6 124 -6 1 in1
+<< end >>
diff --git a/mag/layout_opamp_2.spice b/mag/layout_opamp_2.spice
new file mode 100644
index 0000000..c6c3072
--- /dev/null
+++ b/mag/layout_opamp_2.spice
@@ -0,0 +1,20 @@
+* SPICE3 file created from layout_opamp_2.ext - technology: sky130A
+
+X0 a_173_n2232# in1 a_n28_306# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X1 a_606_306# a_n28_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X2 a_n469_n962# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X3 a_n349_n973# a_n469_n962# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X4 out a_606_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X5 vdd a_n28_306# a_n28_306# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X6 vss a_n349_n973# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X7 vss a_n349_n973# a_n349_n973# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 a_606_306# in2 a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X9 a_n617_n951# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X10 a_n617_n951# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X11 vss a_n349_n973# a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+C0 in2 vss 134.37fF
+C1 in1 vss 89.57fF
+C2 a_n349_n973# vss 3.86fF
+C3 out vss 71.02fF
+C4 a_n469_n962# vss 3.37fF
+C5 vdd vss 131.43fF
diff --git a/mag/layout_opamp_3.ext b/mag/layout_opamp_3.ext
new file mode 100644
index 0000000..21b7c4a
--- /dev/null
+++ b/mag/layout_opamp_3.ext
@@ -0,0 +1,58 @@
+timestamp 1635438119
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 1e+06
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+parameters sky130_fd_pr__res_generic_nd l=l w=w
+node "in2" 178 214824 -54089 104875 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33412 868 0 0 29186246 157736 678736 8940 542173 3268 5045962 22440 0 0 0 0 0 0
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+rect -55328 102631 -53005 102633
+rect -55328 102592 -55313 102631
+rect -55264 102627 -53005 102631
+rect -55264 102592 -55009 102627
+rect -55328 102588 -55009 102592
+rect -54960 102625 -53005 102627
+rect -54960 102588 -54687 102625
+rect -55328 102585 -54687 102588
+rect -54638 102585 -54187 102625
+rect -54138 102585 -53687 102625
+rect -53638 102585 -53187 102625
+rect -53138 102593 -53005 102625
+rect -52954 102593 -52940 102633
+rect -53138 102585 -52940 102593
+rect -55328 102576 -52940 102585
+rect -53717 102322 -53613 102576
+rect -53859 78813 -53132 102322
+rect -54171 78790 -52613 78813
+rect -54179 78513 -52613 78790
+rect -54179 77730 -53818 78513
+rect -52874 77730 -52613 78513
+rect -54179 77469 -52613 77730
+rect -54171 77454 -52613 77469
+rect -57328 31116 -56157 31242
+rect -57328 30863 -56998 31116
+rect -56361 30863 -56157 31116
+rect -57328 30779 -56157 30863
+<< viali >>
+rect -66428 124302 -65899 124993
+rect -62308 114712 -61770 115121
+rect -61357 114707 -60819 115116
+rect -60545 114714 -60007 115123
+rect -59190 114718 -58652 115127
+rect -54828 106781 -54794 106810
+rect -54830 106728 -54796 106757
+rect -54723 106729 -54692 106761
+rect -62103 52494 -61490 52846
+rect -54482 104935 -54459 104961
+rect -54058 104820 -54020 104852
+rect -53818 77730 -52874 78513
+rect -56998 30863 -56361 31116
+<< metal1 >>
+rect -66599 124993 -65639 125392
+rect -66599 124302 -66428 124993
+rect -65899 124302 -65639 124993
+rect -66599 123870 -65639 124302
+rect -62752 115127 -58419 115300
+rect -62752 115123 -59190 115127
+rect -62752 115121 -60545 115123
+rect -62752 114712 -62308 115121
+rect -61770 115116 -60545 115121
+rect -61770 114712 -61357 115116
+rect -62752 114707 -61357 114712
+rect -60819 114712 -60545 115116
+rect -60007 114718 -59190 115123
+rect -58652 114718 -58419 115127
+rect -60007 114712 -58419 114718
+rect -60819 114707 -58419 114712
+rect -62752 114527 -58419 114707
+rect -54839 106810 -54790 106819
+rect -54839 106781 -54828 106810
+rect -54794 106781 -54790 106810
+rect -54839 106757 -54790 106781
+rect -54839 106728 -54830 106757
+rect -54796 106728 -54790 106757
+rect -54839 104861 -54790 106728
+rect -54733 106761 -54684 106771
+rect -54733 106729 -54723 106761
+rect -54692 106729 -54684 106761
+rect -54733 104976 -54684 106729
+rect -54733 104961 -54443 104976
+rect -54733 104935 -54482 104961
+rect -54459 104935 -54443 104961
+rect -54733 104925 -54443 104935
+rect -54839 104852 -54010 104861
+rect -54839 104820 -54058 104852
+rect -54020 104820 -54010 104852
+rect -54839 104812 -54010 104820
+rect -54179 78513 -52628 78790
+rect -54179 77730 -53818 78513
+rect -52874 77730 -52628 78513
+rect -54179 77469 -52628 77730
+rect -62482 52846 -61177 53038
+rect -62482 52494 -62103 52846
+rect -61490 52494 -61177 52846
+rect -62482 52357 -61177 52494
+rect -57328 31116 -56157 31242
+rect -57328 30863 -56998 31116
+rect -56361 30863 -56157 31116
+rect -57328 30779 -56157 30863
+<< via1 >>
+rect -66428 124302 -65899 124993
+rect -62308 114712 -61770 115121
+rect -61357 114707 -60819 115116
+rect -60545 114714 -60007 115121
+rect -60545 114712 -60007 114714
+rect -53818 77730 -52874 78513
+rect -62103 52494 -61490 52846
+rect -56998 30863 -56361 31116
+<< metal2 >>
+rect -66599 124993 -65639 125392
+rect -66599 124302 -66428 124993
+rect -65899 124302 -65639 124993
+rect -66599 123870 -65639 124302
+rect -62752 115121 -58419 115300
+rect -62752 114712 -62308 115121
+rect -61770 115116 -60545 115121
+rect -61770 114712 -61357 115116
+rect -62752 114707 -61357 114712
+rect -60819 114712 -60545 115116
+rect -60007 114712 -58419 115121
+rect -60819 114707 -58419 114712
+rect -62752 114527 -58419 114707
+rect -54179 78513 -52628 78790
+rect -54179 77730 -53818 78513
+rect -52874 77730 -52628 78513
+rect -54179 77469 -52628 77730
+rect -62482 52846 -61177 53038
+rect -62482 52494 -62103 52846
+rect -61490 52494 -61177 52846
+rect -62482 52357 -61177 52494
+rect -57328 31116 -56157 31242
+rect -57328 30863 -56998 31116
+rect -56361 30863 -56157 31116
+rect -57328 30779 -56157 30863
+<< via2 >>
+rect -66428 124302 -65899 124993
+rect -62308 114712 -61770 115121
+rect -61357 114707 -60819 115116
+rect -60545 114712 -60007 115121
+rect -53818 77730 -52874 78513
+rect -62103 52494 -61490 52846
+rect -56998 30863 -56361 31116
+<< metal3 >>
+rect -66681 136547 -66218 137753
+rect -66681 135094 -66205 136547
+rect -66610 125392 -66205 135094
+rect -66610 124993 -65639 125392
+rect -66610 124302 -66428 124993
+rect -65899 124302 -65639 124993
+rect -66610 123890 -65639 124302
+rect -66599 123870 -65639 123890
+rect -66595 115300 -64884 115309
+rect -66595 115121 -58419 115300
+rect -66595 114712 -62308 115121
+rect -61770 115116 -60545 115121
+rect -61770 114712 -61357 115116
+rect -66595 114707 -61357 114712
+rect -60819 114712 -60545 115116
+rect -60007 114712 -58419 115121
+rect -60819 114707 -58419 114712
+rect -66595 114527 -58419 114707
+rect -66595 114526 -64884 114527
+rect -54171 78513 -52613 78813
+rect -54171 78012 -53818 78513
+rect -66729 77730 -53818 78012
+rect -52874 77730 -52613 78513
+rect -66729 77466 -52613 77730
+rect -54171 77454 -52613 77466
+rect -64339 52846 -61229 53038
+rect -64339 52845 -62103 52846
+rect -67009 52494 -62103 52845
+rect -61490 52494 -61229 52846
+rect -67009 52376 -61229 52494
+rect -64339 52357 -61229 52376
+rect -64716 31252 -61805 31254
+rect -66924 31245 -61805 31252
+rect -59455 31245 -56187 31248
+rect -66924 31116 -56187 31245
+rect -66924 30863 -56998 31116
+rect -56361 30863 -56187 31116
+rect -66924 30785 -56187 30863
+rect -66924 30783 -64013 30785
+rect -62229 30779 -56187 30785
+rect -62229 30777 -56980 30779
+rect -62229 30776 -59318 30777
+<< labels >>
+rlabel locali -53760 111645 -53760 111645 1 vdd
+rlabel locali -53403 109371 -53403 109371 1 out
+rlabel locali -53890 102601 -53890 102601 1 vss
+rlabel locali -54044 104946 -54044 104946 1 in2
+rlabel locali -54471 104979 -54471 104979 1 in1
+<< end >>
diff --git a/mag/layout_opamp_3.spice b/mag/layout_opamp_3.spice
new file mode 100644
index 0000000..9fef097
--- /dev/null
+++ b/mag/layout_opamp_3.spice
@@ -0,0 +1,20 @@
+* SPICE3 file created from layout_opamp_3.ext - technology: sky130A
+
+X0 a_n55212_104034# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X1 a_n55064_104023# a_n55136_106543# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X2 a_n54944_104012# a_n55064_104023# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X3 out a_n53989_105291# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X4 a_n55212_104034# a_n55136_106543# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X5 a_n53989_105291# in2 a_n54422_102753# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X6 vss a_n54944_104012# a_n54422_102753# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+X7 vdd a_n54623_105291# a_n54623_105291# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 vss a_n54944_104012# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X9 a_n54422_102753# in1 a_n54623_105291# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X10 a_n53989_105291# a_n54623_105291# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X11 vss a_n54944_104012# a_n54944_104012# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+C0 in2 vss 214.82fF
+C1 in1 vss 166.10fF
+C2 a_n54944_104012# vss 3.86fF
+C3 out vss 166.10fF
+C4 a_n55064_104023# vss 3.37fF
+C5 vdd vss 152.94fF
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
new file mode 100644
index 0000000..c4fedfd
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606502073
+<< metal3 >>
+rect -3136 3072 3136 3100
+rect -3136 -3072 3052 3072
+rect 3116 -3072 3136 3072
+rect -3136 -3100 3136 -3072
+<< via3 >>
+rect 3052 -3072 3116 3072
+<< mimcap >>
+rect -3036 2960 2964 3000
+rect -3036 -2960 2332 2960
+rect 2924 -2960 2964 2960
+rect -3036 -3000 2964 -2960
+<< mimcapcontact >>
+rect 2332 -2960 2924 2960
+<< metal4 >>
+rect 3036 3072 3132 3088
+rect 2331 2960 2925 2961
+rect 2331 -2960 2332 2960
+rect 2924 -2960 2925 2960
+rect 2331 -2961 2925 -2960
+rect 3036 -3072 3052 3072
+rect 3116 -3072 3132 3072
+rect 3036 -3088 3132 -3072
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX -3136 -3100 3064 3100
+string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov -10
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
new file mode 100644
index 0000000..59928eb
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606502073
+<< metal4 >>
+rect -3179 3059 3179 3100
+rect -3179 -3059 2923 3059
+rect 3159 -3059 3179 3059
+rect -3179 -3100 3179 -3059
+<< via4 >>
+rect 2923 -3059 3159 3059
+<< mimcap2 >>
+rect -3079 2960 2921 3000
+rect -3079 -2960 -3039 2960
+rect 2289 -2960 2921 2960
+rect -3079 -3000 2921 -2960
+<< mimcap2contact >>
+rect -3039 -2960 2289 2960
+<< metal5 >>
+rect 2881 3059 3201 3101
+rect -3063 2960 2313 2984
+rect -3063 -2960 -3039 2960
+rect 2289 -2960 2313 2960
+rect -3063 -2984 2313 -2960
+rect 2881 -3059 2923 3059
+rect 3159 -3059 3201 3059
+rect 2881 -3101 3201 -3059
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_2
+string FIXED_BBOX -3179 -3100 3021 3100
+string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov +90
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
new file mode 100644
index 0000000..7be65d4
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
@@ -0,0 +1,98 @@
+magic
+tech sky130A
+timestamp 1606063140
+<< pwell >>
+rect -154 -229 154 229
+<< mvnmos >>
+rect -40 -100 40 100
+<< mvndiff >>
+rect -69 94 -40 100
+rect -69 -94 -63 94
+rect -46 -94 -40 94
+rect -69 -100 -40 -94
+rect 40 94 69 100
+rect 40 -94 46 94
+rect 63 -94 69 94
+rect 40 -100 69 -94
+<< mvndiffc >>
+rect -63 -94 -46 94
+rect 46 -94 63 94
+<< mvpsubdiff >>
+rect -136 205 136 211
+rect -136 188 -82 205
+rect 82 188 136 205
+rect -136 182 136 188
+rect -136 -182 -107 182
+rect 107 157 136 182
+rect 107 -157 113 157
+rect 130 -157 136 157
+rect 107 -182 136 -157
+rect -136 -188 136 -182
+rect -136 -205 -82 -188
+rect 82 -205 136 -188
+rect -136 -211 136 -205
+<< mvpsubdiffcont >>
+rect -82 188 82 205
+rect 113 -157 130 157
+rect -82 -205 82 -188
+<< poly >>
+rect -40 136 40 144
+rect -40 119 -32 136
+rect 32 119 40 136
+rect -40 100 40 119
+rect -40 -119 40 -100
+rect -40 -136 -32 -119
+rect 32 -136 40 -119
+rect -40 -144 40 -136
+<< polycont >>
+rect -32 119 32 136
+rect -32 -136 32 -119
+<< locali >>
+rect -130 188 -82 205
+rect 82 188 130 205
+rect -130 -19 -113 188
+rect 113 157 130 188
+rect -40 119 -32 136
+rect 32 119 40 136
+rect -63 94 -46 102
+rect -63 -102 -46 -94
+rect 46 94 63 102
+rect 46 -102 63 -94
+rect -40 -136 -32 -119
+rect 32 -136 40 -119
+rect 113 -188 130 -157
+rect -130 -205 -82 -188
+rect 82 -205 130 -188
+<< viali >>
+rect -32 119 32 136
+rect -130 -188 -113 -19
+rect -63 -94 -46 94
+rect 46 -94 63 94
+rect -32 -136 32 -119
+<< metal1 >>
+rect -38 136 38 139
+rect -38 119 -32 136
+rect 32 119 38 136
+rect -38 116 38 119
+rect -66 94 -43 100
+rect -133 -19 -110 -13
+rect -133 -188 -130 -19
+rect -113 -188 -110 -19
+rect -66 -94 -63 94
+rect -46 -94 -43 94
+rect -66 -100 -43 -94
+rect 43 94 66 100
+rect 43 -94 46 94
+rect 63 -94 66 94
+rect 43 -100 66 -94
+rect -38 -119 38 -116
+rect -38 -136 -32 -119
+rect 32 -136 38 -119
+rect -38 -139 38 -136
+rect -133 -194 -110 -188
+<< properties >>
+string gencell sky130_fd_pr__nfet_g5v0d10v5
+string FIXED_BBOX -121 -196 121 196
+string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl +45 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
new file mode 100644
index 0000000..0fc9bf5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
@@ -0,0 +1,326 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< pwell >>
+rect -962 -458 962 458
+<< mvnmos >>
+rect -734 -200 -574 200
+rect -516 -200 -356 200
+rect -298 -200 -138 200
+rect -80 -200 80 200
+rect 138 -200 298 200
+rect 356 -200 516 200
+rect 574 -200 734 200
+<< mvndiff >>
+rect -792 188 -734 200
+rect -792 -188 -780 188
+rect -746 -188 -734 188
+rect -792 -200 -734 -188
+rect -574 188 -516 200
+rect -574 -188 -562 188
+rect -528 -188 -516 188
+rect -574 -200 -516 -188
+rect -356 188 -298 200
+rect -356 -188 -344 188
+rect -310 -188 -298 188
+rect -356 -200 -298 -188
+rect -138 188 -80 200
+rect -138 -188 -126 188
+rect -92 -188 -80 188
+rect -138 -200 -80 -188
+rect 80 188 138 200
+rect 80 -188 92 188
+rect 126 -188 138 188
+rect 80 -200 138 -188
+rect 298 188 356 200
+rect 298 -188 310 188
+rect 344 -188 356 188
+rect 298 -200 356 -188
+rect 516 188 574 200
+rect 516 -188 528 188
+rect 562 -188 574 188
+rect 516 -200 574 -188
+rect 734 188 792 200
+rect 734 -188 746 188
+rect 780 -188 792 188
+rect 734 -200 792 -188
+<< mvndiffc >>
+rect -780 -188 -746 188
+rect -562 -188 -528 188
+rect -344 -188 -310 188
+rect -126 -188 -92 188
+rect 92 -188 126 188
+rect 310 -188 344 188
+rect 528 -188 562 188
+rect 746 -188 780 188
+<< mvpsubdiff >>
+rect -926 410 926 422
+rect -926 376 -818 410
+rect 818 376 926 410
+rect -926 364 926 376
+rect -926 314 -868 364
+rect -926 -314 -914 314
+rect -880 -314 -868 314
+rect 868 314 926 364
+rect -926 -364 -868 -314
+rect 868 -314 880 314
+rect 914 -314 926 314
+rect 868 -364 926 -314
+rect -926 -376 926 -364
+rect -926 -410 -818 -376
+rect 818 -410 926 -376
+rect -926 -422 926 -410
+<< mvpsubdiffcont >>
+rect -818 376 818 410
+rect -914 -314 -880 314
+rect 880 -314 914 314
+rect -818 -410 818 -376
+<< poly >>
+rect -734 272 -574 288
+rect -734 238 -718 272
+rect -590 238 -574 272
+rect -734 200 -574 238
+rect -516 272 -356 288
+rect -516 238 -500 272
+rect -372 238 -356 272
+rect -516 200 -356 238
+rect -298 272 -138 288
+rect -298 238 -282 272
+rect -154 238 -138 272
+rect -298 200 -138 238
+rect -80 272 80 288
+rect -80 238 -64 272
+rect 64 238 80 272
+rect -80 200 80 238
+rect 138 272 298 288
+rect 138 238 154 272
+rect 282 238 298 272
+rect 138 200 298 238
+rect 356 272 516 288
+rect 356 238 372 272
+rect 500 238 516 272
+rect 356 200 516 238
+rect 574 272 734 288
+rect 574 238 590 272
+rect 718 238 734 272
+rect 574 200 734 238
+rect -734 -238 -574 -200
+rect -734 -272 -718 -238
+rect -590 -272 -574 -238
+rect -734 -288 -574 -272
+rect -516 -238 -356 -200
+rect -516 -272 -500 -238
+rect -372 -272 -356 -238
+rect -516 -288 -356 -272
+rect -298 -238 -138 -200
+rect -298 -272 -282 -238
+rect -154 -272 -138 -238
+rect -298 -288 -138 -272
+rect -80 -238 80 -200
+rect -80 -272 -64 -238
+rect 64 -272 80 -238
+rect -80 -288 80 -272
+rect 138 -238 298 -200
+rect 138 -272 154 -238
+rect 282 -272 298 -238
+rect 138 -288 298 -272
+rect 356 -238 516 -200
+rect 356 -272 372 -238
+rect 500 -272 516 -238
+rect 356 -288 516 -272
+rect 574 -238 734 -200
+rect 574 -272 590 -238
+rect 718 -272 734 -238
+rect 574 -288 734 -272
+<< polycont >>
+rect -718 238 -590 272
+rect -500 238 -372 272
+rect -282 238 -154 272
+rect -64 238 64 272
+rect 154 238 282 272
+rect 372 238 500 272
+rect 590 238 718 272
+rect -718 -272 -590 -238
+rect -500 -272 -372 -238
+rect -282 -272 -154 -238
+rect -64 -272 64 -238
+rect 154 -272 282 -238
+rect 372 -272 500 -238
+rect 590 -272 718 -238
+<< locali >>
+rect -914 376 -818 410
+rect 818 376 914 410
+rect -914 314 -880 376
+rect 880 314 914 376
+rect -734 238 -718 272
+rect -590 238 -574 272
+rect -516 238 -500 272
+rect -372 238 -356 272
+rect -298 238 -282 272
+rect -154 238 -138 272
+rect -80 238 -64 272
+rect 64 238 80 272
+rect 138 238 154 272
+rect 282 238 298 272
+rect 356 238 372 272
+rect 500 238 516 272
+rect 574 238 590 272
+rect 718 238 734 272
+rect -780 188 -746 204
+rect -780 -204 -746 -188
+rect -562 188 -528 204
+rect -562 -204 -528 -188
+rect -344 188 -310 204
+rect -344 -204 -310 -188
+rect -126 188 -92 204
+rect -126 -204 -92 -188
+rect 92 188 126 204
+rect 92 -204 126 -188
+rect 310 188 344 204
+rect 310 -204 344 -188
+rect 528 188 562 204
+rect 528 -204 562 -188
+rect 746 188 780 204
+rect 746 -204 780 -188
+rect -734 -272 -718 -238
+rect -590 -272 -574 -238
+rect -516 -272 -500 -238
+rect -372 -272 -356 -238
+rect -298 -272 -282 -238
+rect -154 -272 -138 -238
+rect -80 -272 -64 -238
+rect 64 -272 80 -238
+rect 138 -272 154 -238
+rect 282 -272 298 -238
+rect 356 -272 372 -238
+rect 500 -272 516 -238
+rect 574 -272 590 -238
+rect 718 -272 734 -238
+rect -914 -376 -880 -314
+rect 880 -376 914 -314
+rect -914 -410 -818 -376
+rect 818 -410 914 -376
+<< viali >>
+rect -914 -263 -880 263
+rect -718 238 -590 272
+rect -500 238 -372 272
+rect -282 238 -154 272
+rect -64 238 64 272
+rect 154 238 282 272
+rect 372 238 500 272
+rect 590 238 718 272
+rect -780 21 -746 171
+rect -562 -171 -528 -21
+rect -344 21 -310 171
+rect -126 -171 -92 -21
+rect 92 21 126 171
+rect 310 -171 344 -21
+rect 528 21 562 171
+rect 746 -171 780 -21
+rect -718 -272 -590 -238
+rect -500 -272 -372 -238
+rect -282 -272 -154 -238
+rect -64 -272 64 -238
+rect 154 -272 282 -238
+rect 372 -272 500 -238
+rect 590 -272 718 -238
+<< metal1 >>
+rect -920 263 -874 275
+rect -920 -263 -914 263
+rect -880 -263 -874 263
+rect -730 272 -578 278
+rect -730 238 -718 272
+rect -590 238 -578 272
+rect -730 232 -578 238
+rect -512 272 -360 278
+rect -512 238 -500 272
+rect -372 238 -360 272
+rect -512 232 -360 238
+rect -294 272 -142 278
+rect -294 238 -282 272
+rect -154 238 -142 272
+rect -294 232 -142 238
+rect -76 272 76 278
+rect -76 238 -64 272
+rect 64 238 76 272
+rect -76 232 76 238
+rect 142 272 294 278
+rect 142 238 154 272
+rect 282 238 294 272
+rect 142 232 294 238
+rect 360 272 512 278
+rect 360 238 372 272
+rect 500 238 512 272
+rect 360 232 512 238
+rect 578 272 730 278
+rect 578 238 590 272
+rect 718 238 730 272
+rect 578 232 730 238
+rect -786 171 -740 183
+rect -786 21 -780 171
+rect -746 21 -740 171
+rect -786 9 -740 21
+rect -350 171 -304 183
+rect -350 21 -344 171
+rect -310 21 -304 171
+rect -350 9 -304 21
+rect 86 171 132 183
+rect 86 21 92 171
+rect 126 21 132 171
+rect 86 9 132 21
+rect 522 171 568 183
+rect 522 21 528 171
+rect 562 21 568 171
+rect 522 9 568 21
+rect -568 -21 -522 -9
+rect -568 -171 -562 -21
+rect -528 -171 -522 -21
+rect -568 -183 -522 -171
+rect -132 -21 -86 -9
+rect -132 -171 -126 -21
+rect -92 -171 -86 -21
+rect -132 -183 -86 -171
+rect 304 -21 350 -9
+rect 304 -171 310 -21
+rect 344 -171 350 -21
+rect 304 -183 350 -171
+rect 740 -21 786 -9
+rect 740 -171 746 -21
+rect 780 -171 786 -21
+rect 740 -183 786 -171
+rect -920 -275 -874 -263
+rect -730 -238 -578 -232
+rect -730 -272 -718 -238
+rect -590 -272 -578 -238
+rect -730 -278 -578 -272
+rect -512 -238 -360 -232
+rect -512 -272 -500 -238
+rect -372 -272 -360 -238
+rect -512 -278 -360 -272
+rect -294 -238 -142 -232
+rect -294 -272 -282 -238
+rect -154 -272 -142 -238
+rect -294 -278 -142 -272
+rect -76 -238 76 -232
+rect -76 -272 -64 -238
+rect 64 -272 76 -238
+rect -76 -278 76 -272
+rect 142 -238 294 -232
+rect 142 -272 154 -238
+rect 282 -272 294 -238
+rect 142 -278 294 -272
+rect 360 -238 512 -232
+rect 360 -272 372 -238
+rect 500 -272 512 -238
+rect 360 -278 512 -272
+rect 578 -238 730 -232
+rect 578 -272 590 -238
+rect 718 -272 730 -238
+rect 578 -278 730 -272
+<< properties >>
+string gencell sky130_fd_pr__nfet_g5v0d10v5
+string FIXED_BBOX -897 -393 897 393
+string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc +40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 70 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
new file mode 100644
index 0000000..eb312e6
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
@@ -0,0 +1,93 @@
+magic
+tech sky130A
+timestamp 1605994897
+<< pwell >>
+rect -154 -229 154 229
+<< mvnmos >>
+rect -40 -100 40 100
+<< mvndiff >>
+rect -69 94 -40 100
+rect -69 -94 -63 94
+rect -46 -94 -40 94
+rect -69 -100 -40 -94
+rect 40 94 69 100
+rect 40 -94 46 94
+rect 63 -94 69 94
+rect 40 -100 69 -94
+<< mvndiffc >>
+rect -63 -94 -46 94
+rect 46 -94 63 94
+<< mvpsubdiff >>
+rect -136 205 136 211
+rect -136 188 -82 205
+rect 82 188 136 205
+rect -136 182 136 188
+rect -136 -182 -107 182
+rect 107 157 136 182
+rect 107 -157 113 157
+rect 130 -157 136 157
+rect 107 -182 136 -157
+rect -136 -188 136 -182
+rect -136 -205 -82 -188
+rect 82 -205 136 -188
+rect -136 -211 136 -205
+<< mvpsubdiffcont >>
+rect -82 188 82 205
+rect 113 -157 130 157
+rect -82 -205 82 -188
+<< poly >>
+rect -40 136 40 144
+rect -40 119 -32 136
+rect 32 119 40 136
+rect -40 100 40 119
+rect -40 -119 40 -100
+rect -40 -136 -32 -119
+rect 32 -136 40 -119
+rect -40 -144 40 -136
+<< polycont >>
+rect -32 119 32 136
+rect -32 -136 32 -119
+<< locali >>
+rect -130 188 -82 205
+rect 82 188 130 205
+rect -130 -188 -113 188
+rect 113 157 130 188
+rect -40 119 -32 136
+rect 32 119 40 136
+rect -63 94 -46 102
+rect -63 -102 -46 -94
+rect 46 94 63 102
+rect 46 -102 63 -94
+rect -40 -136 -32 -119
+rect 32 -136 40 -119
+rect 113 -188 130 -157
+rect -130 -205 -82 -188
+rect 82 -205 130 -188
+<< viali >>
+rect -32 119 32 136
+rect -63 -94 -46 94
+rect 46 -94 63 94
+rect -32 -136 32 -119
+<< metal1 >>
+rect -38 136 38 139
+rect -38 119 -32 136
+rect 32 119 38 136
+rect -38 116 38 119
+rect -66 94 -43 100
+rect -66 -94 -63 94
+rect -46 -94 -43 94
+rect -66 -100 -43 -94
+rect 43 94 66 100
+rect 43 -94 46 94
+rect 63 -94 66 94
+rect 43 -100 66 -94
+rect -38 -119 38 -116
+rect -38 -136 -32 -119
+rect 32 -136 38 -119
+rect -38 -139 38 -136
+<< properties >>
+string gencell sky130_fd_pr__nfet_g5v0d10v5
+string FIXED_BBOX -121 -196 121 196
+string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
new file mode 100644
index 0000000..e0b0219
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
@@ -0,0 +1,106 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< nwell >>
+rect -338 -497 338 497
+<< mvpmos >>
+rect -80 -200 80 200
+<< mvpdiff >>
+rect -138 188 -80 200
+rect -138 -188 -126 188
+rect -92 -188 -80 188
+rect -138 -200 -80 -188
+rect 80 188 138 200
+rect 80 -188 92 188
+rect 126 -188 138 188
+rect 80 -200 138 -188
+<< mvpdiffc >>
+rect -126 -188 -92 188
+rect 92 -188 126 188
+<< mvnsubdiff >>
+rect -272 419 272 431
+rect -272 385 -164 419
+rect 164 385 272 419
+rect -272 373 272 385
+rect -272 323 -214 373
+rect -272 -323 -260 323
+rect -226 -323 -214 323
+rect 214 323 272 373
+rect -272 -373 -214 -323
+rect 214 -323 226 323
+rect 260 -323 272 323
+rect 214 -373 272 -323
+rect -272 -385 272 -373
+rect -272 -419 -164 -385
+rect 164 -419 272 -385
+rect -272 -431 272 -419
+<< mvnsubdiffcont >>
+rect -164 385 164 419
+rect -260 -323 -226 323
+rect 226 -323 260 323
+rect -164 -419 164 -385
+<< poly >>
+rect -80 281 80 297
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -80 200 80 247
+rect -80 -247 80 -200
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -80 -297 80 -281
+<< polycont >>
+rect -64 247 64 281
+rect -64 -281 64 -247
+<< locali >>
+rect -260 385 -181 419
+rect 181 385 260 419
+rect -260 323 -226 385
+rect 226 323 260 385
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -126 188 -92 204
+rect -126 -204 -92 -188
+rect 92 188 126 204
+rect 92 -204 126 -188
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -260 -385 -226 -323
+rect 226 -385 260 -323
+rect -260 -419 -164 -385
+rect 164 -419 260 -385
+<< viali >>
+rect -181 385 -164 419
+rect -164 385 164 419
+rect 164 385 181 419
+rect -64 247 64 281
+rect -126 -188 -92 188
+rect 92 -188 126 188
+rect -64 -281 64 -247
+<< metal1 >>
+rect -193 419 193 425
+rect -193 385 -181 419
+rect 181 385 193 419
+rect -193 379 193 385
+rect -76 281 76 287
+rect -76 247 -64 281
+rect 64 247 76 281
+rect -76 241 76 247
+rect -132 188 -86 200
+rect -132 -188 -126 188
+rect -92 -188 -86 188
+rect -132 -200 -86 -188
+rect 86 188 132 200
+rect 86 -188 92 188
+rect 126 -188 132 188
+rect 86 -200 132 -188
+rect -76 -247 76 -241
+rect -76 -281 -64 -247
+rect 64 -281 76 -247
+rect -76 -287 76 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_g5v0d10v5
+string FIXED_BBOX -243 -402 243 402
+string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
new file mode 100644
index 0000000..08a17b0
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
@@ -0,0 +1,331 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< nwell >>
+rect -992 -497 992 497
+<< mvpmos >>
+rect -734 -200 -574 200
+rect -516 -200 -356 200
+rect -298 -200 -138 200
+rect -80 -200 80 200
+rect 138 -200 298 200
+rect 356 -200 516 200
+rect 574 -200 734 200
+<< mvpdiff >>
+rect -792 188 -734 200
+rect -792 -188 -780 188
+rect -746 -188 -734 188
+rect -792 -200 -734 -188
+rect -574 188 -516 200
+rect -574 -188 -562 188
+rect -528 -188 -516 188
+rect -574 -200 -516 -188
+rect -356 188 -298 200
+rect -356 -188 -344 188
+rect -310 -188 -298 188
+rect -356 -200 -298 -188
+rect -138 188 -80 200
+rect -138 -188 -126 188
+rect -92 -188 -80 188
+rect -138 -200 -80 -188
+rect 80 188 138 200
+rect 80 -188 92 188
+rect 126 -188 138 188
+rect 80 -200 138 -188
+rect 298 188 356 200
+rect 298 -188 310 188
+rect 344 -188 356 188
+rect 298 -200 356 -188
+rect 516 188 574 200
+rect 516 -188 528 188
+rect 562 -188 574 188
+rect 516 -200 574 -188
+rect 734 188 792 200
+rect 734 -188 746 188
+rect 780 -188 792 188
+rect 734 -200 792 -188
+<< mvpdiffc >>
+rect -780 -188 -746 188
+rect -562 -188 -528 188
+rect -344 -188 -310 188
+rect -126 -188 -92 188
+rect 92 -188 126 188
+rect 310 -188 344 188
+rect 528 -188 562 188
+rect 746 -188 780 188
+<< mvnsubdiff >>
+rect -926 419 926 431
+rect -926 385 -818 419
+rect 818 385 926 419
+rect -926 373 926 385
+rect -926 323 -868 373
+rect -926 -323 -914 323
+rect -880 -323 -868 323
+rect 868 323 926 373
+rect -926 -373 -868 -323
+rect 868 -323 880 323
+rect 914 -323 926 323
+rect 868 -373 926 -323
+rect -926 -385 926 -373
+rect -926 -419 -818 -385
+rect 818 -419 926 -385
+rect -926 -431 926 -419
+<< mvnsubdiffcont >>
+rect -818 385 818 419
+rect -914 -323 -880 323
+rect 880 -323 914 323
+rect -818 -419 818 -385
+<< poly >>
+rect -734 281 -574 297
+rect -734 247 -718 281
+rect -590 247 -574 281
+rect -734 200 -574 247
+rect -516 281 -356 297
+rect -516 247 -500 281
+rect -372 247 -356 281
+rect -516 200 -356 247
+rect -298 281 -138 297
+rect -298 247 -282 281
+rect -154 247 -138 281
+rect -298 200 -138 247
+rect -80 281 80 297
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -80 200 80 247
+rect 138 281 298 297
+rect 138 247 154 281
+rect 282 247 298 281
+rect 138 200 298 247
+rect 356 281 516 297
+rect 356 247 372 281
+rect 500 247 516 281
+rect 356 200 516 247
+rect 574 281 734 297
+rect 574 247 590 281
+rect 718 247 734 281
+rect 574 200 734 247
+rect -734 -247 -574 -200
+rect -734 -281 -718 -247
+rect -590 -281 -574 -247
+rect -734 -297 -574 -281
+rect -516 -247 -356 -200
+rect -516 -281 -500 -247
+rect -372 -281 -356 -247
+rect -516 -297 -356 -281
+rect -298 -247 -138 -200
+rect -298 -281 -282 -247
+rect -154 -281 -138 -247
+rect -298 -297 -138 -281
+rect -80 -247 80 -200
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -80 -297 80 -281
+rect 138 -247 298 -200
+rect 138 -281 154 -247
+rect 282 -281 298 -247
+rect 138 -297 298 -281
+rect 356 -247 516 -200
+rect 356 -281 372 -247
+rect 500 -281 516 -247
+rect 356 -297 516 -281
+rect 574 -247 734 -200
+rect 574 -281 590 -247
+rect 718 -281 734 -247
+rect 574 -297 734 -281
+<< polycont >>
+rect -718 247 -590 281
+rect -500 247 -372 281
+rect -282 247 -154 281
+rect -64 247 64 281
+rect 154 247 282 281
+rect 372 247 500 281
+rect 590 247 718 281
+rect -718 -281 -590 -247
+rect -500 -281 -372 -247
+rect -282 -281 -154 -247
+rect -64 -281 64 -247
+rect 154 -281 282 -247
+rect 372 -281 500 -247
+rect 590 -281 718 -247
+<< locali >>
+rect -914 385 -818 419
+rect 818 385 914 419
+rect 880 323 914 385
+rect -734 247 -718 281
+rect -590 247 -574 281
+rect -516 247 -500 281
+rect -372 247 -356 281
+rect -298 247 -282 281
+rect -154 247 -138 281
+rect -80 247 -64 281
+rect 64 247 80 281
+rect 138 247 154 281
+rect 282 247 298 281
+rect 356 247 372 281
+rect 500 247 516 281
+rect 574 247 590 281
+rect 718 247 734 281
+rect -780 188 -746 204
+rect -780 -204 -746 -188
+rect -562 188 -528 204
+rect -562 -204 -528 -188
+rect -344 188 -310 204
+rect -344 -204 -310 -188
+rect -126 188 -92 204
+rect -126 -204 -92 -188
+rect 92 188 126 204
+rect 92 -204 126 -188
+rect 310 188 344 204
+rect 310 -204 344 -188
+rect 528 188 562 204
+rect 528 -204 562 -188
+rect 746 188 780 204
+rect 746 -204 780 -188
+rect -734 -281 -718 -247
+rect -590 -281 -574 -247
+rect -516 -281 -500 -247
+rect -372 -281 -356 -247
+rect -298 -281 -282 -247
+rect -154 -281 -138 -247
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect 138 -281 154 -247
+rect 282 -281 298 -247
+rect 356 -281 372 -247
+rect 500 -281 516 -247
+rect 574 -281 590 -247
+rect 718 -281 734 -247
+rect -914 -385 -880 -323
+rect 880 -385 914 -323
+rect -914 -419 -818 -385
+rect 818 -419 914 -385
+<< viali >>
+rect -792 385 792 419
+rect -914 323 -880 385
+rect -914 38 -880 323
+rect -718 247 -590 281
+rect -500 247 -372 281
+rect -282 247 -154 281
+rect -64 247 64 281
+rect 154 247 282 281
+rect 372 247 500 281
+rect 590 247 718 281
+rect -780 21 -746 171
+rect -562 -171 -528 -21
+rect -344 21 -310 171
+rect -126 -171 -92 -21
+rect 92 21 126 171
+rect 310 -171 344 -21
+rect 528 21 562 171
+rect 746 -171 780 -21
+rect -718 -281 -590 -247
+rect -500 -281 -372 -247
+rect -282 -281 -154 -247
+rect -64 -281 64 -247
+rect 154 -281 282 -247
+rect 372 -281 500 -247
+rect 590 -281 718 -247
+<< metal1 >>
+rect -804 419 804 425
+rect -920 385 -874 397
+rect -920 38 -914 385
+rect -880 38 -874 385
+rect -804 385 -792 419
+rect 792 385 804 419
+rect -804 379 804 385
+rect -730 281 -578 287
+rect -730 247 -718 281
+rect -590 247 -578 281
+rect -730 241 -578 247
+rect -512 281 -360 287
+rect -512 247 -500 281
+rect -372 247 -360 281
+rect -512 241 -360 247
+rect -294 281 -142 287
+rect -294 247 -282 281
+rect -154 247 -142 281
+rect -294 241 -142 247
+rect -76 281 76 287
+rect -76 247 -64 281
+rect 64 247 76 281
+rect -76 241 76 247
+rect 142 281 294 287
+rect 142 247 154 281
+rect 282 247 294 281
+rect 142 241 294 247
+rect 360 281 512 287
+rect 360 247 372 281
+rect 500 247 512 281
+rect 360 241 512 247
+rect 578 281 730 287
+rect 578 247 590 281
+rect 718 247 730 281
+rect 578 241 730 247
+rect -920 26 -874 38
+rect -786 171 -740 183
+rect -786 21 -780 171
+rect -746 21 -740 171
+rect -786 9 -740 21
+rect -350 171 -304 183
+rect -350 21 -344 171
+rect -310 21 -304 171
+rect -350 9 -304 21
+rect 86 171 132 183
+rect 86 21 92 171
+rect 126 21 132 171
+rect 86 9 132 21
+rect 522 171 568 183
+rect 522 21 528 171
+rect 562 21 568 171
+rect 522 9 568 21
+rect -568 -21 -522 -9
+rect -568 -171 -562 -21
+rect -528 -171 -522 -21
+rect -568 -183 -522 -171
+rect -132 -21 -86 -9
+rect -132 -171 -126 -21
+rect -92 -171 -86 -21
+rect -132 -183 -86 -171
+rect 304 -21 350 -9
+rect 304 -171 310 -21
+rect 344 -171 350 -21
+rect 304 -183 350 -171
+rect 740 -21 786 -9
+rect 740 -171 746 -21
+rect 780 -171 786 -21
+rect 740 -183 786 -171
+rect -730 -247 -578 -241
+rect -730 -281 -718 -247
+rect -590 -281 -578 -247
+rect -730 -287 -578 -281
+rect -512 -247 -360 -241
+rect -512 -281 -500 -247
+rect -372 -281 -360 -247
+rect -512 -287 -360 -281
+rect -294 -247 -142 -241
+rect -294 -281 -282 -247
+rect -154 -281 -142 -247
+rect -294 -287 -142 -281
+rect -76 -247 76 -241
+rect -76 -281 -64 -247
+rect 64 -281 76 -247
+rect -76 -287 76 -281
+rect 142 -247 294 -241
+rect 142 -281 154 -247
+rect 282 -281 294 -247
+rect 142 -287 294 -281
+rect 360 -247 512 -241
+rect 360 -281 372 -247
+rect 500 -281 512 -247
+rect 360 -287 512 -281
+rect 578 -247 730 -241
+rect 578 -281 590 -247
+rect 718 -281 730 -247
+rect 578 -287 730 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_g5v0d10v5
+string FIXED_BBOX -897 -402 897 402
+string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
new file mode 100644
index 0000000..eb421da
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< error_p >>
+rect -221 351 -220 397
+rect -193 379 -192 419
+<< nwell >>
+rect -338 -497 338 497
+<< mvpmos >>
+rect -80 -200 80 200
+<< mvpdiff >>
+rect -138 188 -80 200
+rect -138 -188 -126 188
+rect -92 -188 -80 188
+rect -138 -200 -80 -188
+rect 80 188 138 200
+rect 80 -188 92 188
+rect 126 -188 138 188
+rect 80 -200 138 -188
+<< mvpdiffc >>
+rect -126 -188 -92 188
+rect 92 -188 126 188
+<< mvnsubdiff >>
+rect -272 419 272 431
+rect -272 385 -164 419
+rect 164 385 272 419
+rect -272 373 272 385
+rect -272 323 -214 373
+rect -272 -323 -260 323
+rect -226 -323 -214 323
+rect 214 323 272 373
+rect -272 -373 -214 -323
+rect 214 -323 226 323
+rect 260 -323 272 323
+rect 214 -373 272 -323
+rect -272 -385 272 -373
+rect -272 -419 -164 -385
+rect 164 -419 272 -385
+rect -272 -431 272 -419
+<< mvnsubdiffcont >>
+rect -164 385 164 419
+rect -260 -323 -226 323
+rect 226 -323 260 323
+rect -164 -419 164 -385
+<< poly >>
+rect -80 281 80 297
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -80 200 80 247
+rect -80 -247 80 -200
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -80 -297 80 -281
+<< polycont >>
+rect -64 247 64 281
+rect -64 -281 64 -247
+<< locali >>
+rect -260 385 -181 419
+rect 181 385 260 419
+rect 226 323 260 385
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -126 188 -92 204
+rect -126 -204 -92 -188
+rect 92 188 126 204
+rect 92 -204 126 -188
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -260 -385 -226 -323
+rect 226 -385 260 -323
+rect -260 -419 -164 -385
+rect 164 -419 260 -385
+<< viali >>
+rect -181 385 -164 419
+rect -164 385 164 419
+rect 164 385 181 419
+rect -260 323 -226 385
+rect -260 0 -226 323
+rect -64 247 64 281
+rect -126 -188 -92 188
+rect 92 -188 126 188
+rect -64 -281 64 -247
+<< metal1 >>
+rect -193 419 193 425
+rect -266 385 -220 397
+rect -266 0 -260 385
+rect -226 0 -220 385
+rect -193 385 -181 419
+rect 181 385 193 419
+rect -193 379 193 385
+rect -76 281 76 287
+rect -76 247 -64 281
+rect 64 247 76 281
+rect -76 241 76 247
+rect -266 -12 -220 0
+rect -132 188 -86 200
+rect -132 -188 -126 188
+rect -92 -188 -86 188
+rect -132 -200 -86 -188
+rect 86 188 132 200
+rect 86 -188 92 188
+rect 126 -188 132 188
+rect 86 -200 132 -188
+rect -76 -247 76 -241
+rect -76 -281 -64 -247
+rect 64 -281 76 -247
+rect -76 -287 76 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_g5v0d10v5
+string FIXED_BBOX -243 -402 243 402
+string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
new file mode 100644
index 0000000..19fe898
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< error_p >>
+rect -221 351 -220 397
+rect -193 379 -192 419
+<< nwell >>
+rect -338 -497 338 497
+<< mvpmos >>
+rect -80 -200 80 200
+<< mvpdiff >>
+rect -138 188 -80 200
+rect -138 -188 -126 188
+rect -92 -188 -80 188
+rect -138 -200 -80 -188
+rect 80 188 138 200
+rect 80 -188 92 188
+rect 126 -188 138 188
+rect 80 -200 138 -188
+<< mvpdiffc >>
+rect -126 -188 -92 188
+rect 92 -188 126 188
+<< mvnsubdiff >>
+rect -272 419 272 431
+rect -272 385 -164 419
+rect 164 385 272 419
+rect -272 373 272 385
+rect -272 323 -214 373
+rect -272 -323 -260 323
+rect -226 -323 -214 323
+rect 214 323 272 373
+rect -272 -373 -214 -323
+rect 214 -323 226 323
+rect 260 -323 272 323
+rect 214 -373 272 -323
+rect -272 -385 272 -373
+rect -272 -419 -164 -385
+rect 164 -419 272 -385
+rect -272 -431 272 -419
+<< mvnsubdiffcont >>
+rect -164 385 164 419
+rect -260 -323 -226 323
+rect 226 -323 260 323
+rect -164 -419 164 -385
+<< poly >>
+rect -80 281 80 297
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -80 200 80 247
+rect -80 -247 80 -200
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -80 -297 80 -281
+<< polycont >>
+rect -64 247 64 281
+rect -64 -281 64 -247
+<< locali >>
+rect -260 385 -181 419
+rect 181 385 260 419
+rect 226 323 260 385
+rect -80 247 -64 281
+rect 64 247 80 281
+rect -126 188 -92 204
+rect -126 -204 -92 -188
+rect 92 188 126 204
+rect 92 -204 126 -188
+rect -80 -281 -64 -247
+rect 64 -281 80 -247
+rect -260 -385 -226 -323
+rect 226 -385 260 -323
+rect -260 -419 -164 -385
+rect 164 -419 260 -385
+<< viali >>
+rect -181 385 -164 419
+rect -164 385 164 419
+rect 164 385 181 419
+rect -260 323 -226 385
+rect -260 38 -226 323
+rect -64 247 64 281
+rect -126 -188 -92 188
+rect 92 -188 126 188
+rect -64 -281 64 -247
+<< metal1 >>
+rect -193 419 193 425
+rect -266 385 -220 397
+rect -266 38 -260 385
+rect -226 38 -220 385
+rect -193 385 -181 419
+rect 181 385 193 419
+rect -193 379 193 385
+rect -76 281 76 287
+rect -76 247 -64 281
+rect 64 247 76 281
+rect -76 241 76 247
+rect -266 26 -220 38
+rect -132 188 -86 200
+rect -132 -188 -126 188
+rect -92 -188 -86 188
+rect -132 -200 -86 -188
+rect 86 188 132 200
+rect 86 -188 92 188
+rect 126 -188 132 188
+rect 86 -200 132 -188
+rect -76 -247 76 -241
+rect -76 -281 -64 -247
+rect 64 -281 76 -247
+rect -76 -287 76 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_g5v0d10v5
+string FIXED_BBOX -243 -402 243 402
+string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
new file mode 100644
index 0000000..b8eb64f
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
@@ -0,0 +1,368 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606063140
+<< nwell >>
+rect -1101 -497 1101 497
+<< mvpmos >>
+rect -843 -200 -683 200
+rect -625 -200 -465 200
+rect -407 -200 -247 200
+rect -189 -200 -29 200
+rect 29 -200 189 200
+rect 247 -200 407 200
+rect 465 -200 625 200
+rect 683 -200 843 200
+<< mvpdiff >>
+rect -901 188 -843 200
+rect -901 -188 -889 188
+rect -855 -188 -843 188
+rect -901 -200 -843 -188
+rect -683 188 -625 200
+rect -683 -188 -671 188
+rect -637 -188 -625 188
+rect -683 -200 -625 -188
+rect -465 188 -407 200
+rect -465 -188 -453 188
+rect -419 -188 -407 188
+rect -465 -200 -407 -188
+rect -247 188 -189 200
+rect -247 -188 -235 188
+rect -201 -188 -189 188
+rect -247 -200 -189 -188
+rect -29 188 29 200
+rect -29 -188 -17 188
+rect 17 -188 29 188
+rect -29 -200 29 -188
+rect 189 188 247 200
+rect 189 -188 201 188
+rect 235 -188 247 188
+rect 189 -200 247 -188
+rect 407 188 465 200
+rect 407 -188 419 188
+rect 453 -188 465 188
+rect 407 -200 465 -188
+rect 625 188 683 200
+rect 625 -188 637 188
+rect 671 -188 683 188
+rect 625 -200 683 -188
+rect 843 188 901 200
+rect 843 -188 855 188
+rect 889 -188 901 188
+rect 843 -200 901 -188
+<< mvpdiffc >>
+rect -889 -188 -855 188
+rect -671 -188 -637 188
+rect -453 -188 -419 188
+rect -235 -188 -201 188
+rect -17 -188 17 188
+rect 201 -188 235 188
+rect 419 -188 453 188
+rect 637 -188 671 188
+rect 855 -188 889 188
+<< mvnsubdiff >>
+rect -1035 419 1035 431
+rect -1035 385 -927 419
+rect 927 385 1035 419
+rect -1035 373 1035 385
+rect -1035 323 -977 373
+rect -1035 -323 -1023 323
+rect -989 -323 -977 323
+rect 977 323 1035 373
+rect -1035 -373 -977 -323
+rect 977 -323 989 323
+rect 1023 -323 1035 323
+rect 977 -373 1035 -323
+rect -1035 -385 1035 -373
+rect -1035 -419 -927 -385
+rect 927 -419 1035 -385
+rect -1035 -431 1035 -419
+<< mvnsubdiffcont >>
+rect -927 385 927 419
+rect -1023 -323 -989 323
+rect 989 -323 1023 323
+rect -927 -419 927 -385
+<< poly >>
+rect -843 281 -683 297
+rect -843 247 -827 281
+rect -699 247 -683 281
+rect -843 200 -683 247
+rect -625 281 -465 297
+rect -625 247 -609 281
+rect -481 247 -465 281
+rect -625 200 -465 247
+rect -407 281 -247 297
+rect -407 247 -391 281
+rect -263 247 -247 281
+rect -407 200 -247 247
+rect -189 281 -29 297
+rect -189 247 -173 281
+rect -45 247 -29 281
+rect -189 200 -29 247
+rect 29 281 189 297
+rect 29 247 45 281
+rect 173 247 189 281
+rect 29 200 189 247
+rect 247 281 407 297
+rect 247 247 263 281
+rect 391 247 407 281
+rect 247 200 407 247
+rect 465 281 625 297
+rect 465 247 481 281
+rect 609 247 625 281
+rect 465 200 625 247
+rect 683 281 843 297
+rect 683 247 699 281
+rect 827 247 843 281
+rect 683 200 843 247
+rect -843 -247 -683 -200
+rect -843 -281 -827 -247
+rect -699 -281 -683 -247
+rect -843 -297 -683 -281
+rect -625 -247 -465 -200
+rect -625 -281 -609 -247
+rect -481 -281 -465 -247
+rect -625 -297 -465 -281
+rect -407 -247 -247 -200
+rect -407 -281 -391 -247
+rect -263 -281 -247 -247
+rect -407 -297 -247 -281
+rect -189 -247 -29 -200
+rect -189 -281 -173 -247
+rect -45 -281 -29 -247
+rect -189 -297 -29 -281
+rect 29 -247 189 -200
+rect 29 -281 45 -247
+rect 173 -281 189 -247
+rect 29 -297 189 -281
+rect 247 -247 407 -200
+rect 247 -281 263 -247
+rect 391 -281 407 -247
+rect 247 -297 407 -281
+rect 465 -247 625 -200
+rect 465 -281 481 -247
+rect 609 -281 625 -247
+rect 465 -297 625 -281
+rect 683 -247 843 -200
+rect 683 -281 699 -247
+rect 827 -281 843 -247
+rect 683 -297 843 -281
+<< polycont >>
+rect -827 247 -699 281
+rect -609 247 -481 281
+rect -391 247 -263 281
+rect -173 247 -45 281
+rect 45 247 173 281
+rect 263 247 391 281
+rect 481 247 609 281
+rect 699 247 827 281
+rect -827 -281 -699 -247
+rect -609 -281 -481 -247
+rect -391 -281 -263 -247
+rect -173 -281 -45 -247
+rect 45 -281 173 -247
+rect 263 -281 391 -247
+rect 481 -281 609 -247
+rect 699 -281 827 -247
+<< locali >>
+rect -1023 385 -927 419
+rect 927 385 1023 419
+rect 989 323 1023 385
+rect -843 247 -827 281
+rect -699 247 -683 281
+rect -625 247 -609 281
+rect -481 247 -465 281
+rect -407 247 -391 281
+rect -263 247 -247 281
+rect -189 247 -173 281
+rect -45 247 -29 281
+rect 29 247 45 281
+rect 173 247 189 281
+rect 247 247 263 281
+rect 391 247 407 281
+rect 465 247 481 281
+rect 609 247 625 281
+rect 683 247 699 281
+rect 827 247 843 281
+rect -889 188 -855 204
+rect -889 -204 -855 -188
+rect -671 188 -637 204
+rect -671 -204 -637 -188
+rect -453 188 -419 204
+rect -453 -204 -419 -188
+rect -235 188 -201 204
+rect -235 -204 -201 -188
+rect -17 188 17 204
+rect -17 -204 17 -188
+rect 201 188 235 204
+rect 201 -204 235 -188
+rect 419 188 453 204
+rect 419 -204 453 -188
+rect 637 188 671 204
+rect 637 -204 671 -188
+rect 855 188 889 204
+rect 855 -204 889 -188
+rect -843 -281 -827 -247
+rect -699 -281 -683 -247
+rect -625 -281 -609 -247
+rect -481 -281 -465 -247
+rect -407 -281 -391 -247
+rect -263 -281 -247 -247
+rect -189 -281 -173 -247
+rect -45 -281 -29 -247
+rect 29 -281 45 -247
+rect 173 -281 189 -247
+rect 247 -281 263 -247
+rect 391 -281 407 -247
+rect 465 -281 481 -247
+rect 609 -281 625 -247
+rect 683 -281 699 -247
+rect 827 -281 843 -247
+rect -1023 -385 -989 -323
+rect 989 -385 1023 -323
+rect -1023 -419 -927 -385
+rect 927 -419 1023 -385
+<< viali >>
+rect -890 385 890 419
+rect -1023 323 -989 385
+rect -1023 0 -989 323
+rect -827 247 -699 281
+rect -609 247 -481 281
+rect -391 247 -263 281
+rect -173 247 -45 281
+rect 45 247 173 281
+rect 263 247 391 281
+rect 481 247 609 281
+rect 699 247 827 281
+rect -889 21 -855 171
+rect -671 -171 -637 -21
+rect -453 21 -419 171
+rect -235 -171 -201 -21
+rect -17 21 17 171
+rect 201 -171 235 -21
+rect 419 21 453 171
+rect 637 -171 671 -21
+rect 855 21 889 171
+rect -827 -281 -699 -247
+rect -609 -281 -481 -247
+rect -391 -281 -263 -247
+rect -173 -281 -45 -247
+rect 45 -281 173 -247
+rect 263 -281 391 -247
+rect 481 -281 609 -247
+rect 699 -281 827 -247
+<< metal1 >>
+rect -902 419 902 425
+rect -1029 385 -983 397
+rect -1029 0 -1023 385
+rect -989 0 -983 385
+rect -902 385 -890 419
+rect 890 385 902 419
+rect -902 379 902 385
+rect -839 281 -687 287
+rect -839 247 -827 281
+rect -699 247 -687 281
+rect -839 241 -687 247
+rect -621 281 -469 287
+rect -621 247 -609 281
+rect -481 247 -469 281
+rect -621 241 -469 247
+rect -403 281 -251 287
+rect -403 247 -391 281
+rect -263 247 -251 281
+rect -403 241 -251 247
+rect -185 281 -33 287
+rect -185 247 -173 281
+rect -45 247 -33 281
+rect -185 241 -33 247
+rect 33 281 185 287
+rect 33 247 45 281
+rect 173 247 185 281
+rect 33 241 185 247
+rect 251 281 403 287
+rect 251 247 263 281
+rect 391 247 403 281
+rect 251 241 403 247
+rect 469 281 621 287
+rect 469 247 481 281
+rect 609 247 621 281
+rect 469 241 621 247
+rect 687 281 839 287
+rect 687 247 699 281
+rect 827 247 839 281
+rect 687 241 839 247
+rect -895 171 -849 183
+rect -895 21 -889 171
+rect -855 21 -849 171
+rect -895 9 -849 21
+rect -459 171 -413 183
+rect -459 21 -453 171
+rect -419 21 -413 171
+rect -459 9 -413 21
+rect -23 171 23 183
+rect -23 21 -17 171
+rect 17 21 23 171
+rect -23 9 23 21
+rect 413 171 459 183
+rect 413 21 419 171
+rect 453 21 459 171
+rect 413 9 459 21
+rect 849 171 895 183
+rect 849 21 855 171
+rect 889 21 895 171
+rect 849 9 895 21
+rect -1029 -12 -983 0
+rect -677 -21 -631 -9
+rect -677 -171 -671 -21
+rect -637 -171 -631 -21
+rect -677 -183 -631 -171
+rect -241 -21 -195 -9
+rect -241 -171 -235 -21
+rect -201 -171 -195 -21
+rect -241 -183 -195 -171
+rect 195 -21 241 -9
+rect 195 -171 201 -21
+rect 235 -171 241 -21
+rect 195 -183 241 -171
+rect 631 -21 677 -9
+rect 631 -171 637 -21
+rect 671 -171 677 -21
+rect 631 -183 677 -171
+rect -839 -247 -687 -241
+rect -839 -281 -827 -247
+rect -699 -281 -687 -247
+rect -839 -287 -687 -281
+rect -621 -247 -469 -241
+rect -621 -281 -609 -247
+rect -481 -281 -469 -247
+rect -621 -287 -469 -281
+rect -403 -247 -251 -241
+rect -403 -281 -391 -247
+rect -263 -281 -251 -247
+rect -403 -287 -251 -281
+rect -185 -247 -33 -241
+rect -185 -281 -173 -247
+rect -45 -281 -33 -247
+rect -185 -287 -33 -281
+rect 33 -247 185 -241
+rect 33 -281 45 -247
+rect 173 -281 185 -247
+rect 33 -287 185 -281
+rect 251 -247 403 -241
+rect 251 -281 263 -247
+rect 391 -281 403 -247
+rect 251 -287 403 -281
+rect 469 -247 621 -241
+rect 469 -281 481 -247
+rect 609 -281 621 -247
+rect 469 -287 621 -281
+rect 687 -247 839 -241
+rect 687 -281 699 -247
+rect 827 -281 839 -247
+rect 687 -287 839 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_g5v0d10v5
+string FIXED_BBOX -1006 -402 1006 402
+string parameters w 2.00 l 0.80 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
new file mode 100644
index 0000000..5bd3cec
--- /dev/null
+++ b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
@@ -0,0 +1,167 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606074388
+<< pwell >>
+rect -5446 -3098 5446 3098
+<< psubdiff >>
+rect -5410 3028 -5314 3062
+rect 5314 3028 5410 3062
+rect -5410 2966 -5376 3028
+rect 5376 2966 5410 3028
+rect -5410 -3028 -5376 -2966
+rect 5376 -3028 5410 -2966
+rect -5410 -3062 -5314 -3028
+rect 5314 -3062 5410 -3028
+<< psubdiffcont >>
+rect -5314 3028 5314 3062
+rect -5410 -2966 -5376 2966
+rect 5376 -2966 5410 2966
+rect -5314 -3062 5314 -3028
+<< xpolycontact >>
+rect -5280 2500 -5142 2932
+rect -5280 -2932 -5142 -2500
+rect -4894 2500 -4756 2932
+rect -4894 -2932 -4756 -2500
+rect -4508 2500 -4370 2932
+rect -4508 -2932 -4370 -2500
+rect -4122 2500 -3984 2932
+rect -4122 -2932 -3984 -2500
+rect -3736 2500 -3598 2932
+rect -3736 -2932 -3598 -2500
+rect -3350 2500 -3212 2932
+rect -3350 -2932 -3212 -2500
+rect -2964 2500 -2826 2932
+rect -2964 -2932 -2826 -2500
+rect -2578 2500 -2440 2932
+rect -2578 -2932 -2440 -2500
+rect -2192 2500 -2054 2932
+rect -2192 -2932 -2054 -2500
+rect -1806 2500 -1668 2932
+rect -1806 -2932 -1668 -2500
+rect -1420 2500 -1282 2932
+rect -1420 -2932 -1282 -2500
+rect -1034 2500 -896 2932
+rect -1034 -2932 -896 -2500
+rect -648 2500 -510 2932
+rect -648 -2932 -510 -2500
+rect -262 2500 -124 2932
+rect -262 -2932 -124 -2500
+rect 124 2500 262 2932
+rect 124 -2932 262 -2500
+rect 510 2500 648 2932
+rect 510 -2932 648 -2500
+rect 896 2500 1034 2932
+rect 896 -2932 1034 -2500
+rect 1282 2500 1420 2932
+rect 1282 -2932 1420 -2500
+rect 1668 2500 1806 2932
+rect 1668 -2932 1806 -2500
+rect 2054 2500 2192 2932
+rect 2054 -2932 2192 -2500
+rect 2440 2500 2578 2932
+rect 2440 -2932 2578 -2500
+rect 2826 2500 2964 2932
+rect 2826 -2932 2964 -2500
+rect 3212 2500 3350 2932
+rect 3212 -2932 3350 -2500
+rect 3598 2500 3736 2932
+rect 3598 -2932 3736 -2500
+rect 3984 2500 4122 2932
+rect 3984 -2932 4122 -2500
+rect 4370 2500 4508 2932
+rect 4370 -2932 4508 -2500
+rect 4756 2500 4894 2932
+rect 4756 -2932 4894 -2500
+rect 5142 2500 5280 2932
+rect 5142 -2932 5280 -2500
+<< xpolyres >>
+rect -5280 -2500 -5142 2500
+rect -4894 -2500 -4756 2500
+rect -4508 -2500 -4370 2500
+rect -4122 -2500 -3984 2500
+rect -3736 -2500 -3598 2500
+rect -3350 -2500 -3212 2500
+rect -2964 -2500 -2826 2500
+rect -2578 -2500 -2440 2500
+rect -2192 -2500 -2054 2500
+rect -1806 -2500 -1668 2500
+rect -1420 -2500 -1282 2500
+rect -1034 -2500 -896 2500
+rect -648 -2500 -510 2500
+rect -262 -2500 -124 2500
+rect 124 -2500 262 2500
+rect 510 -2500 648 2500
+rect 896 -2500 1034 2500
+rect 1282 -2500 1420 2500
+rect 1668 -2500 1806 2500
+rect 2054 -2500 2192 2500
+rect 2440 -2500 2578 2500
+rect 2826 -2500 2964 2500
+rect 3212 -2500 3350 2500
+rect 3598 -2500 3736 2500
+rect 3984 -2500 4122 2500
+rect 4370 -2500 4508 2500
+rect 4756 -2500 4894 2500
+rect 5142 -2500 5280 2500
+<< locali >>
+rect -5410 3028 -5314 3062
+rect 5314 3028 5410 3062
+rect -5410 2966 -5376 3028
+rect 5376 2966 5410 3028
+rect -5410 -3028 -5376 -2966
+rect 5376 -3028 5410 -2966
+rect -5410 -3062 -5314 -3028
+rect 5314 -3062 5410 -3028
+<< viali >>
+rect -5410 -2725 -5376 2725
+rect 5376 -2725 5410 2725
+rect -4838 -3062 4838 -3028
+<< metal1 >>
+rect -5416 2725 -5370 2737
+rect -5416 -2725 -5410 2725
+rect -5376 -2725 -5370 2725
+rect -5416 -2737 -5370 -2725
+rect 5370 2725 5416 2737
+rect 5370 -2725 5376 2725
+rect 5410 -2725 5416 2725
+rect 5370 -2737 5416 -2725
+rect -4850 -3028 4850 -3022
+rect -4850 -3062 -4838 -3028
+rect 4838 -3062 4850 -3028
+rect -4850 -3068 4850 -3062
+<< res0p69 >>
+rect -5282 -2502 -5140 2502
+rect -4896 -2502 -4754 2502
+rect -4510 -2502 -4368 2502
+rect -4124 -2502 -3982 2502
+rect -3738 -2502 -3596 2502
+rect -3352 -2502 -3210 2502
+rect -2966 -2502 -2824 2502
+rect -2580 -2502 -2438 2502
+rect -2194 -2502 -2052 2502
+rect -1808 -2502 -1666 2502
+rect -1422 -2502 -1280 2502
+rect -1036 -2502 -894 2502
+rect -650 -2502 -508 2502
+rect -264 -2502 -122 2502
+rect 122 -2502 264 2502
+rect 508 -2502 650 2502
+rect 894 -2502 1036 2502
+rect 1280 -2502 1422 2502
+rect 1666 -2502 1808 2502
+rect 2052 -2502 2194 2502
+rect 2438 -2502 2580 2502
+rect 2824 -2502 2966 2502
+rect 3210 -2502 3352 2502
+rect 3596 -2502 3738 2502
+rect 3982 -2502 4124 2502
+rect 4368 -2502 4510 2502
+rect 4754 -2502 4896 2502
+rect 5140 -2502 5282 2502
+<< properties >>
+string gencell sky130_fd_pr__res_xhigh_po_0p69
+string FIXED_BBOX -5393 -3045 5393 3045
+string parameters w 0.69 l 25.0 m 1 nx 28 wmin 0.690 lmin 0.50 rho 2000 val 72.811k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.690 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 0 viagb 90 viagt 0 viagl 90 viagr 90
+string library sky130
+<< end >>
diff --git a/mag/user_analog_proj_example.mag b/mag/user_analog_proj_example.mag
new file mode 100644
index 0000000..7d27792
--- /dev/null
+++ b/mag/user_analog_proj_example.mag
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1639841760
+<< error_p >>
+rect 5036 7870 5051 7898
+rect 5008 7676 5023 7870
+rect 20366 7862 20381 7890
+rect 20394 7668 20409 7862
+use example_por example_por_1
+timestamp 1639841760
+transform 1 0 14132 0 1 -22
+box 0 0 11344 8338
+use example_por example_por_0
+timestamp 1639841760
+transform -1 0 11285 0 1 -14
+box 0 0 11344 8338
+<< end >>
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
new file mode 100644
index 0000000..23a3913
--- /dev/null
+++ b/mag/user_analog_project_wrapper.ext
@@ -0,0 +1,1709 @@
+timestamp 1640403132
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 1e+06
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use layout_opamp_2 layout_opamp_2_0 1 0 63269 0 1 340125
+use layout_opamp layout_opamp_0 1 0 223495 0 1 340940
+use layout_opamp_3 layout_opamp_3_0 1 0 67079 0 1 203141
+port "io_analog[4]" 41 164647 351150 167147 352400 m5
+port "io_analog[4]" 47 159497 351150 161997 352400 m5
+port "io_analog[5]" 42 113797 351150 116297 352400 m5
+port "io_analog[5]" 48 108647 351150 111147 352400 m5
+port "io_analog[6]" 43 87947 351150 90447 352400 m5
+port "io_analog[6]" 49 82797 351150 85297 352400 m5
+port "io_analog[4]" 41 164647 351150 167147 352400 m4
+port "io_analog[4]" 47 159497 351150 161997 352400 m4
+port "io_analog[5]" 42 113797 351150 116297 352400 m4
+port "io_analog[5]" 48 108647 351150 111147 352400 m4
+port "io_analog[6]" 43 87947 351150 90447 352400 m4
+port "io_analog[6]" 49 82797 351150 85297 352400 m4
+port "io_in_3v3[0]" 83 291760 772 292400 828 m3
+port "io_oeb[26]" 128 -400 772 240 828 m3
+port "io_in[0]" 56 291760 1363 292400 1419 m3
+port "io_out[26]" 155 -400 1363 240 1419 m3
+port "io_out[0]" 137 291760 1954 292400 2010 m3
+port "io_in[26]" 74 -400 1954 240 2010 m3
+port "io_oeb[0]" 110 291760 2545 292400 2601 m3
+port "io_in_3v3[26]" 101 -400 2545 240 2601 m3
+port "io_in_3v3[1]" 94 291760 3136 292400 3192 m3
+port "io_oeb[25]" 127 -400 3136 240 3192 m3
+port "io_in[1]" 67 291760 3727 292400 3783 m3
+port "io_out[25]" 154 -400 3727 240 3783 m3
+port "io_out[1]" 148 291760 4318 292400 4374 m3
+port "io_in[25]" 73 -400 4318 240 4374 m3
+port "io_oeb[1]" 121 291760 4909 292400 4965 m3
+port "io_in_3v3[25]" 100 -400 4909 240 4965 m3
+port "io_in_3v3[2]" 102 291760 5500 292400 5556 m3
+port "io_oeb[24]" 126 -400 5500 240 5556 m3
+port "io_in[2]" 75 291760 6091 292400 6147 m3
+port "io_out[24]" 153 -400 6091 240 6147 m3
+port "io_out[2]" 156 291760 6682 292400 6738 m3
+port "io_in[24]" 72 -400 6682 240 6738 m3
+port "io_oeb[2]" 129 291760 7273 292400 7329 m3
+port "io_in_3v3[24]" 99 -400 7273 240 7329 m3
+port "io_in_3v3[3]" 103 291760 7864 292400 7920 m3
+port "gpio_noesd[17]" 26 -400 7864 240 7920 m3
+port "io_in[3]" 76 291760 8455 292400 8511 m3
+port "gpio_analog[17]" 8 -400 8455 240 8511 m3
+port "io_out[3]" 157 291760 9046 292400 9102 m3
+port "io_oeb[3]" 130 291760 9637 292400 9693 m3
+port "io_in_3v3[4]" 104 291760 10228 292400 10284 m3
+port "io_in[4]" 77 291760 10819 292400 10875 m3
+port "io_out[4]" 158 291760 11410 292400 11466 m3
+port "io_oeb[4]" 131 291760 12001 292400 12057 m3
+port "io_oeb[23]" 125 -400 16211 240 16267 m3
+port "io_out[23]" 152 -400 16802 240 16858 m3
+port "io_in[23]" 71 -400 17393 240 17449 m3
+port "io_in_3v3[23]" 98 -400 17984 240 18040 m3
+port "gpio_noesd[16]" 25 -400 18575 240 18631 m3
+port "gpio_analog[16]" 7 -400 19166 240 19222 m3
+port "io_in_3v3[5]" 105 291760 23457 292400 23513 m3
+port "io_in[5]" 78 291760 24048 292400 24104 m3
+port "io_out[5]" 159 291760 24639 292400 24695 m3
+port "io_oeb[5]" 132 291760 25230 292400 25286 m3
+port "io_oeb[22]" 124 -400 37822 240 37878 m3
+port "io_out[22]" 151 -400 38413 240 38469 m3
+port "io_in[22]" 70 -400 39004 240 39060 m3
+port "io_in_3v3[22]" 97 -400 39595 240 39651 m3
+port "gpio_noesd[15]" 24 -400 40186 240 40242 m3
+port "gpio_analog[15]" 6 -400 40777 240 40833 m3
+port "io_in_3v3[6]" 106 291760 45786 292400 45842 m3
+port "io_in[6]" 79 291760 46377 292400 46433 m3
+port "io_out[6]" 160 291760 46968 292400 47024 m3
+port "io_oeb[6]" 133 291760 47559 292400 47615 m3
+port "io_oeb[21]" 123 -400 59433 240 59489 m3
+port "io_out[21]" 150 -400 60024 240 60080 m3
+port "io_in[21]" 69 -400 60615 240 60671 m3
+port "io_in_3v3[21]" 96 -400 61206 240 61262 m3
+port "gpio_noesd[14]" 23 -400 61797 240 61853 m3
+port "gpio_analog[14]" 5 -400 62388 240 62444 m3
+port "vssa1" 565 291170 68415 292400 70815 m3
+port "vssa1" 564 291170 73415 292400 75815 m3
+port "vssd2" 571 0 81444 830 83844 m3
+port "vssd2" 570 0 86444 830 88844 m3
+port "vssd1" 569 291170 90715 292400 93115 m3
+port "vssd1" 568 291170 95715 292400 98115 m3
+port "vdda2" 560 0 102444 830 104844 m3
+port "vdda2" 561 0 107444 830 109844 m3
+port "vdda1" 559 291170 112615 292400 115015 m3
+port "vdda1" 558 291170 117615 292400 120015 m3
+port "io_oeb[20]" 122 -400 123244 240 123300 m3
+port "io_out[20]" 149 -400 123835 240 123891 m3
+port "io_in[20]" 68 -400 124426 240 124482 m3
+port "io_in_3v3[20]" 95 -400 125017 240 125073 m3
+port "gpio_noesd[13]" 22 -400 125608 240 125664 m3
+port "gpio_analog[13]" 4 -400 126199 240 126255 m3
+port "gpio_analog[0]" 0 291760 134615 292400 134671 m3
+port "gpio_noesd[0]" 18 291760 135206 292400 135262 m3
+port "io_in_3v3[7]" 107 291760 135797 292400 135853 m3
+port "io_in[7]" 80 291760 136388 292400 136444 m3
+port "io_out[7]" 161 291760 136979 292400 137035 m3
+port "io_oeb[7]" 134 291760 137570 292400 137626 m3
+port "io_oeb[19]" 120 -400 144755 240 144811 m3
+port "io_out[19]" 147 -400 145346 240 145402 m3
+port "io_in[19]" 66 -400 145937 240 145993 m3
+port "io_in_3v3[19]" 93 -400 146528 240 146584 m3
+port "gpio_noesd[12]" 21 -400 147119 240 147175 m3
+port "gpio_analog[12]" 3 -400 147710 240 147766 m3
+port "gpio_analog[1]" 9 291760 156826 292400 156882 m3
+port "gpio_noesd[1]" 27 291760 157417 292400 157473 m3
+port "io_in_3v3[8]" 108 291760 158008 292400 158064 m3
+port "io_in[8]" 81 291760 158599 292400 158655 m3
+port "io_out[8]" 162 291760 159190 292400 159246 m3
+port "io_oeb[8]" 135 291760 159781 292400 159837 m3
+port "io_oeb[18]" 119 -400 166366 240 166422 m3
+port "io_out[18]" 146 -400 166957 240 167013 m3
+port "io_in[18]" 65 -400 167548 240 167604 m3
+port "io_in_3v3[18]" 92 -400 168139 240 168195 m3
+port "gpio_noesd[11]" 20 -400 168730 240 168786 m3
+port "gpio_analog[11]" 2 -400 169321 240 169377 m3
+port "gpio_analog[2]" 10 291760 179437 292400 179493 m3
+port "gpio_noesd[2]" 28 291760 180028 292400 180084 m3
+port "io_in_3v3[9]" 109 291760 180619 292400 180675 m3
+port "io_in[9]" 82 291760 181210 292400 181266 m3
+port "io_out[9]" 163 291760 181801 292400 181857 m3
+port "io_oeb[9]" 136 291760 182392 292400 182448 m3
+port "io_oeb[17]" 118 -400 187977 240 188033 m3
+port "io_out[17]" 145 -400 188568 240 188624 m3
+port "io_in[17]" 64 -400 189159 240 189215 m3
+port "io_in_3v3[17]" 91 -400 189750 240 189806 m3
+port "gpio_noesd[10]" 19 -400 190341 240 190397 m3
+port "gpio_analog[10]" 1 -400 190932 240 190988 m3
+port "gpio_analog[3]" 11 291760 202648 292400 202704 m3
+port "gpio_noesd[3]" 29 291760 203239 292400 203295 m3
+port "io_in_3v3[10]" 84 291760 203830 292400 203886 m3
+port "io_in[10]" 57 291760 204421 292400 204477 m3
+port "io_out[10]" 138 291760 205012 292400 205068 m3
+port "io_oeb[10]" 111 291760 205603 292400 205659 m3
+port "io_oeb[16]" 117 -400 209588 240 209644 m3
+port "io_out[16]" 144 -400 210179 240 210235 m3
+port "io_in[16]" 63 -400 210770 240 210826 m3
+port "io_in_3v3[16]" 90 -400 211361 240 211417 m3
+port "gpio_noesd[9]" 35 -400 211952 240 212008 m3
+port "gpio_analog[9]" 17 -400 212543 240 212599 m3
+port "gpio_analog[4]" 12 291760 224859 292400 224915 m3
+port "gpio_noesd[4]" 30 291760 225450 292400 225506 m3
+port "io_in_3v3[11]" 85 291760 226041 292400 226097 m3
+port "io_in[11]" 58 291760 226632 292400 226688 m3
+port "io_out[11]" 139 291760 227223 292400 227279 m3
+port "io_oeb[11]" 112 291760 227814 292400 227870 m3
+port "io_oeb[15]" 116 -400 231199 240 231255 m3
+port "io_out[15]" 143 -400 231790 240 231846 m3
+port "io_in[15]" 62 -400 232381 240 232437 m3
+port "io_in_3v3[15]" 89 -400 232972 240 233028 m3
+port "gpio_noesd[8]" 34 -400 233563 240 233619 m3
+port "gpio_analog[8]" 16 -400 234154 240 234210 m3
+port "gpio_analog[5]" 13 291760 247070 292400 247126 m3
+port "gpio_noesd[5]" 31 291760 247661 292400 247717 m3
+port "io_in_3v3[12]" 86 291760 248252 292400 248308 m3
+port "io_in[12]" 59 291760 248843 292400 248899 m3
+port "io_out[12]" 140 291760 249434 292400 249490 m3
+port "io_oeb[12]" 113 291760 250025 292400 250081 m3
+port "io_oeb[14]" 115 -400 252810 240 252866 m3
+port "io_out[14]" 142 -400 253401 240 253457 m3
+port "io_in[14]" 61 -400 253992 240 254048 m3
+port "io_in_3v3[14]" 88 -400 254583 240 254639 m3
+port "gpio_noesd[7]" 33 -400 255174 240 255230 m3
+port "gpio_analog[7]" 15 -400 255765 240 255821 m3
+port "vdda1" 556 291170 270281 292400 272681 m3
+port "vdda1" 557 291170 275281 292400 277681 m3
+port "vssa2" 567 0 274721 830 277121 m3
+port "vssa2" 566 0 279721 830 282121 m3
+port "gpio_analog[6]" 14 291760 291781 292400 291837 m3
+port "gpio_noesd[6]" 32 291760 292372 292400 292428 m3
+port "io_in_3v3[13]" 87 291760 292963 292400 293019 m3
+port "io_in[13]" 60 291760 293554 292400 293610 m3
+port "io_out[13]" 141 291760 294145 292400 294201 m3
+port "io_oeb[13]" 114 291760 294736 292400 294792 m3
+port "vccd1" 553 291170 314892 292400 317292 m3
+port "vccd2" 555 0 316921 830 319321 m3
+port "vccd1" 552 291170 319892 292400 322292 m3
+port "vccd2" 554 0 321921 830 324321 m3
+port "io_analog[0]" 36 291150 338992 292400 341492 m3
+port "io_analog[10]" 37 0 340121 850 342621 m3
+port "io_analog[1]" 38 283297 351150 285797 352400 m3
+port "vssa1" 562 260297 351170 262697 352400 m3
+port "vssa1" 563 255297 351170 257697 352400 m3
+port "io_analog[2]" 39 232697 351150 235197 352400 m3
+port "io_analog[3]" 40 206697 351150 209197 352400 m3
+port "io_analog[4]" 41 164647 351150 167147 352400 m3
+port "io_clamp_high[0]" 50 163397 351150 164497 352400 m3
+port "io_clamp_low[0]" 53 162147 351150 163247 352400 m3
+port "io_analog[4]" 47 159497 351150 161997 352400 m3
+port "io_analog[5]" 42 113797 351150 116297 352400 m3
+port "io_clamp_high[1]" 51 112547 351150 113647 352400 m3
+port "io_clamp_low[1]" 54 111297 351150 112397 352400 m3
+port "io_analog[5]" 48 108647 351150 111147 352400 m3
+port "io_analog[6]" 43 87947 351150 90447 352400 m3
+port "io_clamp_high[2]" 52 86697 351150 87797 352400 m3
+port "io_clamp_low[2]" 55 85447 351150 86547 352400 m3
+port "io_analog[6]" 49 82797 351150 85297 352400 m3
+port "io_analog[7]" 44 60097 351150 62597 352400 m3
+port "io_analog[8]" 45 34097 351150 36597 352400 m3
+port "io_analog[9]" 46 8097 351150 10597 352400 m3
+port "user_irq[2]" 551 291625 -400 291681 240 m2
+port "user_irq[1]" 550 291034 -400 291090 240 m2
+port "user_irq[0]" 549 290443 -400 290499 240 m2
+port "user_clock2" 548 289852 -400 289908 240 m2
+port "la_oenb[127]" 450 289261 -400 289317 240 m2
+port "la_data_out[127]" 322 288670 -400 288726 240 m2
+port "la_data_in[127]" 194 288079 -400 288135 240 m2
+port "la_oenb[126]" 449 287488 -400 287544 240 m2
+port "la_data_out[126]" 321 286897 -400 286953 240 m2
+port "la_data_in[126]" 193 286306 -400 286362 240 m2
+port "la_oenb[125]" 448 285715 -400 285771 240 m2
+port "la_data_out[125]" 320 285124 -400 285180 240 m2
+port "la_data_in[125]" 192 284533 -400 284589 240 m2
+port "la_oenb[124]" 447 283942 -400 283998 240 m2
+port "la_data_out[124]" 319 283351 -400 283407 240 m2
+port "la_data_in[124]" 191 282760 -400 282816 240 m2
+port "la_oenb[123]" 446 282169 -400 282225 240 m2
+port "la_data_out[123]" 318 281578 -400 281634 240 m2
+port "la_data_in[123]" 190 280987 -400 281043 240 m2
+port "la_oenb[122]" 445 280396 -400 280452 240 m2
+port "la_data_out[122]" 317 279805 -400 279861 240 m2
+port "la_data_in[122]" 189 279214 -400 279270 240 m2
+port "la_oenb[121]" 444 278623 -400 278679 240 m2
+port "la_data_out[121]" 316 278032 -400 278088 240 m2
+port "la_data_in[121]" 188 277441 -400 277497 240 m2
+port "la_oenb[120]" 443 276850 -400 276906 240 m2
+port "la_data_out[120]" 315 276259 -400 276315 240 m2
+port "la_data_in[120]" 187 275668 -400 275724 240 m2
+port "la_oenb[119]" 441 275077 -400 275133 240 m2
+port "la_data_out[119]" 313 274486 -400 274542 240 m2
+port "la_data_in[119]" 185 273895 -400 273951 240 m2
+port "la_oenb[118]" 440 273304 -400 273360 240 m2
+port "la_data_out[118]" 312 272713 -400 272769 240 m2
+port "la_data_in[118]" 184 272122 -400 272178 240 m2
+port "la_oenb[117]" 439 271531 -400 271587 240 m2
+port "la_data_out[117]" 311 270940 -400 270996 240 m2
+port "la_data_in[117]" 183 270349 -400 270405 240 m2
+port "la_oenb[116]" 438 269758 -400 269814 240 m2
+port "la_data_out[116]" 310 269167 -400 269223 240 m2
+port "la_data_in[116]" 182 268576 -400 268632 240 m2
+port "la_oenb[115]" 437 267985 -400 268041 240 m2
+port "la_data_out[115]" 309 267394 -400 267450 240 m2
+port "la_data_in[115]" 181 266803 -400 266859 240 m2
+port "la_oenb[114]" 436 266212 -400 266268 240 m2
+port "la_data_out[114]" 308 265621 -400 265677 240 m2
+port "la_data_in[114]" 180 265030 -400 265086 240 m2
+port "la_oenb[113]" 435 264439 -400 264495 240 m2
+port "la_data_out[113]" 307 263848 -400 263904 240 m2
+port "la_data_in[113]" 179 263257 -400 263313 240 m2
+port "la_oenb[112]" 434 262666 -400 262722 240 m2
+port "la_data_out[112]" 306 262075 -400 262131 240 m2
+port "la_data_in[112]" 178 261484 -400 261540 240 m2
+port "la_oenb[111]" 433 260893 -400 260949 240 m2
+port "la_data_out[111]" 305 260302 -400 260358 240 m2
+port "la_data_in[111]" 177 259711 -400 259767 240 m2
+port "la_oenb[110]" 432 259120 -400 259176 240 m2
+port "la_data_out[110]" 304 258529 -400 258585 240 m2
+port "la_data_in[110]" 176 257938 -400 257994 240 m2
+port "la_oenb[109]" 430 257347 -400 257403 240 m2
+port "la_data_out[109]" 302 256756 -400 256812 240 m2
+port "la_data_in[109]" 174 256165 -400 256221 240 m2
+port "la_oenb[108]" 429 255574 -400 255630 240 m2
+port "la_data_out[108]" 301 254983 -400 255039 240 m2
+port "la_data_in[108]" 173 254392 -400 254448 240 m2
+port "la_oenb[107]" 428 253801 -400 253857 240 m2
+port "la_data_out[107]" 300 253210 -400 253266 240 m2
+port "la_data_in[107]" 172 252619 -400 252675 240 m2
+port "la_oenb[106]" 427 252028 -400 252084 240 m2
+port "la_data_out[106]" 299 251437 -400 251493 240 m2
+port "la_data_in[106]" 171 250846 -400 250902 240 m2
+port "la_oenb[105]" 426 250255 -400 250311 240 m2
+port "la_data_out[105]" 298 249664 -400 249720 240 m2
+port "la_data_in[105]" 170 249073 -400 249129 240 m2
+port "la_oenb[104]" 425 248482 -400 248538 240 m2
+port "la_data_out[104]" 297 247891 -400 247947 240 m2
+port "la_data_in[104]" 169 247300 -400 247356 240 m2
+port "la_oenb[103]" 424 246709 -400 246765 240 m2
+port "la_data_out[103]" 296 246118 -400 246174 240 m2
+port "la_data_in[103]" 168 245527 -400 245583 240 m2
+port "la_oenb[102]" 423 244936 -400 244992 240 m2
+port "la_data_out[102]" 295 244345 -400 244401 240 m2
+port "la_data_in[102]" 167 243754 -400 243810 240 m2
+port "la_oenb[101]" 422 243163 -400 243219 240 m2
+port "la_data_out[101]" 294 242572 -400 242628 240 m2
+port "la_data_in[101]" 166 241981 -400 242037 240 m2
+port "la_oenb[100]" 421 241390 -400 241446 240 m2
+port "la_data_out[100]" 293 240799 -400 240855 240 m2
+port "la_data_in[100]" 165 240208 -400 240264 240 m2
+port "la_oenb[99]" 546 239617 -400 239673 240 m2
+port "la_data_out[99]" 418 239026 -400 239082 240 m2
+port "la_data_in[99]" 290 238435 -400 238491 240 m2
+port "la_oenb[98]" 545 237844 -400 237900 240 m2
+port "la_data_out[98]" 417 237253 -400 237309 240 m2
+port "la_data_in[98]" 289 236662 -400 236718 240 m2
+port "la_oenb[97]" 544 236071 -400 236127 240 m2
+port "la_data_out[97]" 416 235480 -400 235536 240 m2
+port "la_data_in[97]" 288 234889 -400 234945 240 m2
+port "la_oenb[96]" 543 234298 -400 234354 240 m2
+port "la_data_out[96]" 415 233707 -400 233763 240 m2
+port "la_data_in[96]" 287 233116 -400 233172 240 m2
+port "la_oenb[95]" 542 232525 -400 232581 240 m2
+port "la_data_out[95]" 414 231934 -400 231990 240 m2
+port "la_data_in[95]" 286 231343 -400 231399 240 m2
+port "la_oenb[94]" 541 230752 -400 230808 240 m2
+port "la_data_out[94]" 413 230161 -400 230217 240 m2
+port "la_data_in[94]" 285 229570 -400 229626 240 m2
+port "la_oenb[93]" 540 228979 -400 229035 240 m2
+port "la_data_out[93]" 412 228388 -400 228444 240 m2
+port "la_data_in[93]" 284 227797 -400 227853 240 m2
+port "la_oenb[92]" 539 227206 -400 227262 240 m2
+port "la_data_out[92]" 411 226615 -400 226671 240 m2
+port "la_data_in[92]" 283 226024 -400 226080 240 m2
+port "la_oenb[91]" 538 225433 -400 225489 240 m2
+port "la_data_out[91]" 410 224842 -400 224898 240 m2
+port "la_data_in[91]" 282 224251 -400 224307 240 m2
+port "la_oenb[90]" 537 223660 -400 223716 240 m2
+port "la_data_out[90]" 409 223069 -400 223125 240 m2
+port "la_data_in[90]" 281 222478 -400 222534 240 m2
+port "la_oenb[89]" 535 221887 -400 221943 240 m2
+port "la_data_out[89]" 407 221296 -400 221352 240 m2
+port "la_data_in[89]" 279 220705 -400 220761 240 m2
+port "la_oenb[88]" 534 220114 -400 220170 240 m2
+port "la_data_out[88]" 406 219523 -400 219579 240 m2
+port "la_data_in[88]" 278 218932 -400 218988 240 m2
+port "la_oenb[87]" 533 218341 -400 218397 240 m2
+port "la_data_out[87]" 405 217750 -400 217806 240 m2
+port "la_data_in[87]" 277 217159 -400 217215 240 m2
+port "la_oenb[86]" 532 216568 -400 216624 240 m2
+port "la_data_out[86]" 404 215977 -400 216033 240 m2
+port "la_data_in[86]" 276 215386 -400 215442 240 m2
+port "la_oenb[85]" 531 214795 -400 214851 240 m2
+port "la_data_out[85]" 403 214204 -400 214260 240 m2
+port "la_data_in[85]" 275 213613 -400 213669 240 m2
+port "la_oenb[84]" 530 213022 -400 213078 240 m2
+port "la_data_out[84]" 402 212431 -400 212487 240 m2
+port "la_data_in[84]" 274 211840 -400 211896 240 m2
+port "la_oenb[83]" 529 211249 -400 211305 240 m2
+port "la_data_out[83]" 401 210658 -400 210714 240 m2
+port "la_data_in[83]" 273 210067 -400 210123 240 m2
+port "la_oenb[82]" 528 209476 -400 209532 240 m2
+port "la_data_out[82]" 400 208885 -400 208941 240 m2
+port "la_data_in[82]" 272 208294 -400 208350 240 m2
+port "la_oenb[81]" 527 207703 -400 207759 240 m2
+port "la_data_out[81]" 399 207112 -400 207168 240 m2
+port "la_data_in[81]" 271 206521 -400 206577 240 m2
+port "la_oenb[80]" 526 205930 -400 205986 240 m2
+port "la_data_out[80]" 398 205339 -400 205395 240 m2
+port "la_data_in[80]" 270 204748 -400 204804 240 m2
+port "la_oenb[79]" 524 204157 -400 204213 240 m2
+port "la_data_out[79]" 396 203566 -400 203622 240 m2
+port "la_data_in[79]" 268 202975 -400 203031 240 m2
+port "la_oenb[78]" 523 202384 -400 202440 240 m2
+port "la_data_out[78]" 395 201793 -400 201849 240 m2
+port "la_data_in[78]" 267 201202 -400 201258 240 m2
+port "la_oenb[77]" 522 200611 -400 200667 240 m2
+port "la_data_out[77]" 394 200020 -400 200076 240 m2
+port "la_data_in[77]" 266 199429 -400 199485 240 m2
+port "la_oenb[76]" 521 198838 -400 198894 240 m2
+port "la_data_out[76]" 393 198247 -400 198303 240 m2
+port "la_data_in[76]" 265 197656 -400 197712 240 m2
+port "la_oenb[75]" 520 197065 -400 197121 240 m2
+port "la_data_out[75]" 392 196474 -400 196530 240 m2
+port "la_data_in[75]" 264 195883 -400 195939 240 m2
+port "la_oenb[74]" 519 195292 -400 195348 240 m2
+port "la_data_out[74]" 391 194701 -400 194757 240 m2
+port "la_data_in[74]" 263 194110 -400 194166 240 m2
+port "la_oenb[73]" 518 193519 -400 193575 240 m2
+port "la_data_out[73]" 390 192928 -400 192984 240 m2
+port "la_data_in[73]" 262 192337 -400 192393 240 m2
+port "la_oenb[72]" 517 191746 -400 191802 240 m2
+port "la_data_out[72]" 389 191155 -400 191211 240 m2
+port "la_data_in[72]" 261 190564 -400 190620 240 m2
+port "la_oenb[71]" 516 189973 -400 190029 240 m2
+port "la_data_out[71]" 388 189382 -400 189438 240 m2
+port "la_data_in[71]" 260 188791 -400 188847 240 m2
+port "la_oenb[70]" 515 188200 -400 188256 240 m2
+port "la_data_out[70]" 387 187609 -400 187665 240 m2
+port "la_data_in[70]" 259 187018 -400 187074 240 m2
+port "la_oenb[69]" 513 186427 -400 186483 240 m2
+port "la_data_out[69]" 385 185836 -400 185892 240 m2
+port "la_data_in[69]" 257 185245 -400 185301 240 m2
+port "la_oenb[68]" 512 184654 -400 184710 240 m2
+port "la_data_out[68]" 384 184063 -400 184119 240 m2
+port "la_data_in[68]" 256 183472 -400 183528 240 m2
+port "la_oenb[67]" 511 182881 -400 182937 240 m2
+port "la_data_out[67]" 383 182290 -400 182346 240 m2
+port "la_data_in[67]" 255 181699 -400 181755 240 m2
+port "la_oenb[66]" 510 181108 -400 181164 240 m2
+port "la_data_out[66]" 382 180517 -400 180573 240 m2
+port "la_data_in[66]" 254 179926 -400 179982 240 m2
+port "la_oenb[65]" 509 179335 -400 179391 240 m2
+port "la_data_out[65]" 381 178744 -400 178800 240 m2
+port "la_data_in[65]" 253 178153 -400 178209 240 m2
+port "la_oenb[64]" 508 177562 -400 177618 240 m2
+port "la_data_out[64]" 380 176971 -400 177027 240 m2
+port "la_data_in[64]" 252 176380 -400 176436 240 m2
+port "la_oenb[63]" 507 175789 -400 175845 240 m2
+port "la_data_out[63]" 379 175198 -400 175254 240 m2
+port "la_data_in[63]" 251 174607 -400 174663 240 m2
+port "la_oenb[62]" 506 174016 -400 174072 240 m2
+port "la_data_out[62]" 378 173425 -400 173481 240 m2
+port "la_data_in[62]" 250 172834 -400 172890 240 m2
+port "la_oenb[61]" 505 172243 -400 172299 240 m2
+port "la_data_out[61]" 377 171652 -400 171708 240 m2
+port "la_data_in[61]" 249 171061 -400 171117 240 m2
+port "la_oenb[60]" 504 170470 -400 170526 240 m2
+port "la_data_out[60]" 376 169879 -400 169935 240 m2
+port "la_data_in[60]" 248 169288 -400 169344 240 m2
+port "la_oenb[59]" 502 168697 -400 168753 240 m2
+port "la_data_out[59]" 374 168106 -400 168162 240 m2
+port "la_data_in[59]" 246 167515 -400 167571 240 m2
+port "la_oenb[58]" 501 166924 -400 166980 240 m2
+port "la_data_out[58]" 373 166333 -400 166389 240 m2
+port "la_data_in[58]" 245 165742 -400 165798 240 m2
+port "la_oenb[57]" 500 165151 -400 165207 240 m2
+port "la_data_out[57]" 372 164560 -400 164616 240 m2
+port "la_data_in[57]" 244 163969 -400 164025 240 m2
+port "la_oenb[56]" 499 163378 -400 163434 240 m2
+port "la_data_out[56]" 371 162787 -400 162843 240 m2
+port "la_data_in[56]" 243 162196 -400 162252 240 m2
+port "la_oenb[55]" 498 161605 -400 161661 240 m2
+port "la_data_out[55]" 370 161014 -400 161070 240 m2
+port "la_data_in[55]" 242 160423 -400 160479 240 m2
+port "la_oenb[54]" 497 159832 -400 159888 240 m2
+port "la_data_out[54]" 369 159241 -400 159297 240 m2
+port "la_data_in[54]" 241 158650 -400 158706 240 m2
+port "la_oenb[53]" 496 158059 -400 158115 240 m2
+port "la_data_out[53]" 368 157468 -400 157524 240 m2
+port "la_data_in[53]" 240 156877 -400 156933 240 m2
+port "la_oenb[52]" 495 156286 -400 156342 240 m2
+port "la_data_out[52]" 367 155695 -400 155751 240 m2
+port "la_data_in[52]" 239 155104 -400 155160 240 m2
+port "la_oenb[51]" 494 154513 -400 154569 240 m2
+port "la_data_out[51]" 366 153922 -400 153978 240 m2
+port "la_data_in[51]" 238 153331 -400 153387 240 m2
+port "la_oenb[50]" 493 152740 -400 152796 240 m2
+port "la_data_out[50]" 365 152149 -400 152205 240 m2
+port "la_data_in[50]" 237 151558 -400 151614 240 m2
+port "la_oenb[49]" 491 150967 -400 151023 240 m2
+port "la_data_out[49]" 363 150376 -400 150432 240 m2
+port "la_data_in[49]" 235 149785 -400 149841 240 m2
+port "la_oenb[48]" 490 149194 -400 149250 240 m2
+port "la_data_out[48]" 362 148603 -400 148659 240 m2
+port "la_data_in[48]" 234 148012 -400 148068 240 m2
+port "la_oenb[47]" 489 147421 -400 147477 240 m2
+port "la_data_out[47]" 361 146830 -400 146886 240 m2
+port "la_data_in[47]" 233 146239 -400 146295 240 m2
+port "la_oenb[46]" 488 145648 -400 145704 240 m2
+port "la_data_out[46]" 360 145057 -400 145113 240 m2
+port "la_data_in[46]" 232 144466 -400 144522 240 m2
+port "la_oenb[45]" 487 143875 -400 143931 240 m2
+port "la_data_out[45]" 359 143284 -400 143340 240 m2
+port "la_data_in[45]" 231 142693 -400 142749 240 m2
+port "la_oenb[44]" 486 142102 -400 142158 240 m2
+port "la_data_out[44]" 358 141511 -400 141567 240 m2
+port "la_data_in[44]" 230 140920 -400 140976 240 m2
+port "la_oenb[43]" 485 140329 -400 140385 240 m2
+port "la_data_out[43]" 357 139738 -400 139794 240 m2
+port "la_data_in[43]" 229 139147 -400 139203 240 m2
+port "la_oenb[42]" 484 138556 -400 138612 240 m2
+port "la_data_out[42]" 356 137965 -400 138021 240 m2
+port "la_data_in[42]" 228 137374 -400 137430 240 m2
+port "la_oenb[41]" 483 136783 -400 136839 240 m2
+port "la_data_out[41]" 355 136192 -400 136248 240 m2
+port "la_data_in[41]" 227 135601 -400 135657 240 m2
+port "la_oenb[40]" 482 135010 -400 135066 240 m2
+port "la_data_out[40]" 354 134419 -400 134475 240 m2
+port "la_data_in[40]" 226 133828 -400 133884 240 m2
+port "la_oenb[39]" 480 133237 -400 133293 240 m2
+port "la_data_out[39]" 352 132646 -400 132702 240 m2
+port "la_data_in[39]" 224 132055 -400 132111 240 m2
+port "la_oenb[38]" 479 131464 -400 131520 240 m2
+port "la_data_out[38]" 351 130873 -400 130929 240 m2
+port "la_data_in[38]" 223 130282 -400 130338 240 m2
+port "la_oenb[37]" 478 129691 -400 129747 240 m2
+port "la_data_out[37]" 350 129100 -400 129156 240 m2
+port "la_data_in[37]" 222 128509 -400 128565 240 m2
+port "la_oenb[36]" 477 127918 -400 127974 240 m2
+port "la_data_out[36]" 349 127327 -400 127383 240 m2
+port "la_data_in[36]" 221 126736 -400 126792 240 m2
+port "la_oenb[35]" 476 126145 -400 126201 240 m2
+port "la_data_out[35]" 348 125554 -400 125610 240 m2
+port "la_data_in[35]" 220 124963 -400 125019 240 m2
+port "la_oenb[34]" 475 124372 -400 124428 240 m2
+port "la_data_out[34]" 347 123781 -400 123837 240 m2
+port "la_data_in[34]" 219 123190 -400 123246 240 m2
+port "la_oenb[33]" 474 122599 -400 122655 240 m2
+port "la_data_out[33]" 346 122008 -400 122064 240 m2
+port "la_data_in[33]" 218 121417 -400 121473 240 m2
+port "la_oenb[32]" 473 120826 -400 120882 240 m2
+port "la_data_out[32]" 345 120235 -400 120291 240 m2
+port "la_data_in[32]" 217 119644 -400 119700 240 m2
+port "la_oenb[31]" 472 119053 -400 119109 240 m2
+port "la_data_out[31]" 344 118462 -400 118518 240 m2
+port "la_data_in[31]" 216 117871 -400 117927 240 m2
+port "la_oenb[30]" 471 117280 -400 117336 240 m2
+port "la_data_out[30]" 343 116689 -400 116745 240 m2
+port "la_data_in[30]" 215 116098 -400 116154 240 m2
+port "la_oenb[29]" 469 115507 -400 115563 240 m2
+port "la_data_out[29]" 341 114916 -400 114972 240 m2
+port "la_data_in[29]" 213 114325 -400 114381 240 m2
+port "la_oenb[28]" 468 113734 -400 113790 240 m2
+port "la_data_out[28]" 340 113143 -400 113199 240 m2
+port "la_data_in[28]" 212 112552 -400 112608 240 m2
+port "la_oenb[27]" 467 111961 -400 112017 240 m2
+port "la_data_out[27]" 339 111370 -400 111426 240 m2
+port "la_data_in[27]" 211 110779 -400 110835 240 m2
+port "la_oenb[26]" 466 110188 -400 110244 240 m2
+port "la_data_out[26]" 338 109597 -400 109653 240 m2
+port "la_data_in[26]" 210 109006 -400 109062 240 m2
+port "la_oenb[25]" 465 108415 -400 108471 240 m2
+port "la_data_out[25]" 337 107824 -400 107880 240 m2
+port "la_data_in[25]" 209 107233 -400 107289 240 m2
+port "la_oenb[24]" 464 106642 -400 106698 240 m2
+port "la_data_out[24]" 336 106051 -400 106107 240 m2
+port "la_data_in[24]" 208 105460 -400 105516 240 m2
+port "la_oenb[23]" 463 104869 -400 104925 240 m2
+port "la_data_out[23]" 335 104278 -400 104334 240 m2
+port "la_data_in[23]" 207 103687 -400 103743 240 m2
+port "la_oenb[22]" 462 103096 -400 103152 240 m2
+port "la_data_out[22]" 334 102505 -400 102561 240 m2
+port "la_data_in[22]" 206 101914 -400 101970 240 m2
+port "la_oenb[21]" 461 101323 -400 101379 240 m2
+port "la_data_out[21]" 333 100732 -400 100788 240 m2
+port "la_data_in[21]" 205 100141 -400 100197 240 m2
+port "la_oenb[20]" 460 99550 -400 99606 240 m2
+port "la_data_out[20]" 332 98959 -400 99015 240 m2
+port "la_data_in[20]" 204 98368 -400 98424 240 m2
+port "la_oenb[19]" 458 97777 -400 97833 240 m2
+port "la_data_out[19]" 330 97186 -400 97242 240 m2
+port "la_data_in[19]" 202 96595 -400 96651 240 m2
+port "la_oenb[18]" 457 96004 -400 96060 240 m2
+port "la_data_out[18]" 329 95413 -400 95469 240 m2
+port "la_data_in[18]" 201 94822 -400 94878 240 m2
+port "la_oenb[17]" 456 94231 -400 94287 240 m2
+port "la_data_out[17]" 328 93640 -400 93696 240 m2
+port "la_data_in[17]" 200 93049 -400 93105 240 m2
+port "la_oenb[16]" 455 92458 -400 92514 240 m2
+port "la_data_out[16]" 327 91867 -400 91923 240 m2
+port "la_data_in[16]" 199 91276 -400 91332 240 m2
+port "la_oenb[15]" 454 90685 -400 90741 240 m2
+port "la_data_out[15]" 326 90094 -400 90150 240 m2
+port "la_data_in[15]" 198 89503 -400 89559 240 m2
+port "la_oenb[14]" 453 88912 -400 88968 240 m2
+port "la_data_out[14]" 325 88321 -400 88377 240 m2
+port "la_data_in[14]" 197 87730 -400 87786 240 m2
+port "la_oenb[13]" 452 87139 -400 87195 240 m2
+port "la_data_out[13]" 324 86548 -400 86604 240 m2
+port "la_data_in[13]" 196 85957 -400 86013 240 m2
+port "la_oenb[12]" 451 85366 -400 85422 240 m2
+port "la_data_out[12]" 323 84775 -400 84831 240 m2
+port "la_data_in[12]" 195 84184 -400 84240 240 m2
+port "la_oenb[11]" 442 83593 -400 83649 240 m2
+port "la_data_out[11]" 314 83002 -400 83058 240 m2
+port "la_data_in[11]" 186 82411 -400 82467 240 m2
+port "la_oenb[10]" 431 81820 -400 81876 240 m2
+port "la_data_out[10]" 303 81229 -400 81285 240 m2
+port "la_data_in[10]" 175 80638 -400 80694 240 m2
+port "la_oenb[9]" 547 80047 -400 80103 240 m2
+port "la_data_out[9]" 419 79456 -400 79512 240 m2
+port "la_data_in[9]" 291 78865 -400 78921 240 m2
+port "la_oenb[8]" 536 78274 -400 78330 240 m2
+port "la_data_out[8]" 408 77683 -400 77739 240 m2
+port "la_data_in[8]" 280 77092 -400 77148 240 m2
+port "la_oenb[7]" 525 76501 -400 76557 240 m2
+port "la_data_out[7]" 397 75910 -400 75966 240 m2
+port "la_data_in[7]" 269 75319 -400 75375 240 m2
+port "la_oenb[6]" 514 74728 -400 74784 240 m2
+port "la_data_out[6]" 386 74137 -400 74193 240 m2
+port "la_data_in[6]" 258 73546 -400 73602 240 m2
+port "la_oenb[5]" 503 72955 -400 73011 240 m2
+port "la_data_out[5]" 375 72364 -400 72420 240 m2
+port "la_data_in[5]" 247 71773 -400 71829 240 m2
+port "la_oenb[4]" 492 71182 -400 71238 240 m2
+port "la_data_out[4]" 364 70591 -400 70647 240 m2
+port "la_data_in[4]" 236 70000 -400 70056 240 m2
+port "la_oenb[3]" 481 69409 -400 69465 240 m2
+port "la_data_out[3]" 353 68818 -400 68874 240 m2
+port "la_data_in[3]" 225 68227 -400 68283 240 m2
+port "la_oenb[2]" 470 67636 -400 67692 240 m2
+port "la_data_out[2]" 342 67045 -400 67101 240 m2
+port "la_data_in[2]" 214 66454 -400 66510 240 m2
+port "la_oenb[1]" 459 65863 -400 65919 240 m2
+port "la_data_out[1]" 331 65272 -400 65328 240 m2
+port "la_data_in[1]" 203 64681 -400 64737 240 m2
+port "la_oenb[0]" 420 64090 -400 64146 240 m2
+port "la_data_out[0]" 292 63499 -400 63555 240 m2
+port "la_data_in[0]" 164 62908 -400 62964 240 m2
+port "wbs_dat_o[31]" 664 62317 -400 62373 240 m2
+port "wbs_dat_i[31]" 632 61726 -400 61782 240 m2
+port "wbs_adr_i[31]" 599 61135 -400 61191 240 m2
+port "wbs_dat_o[30]" 663 60544 -400 60600 240 m2
+port "wbs_dat_i[30]" 631 59953 -400 60009 240 m2
+port "wbs_adr_i[30]" 598 59362 -400 59418 240 m2
+port "wbs_dat_o[29]" 661 58771 -400 58827 240 m2
+port "wbs_dat_i[29]" 629 58180 -400 58236 240 m2
+port "wbs_adr_i[29]" 596 57589 -400 57645 240 m2
+port "wbs_dat_o[28]" 660 56998 -400 57054 240 m2
+port "wbs_dat_i[28]" 628 56407 -400 56463 240 m2
+port "wbs_adr_i[28]" 595 55816 -400 55872 240 m2
+port "wbs_dat_o[27]" 659 55225 -400 55281 240 m2
+port "wbs_dat_i[27]" 627 54634 -400 54690 240 m2
+port "wbs_adr_i[27]" 594 54043 -400 54099 240 m2
+port "wbs_dat_o[26]" 658 53452 -400 53508 240 m2
+port "wbs_dat_i[26]" 626 52861 -400 52917 240 m2
+port "wbs_adr_i[26]" 593 52270 -400 52326 240 m2
+port "wbs_dat_o[25]" 657 51679 -400 51735 240 m2
+port "wbs_dat_i[25]" 625 51088 -400 51144 240 m2
+port "wbs_adr_i[25]" 592 50497 -400 50553 240 m2
+port "wbs_dat_o[24]" 656 49906 -400 49962 240 m2
+port "wbs_dat_i[24]" 624 49315 -400 49371 240 m2
+port "wbs_adr_i[24]" 591 48724 -400 48780 240 m2
+port "wbs_dat_o[23]" 655 48133 -400 48189 240 m2
+port "wbs_dat_i[23]" 623 47542 -400 47598 240 m2
+port "wbs_adr_i[23]" 590 46951 -400 47007 240 m2
+port "wbs_dat_o[22]" 654 46360 -400 46416 240 m2
+port "wbs_dat_i[22]" 622 45769 -400 45825 240 m2
+port "wbs_adr_i[22]" 589 45178 -400 45234 240 m2
+port "wbs_dat_o[21]" 653 44587 -400 44643 240 m2
+port "wbs_dat_i[21]" 621 43996 -400 44052 240 m2
+port "wbs_adr_i[21]" 588 43405 -400 43461 240 m2
+port "wbs_dat_o[20]" 652 42814 -400 42870 240 m2
+port "wbs_dat_i[20]" 620 42223 -400 42279 240 m2
+port "wbs_adr_i[20]" 587 41632 -400 41688 240 m2
+port "wbs_dat_o[19]" 650 41041 -400 41097 240 m2
+port "wbs_dat_i[19]" 618 40450 -400 40506 240 m2
+port "wbs_adr_i[19]" 585 39859 -400 39915 240 m2
+port "wbs_dat_o[18]" 649 39268 -400 39324 240 m2
+port "wbs_dat_i[18]" 617 38677 -400 38733 240 m2
+port "wbs_adr_i[18]" 584 38086 -400 38142 240 m2
+port "wbs_dat_o[17]" 648 37495 -400 37551 240 m2
+port "wbs_dat_i[17]" 616 36904 -400 36960 240 m2
+port "wbs_adr_i[17]" 583 36313 -400 36369 240 m2
+port "wbs_dat_o[16]" 647 35722 -400 35778 240 m2
+port "wbs_dat_i[16]" 615 35131 -400 35187 240 m2
+port "wbs_adr_i[16]" 582 34540 -400 34596 240 m2
+port "wbs_dat_o[15]" 646 33949 -400 34005 240 m2
+port "wbs_dat_i[15]" 614 33358 -400 33414 240 m2
+port "wbs_adr_i[15]" 581 32767 -400 32823 240 m2
+port "wbs_dat_o[14]" 645 32176 -400 32232 240 m2
+port "wbs_dat_i[14]" 613 31585 -400 31641 240 m2
+port "wbs_adr_i[14]" 580 30994 -400 31050 240 m2
+port "wbs_dat_o[13]" 644 30403 -400 30459 240 m2
+port "wbs_dat_i[13]" 612 29812 -400 29868 240 m2
+port "wbs_adr_i[13]" 579 29221 -400 29277 240 m2
+port "wbs_dat_o[12]" 643 28630 -400 28686 240 m2
+port "wbs_dat_i[12]" 611 28039 -400 28095 240 m2
+port "wbs_adr_i[12]" 578 27448 -400 27504 240 m2
+port "wbs_dat_o[11]" 642 26857 -400 26913 240 m2
+port "wbs_dat_i[11]" 610 26266 -400 26322 240 m2
+port "wbs_adr_i[11]" 577 25675 -400 25731 240 m2
+port "wbs_dat_o[10]" 641 25084 -400 25140 240 m2
+port "wbs_dat_i[10]" 609 24493 -400 24549 240 m2
+port "wbs_adr_i[10]" 576 23902 -400 23958 240 m2
+port "wbs_dat_o[9]" 671 23311 -400 23367 240 m2
+port "wbs_dat_i[9]" 639 22720 -400 22776 240 m2
+port "wbs_adr_i[9]" 606 22129 -400 22185 240 m2
+port "wbs_dat_o[8]" 670 21538 -400 21594 240 m2
+port "wbs_dat_i[8]" 638 20947 -400 21003 240 m2
+port "wbs_adr_i[8]" 605 20356 -400 20412 240 m2
+port "wbs_dat_o[7]" 669 19765 -400 19821 240 m2
+port "wbs_dat_i[7]" 637 19174 -400 19230 240 m2
+port "wbs_adr_i[7]" 604 18583 -400 18639 240 m2
+port "wbs_dat_o[6]" 668 17992 -400 18048 240 m2
+port "wbs_dat_i[6]" 636 17401 -400 17457 240 m2
+port "wbs_adr_i[6]" 603 16810 -400 16866 240 m2
+port "wbs_dat_o[5]" 667 16219 -400 16275 240 m2
+port "wbs_dat_i[5]" 635 15628 -400 15684 240 m2
+port "wbs_adr_i[5]" 602 15037 -400 15093 240 m2
+port "wbs_dat_o[4]" 666 14446 -400 14502 240 m2
+port "wbs_dat_i[4]" 634 13855 -400 13911 240 m2
+port "wbs_adr_i[4]" 601 13264 -400 13320 240 m2
+port "wbs_sel_i[3]" 675 12673 -400 12729 240 m2
+port "wbs_dat_o[3]" 665 12082 -400 12138 240 m2
+port "wbs_dat_i[3]" 633 11491 -400 11547 240 m2
+port "wbs_adr_i[3]" 600 10900 -400 10956 240 m2
+port "wbs_sel_i[2]" 674 10309 -400 10365 240 m2
+port "wbs_dat_o[2]" 662 9718 -400 9774 240 m2
+port "wbs_dat_i[2]" 630 9127 -400 9183 240 m2
+port "wbs_adr_i[2]" 597 8536 -400 8592 240 m2
+port "wbs_sel_i[1]" 673 7945 -400 8001 240 m2
+port "wbs_dat_o[1]" 651 7354 -400 7410 240 m2
+port "wbs_dat_i[1]" 619 6763 -400 6819 240 m2
+port "wbs_adr_i[1]" 586 6172 -400 6228 240 m2
+port "wbs_sel_i[0]" 672 5581 -400 5637 240 m2
+port "wbs_dat_o[0]" 640 4990 -400 5046 240 m2
+port "wbs_dat_i[0]" 608 4399 -400 4455 240 m2
+port "wbs_adr_i[0]" 575 3808 -400 3864 240 m2
+port "wbs_we_i" 677 3217 -400 3273 240 m2
+port "wbs_stb_i" 676 2626 -400 2682 240 m2
+port "wbs_cyc_i" 607 2035 -400 2091 240 m2
+port "wbs_ack_o" 574 1444 -400 1500 240 m2
+port "wb_rst_i" 573 853 -400 909 240 m2
+port "wb_clk_i" 572 262 -400 318 240 m2
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+cap "io_analog[5]" "io_analog[5]" 21250
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+cap "io_clamp_low[1]" "io_analog[5]" 525
+cap "io_clamp_high[2]" "io_clamp_low[2]" 525
+cap "io_analog[6]" "io_clamp_low[2]" 525
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_clamp_high[0]" "io_analog[4]" 525
+cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "io_analog[5]" "io_analog[5]" 26250
+cap "io_analog[5]" "io_clamp_high[1]" 525
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+subcap "la_data_in[46]" -327.272
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+subcap "la_data_in[91]" -355.892
+subcap "la_data_in[93]" -363.524
+subcap "la_data_in[93]" -268.124
+subcap "la_data_out[97]" -331.088
+subcap "la_data_out[97]" -300.56
+subcap "la_oenb[101]" -298.652
+subcap "la_oenb[101]" -332.996
+subcap "la_data_in[106]" -266.216
+subcap "la_data_in[106]" -365.432
+subcap "la_data_in[108]" -353.984
+subcap "la_data_in[108]" -277.664
+subcap "la_data_out[112]" -321.548
+subcap "la_data_out[112]" -310.1
+subcap "la_oenb[116]" -289.112
+subcap "la_oenb[116]" -342.536
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+subcap "la_data_in[123]" -287.204
+subcap "la_data_out[127]" -312.008
+subcap "la_data_out[127]" -319.64
+subcap "io_in_3v3[0]" -200.4
+subcap "io_in[0]" -200.4
+subcap "io_out[0]" -200.4
+subcap "io_oeb[0]" -200.4
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+subcap "io_in_3v3[24]" -308.452
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+subcap "io_in_3v3[24]" -305.276
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+subcap "io_out[3]" -200.4
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+subcap "gpio_analog[16]" -316.392
+subcap "io_in_3v3[5]" -200.4
+subcap "io_in[5]" -384.552
+subcap "io_in[5]" -429.576
+subcap "io_out[5]" -200.4
+subcap "io_oeb[5]" -200.4
+subcap "gpio_noesd[15]" -329.096
+subcap "gpio_noesd[15]" -284.632
+subcap "io_in_3v3[6]" -420.196
+subcap "io_in_3v3[6]" -393.932
+subcap "io_in[6]" -200.4
+subcap "io_out[6]" -200.4
+subcap "io_oeb[6]" -200.4
+subcap "vssa1" -5992.79
+subcap "vssa1" -6073.39
+subcap "vssd2" -6352.88
+subcap "vssd2" -5980
+subcap "vssd2" -5890.88
+subcap "vssd1" -5912.19
+subcap "vssd1" -5992.79
+subcap "vdda2" -6352.88
+subcap "vdda2" -5980
+subcap "vdda2" -5890.88
+subcap "vdda1" -6073.39
+subcap "vdda1" -6153.99
+subcap "gpio_analog[0]" -200.4
+subcap "gpio_noesd[0]" -200.4
+subcap "io_in_3v3[7]" -200.4
+subcap "io_in[7]" -200.4
+subcap "io_out[7]" -200.4
+subcap "io_oeb[7]" -200.4
+subcap "gpio_analog[1]" -200.4
+subcap "gpio_noesd[1]" -200.4
+subcap "io_in_3v3[8]" -200.4
+subcap "io_in[8]" -200.4
+subcap "io_out[8]" -423.948
+subcap "io_out[8]" -390.18
+subcap "io_oeb[8]" -200.4
+subcap "io_in[18]" -268.752
+subcap "io_in[18]" -344.976
+subcap "gpio_analog[2]" -200.4
+subcap "gpio_noesd[2]" -200.4
+subcap "io_in_3v3[9]" -200.4
+subcap "io_in[9]" -200.4
+subcap "io_out[9]" -200.4
+subcap "io_oeb[9]" -200.4
+subcap "io_out[17]" -300.512
+subcap "io_out[17]" -313.216
+subcap "gpio_analog[3]" -200.4
+subcap "gpio_noesd[3]" -200.4
+subcap "io_in_3v3[10]" -200.4
+subcap "io_in[10]" -200.4
+subcap "io_out[10]" -200.4
+subcap "io_oeb[10]" -200.4
+subcap "io_oeb[16]" -332.272
+subcap "io_oeb[16]" -281.456
+subcap "gpio_analog[4]" -200.4
+subcap "gpio_noesd[4]" -200.4
+subcap "io_in_3v3[11]" -200.4
+subcap "io_in[11]" -200.4
+subcap "io_out[11]" -200.4
+subcap "io_oeb[11]" -200.4
+subcap "gpio_analog[8]" -515.994
+subcap "gpio_analog[5]" -200.4
+subcap "gpio_noesd[5]" -200.4
+subcap "io_in_3v3[12]" -200.4
+subcap "io_in[12]" -200.4
+subcap "io_out[12]" -200.4
+subcap "io_oeb[12]" -200.4
+subcap "gpio_analog[7]" -118.646
+subcap "gpio_analog[7]" -196.948
+subcap "vdda1" -6207.19
+subcap "vssa2" -5873.17
+subcap "vdda1" -6287.79
+subcap "vdda1" -5954.8
+subcap "vssa2" -5805.44
+subcap "gpio_analog[6]" -200.4
+subcap "gpio_noesd[6]" -200.4
+subcap "io_in_3v3[13]" -200.4
+subcap "io_in[13]" -390.18
+subcap "io_in[13]" -423.948
+subcap "io_out[13]" -200.4
+subcap "io_oeb[13]" -200.4
+subcap "vccd1" -6054.85
+subcap "vccd2" -5898.16
+subcap "vccd1" -6135.45
+subcap "vccd2" -6104.17
+subcap "io_analog[0]" -6591.86
+subcap "io_analog[0]" -6244
+subcap "io_analog[10]" -6334.63
+subcap "io_analog[8]" -6923.19
+subcap "io_analog[7]" -6901.44
+subcap "io_analog[6]" -2911.77
+subcap "io_analog[6]" -2757.36
+subcap "io_analog[6]" -6798.54
+subcap "io_analog[6]" -2974.77
+subcap "io_analog[6]" -2841.36
+subcap "io_analog[6]" -6720.8
+subcap "io_analog[5]" -2938.77
+subcap "io_analog[5]" -2793.36
+subcap "io_analog[5]" -6852.54
+subcap "io_analog[5]" -2988
+subcap "io_analog[5]" -2859
+subcap "io_analog[5]" -6752.54
+subcap "io_analog[3]" -6862.85
+subcap "io_analog[2]" -6961.04
+subcap "io_analog[1]" -6915.54
+subcap "io_analog[9]" -5943.85
+subcap "io_analog[8]" -6083.79
+subcap "io_analog[7]" -6176.3
+subcap "io_analog[6]" -2670.33
+subcap "io_analog[6]" -2533.39
+subcap "io_analog[6]" -6489.29
+subcap "io_analog[6]" -2571.66
+subcap "io_analog[6]" -2477.89
+subcap "io_analog[6]" -6076
+subcap "io_clamp_low[2]" -3080.79
+subcap "io_clamp_high[2]" -2920.29
+subcap "io_analog[6]" -2973.51
+subcap "io_analog[6]" -2839.68
+subcap "io_analog[6]" -6922.02
+subcap "io_analog[6]" -2646.15
+subcap "io_analog[6]" -2510.45
+subcap "io_analog[6]" -6035.53
+cap "io_analog[6]" "io_analog[6]" 209.52
+cap "io_analog[6]" "io_analog[6]" 275.48
+cap "io_analog[6]" "io_analog[6]" 497
+cap "io_analog[6]" "io_analog[6]" 378
+cap "io_analog[6]" "io_analog[6]" 430.26
+cap "io_analog[6]" "io_analog[6]" 327.24
+subcap "io_analog[5]" -2650.83
+subcap "io_analog[5]" -2514.89
+subcap "io_analog[5]" -6435.79
+subcap "io_analog[5]" -2714.4
+subcap "io_analog[5]" -2631.81
+subcap "io_analog[5]" -6121.18
+cap "io_analog[5]" "io_analog[5]" 330.86
+cap "io_analog[5]" "io_analog[5]" 251.64
+cap "io_analog[5]" "io_analog[5]" 497
+cap "io_analog[5]" "io_analog[5]" 378
+cap "io_analog[5]" "layout_opamp_2_0/vss" 287.82
+cap "io_analog[5]" "layout_opamp_2_0/vss" 378.43
+subcap "io_clamp_low[1]" -3027.29
+subcap "io_clamp_high[1]" -2866.79
+subcap "io_analog[5]" -2475.33
+subcap "io_analog[5]" -2348.39
+subcap "io_analog[5]" -5954.29
+subcap "io_analog[4]" -2553.33
+subcap "io_analog[4]" -2422.39
+subcap "io_analog[4]" -6168.29
+subcap "io_clamp_low[0]" -2759.79
+subcap "io_clamp_high[0]" -3348.29
+subcap "io_clamp_high[0]" -2828
+subcap "io_analog[4]" -2650.83
+subcap "io_analog[4]" -2514.89
+subcap "io_analog[4]" -6435.79
+subcap "io_analog[4]" -2532.66
+subcap "io_analog[4]" -2459.39
+subcap "io_analog[4]" -6084.28
+cap "io_analog[4]" "io_analog[4]" 353.16
+cap "io_analog[4]" "io_analog[4]" 464.34
+cap "layout_opamp_0/in2" "io_analog[4]" 262.98
+cap "layout_opamp_0/in2" "io_analog[4]" 345.77
+subcap "io_analog[3]" -6489.29
+subcap "io_analog[3]" -6096.89
+cap "io_analog[3]" "layout_opamp_0/in1" 25.38
+cap "io_analog[3]" "layout_opamp_0/in1" 41.36
+cap "io_analog[3]" "layout_opamp_0/in1" -203.16
+cap "io_analog[3]" "layout_opamp_0/in1" -291.62
+cap "layout_opamp_0/in1" "layout_opamp_0/in1" -229.14
+cap "layout_opamp_0/in1" "layout_opamp_0/in1" -164.82
+subcap "io_analog[2]" -6596.29
+subcap "io_analog[2]" -6105.52
+subcap "vssa1" -5775.56
+subcap "vssa1" -5880.16
+subcap "io_analog[1]" -6061.29
+merge "layout_opamp_0/out" "io_analog[1]" -5485.38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1783146 -8160 0 0 0 0 0 0
+merge "layout_opamp_3_0/out" "io_analog[10]" -4589.22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1545089 -6671 0 0 0 0 0 0
+merge "layout_opamp_2_0/out" "io_analog[6]" -24839.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4745374 -16266 -4639150 -12900 -4639150 -12900 0 0
+merge "layout_opamp_3_0/vdd" "vccd2" -4980.34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1155230 -8766 0 0 0 0 0 0
+merge "layout_opamp_0/vdd" "io_analog[2]" -5325.22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1672917 -8092 0 0 0 0 0 0
+merge "layout_opamp_0/vss" "io_analog[5]" -35542.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8308066 -28600 -5544900 -14300 -5544900 -14300 0 0
+merge "io_analog[5]" "io_analog[0]"
+merge "io_analog[0]" "layout_opamp_2_0/vss"
+merge "layout_opamp_2_0/vss" "layout_opamp_3_0/vss"
+merge "layout_opamp_3_0/vss" "vssa2"
+merge "vssa2" "SUB"
+merge "layout_opamp_2_0/vdd" "io_analog[7]" -5979.92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2130350 -8350 0 0 0 0 0 0
+merge "layout_opamp_2_0/in2" "io_analog[9]" -6276.24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2236860 -8761 0 0 0 0 0 0
+merge "layout_opamp_2_0/in1" "io_analog[8]" -6243.63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2228472 -8706 0 0 0 0 0 0
+merge "layout_opamp_0/in2" "io_analog[4]" -26529.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5629415 -16259 -5097800 -13600 -5097800 -13600 0 0
+merge "layout_opamp_0/in1" "io_analog[3]" -5996.68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2399200 -8006 0 0 0 0 0 0
+merge "layout_opamp_3_0/in1" "gpio_analog[7]" -595.433 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85169 -1203 0 0 0 0 0 0
+merge "layout_opamp_3_0/in2" "gpio_analog[8]" -144.216 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -23830 -282 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..a7b958e
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,2098 @@
+magic
+tech sky130A
+timestamp 1640403132
+<< metal2 >>
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+rect 231343 -400 231399 240
+rect 231934 -400 231990 240
+rect 232525 -400 232581 240
+rect 233116 -400 233172 240
+rect 233707 -400 233763 240
+rect 234298 -400 234354 240
+rect 234889 -400 234945 240
+rect 235480 -400 235536 240
+rect 236071 -400 236127 240
+rect 236662 -400 236718 240
+rect 237253 -400 237309 240
+rect 237844 -400 237900 240
+rect 238435 -400 238491 240
+rect 239026 -400 239082 240
+rect 239617 -400 239673 240
+rect 240208 -400 240264 240
+rect 240799 -400 240855 240
+rect 241390 -400 241446 240
+rect 241981 -400 242037 240
+rect 242572 -400 242628 240
+rect 243163 -400 243219 240
+rect 243754 -400 243810 240
+rect 244345 -400 244401 240
+rect 244936 -400 244992 240
+rect 245527 -400 245583 240
+rect 246118 -400 246174 240
+rect 246709 -400 246765 240
+rect 247300 -400 247356 240
+rect 247891 -400 247947 240
+rect 248482 -400 248538 240
+rect 249073 -400 249129 240
+rect 249664 -400 249720 240
+rect 250255 -400 250311 240
+rect 250846 -400 250902 240
+rect 251437 -400 251493 240
+rect 252028 -400 252084 240
+rect 252619 -400 252675 240
+rect 253210 -400 253266 240
+rect 253801 -400 253857 240
+rect 254392 -400 254448 240
+rect 254983 -400 255039 240
+rect 255574 -400 255630 240
+rect 256165 -400 256221 240
+rect 256756 -400 256812 240
+rect 257347 -400 257403 240
+rect 257938 -400 257994 240
+rect 258529 -400 258585 240
+rect 259120 -400 259176 240
+rect 259711 -400 259767 240
+rect 260302 -400 260358 240
+rect 260893 -400 260949 240
+rect 261484 -400 261540 240
+rect 262075 -400 262131 240
+rect 262666 -400 262722 240
+rect 263257 -400 263313 240
+rect 263848 -400 263904 240
+rect 264439 -400 264495 240
+rect 265030 -400 265086 240
+rect 265621 -400 265677 240
+rect 266212 -400 266268 240
+rect 266803 -400 266859 240
+rect 267394 -400 267450 240
+rect 267985 -400 268041 240
+rect 268576 -400 268632 240
+rect 269167 -400 269223 240
+rect 269758 -400 269814 240
+rect 270349 -400 270405 240
+rect 270940 -400 270996 240
+rect 271531 -400 271587 240
+rect 272122 -400 272178 240
+rect 272713 -400 272769 240
+rect 273304 -400 273360 240
+rect 273895 -400 273951 240
+rect 274486 -400 274542 240
+rect 275077 -400 275133 240
+rect 275668 -400 275724 240
+rect 276259 -400 276315 240
+rect 276850 -400 276906 240
+rect 277441 -400 277497 240
+rect 278032 -400 278088 240
+rect 278623 -400 278679 240
+rect 279214 -400 279270 240
+rect 279805 -400 279861 240
+rect 280396 -400 280452 240
+rect 280987 -400 281043 240
+rect 281578 -400 281634 240
+rect 282169 -400 282225 240
+rect 282760 -400 282816 240
+rect 283351 -400 283407 240
+rect 283942 -400 283998 240
+rect 284533 -400 284589 240
+rect 285124 -400 285180 240
+rect 285715 -400 285771 240
+rect 286306 -400 286362 240
+rect 286897 -400 286953 240
+rect 287488 -400 287544 240
+rect 288079 -400 288135 240
+rect 288670 -400 288726 240
+rect 289261 -400 289317 240
+rect 289852 -400 289908 240
+rect 290443 -400 290499 240
+rect 291034 -400 291090 240
+rect 291625 -400 291681 240
+<< metal3 >>
+rect 8097 351150 10597 352400
+rect 34097 351150 36597 352400
+rect 60097 351150 62597 352400
+rect 82797 351150 85297 352400
+rect 85447 351150 86547 352400
+rect 86697 351150 87797 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 111297 351150 112397 352400
+rect 112547 351150 113647 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 162147 351150 163247 352400
+rect 163397 351150 164497 352400
+rect 164647 351150 167147 352400
+rect 206697 351150 209197 352400
+rect 232697 351150 235197 352400
+rect 255297 351170 257697 352400
+rect 260297 351170 262697 352400
+rect 283297 351150 285797 352400
+rect -400 340121 850 342621
+rect 291150 338992 292400 341492
+rect -400 321921 830 324321
+rect 291170 319892 292400 322292
+rect -400 316921 830 319321
+rect 291170 314892 292400 317292
+rect 291760 294736 292400 294792
+rect 291760 294145 292400 294201
+rect 291760 293554 292400 293610
+rect 291760 292963 292400 293019
+rect 291760 292372 292400 292428
+rect 291760 291781 292400 291837
+rect -400 279721 830 282121
+rect -400 274721 830 277121
+rect 291170 275281 292400 277681
+rect 291170 270281 292400 272681
+rect -400 255765 240 255821
+rect -400 255174 240 255230
+rect -400 254583 240 254639
+rect -400 253992 240 254048
+rect -400 253401 240 253457
+rect -400 252810 240 252866
+rect 291760 250025 292400 250081
+rect 291760 249434 292400 249490
+rect 291760 248843 292400 248899
+rect 291760 248252 292400 248308
+rect 291760 247661 292400 247717
+rect 291760 247070 292400 247126
+rect -400 234154 240 234210
+rect -400 233563 240 233619
+rect -400 232972 240 233028
+rect -400 232381 240 232437
+rect -400 231790 240 231846
+rect -400 231199 240 231255
+rect 291760 227814 292400 227870
+rect 291760 227223 292400 227279
+rect 291760 226632 292400 226688
+rect 291760 226041 292400 226097
+rect 291760 225450 292400 225506
+rect 291760 224859 292400 224915
+rect -400 212543 240 212599
+rect -400 211952 240 212008
+rect -400 211361 240 211417
+rect -400 210770 240 210826
+rect -400 210179 240 210235
+rect -400 209588 240 209644
+rect 291760 205603 292400 205659
+rect 291760 205012 292400 205068
+rect 291760 204421 292400 204477
+rect 291760 203830 292400 203886
+rect 291760 203239 292400 203295
+rect 291760 202648 292400 202704
+rect -400 190932 240 190988
+rect -400 190341 240 190397
+rect -400 189750 240 189806
+rect -400 189159 240 189215
+rect -400 188568 240 188624
+rect -400 187977 240 188033
+rect 291760 182392 292400 182448
+rect 291760 181801 292400 181857
+rect 291760 181210 292400 181266
+rect 291760 180619 292400 180675
+rect 291760 180028 292400 180084
+rect 291760 179437 292400 179493
+rect -400 169321 240 169377
+rect -400 168730 240 168786
+rect -400 168139 240 168195
+rect -400 167548 240 167604
+rect -400 166957 240 167013
+rect -400 166366 240 166422
+rect 291760 159781 292400 159837
+rect 291760 159190 292400 159246
+rect 291760 158599 292400 158655
+rect 291760 158008 292400 158064
+rect 291760 157417 292400 157473
+rect 291760 156826 292400 156882
+rect -400 147710 240 147766
+rect -400 147119 240 147175
+rect -400 146528 240 146584
+rect -400 145937 240 145993
+rect -400 145346 240 145402
+rect -400 144755 240 144811
+rect 291760 137570 292400 137626
+rect 291760 136979 292400 137035
+rect 291760 136388 292400 136444
+rect 291760 135797 292400 135853
+rect 291760 135206 292400 135262
+rect 291760 134615 292400 134671
+rect -400 126199 240 126255
+rect -400 125608 240 125664
+rect -400 125017 240 125073
+rect -400 124426 240 124482
+rect -400 123835 240 123891
+rect -400 123244 240 123300
+rect 291170 117615 292400 120015
+rect 291170 112615 292400 115015
+rect -400 107444 830 109844
+rect -400 102444 830 104844
+rect 291170 95715 292400 98115
+rect 291170 90715 292400 93115
+rect -400 86444 830 88844
+rect -400 81444 830 83844
+rect 291170 73415 292400 75815
+rect 291170 68415 292400 70815
+rect -400 62388 240 62444
+rect -400 61797 240 61853
+rect -400 61206 240 61262
+rect -400 60615 240 60671
+rect -400 60024 240 60080
+rect -400 59433 240 59489
+rect 291760 47559 292400 47615
+rect 291760 46968 292400 47024
+rect 291760 46377 292400 46433
+rect 291760 45786 292400 45842
+rect -400 40777 240 40833
+rect -400 40186 240 40242
+rect -400 39595 240 39651
+rect -400 39004 240 39060
+rect -400 38413 240 38469
+rect -400 37822 240 37878
+rect 291760 25230 292400 25286
+rect 291760 24639 292400 24695
+rect 291760 24048 292400 24104
+rect 291760 23457 292400 23513
+rect -400 19166 240 19222
+rect -400 18575 240 18631
+rect -400 17984 240 18040
+rect -400 17393 240 17449
+rect -400 16802 240 16858
+rect -400 16211 240 16267
+rect 291760 12001 292400 12057
+rect 291760 11410 292400 11466
+rect 291760 10819 292400 10875
+rect 291760 10228 292400 10284
+rect 291760 9637 292400 9693
+rect 291760 9046 292400 9102
+rect -400 8455 240 8511
+rect 291760 8455 292400 8511
+rect -400 7864 240 7920
+rect 291760 7864 292400 7920
+rect -400 7273 240 7329
+rect 291760 7273 292400 7329
+rect -400 6682 240 6738
+rect 291760 6682 292400 6738
+rect -400 6091 240 6147
+rect 291760 6091 292400 6147
+rect -400 5500 240 5556
+rect 291760 5500 292400 5556
+rect -400 4909 240 4965
+rect 291760 4909 292400 4965
+rect -400 4318 240 4374
+rect 291760 4318 292400 4374
+rect -400 3727 240 3783
+rect 291760 3727 292400 3783
+rect -400 3136 240 3192
+rect 291760 3136 292400 3192
+rect -400 2545 240 2601
+rect 291760 2545 292400 2601
+rect -400 1954 240 2010
+rect 291760 1954 292400 2010
+rect -400 1363 240 1419
+rect 291760 1363 292400 1419
+rect -400 772 240 828
+rect 291760 772 292400 828
+<< metal4 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< metal5 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< comment >>
+rect -50 352000 292050 352050
+rect -50 0 0 352000
+rect 292000 0 292050 352000
+rect -50 -50 292050 0
+use layout_opamp_3 layout_opamp_3_0
+timestamp 1635438119
+transform 1 0 67079 0 1 203141
+box -67009 30776 -51996 137753
+use layout_opamp layout_opamp_0
+timestamp 1635434905
+transform 1 0 223495 0 1 340940
+box -57995 -2409 68132 10992
+use layout_opamp_2 layout_opamp_2_0
+timestamp 1640402886
+transform 1 0 63269 0 1 340125
+box -54849 -2409 47464 11257
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
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+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git "a/mag/user_analog_project_wrapper_empty \050copy\051.mag" "b/mag/user_analog_project_wrapper_empty \050copy\051.mag"
new file mode 100644
index 0000000..02dbe79
--- /dev/null
+++ "b/mag/user_analog_project_wrapper_empty \050copy\051.mag"
@@ -0,0 +1,2091 @@
+magic
+tech sky130A
+timestamp 1632839657
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+rect -400 168730 240 168786
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+rect -400 166366 240 166422
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+rect 291760 156826 292400 156882
+rect -400 147710 240 147766
+rect -400 147119 240 147175
+rect -400 146528 240 146584
+rect -400 145937 240 145993
+rect -400 145346 240 145402
+rect -400 144755 240 144811
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+rect 291760 136388 292400 136444
+rect 291760 135797 292400 135853
+rect 291760 135206 292400 135262
+rect 291760 134615 292400 134671
+rect -400 126199 240 126255
+rect -400 125608 240 125664
+rect -400 125017 240 125073
+rect -400 124426 240 124482
+rect -400 123835 240 123891
+rect -400 123244 240 123300
+rect 291170 117615 292400 120015
+rect 291170 112615 292400 115015
+rect -400 107444 830 109844
+rect -400 102444 830 104844
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+rect 291170 90715 292400 93115
+rect -400 86444 830 88844
+rect -400 81444 830 83844
+rect 291170 73415 292400 75815
+rect 291170 68415 292400 70815
+rect -400 62388 240 62444
+rect -400 61797 240 61853
+rect -400 61206 240 61262
+rect -400 60615 240 60671
+rect -400 60024 240 60080
+rect -400 59433 240 59489
+rect 291760 47559 292400 47615
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+rect -400 40777 240 40833
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+rect -400 39595 240 39651
+rect -400 39004 240 39060
+rect -400 38413 240 38469
+rect -400 37822 240 37878
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+rect 291760 24048 292400 24104
+rect 291760 23457 292400 23513
+rect -400 19166 240 19222
+rect -400 18575 240 18631
+rect -400 17984 240 18040
+rect -400 17393 240 17449
+rect -400 16802 240 16858
+rect -400 16211 240 16267
+rect 291760 12001 292400 12057
+rect 291760 11410 292400 11466
+rect 291760 10819 292400 10875
+rect 291760 10228 292400 10284
+rect 291760 9637 292400 9693
+rect 291760 9046 292400 9102
+rect -400 8455 240 8511
+rect 291760 8455 292400 8511
+rect -400 7864 240 7920
+rect 291760 7864 292400 7920
+rect -400 7273 240 7329
+rect 291760 7273 292400 7329
+rect -400 6682 240 6738
+rect 291760 6682 292400 6738
+rect -400 6091 240 6147
+rect 291760 6091 292400 6147
+rect -400 5500 240 5556
+rect 291760 5500 292400 5556
+rect -400 4909 240 4965
+rect 291760 4909 292400 4965
+rect -400 4318 240 4374
+rect 291760 4318 292400 4374
+rect -400 3727 240 3783
+rect 291760 3727 292400 3783
+rect -400 3136 240 3192
+rect 291760 3136 292400 3192
+rect -400 2545 240 2601
+rect 291760 2545 292400 2601
+rect -400 1954 240 2010
+rect 291760 1954 292400 2010
+rect -400 1363 240 1419
+rect 291760 1363 292400 1419
+rect -400 772 240 828
+rect 291760 772 292400 828
+<< metal4 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< metal5 >>
+rect 82797 351150 85297 352400
+rect 87947 351150 90447 352400
+rect 108647 351150 111147 352400
+rect 113797 351150 116297 352400
+rect 159497 351150 161997 352400
+rect 164647 351150 167147 352400
+<< comment >>
+rect -50 352000 292050 352050
+rect -50 0 0 352000
+rect 292000 0 292050 352000
+rect -50 -50 292050 0
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/netgen/comp.out b/netgen/comp.out
new file mode 100644
index 0000000..42163df
--- /dev/null
+++ b/netgen/comp.out
@@ -0,0 +1,2097 @@
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+Equate elements: no current cell.
+
+Class sky130_fd_sc_hvl__buf_8(0): Merged 18 parallel devices.
+Class sky130_fd_sc_hvl__buf_8(1): Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_g5v0d10v5 (2) |sky130_fd_pr__nfet_g5v0d10v5 (2)
+sky130_fd_pr__pfet_g5v0d10v5 (2) |sky130_fd_pr__pfet_g5v0d10v5 (2)
+Number of devices: 4 |Number of devices: 4
+Number of nets: 7 |Number of nets: 7
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hvl__buf_8 |Circuit 2: sky130_fd_sc_hvl__buf_8
+-------------------------------------------|-------------------------------------------
+A |A
+VPWR |VPWR
+VPB |VPB
+X |X
+VGND |VGND
+VNB |VNB
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hvl__buf_8 and sky130_fd_sc_hvl__buf_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hvl__schmittbuf_1 |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_g5v0d10v5 (4) |sky130_fd_pr__nfet_g5v0d10v5 (4)
+sky130_fd_pr__pfet_g5v0d10v5 (4) |sky130_fd_pr__pfet_g5v0d10v5 (4)
+sky130_fd_pr__res_generic_nd__hv (1) |sky130_fd_pr__res_generic_nd__hv (1)
+sky130_fd_pr__res_generic_pd__hv (1) |sky130_fd_pr__res_generic_pd__hv (1)
+Number of devices: 10 |Number of devices: 10
+Number of nets: 11 |Number of nets: 11
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hvl__schmittbuf_1 |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1
+-------------------------------------------|-------------------------------------------
+A |A
+VPB |VPB
+VNB |VNB
+VGND |VGND
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hvl__schmittbuf_1 and sky130_fd_sc_hvl__schmittbuf_1 are equivalent.
+
+Class sky130_fd_sc_hvl__inv_8(0): Merged 14 parallel devices.
+Class sky130_fd_sc_hvl__inv_8(1): Merged 14 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_g5v0d10v5 (1) |sky130_fd_pr__pfet_g5v0d10v5 (1)
+sky130_fd_pr__nfet_g5v0d10v5 (1) |sky130_fd_pr__nfet_g5v0d10v5 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hvl__inv_8 |Circuit 2: sky130_fd_sc_hvl__inv_8
+-------------------------------------------|-------------------------------------------
+VPWR |VPWR
+VPB |VPB
+VGND |VGND
+VNB |VNB
+A |A
+Y |Y
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hvl__inv_8 and sky130_fd_sc_hvl__inv_8 are equivalent.
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_W5U4AW in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_3YBPVB in circuit example_por (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_WRT4AW in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in circuit example_por (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in circuit example_por (0)(1 instance)
+
+Class example_por(0): Merged 20 parallel devices.
+Class example_por(0): Merged 24 series devices.
+Subcircuit summary:
+Circuit 1: example_por |Circuit 2: example_por
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__cap_mim_m3_2 (1) |sky130_fd_pr__cap_mim_m3_2 (1)
+sky130_fd_sc_hvl__buf_8 (2) |sky130_fd_sc_hvl__buf_8 (2)
+sky130_fd_pr__pfet_g5v0d10v5 (8) |sky130_fd_pr__pfet_g5v0d10v5 (8)
+sky130_fd_pr__nfet_g5v0d10v5 (3) |sky130_fd_pr__nfet_g5v0d10v5 (3)
+sky130_fd_pr__res_xhigh_po_0p69 (3) |sky130_fd_pr__res_xhigh_po_0p69 (3)
+sky130_fd_sc_hvl__schmittbuf_1 (1) |sky130_fd_sc_hvl__schmittbuf_1 (1)
+sky130_fd_pr__cap_mim_m3_1 (1) |sky130_fd_pr__cap_mim_m3_1 (1)
+sky130_fd_sc_hvl__inv_8 (1) |sky130_fd_sc_hvl__inv_8 (1)
+Number of devices: 20 |Number of devices: 20
+Number of nets: 16 |Number of nets: 16
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: example_por |Circuit 2: example_por
+-------------------------------------------|-------------------------------------------
+vdd3v3 |vdd3v3
+porb_h |porb_h
+porb_l |porb_l
+por_l |por_l
+vdd1v8 |vdd1v8
+vss |vss
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes example_por and example_por are equivalent.
+Flattening unmatched subcell user_analog_proj_example in circuit user_analog_project_wrapper (0)(1 instance)
+
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper(0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[2]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[3]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[8]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[5]
+Cell user_analog_project_wrapper(0) disconnected node: io_analog[6]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[14]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[16]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[17]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[18]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper(0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper(0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper(0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[17]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[18]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[19]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[1]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[20]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[21]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[22]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[23]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[24]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[25]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[26]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[2]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[3]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[4]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[5]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[6]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[7]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[8]
+Cell user_analog_project_wrapper(0) disconnected node: io_out[9]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[16]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[17]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[18]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[19]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[1]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[20]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[21]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[22]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[23]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[24]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[25]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[26]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[27]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[28]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[29]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[2]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[30]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[31]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[32]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[33]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[34]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[35]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[36]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[37]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[38]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[39]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[3]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[40]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[41]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[42]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[43]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[44]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[45]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[46]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[47]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[48]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[49]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[4]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[50]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[51]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[52]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[53]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[54]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[55]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[56]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[57]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[58]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[59]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[5]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[60]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[61]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[62]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[63]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[64]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[65]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[66]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[67]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[68]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[69]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[6]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[70]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[71]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[72]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[73]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[74]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[75]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[76]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[77]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[78]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[79]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[7]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[80]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[81]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[82]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[83]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[84]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[85]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[86]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[87]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[88]
+Cell user_analog_project_wrapper(0) disconnected node: la_data_in[89]
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+Cell user_analog_project_wrapper(1) disconnected node: io_out[25]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[24]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[23]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[22]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[21]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[20]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[19]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[18]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[17]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[14]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[13]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[10]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[9]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[8]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[7]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[6]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[5]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[4]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[3]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[2]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[1]
+Cell user_analog_project_wrapper(1) disconnected node: io_out[0]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper(1) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper(1) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[8]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[6]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[5]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[3]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[2]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper(1) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper(1) disconnected node: user_clock2
+Cell user_analog_project_wrapper(1) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper(1) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper(1) disconnected node: user_irq[0]
+Subcircuit summary:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+example_por (2) |example_por (2)
+sky130_fd_pr__res_generic_m3 (10) |sky130_fd_pr__res_generic_m3 (10)
+Number of devices: 12 |Number of devices: 12
+Number of nets: 21 |Number of nets: 21
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+vssd1 |vssd1
+vssa1 |vssa1
+vccd1 |vccd1
+io_analog[4] |io_analog[4]
+vdda1 |vdda1
+gpio_analog[3] |gpio_analog[3]
+io_out[11] |io_out[11]
+io_out[12] |io_out[12]
+gpio_analog[7] |gpio_analog[7]
+io_out[15] |io_out[15]
+io_out[16] |io_out[16]
+io_clamp_low[2] |io_clamp_low[2]
+io_clamp_high[2] |io_clamp_high[2]
+io_clamp_low[1] |io_clamp_low[1]
+io_clamp_high[1] |io_clamp_high[1]
+io_clamp_low[0] |io_clamp_low[0]
+io_clamp_high[0] |io_clamp_high[0]
+io_oeb[12] |io_oeb[12]
+io_oeb[16] |io_oeb[16]
+io_oeb[11] |io_oeb[11]
+io_oeb[15] |io_oeb[15]
+gpio_analog[0] |gpio_analog[0]
+gpio_analog[10] |gpio_analog[10]
+gpio_analog[11] |gpio_analog[11]
+gpio_analog[12] |gpio_analog[12]
+gpio_analog[13] |gpio_analog[13]
+gpio_analog[14] |gpio_analog[14]
+gpio_analog[15] |gpio_analog[15]
+gpio_analog[16] |gpio_analog[16]
+gpio_analog[17] |gpio_analog[17]
+gpio_analog[1] |gpio_analog[1]
+gpio_analog[2] |gpio_analog[2]
+gpio_analog[4] |gpio_analog[4]
+gpio_analog[5] |gpio_analog[5]
+gpio_analog[6] |gpio_analog[6]
+gpio_analog[8] |gpio_analog[8]
+gpio_analog[9] |gpio_analog[9]
+gpio_noesd[0] |gpio_noesd[0]
+gpio_noesd[10] |gpio_noesd[10]
+gpio_noesd[11] |gpio_noesd[11]
+gpio_noesd[12] |gpio_noesd[12]
+gpio_noesd[13] |gpio_noesd[13]
+gpio_noesd[14] |gpio_noesd[14]
+gpio_noesd[15] |gpio_noesd[15]
+gpio_noesd[16] |gpio_noesd[16]
+gpio_noesd[17] |gpio_noesd[17]
+gpio_noesd[1] |gpio_noesd[1]
+gpio_noesd[2] |gpio_noesd[2]
+gpio_noesd[3] |gpio_noesd[3]
+gpio_noesd[4] |gpio_noesd[4]
+gpio_noesd[5] |gpio_noesd[5]
+gpio_noesd[6] |gpio_noesd[6]
+gpio_noesd[7] |gpio_noesd[7]
+gpio_noesd[8] |gpio_noesd[8]
+gpio_noesd[9] |gpio_noesd[9]
+io_analog[0] |io_analog[0]
+io_analog[10] |io_analog[10]
+io_analog[1] |io_analog[1]
+io_analog[2] |io_analog[2]
+io_analog[3] |io_analog[3]
+io_analog[7] |io_analog[7]
+io_analog[8] |io_analog[8]
+io_analog[9] |io_analog[9]
+io_analog[5] |io_analog[5]
+io_analog[6] |io_analog[6]
+io_in[0] |io_in[0]
+io_in[10] |io_in[10]
+io_in[11] |io_in[11]
+io_in[12] |io_in[12]
+io_in[13] |io_in[13]
+io_in[14] |io_in[14]
+io_in[15] |io_in[15]
+io_in[16] |io_in[16]
+io_in[17] |io_in[17]
+io_in[18] |io_in[18]
+io_in[19] |io_in[19]
+io_in[1] |io_in[1]
+io_in[20] |io_in[20]
+io_in[21] |io_in[21]
+io_in[22] |io_in[22]
+io_in[23] |io_in[23]
+io_in[24] |io_in[24]
+io_in[25] |io_in[25]
+io_in[26] |io_in[26]
+io_in[2] |io_in[2]
+io_in[3] |io_in[3]
+io_in[4] |io_in[4]
+io_in[5] |io_in[5]
+io_in[6] |io_in[6]
+io_in[7] |io_in[7]
+io_in[8] |io_in[8]
+io_in[9] |io_in[9]
+io_in_3v3[0] |io_in_3v3[0]
+io_in_3v3[10] |io_in_3v3[10]
+io_in_3v3[11] |io_in_3v3[11]
+io_in_3v3[12] |io_in_3v3[12]
+io_in_3v3[13] |io_in_3v3[13]
+io_in_3v3[14] |io_in_3v3[14]
+io_in_3v3[15] |io_in_3v3[15]
+io_in_3v3[16] |io_in_3v3[16]
+io_in_3v3[17] |io_in_3v3[17]
+io_in_3v3[18] |io_in_3v3[18]
+io_in_3v3[19] |io_in_3v3[19]
+io_in_3v3[1] |io_in_3v3[1]
+io_in_3v3[20] |io_in_3v3[20]
+io_in_3v3[21] |io_in_3v3[21]
+io_in_3v3[22] |io_in_3v3[22]
+io_in_3v3[23] |io_in_3v3[23]
+io_in_3v3[24] |io_in_3v3[24]
+io_in_3v3[25] |io_in_3v3[25]
+io_in_3v3[26] |io_in_3v3[26]
+io_in_3v3[2] |io_in_3v3[2]
+io_in_3v3[3] |io_in_3v3[3]
+io_in_3v3[4] |io_in_3v3[4]
+io_in_3v3[5] |io_in_3v3[5]
+io_in_3v3[6] |io_in_3v3[6]
+io_in_3v3[7] |io_in_3v3[7]
+io_in_3v3[8] |io_in_3v3[8]
+io_in_3v3[9] |io_in_3v3[9]
+io_oeb[0] |io_oeb[0]
+io_oeb[10] |io_oeb[10]
+io_oeb[13] |io_oeb[13]
+io_oeb[14] |io_oeb[14]
+io_oeb[17] |io_oeb[17]
+io_oeb[18] |io_oeb[18]
+io_oeb[19] |io_oeb[19]
+io_oeb[1] |io_oeb[1]
+io_oeb[20] |io_oeb[20]
+io_oeb[21] |io_oeb[21]
+io_oeb[22] |io_oeb[22]
+io_oeb[23] |io_oeb[23]
+io_oeb[24] |io_oeb[24]
+io_oeb[25] |io_oeb[25]
+io_oeb[26] |io_oeb[26]
+io_oeb[2] |io_oeb[2]
+io_oeb[3] |io_oeb[3]
+io_oeb[4] |io_oeb[4]
+io_oeb[5] |io_oeb[5]
+io_oeb[6] |io_oeb[6]
+io_oeb[7] |io_oeb[7]
+io_oeb[8] |io_oeb[8]
+io_oeb[9] |io_oeb[9]
+io_out[0] |io_out[0]
+io_out[10] |io_out[10]
+io_out[13] |io_out[13]
+io_out[14] |io_out[14]
+io_out[17] |io_out[17]
+io_out[18] |io_out[18]
+io_out[19] |io_out[19]
+io_out[1] |io_out[1]
+io_out[20] |io_out[20]
+io_out[21] |io_out[21]
+io_out[22] |io_out[22]
+io_out[23] |io_out[23]
+io_out[24] |io_out[24]
+io_out[25] |io_out[25]
+io_out[26] |io_out[26]
+io_out[2] |io_out[2]
+io_out[3] |io_out[3]
+io_out[4] |io_out[4]
+io_out[5] |io_out[5]
+io_out[6] |io_out[6]
+io_out[7] |io_out[7]
+io_out[8] |io_out[8]
+io_out[9] |io_out[9]
+la_data_in[0] |la_data_in[0]
+la_data_in[100] |la_data_in[100]
+la_data_in[101] |la_data_in[101]
+la_data_in[102] |la_data_in[102]
+la_data_in[103] |la_data_in[103]
+la_data_in[104] |la_data_in[104]
+la_data_in[105] |la_data_in[105]
+la_data_in[106] |la_data_in[106]
+la_data_in[107] |la_data_in[107]
+la_data_in[108] |la_data_in[108]
+la_data_in[109] |la_data_in[109]
+la_data_in[10] |la_data_in[10]
+la_data_in[110] |la_data_in[110]
+la_data_in[111] |la_data_in[111]
+la_data_in[112] |la_data_in[112]
+la_data_in[113] |la_data_in[113]
+la_data_in[114] |la_data_in[114]
+la_data_in[115] |la_data_in[115]
+la_data_in[116] |la_data_in[116]
+la_data_in[117] |la_data_in[117]
+la_data_in[118] |la_data_in[118]
+la_data_in[119] |la_data_in[119]
+la_data_in[11] |la_data_in[11]
+la_data_in[120] |la_data_in[120]
+la_data_in[121] |la_data_in[121]
+la_data_in[122] |la_data_in[122]
+la_data_in[123] |la_data_in[123]
+la_data_in[124] |la_data_in[124]
+la_data_in[125] |la_data_in[125]
+la_data_in[126] |la_data_in[126]
+la_data_in[127] |la_data_in[127]
+la_data_in[12] |la_data_in[12]
+la_data_in[13] |la_data_in[13]
+la_data_in[14] |la_data_in[14]
+la_data_in[15] |la_data_in[15]
+la_data_in[16] |la_data_in[16]
+la_data_in[17] |la_data_in[17]
+la_data_in[18] |la_data_in[18]
+la_data_in[19] |la_data_in[19]
+la_data_in[1] |la_data_in[1]
+la_data_in[20] |la_data_in[20]
+la_data_in[21] |la_data_in[21]
+la_data_in[22] |la_data_in[22]
+la_data_in[23] |la_data_in[23]
+la_data_in[24] |la_data_in[24]
+la_data_in[25] |la_data_in[25]
+la_data_in[26] |la_data_in[26]
+la_data_in[27] |la_data_in[27]
+la_data_in[28] |la_data_in[28]
+la_data_in[29] |la_data_in[29]
+la_data_in[2] |la_data_in[2]
+la_data_in[30] |la_data_in[30]
+la_data_in[31] |la_data_in[31]
+la_data_in[32] |la_data_in[32]
+la_data_in[33] |la_data_in[33]
+la_data_in[34] |la_data_in[34]
+la_data_in[35] |la_data_in[35]
+la_data_in[36] |la_data_in[36]
+la_data_in[37] |la_data_in[37]
+la_data_in[38] |la_data_in[38]
+la_data_in[39] |la_data_in[39]
+la_data_in[3] |la_data_in[3]
+la_data_in[40] |la_data_in[40]
+la_data_in[41] |la_data_in[41]
+la_data_in[42] |la_data_in[42]
+la_data_in[43] |la_data_in[43]
+la_data_in[44] |la_data_in[44]
+la_data_in[45] |la_data_in[45]
+la_data_in[46] |la_data_in[46]
+la_data_in[47] |la_data_in[47]
+la_data_in[48] |la_data_in[48]
+la_data_in[49] |la_data_in[49]
+la_data_in[4] |la_data_in[4]
+la_data_in[50] |la_data_in[50]
+la_data_in[51] |la_data_in[51]
+la_data_in[52] |la_data_in[52]
+la_data_in[53] |la_data_in[53]
+la_data_in[54] |la_data_in[54]
+la_data_in[55] |la_data_in[55]
+la_data_in[56] |la_data_in[56]
+la_data_in[57] |la_data_in[57]
+la_data_in[58] |la_data_in[58]
+la_data_in[59] |la_data_in[59]
+la_data_in[5] |la_data_in[5]
+la_data_in[60] |la_data_in[60]
+la_data_in[61] |la_data_in[61]
+la_data_in[62] |la_data_in[62]
+la_data_in[63] |la_data_in[63]
+la_data_in[64] |la_data_in[64]
+la_data_in[65] |la_data_in[65]
+la_data_in[66] |la_data_in[66]
+la_data_in[67] |la_data_in[67]
+la_data_in[68] |la_data_in[68]
+la_data_in[69] |la_data_in[69]
+la_data_in[6] |la_data_in[6]
+la_data_in[70] |la_data_in[70]
+la_data_in[71] |la_data_in[71]
+la_data_in[72] |la_data_in[72]
+la_data_in[73] |la_data_in[73]
+la_data_in[74] |la_data_in[74]
+la_data_in[75] |la_data_in[75]
+la_data_in[76] |la_data_in[76]
+la_data_in[77] |la_data_in[77]
+la_data_in[78] |la_data_in[78]
+la_data_in[79] |la_data_in[79]
+la_data_in[7] |la_data_in[7]
+la_data_in[80] |la_data_in[80]
+la_data_in[81] |la_data_in[81]
+la_data_in[82] |la_data_in[82]
+la_data_in[83] |la_data_in[83]
+la_data_in[84] |la_data_in[84]
+la_data_in[85] |la_data_in[85]
+la_data_in[86] |la_data_in[86]
+la_data_in[87] |la_data_in[87]
+la_data_in[88] |la_data_in[88]
+la_data_in[89] |la_data_in[89]
+la_data_in[8] |la_data_in[8]
+la_data_in[90] |la_data_in[90]
+la_data_in[91] |la_data_in[91]
+la_data_in[92] |la_data_in[92]
+la_data_in[93] |la_data_in[93]
+la_data_in[94] |la_data_in[94]
+la_data_in[95] |la_data_in[95]
+la_data_in[96] |la_data_in[96]
+la_data_in[97] |la_data_in[97]
+la_data_in[98] |la_data_in[98]
+la_data_in[99] |la_data_in[99]
+la_data_in[9] |la_data_in[9]
+la_data_out[0] |la_data_out[0]
+la_data_out[100] |la_data_out[100]
+la_data_out[101] |la_data_out[101]
+la_data_out[102] |la_data_out[102]
+la_data_out[103] |la_data_out[103]
+la_data_out[104] |la_data_out[104]
+la_data_out[105] |la_data_out[105]
+la_data_out[106] |la_data_out[106]
+la_data_out[107] |la_data_out[107]
+la_data_out[108] |la_data_out[108]
+la_data_out[109] |la_data_out[109]
+la_data_out[10] |la_data_out[10]
+la_data_out[110] |la_data_out[110]
+la_data_out[111] |la_data_out[111]
+la_data_out[112] |la_data_out[112]
+la_data_out[113] |la_data_out[113]
+la_data_out[114] |la_data_out[114]
+la_data_out[115] |la_data_out[115]
+la_data_out[116] |la_data_out[116]
+la_data_out[117] |la_data_out[117]
+la_data_out[118] |la_data_out[118]
+la_data_out[119] |la_data_out[119]
+la_data_out[11] |la_data_out[11]
+la_data_out[120] |la_data_out[120]
+la_data_out[121] |la_data_out[121]
+la_data_out[122] |la_data_out[122]
+la_data_out[123] |la_data_out[123]
+la_data_out[124] |la_data_out[124]
+la_data_out[125] |la_data_out[125]
+la_data_out[126] |la_data_out[126]
+la_data_out[127] |la_data_out[127]
+la_data_out[12] |la_data_out[12]
+la_data_out[13] |la_data_out[13]
+la_data_out[14] |la_data_out[14]
+la_data_out[15] |la_data_out[15]
+la_data_out[16] |la_data_out[16]
+la_data_out[17] |la_data_out[17]
+la_data_out[18] |la_data_out[18]
+la_data_out[19] |la_data_out[19]
+la_data_out[1] |la_data_out[1]
+la_data_out[20] |la_data_out[20]
+la_data_out[21] |la_data_out[21]
+la_data_out[22] |la_data_out[22]
+la_data_out[23] |la_data_out[23]
+la_data_out[24] |la_data_out[24]
+la_data_out[25] |la_data_out[25]
+la_data_out[26] |la_data_out[26]
+la_data_out[27] |la_data_out[27]
+la_data_out[28] |la_data_out[28]
+la_data_out[29] |la_data_out[29]
+la_data_out[2] |la_data_out[2]
+la_data_out[30] |la_data_out[30]
+la_data_out[31] |la_data_out[31]
+la_data_out[32] |la_data_out[32]
+la_data_out[33] |la_data_out[33]
+la_data_out[34] |la_data_out[34]
+la_data_out[35] |la_data_out[35]
+la_data_out[36] |la_data_out[36]
+la_data_out[37] |la_data_out[37]
+la_data_out[38] |la_data_out[38]
+la_data_out[39] |la_data_out[39]
+la_data_out[3] |la_data_out[3]
+la_data_out[40] |la_data_out[40]
+la_data_out[41] |la_data_out[41]
+la_data_out[42] |la_data_out[42]
+la_data_out[43] |la_data_out[43]
+la_data_out[44] |la_data_out[44]
+la_data_out[45] |la_data_out[45]
+la_data_out[46] |la_data_out[46]
+la_data_out[47] |la_data_out[47]
+la_data_out[48] |la_data_out[48]
+la_data_out[49] |la_data_out[49]
+la_data_out[4] |la_data_out[4]
+la_data_out[50] |la_data_out[50]
+la_data_out[51] |la_data_out[51]
+la_data_out[52] |la_data_out[52]
+la_data_out[53] |la_data_out[53]
+la_data_out[54] |la_data_out[54]
+la_data_out[55] |la_data_out[55]
+la_data_out[56] |la_data_out[56]
+la_data_out[57] |la_data_out[57]
+la_data_out[58] |la_data_out[58]
+la_data_out[59] |la_data_out[59]
+la_data_out[5] |la_data_out[5]
+la_data_out[60] |la_data_out[60]
+la_data_out[61] |la_data_out[61]
+la_data_out[62] |la_data_out[62]
+la_data_out[63] |la_data_out[63]
+la_data_out[64] |la_data_out[64]
+la_data_out[65] |la_data_out[65]
+la_data_out[66] |la_data_out[66]
+la_data_out[67] |la_data_out[67]
+la_data_out[68] |la_data_out[68]
+la_data_out[69] |la_data_out[69]
+la_data_out[6] |la_data_out[6]
+la_data_out[70] |la_data_out[70]
+la_data_out[71] |la_data_out[71]
+la_data_out[72] |la_data_out[72]
+la_data_out[73] |la_data_out[73]
+la_data_out[74] |la_data_out[74]
+la_data_out[75] |la_data_out[75]
+la_data_out[76] |la_data_out[76]
+la_data_out[77] |la_data_out[77]
+la_data_out[78] |la_data_out[78]
+la_data_out[79] |la_data_out[79]
+la_data_out[7] |la_data_out[7]
+la_data_out[80] |la_data_out[80]
+la_data_out[81] |la_data_out[81]
+la_data_out[82] |la_data_out[82]
+la_data_out[83] |la_data_out[83]
+la_data_out[84] |la_data_out[84]
+la_data_out[85] |la_data_out[85]
+la_data_out[86] |la_data_out[86]
+la_data_out[87] |la_data_out[87]
+la_data_out[88] |la_data_out[88]
+la_data_out[89] |la_data_out[89]
+la_data_out[8] |la_data_out[8]
+la_data_out[90] |la_data_out[90]
+la_data_out[91] |la_data_out[91]
+la_data_out[92] |la_data_out[92]
+la_data_out[93] |la_data_out[93]
+la_data_out[94] |la_data_out[94]
+la_data_out[95] |la_data_out[95]
+la_data_out[96] |la_data_out[96]
+la_data_out[97] |la_data_out[97]
+la_data_out[98] |la_data_out[98]
+la_data_out[99] |la_data_out[99]
+la_data_out[9] |la_data_out[9]
+la_oenb[0] |la_oenb[0]
+la_oenb[100] |la_oenb[100]
+la_oenb[101] |la_oenb[101]
+la_oenb[102] |la_oenb[102]
+la_oenb[103] |la_oenb[103]
+la_oenb[104] |la_oenb[104]
+la_oenb[105] |la_oenb[105]
+la_oenb[106] |la_oenb[106]
+la_oenb[107] |la_oenb[107]
+la_oenb[108] |la_oenb[108]
+la_oenb[109] |la_oenb[109]
+la_oenb[10] |la_oenb[10]
+la_oenb[110] |la_oenb[110]
+la_oenb[111] |la_oenb[111]
+la_oenb[112] |la_oenb[112]
+la_oenb[113] |la_oenb[113]
+la_oenb[114] |la_oenb[114]
+la_oenb[115] |la_oenb[115]
+la_oenb[116] |la_oenb[116]
+la_oenb[117] |la_oenb[117]
+la_oenb[118] |la_oenb[118]
+la_oenb[119] |la_oenb[119]
+la_oenb[11] |la_oenb[11]
+la_oenb[120] |la_oenb[120]
+la_oenb[121] |la_oenb[121]
+la_oenb[122] |la_oenb[122]
+la_oenb[123] |la_oenb[123]
+la_oenb[124] |la_oenb[124]
+la_oenb[125] |la_oenb[125]
+la_oenb[126] |la_oenb[126]
+la_oenb[127] |la_oenb[127]
+la_oenb[12] |la_oenb[12]
+la_oenb[13] |la_oenb[13]
+la_oenb[14] |la_oenb[14]
+la_oenb[15] |la_oenb[15]
+la_oenb[16] |la_oenb[16]
+la_oenb[17] |la_oenb[17]
+la_oenb[18] |la_oenb[18]
+la_oenb[19] |la_oenb[19]
+la_oenb[1] |la_oenb[1]
+la_oenb[20] |la_oenb[20]
+la_oenb[21] |la_oenb[21]
+la_oenb[22] |la_oenb[22]
+la_oenb[23] |la_oenb[23]
+la_oenb[24] |la_oenb[24]
+la_oenb[25] |la_oenb[25]
+la_oenb[26] |la_oenb[26]
+la_oenb[27] |la_oenb[27]
+la_oenb[28] |la_oenb[28]
+la_oenb[29] |la_oenb[29]
+la_oenb[2] |la_oenb[2]
+la_oenb[30] |la_oenb[30]
+la_oenb[31] |la_oenb[31]
+la_oenb[32] |la_oenb[32]
+la_oenb[33] |la_oenb[33]
+la_oenb[34] |la_oenb[34]
+la_oenb[35] |la_oenb[35]
+la_oenb[36] |la_oenb[36]
+la_oenb[37] |la_oenb[37]
+la_oenb[38] |la_oenb[38]
+la_oenb[39] |la_oenb[39]
+la_oenb[3] |la_oenb[3]
+la_oenb[40] |la_oenb[40]
+la_oenb[41] |la_oenb[41]
+la_oenb[42] |la_oenb[42]
+la_oenb[43] |la_oenb[43]
+la_oenb[44] |la_oenb[44]
+la_oenb[45] |la_oenb[45]
+la_oenb[46] |la_oenb[46]
+la_oenb[47] |la_oenb[47]
+la_oenb[48] |la_oenb[48]
+la_oenb[49] |la_oenb[49]
+la_oenb[4] |la_oenb[4]
+la_oenb[50] |la_oenb[50]
+la_oenb[51] |la_oenb[51]
+la_oenb[52] |la_oenb[52]
+la_oenb[53] |la_oenb[53]
+la_oenb[54] |la_oenb[54]
+la_oenb[55] |la_oenb[55]
+la_oenb[56] |la_oenb[56]
+la_oenb[57] |la_oenb[57]
+la_oenb[58] |la_oenb[58]
+la_oenb[59] |la_oenb[59]
+la_oenb[5] |la_oenb[5]
+la_oenb[60] |la_oenb[60]
+la_oenb[61] |la_oenb[61]
+la_oenb[62] |la_oenb[62]
+la_oenb[63] |la_oenb[63]
+la_oenb[64] |la_oenb[64]
+la_oenb[65] |la_oenb[65]
+la_oenb[66] |la_oenb[66]
+la_oenb[67] |la_oenb[67]
+la_oenb[68] |la_oenb[68]
+la_oenb[69] |la_oenb[69]
+la_oenb[6] |la_oenb[6]
+la_oenb[70] |la_oenb[70]
+la_oenb[71] |la_oenb[71]
+la_oenb[72] |la_oenb[72]
+la_oenb[73] |la_oenb[73]
+la_oenb[74] |la_oenb[74]
+la_oenb[75] |la_oenb[75]
+la_oenb[76] |la_oenb[76]
+la_oenb[77] |la_oenb[77]
+la_oenb[78] |la_oenb[78]
+la_oenb[79] |la_oenb[79]
+la_oenb[7] |la_oenb[7]
+la_oenb[80] |la_oenb[80]
+la_oenb[81] |la_oenb[81]
+la_oenb[82] |la_oenb[82]
+la_oenb[83] |la_oenb[83]
+la_oenb[84] |la_oenb[84]
+la_oenb[85] |la_oenb[85]
+la_oenb[86] |la_oenb[86]
+la_oenb[87] |la_oenb[87]
+la_oenb[88] |la_oenb[88]
+la_oenb[89] |la_oenb[89]
+la_oenb[8] |la_oenb[8]
+la_oenb[90] |la_oenb[90]
+la_oenb[91] |la_oenb[91]
+la_oenb[92] |la_oenb[92]
+la_oenb[93] |la_oenb[93]
+la_oenb[94] |la_oenb[94]
+la_oenb[95] |la_oenb[95]
+la_oenb[96] |la_oenb[96]
+la_oenb[97] |la_oenb[97]
+la_oenb[98] |la_oenb[98]
+la_oenb[99] |la_oenb[99]
+la_oenb[9] |la_oenb[9]
+user_clock2 |user_clock2
+user_irq[0] |user_irq[0]
+user_irq[1] |user_irq[1]
+user_irq[2] |user_irq[2]
+vccd2 |vccd2
+vdda2 |vdda2
+vssa2 |vssa2
+vssd2 |vssd2
+wb_clk_i |wb_clk_i
+wb_rst_i |wb_rst_i
+wbs_ack_o |wbs_ack_o
+wbs_adr_i[0] |wbs_adr_i[0]
+wbs_adr_i[10] |wbs_adr_i[10]
+wbs_adr_i[11] |wbs_adr_i[11]
+wbs_adr_i[12] |wbs_adr_i[12]
+wbs_adr_i[13] |wbs_adr_i[13]
+wbs_adr_i[14] |wbs_adr_i[14]
+wbs_adr_i[15] |wbs_adr_i[15]
+wbs_adr_i[16] |wbs_adr_i[16]
+wbs_adr_i[17] |wbs_adr_i[17]
+wbs_adr_i[18] |wbs_adr_i[18]
+wbs_adr_i[19] |wbs_adr_i[19]
+wbs_adr_i[1] |wbs_adr_i[1]
+wbs_adr_i[20] |wbs_adr_i[20]
+wbs_adr_i[21] |wbs_adr_i[21]
+wbs_adr_i[22] |wbs_adr_i[22]
+wbs_adr_i[23] |wbs_adr_i[23]
+wbs_adr_i[24] |wbs_adr_i[24]
+wbs_adr_i[25] |wbs_adr_i[25]
+wbs_adr_i[26] |wbs_adr_i[26]
+wbs_adr_i[27] |wbs_adr_i[27]
+wbs_adr_i[28] |wbs_adr_i[28]
+wbs_adr_i[29] |wbs_adr_i[29]
+wbs_adr_i[2] |wbs_adr_i[2]
+wbs_adr_i[30] |wbs_adr_i[30]
+wbs_adr_i[31] |wbs_adr_i[31]
+wbs_adr_i[3] |wbs_adr_i[3]
+wbs_adr_i[4] |wbs_adr_i[4]
+wbs_adr_i[5] |wbs_adr_i[5]
+wbs_adr_i[6] |wbs_adr_i[6]
+wbs_adr_i[7] |wbs_adr_i[7]
+wbs_adr_i[8] |wbs_adr_i[8]
+wbs_adr_i[9] |wbs_adr_i[9]
+wbs_cyc_i |wbs_cyc_i
+wbs_dat_i[0] |wbs_dat_i[0]
+wbs_dat_i[10] |wbs_dat_i[10]
+wbs_dat_i[11] |wbs_dat_i[11]
+wbs_dat_i[12] |wbs_dat_i[12]
+wbs_dat_i[13] |wbs_dat_i[13]
+wbs_dat_i[14] |wbs_dat_i[14]
+wbs_dat_i[15] |wbs_dat_i[15]
+wbs_dat_i[16] |wbs_dat_i[16]
+wbs_dat_i[17] |wbs_dat_i[17]
+wbs_dat_i[18] |wbs_dat_i[18]
+wbs_dat_i[19] |wbs_dat_i[19]
+wbs_dat_i[1] |wbs_dat_i[1]
+wbs_dat_i[20] |wbs_dat_i[20]
+wbs_dat_i[21] |wbs_dat_i[21]
+wbs_dat_i[22] |wbs_dat_i[22]
+wbs_dat_i[23] |wbs_dat_i[23]
+wbs_dat_i[24] |wbs_dat_i[24]
+wbs_dat_i[25] |wbs_dat_i[25]
+wbs_dat_i[26] |wbs_dat_i[26]
+wbs_dat_i[27] |wbs_dat_i[27]
+wbs_dat_i[28] |wbs_dat_i[28]
+wbs_dat_i[29] |wbs_dat_i[29]
+wbs_dat_i[2] |wbs_dat_i[2]
+wbs_dat_i[30] |wbs_dat_i[30]
+wbs_dat_i[31] |wbs_dat_i[31]
+wbs_dat_i[3] |wbs_dat_i[3]
+wbs_dat_i[4] |wbs_dat_i[4]
+wbs_dat_i[5] |wbs_dat_i[5]
+wbs_dat_i[6] |wbs_dat_i[6]
+wbs_dat_i[7] |wbs_dat_i[7]
+wbs_dat_i[8] |wbs_dat_i[8]
+wbs_dat_i[9] |wbs_dat_i[9]
+wbs_dat_o[0] |wbs_dat_o[0]
+wbs_dat_o[10] |wbs_dat_o[10]
+wbs_dat_o[11] |wbs_dat_o[11]
+wbs_dat_o[12] |wbs_dat_o[12]
+wbs_dat_o[13] |wbs_dat_o[13]
+wbs_dat_o[14] |wbs_dat_o[14]
+wbs_dat_o[15] |wbs_dat_o[15]
+wbs_dat_o[16] |wbs_dat_o[16]
+wbs_dat_o[17] |wbs_dat_o[17]
+wbs_dat_o[18] |wbs_dat_o[18]
+wbs_dat_o[19] |wbs_dat_o[19]
+wbs_dat_o[1] |wbs_dat_o[1]
+wbs_dat_o[20] |wbs_dat_o[20]
+wbs_dat_o[21] |wbs_dat_o[21]
+wbs_dat_o[22] |wbs_dat_o[22]
+wbs_dat_o[23] |wbs_dat_o[23]
+wbs_dat_o[24] |wbs_dat_o[24]
+wbs_dat_o[25] |wbs_dat_o[25]
+wbs_dat_o[26] |wbs_dat_o[26]
+wbs_dat_o[27] |wbs_dat_o[27]
+wbs_dat_o[28] |wbs_dat_o[28]
+wbs_dat_o[29] |wbs_dat_o[29]
+wbs_dat_o[2] |wbs_dat_o[2]
+wbs_dat_o[30] |wbs_dat_o[30]
+wbs_dat_o[31] |wbs_dat_o[31]
+wbs_dat_o[3] |wbs_dat_o[3]
+wbs_dat_o[4] |wbs_dat_o[4]
+wbs_dat_o[5] |wbs_dat_o[5]
+wbs_dat_o[6] |wbs_dat_o[6]
+wbs_dat_o[7] |wbs_dat_o[7]
+wbs_dat_o[8] |wbs_dat_o[8]
+wbs_dat_o[9] |wbs_dat_o[9]
+wbs_sel_i[0] |wbs_sel_i[0]
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+wbs_sel_i[3] |wbs_sel_i[3]
+wbs_stb_i |wbs_stb_i
+wbs_we_i |wbs_we_i
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes user_analog_project_wrapper and user_analog_project_wrapper are equivalent.
+Circuits match uniquely.
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
new file mode 100644
index 0000000..499f397
--- /dev/null
+++ b/netgen/example_por.spice
@@ -0,0 +1,213 @@
+* NGSPICE file created from example_por.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW VSUBS m4_n3179_n3100# c2_n3079_n3000#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X
+X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=2.9175e+12p pd=2.189e+07u as=8.475e+11p ps=7.13e+06u w=1.5e+06u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.45875e+12p pd=1.289e+07u as=8.4e+11p ps=8.24e+06u w=750000u l=500000u
+X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.68e+12p ps=1.424e+07u w=1.5e+06u l=500000u
+X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=4.2375e+11p pd=4.13e+06u as=0p ps=0u w=750000u l=500000u
+X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200#
++ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200#
++ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297#
++ a_n683_n200#
+X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n80_n288# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288#
++ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200#
+X0 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X3 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n2578_n2932# a_5142_2500# a_n1034_n2932#
++ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500#
++ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932#
++ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500#
++ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500#
++ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500#
++ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932#
++ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500#
+X0 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X
+X0 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X1 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=4.0875e+11p pd=4.09e+06u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+X2 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=2.289e+11p pd=2.77e+06u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X3 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.02225e+12p pd=5.2e+06u as=0p ps=0u w=750000u l=500000u
+X4 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=1.113e+11p ps=1.37e+06u w=420000u l=500000u
+X5 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=1.9875e+11p pd=2.03e+06u as=9.478e+11p ps=4.36e+06u w=750000u l=500000u
+X6 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X7 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=3.975e+11p pd=3.53e+06u as=0p ps=0u w=1.5e+06u l=500000u
+X8 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X9 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.9875e+11p ps=2.03e+06u w=750000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC a_n80_n288# a_n138_n200# a_80_n200# w_n308_n458#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW VSUBS m3_n3136_n3100# c1_n3036_n3000#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200#
++ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297#
++ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200#
+X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=0p ps=0u w=2e+06u l=800000u
+X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200#
++ a_n80_n297#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=5.8e+11p pd=4.58e+06u as=5.8e+11p ps=4.58e+06u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=1.68e+12p pd=1.424e+07u as=2.055e+12p ps=1.774e+07u w=1.5e+06u l=500000u
+X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=8.4e+11p pd=8.24e+06u as=1.14e+12p ps=1.054e+07u w=750000u l=500000u
+X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.ends
+
+.subckt example_por vdd3v3 vdd1v8 vss porb_h por_l porb_l
+Xsky130_fd_pr__cap_mim_m3_2_W5U4AW_0 vss sky130_fd_sc_hvl__schmittbuf_1_0/A vss sky130_fd_pr__cap_mim_m3_2_W5U4AW
+Xsky130_fd_sc_hvl__buf_8_1 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 porb_l
++ sky130_fd_sc_hvl__buf_8
+Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_502_7653# vdd3v3 vdd3v3 vdd3v3
++ m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653#
++ m1_502_7653# vdd3v3 m1_502_7653# m1_502_7653# m1_502_7653# m1_502_7653# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 m1_721_6815# vss m1_721_6815# vss m1_721_6815#
++ m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# m1_721_6815# vss
++ vss m1_721_6815# vss m1_721_6815# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 li_2935_165# vss li_4479_165# li_4866_5813#
++ li_7182_5813# li_5251_165# li_1778_5813# li_9111_165# li_3322_5813# li_9498_5813#
++ li_7567_165# li_7954_5813# li_9883_165# li_8726_5813# li_7182_5813# li_619_165#
++ li_5638_5813# li_1006_5813# li_2163_165# li_5638_5813# li_619_165# li_6795_165#
++ li_5251_165# li_3707_165# li_9498_5813# li_2163_165# li_4479_165# li_4866_5813#
++ vss li_4094_5813# li_2550_5813# li_2550_5813# li_4094_5813# li_8339_165# li_2935_165#
++ li_7954_5813# li_9883_165# vss li_6410_5813# li_8339_165# vss li_1778_5813# li_1006_5813#
++ vss li_6410_5813# li_6023_165# li_6795_165# li_3707_165# vdd3v3 li_1391_165# li_9111_165#
++ li_8726_5813# li_7567_165# li_6023_165# vss li_1391_165# li_3322_5813# sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_2993_7658# vdd3v3 m1_721_6815# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3
++ vdd3v3 sky130_fd_sc_hvl__inv_8_0/A sky130_fd_sc_hvl__schmittbuf_1
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_2756_6573# vdd3v3 m1_4283_8081# m1_2756_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_6249_7690# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A
++ m1_2756_6573# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_185_6573# vdd3v3 m1_502_7653# m1_185_6573#
++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_6249_7690# m1_4283_8081#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 m1_721_6815# vss m1_2756_6573# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 li_2550_5813# vss m1_185_6573# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+Xsky130_fd_pr__cap_mim_m3_1_WRT4AW_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_WRT4AW
+Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_4283_8081# vdd3v3 m1_4283_8081#
++ vdd3v3 m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 m1_4283_8081# m1_4283_8081#
++ m1_4283_8081# m1_4283_8081# m1_4283_8081# m1_4283_8081# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_2993_7658# m1_502_7653#
++ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+Xsky130_fd_sc_hvl__inv_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd1v8 vdd1v8 por_l
++ sky130_fd_sc_hvl__inv_8
+Xsky130_fd_sc_hvl__buf_8_0 sky130_fd_sc_hvl__inv_8_0/A vss vss vdd3v3 vdd3v3 porb_h
++ sky130_fd_sc_hvl__buf_8
+.ends
+
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
new file mode 100755
index 0000000..1d1ad9f
--- /dev/null
+++ b/netgen/run_lvs_por.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the example_por layout
+#
+# NOTE: By specifying the testbench for the schematic-side netlist, the proper
+# includes used by the testbench simulation are picked up. Otherwise, the LVS
+# itself compares just the simple_por subcircuit from the testbench.
+#--------------------------------------------------------------------------------
+netgen -batch lvs "example_por.spice example_por" "../xschem/example_por_tb.spice example_por" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
new file mode 100755
index 0000000..e54f6f6
--- /dev/null
+++ b/netgen/run_lvs_wrapper_verilog.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
new file mode 100755
index 0000000..2e5828c
--- /dev/null
+++ b/netgen/run_lvs_wrapper_xschem.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level xschem subcircuit from the wrapper testbench.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..514f9a5
--- /dev/null
+++ b/netgen/user_analog_project_wrapper.spice
@@ -0,0 +1,341 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_2_W5U4AW c2_n3079_n3000# m4_n3179_n3100#
+X0 c2_n3079_n3000# m4_n3179_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_sc_hvl__buf_8 A VGND VPWR X VNB VPB
+X0 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X2 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X3 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X5 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X9 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X10 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X12 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X15 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X16 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X18 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X19 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X20 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X21 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ a_n683_n200# a_n189_n297# a_29_n297# a_189_n200#
++ a_n901_n200# a_247_n297# a_n407_n297# a_465_n297# a_407_n200# a_n625_n297# a_683_n297#
++ a_625_n200# a_n843_n297# w_n1101_n497# a_843_n200# a_n29_n200# a_n247_n200# a_n465_n200#
+X0 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X7 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS a_n792_n200# a_298_n200# a_516_n200# a_734_n200#
++ w_n962_n458# a_138_n288# a_n298_n288# a_80_n200# a_356_n288# a_n516_n288# a_574_n288#
++ a_n734_n288# a_n138_n200# a_n356_n200# a_n574_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n288# a_n792_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_734_n200# a_574_n288# a_516_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_298_n200# a_138_n288# a_80_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n138_n200# a_n298_n288# a_n356_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n288# a_n574_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_516_n200# a_356_n288# a_298_n200# w_n962_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 a_n1806_2500# a_n4122_n2932# a_n5280_2500#
++ a_2054_n2932# a_896_n2932# a_4756_2500# a_3598_n2932# a_3212_2500# a_n3736_n2932#
++ a_1668_n2932# a_n1806_n2932# a_5142_n2932# a_896_2500# a_510_n2932# a_n3350_2500#
++ a_n4508_2500# a_3212_n2932# a_n4894_2500# a_1282_2500# w_n5446_n3098# a_4756_n2932#
++ a_2826_2500# a_2826_n2932# a_n2192_n2932# a_n1034_2500# a_n2578_2500# a_n1420_2500#
++ a_n2964_2500# a_n648_n2932# a_n648_2500# a_n5280_n2932# a_n3350_n2932# a_4370_2500#
++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_n4894_n2932# a_124_2500# a_n2964_n2932#
++ a_n4122_2500# a_2054_2500# a_510_2500# a_n4508_n2932# a_4370_n2932# a_3598_2500#
++ a_3984_2500# a_2440_n2932# a_2440_2500# a_3984_n2932# a_n2192_2500# a_n3736_2500#
++ a_1668_2500# a_n262_n2932# a_n262_2500# a_n1034_n2932# a_5142_2500# a_n2578_n2932#
+X0 a_n2578_n2932# a_n2578_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X1 a_n1420_n2932# a_n1420_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X2 a_n1806_n2932# a_n1806_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X3 a_3212_n2932# a_3212_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X4 a_3598_n2932# a_3598_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X5 a_n2964_n2932# a_n2964_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X6 a_2826_n2932# a_2826_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X7 a_4370_n2932# a_4370_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X8 a_3984_n2932# a_3984_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X9 a_n262_n2932# a_n262_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X10 a_n3350_n2932# a_n3350_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X11 a_n4122_n2932# a_n4122_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X12 a_n3736_n2932# a_n3736_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X13 a_5142_n2932# a_5142_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X14 a_n4894_n2932# a_n4894_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X15 a_1282_n2932# a_1282_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X16 a_4756_n2932# a_4756_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X17 a_124_n2932# a_124_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X18 a_510_n2932# a_510_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X19 a_896_n2932# a_896_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X20 a_n648_n2932# a_n648_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X21 a_n5280_n2932# a_n5280_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X22 a_n4508_n2932# a_n4508_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X23 a_n1034_n2932# a_n1034_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X24 a_n2192_n2932# a_n2192_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X25 a_2054_n2932# a_2054_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X26 a_1668_n2932# a_1668_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+X27 a_2440_n2932# a_2440_2500# w_n5446_n3098# sky130_fd_pr__res_xhigh_po_0p69 l=2.5e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VPWR X VNB VPB
+X0 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X1 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+X4 a_78_463# VGND VNB sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u
+X5 a_64_207# VPWR VPB sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u
+X6 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X7 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=420000u l=500000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC w_n308_n458# a_80_n200# a_n138_n200# a_n80_n288#
+X0 a_80_n200# a_n80_n288# a_n138_n200# w_n308_n458# sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WRT4AW c1_n3036_n3000# m3_n3136_n3100#
+X0 c1_n3036_n3000# m3_n3136_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV a_n792_n200# a_138_n297# a_n298_n297#
++ a_298_n200# a_356_n297# a_n516_n297# a_574_n297# a_516_n200# a_n734_n297# a_734_n200#
++ a_n80_n297# a_80_n200# a_n138_n200# a_n356_n200# a_n574_n200# w_n992_n497#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X1 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X2 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X3 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X4 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X5 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+X6 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG a_n80_n297# a_80_n200# w_n338_n497# a_n138_n200#
+X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=2e+06u l=800000u
+.ends
+
+.subckt sky130_fd_sc_hvl__inv_8 A VGND VPWR Y VNB VPB
+X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X1 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X2 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X3 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X4 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X5 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X6 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X7 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X8 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X9 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X10 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X11 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X13 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=500000u
+X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=750000u l=500000u
+.ends
+
+.subckt layout_opamp vdd vss in1 in2 out
+X0 a_173_n2232# in1 a_n28_306# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X1 a_606_306# a_n28_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X2 a_n469_n962# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X3 a_n349_n973# a_n469_n962# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X4 out a_606_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X5 vdd a_n28_306# a_n28_306# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X6 vss a_n349_n973# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X7 vss a_n349_n973# a_n349_n973# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 a_606_306# in2 a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X9 a_n617_n951# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X10 a_n617_n951# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X11 vss a_n349_n973# a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+C0 in2 vss 138.44fF
+C1 in1 vss 53.47fF
+C2 a_n349_n973# vss 3.86fF
+C3 out vss 117.43fF
+C4 a_n469_n962# vss 3.37fF
+C5 vdd vss 162.65fF
+.ends
+
+.subckt layout_opamp_2 vdd vss in1 in2 out
+X0 a_173_n2232# in1 a_n28_306# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X1 a_606_306# a_n28_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X2 a_n469_n962# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X3 a_n349_n973# a_n469_n962# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X4 out a_606_306# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X5 vdd a_n28_306# a_n28_306# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X6 vss a_n349_n973# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X7 vss a_n349_n973# a_n349_n973# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 a_606_306# in2 a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X9 a_n617_n951# a_n541_1558# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X10 a_n617_n951# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X11 vss a_n349_n973# a_173_n2232# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+C0 in2 vss 134.37fF
+C1 in1 vss 89.57fF
+C2 a_n349_n973# vss 3.86fF
+C3 out vss 71.02fF
+C4 a_n469_n962# vss 3.37fF
+C5 vdd vss 131.43fF
+.ends
+
+.subckt layout_opamp_3 vdd vss in1 in2 out
+X0 a_n55212_104034# vdd vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X1 a_n55064_104023# a_n55136_106543# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X2 a_n54944_104012# a_n55064_104023# vss sky130_fd_pr__res_generic_nd w=340000u l=2.494e+07u
+X3 out a_n53989_105291# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X4 a_n55212_104034# a_n55136_106543# vss sky130_fd_pr__res_generic_nd w=270000u l=2.492e+07u
+X5 a_n53989_105291# in2 a_n54422_102753# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X6 vss a_n54944_104012# a_n54422_102753# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.002e+07u l=1e+06u
+X7 vdd a_n54623_105291# a_n54623_105291# vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X8 vss a_n54944_104012# out vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=6.289e+07u l=1e+06u
+X9 a_n54422_102753# in1 a_n54623_105291# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.79e+06u l=1e+06u
+X10 a_n53989_105291# a_n54623_105291# vdd vdd sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+X11 vss a_n54944_104012# a_n54944_104012# vss sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.001e+07u l=1e+06u
+C0 in2 vss 214.82fF
+C1 in1 vss 166.10fF
+C2 a_n54944_104012# vss 3.86fF
+C3 out vss 166.10fF
+C4 a_n55064_104023# vss 3.37fF
+C5 vdd vss 152.94fF
+.ends
+
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[7] io_analog[8] io_analog[9]
++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xlayout_opamp io_analog[2] io_analog[0] io_analog[3] io_analog[4] io_analog[1] layout_opamp
+
+Xlayout_opamp_2 io_analog[7] io_analog[5] io_analog[8] io_analog[9] io_analog[6] layout_opamp_2
+
+Xlayout_opamp_3 vccd2 vssa2 gipo_analog[7] gipo_analog[8] io_analog[10] layout_opamp_3
+.ends
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 120000
index 0000000..48e5b4a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1 @@
+../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..a9c2027
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mprj_por
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+ rm -rf *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..6be9cd3
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment:
+
+* Pulling a pre-built docker image
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
+
+Run the following to pull the image:
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables:
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside :
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
+
+> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
new file mode 100644
index 0000000..5d0825f
--- /dev/null
+++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_por
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c
new file mode 100644
index 0000000..9a51fc5
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ // Configure mprj_io 10 and 25 as analog (digital in/out = off)
+ // Configure mprj_io 11, 12, 26, and 27 as digital output
+ // mprj_io 14 to 24 are analog pads and cannot be configured
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG;
+
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Block until end of test */
+ while (1);
+}
+
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v
new file mode 100644
index 0000000..39e4a36
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_por_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire [1:0] status;
+
+ // Signals Assignment
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Power supply for POR
+ assign mprj_io[18] = power3;
+
+ // Readback from POR (digital HV through analog pad connection)
+ assign status = {mprj_io[25], mprj_io[10]};
+
+ // Readback from POR (digital LV)
+ assign checkbits = {mprj_io[27:26], mprj_io[12:11]};
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_por.vcd");
+ $dumpvars(0, mprj_por_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(status == 2'h1);
+ $display("Monitor: mprj_por test started");
+ #100;
+ if (checkbits != 4'h9) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ wait(status == 2'h3);
+ #100;
+ if (checkbits != 4'h5) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ $display("Monitor: mprj_por test Passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #150000; // Need time to run the managment SoC setup.
+ power3 <= 1'b1; // Power up the 2nd POR.
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_por.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
new file mode 100644
index 0000000..d318fba
--- /dev/null
+++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module example_por(
+`ifdef USE_POWER_PINS
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
new file mode 100644
index 0000000..062a873
--- /dev/null
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ // Use behavorial model with gate-level simulation
+ `include "rtl/user_analog_project_wrapper.v"
+ `include "rtl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
new file mode 100644
index 0000000..94412da
--- /dev/null
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,221 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "example_por.v"
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+
+ wire isupply; // Independent 3.3V supply
+ wire io16, io15, io12, io11;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_out[12:11] = {io12, io11};
+ assign io_oeb[12:11] = {vssd1, vssd1};
+
+ assign io_out[16:15] = {io16, io15};
+ assign io_oeb[16:15] = {vssd1, vssd1};
+
+ // IRQ
+ assign irq = 3'b000; // Unused
+
+ // LA --- unused (no need to connect to anything)
+ // assign la_data_out = {128{1'b0}}; // Unused
+
+ // Instantiate the POR. Connect the digital power to user area 1
+ // VCCD, and connect the analog power to user area 1 VDDA.
+
+ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
+ // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
+
+ example_por por1 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vdda1),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[3]), // 3.3V domain output
+ .porb_l(io11), // 1.8V domain output
+ .por_l(io12) // 1.8V domain output
+ );
+
+ // Instantiate 2nd POR with the analog power supply on one of the
+ // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
+ // pad with io_clamp_high/low[0].
+
+ `ifdef USE_POWER_PINS
+ assign isupply = io_analog[4];
+ assign io_clamp_high[0] = isupply;
+ assign io_clamp_low[0] = vssa1;
+
+ // Tie off remaining clamps
+ assign io_clamp_high[2:1] = vssa1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+
+ // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
+ // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
+
+ example_por por2 (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(isupply),
+ .vdd1v8(vccd1),
+ .vss(vssa1),
+ `endif
+ .porb_h(gpio_analog[7]), // 3.3V domain output
+ .porb_l(io15), // 1.8V domain output
+ .por_l(io16) // 1.8V domain output
+ );
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
new file mode 100644
index 0000000..7a73f76
--- /dev/null
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(io_clamp_high),
+ .io_clamp_low(io_clamp_low),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/xschem/.spiceinit b/xschem/.spiceinit
new file mode 100644
index 0000000..e6a73aa
--- /dev/null
+++ b/xschem/.spiceinit
@@ -0,0 +1,5 @@
+* ngspice initialization for sky130
+* assert BSIM compatibility mode with "nf" vs. "W"
+set ngbehavior=hsa
+* "nomodcheck" speeds up loading time
+set ng_nomodcheck
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
new file mode 100644
index 0000000..d9b605c
--- /dev/null
+++ b/xschem/analog_wrapper_tb.sch
@@ -0,0 +1,76 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 300 -290 510 -290 { lab=#net1}
+N 590 -290 590 -250 { lab=#net1}
+N 300 -250 430 -250 { lab=GND}
+N 510 -250 510 -150 { lab=GND}
+N 510 -150 780 -150 { lab=GND}
+N 780 -190 780 -150 { lab=GND}
+N 690 -190 690 -150 { lab=GND}
+N 590 -190 590 -150 { lab=GND}
+N 300 -210 400 -210 { lab=#net2}
+N 480 -270 480 -210 { lab=#net2}
+N 480 -270 690 -270 { lab=#net2}
+N 690 -270 690 -250 { lab=#net2}
+N 300 10 450 10 { lab=#net3}
+N 850 -270 850 0 { lab=io_analog[4]}
+N 780 -270 850 -270 { lab=io_analog[4]}
+N 780 -270 780 -250 { lab=io_analog[4]}
+N 300 30 470 30 { lab=#net4}
+N 300 50 410 50 { lab=#net5}
+N 530 10 660 10 { lab=io_analog[10:0]}
+N 510 -290 590 -290 { lab=#net1}
+N 430 -250 510 -250 { lab=GND}
+N 400 -210 480 -210 { lab=#net2}
+N 460 10 530 10 { lab=io_analog[10:0]}
+N 670 0 850 -0 { lab=io_analog[4]}
+N 300 -270 400 -270 { lab=#net8}
+N 300 -230 400 -230 { lab=#net9}
+N 300 -190 400 -190 { lab=#net10}
+N 300 -190 400 -190 { lab=#net10}
+N 300 -170 400 -170 { lab=#net11}
+N 290 -150 390 -150 { lab=#net12}
+N 290 -130 390 -130 { lab=#net13}
+N 290 -110 390 -110 { lab=#net14}
+N 300 -90 400 -90 { lab=#net15}
+N 300 -10 400 -10 { lab=#net16}
+N 300 70 400 70 { lab=#net17}
+N -60 -290 -0 -290 { lab=#net18}
+N -60 -270 0 -270 { lab=#net19}
+N -60 -250 0 -250 { lab=#net20}
+N -60 -230 0 -230 { lab=#net21}
+N -60 -210 0 -210 { lab=#net22}
+N -60 -210 0 -210 { lab=#net22}
+N -60 -190 0 -190 { lab=#net23}
+N -60 -190 0 -190 { lab=#net23}
+N -60 -170 0 -170 { lab=#net24}
+N -60 -150 0 -150 { lab=#net25}
+N -60 -130 0 -130 { lab=#net26}
+N -60 -110 0 -110 { lab=#net27}
+N -60 -90 0 -90 { lab=#net28}
+N -60 -70 0 -70 { lab=#net29}
+N -60 -50 0 -50 { lab=#net30}
+N 300 -70 400 -70 {}
+N 300 -50 400 -50 {}
+N 300 -30 400 -30 {}
+C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1}
+C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
+C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
+C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
+C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
+C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
+C {devices/code.sym} 920 -130 0 0 {name=TT_MODELS only_toplevel=false
+format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt
+.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
+C {devices/code_shown.sym} 1100 -130 0 0 {name=s1
+only_toplevel=false
+value=".control
+tran 10u 20m
+plot V(\\"io_out[11]\\") V(\\"io_out[12]\\") V(\\"io_out[15]\\") V(\\"io_out[16]\\")
++ V(\\"gpio_analog[3]\\") V(\\"gpio_analog[7]\\")
+.endc"}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
new file mode 100644
index 0000000..523a509
--- /dev/null
+++ b/xschem/analog_wrapper_tb.spice
@@ -0,0 +1,283 @@
+**.subckt analog_wrapper_tb
+x1 net1 net6 GND net7 net2 net8 net9 net10 net16 net17 net18 net19 net20 net21[3] net21[2] net21[1]
++ net21[0] net22[31] net22[30] net22[29] net22[28] net22[27] net22[26] net22[25] net22[24] net22[23] net22[22]
++ net22[21] net22[20] net22[19] net22[18] net22[17] net22[16] net22[15] net22[14] net22[13] net22[12] net22[11]
++ net22[10] net22[9] net22[8] net22[7] net22[6] net22[5] net22[4] net22[3] net22[2] net22[1] net22[0] net23[31]
++ net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22] net23[21] net23[20]
++ net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11] net23[10] net23[9]
++ net23[8] net23[7] net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net11 net12[31] net12[30]
++ net12[29] net12[28] net12[27] net12[26] net12[25] net12[24] net12[23] net12[22] net12[21] net12[20] net12[19]
++ net12[18] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10] net12[9] net12[8]
++ net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net24[127] net24[126] net24[125]
++ net24[124] net24[123] net24[122] net24[121] net24[120] net24[119] net24[118] net24[117] net24[116] net24[115]
++ net24[114] net24[113] net24[112] net24[111] net24[110] net24[109] net24[108] net24[107] net24[106] net24[105]
++ net24[104] net24[103] net24[102] net24[101] net24[100] net24[99] net24[98] net24[97] net24[96] net24[95]
++ net24[94] net24[93] net24[92] net24[91] net24[90] net24[89] net24[88] net24[87] net24[86] net24[85] net24[84]
++ net24[83] net24[82] net24[81] net24[80] net24[79] net24[78] net24[77] net24[76] net24[75] net24[74] net24[73]
++ net24[72] net24[71] net24[70] net24[69] net24[68] net24[67] net24[66] net24[65] net24[64] net24[63] net24[62]
++ net24[61] net24[60] net24[59] net24[58] net24[57] net24[56] net24[55] net24[54] net24[53] net24[52] net24[51]
++ net24[50] net24[49] net24[48] net24[47] net24[46] net24[45] net24[44] net24[43] net24[42] net24[41] net24[40]
++ net24[39] net24[38] net24[37] net24[36] net24[35] net24[34] net24[33] net24[32] net24[31] net24[30] net24[29]
++ net24[28] net24[27] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20] net24[19] net24[18]
++ net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9] net24[8] net24[7]
++ net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net13[127] net13[126] net13[125] net13[124]
++ net13[123] net13[122] net13[121] net13[120] net13[119] net13[118] net13[117] net13[116] net13[115] net13[114]
++ net13[113] net13[112] net13[111] net13[110] net13[109] net13[108] net13[107] net13[106] net13[105] net13[104]
++ net13[103] net13[102] net13[101] net13[100] net13[99] net13[98] net13[97] net13[96] net13[95] net13[94]
++ net13[93] net13[92] net13[91] net13[90] net13[89] net13[88] net13[87] net13[86] net13[85] net13[84] net13[83]
++ net13[82] net13[81] net13[80] net13[79] net13[78] net13[77] net13[76] net13[75] net13[74] net13[73] net13[72]
++ net13[71] net13[70] net13[69] net13[68] net13[67] net13[66] net13[65] net13[64] net13[63] net13[62] net13[61]
++ net13[60] net13[59] net13[58] net13[57] net13[56] net13[55] net13[54] net13[53] net13[52] net13[51] net13[50]
++ net13[49] net13[48] net13[47] net13[46] net13[45] net13[44] net13[43] net13[42] net13[41] net13[40] net13[39]
++ net13[38] net13[37] net13[36] net13[35] net13[34] net13[33] net13[32] net13[31] net13[30] net13[29] net13[28]
++ net13[27] net13[26] net13[25] net13[24] net13[23] net13[22] net13[21] net13[20] net13[19] net13[18] net13[17]
++ net13[16] net13[15] net13[14] net13[13] net13[12] net13[11] net13[10] net13[9] net13[8] net13[7] net13[6]
++ net13[5] net13[4] net13[3] net13[2] net13[1] net13[0] net25[127] net25[126] net25[125] net25[124] net25[123]
++ net25[122] net25[121] net25[120] net25[119] net25[118] net25[117] net25[116] net25[115] net25[114] net25[113]
++ net25[112] net25[111] net25[110] net25[109] net25[108] net25[107] net25[106] net25[105] net25[104] net25[103]
++ net25[102] net25[101] net25[100] net25[99] net25[98] net25[97] net25[96] net25[95] net25[94] net25[93]
++ net25[92] net25[91] net25[90] net25[89] net25[88] net25[87] net25[86] net25[85] net25[84] net25[83] net25[82]
++ net25[81] net25[80] net25[79] net25[78] net25[77] net25[76] net25[75] net25[74] net25[73] net25[72] net25[71]
++ net25[70] net25[69] net25[68] net25[67] net25[66] net25[65] net25[64] net25[63] net25[62] net25[61] net25[60]
++ net25[59] net25[58] net25[57] net25[56] net25[55] net25[54] net25[53] net25[52] net25[51] net25[50] net25[49]
++ net25[48] net25[47] net25[46] net25[45] net25[44] net25[43] net25[42] net25[41] net25[40] net25[39] net25[38]
++ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27]
++ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16]
++ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5]
++ net25[4] net25[3] net25[2] net25[1] net25[0] net26[26] net26[25] net26[24] net26[23] net26[22] net26[21]
++ net26[20] net26[19] net26[18] net26[17] net26[16] net26[15] net26[14] net26[13] net26[12] net26[11] net26[10]
++ net26[9] net26[8] net26[7] net26[6] net26[5] net26[4] net26[3] net26[2] net26[1] net26[0] net27[26]
++ net27[25] net27[24] net27[23] net27[22] net27[21] net27[20] net27[19] net27[18] net27[17] net27[16] net27[15]
++ net27[14] net27[13] net27[12] net27[11] net27[10] net27[9] net27[8] net27[7] net27[6] net27[5] net27[4]
++ net27[3] net27[2] net27[1] net27[0] net29[26] net29[25] net29[24] net29[23] net29[22] net29[21] net29[20]
++ net29[19] net29[18] net29[17] net29[16] net29[15] net29[14] net29[13] net29[12] net29[11] net29[10] net29[9]
++ net29[8] net29[7] net29[6] net29[5] net29[4] net29[3] net29[2] net29[1] net29[0] net30[26] net30[25]
++ net30[24] net30[23] net30[22] net30[21] net30[20] net30[19] net30[18] net30[17] net30[16] net30[15] net30[14]
++ net30[13] net30[12] net30[11] net30[10] net30[9] net30[8] net30[7] net30[6] net30[5] net30[4] net30[3]
++ net30[2] net30[1] net30[0] net31[17] net31[16] net31[15] net31[14] net31[13] net31[12] net31[11] net31[10]
++ net31[9] net31[8] net31[7] net31[6] net31[5] net31[4] net31[3] net31[2] net31[1] net31[0] net14[17]
++ net14[16] net14[15] net14[14] net14[13] net14[12] net14[11] net14[10] net14[9] net14[8] net14[7] net14[6]
++ net14[5] net14[4] net14[3] net14[2] net14[1] net14[0] net3[10] net3[9] net3[8] net3[7] net3[6] net3[5]
++ net3[4] net3[3] net3[2] net3[1] net3[0] net4[2] net4[1] net4[0] net5[2] net5[1] net5[0] net28 net15[2]
++ net15[1] net15[0] user_analog_project_wrapper
+V1 net1 GND PWL(0.0 0 400u 0 5.4m 3.3)
+V2 net2 GND PWL(0.0 0 300u 0 5.3 1.8)
+V3 io_analog[4] GND PWL(0.0 0 100u 0 5m 3.3)
+**** begin user architecture code
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
+.control
+tran 10u 20m
+plot V("io_out[11]") V("io_out[12]") V("io_out[15]") V("io_out[16]") V("gpio_analog[3]")
++ V("gpio_analog[7]")
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: user_analog_project_wrapper.sym # of pins=32
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
++ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
++ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
++ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
++ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
++ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
++ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
++ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
++ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
++ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
++ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
++ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
++ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
++ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
++ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
++ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
++ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
++ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
++ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
++ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
++ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
++ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
++ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
++ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
++ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
++ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
++ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
++ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
++ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
++ user_irq[2] user_irq[1] user_irq[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
+x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
+R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1
+R8 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=0.56 L=0.49 m=1
+R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=0.56 L=0.31 m=1
+R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=0.56 L=0.58 m=1
+R12 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=0.56 L=0.6 m=1
+.ends
+
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/current_test.spice b/xschem/current_test.spice
new file mode 100644
index 0000000..8e4162d
--- /dev/null
+++ b/xschem/current_test.spice
@@ -0,0 +1,86 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Simple POR circuit for Caravel current mirror test
+*-------------------------------------------------------------------
+
+.param mc_mm_switch=0
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+* Note: 20 resistors of length 25um connected in series
+Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
+Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149
+
+* voltage sources at 0V for measuring current in each branch
+
+Vm1 vssm1 vss DC=0
+Vm2 vdda vddm2 DC=0
+Vm3 vdda vddm3 DC=0
+Vm4 vssm4 vss DC=0
+Vm5 vssm5 vss DC=0
+Vm6 vdda vddm6 DC=0
+Vm7 vdda vddm7 DC=0
+
+* D G S B
+Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
+Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
+Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
+
+* Check branch currents in each mirror branch.
+* 1st branch should be 240nA
+* 2nd branch should be 30nA
+* 3rd branch should be 4.3nA
+* 4th branch should be 612pA
+*
+* Result: vin sits at 0.7590 (close to 0.7575 target)
+* I(Vm1/2) = 202.80 nA
+* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77
+* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70
+* I(Vm7) = 0.67 nA (should be /7) actually /6.80
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.01
+Rload vcap vss 1MEG
+*----------------------------
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+op
+print V(vin)
+print I(Vm1)
+print I(Vm2)
+print I(Vm3)
+print I(Vm4)
+print I(Vm5)
+print I(Vm6)
+print I(Vm7)
+.endc
+
+.end
+
diff --git a/xschem/example_por.sch b/xschem/example_por.sch
new file mode 100644
index 0000000..cf6e0c3
--- /dev/null
+++ b/xschem/example_por.sch
@@ -0,0 +1,297 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+L 4 3370 -60 3390 -60 {}
+L 4 3390 -60 3390 80 {}
+L 4 3370 80 3390 80 {}
+T {Current step-down mirror} 2270 140 0 0 0.4 0.4 {}
+T {Charge accumulator} 2650 140 0 0 0.4 0.4 {}
+T {Voltage divider} 1860 140 0 0 0.4 0.4 {}
+T {Schmitt trigger} 2930 -200 0 0 0.4 0.4 {}
+T {150 / 650 * 3.3V = 0.76V} 1860 180 0 0 0.4 0.4 {}
+T {step down 8x} 2130 -430 0 0 0.4 0.4 {}
+T {step down 7x} 2330 80 0 0 0.4 0.4 {}
+T {step down 7x} 2520 -430 0 0 0.4 0.4 {}
+T {1.8V domain outputs} 3400 0 0 0 0.4 0.4 {}
+T {3.3V domain output} 3410 -140 0 0 0.4 0.4 {}
+T {392 : 1} 2270 180 0 0 0.4 0.4 {}
+T {Simple power-on-reset circuit
+calibrated to 500us nominal delay
+no temperature compensation} 1950 -570 0 0 0.6 0.6 {}
+N 2500 -310 2500 -270 { lab=#net1}
+N 2500 -210 2500 -100 { lab=#net2}
+N 2300 -40 2300 20 { lab=#net3}
+N 2300 80 2300 110 { lab=vss}
+N 2360 110 2500 110 { lab=vss}
+N 2500 80 2500 110 { lab=vss}
+N 2400 50 2460 50 { lab=#net3}
+N 2360 -400 2500 -400 { lab=vdd3v3}
+N 2500 -400 2500 -370 { lab=vdd3v3}
+N 2500 -400 2790 -400 { lab=vdd3v3}
+N 2300 -10 2370 -10 { lab=#net3}
+N 2370 -10 2370 50 { lab=#net3}
+N 2500 -290 2570 -290 { lab=#net1}
+N 2570 -340 2570 -290 { lab=#net1}
+N 2540 -340 2570 -340 { lab=#net1}
+N 2500 -190 2570 -190 { lab=#net2}
+N 2570 -240 2570 -190 { lab=#net2}
+N 2540 -240 2570 -240 { lab=#net2}
+N 2240 110 2360 110 { lab=vss}
+N 2500 110 2630 110 { lab=vss}
+N 2500 50 2630 50 { lab=vss}
+N 2110 110 2240 110 { lab=vss}
+N 1930 60 1930 110 { lab=vss}
+N 1930 -160 1930 0 { lab=#net4}
+N 1930 -400 1930 -220 { lab=vdd3v3}
+N 2110 -400 2360 -400 { lab=vdd3v3}
+N 1880 -190 1910 -190 { lab=vss}
+N 1880 -190 1880 110 { lab=vss}
+N 1880 110 1930 110 { lab=vss}
+N 1880 30 1910 30 { lab=vss}
+N 2300 -310 2300 -270 { lab=#net5}
+N 2300 -400 2300 -370 { lab=vdd3v3}
+N 2300 -140 2300 -100 { lab=#net3}
+N 2340 50 2400 50 { lab=#net3}
+N 2300 -210 2300 -140 { lab=#net3}
+N 2100 80 2100 110 { lab=vss}
+N 2100 110 2110 110 { lab=vss}
+N 2050 50 2060 50 { lab=#net4}
+N 2050 -70 2050 50 { lab=#net4}
+N 1930 -70 2050 -70 { lab=#net4}
+N 1930 -400 2110 -400 { lab=vdd3v3}
+N 2100 -400 2100 -370 { lab=vdd3v3}
+N 2100 -310 2100 -270 { lab=#net6}
+N 2100 -210 2100 20 { lab=#net7}
+N 2100 50 2300 50 { lab=vss}
+N 2200 50 2200 110 { lab=vss}
+N 2140 -240 2260 -240 { lab=#net7}
+N 2140 -340 2260 -340 { lab=#net6}
+N 2100 -290 2180 -290 { lab=#net6}
+N 2180 -340 2180 -290 { lab=#net6}
+N 2100 -180 2180 -180 { lab=#net7}
+N 2180 -240 2180 -180 { lab=#net7}
+N 1930 -240 2100 -240 { lab=vdd3v3}
+N 1930 -340 2100 -340 { lab=vdd3v3}
+N 1930 110 2100 110 { lab=vss}
+N 2300 -240 2500 -240 { lab=vdd3v3}
+N 2300 -340 2500 -340 { lab=vdd3v3}
+N 2400 -340 2400 -240 { lab=vdd3v3}
+N 2400 -400 2400 -340 { lab=vdd3v3}
+N 2570 -240 2650 -240 { lab=#net2}
+N 2570 -340 2650 -340 { lab=#net1}
+N 2690 -400 2690 -370 { lab=vdd3v3}
+N 2790 -400 2790 -340 { lab=vdd3v3}
+N 2690 -340 2790 -340 { lab=vdd3v3}
+N 2690 -240 2790 -240 { lab=vdd3v3}
+N 2790 -340 2790 -240 { lab=vdd3v3}
+N 2690 -310 2690 -270 { lab=#net8}
+N 2690 -210 2690 -150 { lab=#net9}
+N 1830 30 1880 30 { lab=vss}
+N 1810 60 1810 110 { lab=vss}
+N 1810 110 1880 110 { lab=vss}
+N 1810 -70 1810 0 { lab=vss}
+N 1810 -70 1880 -70 { lab=vss}
+N 2690 -150 2690 -70 { lab=#net9}
+N 2820 -130 2820 -70 { lab=#net9}
+N 2690 -130 2820 -130 { lab=#net9}
+N 2630 110 2820 110 { lab=vss}
+N 2820 -10 2820 110 { lab=vss}
+N 2690 -10 2690 110 { lab=vss}
+N 2820 -130 2980 -130 { lab=#net9}
+N 3060 -130 3130 -130 { lab=#net10}
+N 3090 -130 3090 60 { lab=#net10}
+N 3090 60 3130 60 { lab=#net10}
+N 3090 -40 3130 -40 { lab=#net10}
+N 3210 -130 3300 -130 { lab=porb_h}
+N 3210 -40 3300 -40 { lab=porb_l}
+N 3210 60 3300 60 { lab=por_l}
+N 2790 -400 2840 -400 { lab=vdd3v3}
+N 2820 110 2870 110 { lab=vss}
+N 2630 50 2690 50 { lab=vss}
+N 2300 -100 2300 -40 { lab=#net3}
+N 2500 -100 2500 -30 { lab=#net2}
+N 2500 -30 2500 20 { lab=#net2}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2480 50 0 0 {name=M2
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 -190 0 0 {name=R1
+L=500
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -340 0 0 {name=M4
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2320 50 0 1 {name=M5
+L=0.8
+W=14
+nf=7
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 30 0 0 {name=R2
+L=150
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -240 0 1 {name=M7
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -340 0 1 {name=M8
+L=0.8
+W=14
+nf=7
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2080 50 0 0 {name=M10
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -240 0 1 {name=M9
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -340 0 1 {name=M11
+L=0.8
+W=16
+nf=8
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -340 0 0 {name=M12
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -240 0 0 {name=M13
+L=0.8
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_g5v0d10v5
+spiceprefix=X
+}
+C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1810 30 0 1 {name=R3
+L=25
+model=res_xhigh_po_0p69
+spiceprefix=X
+mult=2}
+C {sky130_stdcells/buf_8.sym} 3170 -130 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
+C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt }
+C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
+C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
+C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
+C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
+C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
+C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
diff --git a/xschem/example_por.sym b/xschem/example_por.sym
new file mode 100644
index 0000000..e3875f5
--- /dev/null
+++ b/xschem/example_por.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -60 130 -60 {}
+L 4 -130 60 130 60 {}
+L 4 -130 -60 -130 60 {}
+L 4 130 -60 130 60 {}
+L 4 130 -30 150 -30 {}
+L 4 130 0 150 0 {}
+L 4 130 30 150 30 {}
+L 7 -30 -80 -30 -60 {}
+L 7 30 -80 30 -60 {}
+L 7 0 60 0 80 {}
+B 5 -32.5 -82.5 -27.5 -77.5 {name=vdd3v3 dir=inout }
+B 5 27.5 -82.5 32.5 -77.5 {name=vdd1v8 dir=inout }
+B 5 147.5 -32.5 152.5 -27.5 {name=porb_h dir=out }
+B 5 147.5 -2.5 152.5 2.5 {name=porb_l dir=out }
+B 5 147.5 27.5 152.5 32.5 {name=por_l dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
+T {@symname} -47.5 -6 0 0 0.3 0.3 {}
+T {@name} -25 18 0 0 0.2 0.2 {}
+T {vdd3v3} -15 -54 0 1 0.2 0.2 {}
+T {vdd1v8} 55 -54 0 1 0.2 0.2 {}
+T {porb_h} 125 -34 0 1 0.2 0.2 {}
+T {porb_l} 125 -4 0 1 0.2 0.2 {}
+T {por_l} 125 26 0 1 0.2 0.2 {}
+T {vss} 5 46 0 1 0.2 0.2 {}
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
new file mode 100644
index 0000000..a24d814
--- /dev/null
+++ b/xschem/example_por_tb.sch
@@ -0,0 +1,45 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {}
+N -280 60 -10 60 { lab=GND}
+N -540 0 -540 60 { lab=GND}
+N -330 0 -330 60 { lab=GND}
+N -330 -100 -330 -60 { lab=vdd3v3}
+N -330 -110 -330 -100 { lab=vdd3v3}
+N -210 -110 -40 -110 { lab=vdd3v3}
+N -40 -110 -40 -100 { lab=vdd3v3}
+N -540 -130 -540 -60 { lab=vdd1v8}
+N -280 -130 20 -130 { lab=vdd1v8}
+N 20 -130 20 -100 { lab=vdd1v8}
+N 140 -50 180 -50 { lab=porb_h}
+N 140 -20 180 -20 { lab=porb_l}
+N 140 10 180 10 { lab=por_l}
+N -340 -110 -330 -110 { lab=vdd3v3}
+N -500 -130 -490 -130 { lab=vdd1v8}
+N -540 -130 -500 -130 { lab=vdd1v8}
+N -560 -130 -540 -130 { lab=vdd1v8}
+N -540 60 -490 60 { lab=GND}
+N -490 -130 -280 -130 { lab=vdd1v8}
+N -490 60 -330 60 { lab=GND}
+N -330 60 -280 60 { lab=GND}
+N -330 -110 -210 -110 { lab=vdd3v3}
+C {example_por.sym} -10 -20 0 0 {name=x1}
+C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
+C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
+C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
+C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
+C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
+C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
+C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
+C {devices/code.sym} -470 140 0 0 {name=TT_MODELS only_toplevel=false
+format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt
+.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
+C {devices/code_shown.sym} -320 160 0 0 {name=s2 only_toplevel=false value=".control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc"}
diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice
new file mode 100644
index 0000000..fa82f74
--- /dev/null
+++ b/xschem/example_por_tb.spice
@@ -0,0 +1,78 @@
+**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
+*.opin vdd3v3
+*.opin vdd1v8
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
+V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
+V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
+**** begin user architecture code
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
+.control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por_tb.spice.orig
new file mode 100644
index 0000000..069c74d
--- /dev/null
+++ b/xschem/example_por_tb.spice.orig
@@ -0,0 +1,88 @@
+**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
+.param mc_switch=0
+*.opin vdd3v3
+*.opin vdd1v8
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
+V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
+V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
+**** begin user architecture code
+
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+
+.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+
+.control
+tran 1u 20m
+plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
+.endc
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net11 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 net11 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net5 net9 net7 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net1 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net6 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
+XM3 net3 net5 net1 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net7 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net5 net5 net4 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net6 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
+XM7 net3 net3 net2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net2 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net9 net6 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net9 net9 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net8 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net10 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net11 net3 net10 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
+x2 net12 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net12 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net12 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net11 vss vss vdd3v3 vdd3v3 net12 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/test.data b/xschem/test.data
new file mode 100644
index 0000000..c9cde37
--- /dev/null
+++ b/xschem/test.data
@@ -0,0 +1,101 @@
+ 7.00000000e-01 -8.93059159e-08 7.00000000e-01 7.00000000e-01
+ 7.01000000e-01 -9.08452852e-08 7.01000000e-01 7.01000000e-01
+ 7.02000000e-01 -9.24385447e-08 7.02000000e-01 7.02000000e-01
+ 7.03000000e-01 -9.40459956e-08 7.03000000e-01 7.03000000e-01
+ 7.04000000e-01 -9.56814959e-08 7.04000000e-01 7.04000000e-01
+ 7.05000000e-01 -9.73455368e-08 7.05000000e-01 7.05000000e-01
+ 7.06000000e-01 -9.90386085e-08 7.06000000e-01 7.06000000e-01
+ 7.07000000e-01 -1.00761227e-07 7.07000000e-01 7.07000000e-01
+ 7.08000000e-01 -1.02513882e-07 7.08000000e-01 7.08000000e-01
+ 7.09000000e-01 -1.04297110e-07 7.09000000e-01 7.09000000e-01
+ 7.10000000e-01 -1.06111443e-07 7.10000000e-01 7.10000000e-01
+ 7.11000000e-01 -1.07957415e-07 7.11000000e-01 7.11000000e-01
+ 7.12000000e-01 -1.09835552e-07 7.12000000e-01 7.12000000e-01
+ 7.13000000e-01 -1.11746436e-07 7.13000000e-01 7.13000000e-01
+ 7.14000000e-01 -1.13690603e-07 7.14000000e-01 7.14000000e-01
+ 7.15000000e-01 -1.15668634e-07 7.15000000e-01 7.15000000e-01
+ 7.16000000e-01 -1.17681129e-07 7.16000000e-01 7.16000000e-01
+ 7.17000000e-01 -1.19728657e-07 7.17000000e-01 7.17000000e-01
+ 7.18000000e-01 -1.21811839e-07 7.18000000e-01 7.18000000e-01
+ 7.19000000e-01 -1.23931259e-07 7.19000000e-01 7.19000000e-01
+ 7.20000000e-01 -1.26087554e-07 7.20000000e-01 7.20000000e-01
+ 7.21000000e-01 -1.28281358e-07 7.21000000e-01 7.21000000e-01
+ 7.22000000e-01 -1.30513286e-07 7.22000000e-01 7.22000000e-01
+ 7.23000000e-01 -1.32784003e-07 7.23000000e-01 7.23000000e-01
+ 7.24000000e-01 -1.35094165e-07 7.24000000e-01 7.24000000e-01
+ 7.25000000e-01 -1.37444453e-07 7.25000000e-01 7.25000000e-01
+ 7.26000000e-01 -1.39835535e-07 7.26000000e-01 7.26000000e-01
+ 7.27000000e-01 -1.42268085e-07 7.27000000e-01 7.27000000e-01
+ 7.28000000e-01 -1.44742842e-07 7.28000000e-01 7.28000000e-01
+ 7.29000000e-01 -1.47260486e-07 7.29000000e-01 7.29000000e-01
+ 7.30000000e-01 -1.49821761e-07 7.30000000e-01 7.30000000e-01
+ 7.31000000e-01 -1.52427364e-07 7.31000000e-01 7.31000000e-01
+ 7.32000000e-01 -1.55078077e-07 7.32000000e-01 7.32000000e-01
+ 7.33000000e-01 -1.57774611e-07 7.33000000e-01 7.33000000e-01
+ 7.34000000e-01 -1.60517775e-07 7.34000000e-01 7.34000000e-01
+ 7.35000000e-01 -1.63308337e-07 7.35000000e-01 7.35000000e-01
+ 7.36000000e-01 -1.66147061e-07 7.36000000e-01 7.36000000e-01
+ 7.37000000e-01 -1.69034765e-07 7.37000000e-01 7.37000000e-01
+ 7.38000000e-01 -1.71972266e-07 7.38000000e-01 7.38000000e-01
+ 7.39000000e-01 -1.74960357e-07 7.39000000e-01 7.39000000e-01
+ 7.40000000e-01 -1.77999888e-07 7.40000000e-01 7.40000000e-01
+ 7.41000000e-01 -1.81091703e-07 7.41000000e-01 7.41000000e-01
+ 7.42000000e-01 -1.84236664e-07 7.42000000e-01 7.42000000e-01
+ 7.43000000e-01 -1.87435634e-07 7.43000000e-01 7.43000000e-01
+ 7.44000000e-01 -1.90689493e-07 7.44000000e-01 7.44000000e-01
+ 7.45000000e-01 -1.93999127e-07 7.45000000e-01 7.45000000e-01
+ 7.46000000e-01 -1.97365464e-07 7.46000000e-01 7.46000000e-01
+ 7.47000000e-01 -2.00789378e-07 7.47000000e-01 7.47000000e-01
+ 7.48000000e-01 -2.04271837e-07 7.48000000e-01 7.48000000e-01
+ 7.49000000e-01 -2.07813739e-07 7.49000000e-01 7.49000000e-01
+ 7.50000000e-01 -2.11416073e-07 7.50000000e-01 7.50000000e-01
+ 7.51000000e-01 -2.15079797e-07 7.51000000e-01 7.51000000e-01
+ 7.52000000e-01 -2.18805863e-07 7.52000000e-01 7.52000000e-01
+ 7.53000000e-01 -2.22595278e-07 7.53000000e-01 7.53000000e-01
+ 7.54000000e-01 -2.26449036e-07 7.54000000e-01 7.54000000e-01
+ 7.55000000e-01 -2.30368144e-07 7.55000000e-01 7.55000000e-01
+ 7.56000000e-01 -2.34353630e-07 7.56000000e-01 7.56000000e-01
+ 7.57000000e-01 -2.38406548e-07 7.57000000e-01 7.57000000e-01
+ 7.58000000e-01 -2.42527913e-07 7.58000000e-01 7.58000000e-01
+ 7.59000000e-01 -2.46718795e-07 7.59000000e-01 7.59000000e-01
+ 7.60000000e-01 -2.50980278e-07 7.60000000e-01 7.60000000e-01
+ 7.61000000e-01 -2.55313430e-07 7.61000000e-01 7.61000000e-01
+ 7.62000000e-01 -2.59719344e-07 7.62000000e-01 7.62000000e-01
+ 7.63000000e-01 -2.64199148e-07 7.63000000e-01 7.63000000e-01
+ 7.64000000e-01 -2.68753946e-07 7.64000000e-01 7.64000000e-01
+ 7.65000000e-01 -2.73384860e-07 7.65000000e-01 7.65000000e-01
+ 7.66000000e-01 -2.78093044e-07 7.66000000e-01 7.66000000e-01
+ 7.67000000e-01 -2.82879650e-07 7.67000000e-01 7.67000000e-01
+ 7.68000000e-01 -2.87745826e-07 7.68000000e-01 7.68000000e-01
+ 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01
+ 7.70000000e-01 -2.97721660e-07 7.70000000e-01 7.70000000e-01
+ 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01
+ 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01
+ 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01
+ 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01
+ 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01
+ 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01
+ 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01
+ 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01
+ 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01
+ 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01
+ 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01
+ 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01
+ 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01
+ 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01
+ 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01
+ 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01
+ 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01
+ 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01
+ 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01
+ 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01
+ 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01
+ 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01
+ 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01
+ 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01
+ 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01
+ 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01
+ 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01
+ 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01
+ 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01
+ 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01
diff --git a/xschem/threshold_test_tb.spice b/xschem/threshold_test_tb.spice
new file mode 100644
index 0000000..3e9804c
--- /dev/null
+++ b/xschem/threshold_test_tb.spice
@@ -0,0 +1,46 @@
+*---------------------------------------------------------------------------
+* SPDX-FileCopyrightText: 2020 Efabless Corporation
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*---------------------------------------------------------------------------
+* Threshold test for POR circuit
+* Determine gate voltage at which the HV NFET draws 240nA nominal
+*
+* Result: 0.7575V
+*-------------------------------------------------------------------
+
+.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+*----------------------------
+* Testbench circuit
+*----------------------------
+Rtest vdda mir1 1MEG
+Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8
+
+Vgate vin vss DC=0
+Vpwr vdda vss DC=3.3
+Rgnd vss 0 0.1
+
+*----------------------------
+* Testbench control
+*----------------------------
+.control
+* DC sweep from 0.7 to 0.8V
+dc Vgate 0.7 0.8 0.001
+wrdata test.data Vpwr#branch vin
+
+.endc
+
+.end
+
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
new file mode 100644
index 0000000..e3cbcec
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sch
@@ -0,0 +1,180 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 3830 -460 3830 -390 { lab=vdda1}
+N 3730 -460 3830 -460 { lab=vdda1}
+N 3860 -230 3860 -180 { lab=vssa1}
+N 3770 -180 3860 -180 { lab=vssa1}
+N 3890 -460 3890 -390 { lab=vccd1}
+N 3890 -460 3960 -460 { lab=vccd1}
+N 3890 -130 3890 -60 { lab=vccd1}
+N 3890 -130 3950 -130 { lab=vccd1}
+N 3830 -130 3830 -60 { lab=io_analog[4]}
+N 3790 -130 3830 -130 { lab=io_analog[4]}
+N 3860 100 3860 150 { lab=vssa1}
+N 3800 150 3860 150 { lab=vssa1}
+N 4010 -10 4110 -10 { lab=gpio_analog[7]}
+N 4010 20 4110 20 { lab=io_out[15]}
+N 4010 50 4110 50 { lab=io_out[16]}
+N 4010 -340 4130 -340 { lab=gpio_analog[3]}
+N 4010 -310 4130 -310 { lab=io_out[11]}
+N 4010 -280 4130 -280 { lab=io_out[12]}
+N 3670 300 3670 340 { lab=io_clamp_low[2]}
+N 3670 400 3670 420 { lab=vssa1}
+N 3670 440 3670 460 { lab=io_clamp_high[2]}
+N 3670 520 3670 530 { lab=vssa1}
+N 3670 570 3670 590 { lab=io_clamp_low[1]}
+N 3670 650 3670 670 { lab=vssa1}
+N 4160 300 4160 330 { lab=io_clamp_high[1]}
+N 4160 390 4160 410 { lab=vssa1}
+N 4160 440 4160 460 { lab=io_clamp_low[0]}
+N 4160 520 4160 530 { lab=vssa1}
+N 4160 550 4160 560 { lab=io_clamp_high[0]}
+N 4160 620 4160 640 { lab=io_analog[4]}
+N 3630 300 3670 300 { lab=io_clamp_low[2]}
+N 3630 420 3670 420 { lab=vssa1}
+N 3630 440 3670 440 { lab=io_clamp_high[2]}
+N 3630 530 3670 530 { lab=vssa1}
+N 3630 570 3670 570 { lab=io_clamp_low[1]}
+N 3630 670 3670 670 { lab=vssa1}
+N 4130 300 4160 300 { lab=io_clamp_high[1]}
+N 4130 410 4160 410 { lab=vssa1}
+N 4130 440 4160 440 { lab=io_clamp_low[0]}
+N 4130 530 4160 530 { lab=vssa1}
+N 4130 550 4160 550 { lab=io_clamp_high[0]}
+N 4130 640 4160 640 { lab=io_analog[4]}
+N 3670 710 3670 750 { lab=io_oeb[12]}
+N 3670 810 3670 830 { lab=vssd1}
+N 3670 850 3670 870 { lab=io_oeb[16]}
+N 3670 930 3670 940 { lab=vssd1}
+N 4160 710 4160 740 { lab=io_oeb[11]}
+N 4160 800 4160 820 { lab=vssd1}
+N 4160 850 4160 870 { lab=#net1}
+N 4160 930 4160 940 { lab=vssd1}
+N 3630 710 3670 710 { lab=io_oeb[12]}
+N 3630 830 3670 830 { lab=vssd1}
+N 3630 850 3670 850 { lab=io_oeb[16]}
+N 3630 940 3670 940 { lab=vssd1}
+N 4130 710 4160 710 { lab=io_oeb[11]}
+N 4130 820 4160 820 { lab=vssd1}
+N 4130 850 4160 850 { lab=#net1}
+N 4130 940 4160 940 { lab=vssd1}
+C {example_por.sym} 3860 -310 0 0 {name=x1}
+C {example_por.sym} 3860 20 0 0 {name=x2}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
+C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
+C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
+C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
+C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
+C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
+C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
+C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 370 0 0 {name=R1
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 490 0 0 {name=R2
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 620 0 0 {name=R4
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 360 0 0 {name=R5
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 490 0 0 {name=R6
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 590 0 0 {name=R7
+W=11
+L=0.25
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]}
+C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]}
+C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]}
+C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]}
+C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]}
+C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]}
+C {devices/lab_pin.sym} 4130 640 0 0 {name=l24 sig_type=std_logic lab=io_analog[4]}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 780 0 0 {name=R8
+W=0.56
+L=0.49
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 3670 900 0 0 {name=R9
+W=0.56
+L=0.31
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 770 0 0 {name=R11
+W=0.56
+L=0.58
+model=res_generic_m3
+mult=1}
+C {sky130_fd_pr/res_generic_m1.sym} 4160 900 0 0 {name=R12
+W=0.56
+L=0.6
+model=res_generic_m3
+mult=1}
+C {devices/lab_pin.sym} 4130 850 0 0 {name=l25 sig_type=std_logic lab=io_oeb[15]}
+C {devices/lab_pin.sym} 3630 850 0 0 {name=l26 sig_type=std_logic lab=io_oeb[16]}
+C {devices/lab_pin.sym} 4130 710 0 0 {name=l27 sig_type=std_logic lab=io_oeb[11]}
+C {devices/lab_pin.sym} 3630 710 0 0 {name=l28 sig_type=std_logic lab=io_oeb[12]}
+C {devices/lab_pin.sym} 3630 830 0 0 {name=l29 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 3630 940 0 0 {name=l30 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 4130 820 0 0 {name=l31 sig_type=std_logic lab=vssd1}
+C {devices/lab_pin.sym} 4130 940 0 0 {name=l32 sig_type=std_logic lab=vssd1}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..0dc2d20
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.spice
@@ -0,0 +1,202 @@
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] io_in[26]
++ io_in[25] io_in[24] io_in[23] io_in[22] io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15]
++ io_in[14] io_in[13] io_in[12] io_in[11] io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4]
++ io_in[3] io_in[2] io_in[1] io_in[0] io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22]
++ io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14]
++ io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6]
++ io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] user_clock2 io_out[26] io_out[25]
++ io_out[24] io_out[23] io_out[22] io_out[21] io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15]
++ io_out[14] io_out[13] io_out[12] io_out[11] io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5]
++ io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22]
++ io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12]
++ io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2]
++ io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] gpio_analog[15] gpio_analog[14] gpio_analog[13]
++ gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] gpio_analog[8] gpio_analog[7] gpio_analog[6]
++ gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] gpio_analog[1] gpio_analog[0] gpio_noesd[17]
++ gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] gpio_noesd[12] gpio_noesd[11] gpio_noesd[10]
++ gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] gpio_noesd[4] gpio_noesd[3] gpio_noesd[2]
++ gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[5]
++ io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] io_clamp_high[2] io_clamp_high[1]
++ io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_irq[2] user_irq[1] user_irq[0] la_oenb[127]
++ la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] la_oenb[119]
++ la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] la_oenb[111]
++ la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] la_oenb[103]
++ la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] la_oenb[94]
++ la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] la_oenb[85]
++ la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] la_oenb[76]
++ la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] la_oenb[67]
++ la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] la_oenb[58]
++ la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] la_oenb[49]
++ la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] la_oenb[40]
++ la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] la_oenb[31]
++ la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] la_oenb[22]
++ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13]
++ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4]
++ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
+x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
+R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R3 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1
+R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R8 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R10 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1
+R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+R12 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1
+.ends
+
+* expanding symbol: example_por.sym # of pins=6
+* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
+* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
+.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
+*.iopin vdd3v3
+*.iopin vss
+*.opin porb_h
+*.opin porb_l
+*.opin por_l
+*.iopin vdd1v8
+XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
+XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
+XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
+XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
+XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
+x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
+x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
+x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
+x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym
new file mode 100644
index 0000000..a561ba9
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sym
@@ -0,0 +1,111 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -190 130 -190 {}
+L 4 -130 190 130 190 {}
+L 4 -130 -190 -130 190 {}
+L 4 130 -190 130 190 {}
+L 4 -150 -180 -130 -180 {}
+L 4 -150 -160 -130 -160 {}
+L 4 -150 -140 -130 -140 {}
+L 4 -150 -120 -130 -120 {}
+L 4 -150 -100 -130 -100 {}
+L 4 -150 -80 -130 -80 {}
+L 4 -150 -60 -130 -60 {}
+L 4 -150 -40 -130 -40 {}
+L 4 130 -20 150 -20 {}
+L 4 130 0 150 0 {}
+L 4 -150 -20 -130 -20 {}
+L 4 130 20 150 20 {}
+L 4 -150 0 -130 0 {}
+L 4 -150 20 -130 20 {}
+L 4 -150 40 -130 40 {}
+L 4 130 40 150 40 {}
+L 4 130 60 150 60 {}
+L 4 -150 60 -130 60 {}
+L 4 130 180 150 180 {}
+L 7 130 -180 150 -180 {}
+L 7 130 -160 150 -160 {}
+L 7 130 -140 150 -140 {}
+L 7 130 -120 150 -120 {}
+L 7 130 -100 150 -100 {}
+L 7 130 -80 150 -80 {}
+L 7 130 -60 150 -60 {}
+L 7 130 -40 150 -40 {}
+L 7 130 80 150 80 {}
+L 7 130 100 150 100 {}
+L 7 130 120 150 120 {}
+L 7 130 140 150 140 {}
+L 7 130 160 150 160 {}
+B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout }
+B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout }
+B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout }
+B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout }
+B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout }
+B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout }
+B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout }
+B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout }
+B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in }
+B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in }
+B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in }
+B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in }
+B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in }
+B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in }
+B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in }
+B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out }
+B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in }
+B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out }
+B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in }
+B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in }
+B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in }
+B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out }
+B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out }
+B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout }
+B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout }
+B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout }
+B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout }
+B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout }
+B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in }
+B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out }
+T {@symname} -119.5 114 0 0 0.3 0.3 {}
+T {@name} 135 -202 0 0 0.2 0.2 {}
+T {vdda1} 125 -184 0 1 0.2 0.2 {}
+T {vdda2} 125 -164 0 1 0.2 0.2 {}
+T {vssa1} 125 -144 0 1 0.2 0.2 {}
+T {vssa2} 125 -124 0 1 0.2 0.2 {}
+T {vccd1} 125 -104 0 1 0.2 0.2 {}
+T {vccd2} 125 -84 0 1 0.2 0.2 {}
+T {vssd1} 125 -64 0 1 0.2 0.2 {}
+T {vssd2} 125 -44 0 1 0.2 0.2 {}
+T {wb_clk_i} -125 -184 0 0 0.2 0.2 {}
+T {wb_rst_i} -125 -164 0 0 0.2 0.2 {}
+T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {}
+T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {}
+T {wbs_we_i} -125 -104 0 0 0.2 0.2 {}
+T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {}
+T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {}
+T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {}
+T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {}
+T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {}
+T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {}
+T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {}
+T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {}
+T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}
+T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {}
+T {io_out[26:0]} 125 36 0 1 0.2 0.2 {}
+T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {}
+T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {}
+T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {}
+T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {}
+T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {}
+T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {}
+T {user_clock2} -125 56 0 0 0.2 0.2 {}
+T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100644
index 0000000..ca6e33e
--- /dev/null
+++ b/xschem/xschemrc
@@ -0,0 +1,296 @@
+#### xschemrc system configuration file
+
+#### values may be overridden by user's ~/.xschem/xschemrc configuration file
+#### or by project-local ./xschemrc
+
+###########################################################################
+#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
+###########################################################################
+#### Normally there is no reason to set this variable if using standard
+#### installation. Location of files is set at compile time but may be overridden
+#### with following line:
+# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+
+###########################################################################
+#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
+###########################################################################
+#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
+# /home/schippes/.xschem/xschem_library
+# /home/schippes/share/xschem/xschem_library/devices
+# /home/schippes/share/doc/xschem/examples
+# /home/schippes/share/doc/xschem/ngspice
+# /home/schippes/share/doc/xschem/logic
+# /home/schippes/share/doc/xschem/xschem_simulator
+# /home/schippes/share/doc/xschem/binto7seg
+# /home/schippes/share/doc/xschem/pcb
+# /home/schippes/share/doc/xschem/rom8k
+
+#### Allow user environment to override the path to the PDK
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/share/pdk/sky130A"
+}
+#### Flush any previous definition
+set XSCHEM_LIBRARY_PATH {}
+#### include devices/*.sym
+append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
+#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+append XSCHEM_LIBRARY_PATH :$env(PWD)
+append XSCHEM_LIBRARY_PATH :$PDKPATH/libs.tech/xschem
+# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem
+#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
+append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+
+###########################################################################
+#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
+###########################################################################
+#### each line contains a dircolor(pattern) followed by a color
+#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
+#### hex code must be enclosed in braces
+array unset dircolor
+set dircolor(sky130_fd_pr$) blue
+set dircolor(sky130_tests$) blue
+set dircolor(xschem_sky130$) blue
+set dircolor(xschem_library$) red
+set dircolor(devices$) red
+
+###########################################################################
+#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
+###########################################################################
+#### Start without a design if no filename given on command line:
+#### To avoid absolute paths, use a path that is relative to one of the
+#### XSCHEM_LIBRARY_PATH directories. Default: empty
+set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+
+###########################################################################
+#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+###########################################################################
+#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
+# set netlist_dir $env(HOME)/.xschem/simulations
+set netlist_dir .
+
+###########################################################################
+#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
+#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
+###########################################################################
+#### default: empty (use xschem default, [ ])
+# set bus_replacement_char {<>}
+#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
+# set bus_replacement_char {__}
+
+###########################################################################
+#### SOME DEFAULT BEHAVIOR
+###########################################################################
+#### Allowed values: spice, verilog, vhdl, tedax, default: spice
+# set netlist_type spice
+
+#### Some netlisting options (these are the defaults)
+# set hspice_netlist 1
+# set verilog_2001 1
+
+#### to use a fixed line with set change_lw to 0 and set some value to line_width
+#### these are the defaults
+# set line_width 0
+# set change_lw 1
+
+#### allow color postscript and svg exports. Default: 1, enable color
+# set color_ps 1
+
+#### initial size of xschem window you can specify also position with (wxh+x+y)
+#### this is the default:
+# set initial_geometry {900x600}
+
+#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
+#### allowing to move away by zooming / unzooming with mouse wheel
+#### default setting: 0
+# set unzoom_nodrift 0
+
+#### if set to 1 allow to place multiple components with same name.
+#### Warning: this is normally not allowed in any simulation netlist.
+#### default: 0, do not allow place multiple elements with same name (refdes)
+# set disable_unique_names 0
+
+#### if set to 1 continue drawing lines / wires after click
+#### default: 0
+# set persistent_command 1
+
+#### if set to 1 automatically join/trim wires while editing
+#### this may slow down on rally big designs. Can be disabled via menu
+#### default: 0
+# set autotrim_wires 0
+
+#### set widget scaling (mainly for font display), this is useful on 4K displays
+#### default: unset (tk uses its default) > 1.0 ==> bigger
+# set tk_scaling 1.7
+
+#### disable some symbol layers. Default: none, all layers are visible.
+# set enable_layer(5) 0 ;# example to disable pin red boxes
+
+#### enable to scale grid point size as done with lines at close zoom, default: 0
+# set big_grid_points 0
+
+###########################################################################
+#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
+###########################################################################
+#### command to translate xpm to png; (assumes command takes source
+#### and dest file as arguments, example: gm convert plot.xpm plot.png)
+#### default: {gm convert}
+# set to_png {gm convert}
+
+#### command to translate ps to pdf; (assumes command takes source
+#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
+#### default: ps2pdf
+# set to_pdf ps2pdf
+set to_pdf {ps2pdf -dAutoRotatePages=/None}
+
+
+###########################################################################
+#### CUSTOM GRID / SNAP VALUE SETTINGS
+###########################################################################
+#### Warning: changing these values will likely break compatibility
+#### with existing symbol libraries. Defaults: grid 20, snap 10.
+# set grid 20
+# set snap 10
+
+###########################################################################
+#### CUSTOM COLORS MAY BE DEFINED HERE
+###########################################################################
+# set cadlayers 22
+# set light_colors {
+# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
+# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
+# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
+# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+# set dark_colors {
+# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
+# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
+# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
+# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+###########################################################################
+#### CAIRO STUFF
+###########################################################################
+#### Scale all fonts by this number
+# set cairo_font_scale 1.0
+
+#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
+#### match cairo font spacing
+# set nocairo_font_xscale 1.0
+#### set nocairo_font_yscale 1.0
+
+#### Scale line spacing by this number
+# set cairo_font_line_spacing 1.0
+
+#### Specify a font
+# set cairo_font_name {Sans-Serif}
+# set svg_font_name {Sans-Serif}
+
+#### Lift up text by some zoom-corrected pixels for
+#### better compatibility wrt no cairo version.
+#### Useful values in the range [-1, 3]
+# set cairo_vert_correct 0
+# set nocairo_vert_correct 0
+
+###########################################################################
+#### KEYBINDINGS
+###########################################################################
+#### General format for specifying a replacement for a keybind
+#### Replace Ctrl-d with Escape (so you wont kill the program)
+# set replace_key(Control-d) Escape
+
+#### swap w and W keybinds; Always specify Shift for capital letters
+# set replace_key(Shift-W) w
+# set replace_key(w) Shift-W
+
+###########################################################################
+#### TERMINAL
+###########################################################################
+#### default for linux: xterm
+# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
+#### lxterminal is not OK since it will not inherit env vars:
+#### In order to reduce memory usage and increase the performance, all instances
+#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
+
+###########################################################################
+#### EDITOR
+###########################################################################
+#### editor must not detach from launching shell (-f mandatory for gvim)
+#### default for linux: gvim -f
+# set editor {gvim -f -geometry 90x28}
+# set editor { xterm -geometry 100x40 -e nano }
+# set editor { xterm -geometry 100x40 -e pico }
+
+#### For Windows
+# set editor {notepad.exe}
+
+###########################################################################
+#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
+###########################################################################
+#### default: 0 (can be enabled by menu)
+# set show_infowindow 0
+
+###########################################################################
+#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
+###########################################################################
+#### RTDA NC
+# set computerfarm {nc run -Il}
+#### LSF BSUB
+# set computerfarm {bsub -Is}
+
+###########################################################################
+#### TCP CONNECTION WITH GAW
+###########################################################################
+#### set gaw address for socket connection: {host port}
+#### default: set to localhost, port 2020
+# set gaw_tcp_address {localhost 2020}
+
+###########################################################################
+#### XSCHEM LISTEN TO TCP PORT
+###########################################################################
+#### set xschem listening port; default: not enabled
+# set xschem_listen_port 2021
+
+###########################################################################
+#### BESPICE WAVE SOCKET CONNECTION
+###########################################################################
+#### set bespice wave listening port; default: not enabled
+set bespice_listen_port 2022
+
+
+
+###########################################################################
+#### UTILE SPICE STIMULI DESCRIPTION LANGUAGE AND TRANSLATOR
+###########################################################################
+#### default paths are set as shown here:
+# set utile_gui_path ${XSCHEM_SHAREDIR}/utile/utile3
+# set utile_cmd_path ${XSCHEM_SHAREDIR}/utile/utile
+
+###########################################################################
+#### TCL FILES TO LOAD AT STARTUP
+###########################################################################
+#### list of tcl files to preload.
+# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
+lappend tcl_files $PDKPATH/libs.tech/xschem/scripts/sky130_models.tcl
+###########################################################################
+#### XSCHEM TOOLBAR
+###########################################################################
+#### default: not enabled.
+# set toolbar_visible 1
+# set toolbar_horiz 1
+
+###########################################################################
+#### SKYWATER PDK SPECIFIC VARIABLES
+###########################################################################
+
+## (spice patched) skywater-pdk install
+# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+
+## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
+# set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
+# set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
+set SKYWATER_MODELS $PDKPATH/libs.tech/ngspice
+set SKYWATER_STDCELLS $PDKPATH/libs.ref/sky130_fd_sc_hd/spice
