commit	887345971005ed0dc47cb9821b697067620d0fc9	[log] [tgz]
author	SultanShadow <rmsjamil@gmail.com>	Sun Jan 02 19:37:55 2022 +0500
committer	SultanShadow <rmsjamil@gmail.com>	Sun Jan 02 19:37:55 2022 +0500
tree	1f86863393fe6bf9128e3f1a66667773d35993f5
parent	2a3c94373ffc0e53a287be94a569a2139b1cb496 [diff]

Updating Design Files

README.md[diff]
caravel[Deleted - diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/to_ALU_opt_TMR_KP_Voter.gds[Added - diff]
gds/user_proj_example.gds[diff]
gds/user_project_wrapper.gds[diff]
lef/to_ALU_opt_TMR_KP_Voter.lef[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/mprj_stimulus/Makefile[diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[diff]
verilog/gl/user_proj_example.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/ALU_Opt.v[Added - diff]
verilog/rtl/ALU_opt_2.v[Added - diff]
verilog/rtl/ALU_opt_3.v[Added - diff]
verilog/rtl/F_Adder.v[Added - diff]
verilog/rtl/H_Adder.v[Added - diff]
verilog/rtl/KP_Voter.v[Added - diff]
verilog/rtl/MUX_2X1.v[Added - diff]
verilog/rtl/RPA_16bit.v[Added - diff]
verilog/rtl/RPA_4bit.v[Added - diff]
verilog/rtl/RP_Add_Sub_4bit.v[Added - diff]
verilog/rtl/SIPO.v[Added - diff]
verilog/rtl/booth_16bit_sign.v[Added - diff]
verilog/rtl/booth_recoder.v[Added - diff]
verilog/rtl/constraint.sdc[Added - diff]
verilog/rtl/generate_pp_cv.v[Added - diff]
verilog/rtl/to_ALU_opt_TMR_KP_Voter.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

50 files changed

tree: 1f86863393fe6bf9128e3f1a66667773d35993f5

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

ALU FOR RADIATION HARDENED APPLICATIONS

This repo contains the design of a radiation hardened TMR based ALY implemented in SKY130 open source PDK. This design was hardened using openlane