test

gds/and.ext

diff --git a/gds/and.ext b/gds/and.ext
index b35b4d2..763da9c 100644
--- a/gds/and.ext
+++ b/gds/and.ext
@@ -27,14 +27,17 @@
 node "out1" 6488 1253.5 280 -220 li 0 0 0 0 0 0 0 0 32000 960 83200 2400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3340 0 0 136500 4640 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 1983 2469.6 -170 880 nw 0 0 0 0 823200 3640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n126_n696#" 0 0 -126 -696 pw 310384 2388 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "gnd!" "Z1" 409.78
-cap "OUT" "Z1" 43.6452
+cap "VDD" "OUT" 2.3125
+cap "VDD" "vdd!" 48.86
+cap "VDD" "out1" 6.1975
+cap "Z1" "gnd!" 409.78
+cap "Z1" "OUT" 43.6452
+cap "Z1" "B" 67.1786
+cap "Z1" "vdd!" 7.96552
+cap "Z1" "out1" 356.371
 cap "OUT" "gnd!" 198
-cap "B" "Z1" 67.1786
 cap "A" "gnd!" 57.75
 cap "B" "OUT" 8.8
-cap "vdd!" "Z1" 7.96552
-cap "out1" "Z1" 356.371
 cap "vdd!" "gnd!" 13.8886
 cap "out1" "gnd!" 226.769
 cap "vdd!" "OUT" 574.768
@@ -45,9 +48,6 @@
 cap "out1" "B" 176.792
 cap "out1" "A" 13.5179
 cap "out1" "vdd!" 1441.54
-cap "VDD" "OUT" 2.3125
-cap "VDD" "vdd!" 48.86
-cap "VDD" "out1" 6.1975
 device msubckt sky130_fd_pr__nfet_01v8 480 -670 481 -669 l=30 w=300 "w_n126_n696#" "out1" 60 0 "gnd!" 300 0 "OUT" 300 0
 device msubckt sky130_fd_pr__nfet_01v8 230 -670 231 -669 l=30 w=400 "w_n126_n696#" "B" 60 0 "Z1" 400 0 "out1" 400 0
 device msubckt sky130_fd_pr__nfet_01v8 -20 -670 -19 -669 l=30 w=400 "w_n126_n696#" "A" 60 0 "gnd!" 400 0 "Z1" 400 0

gds/and_pd.ext

diff --git a/gds/and_pd.ext b/gds/and_pd.ext
index bef37a2..5a5bf53 100644
--- a/gds/and_pd.ext
+++ b/gds/and_pd.ext
@@ -22,14 +22,11 @@
 node "A" 1358 374.675 -100 -230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 1960 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 2352 1494 -100 410 nw 0 0 0 0 498000 2860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n86_n496#" 0 0 -86 -496 pw 172144 1948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "GND" "Z1" 192.37
-cap "Out" "Z1" 19.8
+cap "Z1" "Out1" 178.758
+cap "Z1" "B" 57.75
 cap "Out" "GND" 118.8
-cap "a_n60_n30#" "Z1" 8.88462
-cap "Out1" "Z1" 178.758
 cap "a_n60_n30#" "GND" 17.7692
 cap "Out1" "GND" 176.55
-cap "B" "Z1" 57.75
 cap "a_n60_n30#" "Out" 277.2
 cap "Out1" "Out" 188.1
 cap "B" "Out" 8.8
@@ -43,6 +40,9 @@
 cap "A" "Out1" 13.5179
 cap "VDD" "Out1" 3.7
 cap "A" "B" 75.0211
+cap "Z1" "GND" 192.37
+cap "Z1" "Out" 19.8
+cap "Z1" "a_n60_n30#" 8.88462
 device msubckt sky130_fd_pr__nfet_01v8 520 -470 521 -469 l=30 w=180 "w_n86_n496#" "Out1" 60 0 "GND" 180 0 "Out" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 270 -470 271 -469 l=30 w=180 "w_n86_n496#" "B" 60 0 "Z1" 180 0 "Out1" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 20 -470 21 -469 l=30 w=180 "w_n86_n496#" "A" 60 0 "GND" 180 0 "Z1" 180 0

gds/cbank.ext

diff --git a/gds/cbank.ext b/gds/cbank.ext
index 2872f12..aeab02d 100644
--- a/gds/cbank.ext
+++ b/gds/cbank.ext
@@ -34,18 +34,18 @@
 node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
 node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "gnd!" 0 0 4950 -1370 li 415872 7104 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
-cap "a_4660_n30#" "a_5640_n30#" 199.5
 cap "a_2730_n30#" "li_1720_n30#" 199.5
-cap "a_3680_n30#" "a_4660_n30#" 199.5
-cap "a_1720_n30#" "li_1720_n30#" 18.13
-cap "a_2730_n30#" "a_3680_n30#" 199.5
 cap "v" "li_1720_n30#" 1301.39
+cap "a_1720_n30#" "li_1720_n30#" 18.13
+cap "a_2730_n30#" "v" 1301.39
+cap "a_6660_n30#" "v" 1301.39
 cap "a_5640_n30#" "v" 1301.39
 cap "a_5640_n30#" "a_6660_n30#" 191.52
 cap "a_4660_n30#" "v" 1301.39
 cap "a_3680_n30#" "v" 1301.39
-cap "a_2730_n30#" "v" 1301.39
-cap "a_6660_n30#" "v" 1301.39
+cap "a_2730_n30#" "a_3680_n30#" 199.5
+cap "a_4660_n30#" "a_5640_n30#" 199.5
+cap "a_3680_n30#" "a_4660_n30#" 199.5
 device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1856 0 "a_6660_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1856 0 "a_5640_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1856 0 "a_4660_n30#" 1440 0
@@ -53,10 +53,10 @@
 device csubckt sky130_fd_pr__cap_mim_m3_1 2540 590 2541 591 w=560 l=560 "None" "v" 1856 0 "a_2730_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1856 0 "li_1720_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3616 0 "gnd!" 1440 0
-cap "switch_4/vin" "switch_4/vout" -0.157143
 cap "a1" "switch_4/vin" -183.5
-cap "a0" "switch_5/vin" 83.635
 cap "a0" "switch_5/vout" 4.23077
+cap "switch_4/vin" "switch_4/vout" -0.157143
+cap "a0" "switch_5/vin" 83.635
 cap "a2" "switch_3/vout" 4.23077
 cap "a2" "switch_3/vin" 83.635
 cap "a1" "switch_4/vout" 4.23077

gds/cp.ext

diff --git a/gds/cp.ext b/gds/cp.ext
index 3f18804..1872f89 100644
--- a/gds/cp.ext
+++ b/gds/cp.ext
@@ -26,23 +26,23 @@
 node "upbar" 658 1347.77 6930 -320 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0
 node "vdd!" 18302 139352 4230 3990 li 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0
 substrate "gnd!" 0 0 4280 -3300 li 16003824 41948 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0
-cap "vdd!" "a_3060_n2840#" 320.4
-cap "upbar" "down" 20.625
-cap "a_10_n50#" "vbias" 192.9
-cap "vdd!" "a_7110_0#" 42.55
 cap "out" "a_1710_0#" 841.733
 cap "a_1710_n2840#" "a_1710_0#" 828.847
 cap "a_10_n50#" "a_1710_0#" 41.6842
-cap "vdd!" "a_6370_0#" 402.828
 cap "a_1710_n2840#" "out" 606.81
+cap "vdd!" "upbar" 149.92
+cap "vdd!" "a_3060_n2840#" 320.4
+cap "upbar" "down" 20.625
+cap "vdd!" "a_7110_0#" 42.55
+cap "vdd!" "a_6370_0#" 402.828
 cap "vdd!" "a_3060_0#" 1788.27
 cap "vdd!" "a_1710_0#" 714.147
 cap "vdd!" "out" 376.075
 cap "upbar" "a_1710_n2840#" 291.6
 cap "vdd!" "a_1710_n2840#" 254.08
 cap "vdd!" "a_10_n50#" 530.297
-cap "vdd!" "upbar" 149.92
 cap "a_1710_0#" "down" 320.4
+cap "a_10_n50#" "vbias" 192.9
 device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
 device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
 device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0

gds/divider.ext

diff --git a/gds/divider.ext b/gds/divider.ext
index d1f9464..f5fbf29 100644
--- a/gds/divider.ext
+++ b/gds/divider.ext
@@ -51,185 +51,177 @@
 node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0
 node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0
 substrate "w_n966_n46#" 0 0 -966 -46 pw 2535060 32560 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0
-cap "li_5560_680#" "m4_7020_30#" 24.425
-cap "li_3980_680#" "gnd" 24.425
-cap "li_3980_680#" "gnd" 27.1625
-cap "li_5740_3250#" "vdd" 27.9
-cap "li_3310_1810#" "vdd" 35.39
-cap "li_5740_3250#" "vdd" 27.9
 cap "li_7140_680#" "m1_5770_3360#" 19.2857
 cap "li_5560_680#" "m1_5770_3360#" 16.875
+cap "w_2780_1920#" "li_3310_1810#" 24.0375
 cap "li_5560_680#" "li_7140_680#" 437.5
-cap "w_2780_1920#" "m4_7030_1860#" 40.0711
-cap "w_2780_1920#" "vdd" 0.84
 cap "li_7040_820#" "m1_5770_3360#" 90
 cap "li_3980_680#" "li_5560_680#" 782.5
 cap "Out" "li_7140_680#" 23.5
-cap "w_2780_1920#" "vdd" 9.82
-cap "w_2780_1920#" "vdd" 4.08
 cap "li_7040_820#" "li_5560_680#" 15
-cap "w_2780_1920#" "vdd" 8.88
-cap "li_5740_3250#" "m1_5770_3360#" 286.375
-cap "mc2" "gnd" 27.9
+cap "vdd" "li_5740_3250#" 27.9
 cap "li_5460_820#" "li_3980_680#" 20
-cap "li_6130_3350#" "m1_5770_3360#" 136.842
-cap "li_5740_3250#" "li_5560_680#" 21.9534
-cap "li_5740_3250#" "li_3980_680#" 22.5
-cap "mc2" "m1_5770_3360#" 35.7143
-cap "mc2" "li_7140_680#" 61.52
-cap "li_5740_3250#" "li_5460_820#" 128.305
-cap "w_2780_1920#" "m1_5770_3360#" 53.84
-cap "li_6130_3350#" "li_5740_3250#" 68.1032
-cap "mc2" "li_5740_3250#" 22.679
-cap "w_2780_1920#" "li_3310_1810#" 24.0375
+cap "vdd" "li_5740_3250#" 27.9
 cap "w_2780_1920#" "li_5740_3250#" 72.945
 cap "w_2780_1920#" "li_6130_3350#" 7.215
 cap "w_2780_1920#" "li_2870_2670#" 76.8485
+cap "m1_5770_3360#" "li_5740_3250#" 286.375
+cap "gnd" "mc2" 27.9
+cap "m1_5770_3360#" "li_6130_3350#" 136.842
+cap "li_5560_680#" "li_5740_3250#" 21.9534
+cap "li_3980_680#" "li_5740_3250#" 22.5
+cap "m1_5770_3360#" "mc2" 35.7143
+cap "li_7140_680#" "mc2" 61.52
+cap "li_5460_820#" "li_5740_3250#" 128.305
 cap "vdd" "vdd" 33.5
+cap "w_2780_1920#" "m4_7030_1860#" 40.0711
 cap "vdd" "vdd" 51.2353
+cap "w_2780_1920#" "vdd" 0.84
 cap "vdd" "vdd" 20.1
+cap "w_2780_1920#" "vdd" 9.82
+cap "li_6130_3350#" "li_5740_3250#" 68.1032
+cap "w_2780_1920#" "vdd" 4.08
+cap "li_5560_680#" "m4_7020_30#" 24.425
+cap "w_2780_1920#" "vdd" 8.88
+cap "mc2" "li_5740_3250#" 22.679
+cap "li_3980_680#" "gnd" 24.425
+cap "li_3980_680#" "gnd" 27.1625
+cap "w_2780_1920#" "m1_5770_3360#" 53.84
+cap "li_3310_1810#" "vdd" 35.39
 cap "w_n966_n46#" "prescaler_0/nand_1/A" 17.3684
-cap "prescaler_0/tspc_2/Z2" "prescaler_0/nand_1/w_n46_n476#" 27.6618
-cap "prescaler_0/tspc_2/a_630_n680#" "prescaler_0/nand_1/w_n46_n476#" 9.78378
-cap "prescaler_0/GND" "prescaler_0/nand_1/w_n46_n476#" 21.945
-cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
-cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/Z2" 27.6618
-cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/GND" 30.14
-cap "tspc_0/D" "tspc_0/Z4" 35.0633
-cap "tspc_0/D" "tspc_0/Z2" 141.466
-cap "tspc_0/w_n140_n70#" "gnd" 0.12
-cap "prescaler_0/tspc_1/w_n146_n706#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
-cap "prescaler_0/tspc_1/w_n146_n706#" "gnd" 21.945
-cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/w_n140_n70#" 0.195
-cap "tspc_0/D" "tspc_0/Z3" 1.36364
-cap "tspc_0/D" "gnd" 413.181
-cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
+cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/tspc_2/a_630_n680#" 9.78378
+cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/GND" 21.945
+cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/tspc_2/Z2" 27.6618
+cap "prescaler_0/tspc_1/a_630_n680#" "prescaler_0/tspc_2/w_n146_n706#" 4.89189
+cap "prescaler_0/tspc_1/Z2" "prescaler_0/tspc_2/w_n146_n706#" 27.6618
+cap "prescaler_0/tspc_1/GND" "prescaler_0/tspc_2/w_n146_n706#" 30.14
 cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
-cap "prescaler_0/tspc_1/w_n146_n706#" "tspc_0/Z2" 27.6618
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
-cap "tspc_1/D" "tspc_1/Z3" 1.36364
-cap "gnd" "tspc_1/Z2" 7.81579
-cap "tspc_1/D" "tspc_1/Z4" 33.0938
-cap "tspc_1/D" "tspc_1/Z2" 213.298
-cap "w_n966_n46#" "tspc_0/a_630_n680#" 9.78378
-cap "w_n966_n46#" "gnd" 23.265
-cap "tspc_0/Q" "tspc_1/w_n140_n70#" 5.55112e-17
-cap "tspc_0/a_740_n680#" "tspc_1/w_n140_n70#" 0.065
-cap "tspc_0/a_740_n680#" "tspc_0/Q" 145.525
-cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583
-cap "tspc_0/Q" "gnd" 21.2143
-cap "w_n966_n46#" "tspc_1/Z2" 27.6618
+cap "tspc_0/Z2" "prescaler_0/tspc_1/w_n146_n706#" 27.6618
+cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
+cap "gnd" "tspc_0/w_n140_n70#" 0.12
+cap "prescaler_0/tspc_1/a_630_n680#" "prescaler_0/tspc_1/w_n146_n706#" 4.89189
+cap "gnd" "prescaler_0/tspc_1/w_n146_n706#" 21.945
+cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
+cap "tspc_0/Z4" "tspc_0/D" 35.0633
+cap "tspc_0/Z2" "tspc_0/D" 141.466
+cap "gnd" "tspc_0/D" 413.181
+cap "tspc_0/Z3" "tspc_0/D" 1.36364
 cap "gnd" "tspc_0/a_630_n680#" 7.61538
+cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583
 cap "tspc_0/a_740_n680#" "gnd" 281.141
-cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795
-cap "tspc_0/Q" "tspc_1/D" 70.641
 cap "tspc_1/D" "tspc_0/a_630_n680#" 5.45455
 cap "tspc_1/D" "gnd" 346.096
-cap "tspc_0/Q" "tspc_1/Z4" 30.4615
+cap "tspc_1/D" "tspc_1/Z3" 1.36364
+cap "tspc_0/Q" "gnd" 21.2143
+cap "tspc_1/D" "tspc_0/a_740_n680#" -7.31795
+cap "tspc_0/Q" "tspc_0/a_740_n680#" 145.525
+cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
+cap "w_n966_n46#" "gnd" 23.265
+cap "w_n966_n46#" "tspc_0/a_630_n680#" 9.78378
+cap "tspc_0/Q" "tspc_1/D" 70.641
 cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
+cap "gnd" "tspc_1/Z2" 7.81579
+cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
+cap "tspc_1/D" "tspc_1/Z4" 33.0938
+cap "tspc_0/Q" "tspc_1/w_n140_n70#" 5.55112e-17
+cap "tspc_1/D" "tspc_1/Z2" 213.298
+cap "tspc_0/Q" "tspc_1/Z4" 30.4615
 cap "tspc_0/Q" "tspc_1/Z2" 25.8231
+cap "w_n966_n46#" "tspc_1/Z2" 27.6618
+cap "tspc_1/Q" "tspc_2/D" 70.641
+cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
 cap "tspc_1/a_740_n680#" "tspc_1/Q" 155.525
+cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "tspc_2/D" "tspc_2/Z4" 20.0553
+cap "tspc_1/Q" "tspc_2/Z4" 30.4615
+cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882
+cap "w_n966_n46#" "tspc_2/Z2" 12.6176
 cap "w_n966_n46#" "tspc_1/GND" 30.14
 cap "w_n966_n46#" "tspc_1/a_630_n680#" 9.78378
+cap "tspc_1/GND" "tspc_2/Z2" 7.81579
+cap "tspc_1/GND" "tspc_1/a_630_n680#" 7.61538
+cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
+cap "tspc_2/D" "tspc_2/Z2" 309.898
+cap "tspc_2/w_n140_n70#" "tspc_1/a_740_n680#" 0.065
+cap "tspc_1/Q" "tspc_2/Z2" 25.8231
+cap "tspc_2/D" "tspc_1/GND" 339.551
+cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
 cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107
 cap "tspc_1/Q" "tspc_1/GND" 21.2143
 cap "tspc_1/a_740_n680#" "tspc_1/GND" 440.385
-cap "tspc_1/GND" "tspc_1/a_630_n680#" 7.61538
-cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
-cap "tspc_1/Q" "tspc_2/D" 70.641
-cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
-cap "tspc_2/D" "tspc_1/GND" 339.551
-cap "tspc_1/Q" "tspc_2/Z4" 30.4615
-cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882
-cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
-cap "w_n966_n46#" "tspc_2/Z2" 12.6176
-cap "tspc_1/Q" "tspc_2/Z2" 25.8231
-cap "tspc_1/GND" "tspc_2/Z2" 7.81579
-cap "tspc_2/D" "tspc_2/Z3" 0.681818
-cap "tspc_2/D" "tspc_2/Z4" 20.0553
-cap "tspc_2/D" "tspc_2/Z2" 309.898
-cap "tspc_1/a_740_n680#" "tspc_2/w_n140_n70#" 0.065
-cap "tspc_2/D" "Out" 20.775
-cap "tspc_2/D" "tspc_2/Z3" 0.681818
-cap "tspc_2/D" "tspc_1/Q" -1.77636e-15
+cap "tspc_2/Z4" "li_5560_680#" 10.5882
 cap "tspc_2/D" "tspc_2/a_630_n680#" 159.583
 cap "tspc_2/D" "tspc_2/GND" 450.398
-cap "tspc_2/D" "tspc_2/Z4" 17.815
 cap "tspc_1/w_n146_n706#" "tspc_2/a_630_n680#" 9.78378
+cap "tspc_2/D" "Out" 20.775
+cap "tspc_2/D" "tspc_2/Z4" 17.815
 cap "tspc_1/w_n146_n706#" "tspc_2/GND" 23.265
 cap "tspc_1/w_n146_n706#" "tspc_2/Z2" 15.0441
-cap "tspc_2/Z4" "li_5560_680#" 10.5882
+cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "tspc_2/D" "tspc_1/Q" -1.77636e-15
 cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/A" 12.2938
 cap "w_n966_n46#" "prescaler_0/nand_1/A" 14.7632
-cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/OUT" -2.84217e-14
 cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/vdd!" 4.57853
+cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/OUT" -2.84217e-14
 cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557
-cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 78.0797
-cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557
+cap "prescaler_0/mc1" "prescaler_0/nand_1/VDD" 78.0797
 cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z2" -1.77636e-15
 cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 2.73
-cap "prescaler_0/tspc_2/Z1" "prescaler_0/nand_1/VDD" 3.19744e-14
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_1/Z3" -2.37588e-14
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_1/Z2" -4.61853e-14
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_1/Z1" 3.55271e-15
+cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z1" 3.19744e-14
+cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557
 cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 73.8879
 cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/a_280_n230#" 16.0962
+cap "prescaler_0/tspc_1/Z3" "prescaler_0/nand_0/VDD" -2.37588e-14
+cap "prescaler_0/tspc_1/Z1" "prescaler_0/nand_0/VDD" 3.55271e-15
+cap "prescaler_0/tspc_1/Z2" "prescaler_0/nand_0/VDD" -4.61853e-14
+cap "vdd" "tspc_0/Z2" 10
+cap "vdd" "tspc_0/Z1" 8.88178e-14
+cap "vdd" "prescaler_0/tspc_1/Q" 19.25
 cap "vdd" "prescaler_0/GND" 244.839
 cap "vdd" "prescaler_0/tspc_1/a_740_n680#" 114.95
 cap "vdd" "and_0/OUT" 7.5
 cap "vdd" "prescaler_0/mc1" 4.79032
-cap "vdd" "tspc_0/Z2" 10
-cap "vdd" "tspc_0/Z1" 8.88178e-14
-cap "vdd" "prescaler_0/tspc_1/Q" 19.25
 cap "nor_0/VDD" "vdd" -3.46
+cap "vdd" "tspc_0/a_740_n680#" 177.528
+cap "nor_0/VDD" "tspc_0/a_740_n680#" 4.63
 cap "tspc_0/Q" "tspc_1/Z1" 7
 cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927
 cap "vdd" "tspc_0/Q" 93.7845
-cap "vdd" "tspc_0/a_740_n680#" 177.528
-cap "nor_0/VDD" "tspc_0/a_740_n680#" 4.63
 cap "tspc_0/a_740_n680#" "tspc_0/Q" 75.365
 cap "nor_0/VDD" "tspc_1/Z2" -2.57572e-14
-cap "vdd" "tspc_1/a_740_n680#" 13.3333
 cap "nor_0/VDD" "tspc_1/a_740_n680#" 76.5957
-cap "nor_0/VDD" "vdd" 224.245
 cap "tspc_1/Q" "tspc_2/Z1" 7
 cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351
+cap "vdd" "tspc_1/a_740_n680#" 13.3333
 cap "tspc_1/a_740_n680#" "tspc_1/Q" 75.365
 cap "nor_0/VDD" "tspc_2/Z2" 7.54952e-15
 cap "nor_0/VDD" "tspc_2/Z1" 2.25375e-14
+cap "nor_0/VDD" "vdd" 224.245
 cap "nor_0/VDD" "tspc_1/Z3" -2.37588e-14
 cap "nor_0/VDD" "tspc_1/Q" 93.7845
-cap "tspc_2/Z2" "tspc_2/vdd!" -2.13163e-14
-cap "tspc_2/Z1" "tspc_2/vdd!" -1.86517e-14
+cap "tspc_2/vdd!" "tspc_2/Z3" -2.37588e-14
+cap "tspc_2/vdd!" "tspc_2/Z2" -2.13163e-14
+cap "tspc_2/vdd!" "tspc_2/Z1" -1.86517e-14
 cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125
-cap "tspc_2/Z3" "tspc_2/vdd!" -2.37588e-14
-cap "Out" "tspc_2/vdd!" 5.9508e-14
+cap "tspc_2/vdd!" "Out" 5.9508e-14
 cap "prescaler_0/tspc_0/vdd!" "w_n140_1520#" 6.56545
 cap "prescaler_0/tspc_0/Q" "w_n140_1520#" 27.2014
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/a_630_n680#" 5.04167
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 12.1359
 cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Q" 9.57252
 cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/a_300_n150#" 5.55112e-16
 cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Z3" -1.15019e-13
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 9.75806
 cap "prescaler_0/tspc_0/a_630_n680#" "mc2" 328.675
-cap "mc2" "prescaler_0/GND" 319.267
-cap "mc2" "prescaler_0/tspc_0/Z2" 126.915
-cap "prescaler_0/tspc_0/a_630_n680#" "prescaler_0/tspc_0/w_n146_n706#" 5.04167
-cap "prescaler_0/GND" "mc2" 127.942
+cap "prescaler_0/GND" "mc2" 319.267
+cap "prescaler_0/tspc_0/Z2" "mc2" 126.915
 cap "prescaler_0/tspc_0/Z2" "mc2" -393.365
-cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 19.9143
 cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/a_280_n230#" 34.0634
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 19.9143
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 3.58696
-cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/OUT" 5.68434e-14
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z2" 1.66533e-15
+cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/OUT" 1.13687e-13
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5
-cap "and_0/Z1" "mc2" 74.215
-cap "and_0/OUT" "mc2" 46.015
-cap "gnd" "mc2" 117.19
-cap "and_0/OUT" "vdd" 39.6
-cap "and_0/B" "mc2" 13.94
-cap "and_0/out1" "mc2" 59.955
-cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566
+cap "prescaler_0/GND" "mc2" 127.942
 cap "and_0/OUT" "gnd" 22.72
 cap "and_0/VDD" "gnd" 23.0856
 cap "w_n966_n46#" "and_0/Z1" 5.5
@@ -238,26 +230,33 @@
 cap "and_0/VDD" "and_0/OUT" 0.870968
 cap "w_n966_n46#" "and_0/OUT" 3.20833
 cap "w_n966_n46#" "and_0/out1" 3.20833
-cap "nor_1/B" "nor_0/B" 2.64706
-cap "nor_1/Out" "nor_0/gnd!" 16.9459
-cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667
-cap "nor_1/B" "nor_1/A" 58.3333
-cap "nor_0/Out" "nor_1/A" 15.1125
-cap "and_0/w_n126_n696#" "nor_0/gnd!" 2.91667
+cap "vdd" "and_0/OUT" 39.6
+cap "and_0/Z1" "mc2" 74.215
+cap "prescaler_0/m1_2700_2190#" "and_0/VDD" 36.6566
+cap "gnd" "mc2" 117.19
+cap "and_0/OUT" "mc2" 46.015
+cap "and_0/B" "mc2" 13.94
+cap "and_0/out1" "mc2" 59.955
+cap "and_0/Z1" "mc2" -164.32
+cap "nor_1/A" "mc2" 12.84
+cap "nor_0/Out" "nor_1/Out" 90.78
 cap "nor_1/Out" "nor_1/B" 13.2
 cap "nor_0/Out" "nor_1/B" 84.4673
-cap "nor_0/VDD" "nor_1/A" 0.99
-cap "nor_0/Out" "nor_1/Out" 90.78
 cap "nor_0/VDD" "nor_0/Out" 4.29
+cap "nor_1/Out" "nor_0/gnd!" 16.9459
 cap "and_0/w_n126_n696#" "nor_1/Out" 7
-cap "and_0/Z1" "mc2" -164.32
-cap "nor_0/gnd!" "mc2" 364.635
-cap "nor_1/A" "mc2" 12.84
-cap "nor_1/B" "mc2" 12.84
+cap "nor_1/B" "nor_0/B" 2.64706
+cap "and_0/w_n126_n696#" "nor_0/gnd!" 2.91667
 cap "nor_1/Out" "mc2" 161.385
-cap "nor_0/Out" "nor_1/Z1" 181.56
 cap "nor_1/Out" "nor_1/Z1" 22.8782
+cap "nor_1/B" "mc2" 12.84
+cap "nor_0/Out" "nor_1/Z1" 181.56
 cap "nor_0/Out" "vdd" 90.78
+cap "nor_0/gnd!" "mc2" 364.635
+cap "nor_0/Out" "nor_1/A" 15.1125
+cap "nor_0/VDD" "nor_1/A" 0.99
+cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667
+cap "nor_1/B" "nor_1/A" 58.3333
 cap "nor_1/A" "nor_0/gnd!" 1.28205
 cap "nor_0/Z1" "nor_1/B" 181.56
 cap "vdd" "nor_1/B" 90.78
@@ -270,24 +269,24 @@
 cap "nor_0/B" "nor_0/Out" 41.7957
 cap "nor_0/VDD" "nor_0/Out" 4.29
 cap "nor_0/B" "nor_0/A" 14.5768
-cap "nor_1/w_n66_n446#" "nor_0/Out" 7
 cap "nor_1/w_n66_n446#" "nor_0/GND" 2
+cap "nor_1/w_n66_n446#" "nor_0/Out" 7
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 9.75806
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/a_630_n680#" 5.04167
 cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 12.1359
-cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 9.75806
-cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 3.58696
-cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 4.5
-cap "w_n966_n46#" "and_0/OUT" 3.20833
-cap "w_n966_n46#" "gnd" 9.75595
-cap "w_n966_n46#" "and_0/Z1" 5.5
-cap "w_n966_n46#" "and_0/out1" 3.20833
-cap "nor_0/gnd!" "mc2" 41.6667
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5
+cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 3.58696
+cap "and_0/out1" "w_n966_n46#" 3.20833
+cap "and_0/Z1" "w_n966_n46#" 5.5
+cap "and_0/OUT" "w_n966_n46#" 3.20833
+cap "gnd" "w_n966_n46#" 9.75595
+cap "mc2" "nor_0/gnd!" 41.6667
 cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667
-cap "and_0/w_n126_n696#" "nor_0/gnd!" 29.5
 cap "and_0/w_n126_n696#" "nor_1/Out" 7
-cap "nor_1/w_n66_n446#" "nor_0/Out" 7
+cap "and_0/w_n126_n696#" "nor_0/gnd!" 29.5
 cap "nor_1/w_n66_n446#" "nor_0/GND" 20.3333
 cap "nor_0/GND" "mc2" 41.6667
+cap "nor_1/w_n66_n446#" "nor_0/Out" 7
 merge "nor_1/gnd!" "nor_0/GND" -277.358 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34184 -2250 0 0 0 0
 merge "nor_0/GND" "nor_1/GND"
 merge "nor_1/GND" "nor_0/gnd!"

gds/filter.ext

diff --git a/gds/filter.ext b/gds/filter.ext
index 5f1ef06..1519c72 100644
--- a/gds/filter.ext
+++ b/gds/filter.ext
@@ -11,21 +11,23 @@
 parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
 parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
 parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l
-port "v" 3 4130 -2280 4130 -2280 li
-port "gnd!" 2 4310 -20570 4310 -20570 li
-port "gnd" 1 4310 -20570 4310 -20570 li
-node "a_4294_n4798#" 51429 0 4294 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_3976_n5230#" 178 415258 3976 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60480 2008 154056 1592 40000 800 40000 800 177102650 116770 0 0 0 0
-node "a_3976_n4798#" 51429 0 3976 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_3976_n2998#" 382 1341.76 3976 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
-substrate "v" 0 0 4130 -2280 li 6814080 87360 0 0 0 0 0 0 0 0 4732000 72800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51962080 147668 853254 8326 97600 1760 241185900 76920 35214504 24450 0 0 0 0
-equiv "v" "gnd!"
-equiv "v" "gnd"
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -19830 -2459 -19829 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 400 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -19730 4121 -19729 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 400 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -13520 -2459 -13519 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 400 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -13340 4121 -13339 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 400 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4770 -7130 4771 -7129 w=6000 l=6000 "None" "v" 23616 0 "v" 400 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 400 0
-device rsubckt sky130_fd_pr__res_xhigh_po 4294 -4798 4295 -4797 l=1800 w=70 "v" "a_4294_n4798#" 0 0 "v" 70 0 "a_3976_n2998#" 70 0
-device rsubckt sky130_fd_pr__res_xhigh_po 3976 -4798 3977 -4797 l=1800 w=70 "v" "a_3976_n4798#" 0 0 "a_3976_n5230#" 70 0 "a_3976_n2998#" 70 0
+port "v" 3 4370 -2280 4370 -2280 li
+port "gnd" 2 4660 -21680 4660 -21680 li
+port "gnd!" 1 4660 -21680 4660 -21680 li
+node "v" 193 85693.9 4370 -2280 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 139680 3148 913254 7546 40000 800 40000 800 35334104 25030 0 0 0 0
+node "a_4534_n4798#" 51429 0 4534 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4216_n5230#" 178 418474 4216 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60480 2008 154056 1592 40000 800 40000 800 178748150 121130 0 0 0 0
+node "a_4216_n4798#" 51429 0 4216 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4216_n2998#" 382 1030.6 4216 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
+substrate "gnd" 0 0 4660 -21680 li 7113600 89280 0 0 0 0 0 0 0 0 4867200 74880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53899200 149720 172800 2880 172800 2880 263135300 79980 0 0 0 0 0 0
+equiv "gnd" "gnd!"
+cap "a_4216_n5230#" "v" 187.252
+cap "a_4216_n2998#" "v" 311.161
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -20940 -2459 -20939 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 3600 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -20840 4471 -20839 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 3600 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -14150 -2459 -14149 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 3600 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -13970 4471 -13969 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 3600 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 5290 -7130 5291 -7129 w=6000 l=6000 "None" "v" 23616 0 "gnd" 3600 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_4216_n5230#" 23616 0 "gnd" 3600 0
+device rsubckt sky130_fd_pr__res_xhigh_po 4534 -4798 4535 -4797 l=1800 w=70 "gnd" "a_4534_n4798#" 0 0 "v" 70 0 "a_4216_n2998#" 70 0
+device rsubckt sky130_fd_pr__res_xhigh_po 4216 -4798 4217 -4797 l=1800 w=70 "gnd" "a_4216_n4798#" 0 0 "a_4216_n5230#" 70 0 "a_4216_n2998#" 70 0

gds/nand.ext

diff --git a/gds/nand.ext b/gds/nand.ext
index 9169180..6c1b916 100644
--- a/gds/nand.ext
+++ b/gds/nand.ext
@@ -22,8 +22,6 @@
 node "A" 1521 380.56 -50 -210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 2060 0 0 9600 480 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 1727 1248 -80 520 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n46_n476#" 0 0 -46 -476 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "VDD" "OUT" 2.96
-cap "VDD" "vdd!" 29.2
 cap "gnd!" "z1" 159.5
 cap "OUT" "z1" 210.754
 cap "OUT" "gnd!" 22
@@ -37,6 +35,8 @@
 cap "a_280_n230#" "vdd!" 13.0842
 cap "A" "OUT" 9.74286
 cap "A" "vdd!" 13.0842
+cap "VDD" "OUT" 2.96
+cap "VDD" "vdd!" 29.2
 cap "A" "a_280_n230#" 81.6947
 device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "w_n46_n476#" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "w_n46_n476#" "A" 60 0 "gnd!" 200 0 "z1" 200 0

gds/nor.ext

diff --git a/gds/nor.ext b/gds/nor.ext
index c99f835..a300119 100644
--- a/gds/nor.ext
+++ b/gds/nor.ext
@@ -23,22 +23,22 @@
 node "A" 2231 379.695 -110 -80 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 3542 2250 -110 990 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n66_n446#" 0 0 -66 -446 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Out" "gnd!" 453.75
 cap "Z1" "gnd!" 9.625
 cap "Z1" "Out" 779.396
 cap "vdd!" "gnd!" 9.625
 cap "B" "gnd!" 39.7045
 cap "vdd!" "Out" 99
 cap "A" "gnd!" 19.25
+cap "vdd!" "Z1" 749.833
 cap "B" "Out" 246.8
 cap "A" "Out" 8.8
-cap "VDD" "Out" 2.3125
-cap "Out" "gnd!" 453.75
-cap "vdd!" "Z1" 749.833
 cap "B" "Z1" 57.75
+cap "VDD" "Out" 2.3125
 cap "A" "vdd!" 57.75
-cap "A" "B" 72.9302
 cap "VDD" "Z1" 2.775
 cap "VDD" "vdd!" 16.2425
+cap "A" "B" 72.9302
 device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "w_n66_n446#" "B" 60 0 "gnd!" 200 0 "Out" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "w_n66_n446#" "A" 60 0 "gnd!" 200 0 "Out" 200 0
 device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0

gds/pd.ext

diff --git a/gds/pd.ext b/gds/pd.ext
index e7c08da..6716ce1 100644
--- a/gds/pd.ext
+++ b/gds/pd.ext
@@ -44,63 +44,56 @@
 cap "VDD" "R" 11.2838
 cap "w_0_n1460#" "VDD" 0.48
 cap "VDD" "VDD" 0.48
-cap "GND" "tspc_r_0/Z1" 14.4375
 cap "tspc_r_0/R" "tspc_r_0/Z3" -7.021
 cap "VDD" "tspc_r_0/Z3" 10.9091
-cap "VDD" "tspc_r_0/R" 100
 cap "VDD" "DIV" 62.5
+cap "VDD" "tspc_r_0/R" 100
+cap "tspc_r_0/Z3" "GND" 7.21875
 cap "VDD" "tspc_r_0/Z2" 72
-cap "GND" "tspc_r_0/Z3" 7.21875
 cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775
-cap "GND" "tspc_r_0/Z2" 9.69375
 cap "tspc_r_0/w_n290_n40#" "VDD" 33.548
-cap "GND" "VDD" 99.8267
-cap "tspc_r_0/w_n276_n506#" "tspc_r_0/VDD" 45.2812
-cap "tspc_r_0/Qbar" "tspc_r_0/w_n276_n506#" 7.21875
-cap "tspc_r_0/Qbar" "tspc_r_0/VDD" 30.4615
-cap "tspc_r_0/Q" "tspc_r_0/VDD" 3.30846e-14
-cap "tspc_r_0/Q" "tspc_r_0/w_n276_n506#" 7.21875
-cap "tspc_r_0/Qbar1" "tspc_r_0/VDD" 5.77316e-15
-cap "tspc_r_0/Qbar1" "tspc_r_0/w_n276_n506#" 7.21875
-cap "tspc_r_0/Z3" "tspc_r_0/VDD" -2.04281e-14
+cap "VDD" "GND" 99.8267
+cap "tspc_r_0/Z2" "GND" 9.69375
+cap "GND" "tspc_r_0/Z1" 14.4375
+cap "tspc_r_0/w_n276_n506#" "tspc_r_0/Qbar" 7.21875
+cap "tspc_r_0/VDD" "tspc_r_0/Qbar" 30.4615
 cap "tspc_r_0/R" "tspc_r_0/Z3" 136.361
+cap "tspc_r_0/VDD" "tspc_r_0/Q" 5.68434e-14
+cap "tspc_r_0/w_n276_n506#" "tspc_r_0/Q" 7.21875
+cap "tspc_r_0/w_n276_n506#" "tspc_r_0/Qbar1" 7.21875
+cap "tspc_r_0/VDD" "tspc_r_0/Z3" -2.84217e-14
+cap "tspc_r_0/w_n276_n506#" "tspc_r_0/VDD" 45.2812
+cap "GND" "VDD" 148.505
 cap "tspc_r_1/Z4" "tspc_r_0/Z4" 19.4595
 cap "GND" "tspc_r_0/Z4" 13.3333
-cap "tspc_r_1/Z3" "tspc_r_0/R" -9.042
 cap "GND" "tspc_r_1/Z4" 13.3333
+cap "tspc_r_1/Z3" "tspc_r_0/R" -9.042
 cap "VDD" "tspc_r_0/R" 66.6667
 cap "GND" "tspc_r_0/R" 64.2857
 cap "VDD" "tspc_r_1/Z2" 72
 cap "VDD" "tspc_r_1/Z3" 10.9091
 cap "VDD" "REF" 44.4444
-cap "GND" "VDD" 148.505
-cap "GND" "tspc_r_1/z5" 13.3333
 cap "tspc_r_1/Qbar" "and_pd_0/Z1" 21.0517
 cap "R" "GND" 145.652
-cap "tspc_r_1/Qbar" "GND" 44.4044
 cap "tspc_r_0/Q" "and_pd_0/Z1" 76.112
-cap "tspc_r_1/Qbar" "R" 31.025
 cap "tspc_r_1/VDD" "GND" 8.88178e-16
-cap "tspc_r_0/Q" "GND" 308.57
+cap "tspc_r_1/z5" "tspc_r_0/z5" 19.4595
+cap "tspc_r_1/Qbar" "GND" 44.4044
+cap "R" "tspc_r_1/Qbar" 31.025
 cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 64.7625
-cap "tspc_r_0/Q" "R" 86.5
-cap "tspc_r_0/Q" "tspc_r_1/Qbar" 17.9186
+cap "R" "tspc_r_0/Q" 86.5
+cap "GND" "tspc_r_0/z5" 13.3333
+cap "tspc_r_0/Q" "GND" 308.57
+cap "R" "tspc_r_1/Q" 150.845
+cap "R" "tspc_r_1/Qbar1" 287.105
+cap "R" "tspc_r_1/Z3" 160.382
+cap "R" "tspc_r_1/clk" 103.99
+cap "GND" "tspc_r_1/z5" 13.3333
 cap "and_pd_0/Out1" "tspc_r_1/Qbar" 45.8071
-cap "tspc_r_1/Q" "R" 150.845
-cap "tspc_r_1/Qbar1" "R" 287.105
-cap "tspc_r_1/Z3" "R" 160.382
-cap "tspc_r_1/clk" "R" 103.99
+cap "tspc_r_0/Q" "tspc_r_1/Qbar" 17.9186
 cap "tspc_r_1/Q" "and_pd_0/Out1" -12.43
 cap "tspc_r_1/Q" "tspc_r_0/Q" 180.938
-cap "tspc_r_1/z5" "tspc_r_0/z5" 19.4595
-cap "GND" "tspc_r_0/z5" 13.3333
-cap "and_pd_0/Out1" "R" 137.14
-cap "DOWN" "R" 90.78
-cap "and_pd_0/Out1" "tspc_r_1/Qbar" 1.71875
-cap "UP" "R" 222.129
-cap "VDD" "R" 56.5714
 cap "UP" "and_pd_0/Out1" 70.6975
-cap "tspc_r_0/w_n276_n506#" "R" 71.3216
 cap "VDD" "and_pd_0/Out1" 12.375
 cap "DOWN" "and_pd_0/Out1" 105.892
 cap "DOWN" "UP" 61.428
@@ -108,25 +101,31 @@
 cap "VDD" "UP" 2.66454e-15
 cap "R" "tspc_r_0/GND" 16.129
 cap "tspc_r_1/Qbar" "and_pd_0/Z1" 1.76471
-cap "DOWN" "and_pd_0/Z1" -9.852
-cap "DOWN" "tspc_r_0/GND" 113.28
-cap "tspc_r_0/w_n276_n506#" "tspc_r_0/GND" 9.20833
-cap "tspc_r_0/w_n276_n506#" "and_pd_0/Z1" 0.916667
+cap "and_pd_0/Z1" "DOWN" -9.852
+cap "R" "and_pd_0/Out1" 137.14
+cap "R" "DOWN" 90.78
+cap "tspc_r_0/GND" "DOWN" 113.28
+cap "and_pd_0/Z1" "tspc_r_0/w_n276_n506#" 0.916667
+cap "tspc_r_1/Qbar" "and_pd_0/Out1" 1.71875
+cap "R" "UP" 222.129
+cap "tspc_r_0/GND" "tspc_r_0/w_n276_n506#" 9.20833
+cap "R" "VDD" 56.5714
+cap "R" "tspc_r_0/w_n276_n506#" 71.3216
+cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775
+cap "w_n446_n1456#" "tspc_r_1/Z2" 9.69375
+cap "w_n446_n1456#" "tspc_r_1/Z3" 7.21875
+cap "w_n446_n1456#" "tspc_r_1/Z1" 14.4375
 cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.548
 cap "w_n446_n1456#" "tspc_r_1/VDD" 58.522
-cap "tspc_r_1/Z2" "tspc_r_1/w_n290_n40#" 12.775
-cap "tspc_r_1/Z1" "w_n446_n1456#" 14.4375
-cap "tspc_r_1/Z2" "w_n446_n1456#" 9.69375
-cap "tspc_r_1/Z3" "w_n446_n1456#" 7.21875
 cap "tspc_r_1/Qbar" "and_pd_0/Out1" 5.42143
 cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 9.4875
-cap "w_n446_n1456#" "and_pd_0/Out1" 7.21875
-cap "w_n446_n1456#" "tspc_r_1/Qbar" 7.21875
-cap "w_n446_n1456#" "tspc_r_1/Q" 7.21875
-cap "w_n446_n1456#" "tspc_r_1/Qbar1" 7.21875
-cap "VDD" "tspc_r_1/VDD" 43.262
+cap "and_pd_0/Out1" "w_n446_n1456#" 7.21875
+cap "tspc_r_1/Qbar" "w_n446_n1456#" 7.21875
+cap "tspc_r_1/Q" "w_n446_n1456#" 7.21875
+cap "tspc_r_1/Qbar1" "w_n446_n1456#" 7.21875
+cap "tspc_r_1/VDD" "w_n446_n1456#" 54.6607
+cap "tspc_r_1/VDD" "VDD" 43.262
 cap "tspc_r_1/Q" "and_pd_0/A" 2.15625
-cap "w_n446_n1456#" "tspc_r_1/VDD" 54.6607
 cap "w_n446_n1456#" "and_pd_0/Out" 11.4354
 cap "w_n446_n1456#" "and_pd_0/Out1" 7.21875
 cap "w_n446_n1456#" "VDD" 18.7589

gds/prescaler.ext

diff --git a/gds/prescaler.ext b/gds/prescaler.ext
index 3849697..a1abc1a 100644
--- a/gds/prescaler.ext
+++ b/gds/prescaler.ext
@@ -41,8 +41,23 @@
 node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_3590_420#" "m1_2700_2190#" 23.5
+cap "li_2030_420#" "m2_970_460#" 17.38
+cap "li_450_280#" "clk" 28.72
+cap "w_1930_2072#" "li_1980_2130#" 10.7855
+cap "w_390_530#" "m4_350_1060#" 2.9032
+cap "li_3590_420#" "Out" 716.418
+cap "mc1" "m2_970_460#" 37.515
+cap "li_2030_420#" "Out" 197.97
+cap "li_n310_330#" "clk" 28.72
+cap "mc1" "m1_2700_2190#" 63.2343
+cap "li_1980_2130#" "m2_970_460#" 138.025
+cap "li_n310_330#" "li_3590_420#" 92.2845
+cap "li_n310_330#" "mc1" 37.515
 cap "GND" "m4_2730_1520#" 23.6471
+cap "w_1930_2072#" "VDD" 1.964
 cap "m2_970_460#" "VDD" 42
+cap "w_1930_2072#" "m2_970_460#" 42.9324
 cap "Out" "GND" 27.9
 cap "mc1" "m4_2730_1520#" 23.175
 cap "mc1" "VDD" 41.675
@@ -50,120 +65,105 @@
 cap "mc1" "m4_350_1060#" 84.575
 cap "li_3590_420#" "m2_970_460#" 183.333
 cap "Out" "m1_2700_2190#" 27.465
-cap "li_3590_420#" "m1_2700_2190#" 23.5
-cap "li_2030_420#" "m2_970_460#" 17.38
-cap "li_450_280#" "clk" 28.72
-cap "w_390_530#" "m4_350_1060#" 2.9032
-cap "w_1930_2072#" "VDD" 1.964
-cap "li_3590_420#" "Out" 716.418
-cap "mc1" "m2_970_460#" 37.515
-cap "li_2030_420#" "Out" 197.97
-cap "li_n310_330#" "clk" 28.72
-cap "mc1" "m1_2700_2190#" 63.2343
-cap "li_1980_2130#" "m2_970_460#" 138.025
-cap "w_1930_2072#" "m2_970_460#" 42.9324
-cap "li_n310_330#" "li_3590_420#" 92.2845
-cap "li_n310_330#" "mc1" 37.515
 cap "w_1930_2072#" "mc1" 2.7456
-cap "w_1930_2072#" "li_1980_2130#" 10.7855
+cap "nand_1/a_280_n230#" "tspc_2/Z4" 106.442
+cap "nand_1/a_280_n230#" "GND" 124.422
+cap "nand_1/a_280_n230#" "nand_1/z1" 153.26
 cap "nand_1/a_280_n230#" "tspc_2/Z3" 75.9225
+cap "nand_1/OUT" "tspc_2/Z4" 12.3811
 cap "nand_1/OUT" "nand_1/z1" 2.11538
 cap "nand_1/a_280_n230#" "tspc_2/Z2" 56.16
-cap "nand_1/a_280_n230#" "tspc_2/Z4" 106.442
 cap "nand_1/A" "nand_1/vdd!" 44.8462
-cap "nand_1/OUT" "tspc_2/Z4" 12.3811
 cap "nand_1/A" "nand_1/a_280_n230#" 13.02
 cap "clk" "nand_1/a_280_n230#" 94.1074
-cap "nand_1/OUT" "nand_1/A" 29.5549
 cap "nand_1/OUT" "nand_1/a_280_n230#" 165.278
 cap "clk" "nand_1/A" 17.42
 cap "nand_1/OUT" "tspc_2/vdd!" 45.9643
+cap "nand_1/OUT" "nand_1/A" 29.5549
 cap "nand_1/OUT" "clk" 127.12
-cap "nand_1/a_280_n230#" "GND" 124.422
-cap "nand_1/a_280_n230#" "nand_1/z1" 153.26
-cap "tspc_1/gnd!" "tspc_1/Z2" 16.9342
-cap "tspc_1/Z2" "tspc_2/a_740_n680#" 5.4
-cap "tspc_1/vdd!" "tspc_2/vdd!" 38.2105
 cap "tspc_1/gnd!" "tspc_1/D" 51.0882
-cap "li_3590_420#" "tspc_2/a_740_n680#" 150.46
-cap "tspc_1/gnd!" "li_3590_420#" 198.939
-cap "tspc_1/D" "tspc_2/a_740_n680#" 32.1861
-cap "tspc_1/Z4" "tspc_2/a_740_n680#" 4.09091
-cap "tspc_2/a_740_n680#" "tspc_1/a_300_n150#" 129.16
-cap "tspc_1/D" "tspc_1/Z2" 85.89
-cap "li_3590_420#" "tspc_1/Z2" 43.32
-cap "tspc_2/Z4" "li_3590_420#" 107.677
+cap "tspc_2/a_740_n680#" "tspc_1/Z2" 5.4
 cap "tspc_1/gnd!" "tspc_2/a_630_n680#" 17.3347
+cap "tspc_1/a_300_n150#" "tspc_1/D" 177.533
+cap "tspc_2/vdd!" "tspc_1/vdd!" 38.2105
+cap "tspc_1/a_300_n150#" "tspc_2/Z3" 198.42
+cap "tspc_2/a_740_n680#" "tspc_1/D" 32.1861
+cap "tspc_1/Z4" "tspc_2/a_740_n680#" 4.09091
+cap "tspc_2/Z4" "li_3590_420#" 107.677
+cap "tspc_1/Z2" "li_3590_420#" 43.32
+cap "tspc_1/D" "li_3590_420#" 142.71
+cap "tspc_2/a_740_n680#" "tspc_1/a_300_n150#" 129.16
+cap "tspc_1/D" "tspc_1/Z3" 3.50402
+cap "tspc_2/Z3" "li_3590_420#" 57.62
+cap "tspc_1/Z4" "li_3590_420#" 51.8
+cap "tspc_1/gnd!" "li_3590_420#" 198.939
+cap "tspc_1/a_300_n150#" "li_3590_420#" 83.0378
+cap "tspc_2/a_740_n680#" "li_3590_420#" 150.46
+cap "tspc_1/D" "tspc_1/Z2" 85.89
 cap "tspc_1/D" "tspc_1/Z1" 39.5832
 cap "tspc_1/D" "tspc_1/vdd!" 59.1194
-cap "li_3590_420#" "tspc_1/D" 142.71
-cap "tspc_1/Z3" "tspc_1/D" 3.50402
-cap "li_3590_420#" "tspc_2/Z3" 57.62
-cap "tspc_1/Z4" "li_3590_420#" 51.8
+cap "tspc_1/gnd!" "tspc_1/Z2" 16.9342
 cap "tspc_1/Z4" "tspc_1/D" 102.17
-cap "li_3590_420#" "tspc_1/a_300_n150#" 83.0378
-cap "tspc_1/D" "tspc_1/a_300_n150#" 177.533
-cap "tspc_2/Z3" "tspc_1/a_300_n150#" 198.42
-cap "Out" "tspc_1/a_300_n150#" 179.587
-cap "tspc_1/a_740_n680#" "Out" 82.65
-cap "tspc_1/Z4" "tspc_2/a_740_n680#" 1.92857
-cap "tspc_1/Q" "tspc_1/Z4" -74.25
-cap "tspc_1/Q" "GND" 218.86
 cap "tspc_1/Z3" "tspc_1/Q" 156.507
 cap "tspc_1/Z2" "tspc_1/Q" 12.84
 cap "Out" "GND" 39.1
+cap "Out" "tspc_1/Q" 50.6
 cap "Out" "tspc_1/Z4" 76.1789
 cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785
-cap "Out" "tspc_1/Q" 50.6
 cap "Out" "tspc_1/Z3" 59.529
 cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
 cap "Out" "tspc_1/Z2" 9.99
-cap "nand_1/vdd!" "mc1" 162.542
+cap "Out" "tspc_1/a_300_n150#" 179.587
+cap "tspc_1/a_740_n680#" "Out" 82.65
+cap "tspc_1/Z4" "tspc_2/a_740_n680#" 1.92857
+cap "tspc_1/Q" "GND" 218.86
+cap "tspc_1/Q" "tspc_1/Z4" -74.25
+cap "nand_1/VDD" "mc1" 9.165
 cap "tspc_0/Q" "nand_1/vdd!" 32.5248
 cap "nand_1/VDD" "nand_1/vdd!" -3.656
-cap "nand_1/VDD" "mc1" 9.165
-cap "nand_1/vdd!" "tspc_2/Z2" 10
+cap "nand_1/vdd!" "mc1" 162.542
 cap "tspc_2/Z2" "mc1" 46.8
-cap "nand_0/OUT" "tspc_0/Z1" 99.6765
-cap "nand_0/a_280_n230#" "VDD" 7.33333
-cap "nand_0/OUT" "VDD" 272.242
-cap "nand_0/VDD" "nand_0/OUT" 8.1659
+cap "nand_1/vdd!" "tspc_2/Z2" 10
 cap "nand_0/OUT" "nand_0/a_280_n230#" 9.77778
 cap "tspc_2/Q" "tspc_1/Z1" 10.4211
 cap "tspc_2/Z2" "mc1" 17.4522
 cap "VDD" "tspc_2/Q" 44.0676
 cap "tspc_1/Z2" "mc1" 18
-cap "tspc_0/Z2" "mc1" 53.3571
 cap "nand_0/VDD" "mc1" 24.5544
 cap "VDD" "mc1" 414.897
+cap "tspc_0/Z2" "mc1" 53.3571
 cap "nand_0/VDD" "tspc_0/a_300_n150#" 2.0976
 cap "tspc_0/a_300_n150#" "VDD" 166.667
 cap "VDD" "tspc_1/Z2" 4.35484
 cap "tspc_0/a_300_n150#" "nand_0/OUT" -6.9
-cap "nand_0/OUT" "nand_0/z1" 6
 cap "VDD" "tspc_0/Z2" 10
 cap "nand_0/VDD" "VDD" -11.884
+cap "nand_0/OUT" "nand_0/z1" 6
+cap "nand_0/OUT" "tspc_0/Z1" 99.6765
+cap "nand_0/VDD" "nand_0/OUT" 8.1659
+cap "nand_0/a_280_n230#" "VDD" 7.33333
+cap "nand_0/OUT" "VDD" 272.242
+cap "VDD" "tspc_1/Z2" 11.9132
 cap "mc1" "tspc_1/Z2" 46.2522
 cap "GND" "VDD" 39.5155
-cap "VDD" "tspc_0/a_300_n150#" 1.66667
 cap "mc1" "VDD" 227.695
 cap "nand_0/a_280_n230#" "VDD" 13.125
 cap "nand_0/OUT" "nand_0/z1" 2.2
-cap "mc1" "nand_0/OUT" 22.3793
 cap "nand_0/VDD" "VDD" -6.44
+cap "mc1" "nand_0/OUT" 22.3793
 cap "nand_0/a_280_n230#" "nand_0/OUT" 0.275
-cap "nand_0/a_280_n230#" "tspc_1/a_740_n680#" 1.36364
 cap "nand_0/VDD" "mc1" 9.555
-cap "VDD" "tspc_1/Z2" 11.9132
+cap "tspc_0/a_300_n150#" "VDD" 1.66667
+cap "tspc_1/a_740_n680#" "nand_0/a_280_n230#" 1.36364
 cap "tspc_0/Q" "tspc_0/a_740_n680#" 18.4737
-cap "nand_0/OUT" "nand_0/z1" 14
 cap "nand_0/OUT" "tspc_0/Z1" 20.5588
 cap "nand_0/OUT" "tspc_0/vdd!" 47.4
 cap "nand_0/OUT" "tspc_0/Z4" 7.71692
 cap "nand_0/OUT" "GND" -5.32907e-15
-cap "tspc_0/Z3" "nand_0/OUT" 5.25747
-cap "tspc_0/a_300_n150#" "nand_0/OUT" 0.18
-cap "tspc_0/w_n140_n70#" "nand_0/OUT" 3.0525
+cap "nand_0/OUT" "tspc_0/a_300_n150#" 0.18
+cap "nand_0/OUT" "tspc_0/Z3" 5.25747
+cap "nand_0/z1" "nand_0/OUT" 14
+cap "nand_0/OUT" "tspc_0/w_n140_n70#" 3.0525
 cap "nand_0/OUT" "nand_0/z1" 3.85
 merge "tspc_0/gnd!" "tspc_0/GND" -422.046 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -213980 -2050 0 0 0 0
 merge "tspc_0/GND" "nand_0/GND"

gds/ro_complete.ext

diff --git a/gds/ro_complete.ext b/gds/ro_complete.ext
index 6a0ea1f..5511178 100644
--- a/gds/ro_complete.ext
+++ b/gds/ro_complete.ext
@@ -29,99 +29,99 @@
 cap "cbank_1/a0" "cbank_1/switch_5/vout" 46.5385
 cap "cbank_1/a2" "cbank_1/switch_3/vout" 46.5385
 cap "cbank_1/a1" "cbank_1/switch_4/vout" 46.5385
-cap "cbank_1/switch_2/vout" "cbank_1/a3" 46.5385
-cap "cbank_1/a4" "cbank_1/switch_1/vout" 46.5385
+cap "cbank_1/a3" "cbank_1/switch_2/vout" 46.5385
 cap "cbank_1/a5" "cbank_1/switch_0/vout" 12.6923
-cap "li_7140_1400#" "cbank_1/switch_0/vin" 23.3333
-cap "cbank_1/switch_0/vout" "cbank_1/a5" 33.8462
-cap "cbank_2/gnd!" "cbank_1/v" 86.7059
-cap "a0" "cbank_2/gnd!" 180.338
+cap "cbank_1/a4" "cbank_1/switch_1/vout" 46.5385
+cap "cbank_1/switch_0/vin" "li_7140_1400#" 23.3333
+cap "cbank_1/a5" "cbank_1/switch_0/vout" 33.8462
+cap "cbank_1/v" "cbank_2/gnd!" 86.7059
+cap "cbank_1/v" "cbank_2/gnd!" 275.882
 cap "a0" "cbank_2/switch_4/vin" 21.2667
+cap "a0" "cbank_2/gnd!" 180.338
 cap "a0" "cbank_1/v" 53.41
-cap "cbank_2/gnd!" "cbank_1/v" 275.882
-cap "a1" "cbank_1/v" 53.41
 cap "cbank_2/switch_4/vout" "cbank_1/v" 275.882
 cap "cbank_2/switch_4/vout" "a2" 59.4701
 cap "cbank_2/switch_3/vin" "a1" 23.0602
 cap "cbank_2/switch_4/vout" "a1" 208.707
+cap "a1" "cbank_1/v" 53.41
 cap "cbank_1/v" "cbank_2/gnd!" 275.882
-cap "cbank_1/v" "a3" 53.41
-cap "cbank_1/v" "a2" 53.41
-cap "cbank_2/switch_1/vin" "a3" 11.1279
-cap "a2" "cbank_2/switch_2/vin" 22.9222
-cap "a3" "cbank_2/gnd!" 191.198
 cap "a2" "cbank_2/gnd!" 123.77
-cap "a4" "cbank_2/switch_0/vin" 20.0419
-cap "a4" "cbank_2/switch_1/vout" 189.52
-cap "a3" "cbank_2/switch_1/vin" 11.1279
-cap "li_7140_1400#" "cbank_2/switch_1/vout" 275.882
+cap "a3" "cbank_2/gnd!" 191.198
+cap "a2" "cbank_1/v" 53.41
+cap "a3" "cbank_1/v" 53.41
+cap "a2" "cbank_2/switch_2/vin" 22.9222
+cap "cbank_2/switch_1/vin" "a3" 11.1279
+cap "cbank_2/switch_1/vout" "li_7140_1400#" 275.882
+cap "cbank_2/switch_0/vin" "a4" 20.0419
 cap "a4" "li_7140_1400#" 53.41
-cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126
+cap "cbank_2/switch_1/vout" "a4" 189.52
+cap "cbank_2/switch_1/vin" "a3" 11.1279
 cap "cbank_2/switch_0/vout" "w_7764_n10666#" 162.097
+cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126
 cap "cbank_2/switch_0/vout" "li_7140_1400#" 233.936
 cap "cbank_2/switch_0/vout" "a5" 124.366
-cap "cbank_2/gnd!" "w_7764_n10666#" 45.6818
+cap "w_7764_n10666#" "cbank_2/gnd!" 45.6818
+cap "cbank_2/a0" "cbank_2/switch_4/vin" 107.067
 cap "cbank_2/a0" "cbank_2/switch_5/vout" 249.402
-cap "cbank_2/switch_4/vin" "cbank_2/a0" 107.067
-cap "cbank_2/a1" "cbank_2/switch_3/vin" 116.096
-cap "cbank_2/a1" "cbank_2/switch_4/vout" 290.488
-cap "cbank_2/a2" "cbank_2/switch_3/vout" 150.151
+cap "cbank_2/switch_3/vout" "cbank_2/a2" 150.151
+cap "cbank_2/switch_3/vin" "cbank_2/a1" 116.096
+cap "cbank_2/switch_4/vout" "cbank_2/a1" 290.488
 cap "cbank_2/a3" "cbank_2/switch_1/vin" 56.0233
+cap "cbank_2/a2" "cbank_2/switch_2/vin" 115.401
+cap "cbank_2/a2" "cbank_2/switch_3/vout" 103.613
 cap "cbank_2/gnd!" "cbank_2/a3" 265.538
-cap "cbank_2/switch_2/vin" "cbank_2/a2" 115.401
-cap "cbank_2/switch_3/vout" "cbank_2/a2" 103.613
 cap "cbank_2/a4" "cbank_2/switch_0/vin" 100.901
 cap "cbank_2/a4" "cbank_2/switch_1/vout" 263.078
-cap "a3" "cbank_2/switch_1/vin" 56.0233
-cap "cbank_2/switch_0/vout" "cbank_2/a5" 12.6923
-cap "cbank_2/a5" "cbank_2/switch_0/vout" 143.972
-cap "cbank_2/v" "cbank_0/gnd!" 47.5484
+cap "cbank_2/a5" "cbank_2/switch_0/vout" 12.6923
+cap "cbank_2/switch_1/vin" "a3" 56.0233
+cap "cbank_2/switch_0/vout" "cbank_2/a5" 143.972
+cap "cbank_0/gnd!" "cbank_2/v" 47.5484
 cap "cbank_2/a0" "cbank_2/v" 53.41
-cap "cbank_2/v" "cbank_0/gnd!" 151.29
+cap "cbank_0/gnd!" "cbank_2/v" 151.29
 cap "cbank_0/gnd!" "cbank_2/v" 151.29
 cap "cbank_2/a1" "cbank_2/v" 53.41
 cap "cbank_2/a3" "cbank_2/v" 53.41
 cap "cbank_2/a2" "cbank_2/v" 53.41
 cap "cbank_2/w_3654_n56#" "cbank_2/v" 151.29
-cap "cbank_0/gnd!" "li_4080_1390#" 151.29
 cap "cbank_2/a4" "li_4080_1390#" 53.41
-cap "cbank_0/gnd!" "li_4080_1390#" 41.6979
+cap "cbank_0/gnd!" "li_4080_1390#" 151.29
+cap "li_4080_1390#" "cbank_0/gnd!" 41.6979
 cap "li_4080_1390#" "cbank_2/switch_0/vin" 133.875
 cap "cbank_0/gnd!" "cbank_2/v" 47.5484
-cap "cbank_0/gnd!" "cbank_2/v" 151.29
 cap "cbank_0/switch_4/vin" "a0" 81.7667
-cap "cbank_0/gnd!" "a0" 294.969
-cap "cbank_0/switch_4/vout" "cbank_2/v" 151.29
+cap "a0" "cbank_0/gnd!" 294.969
+cap "cbank_0/gnd!" "cbank_2/v" 151.29
 cap "cbank_0/switch_4/vout" "a2" 118.019
 cap "cbank_0/switch_3/vin" "a1" 88.6627
 cap "cbank_0/switch_4/vout" "a1" 346.555
-cap "cbank_0/switch_1/vin" "a3" 42.7849
-cap "cbank_0/switch_2/vin" "a2" 88.1317
-cap "cbank_0/gnd!" "a3" 314.948
-cap "cbank_0/gnd!" "a2" 182.319
+cap "cbank_0/switch_4/vout" "cbank_2/v" 151.29
+cap "a3" "cbank_0/gnd!" 314.948
+cap "a2" "cbank_0/gnd!" 182.319
+cap "a3" "cbank_0/switch_1/vin" 42.7849
+cap "a2" "cbank_0/switch_2/vin" 88.1317
 cap "cbank_0/gnd!" "cbank_2/v" 151.29
-cap "cbank_0/switch_1/vout" "li_4080_1390#" 151.29
+cap "li_4080_1390#" "cbank_0/switch_1/vout" 151.29
 cap "cbank_0/switch_0/vin" "a4" 77.0576
 cap "cbank_0/switch_1/vout" "a4" 311.879
 cap "cbank_0/switch_1/vin" "a3" 42.7849
-cap "cbank_0/switch_0/vout" "w_7764_n10666#" 193.269
-cap "cbank_0/switch_0/vout" "li_4080_1390#" 438.698
 cap "cbank_0/switch_0/vout" "li_7140_1400#" 142.26
 cap "cbank_0/switch_0/vout" "a5" 186.594
+cap "w_7764_n10666#" "cbank_0/switch_0/vout" 193.269
+cap "li_4080_1390#" "cbank_0/switch_0/vout" 438.698
 cap "cbank_0/gnd!" "w_7764_n10666#" 45.6818
-cap "a0" "cbank_0/switch_5/vout" 134.77
 cap "a0" "cbank_0/switch_4/vin" 46.5667
+cap "a0" "cbank_0/switch_5/vout" 134.77
 cap "a2" "cbank_0/switch_3/vout" 91.603
 cap "a1" "cbank_0/switch_3/vin" 50.494
 cap "a1" "cbank_0/switch_4/vout" 152.64
-cap "a3" "cbank_0/switch_1/vin" 24.3663
 cap "a3" "cbank_0/switch_2/vout" 141.788
 cap "a2" "cbank_0/switch_2/vin" 50.1916
 cap "a2" "cbank_0/switch_3/vout" 45.0645
-cap "a4" "cbank_0/switch_0/vin" 43.8848
-cap "a4" "cbank_0/switch_1/vout" 140.718
+cap "a3" "cbank_0/switch_1/vin" 24.3663
 cap "cbank_0/switch_1/vin" "a3" 24.3663
 cap "cbank_0/a5" "cbank_0/switch_0/vout" 12.6923
+cap "a4" "cbank_0/switch_0/vin" 43.8848
+cap "a4" "cbank_0/switch_1/vout" 140.718
 cap "a5" "cbank_0/switch_0/vout" 81.7433
 cap "ro_var_extend_0/gnd" "cbank_0/v" 151.9
 cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97
@@ -129,18 +129,18 @@
 cap "ro_var_extend_0/gnd" "li_4080_1390#" 291.625
 cap "ro_var_extend_0/gnd" "li_7140_1400#" 292.345
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
-cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
 cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
+cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
-cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
 cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
+cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 322.14
+cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" -11.167
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 394.496
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/w_n120_n750#" -86.444
-cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" -11.167
 cap "ro_var_extend_0/gnd" "w_7764_n10666#" -79.966
 merge "cbank_0/a4" "cbank_2/a4" -1880.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -239756 -6032 0 0 0 0 0 0 0 0 0 0 0 0
 merge "cbank_2/a4" "cbank_1/a4"

gds/ro_var_extend.ext

diff --git a/gds/ro_var_extend.ext b/gds/ro_var_extend.ext
index 67b0a17..6ed9388 100644
--- a/gds/ro_var_extend.ext
+++ b/gds/ro_var_extend.ext
@@ -21,16 +21,16 @@
 node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
 node "vdd" 21463 18367.8 6020 900 li 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "gnd" 0 0 5980 -160 li 2627212 34004 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vdd" "out2" 235.622
-cap "vdd" "out1" 230.66
-cap "vdd" "out3" 230.554
 cap "out1" "out2" 40.8506
 cap "w_n120_n750#" "vcont" 140.194
 cap "out3" "out2" 1263.05
 cap "w_n120_n750#" "out2" 789.263
 cap "out3" "out1" 1156.32
+cap "vdd" "out2" 235.622
 cap "w_n120_n750#" "out1" 569.035
+cap "vdd" "out1" 230.66
 cap "w_n120_n750#" "out3" 215.464
+cap "vdd" "out3" 230.554
 device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0
 device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0
 device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0

gds/switch.ext

diff --git a/gds/switch.ext b/gds/switch.ext
index d24029c..b9c796c 100644
--- a/gds/switch.ext
+++ b/gds/switch.ext
@@ -12,7 +12,7 @@
 node "vin" 1082 0 -150 1410 li 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0
 node "vcont" 1139 384.82 20 1590 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n216_n26#" 0 0 -216 -26 pw 719144 3948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vcont" "vin" 8.25
 cap "vin" "vout" 420
 cap "vcont" "vout" 16.5
+cap "vcont" "vin" 8.25
 device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "w_n216_n26#" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0

gds/tspc.ext

diff --git a/gds/tspc.ext b/gds/tspc.ext
index 92a448d..9a3d78f 100644
--- a/gds/tspc.ext
+++ b/gds/tspc.ext
@@ -32,43 +32,24 @@
 node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0
 node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n146_n706#" 0 0 -146 -706 pw 475604 4208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vdd!" "Z1" 583.229
-cap "gnd!" "a_630_n680#" 610.469
-cap "Z4" "a_630_n680#" 121.707
-cap "Q" "a_630_n680#" 36.6667
-cap "Z4" "gnd!" 441.644
-cap "Z3" "a_630_n680#" 54.2903
-cap "Q" "gnd!" 289.808
-cap "Z2" "a_630_n680#" 6.6
-cap "Z3" "gnd!" 265.176
 cap "Z3" "Z4" 651.52
 cap "Z2" "gnd!" 156.712
 cap "Z2" "Z4" 361.112
-cap "Z3" "Q" 52.8649
-cap "Z1" "Z4" 3.38462
-cap "Z2" "Z3" 161.5
-cap "Z1" "Z3" 62.0085
-cap "Z1" "Z2" 1068.12
-cap "w_n140_n70#" "a_300_n150#" 0.665
-cap "w_n140_n70#" "vdd!" 85.4425
-cap "w_n140_n70#" "a_740_n680#" 18.5775
-cap "w_n140_n70#" "Q" 6.845
-cap "w_n140_n70#" "Z3" 2.3125
-cap "w_n140_n70#" "Z2" 14.44
-cap "w_n140_n70#" "Z1" 4.1625
-cap "D" "a_300_n150#" 132.679
-cap "vdd!" "a_300_n150#" 20.3736
-cap "a_740_n680#" "a_300_n150#" 12.4103
-cap "vdd!" "D" 19.4229
-cap "a_740_n680#" "vdd!" 515.003
 cap "a_300_n150#" "a_630_n680#" 9.625
+cap "Z3" "Q" 52.8649
+cap "w_n140_n70#" "vdd!" 85.4425
 cap "a_300_n150#" "gnd!" 22.7597
+cap "Z1" "Z4" 3.38462
+cap "w_n140_n70#" "a_740_n680#" 18.5775
 cap "D" "gnd!" 27.9314
 cap "a_300_n150#" "Z4" 118.945
+cap "Z2" "Z3" 161.5
 cap "a_740_n680#" "a_630_n680#" 190.867
 cap "D" "Z4" 97.7372
+cap "Z1" "Z3" 62.0085
 cap "a_740_n680#" "gnd!" 224.895
 cap "vdd!" "Z4" 7.7
+cap "Z1" "Z2" 1068.12
 cap "a_300_n150#" "Z3" 446.312
 cap "a_740_n680#" "Z4" 82.0167
 cap "D" "Z3" 46.1286
@@ -80,6 +61,25 @@
 cap "D" "Z1" 26.4
 cap "vdd!" "Z2" 359.159
 cap "a_740_n680#" "Z3" 334.495
+cap "vdd!" "Z1" 583.229
+cap "D" "a_300_n150#" 132.679
+cap "vdd!" "a_300_n150#" 20.3736
+cap "a_740_n680#" "a_300_n150#" 12.4103
+cap "vdd!" "D" 19.4229
+cap "a_740_n680#" "vdd!" 515.003
+cap "gnd!" "a_630_n680#" 610.469
+cap "w_n140_n70#" "Q" 6.845
+cap "Z4" "a_630_n680#" 121.707
+cap "w_n140_n70#" "Z3" 2.3125
+cap "Q" "a_630_n680#" 36.6667
+cap "Z4" "gnd!" 441.644
+cap "w_n140_n70#" "Z2" 14.44
+cap "Z3" "a_630_n680#" 54.2903
+cap "Q" "gnd!" 289.808
+cap "w_n140_n70#" "Z1" 4.1625
+cap "Z2" "a_630_n680#" 6.6
+cap "Z3" "gnd!" 265.176
+cap "w_n140_n70#" "a_300_n150#" 0.665
 device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "w_n146_n706#" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0
 device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "w_n146_n706#" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "w_n146_n706#" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0

gds/tspc_r.ext

diff --git a/gds/tspc_r.ext b/gds/tspc_r.ext
index 04a3ff2..a67a8e7 100644
--- a/gds/tspc_r.ext
+++ b/gds/tspc_r.ext
@@ -41,52 +41,44 @@
 node "D" 1470 418.74 -290 -120 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
 node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "w_n276_n506#" 0 0 -276 -506 pw 462144 4448 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "Z4" "z5" 42.0885
-cap "GND" "z5" 558.112
-cap "GND" "Z4" 527.304
-cap "R" "GND" 35.3744
-cap "Qbar" "GND" 138.6
-cap "Z2" "Z4" 137.657
-cap "VDD" "z5" 6.6
-cap "Z2" "GND" 142.361
-cap "Q" "z5" 33
-cap "Z2" "R" 208.97
-cap "Qbar1" "z5" 203.056
-cap "VDD" "GND" 17.6
-cap "Z3" "z5" 110
-cap "Q" "GND" 263.95
-cap "Z3" "Z4" 201.943
-cap "Qbar1" "GND" 157.761
-cap "clk" "z5" 38.3774
-cap "VDD" "Qbar" 237.6
 cap "Z1" "Z2" 709.991
-cap "Qbar1" "R" 11.3571
-cap "Z3" "GND" 324.951
-cap "clk" "Z4" 18.15
-cap "Q" "Qbar" 213.204
-cap "VDD" "Z2" 95.0921
-cap "Qbar1" "Qbar" 7.54286
-cap "clk" "GND" 37.5833
-cap "Z3" "R" 137.379
-cap "VDD" "Z1" 316.564
-cap "D" "GND" 14.4375
-cap "clk" "R" 508.778
+cap "z5" "VDD" 6.6
+cap "z5" "Q" 33
+cap "z5" "Qbar1" 203.056
+cap "GND" "VDD" 17.6
+cap "z5" "Z3" 110
+cap "GND" "Q" 263.95
+cap "Z4" "Z3" 201.943
+cap "GND" "Qbar1" 157.761
+cap "z5" "clk" 38.3774
+cap "Qbar" "VDD" 237.6
+cap "R" "Qbar1" 11.3571
+cap "GND" "Z3" 324.951
+cap "Z4" "clk" 18.15
+cap "Qbar" "Q" 213.204
+cap "Z2" "VDD" 95.0921
+cap "Qbar" "Qbar1" 7.54286
+cap "GND" "clk" 37.5833
+cap "R" "Z3" 137.379
+cap "Z1" "VDD" 316.564
+cap "GND" "D" 14.4375
+cap "R" "clk" 508.778
+cap "Z2" "Z3" 249.04
+cap "R" "D" 16.14
+cap "Z1" "Z3" 85.3
+cap "Z2" "clk" 187.91
+cap "Z1" "clk" 170.927
+cap "Qbar" "w_n290_n40#" 1.85
+cap "Z2" "D" 47.3222
+cap "Z2" "w_n290_n40#" 3.04
+cap "Z1" "w_n290_n40#" 7.4
 cap "Q" "VDD" 334.95
-cap "Z3" "Z2" 249.04
-cap "D" "R" 16.14
 cap "Qbar1" "VDD" 315.732
-cap "Z3" "Z1" 85.3
-cap "clk" "Z2" 187.91
 cap "Z3" "VDD" 509.325
-cap "clk" "Z1" 170.927
-cap "w_n290_n40#" "Qbar" 1.85
-cap "D" "Z2" 47.3222
 cap "Qbar1" "Q" 109.835
 cap "clk" "VDD" 129.37
-cap "w_n290_n40#" "Z2" 3.04
 cap "Z3" "Q" 28.6775
 cap "D" "VDD" 38.5
-cap "w_n290_n40#" "Z1" 7.4
 cap "Z3" "Qbar1" 379.384
 cap "w_n290_n40#" "VDD" 7.4
 cap "clk" "Qbar1" 121.715
@@ -96,6 +88,14 @@
 cap "w_n290_n40#" "Z3" 11.56
 cap "D" "clk" 31.5485
 cap "w_n290_n40#" "clk" 10.355
+cap "Z4" "z5" 42.0885
+cap "GND" "z5" 558.112
+cap "GND" "Z4" 527.304
+cap "R" "GND" 35.3744
+cap "Qbar" "GND" 138.6
+cap "Z2" "Z4" 137.657
+cap "Z2" "GND" 142.361
+cap "Z2" "R" 208.97
 device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "w_n276_n506#" "Q" 60 0 "GND" 180 0 "Qbar" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "w_n276_n506#" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "w_n276_n506#" "Z3" 60 0 "GND" 180 0 "z5" 180 0

gds/user_analog_project_wrapper.ext

diff --git a/gds/user_analog_project_wrapper.ext b/gds/user_analog_project_wrapper.ext
index b6ac580..25b782b 100644
--- a/gds/user_analog_project_wrapper.ext
+++ b/gds/user_analog_project_wrapper.ext
@@ -5,11 +5,11 @@
 scale 1000 1 500000
 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
 use filter filter_0 1 0 291454 0 1 660398
-use ro_complete ro_complete_0 1 0 31596 0 1 681444
-use pd pd_0 1 0 87306 0 1 647408
+use cp cp_0 1 0 196464 0 1 608714
+use cp cp_1 1 0 531400 0 1 683270
 use divider divider_0 1 0 163690 0 1 648664
-use cp cp_0 1 0 531400 0 1 683270
-use cp cp_1 1 0 196464 0 1 608714
+use pd pd_0 1 0 87306 0 1 647408
+use ro_complete ro_complete_0 1 0 31596 0 1 681444
 port "io_analog[4]" 42 329294 702300 334294 704800 m5
 port "io_analog[4]" 42 318994 702300 323994 704800 m5
 port "io_analog[5]" 43 227594 702300 232594 704800 m5
@@ -1393,65 +1393,65 @@
 node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
 node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "io_analog[0]" "vdda1" 18313.2
-cap "io_analog[1]" "vdda1" 23516.2
-cap "io_clamp_high[0]" "io_analog[4]" 525
+cap "io_analog[5]" "io_analog[5]" 21250
 cap "io_analog[2]" "vdda1" 219.25
+cap "io_analog[6]" "io_analog[6]" 26250
 cap "io_analog[3]" "vssa1" 6389.64
-cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "io_analog[5]" "io_analog[5]" 21250
 cap "io_analog[2]" "vssa1" 9275.17
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "io_clamp_high[0]" "io_analog[4]" 525
+cap "w_534750_683750#" "w_534690_682780#" 224.4
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
 cap "io_analog[4]" "io_clamp_low[0]" 525
-cap "io_analog[1]" "io_analog[0]" 12301.4
 cap "io_clamp_high[1]" "io_analog[5]" 525
 cap "io_clamp_low[1]" "io_clamp_high[1]" 525
-cap "w_534750_683750#" "w_534690_682780#" 224.4
 cap "io_analog[5]" "io_clamp_low[1]" 525
 cap "io_clamp_high[2]" "io_analog[6]" 525
 cap "io_analog[4]" "io_analog[4]" 26250
 cap "io_clamp_low[2]" "io_clamp_high[2]" 525
 cap "io_analog[6]" "io_clamp_low[2]" 525
 cap "io_analog[4]" "io_analog[4]" 26250
+cap "io_analog[1]" "io_analog[0]" 12301.4
 cap "io_analog[5]" "io_analog[5]" 26250
 cap "io_analog[5]" "io_analog[5]" 26250
 cap "io_analog[4]" "io_analog[4]" 21250
 cap "io_analog[6]" "io_analog[6]" 26250
+cap "io_analog[0]" "vdda1" 18313.2
 cap "io_analog[4]" "io_analog[4]" 21250
-cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_analog[6]" "io_analog[6]" 26250
-cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "cp_0/down" "cp_0/w_6344_n2866#" 439.89
-cap "cp_0/gnd!" "io_analog[1]" -20.89
-cap "cp_0/vbias" "cp_0/gnd!" 6.79412
-cap "cp_0/vbias" "cp_0/gnd!" 8.73529
-cap "cp_0/gnd!" "cp_0/vbias" 6.79412
-cap "cp_0/a_10_n50#" "cp_0/vbias" 31.68
-cap "cp_0/vbias" "cp_0/gnd!" 8.73529
-cap "w_534750_683750#" "cp_0/a_3060_0#" 99.11
-cap "w_534750_683750#" "cp_0/a_3060_0#" 243.801
-cap "cp_0/a_1710_0#" "w_534750_683750#" 37.5
-cap "cp_0/a_3060_0#" "w_534690_682780#" 1083.86
-cap "w_534690_682780#" "w_534750_683750#" -39.04
-cap "cp_0/a_3060_0#" "w_534690_682780#" 904.4
+cap "io_analog[1]" "vdda1" 23516.2
+cap "cp_1/w_6344_n2866#" "cp_1/down" 439.89
+cap "cp_1/gnd!" "io_analog[1]" -20.89
+cap "cp_1/vbias" "cp_1/gnd!" 6.79412
+cap "cp_1/vbias" "cp_1/gnd!" 8.73529
+cap "cp_1/vbias" "cp_1/gnd!" 6.79412
+cap "cp_1/vbias" "cp_1/gnd!" 8.73529
+cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68
+cap "w_534750_683750#" "cp_1/a_1710_0#" 37.5
+cap "w_534750_683750#" "cp_1/a_3060_0#" 99.11
+cap "w_534750_683750#" "cp_1/a_3060_0#" 243.801
+cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86
+cap "w_534750_683750#" "w_534690_682780#" -39.04
+cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4
 cap "w_534750_683750#" "w_534690_682780#" -28
-cap "cp_0/a_3060_0#" "w_534690_682780#" 50.49
-cap "cp_0/a_3060_0#" "w_534690_682780#" 119.25
+cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49
+cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25
 cap "w_534750_683750#" "w_534690_682780#" -15.96
-cap "cp_0/vdd!" "cp_0/vdd!" 27.826
-cap "cp_0/vdd!" "cp_0/upbar" 248.023
-merge "cp_0/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0
-merge "vdda1" "cp_0/vdd!"
-merge "cp_0/vdd!" "w_534690_682780#"
+cap "cp_1/vdd!" "cp_1/vdd!" 27.826
+cap "cp_1/vdd!" "cp_1/upbar" 248.023
+merge "cp_1/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0
+merge "vdda1" "cp_1/vdd!"
+merge "cp_1/vdd!" "w_534690_682780#"
 merge "w_534690_682780#" "w_534750_683750#"
-merge "cp_0/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0
+merge "cp_1/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0
 merge "vssa1" "ro_complete_0/w_7764_n10666#"
 merge "ro_complete_0/w_7764_n10666#" "divider_0/w_n966_n46#"
 merge "divider_0/w_n966_n46#" "pd_0/w_n446_n1456#"
-merge "pd_0/w_n446_n1456#" "filter_0/v"
-merge "filter_0/v" "cp_1/gnd!"
-merge "cp_1/gnd!" "VSUBS"
-merge "cp_0/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0
-merge "cp_0/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0
-merge "cp_0/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
-merge "cp_0/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "pd_0/w_n446_n1456#" "filter_0/gnd"
+merge "filter_0/gnd" "cp_0/gnd!"
+merge "cp_0/gnd!" "VSUBS"
+merge "cp_1/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0
+merge "cp_1/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "cp_1/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "cp_1/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0

gds/user_analog_project_wrapper.gds

diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 951a100..449fa39 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ

mag/and.ext

diff --git a/mag/and.ext b/mag/and.ext
index ebd9764..5c44853 100644
--- a/mag/and.ext
+++ b/mag/and.ext
@@ -15,27 +15,27 @@
 node "out1" 6488 1253.5 10 20 pdif 0 0 0 0 0 0 0 0 32000 960 83200 2400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3340 0 0 136500 4640 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 1983 2469.6 -170 -30 nw 0 0 0 0 823200 3640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "vdd!" "A" 13.5882
+cap "out1" "A" 13.5179
+cap "out1" "vdd!" 1441.54
+cap "VDD" "vdd!" 48.86
+cap "VDD" "out1" 6.1975
+cap "gnd!" "Z1" 409.78
+cap "OUT" "Z1" 43.6452
 cap "OUT" "gnd!" 198
 cap "B" "Z1" 67.1786
-cap "VDD" "vdd!" 48.86
-cap "A" "gnd!" 57.75
 cap "B" "OUT" 8.8
+cap "A" "gnd!" 57.75
 cap "vdd!" "Z1" 7.96552
-cap "VDD" "out1" 6.1975
 cap "out1" "Z1" 356.371
 cap "vdd!" "gnd!" 13.8886
 cap "out1" "gnd!" 226.769
 cap "vdd!" "OUT" 574.768
-cap "out1" "OUT" 261.752
 cap "A" "B" 87.6201
+cap "out1" "OUT" 261.752
 cap "vdd!" "B" 13.5882
-cap "vdd!" "A" 13.5882
-cap "out1" "B" 176.792
-cap "out1" "A" 13.5179
-cap "out1" "vdd!" 1441.54
-cap "gnd!" "Z1" 409.78
 cap "VDD" "OUT" 2.3125
-cap "OUT" "Z1" 43.6452
+cap "out1" "B" 176.792
 device msubckt sky130_fd_pr__nfet_01v8 480 -670 481 -669 l=30 w=300 "VSUBS" "out1" 60 0 "gnd!" 300 0 "OUT" 300 0
 device msubckt sky130_fd_pr__nfet_01v8 230 -670 231 -669 l=30 w=400 "VSUBS" "B" 60 0 "Z1" 400 0 "out1" 400 0
 device msubckt sky130_fd_pr__nfet_01v8 -20 -670 -19 -669 l=30 w=400 "VSUBS" "A" 60 0 "gnd!" 400 0 "Z1" 400 0

mag/and_pd.ext

diff --git a/mag/and_pd.ext b/mag/and_pd.ext
index 3fe6c54..1eeaaea 100644
--- a/mag/and_pd.ext
+++ b/mag/and_pd.ext
@@ -26,16 +26,16 @@
 cap "a_n60_n30#" "Out" 277.2
 cap "Out1" "Out" 188.1
 cap "B" "Out" 8.8
-cap "A" "GND" 57.75
 cap "Out1" "a_n60_n30#" 1023.37
 cap "B" "a_n60_n30#" 18.7
-cap "VDD" "Out" 1.85
 cap "B" "Out1" 271.254
-cap "A" "a_n60_n30#" 18.7
-cap "VDD" "a_n60_n30#" 37.17
-cap "A" "Out1" 13.5179
-cap "VDD" "Out1" 3.7
-cap "A" "B" 75.0211
+cap "GND" "A" 57.75
+cap "Out" "VDD" 1.85
+cap "a_n60_n30#" "A" 18.7
+cap "a_n60_n30#" "VDD" 37.17
+cap "Out1" "A" 13.5179
+cap "Out1" "VDD" 3.7
+cap "B" "A" 75.0211
 device msubckt sky130_fd_pr__nfet_01v8 520 -470 521 -469 l=30 w=180 "VSUBS" "Out1" 60 0 "GND" 180 0 "Out" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 270 -470 271 -469 l=30 w=180 "VSUBS" "B" 60 0 "Z1" 180 0 "Out1" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 20 -470 21 -469 l=30 w=180 "VSUBS" "A" 60 0 "GND" 180 0 "Z1" 180 0

mag/cbank.ext

diff --git a/mag/cbank.ext b/mag/cbank.ext
index 403bc7a..f640bb9 100644
--- a/mag/cbank.ext
+++ b/mag/cbank.ext
@@ -1,4 +1,4 @@
-timestamp 1640959530
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
@@ -26,6 +26,7 @@
 node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0
 node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "gnd!" 0 0 950 -1660 ppd 0 0 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0
+cap "a_6660_n30#" "v" 1301.39
 cap "a_5640_n30#" "v" 1301.39
 cap "a_5640_n30#" "a_6660_n30#" 191.52
 cap "a_4660_n30#" "v" 1301.39
@@ -34,10 +35,9 @@
 cap "a_2730_n30#" "v" 1301.39
 cap "a_3680_n30#" "a_4660_n30#" 199.5
 cap "a_2730_n30#" "a_3680_n30#" 199.5
-cap "a_1720_n30#" "li_1720_n30#" 18.13
 cap "v" "li_1720_n30#" 1301.39
 cap "a_2730_n30#" "li_1720_n30#" 199.5
-cap "a_6660_n30#" "v" 1301.39
+cap "a_1720_n30#" "li_1720_n30#" 18.13
 device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1920 0 "a_6660_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1920 0 "a_5640_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1920 0 "a_4660_n30#" 1440 0
@@ -45,20 +45,20 @@
 device csubckt sky130_fd_pr__cap_mim_m3_1 2540 590 2541 591 w=560 l=560 "None" "v" 1920 0 "a_2730_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1920 0 "li_1720_n30#" 1440 0
 device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3760 0 "gnd!" 1440 0
-cap "switch_1/vin" "switch_1/vcont" -136.5
+cap "switch_1/vin" "switch_1/vout" -0.157143
+cap "switch_1/vcont" "switch_1/vin" -136.5
 cap "switch_0/vcont" "switch_0/vout" 4.23077
 cap "switch_0/vcont" "switch_0/vin" 83.635
-cap "switch_1/vout" "switch_1/vin" -0.157143
-cap "switch_2/vcont" "switch_2/vout" 4.23077
-cap "switch_2/vcont" "switch_2/vin" 83.635
-cap "switch_1/vcont" "switch_1/vout" 4.23077
-cap "switch_1/vcont" "switch_1/vin" 83.635
+cap "switch_2/vout" "switch_2/vcont" 4.23077
+cap "switch_2/vin" "switch_2/vcont" 83.635
+cap "switch_1/vout" "switch_1/vcont" 4.23077
+cap "switch_1/vin" "switch_1/vcont" 83.635
 cap "switch_3/vcont" "switch_3/vout" 4.23077
 cap "switch_3/vcont" "switch_3/vin" 83.635
+cap "switch_4/vcont" "switch_4/vin" 83.635
 cap "switch_5/vcont" "switch_5/vout" 4.23077
 cap "switch_5/vcont" "switch_5/vin" 83.635
 cap "switch_4/vcont" "switch_4/vout" 4.23077
-cap "switch_4/vcont" "switch_4/vin" 83.635
 merge "switch_5/VSUBS" "switch_5/vout" -332.789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -21300 -442 0 0 0 0
 merge "switch_5/vout" "switch_4/VSUBS"
 merge "switch_4/VSUBS" "switch_4/vout"

mag/cp.ext

diff --git a/mag/cp.ext b/mag/cp.ext
index e5b68d0..ed425d7 100644
--- a/mag/cp.ext
+++ b/mag/cp.ext
@@ -20,23 +20,23 @@
 node "upbar" 658 1347.77 6750 -50 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0
 node "vdd!" 18302 139352 -830 -170 nw 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0
 substrate "gnd!" 0 0 -370 -2840 ndif 0 0 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0
+cap "vdd!" "a_3060_n2840#" 320.4
+cap "upbar" "down" 20.625
 cap "out" "a_1710_0#" 841.733
 cap "a_1710_n2840#" "a_1710_0#" 828.847
 cap "a_10_n50#" "a_1710_0#" 41.6842
+cap "vdd!" "a_6370_0#" 402.828
 cap "a_1710_n2840#" "out" 606.81
+cap "vdd!" "a_3060_0#" 1788.27
 cap "vdd!" "a_1710_0#" 714.147
 cap "vdd!" "out" 376.075
 cap "upbar" "a_1710_n2840#" 291.6
 cap "vdd!" "a_1710_n2840#" 254.08
 cap "vdd!" "a_10_n50#" 530.297
-cap "a_7110_0#" "vdd!" 42.55
-cap "a_6370_0#" "vdd!" 402.828
-cap "vdd!" "upbar" 149.92
-cap "a_3060_0#" "vdd!" 1788.27
-cap "a_1710_0#" "down" 320.4
-cap "vdd!" "a_3060_n2840#" 320.4
-cap "upbar" "down" 20.625
 cap "a_10_n50#" "vbias" 192.9
+cap "vdd!" "upbar" 149.92
+cap "vdd!" "a_7110_0#" 42.55
+cap "a_1710_0#" "down" 320.4
 device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0
 device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0
 device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0

mag/divider.ext

diff --git a/mag/divider.ext b/mag/divider.ext
index be95062..cfd9f22 100644
--- a/mag/divider.ext
+++ b/mag/divider.ext
@@ -1,4 +1,4 @@
-timestamp 1640957771
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
@@ -40,241 +40,241 @@
 node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0
 node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0
 substrate "a_n940_n20#" 0 0 -940 -20 ppd 0 0 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vdd" "vdd" 51.2353
 cap "vdd" "vdd" 20.1
-cap "li_3980_680#" "gnd" 24.425
-cap "li_3980_680#" "gnd" 27.1625
-cap "w_2780_1920#" "m4_7030_1860#" 40.0711
-cap "m4_7020_30#" "li_5560_680#" 24.425
-cap "w_2780_1920#" "vdd" 0.84
-cap "w_2780_1920#" "vdd" 9.82
-cap "w_2780_1920#" "vdd" 4.08
-cap "w_2780_1920#" "vdd" 8.88
 cap "li_5740_3250#" "li_5460_820#" 128.305
-cap "li_5740_3250#" "li_6130_3350#" 68.1032
-cap "li_5740_3250#" "mc2" 22.679
+cap "li_5560_680#" "m4_7020_30#" 24.425
+cap "li_6130_3350#" "li_5740_3250#" 68.1032
+cap "mc2" "li_5740_3250#" 22.679
+cap "w_2780_1920#" "li_3310_1810#" 24.0375
+cap "w_2780_1920#" "li_5740_3250#" 72.945
+cap "w_2780_1920#" "li_6130_3350#" 7.215
+cap "w_2780_1920#" "li_2870_2670#" 76.8485
 cap "li_7140_680#" "m1_5770_3360#" 19.2857
+cap "gnd" "li_3980_680#" 24.425
 cap "li_5560_680#" "m1_5770_3360#" 16.875
-cap "w_2780_1920#" "m1_5770_3360#" 53.84
+cap "gnd" "li_3980_680#" 27.1625
 cap "li_5560_680#" "li_7140_680#" 437.5
-cap "li_7040_820#" "m1_5770_3360#" 90
-cap "li_3980_680#" "li_5560_680#" 782.5
-cap "Out" "li_7140_680#" 23.5
-cap "li_7040_820#" "li_5560_680#" 15
-cap "li_5740_3250#" "vdd" 27.9
-cap "li_3310_1810#" "vdd" 35.39
-cap "li_5740_3250#" "vdd" 27.9
-cap "mc2" "gnd" 27.9
-cap "li_6130_3350#" "m1_5770_3360#" 136.842
-cap "li_5740_3250#" "m1_5770_3360#" 286.375
-cap "li_6130_3350#" "w_2780_1920#" 7.215
-cap "mc2" "m1_5770_3360#" 35.7143
+cap "vdd" "li_5740_3250#" 27.9
+cap "vdd" "li_3310_1810#" 35.39
+cap "vdd" "li_5740_3250#" 27.9
+cap "m4_7030_1860#" "w_2780_1920#" 40.0711
+cap "vdd" "w_2780_1920#" 0.84
+cap "m1_5770_3360#" "li_7040_820#" 90
+cap "li_5560_680#" "li_3980_680#" 782.5
+cap "li_7140_680#" "Out" 23.5
+cap "vdd" "w_2780_1920#" 9.82
+cap "vdd" "w_2780_1920#" 4.08
+cap "li_5560_680#" "li_7040_820#" 15
+cap "vdd" "w_2780_1920#" 8.88
+cap "m1_5770_3360#" "li_5740_3250#" 286.375
+cap "gnd" "mc2" 27.9
+cap "m1_5770_3360#" "li_6130_3350#" 136.842
+cap "li_5560_680#" "li_5740_3250#" 21.9534
+cap "m1_5770_3360#" "mc2" 35.7143
+cap "li_7140_680#" "mc2" 61.52
+cap "m1_5770_3360#" "w_2780_1920#" 53.84
 cap "li_5460_820#" "li_3980_680#" 20
-cap "li_3310_1810#" "w_2780_1920#" 24.0375
-cap "mc2" "li_7140_680#" 61.52
-cap "li_5740_3250#" "li_5560_680#" 21.9534
-cap "li_2870_2670#" "w_2780_1920#" 76.8485
-cap "li_5740_3250#" "w_2780_1920#" 72.945
 cap "li_5740_3250#" "li_3980_680#" 22.5
 cap "vdd" "vdd" 33.5
+cap "vdd" "vdd" 51.2353
 cap "a_n940_n20#" "prescaler_0/nand_0/A" 17.3684
 cap "a_n940_n20#" "prescaler_0/tspc_0/a_630_n680#" 9.78378
 cap "a_n940_n20#" "prescaler_0/GND" 21.945
 cap "a_n940_n20#" "prescaler_0/tspc_0/Z2" 27.6618
-cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
 cap "a_n940_n20#" "prescaler_0/tspc_1/Z2" 27.6618
 cap "a_n940_n20#" "prescaler_0/tspc_1/GND" 30.14
-cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
-cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
+cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
+cap "a_n940_n20#" "tspc_0/GND" 21.945
+cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
 cap "tspc_0/D" "tspc_0/Z4" 35.0633
-cap "tspc_0/a_300_n150#" "tspc_0/GND" -3.55271e-15
 cap "tspc_0/D" "tspc_0/Z2" 141.466
+cap "tspc_0/a_300_n150#" "tspc_0/GND" -3.55271e-15
 cap "tspc_0/D" "tspc_0/GND" 413.181
 cap "tspc_0/D" "tspc_0/Z3" 1.36364
 cap "a_n940_n20#" "tspc_0/Z2" 27.6618
 cap "tspc_0/w_n140_n70#" "tspc_0/GND" 0.12
-cap "a_n940_n20#" "tspc_0/GND" 21.945
-cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189
 cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985
-cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17
-cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795
-cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
-cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 145.525
-cap "tspc_1/GND" "tspc_1/Z2" 7.81579
-cap "tspc_1/D" "tspc_1/Z4" 33.0938
-cap "tspc_1/D" "tspc_1/Z2" 213.298
-cap "tspc_1/a_300_n150#" "tspc_1/Z4" 30.4615
-cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823
-cap "a_n940_n20#" "tspc_1/Z2" 27.6618
-cap "tspc_1/a_300_n150#" "tspc_1/Z2" 25.8231
+cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375
+cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195
 cap "tspc_1/GND" "tspc_0/a_630_n680#" 7.61538
 cap "tspc_1/D" "tspc_0/a_630_n680#" 5.45455
 cap "tspc_1/D" "tspc_1/GND" 346.096
-cap "a_n940_n20#" "tspc_1/GND" 23.265
-cap "a_n940_n20#" "tspc_0/a_630_n680#" 9.78378
 cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583
 cap "tspc_1/a_300_n150#" "tspc_1/GND" 21.2143
-cap "tspc_0/a_740_n680#" "tspc_1/GND" 281.141
 cap "tspc_1/D" "tspc_1/Z3" 1.36364
+cap "tspc_0/a_740_n680#" "tspc_1/GND" 281.141
+cap "tspc_1/Z2" "tspc_1/GND" 7.81579
+cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795
 cap "tspc_1/a_300_n150#" "tspc_1/D" 70.641
-cap "tspc_2/gnd!" "tspc_2/Z2" 7.81579
+cap "a_n940_n20#" "tspc_0/a_630_n680#" 9.78378
+cap "a_n940_n20#" "tspc_1/GND" 23.265
+cap "tspc_1/Z4" "tspc_1/D" 33.0938
+cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 145.525
+cap "tspc_1/Z2" "tspc_1/D" 213.298
+cap "tspc_1/Z4" "tspc_1/a_300_n150#" 30.4615
+cap "tspc_1/Z4" "tspc_0/a_740_n680#" 20.5714
+cap "tspc_1/Z2" "tspc_0/a_740_n680#" 112.823
+cap "tspc_1/Z2" "tspc_1/a_300_n150#" 25.8231
+cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065
+cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17
+cap "tspc_1/Z2" "a_n940_n20#" 27.6618
 cap "tspc_2/D" "tspc_2/Z3" 0.681818
+cap "a_n940_n20#" "tspc_2/Z2" 12.6176
+cap "a_n940_n20#" "tspc_2/gnd!" 30.14
+cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378
 cap "tspc_2/D" "tspc_2/Z4" 20.0553
-cap "tspc_2/D" "tspc_2/Z2" 309.898
 cap "tspc_2/a_300_n150#" "tspc_2/Z4" 30.4615
+cap "tspc_2/gnd!" "tspc_2/Z2" 7.81579
+cap "tspc_2/gnd!" "tspc_1/a_630_n680#" 7.61538
 cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882
+cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
+cap "tspc_2/D" "tspc_2/Z2" 309.898
+cap "tspc_2/D" "tspc_2/gnd!" 339.551
 cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18
 cap "tspc_2/a_300_n150#" "tspc_2/Z2" 25.8231
-cap "a_n940_n20#" "tspc_2/Z2" 12.6176
-cap "tspc_2/gnd!" "tspc_1/a_630_n680#" 7.61538
-cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622
-cap "tspc_2/D" "tspc_2/gnd!" 339.551
 cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107
 cap "tspc_2/a_300_n150#" "tspc_2/gnd!" 21.2143
-cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378
 cap "tspc_1/a_740_n680#" "tspc_2/gnd!" 440.385
-cap "a_n940_n20#" "tspc_2/gnd!" 30.14
 cap "tspc_2/a_300_n150#" "tspc_2/D" 70.641
 cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619
 cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 155.525
 cap "tspc_2/w_n140_n70#" "tspc_1/a_740_n680#" 0.065
+cap "tspc_2/a_630_n680#" "a_n940_n20#" 9.78378
+cap "tspc_2/Z4" "tspc_2/D" 17.815
+cap "tspc_2/GND" "a_n940_n20#" 23.265
+cap "tspc_2/Z2" "a_n940_n20#" 15.0441
+cap "tspc_2/Z4" "li_5560_680#" 10.5882
 cap "tspc_2/D" "tspc_2/Q" 20.775
 cap "tspc_2/D" "tspc_2/Z3" 0.681818
-cap "tspc_2/D" "tspc_2/a_630_n680#" 159.583
-cap "tspc_2/D" "tspc_2/GND" 450.398
-cap "tspc_2/D" "tspc_2/Z4" 17.815
 cap "tspc_2/D" "tspc_2/a_300_n150#" -1.77636e-15
-cap "a_n940_n20#" "tspc_2/Z2" 15.0441
-cap "a_n940_n20#" "tspc_2/GND" 23.265
-cap "a_n940_n20#" "tspc_2/a_630_n680#" 9.78378
-cap "tspc_2/Z4" "li_5560_680#" 10.5882
-cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 78.0797
+cap "tspc_2/a_630_n680#" "tspc_2/D" 159.583
+cap "tspc_2/GND" "tspc_2/D" 450.398
 cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/A" 12.2938
 cap "a_n940_n20#" "prescaler_0/nand_0/A" 14.7632
 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/vdd!" 4.57853
 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/D" -2.84217e-14
 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557
+cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 78.0797
+cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557
 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z2" -1.77636e-15
 cap "prescaler_0/nand_0/VDD" "prescaler_0/mc1" 2.73
-cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557
-cap "prescaler_0/tspc_0/Z1" "prescaler_0/nand_0/VDD" -2.4869e-14
+cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z1" -2.4869e-14
 cap "prescaler_0/tspc_1/vdd!" "prescaler_0/mc1" 73.8879
 cap "prescaler_0/tspc_1/vdd!" "prescaler_0/nand_1/a_280_n230#" 14.3654
-cap "prescaler_0/tspc_1/Z3" "prescaler_0/tspc_1/vdd!" -2.37588e-14
-cap "prescaler_0/tspc_1/Z1" "prescaler_0/tspc_1/vdd!" 2.84217e-14
-cap "prescaler_0/tspc_1/Z2" "prescaler_0/tspc_1/vdd!" 5.68434e-14
-cap "tspc_0/vdd!" "prescaler_0/GND" 244.839
-cap "tspc_0/vdd!" "prescaler_0/mc1" 2.6129
-cap "tspc_0/vdd!" "tspc_0/Z2" 10
-cap "tspc_0/vdd!" "tspc_0/Z1" -2.4869e-14
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z3" -2.37588e-14
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z1" 3.19744e-14
+cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z2" 6.92779e-14
+cap "prescaler_0/mc1" "tspc_0/vdd!" 2.6129
+cap "tspc_0/Z1" "tspc_0/vdd!" -2.4869e-14
+cap "tspc_0/Z2" "tspc_0/vdd!" 10
 cap "tspc_0/vdd!" "and_0/OUT" 7.5
-cap "tspc_0/vdd!" "prescaler_0/tspc_1/Q" 19.25
-cap "tspc_0/vdd!" "prescaler_0/tspc_1/a_740_n680#" 114.95
+cap "prescaler_0/tspc_1/Q" "tspc_0/vdd!" 19.25
+cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/vdd!" 114.95
+cap "prescaler_0/GND" "tspc_0/vdd!" 244.839
+cap "tspc_1/w_n140_n70#" "tspc_1/vdd!" -3.46
 cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 75.365
 cap "tspc_1/vdd!" "tspc_1/a_300_n150#" 93.7845
 cap "tspc_1/vdd!" "tspc_0/a_740_n680#" 177.528
 cap "tspc_1/a_300_n150#" "tspc_1/Z1" 7
 cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 4.63
 cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927
-cap "tspc_1/w_n140_n70#" "tspc_1/vdd!" -3.46
-cap "tspc_2/vdd!" "tspc_1/Z3" -2.37588e-14
-cap "tspc_2/vdd!" "tspc_1/Z2" 3.10862e-14
-cap "nor_0/vdd!" "tspc_1/a_740_n680#" 13.3333
-cap "tspc_2/vdd!" "tspc_1/a_740_n680#" 76.5957
-cap "tspc_2/vdd!" "nor_0/vdd!" 224.245
 cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351
 cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 75.365
 cap "tspc_2/vdd!" "tspc_2/Z2" 4.44089e-16
 cap "tspc_2/vdd!" "tspc_2/Z1" 2.2482e-14
 cap "tspc_2/vdd!" "tspc_2/a_300_n150#" 93.7845
+cap "tspc_2/vdd!" "tspc_1/Z3" -2.37588e-14
+cap "tspc_2/vdd!" "tspc_1/Z2" 3.10862e-14
+cap "nor_0/vdd!" "tspc_1/a_740_n680#" 13.3333
+cap "tspc_2/vdd!" "tspc_1/a_740_n680#" 76.5957
+cap "tspc_2/vdd!" "nor_0/vdd!" 224.245
 cap "tspc_2/a_300_n150#" "tspc_2/Z1" 7
-cap "tspc_2/vdd!" "tspc_2/Z3" -2.37588e-14
 cap "tspc_2/vdd!" "tspc_2/Q" -5.32907e-14
+cap "tspc_2/vdd!" "tspc_2/Z3" -2.37588e-14
 cap "tspc_2/vdd!" "tspc_2/Z2" 3.73035e-14
 cap "tspc_2/vdd!" "tspc_2/Z1" -1.90958e-14
 cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125
 cap "w_n140_1520#" "prescaler_0/tspc_2/vdd!" 6.56545
 cap "w_n140_1520#" "prescaler_0/tspc_2/Q" 27.2014
+cap "prescaler_0/tspc_2/a_630_n680#" "mc2" 328.675
+cap "prescaler_0/GND" "mc2" 319.267
+cap "prescaler_0/tspc_2/Z2" "mc2" 136.815
 cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z1" -2.4869e-14
 cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167
 cap "a_n940_n20#" "prescaler_0/GND" 12.1359
 cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Q" 9.57252
 cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/a_740_n680#" -1.13687e-13
 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806
-cap "prescaler_0/tspc_2/a_630_n680#" "mc2" 328.675
-cap "prescaler_0/GND" "mc2" 319.267
-cap "prescaler_0/tspc_2/Z2" "mc2" 136.815
-cap "prescaler_0/GND" "mc2" 127.942
-cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
-cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 19.9143
 cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/a_280_n230#" 34.0634
-cap "prescaler_0/GND" "a_n940_n20#" 3.58696
-cap "prescaler_0/tspc_2/D" "prescaler_0/nand_1/VDD" 1.13687e-13
+cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 19.9143
+cap "a_n940_n20#" "prescaler_0/GND" 3.58696
+cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/D" 1.13687e-13
+cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
+cap "prescaler_0/GND" "mc2" 127.942
 cap "prescaler_0/tspc_2/Z2" "mc2" -280.235
-cap "prescaler_0/mc1" "and_0/out1" 48.6223
+cap "and_0/VDD" "prescaler_0/GND" 23.0856
+cap "a_n940_n20#" "and_0/Z1" 5.5
+cap "prescaler_0/mc1" "prescaler_0/GND" 22.72
+cap "a_n940_n20#" "prescaler_0/mc1" 3.20833
+cap "a_n940_n20#" "prescaler_0/GND" 5.09291
+cap "and_0/VDD" "prescaler_0/mc1" 0.870968
+cap "and_0/out1" "prescaler_0/mc1" 48.6223
 cap "a_n940_n20#" "and_0/out1" 3.20833
 cap "and_0/Z1" "mc2" 74.215
-cap "prescaler_0/mc1" "mc2" 46.015
 cap "prescaler_0/GND" "mc2" 117.19
-cap "prescaler_0/mc1" "and_0/vdd!" 39.6
-cap "prescaler_0/mc1" "prescaler_0/GND" 22.72
+cap "prescaler_0/mc1" "mc2" 46.015
 cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566
 cap "and_0/B" "mc2" 13.94
 cap "and_0/out1" "mc2" 59.955
-cap "prescaler_0/GND" "and_0/VDD" 23.0856
-cap "and_0/Z1" "a_n940_n20#" 5.5
-cap "prescaler_0/GND" "a_n940_n20#" 5.09291
-cap "prescaler_0/mc1" "and_0/VDD" 0.870968
-cap "prescaler_0/mc1" "a_n940_n20#" 3.20833
-cap "and_0/B" "nor_0/Z1" 181.56
-cap "and_0/A" "and_0/vdd!" 5.32907e-15
-cap "and_0/A" "nor_0/Z1" 22.8782
-cap "and_0/B" "and_0/vdd!" 90.78
-cap "nor_0/A" "and_0/GND" 1.28205
-cap "nor_0/B" "nor_1/B" 2.64706
-cap "and_0/A" "and_0/GND" 16.9459
-cap "a_n940_n20#" "and_0/Z1" 0.916667
-cap "nor_0/B" "nor_0/A" 58.3333
-cap "and_0/B" "nor_0/A" 15.1125
-cap "a_n940_n20#" "and_0/GND" 6.50362
-cap "and_0/A" "nor_0/B" 13.2
+cap "prescaler_0/mc1" "and_0/vdd!" 39.6
+cap "mc2" "nor_0/B" 12.84
 cap "and_0/B" "nor_0/B" 84.4673
 cap "and_0/VDD" "nor_0/A" 0.99
 cap "and_0/B" "and_0/A" 90.78
+cap "mc2" "and_0/A" 161.385
 cap "and_0/VDD" "and_0/B" 4.29
+cap "nor_0/Z1" "and_0/A" 22.8782
 cap "a_n940_n20#" "and_0/A" 7
-cap "and_0/Z1" "mc2" -164.32
-cap "and_0/GND" "mc2" 364.635
-cap "nor_0/A" "mc2" 12.84
-cap "nor_0/B" "mc2" 12.84
+cap "nor_0/Z1" "and_0/B" 181.56
 cap "and_0/GND" "and_0/vdd!" -8.88178e-16
-cap "and_0/A" "mc2" 161.385
+cap "and_0/A" "and_0/vdd!" 5.32907e-15
+cap "and_0/B" "and_0/vdd!" 90.78
+cap "nor_0/A" "and_0/GND" 1.28205
+cap "nor_0/B" "nor_1/B" 2.64706
+cap "mc2" "and_0/Z1" -164.32
+cap "and_0/A" "and_0/GND" 16.9459
+cap "a_n940_n20#" "and_0/Z1" 0.916667
+cap "mc2" "and_0/GND" 364.635
+cap "nor_0/B" "nor_0/A" 58.3333
+cap "mc2" "nor_0/A" 12.84
+cap "and_0/B" "nor_0/A" 15.1125
+cap "a_n940_n20#" "and_0/GND" 6.50362
+cap "and_0/A" "nor_0/B" 13.2
+cap "nor_1/A" "nor_1/Out" 180.039
+cap "nor_1/A" "nor_1/GND" 305.362
+cap "nor_1/B" "nor_1/Out" 41.7957
+cap "nor_1/B" "nor_1/A" 14.5768
 cap "nor_0/VDD" "nor_0/B" -7.41
-cap "nor_0/VDD" "nor_1/Out" 4.29
 cap "a_n940_n20#" "nor_1/Out" 7
 cap "a_n940_n20#" "nor_1/GND" 2
+cap "nor_0/VDD" "nor_1/Out" 4.29
 cap "nor_0/vdd!" "nor_0/B" 90.78
 cap "nor_1/Z1" "nor_0/B" 181.56
 cap "nor_1/Out" "nor_0/B" 90.78
 cap "nor_1/A" "nor_0/B" 15.1125
 cap "nor_1/B" "nor_0/B" 17.7596
-cap "nor_1/A" "nor_1/GND" 305.362
-cap "nor_1/A" "nor_1/Out" 180.039
-cap "nor_1/B" "nor_1/Out" 41.7957
-cap "nor_1/B" "nor_1/A" 14.5768
-cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167
-cap "a_n940_n20#" "prescaler_0/GND" 12.1359
 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806
+cap "prescaler_0/tspc_2/a_630_n680#" "a_n940_n20#" 5.04167
+cap "a_n940_n20#" "prescaler_0/GND" 12.1359
+cap "prescaler_0/GND" "a_n940_n20#" 3.58696
 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5
-cap "a_n940_n20#" "prescaler_0/GND" 3.58696
-cap "a_n940_n20#" "and_0/Z1" 5.5
-cap "a_n940_n20#" "and_0/out1" 3.20833
-cap "a_n940_n20#" "and_0/GND" 9.75595
-cap "a_n940_n20#" "and_0/OUT" 3.20833
+cap "and_0/Z1" "a_n940_n20#" 5.5
+cap "and_0/out1" "a_n940_n20#" 3.20833
+cap "and_0/OUT" "a_n940_n20#" 3.20833
+cap "and_0/GND" "a_n940_n20#" 9.75595
 cap "a_n940_n20#" "and_0/Z1" 0.916667
-cap "a_n940_n20#" "and_0/GND" 29.5
 cap "a_n940_n20#" "nor_0/Out" 7
+cap "a_n940_n20#" "and_0/GND" 29.5
 cap "a_n940_n20#" "nor_1/Out" 7
 cap "a_n940_n20#" "nor_1/GND" 20.3333
 merge "nor_1/GND" "nor_0/gnd!" -270.175 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70100 -2250 0 0 0 0

mag/filter.ext

diff --git a/mag/filter.ext b/mag/filter.ext
index f85e42a..b144548 100644
--- a/mag/filter.ext
+++ b/mag/filter.ext
@@ -1,4 +1,4 @@
-timestamp 1640921877
+timestamp 1640983258
 version 8.3
 tech sky130A
 style ngspice()
@@ -11,16 +11,19 @@
 parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
 parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
 parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l
-node "a_4294_n4798#" 51429 0 4294 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_3976_n5230#" 178 415258 3976 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60480 2008 154056 1592 40000 800 40000 800 177102650 116770 0 0 0 0
-node "a_3976_n4798#" 51429 0 3976 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_3976_n2998#" 382 1341.76 3976 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
-substrate "v" 0 0 -3380 -20660 ppd 0 0 0 0 0 0 0 0 0 0 4732000 72800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51962080 147668 853254 8326 97600 1760 241185900 76920 35214504 24450 0 0 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -19830 -2459 -19829 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -19730 4121 -19729 w=6000 l=6000 "None" "a_3976_n5230#" 22890 0 "v" 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -13520 -2459 -13519 w=6000 l=6000 "None" "a_3976_n5230#" 23680 0 "v" 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -13340 4121 -13339 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 4770 -7130 4771 -7129 w=6000 l=6000 "None" "v" 22120 0 "v" 0 0
-device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0
-device rsubckt sky130_fd_pr__res_xhigh_po 4294 -4798 4295 -4797 l=1800 w=70 "v" "a_4294_n4798#" 0 0 "v" 70 0 "a_3976_n2998#" 70 0
-device rsubckt sky130_fd_pr__res_xhigh_po 3976 -4798 3977 -4797 l=1800 w=70 "v" "a_3976_n4798#" 0 0 "a_3976_n5230#" 70 0 "a_3976_n2998#" 70 0
+node "v" 193 85693.9 4534 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 139680 3148 913254 7546 40000 800 40000 800 35334104 25030 0 0 0 0
+node "a_4534_n4798#" 51429 0 4534 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4216_n5230#" 178 418474 4216 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60480 2008 154056 1592 40000 800 40000 800 178748150 121130 0 0 0 0
+node "a_4216_n4798#" 51429 0 4216 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_4216_n2998#" 382 1030.6 4216 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0
+substrate "gnd" 0 0 -3380 -21770 ppd 0 0 0 0 0 0 0 0 0 0 4867200 74880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53899200 149720 172800 2880 172800 2880 263135300 79980 0 0 0 0 0 0
+cap "a_4216_n5230#" "v" 187.252
+cap "a_4216_n2998#" "v" 311.161
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -20940 -2459 -20939 w=6000 l=6000 "None" "a_4216_n5230#" 22900 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -20840 4471 -20839 w=6000 l=6000 "None" "a_4216_n5230#" 22890 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -14150 -2459 -14149 w=6000 l=6000 "None" "a_4216_n5230#" 23680 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 4470 -13970 4471 -13969 w=6000 l=6000 "None" "a_4216_n5230#" 22900 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 5290 -7130 5291 -7129 w=6000 l=6000 "None" "v" 22120 0 "gnd" 0 0
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_4216_n5230#" 22900 0 "gnd" 0 0
+device rsubckt sky130_fd_pr__res_xhigh_po 4534 -4798 4535 -4797 l=1800 w=70 "gnd" "a_4534_n4798#" 0 0 "v" 70 0 "a_4216_n2998#" 70 0
+device rsubckt sky130_fd_pr__res_xhigh_po 4216 -4798 4217 -4797 l=1800 w=70 "gnd" "a_4216_n4798#" 0 0 "a_4216_n5230#" 70 0 "a_4216_n2998#" 70 0

mag/filter.mag

diff --git a/mag/filter.mag b/mag/filter.mag
index ea65c1d..ced26d6 100644
--- a/mag/filter.mag
+++ b/mag/filter.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1640921877
+timestamp 1640983258
 << psubdiff >>
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 rect -3380 330 -3350 530
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@@ -95,194 +95,202 @@
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 << psubdiffcont >>
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-rect 9910 -20630 10110 -20430
-rect 10940 -20630 11140 -20430
-rect 11660 -20630 11860 -20430
+rect 12010 -7090 12210 -6890
+rect -3350 -8780 -3150 -8580
+rect 12010 -8750 12210 -8550
+rect -3350 -9810 -3150 -9610
+rect 12010 -9780 12210 -9580
+rect -3350 -10840 -3150 -10640
+rect 12010 -10810 12210 -10610
+rect -3350 -11870 -3150 -11670
+rect 12010 -11840 12210 -11640
+rect -3350 -12900 -3150 -12700
+rect 12010 -12870 12210 -12670
+rect -3350 -13930 -3150 -13730
+rect 12010 -13900 12210 -13700
+rect -3350 -15440 -3150 -15240
+rect 12010 -15410 12210 -15210
+rect -3350 -16470 -3150 -16270
+rect 12010 -16440 12210 -16240
+rect -3350 -17500 -3150 -17300
+rect 12010 -17470 12210 -17270
+rect -3350 -18530 -3150 -18330
+rect 12010 -18500 12210 -18300
+rect -3350 -19560 -3150 -19360
+rect 12010 -19530 12210 -19330
+rect -3350 -20590 -3150 -20390
+rect 12010 -20560 12210 -20360
+rect -3350 -21740 -3150 -21540
+rect -2450 -21740 -2250 -21540
+rect -1420 -21740 -1220 -21540
+rect -390 -21740 -190 -21540
+rect 640 -21740 840 -21540
+rect 1670 -21740 1870 -21540
+rect 2700 -21740 2900 -21540
+rect 3300 -21740 3500 -21540
+rect 4150 -21740 4350 -21540
+rect 4630 -21740 4830 -21540
+rect 5110 -21740 5310 -21540
+rect 6140 -21740 6340 -21540
+rect 7170 -21740 7370 -21540
+rect 8200 -21740 8400 -21540
+rect 9230 -21740 9430 -21540
+rect 10260 -21740 10460 -21540
+rect 11290 -21740 11490 -21540
+rect 12010 -21740 12210 -21540
 << xpolycontact >>
-rect 3976 -2998 4046 -2566
-rect 3976 -5230 4046 -4798
-rect 4294 -2998 4364 -2566
-rect 4294 -5230 4364 -4798
+rect 4216 -2998 4286 -2566
+rect 4216 -5230 4286 -4798
+rect 4534 -2998 4604 -2566
+rect 4534 -5230 4604 -4798
 << xpolyres >>
-rect 3976 -4798 4046 -2998
-rect 4294 -4798 4364 -2998
+rect 4216 -4798 4286 -2998
+rect 4534 -4798 4604 -2998
 << locali >>
-rect -3600 530 12130 780
+rect -3600 530 12480 780
 rect -3600 330 -3350 530
 rect -3150 330 -2450 530
 rect -2250 330 -1420 530
@@ -371,17 +381,17 @@
 rect -190 330 640 530
 rect 840 330 1670 530
 rect 1870 330 2700 530
-rect 2900 330 3730 530
-rect 3930 330 4760 530
-rect 4960 330 5790 530
-rect 5990 330 6820 530
-rect 7020 330 7850 530
-rect 8050 330 8880 530
-rect 9080 330 9910 530
-rect 10110 330 10940 530
-rect 11140 330 11660 530
-rect 11860 330 12130 530
-rect -3600 60 12130 330
+rect 2900 330 4080 530
+rect 4280 330 5110 530
+rect 5310 330 6140 530
+rect 6340 330 7170 530
+rect 7370 330 8200 530
+rect 8400 330 9230 530
+rect 9430 330 10260 530
+rect 10460 330 11290 530
+rect 11490 330 12010 530
+rect 12210 330 12480 530
+rect -3600 60 12480 330
 rect -3600 -740 -2880 60
 rect -3600 -940 -3350 -740
 rect -3150 -940 -2880 -740
@@ -389,313 +399,337 @@
 rect -3600 -1970 -3350 -1770
 rect -3150 -1970 -2880 -1770
 rect -3600 -2800 -2880 -1970
-rect 11410 -710 12130 60
-rect 11410 -910 11660 -710
-rect 11860 -910 12130 -710
-rect 11410 -1740 12130 -910
-rect 11410 -1940 11660 -1740
-rect 11860 -1940 12130 -1740
-rect 4100 -2180 4430 -2160
-rect 4100 -2380 4210 -2180
-rect 4410 -2380 4430 -2180
-rect 4100 -2400 4430 -2380
+rect 11760 -710 12480 60
+rect 11760 -910 12010 -710
+rect 12210 -910 12480 -710
+rect 11760 -1740 12480 -910
+rect 11760 -1940 12010 -1740
+rect 12210 -1940 12480 -1740
+rect 4340 -2180 4670 -2160
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+rect 4340 -2400 4670 -2380
 rect -3600 -3000 -3350 -2800
 rect -3150 -3000 -2880 -2800
-rect 11410 -2770 12130 -1940
-rect 11410 -2970 11660 -2770
-rect 11860 -2970 12130 -2770
+rect 11760 -2770 12480 -1940
+rect 11760 -2970 12010 -2770
+rect 12210 -2970 12480 -2770
 rect -3600 -3830 -2880 -3000
 rect -3600 -4030 -3350 -3830
 rect -3150 -4030 -2880 -3830
 rect -3600 -4860 -2880 -4030
-rect 11410 -3800 12130 -2970
-rect 11410 -4000 11660 -3800
-rect 11860 -4000 12130 -3800
+rect 11760 -3800 12480 -2970
+rect 11760 -4000 12010 -3800
+rect 12210 -4000 12480 -3800
 rect -3600 -5060 -3350 -4860
 rect -3150 -5060 -2880 -4860
 rect -3600 -5890 -2880 -5060
-rect 11410 -4830 12130 -4000
-rect 11410 -5030 11660 -4830
-rect 11860 -5030 12130 -4830
+rect 11760 -4830 12480 -4000
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+rect 12210 -5030 12480 -4830
 rect -3600 -6090 -3350 -5890
 rect -3150 -6090 -2880 -5890
 rect -3600 -6920 -2880 -6090
 rect -3600 -7120 -3350 -6920
 rect -3150 -7120 -2880 -6920
-rect -3600 -7950 -2880 -7120
-rect -3600 -8150 -3350 -7950
-rect -3150 -8150 -2880 -7950
-rect -3600 -8980 -2880 -8150
-rect -3600 -9180 -3350 -8980
-rect -3150 -9180 -2880 -8980
-rect -3600 -10010 -2880 -9180
-rect -3600 -10210 -3350 -10010
-rect -3150 -10210 -2880 -10010
-rect -3600 -11040 -2880 -10210
-rect -3600 -11240 -3350 -11040
-rect -3150 -11240 -2880 -11040
-rect -3600 -12070 -2880 -11240
-rect -3600 -12270 -3350 -12070
-rect -3150 -12270 -2880 -12070
-rect -3600 -13100 -2880 -12270
-rect -3600 -13300 -3350 -13100
-rect -3150 -13300 -2880 -13100
-rect -3600 -14130 -2880 -13300
-rect -3600 -14330 -3350 -14130
-rect -3150 -14330 -2880 -14130
-rect -3600 -15160 -2880 -14330
-rect -3600 -15360 -3350 -15160
-rect -3150 -15360 -2880 -15160
-rect -3600 -16190 -2880 -15360
-rect -3600 -16390 -3350 -16190
-rect -3150 -16390 -2880 -16190
-rect -3600 -17220 -2880 -16390
-rect -3600 -17420 -3350 -17220
-rect -3150 -17420 -2880 -17220
-rect -3600 -18250 -2880 -17420
-rect -3600 -18450 -3350 -18250
-rect -3150 -18450 -2880 -18250
-rect -3600 -19280 -2880 -18450
-rect -3600 -19480 -3350 -19280
-rect -3150 -19480 -2880 -19280
-rect -3600 -20180 -2880 -19480
-rect 11410 -5860 12130 -5030
-rect 11410 -6060 11660 -5860
-rect 11860 -6060 12130 -5860
-rect 11410 -6890 12130 -6060
-rect 11410 -7090 11660 -6890
-rect 11860 -7090 12130 -6890
-rect 11410 -7920 12130 -7090
-rect 11410 -8120 11660 -7920
-rect 11860 -8120 12130 -7920
-rect 11410 -8950 12130 -8120
-rect 11410 -9150 11660 -8950
-rect 11860 -9150 12130 -8950
-rect 11410 -9980 12130 -9150
-rect 11410 -10180 11660 -9980
-rect 11860 -10180 12130 -9980
-rect 11410 -11010 12130 -10180
-rect 11410 -11210 11660 -11010
-rect 11860 -11210 12130 -11010
-rect 11410 -12040 12130 -11210
-rect 11410 -12240 11660 -12040
-rect 11860 -12240 12130 -12040
-rect 11410 -13070 12130 -12240
-rect 11410 -13270 11660 -13070
-rect 11860 -13270 12130 -13070
-rect 11410 -14100 12130 -13270
-rect 11410 -14300 11660 -14100
-rect 11860 -14300 12130 -14100
-rect 11410 -15130 12130 -14300
-rect 11410 -15330 11660 -15130
-rect 11860 -15330 12130 -15130
-rect 11410 -16160 12130 -15330
-rect 11410 -16360 11660 -16160
-rect 11860 -16360 12130 -16160
-rect 11410 -17190 12130 -16360
-rect 11410 -17390 11660 -17190
-rect 11860 -17390 12130 -17190
-rect 11410 -18220 12130 -17390
-rect 11410 -18420 11660 -18220
-rect 11860 -18420 12130 -18220
-rect 11410 -19250 12130 -18420
-rect 11410 -19450 11660 -19250
-rect 11860 -19450 12130 -19250
-rect 11410 -20180 12130 -19450
-rect -3600 -20430 12130 -20180
-rect -3600 -20630 -3350 -20430
-rect -3150 -20630 -2450 -20430
-rect -2250 -20630 -1420 -20430
-rect -1220 -20630 -390 -20430
-rect -190 -20630 640 -20430
-rect 840 -20630 1670 -20430
-rect 1870 -20630 2700 -20430
-rect 2900 -20630 3730 -20430
-rect 3930 -20630 4760 -20430
-rect 4960 -20630 5790 -20430
-rect 5990 -20630 6820 -20430
-rect 7020 -20630 7850 -20430
-rect 8050 -20630 8880 -20430
-rect 9080 -20630 9910 -20430
-rect 10110 -20630 10940 -20430
-rect 11140 -20630 11660 -20430
-rect 11860 -20630 12130 -20430
-rect -3600 -20900 12130 -20630
+rect -3600 -8580 -2880 -7120
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+rect -3600 -9610 -2880 -8780
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+rect -3600 -11870 -3350 -11670
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+rect -3600 -12700 -2880 -11870
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+rect -3600 -15240 -2880 -13930
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+rect -3600 -17300 -2880 -16470
+rect -3600 -17500 -3350 -17300
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+rect -3600 -18330 -2880 -17500
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+rect -3600 -19360 -2880 -18530
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+rect -3150 -19560 -2880 -19360
+rect -3600 -20390 -2880 -19560
+rect -3600 -20590 -3350 -20390
+rect -3150 -20590 -2880 -20390
+rect -3600 -21290 -2880 -20590
+rect 11760 -5860 12480 -5030
+rect 11760 -6060 12010 -5860
+rect 12210 -6060 12480 -5860
+rect 11760 -6890 12480 -6060
+rect 11760 -7090 12010 -6890
+rect 12210 -7090 12480 -6890
+rect 11760 -8550 12480 -7090
+rect 11760 -8750 12010 -8550
+rect 12210 -8750 12480 -8550
+rect 11760 -9580 12480 -8750
+rect 11760 -9780 12010 -9580
+rect 12210 -9780 12480 -9580
+rect 11760 -10610 12480 -9780
+rect 11760 -10810 12010 -10610
+rect 12210 -10810 12480 -10610
+rect 11760 -11640 12480 -10810
+rect 11760 -11840 12010 -11640
+rect 12210 -11840 12480 -11640
+rect 11760 -12670 12480 -11840
+rect 11760 -12870 12010 -12670
+rect 12210 -12870 12480 -12670
+rect 11760 -13700 12480 -12870
+rect 11760 -13900 12010 -13700
+rect 12210 -13900 12480 -13700
+rect 11760 -15210 12480 -13900
+rect 11760 -15410 12010 -15210
+rect 12210 -15410 12480 -15210
+rect 11760 -16240 12480 -15410
+rect 11760 -16440 12010 -16240
+rect 12210 -16440 12480 -16240
+rect 11760 -17270 12480 -16440
+rect 11760 -17470 12010 -17270
+rect 12210 -17470 12480 -17270
+rect 11760 -18300 12480 -17470
+rect 11760 -18500 12010 -18300
+rect 12210 -18500 12480 -18300
+rect 11760 -19330 12480 -18500
+rect 11760 -19530 12010 -19330
+rect 12210 -19530 12480 -19330
+rect 11760 -20360 12480 -19530
+rect 11760 -20560 12010 -20360
+rect 12210 -20560 12480 -20360
+rect 11760 -21290 12480 -20560
+rect -3600 -21540 12480 -21290
+rect -3600 -21740 -3350 -21540
+rect -3150 -21740 -2450 -21540
+rect -2250 -21740 -1420 -21540
+rect -1220 -21740 -390 -21540
+rect -190 -21740 640 -21540
+rect 840 -21740 1670 -21540
+rect 1870 -21740 2700 -21540
+rect 2900 -21740 3300 -21540
+rect 3500 -21740 4150 -21540
+rect 4350 -21740 4630 -21540
+rect 4830 -21740 5110 -21540
+rect 5310 -21740 6140 -21540
+rect 6340 -21740 7170 -21540
+rect 7370 -21740 8200 -21540
+rect 8400 -21740 9230 -21540
+rect 9430 -21740 10260 -21540
+rect 10460 -21740 11290 -21540
+rect 11490 -21740 12010 -21540
+rect 12210 -21740 12480 -21540
+rect -3600 -22010 12480 -21740
 << viali >>
-rect 4210 -2380 4410 -2180
-rect 3992 -2981 4030 -2584
-rect 4310 -2981 4348 -2584
-rect 3992 -5212 4030 -4815
-rect 4310 -5212 4348 -4815
-rect 4450 -5110 4610 -4950
-rect 3730 -20630 3930 -20430
+rect 4450 -2380 4650 -2180
+rect 4232 -2981 4270 -2584
+rect 4550 -2981 4588 -2584
+rect 4232 -5212 4270 -4815
+rect 4550 -5212 4588 -4815
+rect 3300 -21740 3500 -21540
+rect 4150 -21740 4350 -21540
+rect 4630 -21740 4830 -21540
 << metal1 >>
-rect 4180 -2180 4650 -2150
-rect 4180 -2380 4210 -2180
-rect 4410 -2380 4650 -2180
-rect 4180 -2410 4650 -2380
-rect 3986 -2580 4036 -2572
-rect 4304 -2580 4354 -2572
-rect 3986 -2584 4354 -2580
-rect 3986 -2981 3992 -2584
-rect 4030 -2981 4310 -2584
-rect 4348 -2981 4354 -2584
-rect 3986 -2990 4354 -2981
-rect 3986 -2993 4036 -2990
-rect 4304 -2993 4354 -2990
-rect 3970 -4803 4000 -4800
-rect 3970 -4810 4036 -4803
-rect 3670 -4815 4036 -4810
-rect 3670 -4950 3992 -4815
-rect 3670 -5110 3710 -4950
-rect 3870 -5110 3992 -4950
-rect 3670 -5212 3992 -5110
-rect 4030 -5212 4036 -4815
-rect 3670 -5224 4036 -5212
-rect 4304 -4810 4354 -4803
-rect 4430 -4810 4650 -2410
-rect 4304 -4815 4650 -4810
-rect 4304 -5212 4310 -4815
-rect 4348 -4950 4650 -4815
-rect 4348 -5110 4450 -4950
-rect 4610 -5110 4650 -4950
-rect 4348 -5212 4650 -5110
-rect 4304 -5224 4650 -5212
-rect 3670 -5230 4000 -5224
-rect 4340 -5230 4650 -5224
-rect 3710 -20430 3950 -20410
-rect 3710 -20630 3730 -20430
-rect 3930 -20630 3950 -20430
-rect 3710 -20650 3950 -20630
+rect 4420 -2180 4920 -2150
+rect 4420 -2380 4450 -2180
+rect 4650 -2380 4920 -2180
+rect 4420 -2410 4920 -2380
+rect 4226 -2580 4276 -2572
+rect 4544 -2580 4594 -2572
+rect 4226 -2584 4594 -2580
+rect 4226 -2981 4232 -2584
+rect 4270 -2981 4550 -2584
+rect 4588 -2981 4594 -2584
+rect 4226 -2990 4594 -2981
+rect 4226 -2993 4276 -2990
+rect 4544 -2993 4594 -2990
+rect 4210 -4803 4240 -4800
+rect 4210 -4810 4276 -4803
+rect 3910 -4815 4276 -4810
+rect 3910 -4950 4232 -4815
+rect 3910 -5110 3950 -4950
+rect 4110 -5110 4232 -4950
+rect 3910 -5212 4232 -5110
+rect 4270 -5212 4276 -4815
+rect 3910 -5224 4276 -5212
+rect 4544 -4810 4594 -4803
+rect 4670 -4810 4920 -2410
+rect 4544 -4815 4980 -4810
+rect 4544 -5212 4550 -4815
+rect 4588 -4960 4980 -4815
+rect 4588 -5120 4680 -4960
+rect 4840 -5120 4980 -4960
+rect 4588 -5212 4980 -5120
+rect 4544 -5224 4980 -5212
+rect 3910 -5230 4240 -5224
+rect 4580 -5230 4980 -5224
+rect 3280 -21540 3520 -21520
+rect 3280 -21740 3300 -21540
+rect 3500 -21740 3520 -21540
+rect 3280 -21760 3520 -21740
+rect 4130 -21540 4370 -21520
+rect 4130 -21740 4150 -21540
+rect 4350 -21740 4370 -21540
+rect 4130 -21760 4370 -21740
+rect 4610 -21540 4850 -21520
+rect 4610 -21740 4630 -21540
+rect 4830 -21740 4850 -21540
+rect 4610 -21760 4850 -21740
 << via1 >>
-rect 3710 -5110 3870 -4950
-rect 4450 -5110 4610 -4950
-rect 3730 -20630 3930 -20430
+rect 3950 -5110 4110 -4950
+rect 4680 -5120 4840 -4960
+rect 3300 -21740 3500 -21540
+rect 4150 -21740 4350 -21540
+rect 4630 -21740 4830 -21540
 << metal2 >>
-rect 3690 -4950 3890 -4930
-rect 3690 -5110 3710 -4950
-rect 3870 -5110 3890 -4950
-rect 3690 -5130 3890 -5110
-rect 4430 -4950 4630 -4930
-rect 4430 -5110 4450 -4950
-rect 4610 -5110 4630 -4950
-rect 4430 -5130 4630 -5110
-rect 3710 -20430 3950 -20410
-rect 3710 -20630 3730 -20430
-rect 3930 -20630 3950 -20430
-rect 3710 -20650 3950 -20630
+rect 3930 -4950 4130 -4930
+rect 3930 -5110 3950 -4950
+rect 4110 -5110 4130 -4950
+rect 3930 -5130 4130 -5110
+rect 4660 -4960 4860 -4940
+rect 4660 -5120 4680 -4960
+rect 4840 -5120 4860 -4960
+rect 4660 -5140 4860 -5120
+rect 3280 -21540 3520 -21520
+rect 3280 -21740 3300 -21540
+rect 3500 -21740 3520 -21540
+rect 3280 -21760 3520 -21740
+rect 4130 -21540 4370 -21520
+rect 4130 -21740 4150 -21540
+rect 4350 -21740 4370 -21540
+rect 4130 -21760 4370 -21740
+rect 4610 -21540 4850 -21520
+rect 4610 -21740 4630 -21540
+rect 4830 -21740 4850 -21540
+rect 4610 -21760 4850 -21740
 << via2 >>
-rect 3710 -5110 3870 -4950
-rect 4450 -5110 4610 -4950
-rect 3730 -20630 3930 -20430
+rect 3950 -5110 4110 -4950
+rect 4680 -5120 4840 -4960
+rect 3300 -21740 3500 -21540
+rect 4150 -21740 4350 -21540
+rect 4630 -21740 4830 -21540
 << metal3 >>
 rect -2560 -6220 3600 -1030
-rect 4610 -4930 10830 -970
-rect 3690 -4950 3890 -4930
-rect 3690 -5110 3710 -4950
-rect 3870 -5110 3890 -4950
-rect 3690 -5130 3890 -5110
-rect 4430 -4950 10830 -4930
-rect 4430 -5110 4450 -4950
-rect 4610 -5110 10830 -4950
-rect 4430 -5130 10830 -5110
-rect 4610 -6220 10830 -5130
-rect -2560 -7270 10830 -6220
-rect -2560 -20010 10180 -7270
-rect 140 -20020 920 -20010
-rect 3710 -20410 3940 -20010
-rect 3710 -20430 3950 -20410
-rect 3710 -20630 3730 -20430
-rect 3930 -20630 3950 -20430
-rect 3710 -20650 3950 -20630
+rect 3930 -4950 4130 -4930
+rect 3930 -5110 3950 -4950
+rect 4110 -5110 4130 -4950
+rect 3930 -5130 4130 -5110
+rect 4660 -4960 4860 -4940
+rect 4660 -5120 4680 -4960
+rect 4840 -5120 4860 -4960
+rect 4660 -5140 4860 -5120
+rect 4960 -6220 11350 -970
+rect -2560 -7520 11350 -6220
+rect -2560 -7900 11180 -7520
+rect -2560 -21120 10530 -7900
+rect 140 -21130 920 -21120
+rect 3190 -21540 4910 -21120
+rect 3190 -21740 3300 -21540
+rect 3500 -21740 4150 -21540
+rect 4350 -21740 4630 -21540
+rect 4830 -21740 4910 -21540
+rect 3190 -21850 4910 -21740
 << via3 >>
-rect 3710 -5110 3870 -4950
-rect 4450 -5110 4610 -4950
+rect 3950 -5110 4110 -4950
+rect 4680 -5120 4840 -4960
 << mimcap >>
 rect -2460 -1170 3540 -1130
 rect -2460 -7090 -2420 -1170
 rect 3500 -7090 3540 -1170
 rect -2460 -7130 3540 -7090
-rect 4770 -1170 10770 -1130
-rect 4770 -7090 4810 -1170
-rect 10730 -7090 10770 -1170
-rect 4770 -7130 10770 -7090
-rect 4120 -7380 10120 -7340
-rect -2460 -7560 3540 -7520
-rect -2460 -13480 -2420 -7560
-rect 3500 -13480 3540 -7560
-rect 4120 -13300 4160 -7380
-rect 10080 -13300 10120 -7380
-rect 4120 -13340 10120 -13300
-rect -2460 -13520 3540 -13480
-rect 4120 -13770 10120 -13730
-rect -2460 -13870 3540 -13830
-rect -2460 -19790 -2420 -13870
-rect 3500 -19790 3540 -13870
-rect 4120 -19690 4160 -13770
-rect 10080 -19690 10120 -13770
-rect 4120 -19730 10120 -19690
-rect -2460 -19830 3540 -19790
+rect 5290 -1170 11290 -1130
+rect 5290 -7090 5330 -1170
+rect 11250 -7090 11290 -1170
+rect 5290 -7130 11290 -7090
+rect 4470 -8010 10470 -7970
+rect -2460 -8190 3540 -8150
+rect -2460 -14110 -2420 -8190
+rect 3500 -14110 3540 -8190
+rect 4470 -13930 4510 -8010
+rect 10430 -13930 10470 -8010
+rect 4470 -13970 10470 -13930
+rect -2460 -14150 3540 -14110
+rect 4470 -14880 10470 -14840
+rect -2460 -14980 3540 -14940
+rect -2460 -20900 -2420 -14980
+rect 3500 -20900 3540 -14980
+rect 4470 -20800 4510 -14880
+rect 10430 -20800 10470 -14880
+rect 4470 -20840 10470 -20800
+rect -2460 -20940 3540 -20900
 << mimcapcontact >>
 rect -2420 -7090 3500 -1170
-rect 4810 -7090 10730 -1170
-rect -2420 -13480 3500 -7560
-rect 4160 -13300 10080 -7380
-rect -2420 -19790 3500 -13870
-rect 4160 -19690 10080 -13770
+rect 5330 -7090 11250 -1170
+rect -2420 -14110 3500 -8190
+rect 4510 -13930 10430 -8010
+rect -2420 -20900 3500 -14980
+rect 4510 -20800 10430 -14880
 << metal4 >>
 rect -2421 -1170 140 -1169
 rect 920 -1170 3501 -1169
 rect -2421 -7090 -2420 -1170
 rect 3500 -4810 3501 -1170
-rect 4809 -1170 7370 -1169
-rect 8150 -1170 10731 -1169
-rect 4809 -4810 4810 -1170
-rect 3500 -4930 3830 -4810
-rect 4490 -4930 4810 -4810
-rect 3500 -4950 3890 -4930
-rect 3500 -5110 3710 -4950
-rect 3870 -5110 3890 -4950
-rect 3500 -5130 3890 -5110
-rect 4430 -4950 4810 -4930
-rect 4430 -5110 4450 -4950
-rect 4610 -5110 4810 -4950
-rect 4430 -5130 4810 -5110
-rect 3500 -5230 3830 -5130
-rect 4490 -5230 4810 -5130
+rect 5329 -1170 7890 -1169
+rect 8670 -1170 11251 -1169
+rect 5329 -4810 5330 -1170
+rect 3500 -4930 4070 -4810
+rect 3500 -4950 4130 -4930
+rect 4730 -4940 5330 -4810
+rect 3500 -5110 3950 -4950
+rect 4110 -5110 4130 -4950
+rect 3500 -5130 4130 -5110
+rect 4660 -4960 5330 -4940
+rect 4660 -5120 4680 -4960
+rect 4840 -5120 5330 -4960
+rect 3500 -5230 4070 -5130
+rect 4660 -5140 5330 -5120
+rect 4730 -5230 5330 -5140
 rect 3500 -7090 3501 -5230
 rect -2421 -7091 3501 -7090
-rect 4809 -7090 4810 -5230
-rect 10730 -7090 10731 -1170
-rect 4809 -7091 7370 -7090
-rect 8150 -7091 10731 -7090
-rect 140 -7559 920 -7091
-rect 4159 -7380 6720 -7379
-rect 7500 -7380 10081 -7379
-rect -2421 -7560 3501 -7559
-rect -2421 -13480 -2420 -7560
-rect 3500 -13480 3501 -7560
-rect 4159 -13300 4160 -7380
-rect 10080 -13300 10081 -7380
-rect 4159 -13301 10081 -13300
-rect -2421 -13481 3501 -13480
-rect 140 -13869 920 -13481
-rect 6720 -13769 7500 -13301
-rect 4159 -13770 10081 -13769
-rect -2421 -13870 3501 -13869
-rect -2421 -19790 -2420 -13870
-rect 3500 -16470 3501 -13870
-rect 4159 -16470 4160 -13770
-rect 3500 -17340 4160 -16470
-rect 3500 -19790 3501 -17340
-rect 4159 -19690 4160 -17340
-rect 10080 -19690 10081 -13770
-rect 4159 -19691 6720 -19690
-rect 7510 -19691 10081 -19690
-rect -2421 -19791 140 -19790
-rect 920 -19791 3501 -19790
+rect 5329 -7090 5330 -5230
+rect 11250 -7090 11251 -1170
+rect 5329 -7091 7890 -7090
+rect 8670 -7091 11251 -7090
+rect 140 -8189 920 -7091
+rect 4509 -8010 7070 -8009
+rect 7850 -8010 10431 -8009
+rect -2421 -8190 3501 -8189
+rect -2421 -14110 -2420 -8190
+rect 3500 -14110 3501 -8190
+rect 4509 -13930 4510 -8010
+rect 10430 -13930 10431 -8010
+rect 4509 -13931 10431 -13930
+rect -2421 -14111 3501 -14110
+rect 140 -14979 920 -14111
+rect 7070 -14879 7850 -13931
+rect 4509 -14880 10431 -14879
+rect -2421 -14980 3501 -14979
+rect -2421 -20900 -2420 -14980
+rect 3500 -17580 3501 -14980
+rect 4509 -17580 4510 -14880
+rect 3500 -18450 4510 -17580
+rect 3500 -20900 3501 -18450
+rect 4509 -20800 4510 -18450
+rect 10430 -20800 10431 -14880
+rect 4509 -20801 7070 -20800
+rect 7860 -20801 10431 -20800
+rect -2421 -20901 140 -20900
+rect 920 -20901 3501 -20900
 << labels >>
-rlabel locali 4310 -20570 4310 -20570 1 gnd
-rlabel locali 4310 -20570 4310 -20570 1 gnd!
-rlabel locali 4130 -2280 4130 -2280 1 v
+rlabel psubdiffcont 4660 -21680 4660 -21680 1 gnd!
+rlabel psubdiffcont 4660 -21680 4660 -21680 1 gnd
+rlabel locali 4370 -2280 4370 -2280 1 v
 << end >>

mag/nand.ext

diff --git a/mag/nand.ext b/mag/nand.ext
index 630e049..89b5e0b 100644
--- a/mag/nand.ext
+++ b/mag/nand.ext
@@ -14,22 +14,22 @@
 node "A" 1521 380.56 30 -230 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 2060 0 0 9600 480 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 1727 1248 -80 -20 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "VDD" "OUT" 2.96
-cap "VDD" "vdd!" 29.2
-cap "z1" "OUT" 210.754
-cap "gnd!" "OUT" 22
-cap "z1" "vdd!" 8.55556
-cap "z1" "a_280_n230#" 70.125
-cap "gnd!" "vdd!" 8.55556
-cap "z1" "A" 8.25
-cap "gnd!" "A" 57.75
+cap "gnd!" "z1" 159.5
+cap "OUT" "z1" 210.754
+cap "OUT" "gnd!" 22
+cap "vdd!" "z1" 8.55556
+cap "a_280_n230#" "z1" 70.125
+cap "vdd!" "gnd!" 8.55556
+cap "A" "z1" 8.25
 cap "vdd!" "OUT" 838.2
+cap "A" "gnd!" 57.75
 cap "a_280_n230#" "OUT" 150.608
 cap "a_280_n230#" "vdd!" 13.0842
 cap "A" "OUT" 9.74286
 cap "A" "vdd!" 13.0842
+cap "VDD" "OUT" 2.96
+cap "VDD" "vdd!" 29.2
 cap "A" "a_280_n230#" 81.6947
-cap "gnd!" "z1" 159.5
 device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "VSUBS" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "z1" 200 0
 device msubckt sky130_fd_pr__pfet_01v8 310 20 311 21 l=30 w=400 "VDD" "a_280_n230#" 60 0 "vdd!" 400 0 "OUT" 400 0

mag/nor.ext

diff --git a/mag/nor.ext b/mag/nor.ext
index 9d6cf53..3a99658 100644
--- a/mag/nor.ext
+++ b/mag/nor.ext
@@ -14,22 +14,22 @@
 node "A" 2231 379.695 -40 -100 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0
 node "VDD" 3542 2250 -110 -30 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Out" "gnd!" 453.75
+cap "Z1" "gnd!" 9.625
+cap "Z1" "Out" 779.396
+cap "vdd!" "gnd!" 9.625
+cap "B" "gnd!" 39.7045
+cap "vdd!" "Out" 99
+cap "A" "gnd!" 19.25
+cap "vdd!" "Z1" 749.833
+cap "B" "Out" 246.8
+cap "A" "Out" 8.8
+cap "B" "Z1" 57.75
+cap "VDD" "Out" 2.3125
+cap "A" "vdd!" 57.75
 cap "VDD" "Z1" 2.775
 cap "VDD" "vdd!" 16.2425
-cap "gnd!" "Z1" 9.625
-cap "Out" "Z1" 779.396
-cap "gnd!" "vdd!" 9.625
-cap "gnd!" "B" 39.7045
-cap "Out" "vdd!" 99
-cap "gnd!" "A" 19.25
-cap "Out" "B" 246.8
-cap "Out" "A" 8.8
-cap "vdd!" "Z1" 749.833
-cap "B" "Z1" 57.75
-cap "A" "vdd!" 57.75
 cap "A" "B" 72.9302
-cap "Out" "VDD" 2.3125
-cap "Out" "gnd!" 453.75
 device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "VSUBS" "B" 60 0 "gnd!" 200 0 "Out" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "Out" 200 0
 device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0

mag/pd.ext

diff --git a/mag/pd.ext b/mag/pd.ext
index 40d9624..3f14474 100644
--- a/mag/pd.ext
+++ b/mag/pd.ext
@@ -1,4 +1,4 @@
-timestamp 1640958486
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
@@ -19,103 +19,102 @@
 node "w_0_n1460#" 18910 2199.75 0 -1460 nw 0 0 0 0 662500 5900 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 45800 1300 0 0 0 0
 node "VDD" 27087 2548.65 0 1160 nw 0 0 0 0 793200 7540 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 37400 1040 0 0 0 0
 substrate "a_n420_n1430#" 0 0 -420 -1430 ppd 0 0 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0
-cap "m1_2010_600#" "UP" 4.5
 cap "R" "GND" 53.75
 cap "DOWN" "GND" 50.15
 cap "VDD" "GND" 113.9
-cap "VDD" "R" 11.2838
+cap "m1_2010_600#" "UP" 4.5
 cap "VDD" "DIV" 27.9
 cap "R" "UP" 72
-cap "VDD" "VDD" 0.48
 cap "VDD" "REF" 27.9
 cap "DOWN" "UP" 101.25
 cap "DOWN" "m1_2010_600#" 41.625
 cap "DOWN" "R" 185.417
-cap "w_0_n1460#" "VDD" 0.48
-cap "VDD" "m4_1440_1280#" 4.92
-cap "VDD" "UP" 7.2
+cap "m4_1440_1280#" "VDD" 4.92
+cap "UP" "VDD" 7.2
+cap "R" "VDD" 11.2838
+cap "VDD" "w_0_n1460#" 0.48
+cap "VDD" "VDD" 0.48
 cap "tspc_r_1/VDD" "tspc_r_1/Z3" 10.9091
-cap "tspc_r_1/VDD" "tspc_r_1/clk" 62.5
-cap "tspc_r_1/VDD" "tspc_r_1/R" 100
-cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375
-cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775
-cap "tspc_r_0/GND" "tspc_r_1/Z1" 14.4375
 cap "tspc_r_0/GND" "tspc_r_1/Z3" 7.21875
-cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355
-cap "tspc_r_1/VDD" "tspc_r_1/w_n290_n40#" 33.74
+cap "tspc_r_1/VDD" "tspc_r_1/R" 100
+cap "tspc_r_1/VDD" "tspc_r_1/clk" 62.5
+cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375
 cap "tspc_r_1/VDD" "tspc_r_1/Z2" 72
-cap "tspc_r_1/VDD" "tspc_r_0/GND" 99.8267
-cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615
-cap "tspc_r_1/VDD" "tspc_r_1/Q" -2.37588e-14
-cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 6.30607e-14
-cap "tspc_r_1/VDD" "tspc_r_1/Z3" 8.88178e-15
-cap "a_n420_n1430#" "tspc_r_1/Qbar" 7.21875
+cap "tspc_r_0/GND" "tspc_r_1/VDD" 99.8267
+cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775
+cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.74
+cap "tspc_r_0/GND" "tspc_r_1/Z1" 14.4375
+cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355
 cap "a_n420_n1430#" "tspc_r_1/Q" 7.21875
 cap "a_n420_n1430#" "tspc_r_1/Qbar1" 7.21875
-cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785
 cap "tspc_r_1/VDD" "a_n420_n1430#" 45.2812
+cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785
+cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615
+cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 5.68434e-14
+cap "tspc_r_1/VDD" "tspc_r_1/Z3" 8.88178e-15
+cap "a_n420_n1430#" "tspc_r_1/Qbar" 7.21875
+cap "tspc_r_1/Z4" "tspc_r_0/GND" 13.3333
+cap "tspc_r_0/R" "tspc_r_0/Z3" 13.31
+cap "tspc_r_0/Z4" "tspc_r_0/GND" 13.3333
+cap "tspc_r_0/R" "tspc_r_0/VDD" 66.6667
+cap "tspc_r_0/R" "tspc_r_0/GND" 64.2857
 cap "tspc_r_0/VDD" "tspc_r_0/Z2" 72
-cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595
-cap "tspc_r_0/GND" "tspc_r_0/Z4" 13.3333
-cap "tspc_r_0/GND" "tspc_r_0/R" 64.2857
 cap "tspc_r_0/VDD" "tspc_r_0/Z3" 10.9091
-cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31
 cap "tspc_r_0/VDD" "tspc_r_0/clk" 44.4444
-cap "tspc_r_0/VDD" "tspc_r_0/GND" 150.325
-cap "tspc_r_0/GND" "tspc_r_1/Z4" 13.3333
-cap "tspc_r_0/VDD" "tspc_r_0/R" 66.6667
-cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 68.0625
-cap "and_pd_0/Out1" "tspc_r_0/Qbar" 47.6929
-cap "and_pd_0/A" "tspc_r_0/Qbar" 17.9186
-cap "and_pd_0/B" "and_pd_0/Out1" -14.35
-cap "and_pd_0/Z1" "tspc_r_0/Qbar" 21.0517
-cap "and_pd_0/B" "and_pd_0/A" 183.938
+cap "tspc_r_0/GND" "tspc_r_0/VDD" 150.325
+cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595
 cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595
-cap "and_pd_0/Z1" "and_pd_0/A" 85
-cap "and_pd_0/GND" "tspc_r_0/Qbar" 44.4044
-cap "tspc_r_0/R" "tspc_r_0/Qbar" 31.025
-cap "and_pd_0/GND" "and_pd_0/a_n60_n30#" 1.77636e-15
 cap "and_pd_0/GND" "tspc_r_1/z5" 13.3333
-cap "and_pd_0/GND" "and_pd_0/A" 308.57
-cap "tspc_r_0/R" "and_pd_0/A" 86.5
-cap "tspc_r_0/R" "tspc_r_0/Qbar1" 287.105
-cap "tspc_r_0/R" "and_pd_0/B" 150.845
-cap "tspc_r_0/R" "tspc_r_0/Z3" 143.15
-cap "tspc_r_0/R" "tspc_r_0/clk" 103.99
 cap "and_pd_0/GND" "tspc_r_0/z5" 13.3333
+cap "tspc_r_0/Qbar" "and_pd_0/Z1" 21.0517
 cap "tspc_r_0/R" "and_pd_0/GND" 145.652
-cap "and_pd_0/Out" "and_pd_0/GND" 16.129
-cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231
-cap "and_pd_0/A" "and_pd_0/GND" 113.28
-cap "and_pd_0/A" "and_pd_0/Z1" -23.46
-cap "and_pd_0/Out1" "and_pd_0/Out" 137.14
-cap "and_pd_0/B" "and_pd_0/Out" 222.129
+cap "tspc_r_0/Qbar" "and_pd_0/GND" 44.4044
+cap "and_pd_0/A" "and_pd_0/Z1" 85
+cap "tspc_r_0/Qbar" "tspc_r_0/R" 31.025
+cap "and_pd_0/a_n60_n30#" "and_pd_0/GND" 1.77636e-15
+cap "and_pd_0/A" "and_pd_0/GND" 308.57
+cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 68.0625
+cap "and_pd_0/A" "tspc_r_0/R" 86.5
+cap "and_pd_0/Out1" "tspc_r_0/Qbar" 47.6929
+cap "and_pd_0/B" "tspc_r_0/R" 150.845
+cap "and_pd_0/A" "tspc_r_0/Qbar" 17.9186
+cap "tspc_r_0/Qbar1" "tspc_r_0/R" 287.105
+cap "tspc_r_0/Z3" "tspc_r_0/R" 143.15
+cap "tspc_r_0/clk" "tspc_r_0/R" 103.99
+cap "and_pd_0/B" "and_pd_0/Out1" -14.35
+cap "and_pd_0/B" "and_pd_0/A" 183.938
 cap "and_pd_0/A" "and_pd_0/Out" 90.78
+cap "and_pd_0/VDD" "and_pd_0/Out" 56.5714
+cap "and_pd_0/B" "and_pd_0/Out1" 70.6975
+cap "and_pd_0/A" "and_pd_0/Out1" 105.892
+cap "and_pd_0/VDD" "and_pd_0/Out1" 12.375
+cap "and_pd_0/A" "and_pd_0/B" 58.428
+cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15
 cap "a_n420_n1430#" "and_pd_0/Z1" 0.916667
 cap "a_n420_n1430#" "and_pd_0/GND" 9.20833
 cap "a_n420_n1430#" "and_pd_0/Out" 72.7883
-cap "and_pd_0/VDD" "and_pd_0/Out" 56.5714
-cap "and_pd_0/A" "and_pd_0/Out1" 105.892
-cap "and_pd_0/B" "and_pd_0/Out1" 70.6975
-cap "and_pd_0/VDD" "and_pd_0/Out1" 12.375
-cap "and_pd_0/A" "and_pd_0/B" 58.428
 cap "a_n420_n1430#" "and_pd_0/Out1" 6.41667
-cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15
+cap "and_pd_0/Out" "and_pd_0/GND" 16.129
+cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231
+cap "and_pd_0/A" "and_pd_0/Z1" -23.46
+cap "and_pd_0/Out1" "and_pd_0/Out" 137.14
+cap "and_pd_0/A" "and_pd_0/GND" 113.28
+cap "and_pd_0/B" "and_pd_0/Out" 222.129
+cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375
+cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775
+cap "a_n420_n1430#" "tspc_r_0/Z1" 14.4375
+cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74
 cap "a_n420_n1430#" "tspc_r_0/Z3" 7.21875
-cap "tspc_r_0/Z2" "tspc_r_0/w_n290_n40#" 12.775
-cap "tspc_r_0/Z2" "a_n420_n1430#" 9.69375
-cap "tspc_r_0/Z1" "a_n420_n1430#" 14.4375
-cap "tspc_r_0/VDD" "a_n420_n1430#" 56.7013
-cap "tspc_r_0/VDD" "tspc_r_0/w_n290_n40#" 33.74
-cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 6.1875
-cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Qbar" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Q" 7.21875
-cap "a_n420_n1430#" "tspc_r_0/Qbar1" 7.21875
-cap "and_pd_0/VDD" "and_pd_0/a_n60_n30#" 43.07
-cap "tspc_r_0/Q" "and_pd_0/A" 2.15625
-cap "a_n420_n1430#" "and_pd_0/a_n60_n30#" 54.6607
+cap "a_n420_n1430#" "tspc_r_0/VDD" 56.7013
+cap "tspc_r_0/Qbar" "and_pd_0/a_n60_n30#" 6.1875
 cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571
+cap "tspc_r_0/Qbar1" "a_n420_n1430#" 7.21875
+cap "and_pd_0/a_n60_n30#" "and_pd_0/VDD" 43.07
+cap "and_pd_0/a_n60_n30#" "a_n420_n1430#" 54.6607
+cap "and_pd_0/Out1" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Qbar" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Q" "a_n420_n1430#" 7.21875
+cap "tspc_r_0/Q" "and_pd_0/A" 2.15625
 cap "a_n420_n1430#" "and_pd_0/Out" 9.96875
 cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875
 cap "a_n420_n1430#" "and_pd_0/VDD" 18.7589

mag/prescaler.ext

diff --git a/mag/prescaler.ext b/mag/prescaler.ext
index d3051a5..c8296f4 100644
--- a/mag/prescaler.ext
+++ b/mag/prescaler.ext
@@ -1,4 +1,4 @@
-timestamp 1640957100
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
@@ -29,127 +29,127 @@
 node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "li_n310_330#" "li_3590_420#" 92.2845
-cap "mc1" "m4_2730_1520#" 23.175
-cap "w_1930_2072#" "mc1" 2.7456
 cap "mc1" "VDD" 41.675
-cap "w_1930_2072#" "li_1980_2130#" 10.7855
-cap "mc1" "m4_350_1060#" 84.575
-cap "w_390_530#" "m4_350_1060#" 2.9032
-cap "li_n310_330#" "mc1" 37.515
 cap "li_3590_420#" "clk" 168.462
+cap "mc1" "m4_350_1060#" 84.575
 cap "li_3590_420#" "m2_970_460#" 183.333
 cap "Out" "m1_2700_2190#" 27.465
 cap "li_3590_420#" "m1_2700_2190#" 23.5
 cap "li_2030_420#" "m2_970_460#" 17.38
 cap "li_450_280#" "clk" 28.72
-cap "li_3590_420#" "Out" 716.418
-cap "li_2030_420#" "Out" 197.97
-cap "w_1930_2072#" "m2_970_460#" 42.9324
-cap "VDD" "m2_970_460#" 42
-cap "GND" "Out" 27.9
+cap "w_390_530#" "m4_350_1060#" 2.9032
 cap "w_1930_2072#" "VDD" 1.964
+cap "li_3590_420#" "Out" 716.418
 cap "mc1" "m2_970_460#" 37.515
-cap "GND" "m4_2730_1520#" 23.6471
+cap "li_2030_420#" "Out" 197.97
 cap "li_n310_330#" "clk" 28.72
 cap "mc1" "m1_2700_2190#" 63.2343
 cap "li_1980_2130#" "m2_970_460#" 138.025
-cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225
-cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16
-cap "nand_0/a_280_n230#" "nand_0/z1" 153.26
+cap "w_1930_2072#" "m2_970_460#" 42.9324
+cap "li_n310_330#" "li_3590_420#" 92.2845
+cap "li_n310_330#" "mc1" 37.515
+cap "w_1930_2072#" "mc1" 2.7456
+cap "w_1930_2072#" "li_1980_2130#" 10.7855
+cap "GND" "m4_2730_1520#" 23.6471
+cap "m2_970_460#" "VDD" 42
+cap "Out" "GND" 27.9
+cap "mc1" "m4_2730_1520#" 23.175
 cap "nand_0/a_280_n230#" "tspc_0/GND" 124.422
+cap "nand_0/a_280_n230#" "nand_0/z1" 153.26
+cap "tspc_0/D" "tspc_0/Z4" 12.3811
 cap "nand_0/A" "nand_0/vdd!" 44.8462
 cap "nand_0/A" "nand_0/a_280_n230#" 13.02
-cap "tspc_0/D" "nand_0/z1" 2.11538
 cap "tspc_0/a_300_n150#" "nand_0/a_280_n230#" 94.1074
 cap "tspc_0/D" "nand_0/a_280_n230#" 165.278
+cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225
+cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16
+cap "tspc_0/D" "nand_0/z1" 2.11538
 cap "tspc_0/a_300_n150#" "nand_0/A" 17.42
-cap "tspc_0/D" "tspc_0/vdd!" 45.9643
 cap "tspc_0/D" "nand_0/A" 29.5549
-cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12
 cap "nand_0/a_280_n230#" "tspc_0/Z4" 106.442
-cap "tspc_0/D" "tspc_0/Z4" 12.3811
-cap "tspc_0/GND" "tspc_1/Z2" 16.9342
-cap "tspc_1/Z3" "tspc_0/Q" 3.50402
-cap "tspc_1/Z4" "tspc_0/Q" 102.17
-cap "tspc_0/GND" "tspc_0/Q" 51.0882
-cap "tspc_0/Z3" "li_3590_420#" 57.62
-cap "tspc_1/Z4" "tspc_0/a_740_n680#" 4.09091
-cap "tspc_0/Q" "tspc_1/Z2" 85.89
+cap "tspc_0/D" "tspc_0/vdd!" 45.9643
+cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12
+cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533
+cap "tspc_0/Q" "tspc_0/GND" 51.0882
+cap "tspc_1/Z4" "li_3590_420#" 55.1
 cap "tspc_0/Q" "tspc_1/Z1" 39.5832
 cap "tspc_0/Q" "tspc_1/vdd!" 59.1194
-cap "tspc_1/Z4" "li_3590_420#" 55.1
-cap "tspc_0/GND" "li_3590_420#" 198.939
-cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4
-cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533
-cap "tspc_0/vdd!" "tspc_1/vdd!" 38.2105
-cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861
-cap "tspc_0/Z4" "li_3590_420#" 107.677
-cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347
 cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16
-cap "tspc_1/Z2" "li_3590_420#" 43.32
-cap "tspc_0/Q" "li_3590_420#" 142.71
-cap "tspc_0/Z3" "tspc_0/a_300_n150#" 198.42
+cap "tspc_1/Z2" "tspc_0/GND" 16.9342
+cap "tspc_0/vdd!" "tspc_1/vdd!" 38.2105
+cap "tspc_0/a_300_n150#" "tspc_0/Z3" 198.42
+cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861
 cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378
+cap "tspc_0/GND" "li_3590_420#" 198.939
+cap "tspc_0/Q" "tspc_1/Z2" 85.89
+cap "tspc_0/Q" "li_3590_420#" 142.71
+cap "tspc_0/Q" "tspc_1/Z3" 3.50402
+cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4
+cap "tspc_0/Q" "tspc_1/Z4" 102.17
 cap "tspc_0/a_740_n680#" "li_3590_420#" 150.46
-cap "tspc_1/Q" "tspc_1/GND" 218.86
+cap "tspc_0/Z4" "li_3590_420#" 107.677
+cap "tspc_1/Z2" "li_3590_420#" 43.32
+cap "tspc_0/a_740_n680#" "tspc_1/Z4" 4.09091
+cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347
+cap "tspc_0/Z3" "li_3590_420#" 57.62
 cap "tspc_0/Q" "tspc_1/GND" 39.1
 cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785
 cap "tspc_1/Q" "tspc_1/Z4" 104.585
-cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
 cap "tspc_0/Q" "tspc_1/a_300_n150#" 179.587
 cap "tspc_0/Q" "tspc_1/Z4" 78.2567
-cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65
 cap "tspc_0/Q" "tspc_1/Q" 50.6
 cap "tspc_1/Z4" "tspc_0/a_740_n680#" 1.92857
+cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043
 cap "tspc_1/Z3" "tspc_1/Q" 156.507
 cap "tspc_1/Z2" "tspc_1/Q" 12.84
+cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65
 cap "tspc_0/Q" "tspc_1/Z3" 59.529
+cap "tspc_1/Q" "tspc_1/GND" 218.86
 cap "tspc_0/Q" "tspc_1/Z2" 9.99
+cap "tspc_0/Z2" "mc1" 46.8
 cap "tspc_2/Q" "tspc_0/vdd!" 32.5248
 cap "tspc_0/w_n140_n70#" "tspc_0/vdd!" -3.656
 cap "tspc_0/w_n140_n70#" "mc1" 9.165
 cap "tspc_0/vdd!" "mc1" 162.542
 cap "tspc_0/vdd!" "tspc_0/Z2" 10
-cap "tspc_0/Z2" "mc1" 46.8
+cap "tspc_2/a_300_n150#" "tspc_0/vdd!" 166.667
+cap "tspc_1/Z2" "mc1" 18
+cap "tspc_2/w_n140_n70#" "mc1" 24.5544
+cap "tspc_2/a_300_n150#" "tspc_2/D" -6.9
+cap "tspc_2/D" "nand_1/z1" 6
 cap "tspc_2/Z2" "mc1" 53.3571
 cap "tspc_0/vdd!" "mc1" 414.897
 cap "tspc_0/vdd!" "tspc_1/Z2" 4.35484
-cap "tspc_2/w_n140_n70#" "mc1" 24.5544
-cap "tspc_0/vdd!" "tspc_0/Q" 44.0676
+cap "tspc_2/w_n140_n70#" "tspc_0/vdd!" -11.884
+cap "tspc_0/Q" "tspc_1/Z1" 10.4211
+cap "tspc_0/Z2" "mc1" 17.4522
+cap "tspc_2/w_n140_n70#" "tspc_2/D" 8.1659
+cap "tspc_2/w_n140_n70#" "tspc_2/a_300_n150#" 2.0976
 cap "tspc_0/vdd!" "tspc_2/Z2" 10
-cap "tspc_2/D" "nand_1/z1" 6
+cap "tspc_0/vdd!" "tspc_0/Q" 44.0676
 cap "nand_1/a_280_n230#" "tspc_0/vdd!" 7.33333
 cap "tspc_2/D" "tspc_2/Z1" 99.6765
 cap "tspc_2/D" "tspc_0/vdd!" 272.242
-cap "tspc_2/w_n140_n70#" "tspc_0/vdd!" -11.884
 cap "tspc_2/D" "nand_1/a_280_n230#" 9.77778
-cap "tspc_2/w_n140_n70#" "tspc_2/D" 8.1659
-cap "tspc_2/a_300_n150#" "tspc_0/vdd!" 166.667
-cap "tspc_1/Z2" "mc1" 18
-cap "tspc_2/w_n140_n70#" "tspc_2/a_300_n150#" 2.0976
-cap "tspc_2/a_300_n150#" "tspc_2/D" -6.9
-cap "tspc_0/Q" "tspc_1/Z1" 10.4211
-cap "tspc_0/Z2" "mc1" 17.4522
 cap "nand_1/GND" "tspc_1/vdd!" 39.5155
-cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889
-cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132
-cap "nand_1/A" "tspc_1/vdd!" 227.695
-cap "nand_1/a_280_n230#" "tspc_1/vdd!" 13.125
 cap "nand_1/OUT" "nand_1/z1" 1.83333
-cap "tspc_2/w_n140_n70#" "tspc_1/vdd!" -6.44
-cap "nand_1/a_280_n230#" "tspc_1/a_740_n680#" 1.36364
-cap "nand_1/A" "tspc_1/Z2" 46.2522
 cap "nand_1/A" "nand_1/OUT" 22.3793
 cap "tspc_2/w_n140_n70#" "nand_1/A" 9.555
+cap "tspc_1/a_740_n680#" "nand_1/a_280_n230#" 1.36364
+cap "tspc_1/Z2" "nand_1/A" 46.2522
+cap "tspc_1/vdd!" "nand_1/A" 227.695
+cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889
+cap "tspc_1/vdd!" "nand_1/a_280_n230#" 13.125
+cap "tspc_1/vdd!" "tspc_2/w_n140_n70#" -6.44
+cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132
 cap "tspc_2/Q" "tspc_2/a_740_n680#" 18.4737
-cap "nand_1/z1" "tspc_2/D" 14
-cap "tspc_2/vdd!" "tspc_2/D" 47.4
-cap "tspc_2/Z1" "tspc_2/D" 20.5588
-cap "tspc_2/D" "tspc_2/Z4" 7.71692
-cap "tspc_2/a_300_n150#" "tspc_2/D" 0.18
+cap "tspc_2/D" "nand_1/z1" 14
+cap "tspc_2/D" "tspc_2/vdd!" 47.4
+cap "tspc_2/D" "tspc_2/Z1" 20.5588
 cap "tspc_2/Z3" "tspc_2/D" 5.25747
 cap "tspc_2/w_n140_n70#" "tspc_2/D" 3.0525
+cap "tspc_2/D" "tspc_2/Z4" 7.71692
+cap "tspc_2/a_300_n150#" "tspc_2/D" 0.18
 cap "nand_1/OUT" "nand_1/z1" 2.75
 merge "tspc_2/gnd!" "tspc_2/GND" -681.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -218700 -3450 0 0 0 0
 merge "tspc_2/GND" "nand_1/GND"

mag/ro_complete.ext

diff --git a/mag/ro_complete.ext b/mag/ro_complete.ext
index 3a27871..5cd8702 100644
--- a/mag/ro_complete.ext
+++ b/mag/ro_complete.ext
@@ -1,4 +1,4 @@
-timestamp 1640959700
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
@@ -20,40 +20,40 @@
 substrate "a_7790_n10640#" 0 0 7790 -10640 ppd 0 0 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1036800 17280 1349800 21100 1085200 18160 1085200 18160 3951000 27540 0 0 0 0
 cap "li_4080_1390#" "a5" 77.72
 cap "li_7140_1400#" "a5" 100.96
-cap "cbank_2/switch_0/vout" "cbank_2/a0" 46.5385
-cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385
+cap "cbank_2/a0" "cbank_2/switch_0/vout" 46.5385
 cap "cbank_2/a2" "cbank_2/switch_2/vout" 46.5385
+cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385
 cap "cbank_2/a3" "cbank_2/switch_3/vout" 46.5385
 cap "cbank_2/a5" "cbank_2/switch_5/vout" 12.6923
 cap "cbank_2/a4" "cbank_2/switch_4/vout" 46.5385
 cap "cbank_2/switch_5/vin" "li_7140_1400#" 24
-cap "cbank_2/switch_5/vout" "cbank_2/a5" 33.8462
+cap "cbank_2/a5" "cbank_2/switch_5/vout" 33.8462
 cap "cbank_1/gnd!" "cbank_2/v" 86.7059
-cap "cbank_1/switch_1/vin" "a0" 21.8167
-cap "cbank_1/gnd!" "a0" 181.38
 cap "a0" "cbank_2/v" 53.41
 cap "cbank_1/gnd!" "cbank_2/v" 275.882
+cap "cbank_1/switch_1/vin" "a0" 21.8167
+cap "cbank_1/gnd!" "a0" 181.38
+cap "a1" "cbank_2/v" 53.41
+cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882
 cap "cbank_1/switch_1/vout" "a2" 60.0024
 cap "cbank_1/switch_2/vin" "a1" 23.6566
 cap "cbank_1/switch_1/vout" "a1" 209.96
-cap "a1" "cbank_2/v" 53.41
-cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882
-cap "a2" "cbank_2/v" 53.41
-cap "cbank_1/gnd!" "cbank_2/v" 275.882
-cap "cbank_1/switch_4/vin" "a3" 11.4157
-cap "cbank_1/switch_3/vin" "a2" 23.515
-cap "cbank_1/gnd!" "a3" 192.323
-cap "cbank_1/gnd!" "a2" 124.302
 cap "a3" "cbank_2/v" 53.41
+cap "a2" "cbank_2/v" 53.41
+cap "cbank_1/switch_4/vin" "a3" 11.4157
+cap "cbank_1/gnd!" "cbank_2/v" 275.882
+cap "cbank_1/gnd!" "a3" 192.323
+cap "a2" "cbank_1/switch_3/vin" 23.515
+cap "cbank_1/gnd!" "a2" 124.302
 cap "a4" "li_7140_1400#" 53.41
-cap "a3" "cbank_1/switch_4/vin" 11.4157
 cap "cbank_1/switch_4/vout" "li_7140_1400#" 275.882
 cap "cbank_1/switch_5/vin" "a4" 20.5602
 cap "cbank_1/switch_4/vout" "a4" 190.632
+cap "cbank_1/switch_4/vin" "a3" 11.4157
 cap "li_7140_1400#" "cbank_2/a_6660_n30#" 126
+cap "cbank_1/switch_5/vout" "a_7790_n10640#" 162.097
 cap "cbank_1/switch_5/vout" "li_7140_1400#" 233.936
 cap "cbank_1/switch_5/vout" "a5" 124.931
-cap "cbank_1/switch_5/vout" "a_7790_n10640#" 162.097
 cap "cbank_1/gnd!" "a_7790_n10640#" 45.6818
 cap "cbank_1/a0" "cbank_1/switch_1/vin" 106.517
 cap "cbank_1/a0" "cbank_1/switch_0/vout" 248.36
@@ -79,61 +79,61 @@
 cap "cbank_0/gnd!" "cbank_1/v" 151.29
 cap "cbank_1/a4" "li_4080_1390#" 53.41
 cap "cbank_0/gnd!" "li_4080_1390#" 151.29
-cap "li_4080_1390#" "cbank_1/switch_5/vin" 133.875
 cap "cbank_0/gnd!" "li_4080_1390#" 41.6979
+cap "cbank_1/switch_5/vin" "li_4080_1390#" 133.875
 cap "cbank_0/gnd!" "cbank_1/v" 47.5484
 cap "cbank_0/switch_1/vin" "a0" 82.3167
+cap "cbank_0/gnd!" "cbank_1/v" 151.29
 cap "cbank_0/gnd!" "a0" 296.011
-cap "cbank_1/v" "cbank_0/gnd!" 151.29
 cap "cbank_0/switch_1/vout" "cbank_1/v" 151.29
 cap "cbank_0/switch_1/vout" "a2" 118.551
 cap "cbank_0/switch_2/vin" "a1" 89.259
 cap "cbank_0/switch_1/vout" "a1" 347.808
+cap "cbank_0/switch_4/vin" "a3" 43.0727
+cap "cbank_0/switch_3/vin" "a2" 88.7246
 cap "cbank_1/v" "cbank_0/gnd!" 151.29
 cap "a3" "cbank_0/gnd!" 316.073
 cap "a2" "cbank_0/gnd!" 182.851
-cap "cbank_0/switch_4/vin" "a3" 43.0727
-cap "cbank_0/switch_3/vin" "a2" 88.7246
-cap "a3" "cbank_0/switch_4/vin" 43.0727
-cap "cbank_0/switch_4/vout" "li_4080_1390#" 151.29
 cap "cbank_0/switch_5/vin" "a4" 77.5759
+cap "cbank_0/switch_4/vout" "li_4080_1390#" 151.29
 cap "cbank_0/switch_4/vout" "a4" 312.991
-cap "a_7790_n10640#" "cbank_0/switch_5/vout" 193.269
-cap "li_4080_1390#" "cbank_0/switch_5/vout" 438.698
-cap "li_7140_1400#" "cbank_0/switch_5/vout" 142.26
-cap "a5" "cbank_0/switch_5/vout" 187.16
+cap "cbank_0/switch_4/vin" "a3" 43.0727
+cap "cbank_0/switch_5/vout" "a_7790_n10640#" 193.269
+cap "cbank_0/switch_5/vout" "li_4080_1390#" 438.698
+cap "cbank_0/switch_5/vout" "li_7140_1400#" 142.26
+cap "cbank_0/switch_5/vout" "a5" 187.16
 cap "cbank_0/gnd!" "a_7790_n10640#" 45.6818
 cap "cbank_0/a0" "cbank_0/switch_1/vin" 46.0167
 cap "cbank_0/a0" "cbank_0/switch_0/vout" 133.728
 cap "cbank_0/a1" "cbank_0/switch_2/vin" 49.8976
 cap "cbank_0/a1" "cbank_0/switch_1/vout" 151.387
 cap "cbank_0/a2" "cbank_0/switch_2/vout" 91.0707
-cap "cbank_0/a2" "cbank_0/switch_3/vin" 49.5988
-cap "cbank_0/a2" "cbank_0/switch_2/vout" 44.5323
 cap "cbank_0/a3" "cbank_0/switch_4/vin" 24.0785
 cap "cbank_0/a3" "cbank_0/switch_3/vout" 140.663
+cap "cbank_0/a2" "cbank_0/switch_3/vin" 49.5988
+cap "cbank_0/a2" "cbank_0/switch_2/vout" 44.5323
+cap "cbank_0/switch_4/vin" "a3" 24.0785
 cap "cbank_0/a5" "cbank_0/switch_5/vout" 12.6923
 cap "cbank_0/a4" "cbank_0/switch_5/vin" 43.3665
 cap "cbank_0/a4" "cbank_0/switch_4/vout" 139.606
-cap "cbank_0/switch_4/vin" "a3" 24.0785
 cap "cbank_0/a5" "cbank_0/switch_5/vout" 81.1776
 cap "ro_var_extend_0/gnd" "cbank_0/v" 151.9
 cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97
-cap "li_4080_1390#" "ro_var_extend_0/gnd" 769.58
-cap "li_7140_1400#" "ro_var_extend_0/w_n120_n750#" 294.59
-cap "li_4080_1390#" "ro_var_extend_0/w_n120_n750#" 415.935
-cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 69.0462
+cap "ro_var_extend_0/gnd" "li_4080_1390#" 769.58
+cap "ro_var_extend_0/w_n120_n750#" "li_4080_1390#" 415.935
+cap "ro_var_extend_0/w_n120_n750#" "li_7140_1400#" 294.59
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 69.0462
+cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
+cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15
 cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703
-cap "ro_var_extend_0/out3" "ro_var_extend_0/out1" 116.667
-cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023
-cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
 cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100
+cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5
-cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55
 cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 214.76
-cap "ro_var_extend_0/vcont" "ro_var_extend_0/gnd" -11.167
-cap "ro_var_extend_0/out3" "ro_var_extend_0/gnd" 392.251
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/vcont" -11.167
+cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 392.251
 merge "cbank_0/a4" "cbank_1/a4" -1801.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -154480 -6032 0 0 0 0 0 0 0 0 0 0 0 0
 merge "cbank_1/a4" "cbank_2/a4"
 merge "cbank_2/a4" "a4"

mag/ro_var_extend.ext

diff --git a/mag/ro_var_extend.ext b/mag/ro_var_extend.ext
index de1eaa2..1d6e822 100644
--- a/mag/ro_var_extend.ext
+++ b/mag/ro_var_extend.ext
@@ -14,16 +14,16 @@
 node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0
 node "vdd" 21463 18367.8 -250 320 nw 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "gnd" 0 0 -710 -890 ppd 0 0 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0
+cap "vdd" "out2" 235.622
+cap "vdd" "out1" 230.66
+cap "vdd" "out3" 230.554
 cap "out1" "out2" 40.8506
 cap "w_n120_n750#" "vcont" 140.194
 cap "out3" "out2" 1263.05
 cap "w_n120_n750#" "out2" 789.263
 cap "out3" "out1" 1156.32
 cap "w_n120_n750#" "out1" 569.035
-cap "vdd" "out2" 235.622
 cap "w_n120_n750#" "out3" 215.464
-cap "vdd" "out1" 230.66
-cap "vdd" "out3" 230.554
 device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0
 device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0
 device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0

mag/switch.ext

diff --git a/mag/switch.ext b/mag/switch.ext
index fadf98e..4013755 100644
--- a/mag/switch.ext
+++ b/mag/switch.ext
@@ -9,7 +9,7 @@
 node "vin" 1082 0 -190 0 ndif 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0
 node "vcont" 1139 384.82 -40 1460 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "vin" "vout" 420
-cap "vcont" "vout" 16.5
+cap "vout" "vin" 420
+cap "vout" "vcont" 16.5
 cap "vcont" "vin" 8.25
 device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "VSUBS" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0

mag/tspc.ext

diff --git a/mag/tspc.ext b/mag/tspc.ext
index 8eb3555..b271c3b 100644
--- a/mag/tspc.ext
+++ b/mag/tspc.ext
@@ -19,54 +19,54 @@
 node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0
 node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "a_300_n150#" "a_630_n680#" 9.625
-cap "Z4" "gnd!" 441.644
-cap "Q" "gnd!" 289.808
-cap "Z3" "gnd!" 265.176
-cap "Z3" "Z4" 651.52
-cap "Z2" "gnd!" 156.712
-cap "a_740_n680#" "gnd!" 224.895
-cap "Z2" "Z4" 361.112
-cap "Z3" "Q" 52.8649
-cap "a_740_n680#" "Z4" 82.0167
-cap "Z1" "Z4" 3.38462
-cap "a_740_n680#" "Q" 178.823
-cap "a_300_n150#" "gnd!" 22.7597
-cap "Z2" "Z3" 161.5
-cap "w_n140_n70#" "Q" 6.845
-cap "a_740_n680#" "Z3" 334.495
-cap "Z1" "Z3" 62.0085
-cap "D" "gnd!" 27.9314
-cap "a_300_n150#" "Z4" 118.945
-cap "w_n140_n70#" "Z3" 2.3125
-cap "Z1" "Z2" 1068.12
+cap "a_740_n680#" "a_630_n680#" 190.867
 cap "D" "Z4" 97.7372
-cap "w_n140_n70#" "Z2" 14.44
+cap "Z1" "Z3" 62.0085
+cap "a_740_n680#" "gnd!" 224.895
 cap "vdd!" "Z4" 7.7
+cap "Z1" "Z2" 1068.12
 cap "a_300_n150#" "Z3" 446.312
-cap "w_n140_n70#" "a_740_n680#" 18.5775
-cap "w_n140_n70#" "Z1" 4.1625
+cap "a_740_n680#" "Z4" 82.0167
 cap "D" "Z3" 46.1286
 cap "vdd!" "Q" 607.82
 cap "a_300_n150#" "Z2" 110.226
-cap "a_300_n150#" "a_740_n680#" 12.4103
+cap "a_740_n680#" "Q" 178.823
 cap "vdd!" "Z3" 671.367
 cap "D" "Z2" 91.0218
-cap "a_300_n150#" "w_n140_n70#" 0.665
 cap "D" "Z1" 26.4
 cap "vdd!" "Z2" 359.159
-cap "vdd!" "a_740_n680#" 515.003
+cap "w_n140_n70#" "Q" 6.845
+cap "a_740_n680#" "Z3" 334.495
 cap "vdd!" "Z1" 583.229
-cap "a_630_n680#" "gnd!" 610.469
-cap "vdd!" "w_n140_n70#" 85.4425
-cap "a_630_n680#" "Z4" 121.707
+cap "w_n140_n70#" "Z3" 2.3125
 cap "D" "a_300_n150#" 132.679
 cap "vdd!" "a_300_n150#" 20.3736
-cap "a_630_n680#" "Q" 36.6667
-cap "a_630_n680#" "Z3" 54.2903
+cap "w_n140_n70#" "Z2" 14.44
+cap "a_740_n680#" "a_300_n150#" 12.4103
 cap "vdd!" "D" 19.4229
-cap "a_630_n680#" "Z2" 6.6
-cap "a_630_n680#" "a_740_n680#" 190.867
+cap "w_n140_n70#" "Z1" 4.1625
+cap "w_n140_n70#" "a_300_n150#" 0.665
+cap "a_740_n680#" "vdd!" 515.003
+cap "w_n140_n70#" "vdd!" 85.4425
+cap "w_n140_n70#" "a_740_n680#" 18.5775
+cap "gnd!" "a_630_n680#" 610.469
+cap "Z4" "a_630_n680#" 121.707
+cap "Q" "a_630_n680#" 36.6667
+cap "Z4" "gnd!" 441.644
+cap "Z3" "a_630_n680#" 54.2903
+cap "Q" "gnd!" 289.808
+cap "Z2" "a_630_n680#" 6.6
+cap "Z3" "gnd!" 265.176
+cap "Z3" "Z4" 651.52
+cap "Z2" "gnd!" 156.712
+cap "Z2" "Z4" 361.112
+cap "a_300_n150#" "a_630_n680#" 9.625
+cap "Z3" "Q" 52.8649
+cap "a_300_n150#" "gnd!" 22.7597
+cap "Z1" "Z4" 3.38462
+cap "D" "gnd!" 27.9314
+cap "a_300_n150#" "Z4" 118.945
+cap "Z2" "Z3" 161.5
 device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "VSUBS" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0
 device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "VSUBS" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0
 device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "VSUBS" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0

mag/tspc_r.ext

diff --git a/mag/tspc_r.ext b/mag/tspc_r.ext
index 480997a..5474662 100644
--- a/mag/tspc_r.ext
+++ b/mag/tspc_r.ext
@@ -21,21 +21,32 @@
 node "D" 1470 418.74 -250 -140 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0
 node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "Z3" "Z4" 201.943
-cap "clk" "z5" 38.3774
-cap "clk" "Z4" 18.15
+cap "w_n290_n40#" "Qbar1" 1.82
+cap "w_n290_n40#" "Z3" 11.56
+cap "D" "clk" 31.5485
+cap "w_n290_n40#" "clk" 10.355
 cap "Z4" "z5" 42.0885
+cap "GND" "z5" 558.112
+cap "GND" "Z4" 527.304
 cap "R" "GND" 35.3744
 cap "Qbar" "GND" 138.6
+cap "Z2" "Z4" 137.657
+cap "VDD" "z5" 6.6
 cap "Z2" "GND" 142.361
+cap "Q" "z5" 33
 cap "Z2" "R" 208.97
+cap "Qbar1" "z5" 203.056
 cap "VDD" "GND" 17.6
+cap "Z3" "z5" 110
 cap "Q" "GND" 263.95
+cap "Z3" "Z4" 201.943
 cap "Qbar1" "GND" 157.761
+cap "clk" "z5" 38.3774
 cap "VDD" "Qbar" 237.6
 cap "Z1" "Z2" 709.991
 cap "Qbar1" "R" 11.3571
 cap "Z3" "GND" 324.951
+cap "clk" "Z4" 18.15
 cap "Q" "Qbar" 213.204
 cap "VDD" "Z2" 95.0921
 cap "Qbar1" "Qbar" 7.54286
@@ -63,19 +74,8 @@
 cap "Z3" "Qbar1" 379.384
 cap "w_n290_n40#" "VDD" 7.4
 cap "clk" "Qbar1" 121.715
-cap "GND" "z5" 558.112
 cap "w_n290_n40#" "Q" 1.85
 cap "clk" "Z3" 652.716
-cap "GND" "Z4" 527.304
-cap "w_n290_n40#" "Qbar1" 1.82
-cap "w_n290_n40#" "Z3" 11.56
-cap "D" "clk" 31.5485
-cap "w_n290_n40#" "clk" 10.355
-cap "Z2" "Z4" 137.657
-cap "VDD" "z5" 6.6
-cap "Q" "z5" 33
-cap "Qbar1" "z5" 203.056
-cap "Z3" "z5" 110
 device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "VSUBS" "Q" 60 0 "GND" 180 0 "Qbar" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "VSUBS" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0
 device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "VSUBS" "Z3" 60 0 "GND" 180 0 "z5" 180 0

mag/user_analog_project_wrapper.ext

diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
index 84aa6ca..419b47e 100644
--- a/mag/user_analog_project_wrapper.ext
+++ b/mag/user_analog_project_wrapper.ext
@@ -1,14 +1,14 @@
-timestamp 1640978128
+timestamp 1640983325
 version 8.3
 tech sky130A
 style ngspice()
 scale 1000 1 500000
 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use cp cp_0 1 0 196464 0 1 608714
-use cp cp_1 1 0 531400 0 1 683270
-use divider divider_0 1 0 163690 0 1 648664
-use pd pd_0 1 0 87306 0 1 647408
 use ro_complete ro_complete_0 1 0 31596 0 1 681444
+use pd pd_0 1 0 87306 0 1 647408
+use divider divider_0 1 0 163690 0 1 648664
+use cp cp_1 1 0 531400 0 1 683270
+use cp cp_0 1 0 196464 0 1 608714
 use filter filter_0 1 0 291454 0 1 660398
 port "io_analog[4]" 41 329294 702300 334294 704800 m5
 port "io_analog[4]" 47 318994 702300 323994 704800 m5
@@ -1393,18 +1393,24 @@
 node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0
 node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "io_analog[6]" "io_analog[6]" 21250
+cap "w_534690_682780#" "w_534750_683750#" 224.4
+cap "io_analog[2]" "vdda1" 219.25
 cap "io_clamp_high[0]" "io_analog[4]" 525
+cap "io_analog[2]" "vssa1" 9275.17
 cap "io_clamp_low[0]" "io_clamp_high[0]" 525
 cap "io_analog[4]" "io_clamp_low[0]" 525
 cap "io_clamp_high[1]" "io_analog[5]" 525
+cap "io_analog[1]" "io_analog[0]" 12301.4
 cap "io_clamp_low[1]" "io_clamp_high[1]" 525
 cap "io_analog[5]" "io_clamp_low[1]" 525
+cap "io_analog[1]" "vdda1" 23516.2
+cap "io_analog[3]" "vssa1" 6389.64
 cap "io_clamp_high[2]" "io_analog[6]" 525
 cap "io_analog[4]" "io_analog[4]" 26250
 cap "io_clamp_low[2]" "io_clamp_high[2]" 525
 cap "io_analog[6]" "io_clamp_low[2]" 525
 cap "io_analog[4]" "io_analog[4]" 26250
-cap "w_534750_683750#" "w_534690_682780#" 224.4
 cap "io_analog[5]" "io_analog[5]" 26250
 cap "io_analog[5]" "io_analog[5]" 26250
 cap "io_analog[4]" "io_analog[4]" 21250
@@ -1413,31 +1419,25 @@
 cap "io_analog[5]" "io_analog[5]" 21250
 cap "io_analog[6]" "io_analog[6]" 26250
 cap "io_analog[5]" "io_analog[5]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
-cap "io_analog[6]" "io_analog[6]" 21250
 cap "io_analog[0]" "vdda1" 18313.2
-cap "io_analog[1]" "vdda1" 23516.2
-cap "io_analog[1]" "io_analog[0]" 12301.4
-cap "io_analog[2]" "vdda1" 219.25
-cap "io_analog[3]" "vssa1" 6389.64
-cap "io_analog[2]" "vssa1" 9275.17
+cap "io_analog[6]" "io_analog[6]" 21250
 cap "cp_1/down" "cp_1/gnd!" 439.89
 cap "cp_1/gnd!" "io_analog[1]" -20.89
 cap "cp_1/vbias" "cp_1/gnd!" 6.79412
 cap "cp_1/vbias" "cp_1/gnd!" 8.73529
 cap "cp_1/vbias" "cp_1/gnd!" 6.79412
-cap "cp_1/vbias" "cp_1/gnd!" 8.73529
 cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68
+cap "cp_1/vbias" "cp_1/gnd!" 8.73529
 cap "cp_1/a_1710_n2840#" "cp_1/a_1710_0#" 37.5
 cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 99.11
 cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 243.801
-cap "w_534690_682780#" "cp_1/a_3060_0#" 1083.86
-cap "w_534690_682780#" "w_534750_683750#" -39.04
-cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4
+cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86
+cap "w_534750_683750#" "w_534690_682780#" -39.04
+cap "w_534690_682780#" "cp_1/a_3060_0#" 904.4
 cap "w_534690_682780#" "w_534750_683750#" -28
 cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49
 cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25
-cap "w_534690_682780#" "w_534750_683750#" -15.96
+cap "w_534750_683750#" "w_534690_682780#" -15.96
 cap "cp_1/vdd!" "cp_1/vdd!" 27.826
 cap "cp_1/vdd!" "cp_1/upbar" 248.023
 merge "cp_1/a_1710_n2840#" "vdda1" -20146.9 0 0 0 0 -5982920 -15262 0 0 173200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 168900 0 168900 0 168900 0 1321396 -4792 832050 -9472 0 0 0 0
@@ -1448,8 +1448,8 @@
 merge "vssa1" "ro_complete_0/a_7790_n10640#"
 merge "ro_complete_0/a_7790_n10640#" "divider_0/a_n940_n20#"
 merge "divider_0/a_n940_n20#" "pd_0/a_n420_n1430#"
-merge "pd_0/a_n420_n1430#" "filter_0/v"
-merge "filter_0/v" "cp_0/gnd!"
+merge "pd_0/a_n420_n1430#" "filter_0/gnd"
+merge "filter_0/gnd" "cp_0/gnd!"
 merge "cp_0/gnd!" "VSUBS"
 merge "cp_1/down" "io_analog[1]" -8142.87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -163500 -2410 -16700 -870 -226500 -1840 -12500000 -15000 0 0 0 0 0 0
 merge "cp_1/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0

mag/user_analog_project_wrapper.mag

diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 63ba54c..6ce781e 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1640978128
+timestamp 1640983325
 << nwell >>
 rect 267375 341875 267540 343575
 rect 267345 341390 267565 341585
@@ -862,30 +862,30 @@
 rect -50 0 0 352000
 rect 292000 0 292050 352000
 rect -50 -50 292050 0
-use filter  filter_0
-timestamp 1640921877
-transform 1 0 145727 0 1 330199
-box -1800 -10450 6065 390
+use ro_complete  ro_complete_0
+timestamp 1640983325
+transform 1 0 15798 0 1 340722
+box -57 -5330 4455 1440
+use pd  pd_0
+timestamp 1640983325
+transform 1 0 43653 0 1 323704
+box -215 -855 1685 810
+use divider  divider_0
+timestamp 1640983325
+transform 1 0 81845 0 1 324332
+box -490 -235 4690 2150
 use cp  cp_1
-timestamp 1640960365
+timestamp 1640911461
 transform 1 0 265700 0 1 341635
 box -415 -1715 4690 2035
 use cp  cp_0
-timestamp 1640960365
+timestamp 1640911461
 transform 1 0 98232 0 1 304357
 box -415 -1715 4690 2035
-use divider  divider_0
-timestamp 1640960365
-transform 1 0 81845 0 1 324332
-box -490 -235 4690 2150
-use pd  pd_0
-timestamp 1640960365
-transform 1 0 43653 0 1 323704
-box -215 -855 1685 810
-use ro_complete  ro_complete_0
-timestamp 1640960365
-transform 1 0 15798 0 1 340722
-box -57 -5330 4455 1440
+use filter  filter_0
+timestamp 1640983258
+transform 1 0 145727 0 1 330199
+box -1800 -11005 6240 390
 << labels >>
 flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
 port 0 nsew signal bidirectional

netgen/user_analog_project_wrapper.spice

diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index f1c6493..1f821fc 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1215 +106,1218 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-C0 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
-C1 gnd divider_0/and_0/B 0.45fF
-C2 divider_0/nor_1/Z1 gnd 0.01fF
-C3 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
-C4 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
-C5 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C6 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C7 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C8 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF
-C9 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
-C10 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C11 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C12 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF
-C13 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
-C14 gnd divider_0/tspc_2/Z4 0.44fF
-C15 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF
-C16 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
-C17 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
-C18 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C19 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C20 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF
-C21 io_clamp_high[1] io_analog[5] 0.53fF
-C22 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C23 cp_1/a_10_n50# cp_1/a_1710_0# 0.04fF
-C24 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
-C25 divider_0/tspc_0/a_630_n680# gnd 0.62fF
-C26 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C27 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
-C28 ro_complete_0/a0 ro_complete_0/cbank_0/switch_4/vin 0.13fF
-C29 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C30 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF
-C31 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF
-C32 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
-C33 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
-C34 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C35 divider_0/tspc_0/Z4 gnd 0.44fF
-C36 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z1 1.07fF
-C37 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C38 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
-C39 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C40 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF
-C41 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
-C42 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C43 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C44 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C45 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C46 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C47 divider_0/and_0/OUT gnd 0.28fF
-C48 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF
-C49 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
-C50 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
-C51 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C52 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C53 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
-C54 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
-C55 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
-C56 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
-C57 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C58 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
-C59 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
-C60 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
-C61 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF
-C62 io_clamp_low[0] io_analog[4] 0.53fF
-C63 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C64 pd_0/DOWN pd_0/R 0.36fF
-C65 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
-C66 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
-C67 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
-C68 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
-C69 divider_0/nor_1/B divider_0/and_0/A 0.26fF
-C70 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF
-C71 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
-C72 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
-C73 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
-C74 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_0/vin 1.30fF
-C75 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
-C76 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
-C77 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF
-C78 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF
-C79 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C80 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
-C81 cp_1/a_1710_0# cp_1/out 0.84fF
-C82 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C83 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF
-C84 divider_0/prescaler_0/tspc_0/D gnd 0.05fF
-C85 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
-C86 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C87 gnd divider_0/and_0/out1 0.23fF
-C88 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
-C89 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
-C90 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
-C91 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C92 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
-C93 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C94 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
-C95 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C96 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF
-C97 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
-C98 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF
-C99 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
-C100 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF
-C101 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
-C102 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C103 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
-C104 gnd divider_0/tspc_2/a_630_n680# 0.61fF
-C105 divider_0/nor_1/A divider_0/and_0/A 0.01fF
-C106 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
-C107 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
-C108 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
-C109 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C110 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF
-C111 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
-C112 divider_0/nor_0/B divider_0/and_0/B 0.29fF
-C113 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF
-C114 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C115 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C116 cp_1/a_1710_0# cp_1/down 0.32fF
-C117 divider_0/mc2 divider_0/nor_1/B 0.06fF
-C118 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C119 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF
-C120 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF
-C121 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C122 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C123 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C124 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C125 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.09fF
-C126 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
-C127 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
-C128 gnd divider_0/clk 0.07fF
-C129 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF
-C130 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
-C131 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C132 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
-C133 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
-C134 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF
-C135 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
-C136 pd_0/R pd_0/UP 0.45fF
-C137 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF
-C138 divider_0/and_0/OUT divider_0/clk 0.04fF
-C139 gnd divider_0/nor_0/B 1.08fF
-C140 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
-C141 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
-C142 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
-C143 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
-C144 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF
-C145 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
-C146 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
-C147 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF
-C148 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C149 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF
-C150 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
-C151 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF
-C152 divider_0/mc2 divider_0/nor_1/A 0.04fF
-C153 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C154 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
-C155 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
-C156 gnd divider_0/tspc_0/Z3 0.27fF
-C157 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF
-C158 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C159 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
-C160 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF
-C161 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C162 divider_0/and_0/A divider_0/and_0/B 0.18fF
-C163 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C164 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
-C165 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF
-C166 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF
-C167 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
-C168 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C169 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
-C170 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF
-C171 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF
-C172 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C173 gnd divider_0/tspc_2/Z2 0.16fF
-C174 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF
-C175 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
-C176 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C177 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C178 io_clamp_high[2] io_analog[6] 0.53fF
-C179 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
-C180 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C181 divider_0/tspc_1/Z3 gnd 0.27fF
-C182 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF
-C183 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF
-C184 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C185 gnd divider_0/and_0/A 0.53fF
-C186 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C187 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
-C188 cp_1/a_10_n50# cp_1/vbias 0.19fF
-C189 cp_1/a_1710_n2840# cp_1/out 0.61fF
-C190 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C191 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF
-C192 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
-C193 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
-C194 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_5/vin 1.30fF
-C195 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C196 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
-C197 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF
-C198 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C199 gnd divider_0/Out 0.29fF
-C200 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
-C201 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
-C202 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
-C203 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
-C204 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C205 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF
-C206 ro_complete_0/a4 ro_complete_0/cbank_0/switch_0/vin 0.12fF
-C207 io_clamp_low[1] io_analog[5] 0.53fF
-C208 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
-C209 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
-C210 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF
-C211 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF
-C212 divider_0/mc2 divider_0/and_0/B 0.20fF
-C213 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF
-C214 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF
-C215 divider_0/prescaler_0/tspc_2/D gnd 0.05fF
-C216 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF
-C217 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
-C218 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C219 pd_0/R pd_0/and_pd_0/Z1 0.02fF
-C220 divider_0/tspc_0/Q gnd 0.33fF
-C221 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C222 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C223 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
-C224 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C225 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
-C226 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C227 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C228 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
-C229 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C230 ro_complete_0/a0 ro_complete_0/cbank_0/switch_5/vin 0.09fF
-C231 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
-C232 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
-C233 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C234 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
-C235 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C236 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_0/vin 0.19fF
-C237 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
-C238 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
-C239 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
-C240 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C241 io_analog[2] io_analog[1] 0.02fF
-C242 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
-C243 divider_0/mc2 gnd 1.36fF
-C244 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
-C245 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C246 cp_1/a_1710_n2840# cp_1/a_1710_0# 0.83fF
-C247 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
-C248 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
-C249 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
-C250 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
-C251 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF
-C252 pd_0/DOWN pd_0/UP 0.46fF
-C253 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C254 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C255 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C256 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C257 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C258 cp_1/upbar cp_1/down 0.02fF
-C259 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
-C260 gnd divider_0/prescaler_0/nand_1/z1 0.16fF
-C261 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
-C262 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
-C263 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C264 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
-C265 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
-C266 divider_0/mc2 divider_0/and_0/OUT 0.05fF
-C267 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
-C268 gnd divider_0/and_0/Z1 0.41fF
-C269 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z1 0.06fF
-C270 io_analog[0] io_analog[1] 12.30fF
-C271 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
-C272 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/mc2 0.33fF
-C273 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C274 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C275 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/switch_3/vin 0.20fF
-C276 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
-C277 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
-C278 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C279 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
-C280 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
-C281 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
-C282 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
-C283 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
-C284 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
-C285 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF
-C286 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF
-C287 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
-C288 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF
-C289 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a2 0.14fF
-C290 io_clamp_high[0] io_analog[4] 0.53fF
-C291 divider_0/nor_1/B divider_0/and_0/B 0.31fF
-C292 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C293 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF
-C294 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
-C295 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C296 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C297 pd_0/R pd_0/REF 0.61fF
-C298 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C299 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
-C300 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
-C301 divider_0/tspc_1/a_630_n680# gnd 0.62fF
-C302 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
-C303 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C304 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
-C305 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
-C306 divider_0/mc2 divider_0/and_0/out1 0.06fF
-C307 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
-C308 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF
-C309 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF
-C310 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF
-C311 cp_0/a_1710_0# io_analog[0] 0.84fF
-C312 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF
-C313 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C314 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
-C315 divider_0/nor_0/B divider_0/Out 0.22fF
-C316 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF
-C317 gnd divider_0/prescaler_0/Out 0.46fF
-C318 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
-C319 cp_0/a_10_n50# io_analog[3] 0.22fF
-C320 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
-C321 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF
-C322 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C323 divider_0/nor_1/B gnd 1.10fF
-C324 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
-C325 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
-C326 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF
-C327 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
-C328 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF
-C329 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
-C330 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF
-C331 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF
-C332 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
-C333 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
-C334 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C335 divider_0/nor_1/A divider_0/and_0/B 0.08fF
-C336 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
-C337 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
-C338 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
-C339 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
-C340 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
-C341 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
-C342 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF
-C343 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_2/vin 1.30fF
-C344 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_3/vin 0.20fF
-C345 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
-C346 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
-C347 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF
-C348 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
-C349 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF
-C350 cp_0/a_1710_0# io_analog[1] 0.32fF
-C351 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
-C352 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C353 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
-C354 gnd divider_0/tspc_0/Z2 0.16fF
-C355 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF
-C356 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF
-C357 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
-C358 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
-C359 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C360 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C361 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF
-C362 divider_0/mc2 divider_0/nor_0/B 0.15fF
-C363 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF
-C364 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
-C365 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
-C366 divider_0/nor_1/A gnd 1.02fF
-C367 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C368 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C369 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C370 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF
-C371 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
-C372 io_clamp_low[2] io_analog[6] 0.53fF
-C373 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
-C374 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
-C375 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C376 divider_0/tspc_1/Z2 gnd 0.16fF
-C377 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
-C378 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C379 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
-C380 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF
-C381 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
-C382 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF
-C383 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF
-C384 pd_0/R pd_0/and_pd_0/Out1 0.33fF
-C385 divider_0/nor_0/Z1 gnd 0.01fF
-C386 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
-C387 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
-C388 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C389 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C390 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF
-C391 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
-C392 cp_1/a_1710_n2840# cp_1/upbar 0.29fF
-C393 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
-C394 divider_0/tspc_1/Z4 gnd 0.44fF
-C395 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF
-C396 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF
-C397 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C398 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
-C399 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C400 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C401 gnd divider_0/tspc_2/Z3 0.27fF
-C402 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
-C403 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
-C404 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF
-C405 divider_0/prescaler_0/Out divider_0/clk 0.51fF
-C406 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
-C407 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C408 pd_0/DIV pd_0/R 0.51fF
-C409 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/a5 0.09fF
-C410 ro_complete_0/cbank_0/v ro_complete_0/cbank_0/switch_4/vin 1.30fF
-C411 divider_0/mc2 divider_0/and_0/A 0.16fF
-C412 divider_0/tspc_1/Q gnd 0.33fF
-C413 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
-C414 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF
-C415 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF
-C416 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C0 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
+C1 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
+C2 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF
+C3 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
+C4 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF
+C5 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
+C6 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C7 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C8 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C9 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
+C10 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF
+C11 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C12 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
+C13 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
+C14 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF
+C15 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C16 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF
+C17 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF
+C18 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
+C19 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF
+C20 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF
+C21 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
+C22 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
+C23 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C24 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF
+C25 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C26 cp_0/a_1710_n2840# cp_0/out 0.61fF
+C27 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
+C28 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
+C29 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
+C30 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
+C31 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C32 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
+C33 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
+C34 gnd divider_0/tspc_0/Q 0.33fF
+C35 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C36 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
+C37 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C38 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C39 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF
+C40 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
+C41 divider_0/tspc_0/Z2 gnd 0.16fF
+C42 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
+C43 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
+C44 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C45 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
+C46 divider_0/nor_1/B divider_0/mc2 0.06fF
+C47 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF
+C48 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C49 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
+C50 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
+C51 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
+C52 io_clamp_low[2] io_analog[6] 0.53fF
+C53 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
+C54 divider_0/tspc_1/Z2 gnd 0.16fF
+C55 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
+C56 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF
+C57 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
+C58 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF
+C59 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
+C60 pd_0/R pd_0/and_pd_0/Out1 0.33fF
+C61 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
+C62 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C63 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
+C64 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF
+C65 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
+C66 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C67 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C68 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF
+C69 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
+C70 divider_0/tspc_1/Z4 gnd 0.44fF
+C71 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF
+C72 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C73 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C74 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
+C75 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C76 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C77 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
+C78 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C79 pd_0/and_pd_0/Z1 pd_0/UP 0.06fF
+C80 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
+C81 gnd divider_0/tspc_2/Z3 0.27fF
+C82 divider_0/tspc_1/a_630_n680# gnd 0.62fF
+C83 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF
+C84 divider_0/nor_0/Z1 gnd 0.01fF
+C85 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF
+C86 divider_0/prescaler_0/Out divider_0/clk 0.51fF
+C87 filter_0/a_4216_n2998# filter_0/v 0.31fF
+C88 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF
+C89 divider_0/tspc_1/Q gnd 0.33fF
+C90 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/mc2 0.33fF
+C91 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C92 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
+C93 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
+C94 divider_0/nor_1/A divider_0/and_0/B 0.08fF
+C95 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF
+C96 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF
+C97 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C98 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C99 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C100 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
+C101 gnd divider_0/and_0/B 0.45fF
+C102 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
+C103 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C104 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF
+C105 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C106 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C107 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
+C108 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C109 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C110 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
+C111 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C112 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
+C113 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
+C114 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
+C115 gnd divider_0/tspc_2/Z4 0.44fF
+C116 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF
+C117 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C118 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
+C119 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
+C120 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C121 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF
+C122 filter_0/a_4216_n5230# filter_0/v 0.19fF
+C123 io_clamp_high[1] io_analog[5] 0.53fF
+C124 divider_0/tspc_1/Z1 divider_0/tspc_0/Q 0.01fF
+C125 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C126 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
+C127 divider_0/nor_1/A gnd 1.02fF
+C128 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C129 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF
+C130 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C131 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C132 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
+C133 io_analog[0] io_analog[1] 12.30fF
+C134 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
+C135 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
+C136 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C137 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF
+C138 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
+C139 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
+C140 divider_0/and_0/OUT gnd 0.28fF
+C141 divider_0/mc2 divider_0/and_0/B 0.20fF
+C142 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C143 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C144 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
+C145 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
+C146 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
+C147 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
+C148 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
+C149 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C150 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C151 pd_0/DIV pd_0/R 0.51fF
+C152 pd_0/and_pd_0/Z1 pd_0/tspc_r_1/Qbar 0.02fF
+C153 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
+C154 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
+C155 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C156 pd_0/DOWN pd_0/R 0.36fF
+C157 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
+C158 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
+C159 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
+C160 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
+C161 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
+C162 io_clamp_low[0] io_analog[4] 0.53fF
+C163 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF
+C164 divider_0/tspc_0/a_630_n680# gnd 0.62fF
+C165 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF
+C166 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
+C167 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
+C168 divider_0/nor_1/B divider_0/and_0/A 0.26fF
+C169 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C170 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C171 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C172 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C173 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF
+C174 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C175 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
+C176 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C177 divider_0/mc2 divider_0/nor_1/A 0.04fF
+C178 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
+C179 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C180 divider_0/mc2 gnd 1.36fF
+C181 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C182 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
+C183 divider_0/tspc_1/Z3 divider_0/tspc_0/Q 0.45fF
+C184 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF
+C185 divider_0/prescaler_0/tspc_0/D gnd 0.05fF
+C186 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C187 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C188 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
+C189 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF
+C190 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C191 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
+C192 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
+C193 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C194 cp_0/a_1710_n2840# cp_0/upbar 0.29fF
+C195 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
+C196 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
+C197 gnd divider_0/and_0/out1 0.23fF
+C198 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
+C199 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
+C200 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
+C201 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
+C202 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
+C203 divider_0/mc2 divider_0/and_0/OUT 0.05fF
+C204 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
+C205 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C206 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF
+C207 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
+C208 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF
+C209 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
+C210 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF
+C211 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C212 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C213 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
+C214 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
+C215 gnd divider_0/tspc_2/a_630_n680# 0.61fF
+C216 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF
+C217 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C218 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF
+C219 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C220 pd_0/R pd_0/UP 0.45fF
+C221 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
+C222 divider_0/nor_0/B divider_0/and_0/B 0.29fF
+C223 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF
+C224 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
+C225 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF
+C226 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF
+C227 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C228 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
+C229 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
+C230 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C231 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C232 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C233 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
+C234 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
+C235 gnd divider_0/clk 0.07fF
+C236 io_analog[0] cp_1/a_1710_0# 0.84fF
+C237 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF
+C238 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
+C239 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C240 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF
+C241 divider_0/mc2 divider_0/and_0/out1 0.06fF
+C242 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
+C243 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
+C244 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF
+C245 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
+C246 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
+C247 pd_0/and_pd_0/Out1 pd_0/UP 0.33fF
+C248 divider_0/and_0/OUT divider_0/clk 0.04fF
+C249 gnd divider_0/nor_0/B 1.08fF
+C250 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C251 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C252 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
+C253 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
+C254 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF
+C255 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C256 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF
+C257 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF
+C258 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
+C259 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
+C260 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
+C261 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C262 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
+C263 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
+C264 gnd divider_0/tspc_0/Z4 0.44fF
+C265 io_analog[1] cp_1/a_1710_0# 0.32fF
+C266 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF
+C267 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C268 divider_0/and_0/A divider_0/and_0/B 0.18fF
+C269 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C270 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF
+C271 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF
+C272 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C273 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C274 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C275 gnd divider_0/tspc_2/Z2 0.16fF
+C276 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF
+C277 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
+C278 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C279 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF
+C280 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
+C281 io_clamp_high[2] io_analog[6] 0.53fF
+C282 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
+C283 divider_0/tspc_1/Z3 gnd 0.27fF
+C284 divider_0/mc2 divider_0/nor_0/B 0.15fF
+C285 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C286 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
+C287 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF
+C288 divider_0/nor_1/A divider_0/and_0/A 0.01fF
+C289 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C290 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C291 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF
+C292 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
+C293 gnd divider_0/and_0/A 0.53fF
+C294 divider_0/tspc_0/Z3 gnd 0.27fF
+C295 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C296 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C297 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF
+C298 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
+C299 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C300 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
+C301 cp_0/vbias cp_0/a_10_n50# 0.19fF
+C302 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
+C303 pd_0/and_pd_0/Out1 pd_0/tspc_r_1/Qbar 0.05fF
+C304 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
+C305 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
+C306 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
+C307 gnd divider_0/Out 0.29fF
+C308 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
+C309 cp_1/a_10_n50# cp_1/a_1710_0# 0.04fF
+C310 io_clamp_low[1] io_analog[5] 0.53fF
+C311 divider_0/nor_1/B divider_0/tspc_0/Q 0.22fF
+C312 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF
+C313 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF
+C314 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C315 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C316 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
+C317 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
+C318 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF
+C319 divider_0/prescaler_0/tspc_2/D gnd 0.05fF
+C320 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF
+C321 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF
+C322 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C323 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C324 pd_0/DOWN pd_0/UP 0.46fF
+C325 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C326 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C327 pd_0/R pd_0/and_pd_0/Z1 0.02fF
+C328 io_analog[2] io_analog[1] 0.02fF
+C329 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C330 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C331 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
+C332 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C333 divider_0/mc2 divider_0/and_0/A 0.16fF
+C334 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
+C335 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C336 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
+C337 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
+C338 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C339 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
+C340 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
+C341 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
+C342 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C343 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C344 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
+C345 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
+C346 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
+C347 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF
+C348 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
+C349 divider_0/nor_1/Z1 gnd 0.01fF
+C350 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
+C351 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF
+C352 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C353 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C354 cp_0/upbar cp_0/down 0.02fF
+C355 gnd divider_0/prescaler_0/nand_1/z1 0.16fF
+C356 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
+C357 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
+C358 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C359 pd_0/R pd_0/REF 0.61fF
+C360 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
+C361 gnd divider_0/and_0/Z1 0.41fF
+C362 cp_0/a_1710_0# cp_0/out 0.84fF
+C363 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C364 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
+C365 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
+C366 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C367 divider_0/tspc_1/Z2 divider_0/tspc_0/Q 0.14fF
+C368 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
+C369 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C370 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C371 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
+C372 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
+C373 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
+C374 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
+C375 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
+C376 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
+C377 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
+C378 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
+C379 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
+C380 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF
+C381 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF
+C382 io_clamp_high[0] io_analog[4] 0.53fF
+C383 divider_0/nor_1/B divider_0/and_0/B 0.31fF
+C384 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C385 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF
+C386 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C387 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C388 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C389 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C390 divider_0/tspc_1/Z4 divider_0/tspc_0/Q 0.15fF
+C391 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C392 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
+C393 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
+C394 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF
+C395 cp_0/a_1710_0# cp_0/down 0.32fF
+C396 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C397 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
+C398 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C399 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
+C400 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
+C401 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
+C402 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF
+C403 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF
+C404 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF
+C405 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
+C406 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C407 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C408 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
+C409 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
+C410 divider_0/nor_0/B divider_0/Out 0.22fF
+C411 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF
+C412 gnd divider_0/prescaler_0/Out 0.46fF
+C413 io_analog[3] cp_1/a_10_n50# 0.22fF
+C414 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
+C415 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
+C416 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C417 divider_0/nor_1/B gnd 1.10fF
+C418 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
 Xpd_0 VDD vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd
-Xcp_0 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp
-Xcp_1 cp_1/vbias vdd vssa1 cp_1/out cp_1/down cp_1/upbar cp
-Xfilter_0 vssa1 filter
+Xcp_0 cp_0/vbias vdd vssa1 cp_0/out cp_0/down cp_0/upbar cp
+Xcp_1 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp
+Xfilter_0 vssa1 filter_0/v filter
 Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4
 + ro_complete_0/a3 ro_complete_0/a2 ro_complete
 Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider
-C417 io_analog[4] vdda1 25.05fF
-C418 io_analog[5] vdda1 25.05fF
-C419 io_analog[6] vdda1 25.05fF
-C420 io_in_3v3[0] vdda1 0.61fF
-C421 io_oeb[26] vdda1 0.61fF
-C422 io_in[0] vdda1 0.61fF
-C423 io_out[26] vdda1 0.61fF
-C424 io_out[0] vdda1 0.61fF
-C425 io_in[26] vdda1 0.61fF
-C426 io_oeb[0] vdda1 0.61fF
-C427 io_in_3v3[26] vdda1 0.61fF
-C428 io_in_3v3[1] vdda1 0.61fF
-C429 io_oeb[25] vdda1 0.61fF
-C430 io_in[1] vdda1 0.61fF
-C431 io_out[25] vdda1 0.61fF
-C432 io_out[1] vdda1 0.61fF
-C433 io_in[25] vdda1 0.61fF
-C434 io_oeb[1] vdda1 0.61fF
-C435 io_in_3v3[25] vdda1 0.61fF
-C436 io_in_3v3[2] vdda1 0.61fF
-C437 io_oeb[24] vdda1 0.61fF
-C438 io_in[2] vdda1 0.61fF
-C439 io_out[24] vdda1 0.61fF
-C440 io_out[2] vdda1 0.61fF
-C441 io_in[24] vdda1 0.61fF
-C442 io_oeb[2] vdda1 0.61fF
-C443 io_in_3v3[24] vdda1 0.61fF
-C444 io_in_3v3[3] vdda1 0.61fF
-C445 gpio_noesd[17] vdda1 0.61fF
-C446 io_in[3] vdda1 0.61fF
-C447 gpio_analog[17] vdda1 0.61fF
-C448 io_out[3] vdda1 0.61fF
-C449 io_oeb[3] vdda1 0.61fF
-C450 io_in_3v3[4] vdda1 0.61fF
-C451 io_in[4] vdda1 0.61fF
-C452 io_out[4] vdda1 0.61fF
-C453 io_oeb[4] vdda1 0.61fF
-C454 io_oeb[23] vdda1 0.61fF
-C455 io_out[23] vdda1 0.61fF
-C456 io_in[23] vdda1 0.61fF
-C457 io_in_3v3[23] vdda1 0.61fF
-C458 gpio_noesd[16] vdda1 0.61fF
-C459 gpio_analog[16] vdda1 0.61fF
-C460 io_in_3v3[5] vdda1 0.61fF
-C461 io_in[5] vdda1 0.61fF
-C462 io_out[5] vdda1 0.61fF
-C463 io_oeb[5] vdda1 0.61fF
-C464 io_oeb[22] vdda1 0.61fF
-C465 io_out[22] vdda1 0.61fF
-C466 io_in[22] vdda1 0.61fF
-C467 io_in_3v3[22] vdda1 0.61fF
-C468 gpio_noesd[15] vdda1 0.61fF
-C469 gpio_analog[15] vdda1 0.61fF
-C470 io_in_3v3[6] vdda1 0.61fF
-C471 io_in[6] vdda1 0.61fF
-C472 io_out[6] vdda1 0.61fF
-C473 io_oeb[6] vdda1 0.61fF
-C474 io_oeb[21] vdda1 0.61fF
-C475 io_out[21] vdda1 0.61fF
-C476 io_in[21] vdda1 0.61fF
-C477 io_in_3v3[21] vdda1 0.61fF
-C478 gpio_noesd[14] vdda1 0.61fF
-C479 gpio_analog[14] vdda1 0.61fF
-C480 vssd2 vdda1 13.04fF
-C481 vssd1 vdda1 13.04fF
-C482 vdda2 vdda1 13.04fF
-C483 io_oeb[20] vdda1 0.61fF
-C484 io_out[20] vdda1 0.61fF
-C485 io_in[20] vdda1 0.61fF
-C486 io_in_3v3[20] vdda1 0.61fF
-C487 gpio_noesd[13] vdda1 0.61fF
-C488 gpio_analog[13] vdda1 0.61fF
-C489 gpio_analog[0] vdda1 0.61fF
-C490 gpio_noesd[0] vdda1 0.61fF
-C491 io_in_3v3[7] vdda1 0.61fF
-C492 io_in[7] vdda1 0.61fF
-C493 io_out[7] vdda1 0.61fF
-C494 io_oeb[7] vdda1 0.61fF
-C495 io_oeb[19] vdda1 0.61fF
-C496 io_out[19] vdda1 0.61fF
-C497 io_in[19] vdda1 0.61fF
-C498 io_in_3v3[19] vdda1 0.61fF
-C499 gpio_noesd[12] vdda1 0.61fF
-C500 gpio_analog[12] vdda1 0.61fF
-C501 gpio_analog[1] vdda1 0.61fF
-C502 gpio_noesd[1] vdda1 0.61fF
-C503 io_in_3v3[8] vdda1 0.61fF
-C504 io_in[8] vdda1 0.61fF
-C505 io_out[8] vdda1 0.61fF
-C506 io_oeb[8] vdda1 0.61fF
-C507 io_oeb[18] vdda1 0.61fF
-C508 io_out[18] vdda1 0.61fF
-C509 io_in[18] vdda1 0.61fF
-C510 io_in_3v3[18] vdda1 0.61fF
-C511 gpio_noesd[11] vdda1 0.61fF
-C512 gpio_analog[11] vdda1 0.61fF
-C513 gpio_analog[2] vdda1 0.61fF
-C514 gpio_noesd[2] vdda1 0.61fF
-C515 io_in_3v3[9] vdda1 0.61fF
-C516 io_in[9] vdda1 0.61fF
-C517 io_out[9] vdda1 0.61fF
-C518 io_oeb[9] vdda1 0.61fF
-C519 io_oeb[17] vdda1 0.61fF
-C520 io_out[17] vdda1 0.61fF
-C521 io_in[17] vdda1 0.61fF
-C522 io_in_3v3[17] vdda1 0.61fF
-C523 gpio_noesd[10] vdda1 0.61fF
-C524 gpio_analog[10] vdda1 0.61fF
-C525 gpio_analog[3] vdda1 0.61fF
-C526 gpio_noesd[3] vdda1 0.61fF
-C527 io_in_3v3[10] vdda1 0.61fF
-C528 io_in[10] vdda1 0.61fF
-C529 io_out[10] vdda1 0.61fF
-C530 io_oeb[10] vdda1 0.61fF
-C531 io_oeb[16] vdda1 0.61fF
-C532 io_out[16] vdda1 0.61fF
-C533 io_in[16] vdda1 0.61fF
-C534 io_in_3v3[16] vdda1 0.61fF
-C535 gpio_noesd[9] vdda1 0.61fF
-C536 gpio_analog[9] vdda1 0.61fF
-C537 gpio_analog[4] vdda1 0.61fF
-C538 gpio_noesd[4] vdda1 0.61fF
-C539 io_in_3v3[11] vdda1 0.61fF
-C540 io_in[11] vdda1 0.61fF
-C541 io_out[11] vdda1 0.61fF
-C542 io_oeb[11] vdda1 0.61fF
-C543 io_oeb[15] vdda1 0.61fF
-C544 io_out[15] vdda1 0.61fF
-C545 io_in[15] vdda1 0.61fF
-C546 io_in_3v3[15] vdda1 0.61fF
-C547 gpio_noesd[8] vdda1 0.61fF
-C548 gpio_analog[8] vdda1 0.61fF
-C549 gpio_analog[5] vdda1 0.61fF
-C550 gpio_noesd[5] vdda1 0.61fF
-C551 io_in_3v3[12] vdda1 0.61fF
-C552 io_in[12] vdda1 0.61fF
-C553 io_out[12] vdda1 0.61fF
-C554 io_oeb[12] vdda1 0.61fF
-C555 io_oeb[14] vdda1 0.61fF
-C556 io_out[14] vdda1 0.61fF
-C557 io_in[14] vdda1 0.61fF
-C558 io_in_3v3[14] vdda1 0.61fF
-C559 gpio_noesd[7] vdda1 0.61fF
-C560 gpio_analog[7] vdda1 0.61fF
-C561 vssa2 vdda1 13.04fF
-C562 gpio_analog[6] vdda1 0.61fF
-C563 gpio_noesd[6] vdda1 0.61fF
-C564 io_in_3v3[13] vdda1 0.61fF
-C565 io_in[13] vdda1 0.61fF
-C566 io_out[13] vdda1 0.61fF
-C567 io_oeb[13] vdda1 0.61fF
-C568 vccd1 vdda1 13.04fF
-C569 vccd2 vdda1 13.04fF
-C570 io_analog[10] vdda1 6.83fF
-C571 io_clamp_high[0] vdda1 3.58fF
-C572 io_clamp_low[0] vdda1 3.58fF
-C573 io_clamp_high[1] vdda1 3.58fF
-C574 io_clamp_low[1] vdda1 3.58fF
-C575 io_clamp_high[2] vdda1 3.58fF
-C576 io_clamp_low[2] vdda1 3.58fF
-C577 io_analog[7] vdda1 6.83fF
-C578 io_analog[8] vdda1 6.83fF
-C579 io_analog[9] vdda1 6.83fF
-C580 user_irq[2] vdda1 0.63fF
-C581 user_irq[1] vdda1 0.63fF
-C582 user_irq[0] vdda1 0.63fF
-C583 user_clock2 vdda1 0.63fF
-C584 la_oenb[127] vdda1 0.63fF
-C585 la_data_out[127] vdda1 0.63fF
-C586 la_data_in[127] vdda1 0.63fF
-C587 la_oenb[126] vdda1 0.63fF
-C588 la_data_out[126] vdda1 0.63fF
-C589 la_data_in[126] vdda1 0.63fF
-C590 la_oenb[125] vdda1 0.63fF
-C591 la_data_out[125] vdda1 0.63fF
-C592 la_data_in[125] vdda1 0.63fF
-C593 la_oenb[124] vdda1 0.63fF
-C594 la_data_out[124] vdda1 0.63fF
-C595 la_data_in[124] vdda1 0.63fF
-C596 la_oenb[123] vdda1 0.63fF
-C597 la_data_out[123] vdda1 0.63fF
-C598 la_data_in[123] vdda1 0.63fF
-C599 la_oenb[122] vdda1 0.63fF
-C600 la_data_out[122] vdda1 0.63fF
-C601 la_data_in[122] vdda1 0.63fF
-C602 la_oenb[121] vdda1 0.63fF
-C603 la_data_out[121] vdda1 0.63fF
-C604 la_data_in[121] vdda1 0.63fF
-C605 la_oenb[120] vdda1 0.63fF
-C606 la_data_out[120] vdda1 0.63fF
-C607 la_data_in[120] vdda1 0.63fF
-C608 la_oenb[119] vdda1 0.63fF
-C609 la_data_out[119] vdda1 0.63fF
-C610 la_data_in[119] vdda1 0.63fF
-C611 la_oenb[118] vdda1 0.63fF
-C612 la_data_out[118] vdda1 0.63fF
-C613 la_data_in[118] vdda1 0.63fF
-C614 la_oenb[117] vdda1 0.63fF
-C615 la_data_out[117] vdda1 0.63fF
-C616 la_data_in[117] vdda1 0.63fF
-C617 la_oenb[116] vdda1 0.63fF
-C618 la_data_out[116] vdda1 0.63fF
-C619 la_data_in[116] vdda1 0.63fF
-C620 la_oenb[115] vdda1 0.63fF
-C621 la_data_out[115] vdda1 0.63fF
-C622 la_data_in[115] vdda1 0.63fF
-C623 la_oenb[114] vdda1 0.63fF
-C624 la_data_out[114] vdda1 0.63fF
-C625 la_data_in[114] vdda1 0.63fF
-C626 la_oenb[113] vdda1 0.63fF
-C627 la_data_out[113] vdda1 0.63fF
-C628 la_data_in[113] vdda1 0.63fF
-C629 la_oenb[112] vdda1 0.63fF
-C630 la_data_out[112] vdda1 0.63fF
-C631 la_data_in[112] vdda1 0.63fF
-C632 la_oenb[111] vdda1 0.63fF
-C633 la_data_out[111] vdda1 0.63fF
-C634 la_data_in[111] vdda1 0.63fF
-C635 la_oenb[110] vdda1 0.63fF
-C636 la_data_out[110] vdda1 0.63fF
-C637 la_data_in[110] vdda1 0.63fF
-C638 la_oenb[109] vdda1 0.63fF
-C639 la_data_out[109] vdda1 0.63fF
-C640 la_data_in[109] vdda1 0.63fF
-C641 la_oenb[108] vdda1 0.63fF
-C642 la_data_out[108] vdda1 0.63fF
-C643 la_data_in[108] vdda1 0.63fF
-C644 la_oenb[107] vdda1 0.63fF
-C645 la_data_out[107] vdda1 0.63fF
-C646 la_data_in[107] vdda1 0.63fF
-C647 la_oenb[106] vdda1 0.63fF
-C648 la_data_out[106] vdda1 0.63fF
-C649 la_data_in[106] vdda1 0.63fF
-C650 la_oenb[105] vdda1 0.63fF
-C651 la_data_out[105] vdda1 0.63fF
-C652 la_data_in[105] vdda1 0.63fF
-C653 la_oenb[104] vdda1 0.63fF
-C654 la_data_out[104] vdda1 0.63fF
-C655 la_data_in[104] vdda1 0.63fF
-C656 la_oenb[103] vdda1 0.63fF
-C657 la_data_out[103] vdda1 0.63fF
-C658 la_data_in[103] vdda1 0.63fF
-C659 la_oenb[102] vdda1 0.63fF
-C660 la_data_out[102] vdda1 0.63fF
-C661 la_data_in[102] vdda1 0.63fF
-C662 la_oenb[101] vdda1 0.63fF
-C663 la_data_out[101] vdda1 0.63fF
-C664 la_data_in[101] vdda1 0.63fF
-C665 la_oenb[100] vdda1 0.63fF
-C666 la_data_out[100] vdda1 0.63fF
-C667 la_data_in[100] vdda1 0.63fF
-C668 la_oenb[99] vdda1 0.63fF
-C669 la_data_out[99] vdda1 0.63fF
-C670 la_data_in[99] vdda1 0.63fF
-C671 la_oenb[98] vdda1 0.63fF
-C672 la_data_out[98] vdda1 0.63fF
-C673 la_data_in[98] vdda1 0.63fF
-C674 la_oenb[97] vdda1 0.63fF
-C675 la_data_out[97] vdda1 0.63fF
-C676 la_data_in[97] vdda1 0.63fF
-C677 la_oenb[96] vdda1 0.63fF
-C678 la_data_out[96] vdda1 0.63fF
-C679 la_data_in[96] vdda1 0.63fF
-C680 la_oenb[95] vdda1 0.63fF
-C681 la_data_out[95] vdda1 0.63fF
-C682 la_data_in[95] vdda1 0.63fF
-C683 la_oenb[94] vdda1 0.63fF
-C684 la_data_out[94] vdda1 0.63fF
-C685 la_data_in[94] vdda1 0.63fF
-C686 la_oenb[93] vdda1 0.63fF
-C687 la_data_out[93] vdda1 0.63fF
-C688 la_data_in[93] vdda1 0.63fF
-C689 la_oenb[92] vdda1 0.63fF
-C690 la_data_out[92] vdda1 0.63fF
-C691 la_data_in[92] vdda1 0.63fF
-C692 la_oenb[91] vdda1 0.63fF
-C693 la_data_out[91] vdda1 0.63fF
-C694 la_data_in[91] vdda1 0.63fF
-C695 la_oenb[90] vdda1 0.63fF
-C696 la_data_out[90] vdda1 0.63fF
-C697 la_data_in[90] vdda1 0.63fF
-C698 la_oenb[89] vdda1 0.63fF
-C699 la_data_out[89] vdda1 0.63fF
-C700 la_data_in[89] vdda1 0.63fF
-C701 la_oenb[88] vdda1 0.63fF
-C702 la_data_out[88] vdda1 0.63fF
-C703 la_data_in[88] vdda1 0.63fF
-C704 la_oenb[87] vdda1 0.63fF
-C705 la_data_out[87] vdda1 0.63fF
-C706 la_data_in[87] vdda1 0.63fF
-C707 la_oenb[86] vdda1 0.63fF
-C708 la_data_out[86] vdda1 0.63fF
-C709 la_data_in[86] vdda1 0.63fF
-C710 la_oenb[85] vdda1 0.63fF
-C711 la_data_out[85] vdda1 0.63fF
-C712 la_data_in[85] vdda1 0.63fF
-C713 la_oenb[84] vdda1 0.63fF
-C714 la_data_out[84] vdda1 0.63fF
-C715 la_data_in[84] vdda1 0.63fF
-C716 la_oenb[83] vdda1 0.63fF
-C717 la_data_out[83] vdda1 0.63fF
-C718 la_data_in[83] vdda1 0.63fF
-C719 la_oenb[82] vdda1 0.63fF
-C720 la_data_out[82] vdda1 0.63fF
-C721 la_data_in[82] vdda1 0.63fF
-C722 la_oenb[81] vdda1 0.63fF
-C723 la_data_out[81] vdda1 0.63fF
-C724 la_data_in[81] vdda1 0.63fF
-C725 la_oenb[80] vdda1 0.63fF
-C726 la_data_out[80] vdda1 0.63fF
-C727 la_data_in[80] vdda1 0.63fF
-C728 la_oenb[79] vdda1 0.63fF
-C729 la_data_out[79] vdda1 0.63fF
-C730 la_data_in[79] vdda1 0.63fF
-C731 la_oenb[78] vdda1 0.63fF
-C732 la_data_out[78] vdda1 0.63fF
-C733 la_data_in[78] vdda1 0.63fF
-C734 la_oenb[77] vdda1 0.63fF
-C735 la_data_out[77] vdda1 0.63fF
-C736 la_data_in[77] vdda1 0.63fF
-C737 la_oenb[76] vdda1 0.63fF
-C738 la_data_out[76] vdda1 0.63fF
-C739 la_data_in[76] vdda1 0.63fF
-C740 la_oenb[75] vdda1 0.63fF
-C741 la_data_out[75] vdda1 0.63fF
-C742 la_data_in[75] vdda1 0.63fF
-C743 la_oenb[74] vdda1 0.63fF
-C744 la_data_out[74] vdda1 0.63fF
-C745 la_data_in[74] vdda1 0.63fF
-C746 la_oenb[73] vdda1 0.63fF
-C747 la_data_out[73] vdda1 0.63fF
-C748 la_data_in[73] vdda1 0.63fF
-C749 la_oenb[72] vdda1 0.63fF
-C750 la_data_out[72] vdda1 0.63fF
-C751 la_data_in[72] vdda1 0.63fF
-C752 la_oenb[71] vdda1 0.63fF
-C753 la_data_out[71] vdda1 0.63fF
-C754 la_data_in[71] vdda1 0.63fF
-C755 la_oenb[70] vdda1 0.63fF
-C756 la_data_out[70] vdda1 0.63fF
-C757 la_data_in[70] vdda1 0.63fF
-C758 la_oenb[69] vdda1 0.63fF
-C759 la_data_out[69] vdda1 0.63fF
-C760 la_data_in[69] vdda1 0.63fF
-C761 la_oenb[68] vdda1 0.63fF
-C762 la_data_out[68] vdda1 0.63fF
-C763 la_data_in[68] vdda1 0.63fF
-C764 la_oenb[67] vdda1 0.63fF
-C765 la_data_out[67] vdda1 0.63fF
-C766 la_data_in[67] vdda1 0.63fF
-C767 la_oenb[66] vdda1 0.63fF
-C768 la_data_out[66] vdda1 0.63fF
-C769 la_data_in[66] vdda1 0.63fF
-C770 la_oenb[65] vdda1 0.63fF
-C771 la_data_out[65] vdda1 0.63fF
-C772 la_data_in[65] vdda1 0.63fF
-C773 la_oenb[64] vdda1 0.63fF
-C774 la_data_out[64] vdda1 0.63fF
-C775 la_data_in[64] vdda1 0.63fF
-C776 la_oenb[63] vdda1 0.63fF
-C777 la_data_out[63] vdda1 0.63fF
-C778 la_data_in[63] vdda1 0.63fF
-C779 la_oenb[62] vdda1 0.63fF
-C780 la_data_out[62] vdda1 0.63fF
-C781 la_data_in[62] vdda1 0.63fF
-C782 la_oenb[61] vdda1 0.63fF
-C783 la_data_out[61] vdda1 0.63fF
-C784 la_data_in[61] vdda1 0.63fF
-C785 la_oenb[60] vdda1 0.63fF
-C786 la_data_out[60] vdda1 0.63fF
-C787 la_data_in[60] vdda1 0.63fF
-C788 la_oenb[59] vdda1 0.63fF
-C789 la_data_out[59] vdda1 0.63fF
-C790 la_data_in[59] vdda1 0.63fF
-C791 la_oenb[58] vdda1 0.63fF
-C792 la_data_out[58] vdda1 0.63fF
-C793 la_data_in[58] vdda1 0.63fF
-C794 la_oenb[57] vdda1 0.63fF
-C795 la_data_out[57] vdda1 0.63fF
-C796 la_data_in[57] vdda1 0.63fF
-C797 la_oenb[56] vdda1 0.63fF
-C798 la_data_out[56] vdda1 0.63fF
-C799 la_data_in[56] vdda1 0.63fF
-C800 la_oenb[55] vdda1 0.63fF
-C801 la_data_out[55] vdda1 0.63fF
-C802 la_data_in[55] vdda1 0.63fF
-C803 la_oenb[54] vdda1 0.63fF
-C804 la_data_out[54] vdda1 0.63fF
-C805 la_data_in[54] vdda1 0.63fF
-C806 la_oenb[53] vdda1 0.63fF
-C807 la_data_out[53] vdda1 0.63fF
-C808 la_data_in[53] vdda1 0.63fF
-C809 la_oenb[52] vdda1 0.63fF
-C810 la_data_out[52] vdda1 0.63fF
-C811 la_data_in[52] vdda1 0.63fF
-C812 la_oenb[51] vdda1 0.63fF
-C813 la_data_out[51] vdda1 0.63fF
-C814 la_data_in[51] vdda1 0.63fF
-C815 la_oenb[50] vdda1 0.63fF
-C816 la_data_out[50] vdda1 0.63fF
-C817 la_data_in[50] vdda1 0.63fF
-C818 la_oenb[49] vdda1 0.63fF
-C819 la_data_out[49] vdda1 0.63fF
-C820 la_data_in[49] vdda1 0.63fF
-C821 la_oenb[48] vdda1 0.63fF
-C822 la_data_out[48] vdda1 0.63fF
-C823 la_data_in[48] vdda1 0.63fF
-C824 la_oenb[47] vdda1 0.63fF
-C825 la_data_out[47] vdda1 0.63fF
-C826 la_data_in[47] vdda1 0.63fF
-C827 la_oenb[46] vdda1 0.63fF
-C828 la_data_out[46] vdda1 0.63fF
-C829 la_data_in[46] vdda1 0.63fF
-C830 la_oenb[45] vdda1 0.63fF
-C831 la_data_out[45] vdda1 0.63fF
-C832 la_data_in[45] vdda1 0.63fF
-C833 la_oenb[44] vdda1 0.63fF
-C834 la_data_out[44] vdda1 0.63fF
-C835 la_data_in[44] vdda1 0.63fF
-C836 la_oenb[43] vdda1 0.63fF
-C837 la_data_out[43] vdda1 0.63fF
-C838 la_data_in[43] vdda1 0.63fF
-C839 la_oenb[42] vdda1 0.63fF
-C840 la_data_out[42] vdda1 0.63fF
-C841 la_data_in[42] vdda1 0.63fF
-C842 la_oenb[41] vdda1 0.63fF
-C843 la_data_out[41] vdda1 0.63fF
-C844 la_data_in[41] vdda1 0.63fF
-C845 la_oenb[40] vdda1 0.63fF
-C846 la_data_out[40] vdda1 0.63fF
-C847 la_data_in[40] vdda1 0.63fF
-C848 la_oenb[39] vdda1 0.63fF
-C849 la_data_out[39] vdda1 0.63fF
-C850 la_data_in[39] vdda1 0.63fF
-C851 la_oenb[38] vdda1 0.63fF
-C852 la_data_out[38] vdda1 0.63fF
-C853 la_data_in[38] vdda1 0.63fF
-C854 la_oenb[37] vdda1 0.63fF
-C855 la_data_out[37] vdda1 0.63fF
-C856 la_data_in[37] vdda1 0.63fF
-C857 la_oenb[36] vdda1 0.63fF
-C858 la_data_out[36] vdda1 0.63fF
-C859 la_data_in[36] vdda1 0.63fF
-C860 la_oenb[35] vdda1 0.63fF
-C861 la_data_out[35] vdda1 0.63fF
-C862 la_data_in[35] vdda1 0.63fF
-C863 la_oenb[34] vdda1 0.63fF
-C864 la_data_out[34] vdda1 0.63fF
-C865 la_data_in[34] vdda1 0.63fF
-C866 la_oenb[33] vdda1 0.63fF
-C867 la_data_out[33] vdda1 0.63fF
-C868 la_data_in[33] vdda1 0.63fF
-C869 la_oenb[32] vdda1 0.63fF
-C870 la_data_out[32] vdda1 0.63fF
-C871 la_data_in[32] vdda1 0.63fF
-C872 la_oenb[31] vdda1 0.63fF
-C873 la_data_out[31] vdda1 0.63fF
-C874 la_data_in[31] vdda1 0.63fF
-C875 la_oenb[30] vdda1 0.63fF
-C876 la_data_out[30] vdda1 0.63fF
-C877 la_data_in[30] vdda1 0.63fF
-C878 la_oenb[29] vdda1 0.63fF
-C879 la_data_out[29] vdda1 0.63fF
-C880 la_data_in[29] vdda1 0.63fF
-C881 la_oenb[28] vdda1 0.63fF
-C882 la_data_out[28] vdda1 0.63fF
-C883 la_data_in[28] vdda1 0.63fF
-C884 la_oenb[27] vdda1 0.63fF
-C885 la_data_out[27] vdda1 0.63fF
-C886 la_data_in[27] vdda1 0.63fF
-C887 la_oenb[26] vdda1 0.63fF
-C888 la_data_out[26] vdda1 0.63fF
-C889 la_data_in[26] vdda1 0.63fF
-C890 la_oenb[25] vdda1 0.63fF
-C891 la_data_out[25] vdda1 0.63fF
-C892 la_data_in[25] vdda1 0.63fF
-C893 la_oenb[24] vdda1 0.63fF
-C894 la_data_out[24] vdda1 0.63fF
-C895 la_data_in[24] vdda1 0.63fF
-C896 la_oenb[23] vdda1 0.63fF
-C897 la_data_out[23] vdda1 0.63fF
-C898 la_data_in[23] vdda1 0.63fF
-C899 la_oenb[22] vdda1 0.63fF
-C900 la_data_out[22] vdda1 0.63fF
-C901 la_data_in[22] vdda1 0.63fF
-C902 la_oenb[21] vdda1 0.63fF
-C903 la_data_out[21] vdda1 0.63fF
-C904 la_data_in[21] vdda1 0.63fF
-C905 la_oenb[20] vdda1 0.63fF
-C906 la_data_out[20] vdda1 0.63fF
-C907 la_data_in[20] vdda1 0.63fF
-C908 la_oenb[19] vdda1 0.63fF
-C909 la_data_out[19] vdda1 0.63fF
-C910 la_data_in[19] vdda1 0.63fF
-C911 la_oenb[18] vdda1 0.63fF
-C912 la_data_out[18] vdda1 0.63fF
-C913 la_data_in[18] vdda1 0.63fF
-C914 la_oenb[17] vdda1 0.63fF
-C915 la_data_out[17] vdda1 0.63fF
-C916 la_data_in[17] vdda1 0.63fF
-C917 la_oenb[16] vdda1 0.63fF
-C918 la_data_out[16] vdda1 0.63fF
-C919 la_data_in[16] vdda1 0.63fF
-C920 la_oenb[15] vdda1 0.63fF
-C921 la_data_out[15] vdda1 0.63fF
-C922 la_data_in[15] vdda1 0.63fF
-C923 la_oenb[14] vdda1 0.63fF
-C924 la_data_out[14] vdda1 0.63fF
-C925 la_data_in[14] vdda1 0.63fF
-C926 la_oenb[13] vdda1 0.63fF
-C927 la_data_out[13] vdda1 0.63fF
-C928 la_data_in[13] vdda1 0.63fF
-C929 la_oenb[12] vdda1 0.63fF
-C930 la_data_out[12] vdda1 0.63fF
-C931 la_data_in[12] vdda1 0.63fF
-C932 la_oenb[11] vdda1 0.63fF
-C933 la_data_out[11] vdda1 0.63fF
-C934 la_data_in[11] vdda1 0.63fF
-C935 la_oenb[10] vdda1 0.63fF
-C936 la_data_out[10] vdda1 0.63fF
-C937 la_data_in[10] vdda1 0.63fF
-C938 la_oenb[9] vdda1 0.63fF
-C939 la_data_out[9] vdda1 0.63fF
-C940 la_data_in[9] vdda1 0.63fF
-C941 la_oenb[8] vdda1 0.63fF
-C942 la_data_out[8] vdda1 0.63fF
-C943 la_data_in[8] vdda1 0.63fF
-C944 la_oenb[7] vdda1 0.63fF
-C945 la_data_out[7] vdda1 0.63fF
-C946 la_data_in[7] vdda1 0.63fF
-C947 la_oenb[6] vdda1 0.63fF
-C948 la_data_out[6] vdda1 0.63fF
-C949 la_data_in[6] vdda1 0.63fF
-C950 la_oenb[5] vdda1 0.63fF
-C951 la_data_out[5] vdda1 0.63fF
-C952 la_data_in[5] vdda1 0.63fF
-C953 la_oenb[4] vdda1 0.63fF
-C954 la_data_out[4] vdda1 0.63fF
-C955 la_data_in[4] vdda1 0.63fF
-C956 la_oenb[3] vdda1 0.63fF
-C957 la_data_out[3] vdda1 0.63fF
-C958 la_data_in[3] vdda1 0.63fF
-C959 la_oenb[2] vdda1 0.63fF
-C960 la_data_out[2] vdda1 0.63fF
-C961 la_data_in[2] vdda1 0.63fF
-C962 la_oenb[1] vdda1 0.63fF
-C963 la_data_out[1] vdda1 0.63fF
-C964 la_data_in[1] vdda1 0.63fF
-C965 la_oenb[0] vdda1 0.63fF
-C966 la_data_out[0] vdda1 0.63fF
-C967 la_data_in[0] vdda1 0.63fF
-C968 wbs_dat_o[31] vdda1 0.63fF
-C969 wbs_dat_i[31] vdda1 0.63fF
-C970 wbs_adr_i[31] vdda1 0.63fF
-C971 wbs_dat_o[30] vdda1 0.63fF
-C972 wbs_dat_i[30] vdda1 0.63fF
-C973 wbs_adr_i[30] vdda1 0.63fF
-C974 wbs_dat_o[29] vdda1 0.63fF
-C975 wbs_dat_i[29] vdda1 0.63fF
-C976 wbs_adr_i[29] vdda1 0.63fF
-C977 wbs_dat_o[28] vdda1 0.63fF
-C978 wbs_dat_i[28] vdda1 0.63fF
-C979 wbs_adr_i[28] vdda1 0.63fF
-C980 wbs_dat_o[27] vdda1 0.63fF
-C981 wbs_dat_i[27] vdda1 0.63fF
-C982 wbs_adr_i[27] vdda1 0.63fF
-C983 wbs_dat_o[26] vdda1 0.63fF
-C984 wbs_dat_i[26] vdda1 0.63fF
-C985 wbs_adr_i[26] vdda1 0.63fF
-C986 wbs_dat_o[25] vdda1 0.63fF
-C987 wbs_dat_i[25] vdda1 0.63fF
-C988 wbs_adr_i[25] vdda1 0.63fF
-C989 wbs_dat_o[24] vdda1 0.63fF
-C990 wbs_dat_i[24] vdda1 0.63fF
-C991 wbs_adr_i[24] vdda1 0.63fF
-C992 wbs_dat_o[23] vdda1 0.63fF
-C993 wbs_dat_i[23] vdda1 0.63fF
-C994 wbs_adr_i[23] vdda1 0.63fF
-C995 wbs_dat_o[22] vdda1 0.63fF
-C996 wbs_dat_i[22] vdda1 0.63fF
-C997 wbs_adr_i[22] vdda1 0.63fF
-C998 wbs_dat_o[21] vdda1 0.63fF
-C999 wbs_dat_i[21] vdda1 0.63fF
-C1000 wbs_adr_i[21] vdda1 0.63fF
-C1001 wbs_dat_o[20] vdda1 0.63fF
-C1002 wbs_dat_i[20] vdda1 0.63fF
-C1003 wbs_adr_i[20] vdda1 0.63fF
-C1004 wbs_dat_o[19] vdda1 0.63fF
-C1005 wbs_dat_i[19] vdda1 0.63fF
-C1006 wbs_adr_i[19] vdda1 0.63fF
-C1007 wbs_dat_o[18] vdda1 0.63fF
-C1008 wbs_dat_i[18] vdda1 0.63fF
-C1009 wbs_adr_i[18] vdda1 0.63fF
-C1010 wbs_dat_o[17] vdda1 0.63fF
-C1011 wbs_dat_i[17] vdda1 0.63fF
-C1012 wbs_adr_i[17] vdda1 0.63fF
-C1013 wbs_dat_o[16] vdda1 0.63fF
-C1014 wbs_dat_i[16] vdda1 0.63fF
-C1015 wbs_adr_i[16] vdda1 0.63fF
-C1016 wbs_dat_o[15] vdda1 0.63fF
-C1017 wbs_dat_i[15] vdda1 0.63fF
-C1018 wbs_adr_i[15] vdda1 0.63fF
-C1019 wbs_dat_o[14] vdda1 0.63fF
-C1020 wbs_dat_i[14] vdda1 0.63fF
-C1021 wbs_adr_i[14] vdda1 0.63fF
-C1022 wbs_dat_o[13] vdda1 0.63fF
-C1023 wbs_dat_i[13] vdda1 0.63fF
-C1024 wbs_adr_i[13] vdda1 0.63fF
-C1025 wbs_dat_o[12] vdda1 0.63fF
-C1026 wbs_dat_i[12] vdda1 0.63fF
-C1027 wbs_adr_i[12] vdda1 0.63fF
-C1028 wbs_dat_o[11] vdda1 0.63fF
-C1029 wbs_dat_i[11] vdda1 0.63fF
-C1030 wbs_adr_i[11] vdda1 0.63fF
-C1031 wbs_dat_o[10] vdda1 0.63fF
-C1032 wbs_dat_i[10] vdda1 0.63fF
-C1033 wbs_adr_i[10] vdda1 0.63fF
-C1034 wbs_dat_o[9] vdda1 0.63fF
-C1035 wbs_dat_i[9] vdda1 0.63fF
-C1036 wbs_adr_i[9] vdda1 0.63fF
-C1037 wbs_dat_o[8] vdda1 0.63fF
-C1038 wbs_dat_i[8] vdda1 0.63fF
-C1039 wbs_adr_i[8] vdda1 0.63fF
-C1040 wbs_dat_o[7] vdda1 0.63fF
-C1041 wbs_dat_i[7] vdda1 0.63fF
-C1042 wbs_adr_i[7] vdda1 0.63fF
-C1043 wbs_dat_o[6] vdda1 0.63fF
-C1044 wbs_dat_i[6] vdda1 0.63fF
-C1045 wbs_adr_i[6] vdda1 0.63fF
-C1046 wbs_dat_o[5] vdda1 0.63fF
-C1047 wbs_dat_i[5] vdda1 0.63fF
-C1048 wbs_adr_i[5] vdda1 0.63fF
-C1049 wbs_dat_o[4] vdda1 0.63fF
-C1050 wbs_dat_i[4] vdda1 0.63fF
-C1051 wbs_adr_i[4] vdda1 0.63fF
-C1052 wbs_sel_i[3] vdda1 0.63fF
-C1053 wbs_dat_o[3] vdda1 0.63fF
-C1054 wbs_dat_i[3] vdda1 0.63fF
-C1055 wbs_adr_i[3] vdda1 0.63fF
-C1056 wbs_sel_i[2] vdda1 0.63fF
-C1057 wbs_dat_o[2] vdda1 0.63fF
-C1058 wbs_dat_i[2] vdda1 0.63fF
-C1059 wbs_adr_i[2] vdda1 0.63fF
-C1060 wbs_sel_i[1] vdda1 0.63fF
-C1061 wbs_dat_o[1] vdda1 0.63fF
-C1062 wbs_dat_i[1] vdda1 0.63fF
-C1063 wbs_adr_i[1] vdda1 0.63fF
-C1064 wbs_sel_i[0] vdda1 0.63fF
-C1065 wbs_dat_o[0] vdda1 0.63fF
-C1066 wbs_dat_i[0] vdda1 0.63fF
-C1067 wbs_adr_i[0] vdda1 0.63fF
-C1068 wbs_we_i vdda1 0.63fF
-C1069 wbs_stb_i vdda1 0.63fF
-C1070 wbs_cyc_i vdda1 0.63fF
-C1071 wbs_ack_o vdda1 0.63fF
-C1072 wb_rst_i vdda1 0.63fF
-C1073 wb_clk_i vdda1 0.63fF
-C1074 divider_0/and_0/Z1 vdda1 0.33fF
-C1075 divider_0/and_0/B vdda1 1.79fF
-C1076 divider_0/and_0/A vdda1 1.66fF
-C1077 divider_0/and_0/out1 vdda1 2.71fF
-C1078 divider_0/tspc_2/Z4 vdda1 0.42fF
-C1079 divider_0/Out vdda1 1.31fF
-C1080 divider_0/tspc_2/Z3 vdda1 2.00fF
-C1081 divider_0/tspc_2/Z2 vdda1 1.29fF
-C1082 divider_0/tspc_2/Z1 vdda1 0.99fF
-C1083 divider_0/nor_0/B vdda1 5.25fF
-C1084 divider_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING
-C1085 divider_0/tspc_1/Z4 vdda1 0.42fF
-C1086 divider_0/tspc_1/Q vdda1 2.79fF
-C1087 divider_0/tspc_1/Z3 vdda1 2.00fF
-C1088 divider_0/tspc_1/Z2 vdda1 1.29fF
-C1089 divider_0/tspc_1/Z1 vdda1 0.99fF
-C1090 divider_0/nor_1/B vdda1 5.95fF
-C1091 divider_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING
-C1092 divider_0/tspc_0/Z4 vdda1 0.42fF
-C1093 divider_0/tspc_0/Q vdda1 2.81fF
-C1094 divider_0/tspc_0/Z3 vdda1 2.00fF
-C1095 divider_0/tspc_0/Z2 vdda1 1.30fF
-C1096 divider_0/tspc_0/Z1 vdda1 0.99fF
-C1097 divider_0/nor_1/A vdda1 6.02fF
-C1098 divider_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING
-C1099 divider_0/clk vdda1 5.56fF
-C1100 divider_0/prescaler_0/Out vdda1 4.13fF
-C1101 divider_0/prescaler_0/nand_1/z1 vdda1 0.20fF
-C1102 gnd vdda1 21.94fF
-C1103 divider_0/prescaler_0/tspc_2/D vdda1 2.59fF
-C1104 divider_0/prescaler_0/tspc_0/Q vdda1 3.30fF
-C1105 divider_0/prescaler_0/tspc_1/Q vdda1 2.78fF
-C1106 divider_0/prescaler_0/nand_0/z1 vdda1 0.20fF
-C1107 divider_0/prescaler_0/tspc_0/D vdda1 3.07fF
-C1108 divider_0/and_0/OUT vdda1 5.35fF
-C1109 divider_0/prescaler_0/tspc_2/Z4 vdda1 0.42fF
-C1110 divider_0/prescaler_0/tspc_2/Z3 vdda1 2.00fF
-C1111 divider_0/prescaler_0/tspc_2/Z2 vdda1 1.30fF
-C1112 divider_0/prescaler_0/tspc_2/Z1 vdda1 0.99fF
-C1113 divider_0/prescaler_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING
-C1114 divider_0/prescaler_0/tspc_2/a_740_n680# vdda1 1.89fF **FLOATING
-C1115 divider_0/prescaler_0/tspc_1/Z4 vdda1 0.42fF
-C1116 divider_0/prescaler_0/tspc_1/Z3 vdda1 2.00fF
-C1117 divider_0/prescaler_0/tspc_1/Z2 vdda1 1.31fF
-C1118 divider_0/prescaler_0/tspc_1/Z1 vdda1 0.99fF
-C1119 divider_0/prescaler_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING
-C1120 divider_0/prescaler_0/m1_2700_2190# vdda1 3.99fF **FLOATING
-C1121 divider_0/prescaler_0/tspc_0/Z4 vdda1 0.42fF
-C1122 divider_0/prescaler_0/tspc_0/Z3 vdda1 2.00fF
-C1123 divider_0/prescaler_0/tspc_0/Z2 vdda1 1.30fF
-C1124 divider_0/prescaler_0/tspc_0/Z1 vdda1 0.99fF
-C1125 divider_0/prescaler_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING
-C1126 divider_0/prescaler_0/tspc_0/a_740_n680# vdda1 1.89fF **FLOATING
-C1127 divider_0/nor_1/Z1 vdda1 1.33fF
-C1128 divider_0/nor_0/Z1 vdda1 1.33fF
-C1129 divider_0/mc2 vdda1 3.93fF
-C1130 ro_complete_0/cbank_2/v vdda1 17.84fF
-C1131 ro_complete_0/cbank_2/switch_5/vin vdda1 0.78fF
-C1132 ro_complete_0/cbank_2/switch_4/vin vdda1 1.50fF
-C1133 ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF
-C1134 ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF
-C1135 ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF
-C1136 ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF
-C1137 ro_complete_0/cbank_1/v vdda1 16.11fF
-C1138 ro_complete_0/cbank_1/switch_5/vin vdda1 0.78fF
-C1139 ro_complete_0/a0 vdda1 7.88fF
-C1140 ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF
-C1141 ro_complete_0/a1 vdda1 5.39fF
-C1142 ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF
-C1143 ro_complete_0/a3 vdda1 6.85fF
-C1144 ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF
-C1145 ro_complete_0/a2 vdda1 5.48fF
-C1146 ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF
-C1147 ro_complete_0/a4 vdda1 5.36fF
-C1148 ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF
-C1149 ro_complete_0/a5 vdda1 5.19fF
-C1150 ro_complete_0/cbank_0/v vdda1 14.98fF
-C1151 ro_complete_0/cbank_0/switch_5/vin vdda1 0.78fF
-C1152 ro_complete_0/cbank_0/switch_4/vin vdda1 1.50fF
-C1153 ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF
-C1154 ro_complete_0/cbank_0/switch_3/vin vdda1 0.56fF
-C1155 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
-C1156 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
-C1157 ro_complete_0/ro_var_extend_0/vcont vdda1 0.57fF
-C1158 filter_0/a_3976_n5230# vdda1 415.26fF **FLOATING
-C1159 filter_0/a_3976_n2998# vdda1 1.34fF **FLOATING
-C1160 cp_1/down vdda1 1.54fF
-C1161 cp_1/vbias vdda1 2.41fF
-C1162 cp_1/out vdda1 5.26fF
-C1163 cp_1/upbar vdda1 1.50fF
-C1164 cp_1/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1165 cp_1/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1166 cp_1/a_7110_0# vdda1 0.17fF **FLOATING
-C1167 cp_1/a_6370_0# vdda1 0.40fF **FLOATING
-C1168 cp_1/a_3060_0# vdda1 1.65fF **FLOATING
-C1169 cp_1/a_1710_0# vdda1 5.76fF **FLOATING
-C1170 cp_1/a_1710_n2840# vdda1 4.89fF **FLOATING
-C1171 cp_1/a_10_n50# vdda1 2.96fF **FLOATING
-C1172 io_analog[1] vdda1 108.63fF
-C1173 io_analog[3] vdda1 197.37fF
-C1174 io_analog[0] vdda1 74.25fF
-C1175 io_analog[2] vdda1 108.15fF
-C1176 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
-C1177 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
-C1178 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
-C1179 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
-C1180 cp_0/a_3060_0# vdda1 4.15fF **FLOATING
-C1181 cp_0/a_1710_0# vdda1 6.63fF **FLOATING
-C1182 cp_0/a_10_n50# vdda1 2.96fF **FLOATING
-C1183 pd_0/and_pd_0/Z1 vdda1 0.39fF
-C1184 pd_0/and_pd_0/Out1 vdda1 2.22fF
-C1185 pd_0/tspc_r_1/z5 vdda1 1.10fF
-C1186 pd_0/tspc_r_1/Z4 vdda1 1.07fF
-C1187 pd_0/tspc_r_1/Qbar vdda1 0.88fF
-C1188 pd_0/tspc_r_1/Z2 vdda1 1.22fF
-C1189 pd_0/tspc_r_1/Z1 vdda1 0.67fF
-C1190 pd_0/UP vdda1 2.21fF
-C1191 pd_0/tspc_r_1/Qbar1 vdda1 1.34fF
-C1192 pd_0/tspc_r_1/Z3 vdda1 2.12fF
-C1193 pd_0/REF vdda1 1.80fF
-C1194 pd_0/tspc_r_0/z5 vdda1 1.10fF
-C1195 pd_0/tspc_r_0/Z4 vdda1 1.07fF
-C1196 pd_0/R vdda1 3.05fF
-C1197 pd_0/tspc_r_0/Qbar vdda1 0.79fF
-C1198 pd_0/tspc_r_0/Z2 vdda1 1.22fF
-C1199 pd_0/tspc_r_0/Z1 vdda1 0.67fF
-C1200 pd_0/DOWN vdda1 3.08fF
-C1201 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
-C1202 pd_0/tspc_r_0/Z3 vdda1 2.12fF
-C1203 pd_0/DIV vdda1 1.82fF
+C419 io_analog[4] vdda1 25.05fF
+C420 io_analog[5] vdda1 25.05fF
+C421 io_analog[6] vdda1 25.05fF
+C422 io_in_3v3[0] vdda1 0.61fF
+C423 io_oeb[26] vdda1 0.61fF
+C424 io_in[0] vdda1 0.61fF
+C425 io_out[26] vdda1 0.61fF
+C426 io_out[0] vdda1 0.61fF
+C427 io_in[26] vdda1 0.61fF
+C428 io_oeb[0] vdda1 0.61fF
+C429 io_in_3v3[26] vdda1 0.61fF
+C430 io_in_3v3[1] vdda1 0.61fF
+C431 io_oeb[25] vdda1 0.61fF
+C432 io_in[1] vdda1 0.61fF
+C433 io_out[25] vdda1 0.61fF
+C434 io_out[1] vdda1 0.61fF
+C435 io_in[25] vdda1 0.61fF
+C436 io_oeb[1] vdda1 0.61fF
+C437 io_in_3v3[25] vdda1 0.61fF
+C438 io_in_3v3[2] vdda1 0.61fF
+C439 io_oeb[24] vdda1 0.61fF
+C440 io_in[2] vdda1 0.61fF
+C441 io_out[24] vdda1 0.61fF
+C442 io_out[2] vdda1 0.61fF
+C443 io_in[24] vdda1 0.61fF
+C444 io_oeb[2] vdda1 0.61fF
+C445 io_in_3v3[24] vdda1 0.61fF
+C446 io_in_3v3[3] vdda1 0.61fF
+C447 gpio_noesd[17] vdda1 0.61fF
+C448 io_in[3] vdda1 0.61fF
+C449 gpio_analog[17] vdda1 0.61fF
+C450 io_out[3] vdda1 0.61fF
+C451 io_oeb[3] vdda1 0.61fF
+C452 io_in_3v3[4] vdda1 0.61fF
+C453 io_in[4] vdda1 0.61fF
+C454 io_out[4] vdda1 0.61fF
+C455 io_oeb[4] vdda1 0.61fF
+C456 io_oeb[23] vdda1 0.61fF
+C457 io_out[23] vdda1 0.61fF
+C458 io_in[23] vdda1 0.61fF
+C459 io_in_3v3[23] vdda1 0.61fF
+C460 gpio_noesd[16] vdda1 0.61fF
+C461 gpio_analog[16] vdda1 0.61fF
+C462 io_in_3v3[5] vdda1 0.61fF
+C463 io_in[5] vdda1 0.61fF
+C464 io_out[5] vdda1 0.61fF
+C465 io_oeb[5] vdda1 0.61fF
+C466 io_oeb[22] vdda1 0.61fF
+C467 io_out[22] vdda1 0.61fF
+C468 io_in[22] vdda1 0.61fF
+C469 io_in_3v3[22] vdda1 0.61fF
+C470 gpio_noesd[15] vdda1 0.61fF
+C471 gpio_analog[15] vdda1 0.61fF
+C472 io_in_3v3[6] vdda1 0.61fF
+C473 io_in[6] vdda1 0.61fF
+C474 io_out[6] vdda1 0.61fF
+C475 io_oeb[6] vdda1 0.61fF
+C476 io_oeb[21] vdda1 0.61fF
+C477 io_out[21] vdda1 0.61fF
+C478 io_in[21] vdda1 0.61fF
+C479 io_in_3v3[21] vdda1 0.61fF
+C480 gpio_noesd[14] vdda1 0.61fF
+C481 gpio_analog[14] vdda1 0.61fF
+C482 vssd2 vdda1 13.04fF
+C483 vssd1 vdda1 13.04fF
+C484 vdda2 vdda1 13.04fF
+C485 io_oeb[20] vdda1 0.61fF
+C486 io_out[20] vdda1 0.61fF
+C487 io_in[20] vdda1 0.61fF
+C488 io_in_3v3[20] vdda1 0.61fF
+C489 gpio_noesd[13] vdda1 0.61fF
+C490 gpio_analog[13] vdda1 0.61fF
+C491 gpio_analog[0] vdda1 0.61fF
+C492 gpio_noesd[0] vdda1 0.61fF
+C493 io_in_3v3[7] vdda1 0.61fF
+C494 io_in[7] vdda1 0.61fF
+C495 io_out[7] vdda1 0.61fF
+C496 io_oeb[7] vdda1 0.61fF
+C497 io_oeb[19] vdda1 0.61fF
+C498 io_out[19] vdda1 0.61fF
+C499 io_in[19] vdda1 0.61fF
+C500 io_in_3v3[19] vdda1 0.61fF
+C501 gpio_noesd[12] vdda1 0.61fF
+C502 gpio_analog[12] vdda1 0.61fF
+C503 gpio_analog[1] vdda1 0.61fF
+C504 gpio_noesd[1] vdda1 0.61fF
+C505 io_in_3v3[8] vdda1 0.61fF
+C506 io_in[8] vdda1 0.61fF
+C507 io_out[8] vdda1 0.61fF
+C508 io_oeb[8] vdda1 0.61fF
+C509 io_oeb[18] vdda1 0.61fF
+C510 io_out[18] vdda1 0.61fF
+C511 io_in[18] vdda1 0.61fF
+C512 io_in_3v3[18] vdda1 0.61fF
+C513 gpio_noesd[11] vdda1 0.61fF
+C514 gpio_analog[11] vdda1 0.61fF
+C515 gpio_analog[2] vdda1 0.61fF
+C516 gpio_noesd[2] vdda1 0.61fF
+C517 io_in_3v3[9] vdda1 0.61fF
+C518 io_in[9] vdda1 0.61fF
+C519 io_out[9] vdda1 0.61fF
+C520 io_oeb[9] vdda1 0.61fF
+C521 io_oeb[17] vdda1 0.61fF
+C522 io_out[17] vdda1 0.61fF
+C523 io_in[17] vdda1 0.61fF
+C524 io_in_3v3[17] vdda1 0.61fF
+C525 gpio_noesd[10] vdda1 0.61fF
+C526 gpio_analog[10] vdda1 0.61fF
+C527 gpio_analog[3] vdda1 0.61fF
+C528 gpio_noesd[3] vdda1 0.61fF
+C529 io_in_3v3[10] vdda1 0.61fF
+C530 io_in[10] vdda1 0.61fF
+C531 io_out[10] vdda1 0.61fF
+C532 io_oeb[10] vdda1 0.61fF
+C533 io_oeb[16] vdda1 0.61fF
+C534 io_out[16] vdda1 0.61fF
+C535 io_in[16] vdda1 0.61fF
+C536 io_in_3v3[16] vdda1 0.61fF
+C537 gpio_noesd[9] vdda1 0.61fF
+C538 gpio_analog[9] vdda1 0.61fF
+C539 gpio_analog[4] vdda1 0.61fF
+C540 gpio_noesd[4] vdda1 0.61fF
+C541 io_in_3v3[11] vdda1 0.61fF
+C542 io_in[11] vdda1 0.61fF
+C543 io_out[11] vdda1 0.61fF
+C544 io_oeb[11] vdda1 0.61fF
+C545 io_oeb[15] vdda1 0.61fF
+C546 io_out[15] vdda1 0.61fF
+C547 io_in[15] vdda1 0.61fF
+C548 io_in_3v3[15] vdda1 0.61fF
+C549 gpio_noesd[8] vdda1 0.61fF
+C550 gpio_analog[8] vdda1 0.61fF
+C551 gpio_analog[5] vdda1 0.61fF
+C552 gpio_noesd[5] vdda1 0.61fF
+C553 io_in_3v3[12] vdda1 0.61fF
+C554 io_in[12] vdda1 0.61fF
+C555 io_out[12] vdda1 0.61fF
+C556 io_oeb[12] vdda1 0.61fF
+C557 io_oeb[14] vdda1 0.61fF
+C558 io_out[14] vdda1 0.61fF
+C559 io_in[14] vdda1 0.61fF
+C560 io_in_3v3[14] vdda1 0.61fF
+C561 gpio_noesd[7] vdda1 0.61fF
+C562 gpio_analog[7] vdda1 0.61fF
+C563 vssa2 vdda1 13.04fF
+C564 gpio_analog[6] vdda1 0.61fF
+C565 gpio_noesd[6] vdda1 0.61fF
+C566 io_in_3v3[13] vdda1 0.61fF
+C567 io_in[13] vdda1 0.61fF
+C568 io_out[13] vdda1 0.61fF
+C569 io_oeb[13] vdda1 0.61fF
+C570 vccd1 vdda1 13.04fF
+C571 vccd2 vdda1 13.04fF
+C572 io_analog[10] vdda1 6.83fF
+C573 io_clamp_high[0] vdda1 3.58fF
+C574 io_clamp_low[0] vdda1 3.58fF
+C575 io_clamp_high[1] vdda1 3.58fF
+C576 io_clamp_low[1] vdda1 3.58fF
+C577 io_clamp_high[2] vdda1 3.58fF
+C578 io_clamp_low[2] vdda1 3.58fF
+C579 io_analog[7] vdda1 6.83fF
+C580 io_analog[8] vdda1 6.83fF
+C581 io_analog[9] vdda1 6.83fF
+C582 user_irq[2] vdda1 0.63fF
+C583 user_irq[1] vdda1 0.63fF
+C584 user_irq[0] vdda1 0.63fF
+C585 user_clock2 vdda1 0.63fF
+C586 la_oenb[127] vdda1 0.63fF
+C587 la_data_out[127] vdda1 0.63fF
+C588 la_data_in[127] vdda1 0.63fF
+C589 la_oenb[126] vdda1 0.63fF
+C590 la_data_out[126] vdda1 0.63fF
+C591 la_data_in[126] vdda1 0.63fF
+C592 la_oenb[125] vdda1 0.63fF
+C593 la_data_out[125] vdda1 0.63fF
+C594 la_data_in[125] vdda1 0.63fF
+C595 la_oenb[124] vdda1 0.63fF
+C596 la_data_out[124] vdda1 0.63fF
+C597 la_data_in[124] vdda1 0.63fF
+C598 la_oenb[123] vdda1 0.63fF
+C599 la_data_out[123] vdda1 0.63fF
+C600 la_data_in[123] vdda1 0.63fF
+C601 la_oenb[122] vdda1 0.63fF
+C602 la_data_out[122] vdda1 0.63fF
+C603 la_data_in[122] vdda1 0.63fF
+C604 la_oenb[121] vdda1 0.63fF
+C605 la_data_out[121] vdda1 0.63fF
+C606 la_data_in[121] vdda1 0.63fF
+C607 la_oenb[120] vdda1 0.63fF
+C608 la_data_out[120] vdda1 0.63fF
+C609 la_data_in[120] vdda1 0.63fF
+C610 la_oenb[119] vdda1 0.63fF
+C611 la_data_out[119] vdda1 0.63fF
+C612 la_data_in[119] vdda1 0.63fF
+C613 la_oenb[118] vdda1 0.63fF
+C614 la_data_out[118] vdda1 0.63fF
+C615 la_data_in[118] vdda1 0.63fF
+C616 la_oenb[117] vdda1 0.63fF
+C617 la_data_out[117] vdda1 0.63fF
+C618 la_data_in[117] vdda1 0.63fF
+C619 la_oenb[116] vdda1 0.63fF
+C620 la_data_out[116] vdda1 0.63fF
+C621 la_data_in[116] vdda1 0.63fF
+C622 la_oenb[115] vdda1 0.63fF
+C623 la_data_out[115] vdda1 0.63fF
+C624 la_data_in[115] vdda1 0.63fF
+C625 la_oenb[114] vdda1 0.63fF
+C626 la_data_out[114] vdda1 0.63fF
+C627 la_data_in[114] vdda1 0.63fF
+C628 la_oenb[113] vdda1 0.63fF
+C629 la_data_out[113] vdda1 0.63fF
+C630 la_data_in[113] vdda1 0.63fF
+C631 la_oenb[112] vdda1 0.63fF
+C632 la_data_out[112] vdda1 0.63fF
+C633 la_data_in[112] vdda1 0.63fF
+C634 la_oenb[111] vdda1 0.63fF
+C635 la_data_out[111] vdda1 0.63fF
+C636 la_data_in[111] vdda1 0.63fF
+C637 la_oenb[110] vdda1 0.63fF
+C638 la_data_out[110] vdda1 0.63fF
+C639 la_data_in[110] vdda1 0.63fF
+C640 la_oenb[109] vdda1 0.63fF
+C641 la_data_out[109] vdda1 0.63fF
+C642 la_data_in[109] vdda1 0.63fF
+C643 la_oenb[108] vdda1 0.63fF
+C644 la_data_out[108] vdda1 0.63fF
+C645 la_data_in[108] vdda1 0.63fF
+C646 la_oenb[107] vdda1 0.63fF
+C647 la_data_out[107] vdda1 0.63fF
+C648 la_data_in[107] vdda1 0.63fF
+C649 la_oenb[106] vdda1 0.63fF
+C650 la_data_out[106] vdda1 0.63fF
+C651 la_data_in[106] vdda1 0.63fF
+C652 la_oenb[105] vdda1 0.63fF
+C653 la_data_out[105] vdda1 0.63fF
+C654 la_data_in[105] vdda1 0.63fF
+C655 la_oenb[104] vdda1 0.63fF
+C656 la_data_out[104] vdda1 0.63fF
+C657 la_data_in[104] vdda1 0.63fF
+C658 la_oenb[103] vdda1 0.63fF
+C659 la_data_out[103] vdda1 0.63fF
+C660 la_data_in[103] vdda1 0.63fF
+C661 la_oenb[102] vdda1 0.63fF
+C662 la_data_out[102] vdda1 0.63fF
+C663 la_data_in[102] vdda1 0.63fF
+C664 la_oenb[101] vdda1 0.63fF
+C665 la_data_out[101] vdda1 0.63fF
+C666 la_data_in[101] vdda1 0.63fF
+C667 la_oenb[100] vdda1 0.63fF
+C668 la_data_out[100] vdda1 0.63fF
+C669 la_data_in[100] vdda1 0.63fF
+C670 la_oenb[99] vdda1 0.63fF
+C671 la_data_out[99] vdda1 0.63fF
+C672 la_data_in[99] vdda1 0.63fF
+C673 la_oenb[98] vdda1 0.63fF
+C674 la_data_out[98] vdda1 0.63fF
+C675 la_data_in[98] vdda1 0.63fF
+C676 la_oenb[97] vdda1 0.63fF
+C677 la_data_out[97] vdda1 0.63fF
+C678 la_data_in[97] vdda1 0.63fF
+C679 la_oenb[96] vdda1 0.63fF
+C680 la_data_out[96] vdda1 0.63fF
+C681 la_data_in[96] vdda1 0.63fF
+C682 la_oenb[95] vdda1 0.63fF
+C683 la_data_out[95] vdda1 0.63fF
+C684 la_data_in[95] vdda1 0.63fF
+C685 la_oenb[94] vdda1 0.63fF
+C686 la_data_out[94] vdda1 0.63fF
+C687 la_data_in[94] vdda1 0.63fF
+C688 la_oenb[93] vdda1 0.63fF
+C689 la_data_out[93] vdda1 0.63fF
+C690 la_data_in[93] vdda1 0.63fF
+C691 la_oenb[92] vdda1 0.63fF
+C692 la_data_out[92] vdda1 0.63fF
+C693 la_data_in[92] vdda1 0.63fF
+C694 la_oenb[91] vdda1 0.63fF
+C695 la_data_out[91] vdda1 0.63fF
+C696 la_data_in[91] vdda1 0.63fF
+C697 la_oenb[90] vdda1 0.63fF
+C698 la_data_out[90] vdda1 0.63fF
+C699 la_data_in[90] vdda1 0.63fF
+C700 la_oenb[89] vdda1 0.63fF
+C701 la_data_out[89] vdda1 0.63fF
+C702 la_data_in[89] vdda1 0.63fF
+C703 la_oenb[88] vdda1 0.63fF
+C704 la_data_out[88] vdda1 0.63fF
+C705 la_data_in[88] vdda1 0.63fF
+C706 la_oenb[87] vdda1 0.63fF
+C707 la_data_out[87] vdda1 0.63fF
+C708 la_data_in[87] vdda1 0.63fF
+C709 la_oenb[86] vdda1 0.63fF
+C710 la_data_out[86] vdda1 0.63fF
+C711 la_data_in[86] vdda1 0.63fF
+C712 la_oenb[85] vdda1 0.63fF
+C713 la_data_out[85] vdda1 0.63fF
+C714 la_data_in[85] vdda1 0.63fF
+C715 la_oenb[84] vdda1 0.63fF
+C716 la_data_out[84] vdda1 0.63fF
+C717 la_data_in[84] vdda1 0.63fF
+C718 la_oenb[83] vdda1 0.63fF
+C719 la_data_out[83] vdda1 0.63fF
+C720 la_data_in[83] vdda1 0.63fF
+C721 la_oenb[82] vdda1 0.63fF
+C722 la_data_out[82] vdda1 0.63fF
+C723 la_data_in[82] vdda1 0.63fF
+C724 la_oenb[81] vdda1 0.63fF
+C725 la_data_out[81] vdda1 0.63fF
+C726 la_data_in[81] vdda1 0.63fF
+C727 la_oenb[80] vdda1 0.63fF
+C728 la_data_out[80] vdda1 0.63fF
+C729 la_data_in[80] vdda1 0.63fF
+C730 la_oenb[79] vdda1 0.63fF
+C731 la_data_out[79] vdda1 0.63fF
+C732 la_data_in[79] vdda1 0.63fF
+C733 la_oenb[78] vdda1 0.63fF
+C734 la_data_out[78] vdda1 0.63fF
+C735 la_data_in[78] vdda1 0.63fF
+C736 la_oenb[77] vdda1 0.63fF
+C737 la_data_out[77] vdda1 0.63fF
+C738 la_data_in[77] vdda1 0.63fF
+C739 la_oenb[76] vdda1 0.63fF
+C740 la_data_out[76] vdda1 0.63fF
+C741 la_data_in[76] vdda1 0.63fF
+C742 la_oenb[75] vdda1 0.63fF
+C743 la_data_out[75] vdda1 0.63fF
+C744 la_data_in[75] vdda1 0.63fF
+C745 la_oenb[74] vdda1 0.63fF
+C746 la_data_out[74] vdda1 0.63fF
+C747 la_data_in[74] vdda1 0.63fF
+C748 la_oenb[73] vdda1 0.63fF
+C749 la_data_out[73] vdda1 0.63fF
+C750 la_data_in[73] vdda1 0.63fF
+C751 la_oenb[72] vdda1 0.63fF
+C752 la_data_out[72] vdda1 0.63fF
+C753 la_data_in[72] vdda1 0.63fF
+C754 la_oenb[71] vdda1 0.63fF
+C755 la_data_out[71] vdda1 0.63fF
+C756 la_data_in[71] vdda1 0.63fF
+C757 la_oenb[70] vdda1 0.63fF
+C758 la_data_out[70] vdda1 0.63fF
+C759 la_data_in[70] vdda1 0.63fF
+C760 la_oenb[69] vdda1 0.63fF
+C761 la_data_out[69] vdda1 0.63fF
+C762 la_data_in[69] vdda1 0.63fF
+C763 la_oenb[68] vdda1 0.63fF
+C764 la_data_out[68] vdda1 0.63fF
+C765 la_data_in[68] vdda1 0.63fF
+C766 la_oenb[67] vdda1 0.63fF
+C767 la_data_out[67] vdda1 0.63fF
+C768 la_data_in[67] vdda1 0.63fF
+C769 la_oenb[66] vdda1 0.63fF
+C770 la_data_out[66] vdda1 0.63fF
+C771 la_data_in[66] vdda1 0.63fF
+C772 la_oenb[65] vdda1 0.63fF
+C773 la_data_out[65] vdda1 0.63fF
+C774 la_data_in[65] vdda1 0.63fF
+C775 la_oenb[64] vdda1 0.63fF
+C776 la_data_out[64] vdda1 0.63fF
+C777 la_data_in[64] vdda1 0.63fF
+C778 la_oenb[63] vdda1 0.63fF
+C779 la_data_out[63] vdda1 0.63fF
+C780 la_data_in[63] vdda1 0.63fF
+C781 la_oenb[62] vdda1 0.63fF
+C782 la_data_out[62] vdda1 0.63fF
+C783 la_data_in[62] vdda1 0.63fF
+C784 la_oenb[61] vdda1 0.63fF
+C785 la_data_out[61] vdda1 0.63fF
+C786 la_data_in[61] vdda1 0.63fF
+C787 la_oenb[60] vdda1 0.63fF
+C788 la_data_out[60] vdda1 0.63fF
+C789 la_data_in[60] vdda1 0.63fF
+C790 la_oenb[59] vdda1 0.63fF
+C791 la_data_out[59] vdda1 0.63fF
+C792 la_data_in[59] vdda1 0.63fF
+C793 la_oenb[58] vdda1 0.63fF
+C794 la_data_out[58] vdda1 0.63fF
+C795 la_data_in[58] vdda1 0.63fF
+C796 la_oenb[57] vdda1 0.63fF
+C797 la_data_out[57] vdda1 0.63fF
+C798 la_data_in[57] vdda1 0.63fF
+C799 la_oenb[56] vdda1 0.63fF
+C800 la_data_out[56] vdda1 0.63fF
+C801 la_data_in[56] vdda1 0.63fF
+C802 la_oenb[55] vdda1 0.63fF
+C803 la_data_out[55] vdda1 0.63fF
+C804 la_data_in[55] vdda1 0.63fF
+C805 la_oenb[54] vdda1 0.63fF
+C806 la_data_out[54] vdda1 0.63fF
+C807 la_data_in[54] vdda1 0.63fF
+C808 la_oenb[53] vdda1 0.63fF
+C809 la_data_out[53] vdda1 0.63fF
+C810 la_data_in[53] vdda1 0.63fF
+C811 la_oenb[52] vdda1 0.63fF
+C812 la_data_out[52] vdda1 0.63fF
+C813 la_data_in[52] vdda1 0.63fF
+C814 la_oenb[51] vdda1 0.63fF
+C815 la_data_out[51] vdda1 0.63fF
+C816 la_data_in[51] vdda1 0.63fF
+C817 la_oenb[50] vdda1 0.63fF
+C818 la_data_out[50] vdda1 0.63fF
+C819 la_data_in[50] vdda1 0.63fF
+C820 la_oenb[49] vdda1 0.63fF
+C821 la_data_out[49] vdda1 0.63fF
+C822 la_data_in[49] vdda1 0.63fF
+C823 la_oenb[48] vdda1 0.63fF
+C824 la_data_out[48] vdda1 0.63fF
+C825 la_data_in[48] vdda1 0.63fF
+C826 la_oenb[47] vdda1 0.63fF
+C827 la_data_out[47] vdda1 0.63fF
+C828 la_data_in[47] vdda1 0.63fF
+C829 la_oenb[46] vdda1 0.63fF
+C830 la_data_out[46] vdda1 0.63fF
+C831 la_data_in[46] vdda1 0.63fF
+C832 la_oenb[45] vdda1 0.63fF
+C833 la_data_out[45] vdda1 0.63fF
+C834 la_data_in[45] vdda1 0.63fF
+C835 la_oenb[44] vdda1 0.63fF
+C836 la_data_out[44] vdda1 0.63fF
+C837 la_data_in[44] vdda1 0.63fF
+C838 la_oenb[43] vdda1 0.63fF
+C839 la_data_out[43] vdda1 0.63fF
+C840 la_data_in[43] vdda1 0.63fF
+C841 la_oenb[42] vdda1 0.63fF
+C842 la_data_out[42] vdda1 0.63fF
+C843 la_data_in[42] vdda1 0.63fF
+C844 la_oenb[41] vdda1 0.63fF
+C845 la_data_out[41] vdda1 0.63fF
+C846 la_data_in[41] vdda1 0.63fF
+C847 la_oenb[40] vdda1 0.63fF
+C848 la_data_out[40] vdda1 0.63fF
+C849 la_data_in[40] vdda1 0.63fF
+C850 la_oenb[39] vdda1 0.63fF
+C851 la_data_out[39] vdda1 0.63fF
+C852 la_data_in[39] vdda1 0.63fF
+C853 la_oenb[38] vdda1 0.63fF
+C854 la_data_out[38] vdda1 0.63fF
+C855 la_data_in[38] vdda1 0.63fF
+C856 la_oenb[37] vdda1 0.63fF
+C857 la_data_out[37] vdda1 0.63fF
+C858 la_data_in[37] vdda1 0.63fF
+C859 la_oenb[36] vdda1 0.63fF
+C860 la_data_out[36] vdda1 0.63fF
+C861 la_data_in[36] vdda1 0.63fF
+C862 la_oenb[35] vdda1 0.63fF
+C863 la_data_out[35] vdda1 0.63fF
+C864 la_data_in[35] vdda1 0.63fF
+C865 la_oenb[34] vdda1 0.63fF
+C866 la_data_out[34] vdda1 0.63fF
+C867 la_data_in[34] vdda1 0.63fF
+C868 la_oenb[33] vdda1 0.63fF
+C869 la_data_out[33] vdda1 0.63fF
+C870 la_data_in[33] vdda1 0.63fF
+C871 la_oenb[32] vdda1 0.63fF
+C872 la_data_out[32] vdda1 0.63fF
+C873 la_data_in[32] vdda1 0.63fF
+C874 la_oenb[31] vdda1 0.63fF
+C875 la_data_out[31] vdda1 0.63fF
+C876 la_data_in[31] vdda1 0.63fF
+C877 la_oenb[30] vdda1 0.63fF
+C878 la_data_out[30] vdda1 0.63fF
+C879 la_data_in[30] vdda1 0.63fF
+C880 la_oenb[29] vdda1 0.63fF
+C881 la_data_out[29] vdda1 0.63fF
+C882 la_data_in[29] vdda1 0.63fF
+C883 la_oenb[28] vdda1 0.63fF
+C884 la_data_out[28] vdda1 0.63fF
+C885 la_data_in[28] vdda1 0.63fF
+C886 la_oenb[27] vdda1 0.63fF
+C887 la_data_out[27] vdda1 0.63fF
+C888 la_data_in[27] vdda1 0.63fF
+C889 la_oenb[26] vdda1 0.63fF
+C890 la_data_out[26] vdda1 0.63fF
+C891 la_data_in[26] vdda1 0.63fF
+C892 la_oenb[25] vdda1 0.63fF
+C893 la_data_out[25] vdda1 0.63fF
+C894 la_data_in[25] vdda1 0.63fF
+C895 la_oenb[24] vdda1 0.63fF
+C896 la_data_out[24] vdda1 0.63fF
+C897 la_data_in[24] vdda1 0.63fF
+C898 la_oenb[23] vdda1 0.63fF
+C899 la_data_out[23] vdda1 0.63fF
+C900 la_data_in[23] vdda1 0.63fF
+C901 la_oenb[22] vdda1 0.63fF
+C902 la_data_out[22] vdda1 0.63fF
+C903 la_data_in[22] vdda1 0.63fF
+C904 la_oenb[21] vdda1 0.63fF
+C905 la_data_out[21] vdda1 0.63fF
+C906 la_data_in[21] vdda1 0.63fF
+C907 la_oenb[20] vdda1 0.63fF
+C908 la_data_out[20] vdda1 0.63fF
+C909 la_data_in[20] vdda1 0.63fF
+C910 la_oenb[19] vdda1 0.63fF
+C911 la_data_out[19] vdda1 0.63fF
+C912 la_data_in[19] vdda1 0.63fF
+C913 la_oenb[18] vdda1 0.63fF
+C914 la_data_out[18] vdda1 0.63fF
+C915 la_data_in[18] vdda1 0.63fF
+C916 la_oenb[17] vdda1 0.63fF
+C917 la_data_out[17] vdda1 0.63fF
+C918 la_data_in[17] vdda1 0.63fF
+C919 la_oenb[16] vdda1 0.63fF
+C920 la_data_out[16] vdda1 0.63fF
+C921 la_data_in[16] vdda1 0.63fF
+C922 la_oenb[15] vdda1 0.63fF
+C923 la_data_out[15] vdda1 0.63fF
+C924 la_data_in[15] vdda1 0.63fF
+C925 la_oenb[14] vdda1 0.63fF
+C926 la_data_out[14] vdda1 0.63fF
+C927 la_data_in[14] vdda1 0.63fF
+C928 la_oenb[13] vdda1 0.63fF
+C929 la_data_out[13] vdda1 0.63fF
+C930 la_data_in[13] vdda1 0.63fF
+C931 la_oenb[12] vdda1 0.63fF
+C932 la_data_out[12] vdda1 0.63fF
+C933 la_data_in[12] vdda1 0.63fF
+C934 la_oenb[11] vdda1 0.63fF
+C935 la_data_out[11] vdda1 0.63fF
+C936 la_data_in[11] vdda1 0.63fF
+C937 la_oenb[10] vdda1 0.63fF
+C938 la_data_out[10] vdda1 0.63fF
+C939 la_data_in[10] vdda1 0.63fF
+C940 la_oenb[9] vdda1 0.63fF
+C941 la_data_out[9] vdda1 0.63fF
+C942 la_data_in[9] vdda1 0.63fF
+C943 la_oenb[8] vdda1 0.63fF
+C944 la_data_out[8] vdda1 0.63fF
+C945 la_data_in[8] vdda1 0.63fF
+C946 la_oenb[7] vdda1 0.63fF
+C947 la_data_out[7] vdda1 0.63fF
+C948 la_data_in[7] vdda1 0.63fF
+C949 la_oenb[6] vdda1 0.63fF
+C950 la_data_out[6] vdda1 0.63fF
+C951 la_data_in[6] vdda1 0.63fF
+C952 la_oenb[5] vdda1 0.63fF
+C953 la_data_out[5] vdda1 0.63fF
+C954 la_data_in[5] vdda1 0.63fF
+C955 la_oenb[4] vdda1 0.63fF
+C956 la_data_out[4] vdda1 0.63fF
+C957 la_data_in[4] vdda1 0.63fF
+C958 la_oenb[3] vdda1 0.63fF
+C959 la_data_out[3] vdda1 0.63fF
+C960 la_data_in[3] vdda1 0.63fF
+C961 la_oenb[2] vdda1 0.63fF
+C962 la_data_out[2] vdda1 0.63fF
+C963 la_data_in[2] vdda1 0.63fF
+C964 la_oenb[1] vdda1 0.63fF
+C965 la_data_out[1] vdda1 0.63fF
+C966 la_data_in[1] vdda1 0.63fF
+C967 la_oenb[0] vdda1 0.63fF
+C968 la_data_out[0] vdda1 0.63fF
+C969 la_data_in[0] vdda1 0.63fF
+C970 wbs_dat_o[31] vdda1 0.63fF
+C971 wbs_dat_i[31] vdda1 0.63fF
+C972 wbs_adr_i[31] vdda1 0.63fF
+C973 wbs_dat_o[30] vdda1 0.63fF
+C974 wbs_dat_i[30] vdda1 0.63fF
+C975 wbs_adr_i[30] vdda1 0.63fF
+C976 wbs_dat_o[29] vdda1 0.63fF
+C977 wbs_dat_i[29] vdda1 0.63fF
+C978 wbs_adr_i[29] vdda1 0.63fF
+C979 wbs_dat_o[28] vdda1 0.63fF
+C980 wbs_dat_i[28] vdda1 0.63fF
+C981 wbs_adr_i[28] vdda1 0.63fF
+C982 wbs_dat_o[27] vdda1 0.63fF
+C983 wbs_dat_i[27] vdda1 0.63fF
+C984 wbs_adr_i[27] vdda1 0.63fF
+C985 wbs_dat_o[26] vdda1 0.63fF
+C986 wbs_dat_i[26] vdda1 0.63fF
+C987 wbs_adr_i[26] vdda1 0.63fF
+C988 wbs_dat_o[25] vdda1 0.63fF
+C989 wbs_dat_i[25] vdda1 0.63fF
+C990 wbs_adr_i[25] vdda1 0.63fF
+C991 wbs_dat_o[24] vdda1 0.63fF
+C992 wbs_dat_i[24] vdda1 0.63fF
+C993 wbs_adr_i[24] vdda1 0.63fF
+C994 wbs_dat_o[23] vdda1 0.63fF
+C995 wbs_dat_i[23] vdda1 0.63fF
+C996 wbs_adr_i[23] vdda1 0.63fF
+C997 wbs_dat_o[22] vdda1 0.63fF
+C998 wbs_dat_i[22] vdda1 0.63fF
+C999 wbs_adr_i[22] vdda1 0.63fF
+C1000 wbs_dat_o[21] vdda1 0.63fF
+C1001 wbs_dat_i[21] vdda1 0.63fF
+C1002 wbs_adr_i[21] vdda1 0.63fF
+C1003 wbs_dat_o[20] vdda1 0.63fF
+C1004 wbs_dat_i[20] vdda1 0.63fF
+C1005 wbs_adr_i[20] vdda1 0.63fF
+C1006 wbs_dat_o[19] vdda1 0.63fF
+C1007 wbs_dat_i[19] vdda1 0.63fF
+C1008 wbs_adr_i[19] vdda1 0.63fF
+C1009 wbs_dat_o[18] vdda1 0.63fF
+C1010 wbs_dat_i[18] vdda1 0.63fF
+C1011 wbs_adr_i[18] vdda1 0.63fF
+C1012 wbs_dat_o[17] vdda1 0.63fF
+C1013 wbs_dat_i[17] vdda1 0.63fF
+C1014 wbs_adr_i[17] vdda1 0.63fF
+C1015 wbs_dat_o[16] vdda1 0.63fF
+C1016 wbs_dat_i[16] vdda1 0.63fF
+C1017 wbs_adr_i[16] vdda1 0.63fF
+C1018 wbs_dat_o[15] vdda1 0.63fF
+C1019 wbs_dat_i[15] vdda1 0.63fF
+C1020 wbs_adr_i[15] vdda1 0.63fF
+C1021 wbs_dat_o[14] vdda1 0.63fF
+C1022 wbs_dat_i[14] vdda1 0.63fF
+C1023 wbs_adr_i[14] vdda1 0.63fF
+C1024 wbs_dat_o[13] vdda1 0.63fF
+C1025 wbs_dat_i[13] vdda1 0.63fF
+C1026 wbs_adr_i[13] vdda1 0.63fF
+C1027 wbs_dat_o[12] vdda1 0.63fF
+C1028 wbs_dat_i[12] vdda1 0.63fF
+C1029 wbs_adr_i[12] vdda1 0.63fF
+C1030 wbs_dat_o[11] vdda1 0.63fF
+C1031 wbs_dat_i[11] vdda1 0.63fF
+C1032 wbs_adr_i[11] vdda1 0.63fF
+C1033 wbs_dat_o[10] vdda1 0.63fF
+C1034 wbs_dat_i[10] vdda1 0.63fF
+C1035 wbs_adr_i[10] vdda1 0.63fF
+C1036 wbs_dat_o[9] vdda1 0.63fF
+C1037 wbs_dat_i[9] vdda1 0.63fF
+C1038 wbs_adr_i[9] vdda1 0.63fF
+C1039 wbs_dat_o[8] vdda1 0.63fF
+C1040 wbs_dat_i[8] vdda1 0.63fF
+C1041 wbs_adr_i[8] vdda1 0.63fF
+C1042 wbs_dat_o[7] vdda1 0.63fF
+C1043 wbs_dat_i[7] vdda1 0.63fF
+C1044 wbs_adr_i[7] vdda1 0.63fF
+C1045 wbs_dat_o[6] vdda1 0.63fF
+C1046 wbs_dat_i[6] vdda1 0.63fF
+C1047 wbs_adr_i[6] vdda1 0.63fF
+C1048 wbs_dat_o[5] vdda1 0.63fF
+C1049 wbs_dat_i[5] vdda1 0.63fF
+C1050 wbs_adr_i[5] vdda1 0.63fF
+C1051 wbs_dat_o[4] vdda1 0.63fF
+C1052 wbs_dat_i[4] vdda1 0.63fF
+C1053 wbs_adr_i[4] vdda1 0.63fF
+C1054 wbs_sel_i[3] vdda1 0.63fF
+C1055 wbs_dat_o[3] vdda1 0.63fF
+C1056 wbs_dat_i[3] vdda1 0.63fF
+C1057 wbs_adr_i[3] vdda1 0.63fF
+C1058 wbs_sel_i[2] vdda1 0.63fF
+C1059 wbs_dat_o[2] vdda1 0.63fF
+C1060 wbs_dat_i[2] vdda1 0.63fF
+C1061 wbs_adr_i[2] vdda1 0.63fF
+C1062 wbs_sel_i[1] vdda1 0.63fF
+C1063 wbs_dat_o[1] vdda1 0.63fF
+C1064 wbs_dat_i[1] vdda1 0.63fF
+C1065 wbs_adr_i[1] vdda1 0.63fF
+C1066 wbs_sel_i[0] vdda1 0.63fF
+C1067 wbs_dat_o[0] vdda1 0.63fF
+C1068 wbs_dat_i[0] vdda1 0.63fF
+C1069 wbs_adr_i[0] vdda1 0.63fF
+C1070 wbs_we_i vdda1 0.63fF
+C1071 wbs_stb_i vdda1 0.63fF
+C1072 wbs_cyc_i vdda1 0.63fF
+C1073 wbs_ack_o vdda1 0.63fF
+C1074 wb_rst_i vdda1 0.63fF
+C1075 wb_clk_i vdda1 0.63fF
+C1076 divider_0/and_0/Z1 vdda1 0.33fF
+C1077 divider_0/and_0/B vdda1 1.79fF
+C1078 divider_0/and_0/A vdda1 1.66fF
+C1079 divider_0/and_0/out1 vdda1 2.71fF
+C1080 divider_0/tspc_2/Z4 vdda1 0.42fF
+C1081 divider_0/Out vdda1 1.31fF
+C1082 divider_0/tspc_2/Z3 vdda1 2.00fF
+C1083 divider_0/tspc_2/Z2 vdda1 1.29fF
+C1084 divider_0/tspc_2/Z1 vdda1 0.99fF
+C1085 divider_0/nor_0/B vdda1 5.25fF
+C1086 divider_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING
+C1087 divider_0/tspc_1/Z4 vdda1 0.42fF
+C1088 divider_0/tspc_1/Q vdda1 2.79fF
+C1089 divider_0/tspc_1/Z3 vdda1 2.00fF
+C1090 divider_0/tspc_1/Z2 vdda1 1.29fF
+C1091 divider_0/tspc_1/Z1 vdda1 0.99fF
+C1092 divider_0/nor_1/B vdda1 5.95fF
+C1093 divider_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING
+C1094 divider_0/tspc_0/Z4 vdda1 0.42fF
+C1095 divider_0/tspc_0/Q vdda1 2.81fF
+C1096 divider_0/tspc_0/Z3 vdda1 2.00fF
+C1097 divider_0/tspc_0/Z2 vdda1 1.30fF
+C1098 divider_0/tspc_0/Z1 vdda1 0.99fF
+C1099 divider_0/nor_1/A vdda1 6.02fF
+C1100 divider_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING
+C1101 divider_0/clk vdda1 5.56fF
+C1102 divider_0/prescaler_0/Out vdda1 4.13fF
+C1103 divider_0/prescaler_0/nand_1/z1 vdda1 0.20fF
+C1104 gnd vdda1 21.94fF
+C1105 divider_0/prescaler_0/tspc_2/D vdda1 2.59fF
+C1106 divider_0/prescaler_0/tspc_0/Q vdda1 3.30fF
+C1107 divider_0/prescaler_0/tspc_1/Q vdda1 2.78fF
+C1108 divider_0/prescaler_0/nand_0/z1 vdda1 0.20fF
+C1109 divider_0/prescaler_0/tspc_0/D vdda1 3.07fF
+C1110 divider_0/and_0/OUT vdda1 5.35fF
+C1111 divider_0/prescaler_0/tspc_2/Z4 vdda1 0.42fF
+C1112 divider_0/prescaler_0/tspc_2/Z3 vdda1 2.00fF
+C1113 divider_0/prescaler_0/tspc_2/Z2 vdda1 1.30fF
+C1114 divider_0/prescaler_0/tspc_2/Z1 vdda1 0.99fF
+C1115 divider_0/prescaler_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING
+C1116 divider_0/prescaler_0/tspc_2/a_740_n680# vdda1 1.89fF **FLOATING
+C1117 divider_0/prescaler_0/tspc_1/Z4 vdda1 0.42fF
+C1118 divider_0/prescaler_0/tspc_1/Z3 vdda1 2.00fF
+C1119 divider_0/prescaler_0/tspc_1/Z2 vdda1 1.31fF
+C1120 divider_0/prescaler_0/tspc_1/Z1 vdda1 0.99fF
+C1121 divider_0/prescaler_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING
+C1122 divider_0/prescaler_0/m1_2700_2190# vdda1 3.99fF **FLOATING
+C1123 divider_0/prescaler_0/tspc_0/Z4 vdda1 0.42fF
+C1124 divider_0/prescaler_0/tspc_0/Z3 vdda1 2.00fF
+C1125 divider_0/prescaler_0/tspc_0/Z2 vdda1 1.30fF
+C1126 divider_0/prescaler_0/tspc_0/Z1 vdda1 0.99fF
+C1127 divider_0/prescaler_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING
+C1128 divider_0/prescaler_0/tspc_0/a_740_n680# vdda1 1.89fF **FLOATING
+C1129 divider_0/nor_1/Z1 vdda1 1.33fF
+C1130 divider_0/nor_0/Z1 vdda1 1.33fF
+C1131 divider_0/mc2 vdda1 3.93fF
+C1132 ro_complete_0/cbank_2/v vdda1 17.84fF
+C1133 ro_complete_0/cbank_2/switch_5/vin vdda1 0.78fF
+C1134 ro_complete_0/cbank_2/switch_4/vin vdda1 1.50fF
+C1135 ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF
+C1136 ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF
+C1137 ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF
+C1138 ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF
+C1139 ro_complete_0/cbank_1/v vdda1 16.11fF
+C1140 ro_complete_0/cbank_1/switch_5/vin vdda1 0.78fF
+C1141 ro_complete_0/a0 vdda1 7.88fF
+C1142 ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF
+C1143 ro_complete_0/a1 vdda1 5.39fF
+C1144 ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF
+C1145 ro_complete_0/a3 vdda1 6.85fF
+C1146 ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF
+C1147 ro_complete_0/a2 vdda1 5.48fF
+C1148 ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF
+C1149 ro_complete_0/a4 vdda1 5.36fF
+C1150 ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF
+C1151 ro_complete_0/a5 vdda1 5.19fF
+C1152 ro_complete_0/cbank_0/v vdda1 14.98fF
+C1153 ro_complete_0/cbank_0/switch_5/vin vdda1 0.78fF
+C1154 ro_complete_0/cbank_0/switch_4/vin vdda1 1.50fF
+C1155 ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF
+C1156 ro_complete_0/cbank_0/switch_3/vin vdda1 0.56fF
+C1157 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF
+C1158 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF
+C1159 ro_complete_0/ro_var_extend_0/vcont vdda1 0.57fF
+C1160 filter_0/v vdda1 85.69fF
+C1161 filter_0/a_4216_n5230# vdda1 418.47fF **FLOATING
+C1162 filter_0/a_4216_n2998# vdda1 1.03fF **FLOATING
+C1163 io_analog[1] vdda1 108.63fF
+C1164 io_analog[3] vdda1 197.37fF
+C1165 io_analog[0] vdda1 74.25fF
+C1166 io_analog[2] vdda1 108.15fF
+C1167 cp_1/a_7110_n2840# vdda1 0.17fF **FLOATING
+C1168 cp_1/a_3060_n2840# vdda1 1.71fF **FLOATING
+C1169 cp_1/a_7110_0# vdda1 0.17fF **FLOATING
+C1170 cp_1/a_6370_0# vdda1 0.40fF **FLOATING
+C1171 cp_1/a_3060_0# vdda1 4.15fF **FLOATING
+C1172 cp_1/a_1710_0# vdda1 6.63fF **FLOATING
+C1173 cp_1/a_10_n50# vdda1 2.96fF **FLOATING
+C1174 cp_0/down vdda1 1.54fF
+C1175 cp_0/vbias vdda1 2.41fF
+C1176 cp_0/out vdda1 5.26fF
+C1177 cp_0/upbar vdda1 1.50fF
+C1178 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING
+C1179 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING
+C1180 cp_0/a_7110_0# vdda1 0.17fF **FLOATING
+C1181 cp_0/a_6370_0# vdda1 0.40fF **FLOATING
+C1182 cp_0/a_3060_0# vdda1 1.65fF **FLOATING
+C1183 cp_0/a_1710_0# vdda1 5.76fF **FLOATING
+C1184 cp_0/a_1710_n2840# vdda1 4.89fF **FLOATING
+C1185 cp_0/a_10_n50# vdda1 2.96fF **FLOATING
+C1186 pd_0/and_pd_0/Z1 vdda1 0.39fF
+C1187 pd_0/and_pd_0/Out1 vdda1 2.22fF
+C1188 pd_0/tspc_r_1/z5 vdda1 1.10fF
+C1189 pd_0/tspc_r_1/Z4 vdda1 1.07fF
+C1190 pd_0/tspc_r_1/Qbar vdda1 0.88fF
+C1191 pd_0/tspc_r_1/Z2 vdda1 1.22fF
+C1192 pd_0/tspc_r_1/Z1 vdda1 0.67fF
+C1193 pd_0/UP vdda1 2.21fF
+C1194 pd_0/tspc_r_1/Qbar1 vdda1 1.34fF
+C1195 pd_0/tspc_r_1/Z3 vdda1 2.12fF
+C1196 pd_0/REF vdda1 1.80fF
+C1197 pd_0/tspc_r_0/z5 vdda1 1.10fF
+C1198 pd_0/tspc_r_0/Z4 vdda1 1.07fF
+C1199 pd_0/R vdda1 3.05fF
+C1200 pd_0/tspc_r_0/Qbar vdda1 0.79fF
+C1201 pd_0/tspc_r_0/Z2 vdda1 1.22fF
+C1202 pd_0/tspc_r_0/Z1 vdda1 0.67fF
+C1203 pd_0/DOWN vdda1 3.08fF
+C1204 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF
+C1205 pd_0/tspc_r_0/Z3 vdda1 2.12fF
+C1206 pd_0/DIV vdda1 1.82fF
 .ends