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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-004
/
slot-010
/
94e07c3d1bf6644b48bd07439c4fe73157a6c701
/
.
/
verilog
/
rtl
/
ibex_core
/
prim_clock_gating.v
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module
prim_clock_gating
(
clk_i
,
en_i
,
test_en_i
,
clk_o
);
input wire clk_i
;
input wire en_i
;
input wire test_en_i
;
output wire clk_o
;
reg clk_en
;
always
@(*)
if
(
clk_i
==
1
'b0)
clk_en <= en_i | test_en_i;
assign clk_o = clk_i & clk_en;
endmodule