tree: 226faee97d7a191c159291d93902ac5f864116c5 [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. info.yaml
  14. LICENSE
  15. Makefile
  16. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

ICESOC is a Heterogeneous Multicore SoC, integrating a customised embedded FPGA fabric and two RISC-V cores dedecating for Cryptographical applications.