| module ibex_top ( |
| clk_i, |
| rst_ni, |
| test_en_i, |
| ram_cfg_i, |
| hart_id_i, |
| boot_addr_i, |
| instr_req_o, |
| instr_gnt_i, |
| instr_rvalid_i, |
| instr_addr_o, |
| instr_rdata_i, |
| instr_rdata_intg_i, |
| instr_err_i, |
| data_req_o, |
| data_gnt_i, |
| data_rvalid_i, |
| data_we_o, |
| data_be_o, |
| data_addr_o, |
| data_wdata_o, |
| data_wdata_intg_o, |
| data_rdata_i, |
| data_rdata_intg_i, |
| data_err_i, |
| eFPGA_operand_a_o, |
| eFPGA_operand_b_o, |
| eFPGA_result_a_i, |
| eFPGA_result_b_i, |
| eFPGA_result_c_i, |
| eFPGA_write_strobe_o, |
| eFPGA_fpga_done_i, |
| eFPGA_en_o, |
| eFPGA_operator_o, |
| eFPGA_delay_o, |
| irq_software_i, |
| irq_timer_i, |
| irq_external_i, |
| irq_fast_i, |
| irq_nm_i, |
| debug_req_i, |
| crash_dump_o, |
| fetch_enable_i, |
| alert_minor_o, |
| alert_major_o, |
| core_sleep_o, |
| scan_rst_ni |
| ); |
| parameter [0:0] PMPEnable = 1'b0; |
| parameter [31:0] PMPGranularity = 0; |
| parameter [31:0] PMPNumRegions = 4; |
| parameter [31:0] MHPMCounterNum = 0; |
| parameter [31:0] MHPMCounterWidth = 40; |
| parameter [0:0] RV32E = 1'b0; |
| parameter integer RV32M = 32'sd2; |
| parameter integer RV32B = 32'sd0; |
| parameter integer RV32Zk = 32'sd2; |
| parameter integer RegFile = 32'sd0; |
| parameter [0:0] BranchTargetALU = 1'b0; |
| parameter [0:0] WritebackStage = 1'b0; |
| parameter [0:0] ICache = 1'b0; |
| parameter [0:0] ICacheECC = 1'b0; |
| parameter [0:0] BranchPredictor = 1'b0; |
| parameter [0:0] DbgTriggerEn = 1'b0; |
| parameter [31:0] DbgHwBreakNum = 1; |
| parameter [0:0] SecureIbex = 1'b0; |
| localparam signed [31:0] ibex_pkg_LfsrWidth = 32; |
| localparam [31:0] ibex_pkg_RndCnstLfsrSeedDefault = 32'hac533bf4; |
| parameter [31:0] RndCnstLfsrSeed = ibex_pkg_RndCnstLfsrSeedDefault; |
| localparam [159:0] ibex_pkg_RndCnstLfsrPermDefault = 160'h1e35ecba467fd1b12e958152c04fa43878a8daed; |
| parameter [159:0] RndCnstLfsrPerm = ibex_pkg_RndCnstLfsrPermDefault; |
| parameter [31:0] DmHaltAddr = 32'h1a110800; |
| parameter [31:0] DmExceptionAddr = 32'h1a110808; |
| input wire clk_i; |
| input wire rst_ni; |
| input wire test_en_i; |
| input wire ram_cfg_i; |
| input wire [31:0] hart_id_i; |
| input wire [31:0] boot_addr_i; |
| output wire instr_req_o; |
| input wire instr_gnt_i; |
| input wire instr_rvalid_i; |
| output wire [31:0] instr_addr_o; |
| input wire [31:0] instr_rdata_i; |
| input wire [6:0] instr_rdata_intg_i; |
| input wire instr_err_i; |
| output wire data_req_o; |
| input wire data_gnt_i; |
| input wire data_rvalid_i; |
| output wire data_we_o; |
| output wire [3:0] data_be_o; |
| output wire [31:0] data_addr_o; |
| output wire [31:0] data_wdata_o; |
| output wire [6:0] data_wdata_intg_o; |
| input wire [31:0] data_rdata_i; |
| input wire [6:0] data_rdata_intg_i; |
| input wire data_err_i; |
| output wire [31:0] eFPGA_operand_a_o; |
| output wire [31:0] eFPGA_operand_b_o; |
| input wire [31:0] eFPGA_result_a_i; |
| input wire [31:0] eFPGA_result_b_i; |
| input wire [31:0] eFPGA_result_c_i; |
| output wire eFPGA_write_strobe_o; |
| input wire eFPGA_fpga_done_i; |
| output wire eFPGA_en_o; |
| output wire [1:0] eFPGA_operator_o; |
| output wire [3:0] eFPGA_delay_o; |
| input wire irq_software_i; |
| input wire irq_timer_i; |
| input wire irq_external_i; |
| input wire [14:0] irq_fast_i; |
| input wire irq_nm_i; |
| input wire debug_req_i; |
| output wire [127:0] crash_dump_o; |
| input wire fetch_enable_i; |
| output wire alert_minor_o; |
| output wire alert_major_o; |
| output wire core_sleep_o; |
| input wire scan_rst_ni; |
| localparam [0:0] Lockstep = SecureIbex; |
| localparam [0:0] ResetAll = Lockstep; |
| localparam [0:0] DummyInstructions = SecureIbex; |
| localparam [0:0] RegFileECC = SecureIbex; |
| localparam [31:0] RegFileDataWidth = (RegFileECC ? 39 : 32); |
| localparam [31:0] ibex_pkg_BUS_SIZE = 32; |
| localparam [31:0] BusSizeECC = (ICacheECC ? 39 : ibex_pkg_BUS_SIZE); |
| localparam [31:0] ibex_pkg_BUS_BYTES = 4; |
| localparam [31:0] ibex_pkg_IC_LINE_SIZE = 64; |
| localparam [31:0] ibex_pkg_IC_LINE_BYTES = 8; |
| localparam [31:0] ibex_pkg_IC_LINE_BEATS = ibex_pkg_IC_LINE_BYTES / ibex_pkg_BUS_BYTES; |
| localparam [31:0] LineSizeECC = BusSizeECC * ibex_pkg_IC_LINE_BEATS; |
| localparam [31:0] ibex_pkg_ADDR_W = 32; |
| localparam [31:0] ibex_pkg_IC_NUM_WAYS = 2; |
| localparam [31:0] ibex_pkg_IC_SIZE_BYTES = 4096; |
| localparam [31:0] ibex_pkg_IC_NUM_LINES = (ibex_pkg_IC_SIZE_BYTES / ibex_pkg_IC_NUM_WAYS) / ibex_pkg_IC_LINE_BYTES; |
| localparam [31:0] ibex_pkg_IC_INDEX_W = $clog2(ibex_pkg_IC_NUM_LINES); |
| localparam [31:0] ibex_pkg_IC_LINE_W = 3; |
| localparam [31:0] ibex_pkg_IC_TAG_SIZE = ((ibex_pkg_ADDR_W - ibex_pkg_IC_INDEX_W) - ibex_pkg_IC_LINE_W) + 1; |
| localparam [31:0] TagSizeECC = (ICacheECC ? ibex_pkg_IC_TAG_SIZE + 6 : ibex_pkg_IC_TAG_SIZE); |
| wire clk; |
| wire core_busy_d; |
| reg core_busy_q; |
| wire clock_en; |
| wire irq_pending; |
| wire dummy_instr_id; |
| wire [4:0] rf_raddr_a; |
| wire [4:0] rf_raddr_b; |
| wire [4:0] rf_waddr_wb; |
| wire rf_we_wb; |
| wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc; |
| wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc; |
| wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc; |
| wire [1:0] ic_tag_req; |
| wire ic_tag_write; |
| wire [ibex_pkg_IC_INDEX_W - 1:0] ic_tag_addr; |
| wire [TagSizeECC - 1:0] ic_tag_wdata; |
| wire [(ibex_pkg_IC_NUM_WAYS * TagSizeECC) - 1:0] ic_tag_rdata; |
| wire [1:0] ic_data_req; |
| wire ic_data_write; |
| wire [ibex_pkg_IC_INDEX_W - 1:0] ic_data_addr; |
| wire [LineSizeECC - 1:0] ic_data_wdata; |
| wire [(ibex_pkg_IC_NUM_WAYS * LineSizeECC) - 1:0] ic_data_rdata; |
| wire core_alert_major; |
| wire core_alert_minor; |
| wire lockstep_alert_major; |
| wire lockstep_alert_minor; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| core_busy_q <= 1'b0; |
| else |
| core_busy_q <= core_busy_d; |
| assign clock_en = ((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i; |
| assign core_sleep_o = ~clock_en; |
| prim_clock_gating core_clock_gate_i( |
| .clk_i(clk_i), |
| .en_i(clock_en), |
| .test_en_i(test_en_i), |
| .clk_o(clk) |
| ); |
| ibex_core #( |
| .PMPEnable(PMPEnable), |
| .PMPGranularity(PMPGranularity), |
| .PMPNumRegions(PMPNumRegions), |
| .MHPMCounterNum(MHPMCounterNum), |
| .MHPMCounterWidth(MHPMCounterWidth), |
| .RV32E(RV32E), |
| .RV32M(RV32M), |
| .RV32B(RV32B), |
| .RV32Zk(RV32Zk), |
| .BranchTargetALU(BranchTargetALU), |
| .ICache(ICache), |
| .ICacheECC(ICacheECC), |
| .BusSizeECC(BusSizeECC), |
| .TagSizeECC(TagSizeECC), |
| .LineSizeECC(LineSizeECC), |
| .BranchPredictor(BranchPredictor), |
| .DbgTriggerEn(DbgTriggerEn), |
| .DbgHwBreakNum(DbgHwBreakNum), |
| .WritebackStage(WritebackStage), |
| .ResetAll(ResetAll), |
| .RndCnstLfsrSeed(RndCnstLfsrSeed), |
| .RndCnstLfsrPerm(RndCnstLfsrPerm), |
| .SecureIbex(SecureIbex), |
| .DummyInstructions(DummyInstructions), |
| .RegFileECC(RegFileECC), |
| .RegFileDataWidth(RegFileDataWidth), |
| .DmHaltAddr(DmHaltAddr), |
| .DmExceptionAddr(DmExceptionAddr) |
| ) u_ibex_core( |
| .clk_i(clk), |
| .rst_ni(rst_ni), |
| .hart_id_i(hart_id_i), |
| .boot_addr_i(boot_addr_i), |
| .instr_req_o(instr_req_o), |
| .instr_gnt_i(instr_gnt_i), |
| .instr_rvalid_i(instr_rvalid_i), |
| .instr_addr_o(instr_addr_o), |
| .instr_rdata_i(instr_rdata_i), |
| .instr_err_i(instr_err_i), |
| .data_req_o(data_req_o), |
| .data_gnt_i(data_gnt_i), |
| .data_rvalid_i(data_rvalid_i), |
| .data_we_o(data_we_o), |
| .data_be_o(data_be_o), |
| .data_addr_o(data_addr_o), |
| .data_wdata_o(data_wdata_o), |
| .data_rdata_i(data_rdata_i), |
| .data_err_i(data_err_i), |
| .eFPGA_operand_a_o(eFPGA_operand_a_o), |
| .eFPGA_operand_b_o(eFPGA_operand_b_o), |
| .eFPGA_result_a_i(eFPGA_result_a_i), |
| .eFPGA_result_b_i(eFPGA_result_b_i), |
| .eFPGA_result_c_i(eFPGA_result_c_i), |
| .eFPGA_write_strobe_o(eFPGA_write_strobe_o), |
| .eFPGA_fpga_done_i(eFPGA_fpga_done_i), |
| .eFPGA_en_o(eFPGA_en_o), |
| .eFPGA_operator_o(eFPGA_operator_o), |
| .eFPGA_delay_o(eFPGA_delay_o), |
| .dummy_instr_id_o(dummy_instr_id), |
| .rf_raddr_a_o(rf_raddr_a), |
| .rf_raddr_b_o(rf_raddr_b), |
| .rf_waddr_wb_o(rf_waddr_wb), |
| .rf_we_wb_o(rf_we_wb), |
| .rf_wdata_wb_ecc_o(rf_wdata_wb_ecc), |
| .rf_rdata_a_ecc_i(rf_rdata_a_ecc), |
| .rf_rdata_b_ecc_i(rf_rdata_b_ecc), |
| .ic_tag_req_o(ic_tag_req), |
| .ic_tag_write_o(ic_tag_write), |
| .ic_tag_addr_o(ic_tag_addr), |
| .ic_tag_wdata_o(ic_tag_wdata), |
| .ic_tag_rdata_i(ic_tag_rdata), |
| .ic_data_req_o(ic_data_req), |
| .ic_data_write_o(ic_data_write), |
| .ic_data_addr_o(ic_data_addr), |
| .ic_data_wdata_o(ic_data_wdata), |
| .ic_data_rdata_i(ic_data_rdata), |
| .irq_software_i(irq_software_i), |
| .irq_timer_i(irq_timer_i), |
| .irq_external_i(irq_external_i), |
| .irq_fast_i(irq_fast_i), |
| .irq_nm_i(irq_nm_i), |
| .irq_pending_o(irq_pending), |
| .debug_req_i(debug_req_i), |
| .crash_dump_o(crash_dump_o), |
| .fetch_enable_i(fetch_enable_i), |
| .alert_minor_o(core_alert_minor), |
| .alert_major_o(core_alert_major), |
| .core_busy_o(core_busy_d) |
| ); |
| generate |
| if (RegFile == 32'sd0) begin : gen_regfile_ff |
| ibex_register_file_ff #( |
| .RV32E(RV32E), |
| .DataWidth(RegFileDataWidth), |
| .DummyInstructions(DummyInstructions) |
| ) register_file_i( |
| .clk_i(clk), |
| .rst_ni(rst_ni), |
| .test_en_i(test_en_i), |
| .dummy_instr_id_i(dummy_instr_id), |
| .raddr_a_i(rf_raddr_a), |
| .rdata_a_o(rf_rdata_a_ecc), |
| .raddr_b_i(rf_raddr_b), |
| .rdata_b_o(rf_rdata_b_ecc), |
| .waddr_a_i(rf_waddr_wb), |
| .wdata_a_i(rf_wdata_wb_ecc), |
| .we_a_i(rf_we_wb) |
| ); |
| end |
| else if (RegFile == 32'sd1) begin : gen_regfile_fpga |
| ibex_register_file_fpga #( |
| .RV32E(RV32E), |
| .DataWidth(RegFileDataWidth), |
| .DummyInstructions(DummyInstructions) |
| ) register_file_i( |
| .clk_i(clk), |
| .rst_ni(rst_ni), |
| .test_en_i(test_en_i), |
| .dummy_instr_id_i(dummy_instr_id), |
| .raddr_a_i(rf_raddr_a), |
| .rdata_a_o(rf_rdata_a_ecc), |
| .raddr_b_i(rf_raddr_b), |
| .rdata_b_o(rf_rdata_b_ecc), |
| .waddr_a_i(rf_waddr_wb), |
| .wdata_a_i(rf_wdata_wb_ecc), |
| .we_a_i(rf_we_wb) |
| ); |
| end |
| else if (RegFile == 32'sd2) begin : gen_regfile_latch |
| ibex_register_file_latch #( |
| .RV32E(RV32E), |
| .DataWidth(RegFileDataWidth), |
| .DummyInstructions(DummyInstructions) |
| ) register_file_i( |
| .clk_i(clk), |
| .rst_ni(rst_ni), |
| .test_en_i(test_en_i), |
| .dummy_instr_id_i(dummy_instr_id), |
| .raddr_a_i(rf_raddr_a), |
| .rdata_a_o(rf_rdata_a_ecc), |
| .raddr_b_i(rf_raddr_b), |
| .rdata_b_o(rf_rdata_b_ecc), |
| .waddr_a_i(rf_waddr_wb), |
| .wdata_a_i(rf_wdata_wb_ecc), |
| .we_a_i(rf_we_wb) |
| ); |
| end |
| endgenerate |
| wire unused_ram_cfg; |
| wire unused_ram_inputs; |
| assign unused_ram_cfg = ram_cfg_i; |
| assign unused_ram_inputs = ((((((|ic_tag_req & ic_tag_write) & |ic_tag_addr) & |ic_tag_wdata) & |ic_data_req) & ic_data_write) & |ic_data_addr) & |ic_data_wdata; |
| function automatic [TagSizeECC - 1:0] sv2v_cast_CFEC9; |
| input reg [TagSizeECC - 1:0] inp; |
| sv2v_cast_CFEC9 = inp; |
| endfunction |
| assign ic_tag_rdata = {ibex_pkg_IC_NUM_WAYS {sv2v_cast_CFEC9('b0)}}; |
| function automatic [LineSizeECC - 1:0] sv2v_cast_80844; |
| input reg [LineSizeECC - 1:0] inp; |
| sv2v_cast_80844 = inp; |
| endfunction |
| assign ic_data_rdata = {ibex_pkg_IC_NUM_WAYS {sv2v_cast_80844('b0)}}; |
| assign lockstep_alert_major = 1'b0; |
| assign lockstep_alert_minor = 1'b0; |
| assign data_wdata_intg_o = 'b0; |
| wire unused_scan; |
| wire unused_intg; |
| assign unused_scan = scan_rst_ni; |
| assign unused_intg = |{instr_rdata_intg_i, data_rdata_intg_i}; |
| assign alert_major_o = core_alert_major | lockstep_alert_major; |
| assign alert_minor_o = core_alert_minor | lockstep_alert_minor; |
| endmodule |