commit e2e302a79707fb085c8e3e9097487808f074f845
author Muhammed Çelik <celikmuhammed@outlook.com.tr> Wed Dec 29 13:52:11 2021 +0300
committer Muhammed Çelik <celikmuhammed@outlook.com.tr> Wed Dec 29 13:52:11 2021 +0300
tree 096235ab6c499a68e1162e6e6c8b57f4933fe482
parent f3a26d07e41181f1ef424e48555af25d1e98333b

Update README.md

README.md

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 Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)
 
-First couple of parity bits (Y1W1) are generated from normal ordered input data.
-Second couple of parity bits (Y2W2) are generated from interleaved input data.
+First couple of parity bits (Y1W1) are generated from normal ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
+
+The design involves 2 paths one of which is used for interleaved input data.
 
 #### Top-Level Diagram
 ![alt text](docs/encoder_schematic.png)