Add Turbo Encoder RTL files, add tests
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
old mode 100644
new mode 100755
index 2aa188c..e664a25
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -13,27 +13,40 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_proj_example
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/user_proj_example.v \
+ $script_dir/../../verilog/rtl/turbo_encoder_top.v \
+ $script_dir/../../verilog/rtl/turbo_enc_agu.v \
+ $script_dir/../../verilog/rtl/pre_encoder.v \
+ $script_dir/../../verilog/rtl/pre_encoder_rom.v \
+ $script_dir/../../verilog/rtl/dual_ram.v \
+ $script_dir/../../verilog/rtl/encoder_core.v \
+ $script_dir/../../verilog/rtl/fifo.v"
set ::env(DESIGN_IS_CORE) 0
set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
+#set ::env(CLOCK_NET) "turbo_encoder_top_inst.i_clk"
+set ::env(CLOCK_PERIOD) "20"
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
+#set ::env(FP_SIZING) absolute
+#set ::env(DIE_AREA) "0 0 900 600"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.3"
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) "0.3"
+
+#set ::env(PL_BASIC_PLACEMENT) 1
+#set ::env(PL_TARGET_DENSITY) 0.05
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
@@ -45,6 +58,6 @@
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(DIODE_INSERTION_STRATEGY) 3
# If you're going to use multiple power domains, then disable cvc run.
set ::env(RUN_CVC) 1
diff --git a/verilog/dv/turbo_encoder_gpio_test/Makefile b/verilog/dv/turbo_encoder_gpio_test/Makefile
new file mode 100644
index 0000000..514d9ce
--- /dev/null
+++ b/verilog/dv/turbo_encoder_gpio_test/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = turbo_encoder_gpio_test
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/turbo_encoder_gpio_test/encoder_input.txt b/verilog/dv/turbo_encoder_gpio_test/encoder_input.txt
new file mode 100644
index 0000000..fd104c0
--- /dev/null
+++ b/verilog/dv/turbo_encoder_gpio_test/encoder_input.txt
@@ -0,0 +1,56 @@
+11
+10
+11
+00
+00
+00
+00
+11
+11
+01
+11
+10
+00
+01
+00
+01
+00
+00
+00
+00
+00
+10
+01
+10
+00
+01
+11
+10
+10
+10
+01
+01
+10
+00
+10
+10
+01
+10
+11
+00
+10
+01
+11
+01
+01
+00
+01
+10
+01
+10
+00
+11
+01
+00
+00
+11
diff --git a/verilog/dv/turbo_encoder_gpio_test/ref_encoder_out.txt b/verilog/dv/turbo_encoder_gpio_test/ref_encoder_out.txt
new file mode 100644
index 0000000..b4f8841
--- /dev/null
+++ b/verilog/dv/turbo_encoder_gpio_test/ref_encoder_out.txt
@@ -0,0 +1,56 @@
+110000
+100010
+111000
+000100
+000111
+000001
+001110
+110010
+111011
+011101
+111111
+100000
+001100
+011011
+001111
+010000
+000000
+000101
+001100
+001101
+000110
+100111
+010101
+101110
+000010
+011110
+110101
+101101
+101000
+101001
+010111
+011011
+101111
+000100
+100010
+101000
+011100
+100110
+110110
+001000
+101101
+011111
+110111
+011110
+010111
+001001
+011010
+101100
+011001
+100110
+001001
+110110
+010101
+000101
+000100
+110010
diff --git a/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test.c b/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test.c
new file mode 100644
index 0000000..045b6c5
--- /dev/null
+++ b/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test.c
@@ -0,0 +1,103 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+
+void main()
+{
+
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFE; // [95:64]
+ reg_la1_data = 0x00000001;
+ // Flag start of the test
+ reg_mprj_datah = 0x0000003F;
+
+ /*reg_mprj_slave = 0x00002710;
+ if (reg_mprj_slave == 0x2752) {
+ reg_mprj_datal = 0xAB610000;
+ } else {
+ reg_mprj_datal = 0xAB600000;
+ }*/
+}
diff --git a/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test_tb.v b/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test_tb.v
new file mode 100644
index 0000000..532363a
--- /dev/null
+++ b/verilog/dv/turbo_encoder_gpio_test/turbo_encoder_gpio_test_tb.v
@@ -0,0 +1,258 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module turbo_encoder_gpio_test_tb;
+
+ reg RSTB;
+ reg CSB;
+ reg clock = 0;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ reg [1:0] encoder_input [55:0];
+ reg [5:0] ref_encoder_out [55:0];
+
+ integer i, j, mismatch_count = 0, dump_file;
+
+ reg test_start = 0;
+
+ reg rstn = 1;
+ reg i_bof = 0;
+ reg i_eof = 0;
+ reg i_valid = 0;
+ reg i_ready = 1;
+ reg [1:0] i_data;
+ reg [5:0] param_sel = 0;
+
+ wire clk;
+ wire o_bof;
+ wire o_eof;
+ wire o_valid;
+ wire o_ready;
+ wire [5:0] o_data;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ assign mprj_io[8] = rstn;
+ assign mprj_io[9] = i_bof;
+ assign mprj_io[10] = i_eof;
+ assign mprj_io[11] = i_valid;
+ assign mprj_io[18] = i_ready;
+ assign mprj_io[14:13] = i_data;
+ assign mprj_io[30:25] = param_sel;
+ assign clk = mprj_io[31];
+ assign o_bof = mprj_io[15];
+ assign o_eof = mprj_io[16];
+ assign o_valid = mprj_io[17];
+ assign o_ready = mprj_io[12];
+ assign o_data = mprj_io[24:19];
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock = ~clock;
+
+ initial begin
+ $dumpfile("turbo_encoder_gpio_test.vcd");
+ $dumpvars(0, turbo_encoder_gpio_test_tb);
+ $readmemb("encoder_input.txt", encoder_input);
+ $readmemb("ref_encoder_out.txt", ref_encoder_out);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (30) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Turbo Encoder Test (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Turbo Encoder Test (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ dump_file = $fopen("test_dump.txt");
+
+ wait(test_start);
+
+ for (j = 0; j < 300; j = j + 1) begin
+ $fdisplay(dump_file, "\n -------------------- t = %d -------------------- \n\n", j);
+ $fdisplay(dump_file, "i_clk : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_clk);
+ $fdisplay(dump_file, "i_rstn : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_rstn);
+ $fdisplay(dump_file, "i_bof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_bof);
+ $fdisplay(dump_file, "i_eof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_eof);
+ $fdisplay(dump_file, "i_valid : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_valid);
+ $fdisplay(dump_file, "i_data : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_data);
+ $fdisplay(dump_file, "i_ready : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_ready);
+ $fdisplay(dump_file, "o_ready : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_ready);
+ $fdisplay(dump_file, "o_valid : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_valid);
+ $fdisplay(dump_file, "o_bof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_bof);
+ $fdisplay(dump_file, "o_eof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_eof);
+ $fdisplay(dump_file, "o_data : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_data);
+ #20 wait(clk);
+ end
+ end
+
+ initial begin
+ wait (mprj_io [37:32] == 6'b111111);
+ test_start = 1;
+ $display("Monitor: Turbo Encoder Test Started");
+ rstn = 0;
+ #100;
+ rstn = 1;
+
+ wait (~clk);
+ wait (clk);
+
+ i_valid = 1;
+
+ for (i = 0; i < 56; i = i + 1) begin
+ if (i == 0) i_bof = 1;
+ else i_bof = 0;
+
+ if (i == 55) i_eof = 1;
+ else i_eof = 0;
+
+ i_data = encoder_input[i];
+ $display("Input Data = %b", encoder_input[i]);
+
+ wait(~clk);
+ wait(clk);
+ end
+
+ i_valid = 0;
+ i_eof = 0;
+
+ wait(o_bof);
+ wait(clk);
+
+ for (i = 0; i < 56; i = i + 1) begin
+ if (o_data != ref_encoder_out[i]) mismatch_count = mismatch_count + 1;
+ $display("Output Data = %b, Reference Data = %b", o_data, ref_encoder_out[i]);
+
+ wait(~clk);
+ wait(clk);
+ end
+
+ if(mismatch_count == 0) begin
+ `ifdef GL
+ $display("Monitor: Turbo Encoder Test (GL) Passed");
+ `else
+ $display("Monitor: Turbo Encoder Test (RTL) Passed");
+ `endif
+ end
+ else begin
+ `ifdef GL
+ $display ("Monitor: Mismatch, Turbo Encoder Test (GL) Failed");
+ `else
+ $display ("Monitor: Mismatch, Turbo Encoder Test (RTL) Failed");
+ `endif
+ end
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("turbo_encoder_gpio_test.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/dv/turbo_encoder_la_test/Makefile b/verilog/dv/turbo_encoder_la_test/Makefile
new file mode 100644
index 0000000..49d3205
--- /dev/null
+++ b/verilog/dv/turbo_encoder_la_test/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = turbo_encoder_la_test
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test.c b/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test.c
new file mode 100644
index 0000000..e60e9e5
--- /dev/null
+++ b/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test.c
@@ -0,0 +1,203 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks counter value through the wishbone port
+*/
+
+void main()
+{
+
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datah = 0x0000003F;
+
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFF80; // [63:32]
+
+ reg_la1_data = 0x00000000;
+
+ // Flag start of the test
+
+ /*for (int i = 0; i < 56; i++){
+ reg_mprj_slave = input_data[i];
+ }
+
+ for (int i = 0; i < 56; i++){
+ while (reg_mprj_slave == out_ref_data[i])
+ reg_mprj_slave = input_data[i];
+ }*/
+
+ reg_mprj_slave = 0x0000c043;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c002;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c003;
+ reg_mprj_slave = 0x0000c001;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c000;
+ reg_mprj_slave = 0x0000c083;
+
+ for (int i = 0; i < 8; i++);
+
+ reg_mprj_slave = 0x00006000;
+
+ while (reg_mprj_slave != 0x0000c070);
+ while (reg_mprj_slave != 0x0000c022);
+ while (reg_mprj_slave != 0x0000c038);
+ while (reg_mprj_slave != 0x0000c004);
+ while (reg_mprj_slave != 0x0000c007);
+ while (reg_mprj_slave != 0x0000c001);
+ while (reg_mprj_slave != 0x0000c00e);
+ while (reg_mprj_slave != 0x0000c032);
+ while (reg_mprj_slave != 0x0000c03b);
+ while (reg_mprj_slave != 0x0000c01d);
+ while (reg_mprj_slave != 0x0000c03f);
+ while (reg_mprj_slave != 0x0000c020);
+ while (reg_mprj_slave != 0x0000c00c);
+ while (reg_mprj_slave != 0x0000c01b);
+ while (reg_mprj_slave != 0x0000c00f);
+ while (reg_mprj_slave != 0x0000c010);
+ while (reg_mprj_slave != 0x0000c000);
+ while (reg_mprj_slave != 0x0000c005);
+ while (reg_mprj_slave != 0x0000c00c);
+ while (reg_mprj_slave != 0x0000c00d);
+ while (reg_mprj_slave != 0x0000c006);
+ while (reg_mprj_slave != 0x0000c027);
+ while (reg_mprj_slave != 0x0000c015);
+ while (reg_mprj_slave != 0x0000c02e);
+ while (reg_mprj_slave != 0x0000c002);
+ while (reg_mprj_slave != 0x0000c01e);
+ while (reg_mprj_slave != 0x0000c035);
+ while (reg_mprj_slave != 0x0000c02d);
+ while (reg_mprj_slave != 0x0000c028);
+ while (reg_mprj_slave != 0x0000c029);
+ while (reg_mprj_slave != 0x0000c017);
+ while (reg_mprj_slave != 0x0000c01b);
+ while (reg_mprj_slave != 0x0000c02f);
+ while (reg_mprj_slave != 0x0000c004);
+ while (reg_mprj_slave != 0x0000c022);
+ while (reg_mprj_slave != 0x0000c028);
+ while (reg_mprj_slave != 0x0000c01c);
+ while (reg_mprj_slave != 0x0000c026);
+ while (reg_mprj_slave != 0x0000c036);
+ while (reg_mprj_slave != 0x0000c008);
+ while (reg_mprj_slave != 0x0000c02d);
+ while (reg_mprj_slave != 0x0000c01f);
+ while (reg_mprj_slave != 0x0000c037);
+ while (reg_mprj_slave != 0x0000c01e);
+ while (reg_mprj_slave != 0x0000c017);
+ while (reg_mprj_slave != 0x0000c009);
+ while (reg_mprj_slave != 0x0000c01a);
+ while (reg_mprj_slave != 0x0000c02c);
+ while (reg_mprj_slave != 0x0000c019);
+ while (reg_mprj_slave != 0x0000c026);
+ while (reg_mprj_slave != 0x0000c009);
+ while (reg_mprj_slave != 0x0000c036);
+ while (reg_mprj_slave != 0x0000c015);
+ while (reg_mprj_slave != 0x0000c005);
+ while (reg_mprj_slave != 0x0000c004);
+ while (reg_mprj_slave != 0x0000c0b2);
+
+ reg_mprj_datah = 0x0000003E;
+}
diff --git a/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test_tb.v b/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test_tb.v
new file mode 100644
index 0000000..f7babea
--- /dev/null
+++ b/verilog/dv/turbo_encoder_la_test/turbo_encoder_la_test_tb.v
@@ -0,0 +1,189 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module turbo_encoder_la_test_tb;
+
+ reg RSTB;
+ reg CSB;
+ reg clock = 0;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ reg [1:0] encoder_input [55:0];
+ reg [5:0] ref_encoder_out [55:0];
+
+ integer i, j, mismatch_count = 0, dump_file;
+
+ reg test_start = 0;
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock = ~clock;
+
+ initial begin
+ $dumpfile("turbo_encoder_la_test.vcd");
+ $dumpvars(0, turbo_encoder_la_test_tb);
+ $readmemb("encoder_input.txt", encoder_input);
+ $readmemb("ref_encoder_out.txt", ref_encoder_out);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (50) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Turbo Encoder Test (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Turbo Encoder Test (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ dump_file = $fopen("test_dump.txt");
+
+ wait(test_start);
+
+ for (j = 0; j < 300; j = j + 1) begin
+ $fdisplay(dump_file, "\n -------------------- t = %d -------------------- \n\n", j);
+ $fdisplay(dump_file, "i_clk : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_clk);
+ $fdisplay(dump_file, "i_rstn : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_rstn);
+ $fdisplay(dump_file, "i_bof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_bof);
+ $fdisplay(dump_file, "i_eof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_eof);
+ $fdisplay(dump_file, "i_valid : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_valid);
+ $fdisplay(dump_file, "i_data : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_data);
+ $fdisplay(dump_file, "i_ready : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.i_ready);
+ $fdisplay(dump_file, "o_ready : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_ready);
+ $fdisplay(dump_file, "o_valid : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_valid);
+ $fdisplay(dump_file, "o_bof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_bof);
+ $fdisplay(dump_file, "o_eof : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_eof);
+ $fdisplay(dump_file, "o_data : %b\n", uut.mprj.mprj.turbo_encoder_top_inst.o_data);
+ #20 wait(clock);
+ end
+ end
+
+ initial begin
+ wait (mprj_io [37:32] == 6'b111111);
+
+ test_start = 1;
+
+ $display("Monitor: Turbo Encoder Test Started");
+
+ wait (mprj_io [37:32] == 6'b111110);
+
+ `ifdef GL
+ $display("Monitor: Turbo Encoder Test (GL) Passed");
+ `else
+ $display("Monitor: Turbo Encoder Test (RTL) Passed");
+ `endif
+
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("turbo_encoder_la_test.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/rtl/dual_ram.v b/verilog/rtl/dual_ram.v
new file mode 100644
index 0000000..2a9f8dc
--- /dev/null
+++ b/verilog/rtl/dual_ram.v
@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+module dual_ram
+(
+ input [1:0] dia, dib,
+ input [11:0] addra, addrb,
+ input wea, web, clk,
+ output reg [1:0] doa, dob
+);
+ // Declare the RAM variable
+ reg [1:0] ram[2395:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (wea)
+ begin
+ ram[addra] <= dia;
+ doa <= dia;
+ end
+ else
+ begin
+ doa <= ram[addra];
+ end
+ end
+
+ // Port B
+ always @ (posedge clk)
+ begin
+ if (web)
+ begin
+ ram[addrb] <= dib;
+ dob <= dib;
+ end
+ else
+ begin
+ dob <= ram[addrb];
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/encoder_core.v b/verilog/rtl/encoder_core.v
new file mode 100644
index 0000000..fafdcd2
--- /dev/null
+++ b/verilog/rtl/encoder_core.v
@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+module encoder_core (
+ //inputs
+ i_clk,
+ i_rstn,
+ i_valid,
+ i_ena,
+ i_load_si,
+ i_a,
+ i_b,
+ i_si,
+ //outputs
+ o_a,
+ o_b,
+ o_y,
+ o_w,
+ o_so
+);
+
+ parameter MAX_BLOCK_WIDTH = 10,
+ P_WIDTH = 10,
+ MAX_DATA_WIDTH = MAX_BLOCK_WIDTH+2;
+
+ input i_clk;
+ input i_rstn;
+ input i_valid;
+ input i_ena;
+ input i_load_si;
+ input i_a;
+ input i_b;
+ input[3:0] i_si;
+
+ output o_a;
+ output o_b;
+ output o_y;
+ output o_w;
+ output[3:0] o_so;
+
+ reg[3:0] s_reg;
+//
+
+
+ always @(posedge i_clk)
+ begin
+ if (i_rstn == 0) //
+ s_reg <= 0;
+
+ else begin
+
+ if (i_load_si == 1)
+ s_reg <= i_si;
+ else if (i_valid == 1 && i_ena == 1)
+ begin
+ s_reg[3] <= i_a ^ i_b ^ s_reg[1] ^ s_reg[0];
+ s_reg[2] <= s_reg[3] ^ i_b;
+ s_reg[1] <= s_reg[2];
+ s_reg[0] <= s_reg[1] ^ i_b;
+ end
+ else
+ s_reg <= s_reg;
+
+ end
+ end
+
+ assign o_a = i_a;
+ assign o_b = i_b;
+ assign o_y = i_a ^ i_b ^ s_reg[1] ^ s_reg[0] ^ s_reg[3] ^ s_reg[2] ^ s_reg[0];
+ assign o_w = i_a ^ i_b ^ s_reg[1] ^ s_reg[0] ^ s_reg[2] ^ s_reg[1] ^ s_reg[0];
+ assign o_so = s_reg;
+
+endmodule
+
diff --git a/verilog/rtl/fifo.v b/verilog/rtl/fifo.v
new file mode 100644
index 0000000..a693122
--- /dev/null
+++ b/verilog/rtl/fifo.v
@@ -0,0 +1,91 @@
+// Listing 4.20
+module fifo
+ #(
+ parameter B=8, // number of bits in a word
+ W=4 // number of address bits
+ )
+ (
+ input wire clk, reset,
+ input wire rd, wr,
+ input wire [B-1:0] w_data,
+ output wire empty, full,
+ output wire [B-1:0] r_data
+ );
+
+ //signal declaration
+ reg [B-1:0] array_reg [2**W-1:0]; // register array
+ reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
+ reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
+ reg full_reg, empty_reg, full_next, empty_next;
+ wire wr_en;
+
+ // body
+ // register file write operation
+ always @(posedge clk)
+ if (wr_en)
+ array_reg[w_ptr_reg] <= w_data;
+ // register file read operation
+ assign r_data = array_reg[r_ptr_reg];
+ // write enabled only when FIFO is not full
+ assign wr_en = wr & ~full_reg;
+
+ // fifo control logic
+ // register for read and write pointers
+ always @(posedge clk, posedge reset)
+ if (reset)
+ begin
+ w_ptr_reg <= 0;
+ r_ptr_reg <= 0;
+ full_reg <= 1'b0;
+ empty_reg <= 1'b1;
+ end
+ else
+ begin
+ w_ptr_reg <= w_ptr_next;
+ r_ptr_reg <= r_ptr_next;
+ full_reg <= full_next;
+ empty_reg <= empty_next;
+ end
+
+ // next-state logic for read and write pointers
+ always @*
+ begin
+ // successive pointer values
+ w_ptr_succ = w_ptr_reg + 1;
+ r_ptr_succ = r_ptr_reg + 1;
+ // default: keep old values
+ w_ptr_next = w_ptr_reg;
+ r_ptr_next = r_ptr_reg;
+ full_next = full_reg;
+ empty_next = empty_reg;
+ case ({wr, rd})
+ // 2'b00: no op
+ 2'b01: // read
+ if (~empty_reg) // not empty
+ begin
+ r_ptr_next = r_ptr_succ;
+ full_next = 1'b0;
+ if (r_ptr_succ==w_ptr_reg)
+ empty_next = 1'b1;
+ end
+ 2'b10: // write
+ if (~full_reg) // not full
+ begin
+ w_ptr_next = w_ptr_succ;
+ empty_next = 1'b0;
+ if (w_ptr_succ==r_ptr_reg)
+ full_next = 1'b1;
+ end
+ 2'b11: // write and read
+ begin
+ w_ptr_next = w_ptr_succ;
+ r_ptr_next = r_ptr_succ;
+ end
+ endcase
+ end
+
+ // output
+ assign full = full_reg;
+ assign empty = empty_reg;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/pre_encoder.v b/verilog/rtl/pre_encoder.v
new file mode 100644
index 0000000..dbf974a
--- /dev/null
+++ b/verilog/rtl/pre_encoder.v
@@ -0,0 +1,104 @@
+`timescale 1ns / 1ps
+module pre_encoder (
+ //inputs
+ i_clk,
+ i_rstn,
+ i_valid,
+ i_ena,
+ i_load_si,
+ i_a,
+ i_b,
+ i_conf_blocksize,
+
+ //outputs
+ o_s
+);
+ parameter MAX_BLOCK_WIDTH = 10,
+ P_WIDTH = 10,
+ MAX_DATA_WIDTH = MAX_BLOCK_WIDTH+2;
+
+
+ input i_clk;
+ input i_rstn;
+ input i_valid;
+ input i_ena;
+ input i_load_si;
+ input i_a;
+ input i_b;
+ input[MAX_BLOCK_WIDTH-1:0] i_conf_blocksize;
+
+ output[3:0] o_s;
+
+ // wires and registers assigned
+ wire[3:0] o_so;
+ wire[3:0] w_S_out;
+ reg [3:0] nmod15_minus1;
+ encoder_core ec1 (
+ .i_clk (i_clk),
+ .i_rstn (i_rstn),
+ .i_valid (i_valid),
+ .i_ena (i_ena),
+ .i_load_si (i_load_si),
+ .i_a (i_a),
+ .i_b (i_b),
+ .i_si (4'b0000),
+ .o_a (),
+ .o_b (),
+ .o_y (),
+ .o_w (),
+ .o_so (o_so)
+ );
+
+ pre_encoder_rom pre_rom(
+ .i_S(o_so),
+ .i_nmod15_minus1(nmod15_minus1),
+ .o_S_out(w_S_out)
+ );
+
+ always @(i_conf_blocksize)
+ begin
+ case(i_conf_blocksize)
+ 14: nmod15_minus1 = 10;
+ 38: nmod15_minus1 = 1;
+ 51: nmod15_minus1 = 8;
+ 55: nmod15_minus1 = 9;
+ 59: nmod15_minus1 = 10;
+ 62: nmod15_minus1 = 7;
+ 69: nmod15_minus1 = 5;
+ 84: nmod15_minus1 = 5;
+ 85: nmod15_minus1 = 9;
+ 93: nmod15_minus1 = 11;
+ 96: nmod15_minus1 = 8;
+ 100:nmod15_minus1 = 9;
+ 108:nmod15_minus1 = 11;
+ 115:nmod15_minus1 = 9;
+ 123:nmod15_minus1 = 11;
+ 130:nmod15_minus1 = 9;
+ 144:nmod15_minus1 = 5;
+ 170:nmod15_minus1 = 4;
+ 175:nmod15_minus1 = 9;
+ 188:nmod15_minus1 = 1;
+ 194:nmod15_minus1 = 10;
+ 264:nmod15_minus1 = 5;
+ 298:nmod15_minus1 = 6;
+ 333:nmod15_minus1 = 11;
+ 355:nmod15_minus1 = 9;
+ 400:nmod15_minus1 = 9;
+ 438:nmod15_minus1 = 11;
+ 444:nmod15_minus1 = 5;
+ 539:nmod15_minus1 = 10;
+ 599:nmod15_minus1 = 10;
+ 128:nmod15_minus1 = 1;
+ 192:nmod15_minus1 = 2;
+ 256:nmod15_minus1 = 3;
+ 307:nmod15_minus1 = 12;
+ default: nmod15_minus1 = 0;
+ endcase
+ end
+
+ assign o_s = w_S_out;
+
+endmodule
+
+
+
\ No newline at end of file
diff --git a/verilog/rtl/pre_encoder_rom.v b/verilog/rtl/pre_encoder_rom.v
new file mode 100644
index 0000000..54d24b3
--- /dev/null
+++ b/verilog/rtl/pre_encoder_rom.v
@@ -0,0 +1,259 @@
+`timescale 1ns / 1ps
+module pre_encoder_rom (
+ i_S,
+ i_nmod15_minus1,
+ o_S_out
+);
+ input [3:0] i_S;
+ input [3:0] i_nmod15_minus1;
+ output reg [3:0] o_S_out;
+
+ wire [7:0] addr;
+
+ assign addr = {i_nmod15_minus1,i_S}; // multiply by 16 and add current state //changed non-blocking assignment to blocking assignment
+
+ always @(*)
+ begin
+
+ case (addr)
+ 0: o_S_out = 0;
+ 1: o_S_out = 14;
+ 2: o_S_out = 3;
+ 3: o_S_out = 13;
+ 4: o_S_out = 7;
+ 5: o_S_out = 9;
+ 6: o_S_out = 4;
+ 7: o_S_out = 10;
+ 8: o_S_out = 15;
+ 9: o_S_out = 1;
+ 10: o_S_out = 12;
+ 11: o_S_out = 2;
+ 12: o_S_out = 8;
+ 13: o_S_out = 6;
+ 14: o_S_out = 11;
+ 15: o_S_out = 5;
+
+ 16: o_S_out = 0;
+ 17: o_S_out = 11;
+ 18: o_S_out = 13;
+ 19: o_S_out = 6;
+ 20: o_S_out = 10;
+ 21: o_S_out = 1;
+ 22: o_S_out = 7;
+ 23: o_S_out = 12;
+ 24: o_S_out = 5;
+ 25: o_S_out = 14;
+ 26: o_S_out = 8;
+ 27: o_S_out = 3;
+ 28: o_S_out = 15;
+ 29: o_S_out = 4;
+ 30: o_S_out = 2;
+ 31: o_S_out = 9;
+
+ 32: o_S_out = 0;
+ 33: o_S_out = 8;
+ 34: o_S_out = 9;
+ 35: o_S_out = 1;
+ 36: o_S_out = 2;
+ 37: o_S_out = 10;
+ 38: o_S_out = 11;
+ 39: o_S_out = 3;
+ 40: o_S_out = 4;
+ 41: o_S_out = 12;
+ 42: o_S_out = 13;
+ 43: o_S_out = 5;
+ 44: o_S_out = 6;
+ 45: o_S_out = 14;
+ 46: o_S_out = 15;
+ 47: o_S_out = 7;
+
+ 48: o_S_out = 0;
+ 49: o_S_out = 3;
+ 50: o_S_out = 4;
+ 51: o_S_out = 7;
+ 52: o_S_out = 8;
+ 53: o_S_out =11;
+ 54: o_S_out = 12;
+ 55: o_S_out = 15;
+ 56: o_S_out = 1;
+ 57: o_S_out = 2;
+ 58: o_S_out = 5;
+ 59: o_S_out = 6;
+ 60: o_S_out = 9;
+ 61: o_S_out = 10;
+ 62: o_S_out = 13;
+ 63: o_S_out = 14;
+
+ 64: o_S_out = 0;
+ 65: o_S_out = 12;
+ 66: o_S_out = 5;
+ 67: o_S_out = 9;
+ 68: o_S_out = 11;
+ 69: o_S_out = 7;
+ 70: o_S_out = 14;
+ 71: o_S_out = 2;
+ 72: o_S_out = 6;
+ 73: o_S_out = 10;
+ 74: o_S_out = 3;
+ 75: o_S_out = 15;
+ 76: o_S_out = 13;
+ 77: o_S_out = 1;
+ 78: o_S_out = 8;
+ 79: o_S_out = 4;
+
+ 80: o_S_out = 0;
+ 81: o_S_out = 4;
+ 82: o_S_out = 12;
+ 83: o_S_out = 8;
+ 84: o_S_out = 9;
+ 85: o_S_out = 13;
+ 86: o_S_out = 5;
+ 87: o_S_out = 1;
+ 88: o_S_out = 2;
+ 89: o_S_out = 6;
+ 90: o_S_out = 14;
+ 91: o_S_out = 10;
+ 92: o_S_out = 11;
+ 93: o_S_out = 15;
+ 94: o_S_out = 7;
+ 95: o_S_out = 3;
+
+ 96: o_S_out = 0;
+ 97: o_S_out = 6;
+ 98: o_S_out = 10;
+ 99: o_S_out = 12;
+ 100: o_S_out = 5;
+ 101: o_S_out = 3;
+ 102: o_S_out = 15;
+ 103: o_S_out = 9;
+ 104: o_S_out = 11;
+ 105: o_S_out = 13;
+ 106: o_S_out = 1;
+ 107: o_S_out = 7;
+ 108: o_S_out = 14;
+ 109: o_S_out = 8;
+ 110: o_S_out = 4;
+ 111: o_S_out = 2;
+
+ 112: o_S_out = 0;
+ 113: o_S_out = 7;
+ 114: o_S_out = 8;
+ 115: o_S_out = 15;
+ 116: o_S_out = 1;
+ 117: o_S_out = 6;
+ 118: o_S_out = 9;
+ 119: o_S_out = 14;
+ 120: o_S_out = 3;
+ 121: o_S_out = 4;
+ 122: o_S_out = 11;
+ 123: o_S_out = 12;
+ 124: o_S_out = 2;
+ 125: o_S_out = 5;
+ 126: o_S_out = 10;
+ 127: o_S_out = 13;
+
+ 128: o_S_out = 0;
+ 129: o_S_out = 5;
+ 130: o_S_out = 14;
+ 131: o_S_out = 11;
+ 132: o_S_out = 13;
+ 133: o_S_out = 8;
+ 134: o_S_out = 3;
+ 135: o_S_out = 6;
+ 136: o_S_out = 10;
+ 137: o_S_out = 15;
+ 138: o_S_out = 4;
+ 139: o_S_out = 1;
+ 140: o_S_out = 7;
+ 141: o_S_out = 2;
+ 142: o_S_out = 9;
+ 143: o_S_out = 12;
+
+ 144: o_S_out = 0;
+ 145: o_S_out = 13;
+ 146: o_S_out = 7;
+ 147: o_S_out = 10;
+ 148: o_S_out = 15;
+ 149: o_S_out = 2;
+ 150: o_S_out = 8;
+ 151: o_S_out = 5;
+ 152: o_S_out = 14;
+ 153: o_S_out = 3;
+ 154: o_S_out = 9;
+ 155: o_S_out = 4;
+ 156: o_S_out = 1;
+ 157: o_S_out = 12;
+ 158: o_S_out = 6;
+ 159: o_S_out = 11;
+
+ 160: o_S_out = 0;
+ 161: o_S_out = 2;
+ 162: o_S_out = 6;
+ 163: o_S_out = 4;
+ 164: o_S_out = 12;
+ 165: o_S_out = 14;
+ 166: o_S_out = 10;
+ 167: o_S_out = 8;
+ 168: o_S_out = 9;
+ 169: o_S_out = 11;
+ 170: o_S_out = 15;
+ 171: o_S_out = 13;
+ 172: o_S_out = 5;
+ 173: o_S_out = 7;
+ 174: o_S_out = 3;
+ 175: o_S_out = 1;
+
+ 176: o_S_out = 0;
+ 177: o_S_out = 9;
+ 178: o_S_out = 11;
+ 179: o_S_out = 2;
+ 180: o_S_out = 6;
+ 181: o_S_out = 15;
+ 182: o_S_out = 13;
+ 183: o_S_out = 4;
+ 184: o_S_out = 12;
+ 185: o_S_out = 5;
+ 186: o_S_out = 7;
+ 187: o_S_out = 14;
+ 188: o_S_out = 10;
+ 189: o_S_out = 3;
+ 190: o_S_out = 1;
+ 191: o_S_out = 8;
+
+ 192: o_S_out = 0;
+ 193: o_S_out = 10;
+ 194: o_S_out = 15;
+ 195: o_S_out = 5;
+ 196: o_S_out = 14;
+ 197: o_S_out = 4;
+ 198: o_S_out = 1;
+ 199: o_S_out = 11;
+ 200: o_S_out = 13;
+ 201: o_S_out = 7;
+ 202: o_S_out = 2;
+ 203: o_S_out = 8;
+ 204: o_S_out = 3;
+ 205: o_S_out = 9;
+ 206: o_S_out = 12;
+ 207: o_S_out = 6;
+
+ 208: o_S_out = 0;
+ 209: o_S_out = 15;
+ 210: o_S_out = 1;
+ 211: o_S_out = 14;
+ 212: o_S_out = 3;
+ 213: o_S_out = 12;
+ 214: o_S_out = 2;
+ 215: o_S_out = 13;
+ 216: o_S_out = 7;
+ 217: o_S_out = 8;
+ 218: o_S_out = 6;
+ 219: o_S_out = 9;
+ 220: o_S_out = 4;
+ 221: o_S_out = 11;
+ 222: o_S_out = 5;
+ 223: o_S_out = 10;
+ default: o_S_out = 0;
+ endcase
+ end
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/turbo_enc_agu.v b/verilog/rtl/turbo_enc_agu.v
new file mode 100644
index 0000000..e03a76c
--- /dev/null
+++ b/verilog/rtl/turbo_enc_agu.v
@@ -0,0 +1,193 @@
+`timescale 1ns / 1ps
+module turbo_enc_agu (
+ //inputs
+ i_clk,
+ i_rstn,
+ i_block_size,
+ i_mode,
+ i_ea,
+ i_p0,
+ i_q0,
+ i_q1,
+ i_q2,
+ i_q3,
+ i_start,
+ i_ib_data_ab,
+ //outputs
+ o_ib_adx_ab,
+ o_siso_data_ab,
+ o_siso_buf_wr,
+ o_read_done
+);
+ parameter MAX_BLOCK_WIDTH = 10,
+ P_WIDTH = 10,
+ MAX_DATA_WIDTH = MAX_BLOCK_WIDTH + 2;
+
+
+ input i_clk;
+ input i_rstn;
+ input[MAX_BLOCK_WIDTH-1:0] i_block_size;
+ input i_mode;
+ input[MAX_DATA_WIDTH-1:0] i_ea;
+ input[P_WIDTH-1:0] i_p0;
+ input[MAX_DATA_WIDTH-1:0] i_q0;
+ input[MAX_DATA_WIDTH-1:0] i_q1;
+ input[MAX_DATA_WIDTH-1:0] i_q2;
+ input[MAX_DATA_WIDTH-1:0] i_q3;
+ input i_start;
+ input[1:0] i_ib_data_ab;
+
+
+ output[MAX_DATA_WIDTH-1:0] o_ib_adx_ab;
+ output[1:0] o_siso_data_ab;
+ output reg o_siso_buf_wr;
+ output o_read_done;
+
+ reg addr_state; // state machine for addr_states
+ parameter wait_start = 0, addr_generate = 1;
+ reg mode;
+ reg[MAX_DATA_WIDTH-1:0] lin_adx;
+ reg[MAX_DATA_WIDTH-1:0] lin_adx_d;
+
+ reg[MAX_DATA_WIDTH-1:0] pi_d;
+ reg[MAX_DATA_WIDTH-1:0] lambda_d;
+ reg toggle_d;
+ reg valid;
+ reg valid_d;
+ reg read_done;
+ reg read_done_d;
+
+
+ wire[MAX_DATA_WIDTH-1:0] n;
+ wire[MAX_DATA_WIDTH-1:0] q0_d;
+ wire[MAX_DATA_WIDTH-1:0] q1_d;
+ wire[MAX_DATA_WIDTH-1:0] q2_d;
+ wire[MAX_DATA_WIDTH-1:0] q3_d;
+ reg[MAX_DATA_WIDTH-1:0] q_mux;
+ wire[MAX_DATA_WIDTH-1:0] lambda;
+ wire[MAX_DATA_WIDTH-1:0] pi;
+ wire[(MAX_DATA_WIDTH+1)-1:0] lambda_mod_1;
+ wire signed[(MAX_DATA_WIDTH+1)-1:0] lambda_mod_2;
+ wire[(MAX_DATA_WIDTH+1)-1:0] pi_mod_1;
+ wire signed[(MAX_DATA_WIDTH+1)-1:0] pi_mod_2;
+ wire siso_buf_wr;
+
+ assign q0_d = i_q0;
+ assign q1_d = i_q1;
+ assign q2_d = i_q2;
+ assign q3_d = i_q3;
+
+ always @(posedge i_clk) //address_generation_process
+ begin
+ if(i_rstn == 0) begin
+ addr_state <= wait_start;
+ mode <= 0;
+ lin_adx <= 0;
+ lin_adx_d <= 0;
+ lambda_d <= 0;
+ pi_d <= 0;
+ valid <= 0;
+ read_done <= 0;
+ end
+
+ else begin
+ case(addr_state)
+ wait_start:
+ begin
+ valid <= 0;
+ read_done <= 0;
+ if (i_start == 1) begin
+ mode <= i_mode;
+ lin_adx <= 0;
+ lambda_d <= 0;
+ addr_state <= addr_generate;
+ end
+ end
+ addr_generate:
+ begin
+ valid <= 1;
+ lin_adx <= lin_adx + 1;
+ lin_adx_d <= lin_adx;
+ lambda_d <= lambda;
+ pi_d <= pi;
+ if (lin_adx == i_ea) begin
+ read_done <= 1;
+ addr_state <= wait_start;
+ end
+ end
+ endcase
+
+ end
+ end
+
+ assign siso_buf_wr = valid_d;
+
+ always @(posedge i_clk) // siso_buffer_write_process
+ begin
+ if (i_rstn == 0) begin
+ valid_d <= 0;
+ toggle_d <= 0;
+ read_done_d <= 0;
+ end
+
+ else begin
+ valid_d <= valid;
+ if (mode == 1)begin
+ toggle_d <= ~pi_d[0];
+ end
+ else begin
+ toggle_d <= 0;
+ end
+
+ read_done_d <= read_done;
+ end
+ end
+
+ assign n = {i_block_size,2'b00};
+
+ // ACC Unit 1
+ assign lambda_mod_1 = {1'b0,lambda_d} + i_p0;
+ assign lambda_mod_2 = lambda_mod_1 - {1'b0,n};
+ assign lambda = (lambda_mod_2[MAX_DATA_WIDTH]) ? lambda_mod_1[MAX_DATA_WIDTH-1:0] : lambda_mod_2[MAX_DATA_WIDTH-1:0];
+
+ // ACC Unit 2
+ always@(*)
+ begin
+ case (lin_adx[1:0])
+ 1: q_mux = q1_d;
+ 2: q_mux = q2_d;
+ 3: q_mux = q3_d;
+ default: q_mux = q0_d;
+ endcase
+ end
+
+ assign pi_mod_1 = {1'b0,lambda_d} + {1'b0,q_mux};
+ assign pi_mod_2 = pi_mod_1 - {1'b0,n};
+ assign pi = (pi_mod_2[MAX_DATA_WIDTH]) ? pi_mod_1[MAX_DATA_WIDTH-1:0] : pi_mod_2[MAX_DATA_WIDTH-1:0];
+
+ // read data from input buffer
+ assign o_ib_adx_ab = (mode) ? pi_d : lin_adx_d;
+
+
+ // send data to encoder
+ assign o_siso_data_ab = (toggle_d) ? {i_ib_data_ab[0],i_ib_data_ab[1]} : i_ib_data_ab;
+
+
+ always @(posedge i_clk)
+ begin
+ if (i_rstn == 0)
+ o_siso_buf_wr <= 0;
+ else
+ o_siso_buf_wr <= siso_buf_wr;
+
+ end
+
+ // Send feedback to controller
+
+ assign o_read_done = read_done_d;
+
+endmodule
+
+
+
+
\ No newline at end of file
diff --git a/verilog/rtl/turbo_encoder_top.v b/verilog/rtl/turbo_encoder_top.v
new file mode 100644
index 0000000..0da7ca8
--- /dev/null
+++ b/verilog/rtl/turbo_encoder_top.v
@@ -0,0 +1,390 @@
+`timescale 1ns / 1ps
+module turbo_encoder_top (
+ //inputs
+ i_clk,
+ i_rstn,
+ i_bof,
+ i_eof,
+ i_valid,
+ i_data,
+ i_ready,
+ //outputs
+ o_ready,
+ o_valid,
+ o_bof,
+ o_eof,
+ o_data,
+ //
+
+ i_conf_blocksize,
+ i_conf_p,
+ i_conf_q0,
+ i_conf_q1,
+ i_conf_q2,
+ i_conf_q3
+);
+
+parameter MAX_BLOCK_WIDTH = 10,
+ P_WIDTH = 10,
+ MAX_DATA_WIDTH = MAX_BLOCK_WIDTH+2;
+
+input i_clk;
+input i_rstn;
+input i_bof;
+input i_eof;
+input i_valid;
+input[1:0] i_data;
+input i_ready;
+
+output reg o_ready;
+output o_valid;
+output o_bof;
+output reg o_eof;
+output[5:0]o_data;
+
+input[MAX_BLOCK_WIDTH-1:0] i_conf_blocksize;
+input[P_WIDTH-1:0] i_conf_p;
+input[MAX_DATA_WIDTH-1:0] i_conf_q0;
+input[MAX_DATA_WIDTH-1:0] i_conf_q1;
+input[MAX_DATA_WIDTH-1:0] i_conf_q2;
+input[MAX_DATA_WIDTH-1:0] i_conf_q3;
+
+// AGU_0 Signals
+wire[MAX_DATA_WIDTH-1:0] agu_ib_adx_ab;
+wire[1:0] agu_data_ab;
+wire agu_buf_wr;
+reg start;
+wire[MAX_DATA_WIDTH-1:0] agu_ea;
+wire[MAX_DATA_WIDTH-1:0] agu_ea_gen;
+wire read_done;
+reg[1:0] agu_data_ab_d;
+reg start_d1;
+reg start_d2;
+reg start_d3;
+reg start_d4;
+reg start_d5;
+reg valid_select;
+
+// AGU_1 Signals
+wire[MAX_DATA_WIDTH-1:0] agu_int_ib_adx_ab;
+wire[1:0] agu_int_data_ab;
+reg[1:0] agu_int_data_ab_d;
+wire agu_int_buf_wr;
+reg[1:0] ib_data;
+
+// RAM_0 Signals
+reg wea_AB;
+reg[MAX_DATA_WIDTH-1:0] addra;
+wire[1:0] dob_ram0_AB_0;
+
+// RAM_1 Signals
+wire[1:0] dob_ram1_AB_0;
+
+// pre encoder signals
+reg pre_enc_valid;
+reg pre_enc_ena;
+reg pre_enc_load_si;
+wire[3:0] o_s;
+wire[3:0] o_s_int;
+
+// encoder signals
+reg enc_ena;
+reg enc_load_si;
+wire o_a;
+wire o_b;
+wire o_y1;
+wire o_w1;
+wire o_y2;
+wire o_w2;
+
+//delay registers
+reg read_done_d;
+reg read_done_dd;
+
+
+reg [2:0]state; // state machine
+ parameter
+ idle = 3'b000,
+ write_input_buffer_state = 3'b001,
+ pre_encode_state = 3'b010,
+ ready_wait_state = 3'b011,
+ si_load_state = 3'b100,
+ encode_state = 3'b101,
+ encode_state_end = 3'b110;
+
+
+
+assign agu_ea_gen = {i_conf_blocksize,2'b00};
+assign agu_ea = agu_ea_gen - 1;
+
+dual_ram inst_input_ram_0(
+ //port a (read/write)
+ .clk(i_clk),
+ .wea(wea_AB),
+ .addra(addra),
+ .dia(ib_data),
+ .doa(),
+ //port b (read/write)
+ .web(0),
+ .addrb(agu_ib_adx_ab),
+ .dib(0),
+ .dob(dob_ram0_AB_0)
+);
+
+
+dual_ram inst_input_ram_1(
+ //port a (read/write)
+ .clk(i_clk),
+ .wea(wea_AB),
+ .addra(addra),
+ .dia(ib_data),
+ .doa(),
+ //port b (read/write)
+ .web(0),
+ .addrb(agu_int_ib_adx_ab),
+ .dib(0),
+ .dob(dob_ram1_AB_0)
+);
+
+turbo_enc_agu inst_agu_0(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_block_size(i_conf_blocksize),
+ .i_mode(0),
+ .i_ea(agu_ea),
+ .i_p0(i_conf_p),
+ .i_q0(i_conf_q0),
+ .i_q1(i_conf_q1),
+ .i_q2(i_conf_q2),
+ .i_q3(i_conf_q3),
+ .i_start(start),
+ .i_ib_data_ab(dob_ram0_AB_0),
+ .o_ib_adx_ab(agu_ib_adx_ab),
+ .o_siso_data_ab(agu_data_ab),
+ .o_siso_buf_wr(agu_buf_wr),
+ .o_read_done(read_done)
+);
+
+turbo_enc_agu inst_agu_1(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_block_size(i_conf_blocksize),
+ .i_mode(1),
+ .i_ea(agu_ea),
+ .i_p0(i_conf_p),
+ .i_q0(i_conf_q0),
+ .i_q1(i_conf_q1),
+ .i_q2(i_conf_q2),
+ .i_q3(i_conf_q3),
+ .i_start(start),
+ .i_ib_data_ab(dob_ram1_AB_0),
+ .o_ib_adx_ab(agu_int_ib_adx_ab),
+ .o_siso_data_ab(agu_int_data_ab),
+ .o_siso_buf_wr(agu_int_buf_wr),
+ .o_read_done()
+);
+
+pre_encoder inst_pre_encoder_0(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_valid(agu_buf_wr),
+ .i_ena(pre_enc_ena),
+ .i_load_si(pre_enc_load_si),
+ .i_a(agu_data_ab_d[1]),
+ .i_b(agu_data_ab_d[0]),
+ .i_conf_blocksize(i_conf_blocksize),
+
+ .o_s(o_s)
+);
+
+pre_encoder inst_pre_encoder_1(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_valid(agu_int_buf_wr),
+ .i_ena(pre_enc_ena),
+ .i_load_si(pre_enc_load_si),
+ .i_a(agu_int_data_ab_d[1]),
+ .i_b(agu_int_data_ab_d[0]),
+ .i_conf_blocksize(i_conf_blocksize),
+
+ .o_s(o_s_int)
+);
+
+encoder_core inst_encoder_core_0(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_valid(agu_buf_wr),
+ .i_ena(enc_ena),
+ .i_load_si(enc_load_si),
+ .i_a(agu_data_ab_d[1]),
+ .i_b(agu_data_ab_d[0]),
+ .i_si(o_s),
+
+ .o_a(o_a),
+ .o_b(o_b),
+ .o_y(o_y1),
+ .o_w(o_w1),
+ .o_so()
+);
+
+encoder_core inst_encoder_core_1(
+ .i_clk(i_clk),
+ .i_rstn(i_rstn),
+ .i_valid(agu_buf_wr),
+ .i_ena(enc_ena),
+ .i_load_si(enc_load_si),
+ .i_a(agu_int_data_ab_d[1]),
+ .i_b(agu_int_data_ab_d[0]),
+ .i_si(o_s_int),
+
+ .o_a(),
+ .o_b(),
+ .o_y(o_y2),
+ .o_w(o_w2),
+ .o_so()
+);
+
+always @(posedge i_clk) //state machine
+begin
+ if (i_rstn == 0)
+ begin
+ state <= idle;
+ pre_enc_load_si <= 0;
+ enc_load_si <= 0;
+ start <= 0;
+ o_eof <= 0;
+ o_ready <= 1;
+ read_done_d <= 0;
+ read_done_dd <= 0;
+ addra <= 0;
+ ib_data <= 0;
+ pre_enc_ena <= 0;
+ enc_ena <= 0;
+ agu_data_ab_d <= 0;
+ start_d1 <= 0;
+ start_d2 <= 0;
+ start_d3 <= 0;
+ start_d4 <= 0;
+ start_d5 <= 0;
+ valid_select <= 0;
+ end
+
+ else
+ begin
+ read_done_d <= read_done;
+ read_done_dd <= read_done_d;
+ //read_done_ddd <= read_done_dd;
+ agu_data_ab_d <= agu_data_ab;
+ agu_int_data_ab_d <= agu_int_data_ab;
+ start_d1 <= start;
+ start_d2 <= start_d1;
+ start_d3 <= start_d2;
+ start_d4 <= start_d3;
+ start_d5 <= start_d4;
+
+
+ case (state)
+ idle: ////
+ begin
+ addra <= 0;
+ wea_AB <= 0;
+ pre_enc_load_si <= 0;
+ pre_enc_valid <= 0;
+ enc_load_si <= 0;
+ start <= 0;
+ o_eof <= 0;
+ o_ready <= 1;
+ ib_data <= 0;
+ pre_enc_ena <= 0;
+ enc_ena <= 0;
+ valid_select <= 0;
+
+ if (i_bof == 1 && i_valid == 1) begin
+ wea_AB <= 1;
+ ib_data <= i_data;
+ state <= write_input_buffer_state;
+ end
+ end
+ write_input_buffer_state: ////
+ begin
+ valid_select <= 0;
+
+ if (i_valid == 1) begin
+ wea_AB <= 1;
+ addra <= addra + 1;
+ ib_data <= i_data;
+
+ if (i_eof == 1) begin
+ state <= pre_encode_state;
+ o_ready <= 0;
+ pre_enc_load_si <= 1;
+ pre_enc_ena <= 1;
+ start <= 1;
+ end
+ end
+
+ else
+ wea_AB <= 0;
+ end
+ pre_encode_state: ////
+ begin
+ wea_AB <= 0;
+ pre_enc_load_si <= 1'b0;
+ start <= 0;
+
+ if (read_done_dd == 1) begin
+ if(i_ready == 1)
+ state <= si_load_state;
+ else
+ state <= ready_wait_state;
+ end
+ end
+ ready_wait_state: ////
+ begin
+ if (i_ready == 1)
+ state <= si_load_state;
+ end
+ si_load_state: ////
+ begin
+ valid_select <= 1;
+ state <= encode_state;
+ pre_enc_ena <= 0;
+ enc_load_si <= 1;
+ enc_ena <= 1;
+ start <= 1;
+ end
+ encode_state: ////
+ begin
+ enc_load_si <= 0;
+ start <= 0;
+ if (read_done == 1) begin
+ o_eof <= 1;
+ state <= encode_state_end;
+ end
+ end
+ encode_state_end: ////
+ begin
+ o_eof <= 0;
+ state <= idle;
+ end
+
+ default:
+ begin
+ state <= idle;
+ end
+
+ endcase
+ end
+end
+
+assign o_bof = start_d4 & valid_select;
+assign o_valid = agu_buf_wr & valid_select;
+assign o_data = {o_a , o_b , o_y1 , o_w1 , o_y2 , o_w2};
+
+endmodule
+
+
+
+
+
+
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..5936275 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,11 @@
`else
`include "user_project_wrapper.v"
`include "user_proj_example.v"
+ `include "fifo.v"
+ `include "dual_ram.v"
+ `include "encoder_core.v"
+ `include "pre_encoder_rom.v"
+ `include "pre_encoder.v"
+ `include "turbo_enc_agu.v"
+ `include "turbo_encoder_top.v"
`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..f7b7834 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -70,96 +70,505 @@
);
wire clk;
wire rst;
+ wire i_bof;
+ wire i_eof;
+ wire i_valid;
+ wire [1:0] i_data;
+ wire i_ready;
+ wire o_ready;
+ wire o_valid;
+ wire o_bof;
+ wire o_eof;
+ wire [5:0] o_data;
+
+ wire rx_fifo_rd;
+ wire rx_fifo_wr;
+ wire [3:0] rx_fifo_r_data;
+ wire [3:0] rx_fifo_w_data;
+ wire rx_fifo_empty;
+ wire rx_fifo_full;
+
+ wire tx_fifo_rd;
+ wire tx_fifo_wr;
+ wire [7:0] tx_fifo_r_data;
+ wire [7:0] tx_fifo_w_data;
+ wire tx_fifo_empty;
+ wire tx_fifo_full;
+
+ wire [5:0] param_sel;
+
+ reg rx_fifo_rd_start;
+ reg tx_fifo_rd_start;
+ reg master_rden;
+ reg wbs_ack_o;
+
+ reg [9:0] i_conf_blocksize;
+ reg [9:0] i_conf_p;
+ reg [11:0] i_conf_q0;
+ reg [11:0] i_conf_q1;
+ reg [11:0] i_conf_q2;
+ reg [11:0] i_conf_q3;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
wire valid;
wire [3:0] wstrb;
- wire [31:0] la_write;
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
- // IO
- assign io_out = count;
assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
// IRQ
assign irq = 3'b000; // Unused
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+ assign rx_fifo_rd = rx_fifo_rd_start & (~rx_fifo_empty);
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
+ assign clk = wb_clk_i;
+ assign rst = wb_rst_i;
+ assign i_bof = (la_data_in[32]) ? io_in[9] : rx_fifo_rd & rx_fifo_r_data[2];
+ assign i_eof = (la_data_in[32]) ? io_in[10] : rx_fifo_rd & rx_fifo_r_data[3];
+ assign i_valid = (la_data_in[32]) ? io_in[11] : rx_fifo_rd;
+ assign i_data = (la_data_in[32]) ? io_in[14:13] : (rx_fifo_rd) ? rx_fifo_r_data[1:0] : 0;
+ assign i_ready = (la_data_in[32]) ? io_in[18] : 1'b1;
+
+ assign wbs_dat_o[14] = (la_data_in[32]) ? 1'bz : 1'b1;
+ assign wbs_dat_o[15] = (la_data_in[32]) ? 1'bz : tx_fifo_rd_start;
+ assign wbs_dat_o[6] = (la_data_in[32]) ? 1'bz : tx_fifo_r_data[6];
+ assign wbs_dat_o[7] = (la_data_in[32]) ? 1'bz : tx_fifo_r_data[7];
+ assign wbs_dat_o[5:0] = (la_data_in[32]) ? 6'bz : tx_fifo_r_data[5:0];
+ assign wbs_dat_o[31:16] = 0;
+ assign wbs_dat_o[13:8] = 0;
+
+ assign io_out[12] = (la_data_in[32]) ? o_ready : 1'bz;
+ assign io_out[17] = (la_data_in[32]) ? o_valid : 1'bz;
+ assign io_out[15] = (la_data_in[32]) ? o_bof : 1'bz;
+ assign io_out[16] = (la_data_in[32]) ? o_eof : 1'bz;
+ assign io_out[24:19] = (la_data_in[32]) ? o_data : 6'bz;
+ assign io_out[31] = (la_data_in[32]) ? ~wb_clk_i : 1'bz;
+
+ assign param_sel = (la_data_in[32]) ? io_in[30:25] : la_data_in[38:33];
+
+ turbo_encoder_top turbo_encoder_top_inst(
+ .i_clk(clk),
+ .i_rstn(~rst),
+ .i_bof(i_bof),
+ .i_eof(i_eof),
+ .i_valid(i_valid),
+ .i_data(i_data),
+ .i_ready(i_ready),
+ .o_ready(o_ready),
+ .o_valid(o_valid),
+ .o_bof(o_bof),
+ .o_eof(o_eof),
+ .o_data(o_data),
+ .i_conf_blocksize(i_conf_blocksize),
+ .i_conf_p(i_conf_p),
+ .i_conf_q0(i_conf_q0),
+ .i_conf_q1(i_conf_q1),
+ .i_conf_q2(i_conf_q2),
+ .i_conf_q3(i_conf_q3)
);
-endmodule
+ fifo #(.B(4), .W(8)) rx_fifo_inst(
+ .clk(clk),
+ .reset(rst),
+ .rd(rx_fifo_rd),
+ .wr(valid & (~wbs_ack_o) & wbs_dat_i[15]),
+ .w_data({wbs_dat_i[7], wbs_dat_i[6], wbs_dat_i[1:0]}),
+ .r_data(rx_fifo_r_data),
+ .empty(rx_fifo_empty),
+ .full(rx_fifo_full)
+ );
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
+ fifo #(.B(8), .W(8)) tx_fifo_inst(
+ .clk(clk),
+ .reset(rst),
+ .rd(valid & wbs_ack_o & master_rden ),
+ .wr(o_valid),
+ .w_data({o_eof, o_bof, o_data}),
+ .r_data(tx_fifo_r_data),
+ .empty(tx_fifo_empty),
+ .full(tx_fifo_full)
+ );
always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
+ if (rst) begin
+ rx_fifo_rd_start = 0;
+ tx_fifo_rd_start = 0;
+ master_rden = 0;
+ wbs_ack_o = 0;
+ end
+ else begin
+ if (valid & wbs_dat_i[15] & wbs_dat_i[7]) rx_fifo_rd_start <= 1;
+ if (rx_fifo_empty) rx_fifo_rd_start <= 0;
+
+ if (o_eof) tx_fifo_rd_start <= 1;
+ if (tx_fifo_empty) tx_fifo_rd_start <= 0;
+
+ if ((~wbs_dat_i[13]) & valid & (~wbs_ack_o)) master_rden <= 0;
+ if (wbs_dat_i[13] & valid & (~wbs_ack_o)) master_rden <= 1;
+
+ wbs_ack_o <= 0;
+ if (valid & (~wbs_ack_o)) wbs_ack_o <= 1;
+
+ case(param_sel)
+
+ 0:
+ begin
+ i_conf_blocksize <= 14;
+ i_conf_p <= 9;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 11;
+ i_conf_q2 <= 51;
+ i_conf_q3 <= 19;
+ end
+
+ 1:
+ begin
+ i_conf_blocksize <= 38;
+ i_conf_p <= 17;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 23;
+ i_conf_q2 <= 63;
+ i_conf_q3 <= 11;
+ end
+
+ 2:
+ begin
+ i_conf_blocksize <= 51;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 23;
+ i_conf_q2 <= 107;
+ i_conf_q3 <= 107;
+ end
+
+ 3:
+ begin
+ i_conf_blocksize <= 55;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 43;
+ i_conf_q2 <= 131;
+ i_conf_q3 <= 115;
+ end
+
+ 4:
+ begin
+ i_conf_blocksize <= 59;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 11;
+ i_conf_q2 <= 23;
+ i_conf_q3 <= 219;
+ end
+
+ 5:
+ begin
+ i_conf_blocksize <= 62;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 35;
+ i_conf_q2 <= 63;
+ i_conf_q3 <= 63;
+ end
+
+ 6:
+ begin
+ i_conf_blocksize <= 69;
+ i_conf_p <= 25;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 111;
+ i_conf_q3 <= 103;
+ end
+
+ 7:
+ begin
+ i_conf_blocksize <= 84;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 83;
+ i_conf_q3 <= 71;
+ end
+
+ 8:
+ begin
+ i_conf_blocksize <= 85;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 55;
+ i_conf_q2 <= 255;
+ i_conf_q3 <= 215;
+ end
+
+ 9:
+ begin
+ i_conf_blocksize <= 93;
+ i_conf_p <= 25;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 31;
+ i_conf_q2 <= 111;
+ i_conf_q3 <= 107;
+ end
+
+ 10:
+ begin
+ i_conf_blocksize <= 96;
+ i_conf_p <= 25;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 11;
+ i_conf_q2 <= 103;
+ i_conf_q3 <= 107;
+ end
+
+ 11:
+ begin
+ i_conf_blocksize <= 100;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 35;
+ i_conf_q2 <= 131;
+ i_conf_q3 <= 127;
+ end
+
+ 12:
+ begin
+ i_conf_blocksize <= 108;
+ i_conf_p <= 29;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 19;
+ i_conf_q2 <= 123;
+ i_conf_q3 <= 123;
+ end
+
+ 13:
+ begin
+ i_conf_blocksize <= 115;
+ i_conf_p <= 29;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 23;
+ i_conf_q2 <= 239;
+ i_conf_q3 <= 239;
+ end
+
+ 14:
+ begin
+ i_conf_blocksize <= 123;
+ i_conf_p <= 31;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 15;
+ i_conf_q2 <= 7;
+ i_conf_q3 <= 3;
+ end
+
+ 15:
+ begin
+ i_conf_blocksize <= 128;
+ i_conf_p <= 31;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 135;
+ i_conf_q3 <= 131;
+ end
+
+ 16:
+ begin
+ i_conf_blocksize <= 130;
+ i_conf_p <= 31;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 11;
+ i_conf_q3 <= 3;
+ end
+
+ 17:
+ begin
+ i_conf_blocksize <= 144;
+ i_conf_p <= 31;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 3;
+ i_conf_q2 <= 3;
+ i_conf_q3 <= 3;
+ end
+
+ 18:
+ begin
+ i_conf_blocksize <= 170;
+ i_conf_p <= 33;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 63;
+ i_conf_q2 <= 523;
+ i_conf_q3 <= 515;
+ end
+
+ 19:
+ begin
+ i_conf_blocksize <= 175;
+ i_conf_p <= 37;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 11;
+ i_conf_q2 <= 3;
+ i_conf_q3 <= 11;
+ end
+
+ 20:
+ begin
+ i_conf_blocksize <= 188;
+ i_conf_p <= 37;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 15;
+ i_conf_q2 <= 167;
+ i_conf_q3 <= 159;
+ end
+
+ 21:
+ begin
+ i_conf_blocksize <= 192;
+ i_conf_p <= 37;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 183;
+ i_conf_q3 <= 123;
+ end
+
+ 22:
+ begin
+ i_conf_blocksize <= 194;
+ i_conf_p <= 39;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 3;
+ i_conf_q2 <= 319;
+ i_conf_q3 <= 319;
+ end
+
+ 23:
+ begin
+ i_conf_blocksize <= 256;
+ i_conf_p <= 45;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 199;
+ i_conf_q3 <= 183;
+ end
+
+ 24:
+ begin
+ i_conf_blocksize <= 264;
+ i_conf_p <= 43;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 3;
+ i_conf_q2 <= 27;
+ i_conf_q3 <= 11;
+ end
+
+ 25:
+ begin
+ i_conf_blocksize <= 298;
+ i_conf_p <= 49;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 15;
+ i_conf_q2 <= 23;
+ i_conf_q3 <= 3;
+ end
+
+ 26:
+ begin
+ i_conf_blocksize <= 307;
+ i_conf_p <= 49;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 27;
+ i_conf_q2 <= 3;
+ i_conf_q3 <= 7;
+ end
+
+ 27:
+ begin
+ i_conf_blocksize <= 333;
+ i_conf_p <= 49;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 23;
+ i_conf_q2 <= 3;
+ i_conf_q3 <= 23;
+ end
+
+ 28:
+ begin
+ i_conf_blocksize <= 355;
+ i_conf_p <= 53;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 19;
+ i_conf_q2 <= 239;
+ i_conf_q3 <= 223;
+ end
+
+ 29:
+ begin
+ i_conf_blocksize <= 400;
+ i_conf_p <= 53;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 43;
+ i_conf_q2 <= 243;
+ i_conf_q3 <= 219;
+ end
+
+ 30:
+ begin
+ i_conf_blocksize <= 438;
+ i_conf_p <= 59;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 7;
+ i_conf_q2 <= 247;
+ i_conf_q3 <= 243;
+ end
+
+ 31:
+ begin
+ i_conf_blocksize <= 444;
+ i_conf_p <= 59;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 35;
+ i_conf_q2 <= 731;
+ i_conf_q3 <= 715;
+ end
+
+ 32:
+ begin
+ i_conf_blocksize <= 539;
+ i_conf_p <= 65;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 15;
+ i_conf_q2 <= 31;
+ i_conf_q3 <= 3;
+ end
+
+ 33:
+ begin
+ i_conf_blocksize <= 59;
+ i_conf_p <= 23;
+ i_conf_q0 <= 3;
+ i_conf_q1 <= 11;
+ i_conf_q2 <= 23;
+ i_conf_q3 <= 219;
+ end
+
+ default:
+ begin
+ i_conf_blocksize <= 0;
+ i_conf_p <= 0;
+ i_conf_q0 <= 0;
+ i_conf_q1 <= 0;
+ i_conf_q2 <= 0;
+ i_conf_q3 <= 0;
+ end
+ endcase
end
end
-
endmodule
+
`default_nettype wire
