Merge pull request #1 from muhammed-celik/main_
Main
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Overview
========
-TBA
+The Turbo Encoder is used for FEC encoding for linear modulation.
+
+Encoder takes 2 bits of input (namely A and B) and generates 6 bits of output in the form (AB Y1W1 Y2W2)
+
+First couple of parity bits (Y1W1) are generated from normal ordered input data while second couple of parity bits (Y2W2) are generated from interleaved input data.
+
+The design involves two paths one of which is used for interleaved input data.
+
+#### Top-Level Diagram
+
+
+-Input Data is stored at dual channel rams.
+
+-AGU (Address Generator Unit) generates data indices for interleaving.
+
+-Pre Encoder unit identifies initial state of the encoder.
+
+-Encoder Core produces outputs according to the state and the inputs.
+
+#### Synthesis Report
+
+
+#### Implementation Report
+
+
+-Reports are based on Xilinx Spartan-7 xc7s6ftgb196-1
+
+
+#### Throughput
+
+
+'N' = input data block size in couple number ranging from 56 to 2396.
+
+'f' = frequency in Mhz.
+
+For 50 Mhz clock speed and N = 56, throughput equals 31.5 Mbps.
+
+For 50 Mhz clock speed and N = 2396, throughput equals 33.3 Mbps.
Setup
========
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