blob: 5169eb46e48a4720e99bad63faa8f94312682160 [file] [log] [blame]
---
project:
description: "ReRAM test chip, 4T1R Structure"
foundry: "SkyWater"
git_url: "https://github.com/lnis-uofu/testchip_4t1r.git"
organization: "LNIS Laboratory"
organization_url: "https://sites.google.com/site/pegaillardon/home"
owner: "Lea Enginger"
process: "s8"
project_name: "testchip_4t1r"
project_id: "00000000"
tags:
- "Chipignite"
- "ReRAM"
category: ""
top_level_netlist: "caravel/verilog/gl/caravan.v"
user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
version: ""
cover_image: ""