Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-004
/
slot-008
/
6912429be7f8dabf321279043cc55754164c8dc0
commit
6912429be7f8dabf321279043cc55754164c8dc0
[
log
]
author
Ganesh Gore <goreganesh007@gmail.com>
Sat Dec 11 16:53:54 2021 -0700
committer
Ganesh Gore <goreganesh007@gmail.com>
Sat Dec 11 16:53:54 2021 -0700
tree
8a312e5ef2a9d98a345f5d6773b709530a893a44
parent
a41d72f4c5cd3910bfc87560307589d300be6b4c
[
diff
]
Added Verilog
docs/source/index.rst
[
diff
]
openlane/.gitignore
[Added -
diff
]
verilog/dv/Makefile
[Added -
diff
]
verilog/dv/README.md
[Added -
diff
]
verilog/dv/mprj_por/Makefile
[Added -
diff
]
verilog/dv/mprj_por/mprj_por.c
[Added -
diff
]
verilog/dv/mprj_por/mprj_por_tb.v
[Added -
diff
]
verilog/rtl/example_por.v
[Added -
diff
]
verilog/rtl/uprj_analog_netlists.v
[Added -
diff
]
verilog/rtl/user_analog_proj_example.v
[Added -
diff
]
verilog/rtl/user_analog_project_wrapper.v
[Added -
diff
]
11 files changed
tree: 8a312e5ef2a9d98a345f5d6773b709530a893a44
.github/
docs/
gds/
mag/
openlane/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
RRAM_4T1R
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.
