Added Verilog
diff --git a/docs/source/index.rst b/docs/source/index.rst index b5f711d..a5a9e4c 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst
@@ -242,13 +242,6 @@ management SoC power supply must be stable and the C program running off of the SPI flash before the user area power supplies are raised. -**NOTE** - - When running spice extraction on the user_analog_project_wrapper layout, it is recommended to use `ext2spice short resistor`. - This is to preserve all the different port names in the extracted netlist. In case you have two ports that are electrically shorted - in the layout, the `short resistor` option will tell magic not to merge the two shorted ports instead it adds zero-ohm ideal resistors - between the net names so that they can be kept as separate nets. - Running Open-MPW Precheck Locally ================================= @@ -318,8 +311,6 @@ |:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level) -|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice - |:heavy_check_mark:| The hardened Macros are LVS and DRC clean |:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
diff --git a/openlane/.gitignore b/openlane/.gitignore new file mode 100644 index 0000000..e4867d8 --- /dev/null +++ b/openlane/.gitignore
@@ -0,0 +1,2 @@ +*/runs +default.cvcrc
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile new file mode 100644 index 0000000..a9c2027 --- /dev/null +++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +# ---- Test patterns for project striVe ---- + +.SUFFIXES: +.SILENT: clean all + +PATTERNS = mprj_por + +all: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \ + done + +DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) +$(DV_PATTERNS): verify-% : + cd $* && make + +clean: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make clean ) ; \ + done + rm -rf *.log + +.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md new file mode 100644 index 0000000..6be9cd3 --- /dev/null +++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@ +<!--- +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 +--> + +# Simulation Environment Setup + +There are two options for setting up the simulation environment: + +* Pulling a pre-built docker image +* Installing the dependecies locally + +## 1. Docker + +There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup) + +Run the following to pull the image: + +``` +docker pull efabless/dv_setup:latest +``` + +## 2. Local Installion (Linux) + +You will need to fullfil these dependecies: + +* Icarus Verilog (10.2+) +* RV32I Toolchain + +Using apt, you can install Icarus Verilog: + +```bash +sudo apt-get install iverilog +``` + +Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain, + +```bash +export GCC_PATH=<gcc-installation-path> +``` + +Then, run the following: + +```bash +# packages needed: +sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ + libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \ + gperf libtool patchutils bc zlib1g-dev git libexpat1-dev + +sudo mkdir $GCC_PATH +sudo chown $USER $GCC_PATH + +git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i +cd riscv-gnu-toolchain-rv32i +git checkout 411d134 +git submodule update --init --recursive + +mkdir build; cd build +../configure --with-arch=rv32i --prefix=$GCC_PATH +make -j$(nproc) +``` + +# Running Simulation + +## Docker + +First, you will need to export a number of environment variables: + +```bash +export PDK_PATH=<pdk-location/sky130A> +export CARAVEL_ROOT=<caravel_root> +export UPRJ_ROOT=<user_project_root> +``` + +Then, run the following command to start the docker container : + +``` +docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest +``` + +Then, navigate to the directory where the DV tests reside : + +```bash +cd $UPRJ_ROOT/verilog/dv/ +``` + +Then, follow the instructions at [Both](#both) to run RTL/GL simulation. + +## Local + +You will need to export these environment variables: + +```bash +export GCC_PATH=<gcc-installation-path> +export PDK_PATH=<pdk-location/sky130A> +``` + +Then, follow the instruction at [Both](#both) to run RTL/GL simulation. + +## Both + +To run RTL simulation for one of the DV tests, + +```bash +cd <dv-test> +make +``` + +To run gate level simulation for one of the DV tests, + +```bash +cd <dv-test> +SIM=GL make +``` + +# User Analog Project Example DV + +> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile new file mode 100644 index 0000000..e54380b --- /dev/null +++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,78 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_BEHAVIOURAL_MODELS = ../ + +## RISCV GCC +GCC_PATH?=/ef/apps/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/ef/tech/SW/sky130A + +## Simulation mode: RTL/GL +SIM?=RTL + +.SUFFIXES: + +PATTERN = mprj_por + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex +ifeq ($(SIM),RTL) + iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + $< -o $@ +else + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c new file mode 100644 index 0000000..9a51fc5 --- /dev/null +++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include "verilog/dv/caravel/defs.h" + +// -------------------------------------------------------- + +void main() +{ + reg_spimaster_config = 0xa002; // Enable, prescaler = 2 + + reg_mprj_datal = 0x00000000; + reg_mprj_datah = 0x00000000; + + // Configure mprj_io 10 and 25 as analog (digital in/out = off) + // Configure mprj_io 11, 12, 26, and 27 as digital output + // mprj_io 14 to 24 are analog pads and cannot be configured + + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG; + + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + /* Block until end of test */ + while (1); +} +
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v new file mode 100644 index 0000000..39e4a36 --- /dev/null +++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire + +`timescale 1 ns / 1 ps + +`include "uprj_analog_netlists.v" +`include "caravan_netlists.v" +`include "spiflash.v" +`include "tbuart.v" + +module mprj_por_tb; + // Signals declaration + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3; + + wire HIGH; + wire LOW; + wire TRI; + assign HIGH = 1'b1; + assign LOW = 1'b0; + assign TRI = 1'bz; + + wire gpio; + wire uart_tx; + wire [37:0] mprj_io; + wire [3:0] checkbits; + wire [1:0] status; + + // Signals Assignment + assign uart_tx = mprj_io[6]; + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // Power supply for POR + assign mprj_io[18] = power3; + + // Readback from POR (digital HV through analog pad connection) + assign status = {mprj_io[25], mprj_io[10]}; + + // Readback from POR (digital LV) + assign checkbits = {mprj_io[27:26], mprj_io[12:11]}; + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("mprj_por.vcd"); + $dumpvars(0, mprj_por_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (150) begin + repeat (1000) @(posedge clock); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + wait(status == 2'h1); + $display("Monitor: mprj_por test started"); + #100; + if (checkbits != 4'h9) begin + $display("Monitor: mprj_por test failed"); + $finish; + end + wait(status == 2'h3); + #100; + if (checkbits != 4'h5) begin + $display("Monitor: mprj_por test failed"); + $finish; + end + $display("Monitor: mprj_por test Passed"); + #10000; + $finish; + end + + // Reset Operation + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #150000; // Need time to run the managment SoC setup. + power3 <= 1'b1; // Power up the 2nd POR. + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire VSS = 1'b0; + + caravan uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + + spiflash #( + .FILENAME("mprj_por.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + + // Testbench UART + tbuart tbuart ( + .ser_rx(uart_tx) + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v new file mode 100644 index 0000000..d318fba --- /dev/null +++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +`timescale 1 ns / 1 ps + +// This is just a copy of simple_por.v from the Caravel project, used +// as an analog user project example. + +module example_por( +`ifdef USE_POWER_PINS + inout vdd3v3, + inout vdd1v8, + inout vss, +`endif + output porb_h, + output porb_l, + output por_l +); + + wire mid, porb_h; + reg inode; + + // This is a behavioral model! Actual circuit is a resitor dumping + // current (slowly) from vdd3v3 onto a capacitor, and this fed into + // two schmitt triggers for strong hysteresis/glitch tolerance. + + initial begin + inode <= 1'b0; + end + + // Emulate current source on capacitor as a 500ns delay either up or + // down. Note that this is sped way up for verilog simulation; the + // actual circuit is set to a 15ms delay. + + always @(posedge vdd3v3) begin + #500 inode <= 1'b1; + end + always @(negedge vdd3v3) begin + #500 inode <= 1'b0; + end + + // Instantiate two shmitt trigger buffers in series + + sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 ( +`ifdef USE_POWER_PINS + .VPWR(vdd3v3), + .VGND(vss), + .VPB(vdd3v3), + .VNB(vss), +`endif + .A(inode), + .X(mid) + ); + + sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 ( +`ifdef USE_POWER_PINS + .VPWR(vdd3v3), + .VGND(vss), + .VPB(vdd3v3), + .VNB(vss), +`endif + .A(mid), + .X(porb_h) + ); + + sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level ( +`ifdef USE_POWER_PINS + .VPWR(vdd3v3), + .VPB(vdd3v3), + .LVPWR(vdd1v8), + .VNB(vss), + .VGND(vss), +`endif + .A(porb_h), + .X(porb_l) + ); + + // since this is behavioral anyway, but this should be + // replaced by a proper inverter + assign por_l = ~porb_l; +endmodule +`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v new file mode 100644 index 0000000..46c2606 --- /dev/null +++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,37 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +/*--------------------------------------------------------------*/ +/* caravel, a project harness for the Google/SkyWater sky130 */ +/* fabrication process and open source PDK */ +/* */ +/* Copyright 2020 efabless, Inc. */ +/* Written by Tim Edwards, December 2019 */ +/* and Mohamed Shalan, August 2020 */ +/* This file is open source hardware released under the */ +/* Apache 2.0 license. See file LICENSE. */ +/* */ +/*--------------------------------------------------------------*/ + +`include "defines.v" +`define USE_POWER_PINS + +`ifdef GL + `default_nettype wire + `include "gl/user_analog_project_wrapper.v" + `include "gl/user_analog_proj_example.v" +`else + `include "user_analog_project_wrapper.v" + `include "user_analog_proj_example.v" +`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v new file mode 100644 index 0000000..94412da --- /dev/null +++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,221 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`include "example_por.v" + +/* + * I/O mapping for analog + * + * mprj_io[37] io_in/out/oeb/in_3v3[26] --- --- + * mprj_io[36] io_in/out/oeb/in_3v3[25] --- --- + * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] --- + * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] --- + * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] --- + * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] --- + * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] --- + * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] --- + * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] --- + * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] --- + * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] --- + * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] --- + * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] --- + * mprj_io[24] --- --- user_analog[10] + * mprj_io[23] --- --- user_analog[9] + * mprj_io[22] --- --- user_analog[8] + * mprj_io[21] --- --- user_analog[7] + * mprj_io[20] --- --- user_analog[6] clamp[2] + * mprj_io[19] --- --- user_analog[5] clamp[1] + * mprj_io[18] --- --- user_analog[4] clamp[0] + * mprj_io[17] --- --- user_analog[3] + * mprj_io[16] --- --- user_analog[2] + * mprj_io[15] --- --- user_analog[1] + * mprj_io[14] --- --- user_analog[0] + * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] --- + * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] --- + * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] --- + * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] --- + * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] --- + * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] --- + * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] --- + * mprj_io[6] io_in/out/oeb/in_3v3[6] --- --- + * mprj_io[5] io_in/out/oeb/in_3v3[5] --- --- + * mprj_io[4] io_in/out/oeb/in_3v3[4] --- --- + * mprj_io[3] io_in/out/oeb/in_3v3[3] --- --- + * mprj_io[2] io_in/out/oeb/in_3v3[2] --- --- + * mprj_io[1] io_in/out/oeb/in_3v3[1] --- --- + * mprj_io[0] io_in/out/oeb/in_3v3[0] --- --- + * + */ + +/* + *---------------------------------------------------------------- + * + * user_analog_proj_example + * + * This is an example of a (trivially simple) analog user project, + * showing how the user project can connect to the I/O pads, both + * the digital pads, the analog connection on the digital pads, + * and the dedicated analog pins used as an additional power supply + * input, with a connected ESD clamp. + * + * See the testbench in directory "mprj_por" for the example + * program that drives this user project. + * + *---------------------------------------------------------------- + */ + +module user_analog_proj_example ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + // IOs + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in, + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb, + + // GPIO-analog + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog, + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd, + + // Dedicated analog + inout [`ANALOG_PADS-1:0] io_analog, + inout [2:0] io_clamp_high, + inout [2:0] io_clamp_low, + + // Clock + input user_clock2, + + // IRQ + output [2:0] irq +); + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in; + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3; + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out; + wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb; + wire [`ANALOG_PADS-1:0] io_analog; + + // wire [31:0] rdata; + // wire [31:0] wdata; + + // wire valid; + // wire [3:0] wstrb; + + wire isupply; // Independent 3.3V supply + wire io16, io15, io12, io11; + + // WB MI A + // assign valid = wbs_cyc_i && wbs_stb_i; + // assign wstrb = wbs_sel_i & {4{wbs_we_i}}; + // assign wbs_dat_o = rdata; + // assign wdata = wbs_dat_i; + + // IO --- unused (no need to connect to anything) + // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0; + // assign io_out[14:13] = 11'b0; + // assign io_out[10:0] = 11'b0; + + // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1; + // assign io_oeb[14:13] = 11'b1; + // assign io_oeb[10:0] = 11'b1; + + // IO --- enable outputs on 11, 12, 15, and 16 + assign io_out[12:11] = {io12, io11}; + assign io_oeb[12:11] = {vssd1, vssd1}; + + assign io_out[16:15] = {io16, io15}; + assign io_oeb[16:15] = {vssd1, vssd1}; + + // IRQ + assign irq = 3'b000; // Unused + + // LA --- unused (no need to connect to anything) + // assign la_data_out = {128{1'b0}}; // Unused + + // Instantiate the POR. Connect the digital power to user area 1 + // VCCD, and connect the analog power to user area 1 VDDA. + + // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3] + // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12] + + example_por por1 ( + `ifdef USE_POWER_PINS + .vdd3v3(vdda1), + .vdd1v8(vccd1), + .vss(vssa1), + `endif + .porb_h(gpio_analog[3]), // 3.3V domain output + .porb_l(io11), // 1.8V domain output + .por_l(io12) // 1.8V domain output + ); + + // Instantiate 2nd POR with the analog power supply on one of the + // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same + // pad with io_clamp_high/low[0]. + + `ifdef USE_POWER_PINS + assign isupply = io_analog[4]; + assign io_clamp_high[0] = isupply; + assign io_clamp_low[0] = vssa1; + + // Tie off remaining clamps + assign io_clamp_high[2:1] = vssa1; + assign io_clamp_low[2:1] = vssa1; + `endif + + // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7] + // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16] + + example_por por2 ( + `ifdef USE_POWER_PINS + .vdd3v3(isupply), + .vdd1v8(vccd1), + .vss(vssa1), + `endif + .porb_h(gpio_analog[7]), // 3.3V domain output + .porb_l(io15), // 1.8V domain output + .por_l(io16) // 1.8V domain output + ); + +endmodule + +`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v new file mode 100644 index 0000000..a4a8c1a --- /dev/null +++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,181 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_analog_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user analog project. + * + *------------------------------------------------------------- + */ + +module user_analog_project_wrapper ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + /* GPIOs. There are 27 GPIOs, on either side of the analog. + * These have the following mapping to the GPIO padframe pins + * and memory-mapped registers, since the numbering remains the + * same as caravel but skips over the analog I/O: + * + * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25] + * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0] + * + * When the GPIOs are configured by the Management SoC for + * user use, they have three basic bidirectional controls: + * in, out, and oeb (output enable, sense inverted). For + * analog projects, a 3.3V copy of the signal input is + * available. out and oeb must be 1.8V signals. + */ + + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in, + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb, + + /* Analog (direct connection to GPIO pad---not for high voltage or + * high frequency use). The management SoC must turn off both + * input and output buffers on these GPIOs to allow analog access. + * These signals may drive a voltage up to the value of VDDIO + * (3.3V typical, 5.5V maximum). + * + * Note that analog I/O is not available on the 7 lowest-numbered + * GPIO pads, and so the analog_io indexing is offset from the + * GPIO indexing by 7, as follows: + * + * gpio_analog/noesd [17:7] <---> mprj_io[35:25] + * gpio_analog/noesd [6:0] <---> mprj_io[13:7] + * + */ + + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog, + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd, + + /* Analog signals, direct through to pad. These have no ESD at all, + * so ESD protection is the responsibility of the designer. + * + * user_analog[10:0] <---> mprj_io[24:14] + * + */ + inout [`ANALOG_PADS-1:0] io_analog, + + /* Additional power supply ESD clamps, one per analog pad. The + * high side should be connected to a 3.3-5.5V power supply. + * The low side should be connected to ground. + * + * clamp_high[2:0] <---> mprj_io[20:18] + * clamp_low[2:0] <---> mprj_io[20:18] + * + */ + inout [2:0] io_clamp_high, + inout [2:0] io_clamp_low, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + +/*--------------------------------------*/ +/* User project is instantiated here */ +/*--------------------------------------*/ + +user_analog_proj_example mprj ( + `ifdef USE_POWER_PINS + .vdda1(vdda1), // User area 1 3.3V power + .vdda2(vdda2), // User area 2 3.3V power + .vssa1(vssa1), // User area 1 analog ground + .vssa2(vssa2), // User area 2 analog ground + .vccd1(vccd1), // User area 1 1.8V power + .vccd2(vccd2), // User area 2 1.8V power + .vssd1(vssd1), // User area 1 digital ground + .vssd2(vssd2), // User area 2 digital ground + `endif + + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // MGMT SoC Wishbone Slave + + .wbs_cyc_i(wbs_cyc_i), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o), + .wbs_dat_o(wbs_dat_o), + + // Logic Analyzer + + .la_data_in(la_data_in), + .la_data_out(la_data_out), + .la_oenb (la_oenb), + + // IO Pads + .io_in (io_in), + .io_in_3v3 (io_in_3v3), + .io_out(io_out), + .io_oeb(io_oeb), + + // GPIO-analog + .gpio_analog(gpio_analog), + .gpio_noesd(gpio_noesd), + + // Dedicated analog + .io_analog(io_analog), + .io_clamp_high(io_clamp_high), + .io_clamp_low(io_clamp_low), + + // Clock + .user_clock2(user_clock2), + + // IRQ + .irq(user_irq) +); + +endmodule // user_analog_project_wrapper + +`default_nettype wire