blob: a3ff2278ca605a643ef41d1fe1ee8dc4a32416a4 [file] [log] [blame]
---
project:
description: "ReRAM based test chip"
foundry: "SkyWater"
git_url: ""
organization: "LNIS Laboratory"
organization_url: "https://sites.google.com/site/pegaillardon/home"
owner: "Lea Enginger"
process: "s8"
project_name: "Caravel Analog User"
project_id: "00000000"
tags:
- "Chipignite"
- "ReRAM"
category: ""
top_level_netlist: "caravel/verilog/gl/caravan.v"
user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
version: ""
cover_image: ""