Added Verilog
11 files changed
tree: 8a312e5ef2a9d98a345f5d6773b709530a893a44
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. openlane/
  6. verilog/
  7. .gitignore
  8. .gitmodules
  9. info.yaml
  10. LICENSE
  11. Makefile
  12. README.md
README.md

RRAM_4T1R

License CI Caravan Build


:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.