openlane/user_proj_example/config.json

{
    "PDK"                      : "sky130A",
    "STD_CELL_LIBRARY"         : "sky130_fd_sc_hd",
    "CARAVEL_ROOT"             : "../../caravel",
    "CLOCK_NET"                : "main_module_ins.wb_clk_i",
    "CLOCK_PERIOD"             : "10",
    "CLOCK_PORT"               : "wb_clk_i",
    "DESIGN_IS_CORE"           : "0",
    "DESIGN_NAME"              : "user_proj_example",
    "DIE_AREA"                 : "0 0 900 900",
    "DIODE_INSERTION_STRATEGY" : "4",
    "FP_PIN_ORDER_CFG"         : "pin_order.cfg",
    "FP_SIZING"                : "absolute",
    "GLB_RT_MAXLAYER"          : "5",
    "GND_NETS"                 : "vssd1",
    "PL_BASIC_PLACEMENT"       : "1",
    "PL_TARGET_DENSITY"        : "0.45",
    "RUN_CVC"                  : "1",
    "VDD_NETS"                 : "vccd1",
    "VERILOG_FILES"            : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v", "../../verilog/rtl/controller/main_module.v", "../../verilog/rtl/controller/control_module.v", "../../verilog/rtl/controller/io_module.v",  "../../verilog/rtl/controller/logic_control.v",  "../../verilog/rtl/controller/status_sender_data.v","../../verilog/rtl/controller/pmu.v",  "../../verilog/rtl/controller/UART_SERVER/uart.v", "../../verilog/rtl/controller/UART_SERVER/uart_rx.v", "../../verilog/rtl/UART_SERVER/uart_tx.v"]
}