commit: 3ea9cc35989e7fa77956fab72d5116721e306ed1

[log]
author: jaquerinte <ivanrodriguezferrandez@gmail.com>

Mon Dec 06 14:08:00 2021 +0100
committer: jaquerinte <ivanrodriguezferrandez@gmail.com>

Mon Dec 06 14:08:00 2021 +0100
tree: 405d9ee8271179e51a6182c466d040c18462b65e
parent: e8c464e23ebe026381ab166fcf6c09d8114a4ba4 [diff]

initial commit

README.md[diff]
caravel[Added - diff]
clean_run.sh[Added - diff]
def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
make_complete.sh[Added - diff]
make_sythesys.sh[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
run_test.sh[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/UART_SERVER/COPYING[Added - diff]
verilog/rtl/UART_SERVER/uart.v[Added - diff]
verilog/rtl/UART_SERVER/uart_rx.v[Added - diff]
verilog/rtl/UART_SERVER/uart_tx.v[Added - diff]
verilog/rtl/control_module.v[Added - diff]
verilog/rtl/io_module.v[Added - diff]
verilog/rtl/logic_control.v[Added - diff]
verilog/rtl/status_sender_data.v[Added - diff]
verilog/rtl/top_module.v[Added - diff]

37 files changed

tree: 405d9ee8271179e51a6182c466d040c18462b65e

README.md

Space Controller

Authors

Ivan Rodriguez-Ferrandez (UPC¹-BSC²)
Alvaro Jover-Alvarez (UPC¹-BSC²)
Leonidas Kosmidis (BSC²-UPC¹)
David Steenari (ESA³)
¹ Universitat Politècnica de Catalunya (UPC)
² Barcelona Supercomputing Center (BSC)
³ European Space Agency (ESA)

Main Version of the chip: 2.0V EXTENDED

Change Log

Version 1.0V:
- TODO

Chip Layout

Description

How To Use The Chip

Triple Redundancy Implementation

Block Description

Module Ports:

Input Ports
Output Ports

Caravel Connections

GPIO Connections

Logic Analyzer Probes

Input probes:
Output probes:

Wishbone Connection

User Maskable Interrupt Signals

Description of the Modules

Module List

Wishbone Description

Memory Map

Software Example

Available Tests