latest version of the code

caravel

diff --git a/caravel b/caravel
index 793bf63..ff960da 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 793bf634c2c1b1af90be95fcd85688e869bfb667
+Subproject commit ff960da6e06dd9097e7e1152e90f5998235a7882

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 30f4576..f7f5671 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -36,15 +36,15 @@
 set ::env(DESIGN_IS_CORE) 0
 
 set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "wb_clk_i"
+set ::env(CLOCK_NET) "main_module.PMU_inst_1.clk "
 set ::env(CLOCK_PERIOD) "10"
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 900"
+set ::env(DIE_AREA) "0 0 1600 1600"
 
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
-set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_BASIC_PLACEMENT) 0
 set ::env(PL_TARGET_DENSITY) 0.45
 
 # Maximum layer used for routing is metal 4.
@@ -60,3 +60,5 @@
 set ::env(DIODE_INSERTION_STRATEGY) 4 
 # If you're going to use multiple power domains, then disable cvc run.
 set ::env(RUN_CVC) 1
+
+set ::env(ROUTING_CORES) 4

verilog/rtl/controller/main_module.v

diff --git a/verilog/rtl/controller/main_module.v b/verilog/rtl/controller/main_module.v
index 9f18648..09a1c97 100644
--- a/verilog/rtl/controller/main_module.v
+++ b/verilog/rtl/controller/main_module.v
@@ -117,6 +117,13 @@
     assign xor_reduce_2_out_io = |xor_2_out_io;
     assign xor_reduce_3_out_io = |xor_3_out_io;
     // end output_io
+    wire ready_pmu; // wire to connect to the PMU
+    wire ready_pmu_backup; // wire to connect to the PMU
+    wire [WORD_SIZE - 1 : 0] rdata_pmu; // wire that carries the data form de pmu 
+    wire [WORD_SIZE - 1 : 0] rdata_pmu_backup; // wire that carries the data form de pmu backup
+
+    assign ready_o = ready_pmu | ready_pmu_backup | ready_pmu_backup;
+    assign rdata_o = ready_pmu ? rdata_pmu : rdata_pmu_backup;
     
     control_module #(
         .WORD_SIZE(WORD_SIZE),
@@ -184,18 +191,41 @@
     PMU#(
         .WORD_SIZE(WORD_SIZE),
         .OUTPUTS(OUTPUTS),
-        .INPUTS(INPUTS)
+        .INPUTS(INPUTS),
+        .ADDRBASE (20'h3000_0)
     )
     PMU_inst_1(
         .clk(clk),
         .rst(rst),
         .wstrb_i(wstrb_i),
         .wdata_i(wdata_i),
+        .output_io_error({xor_reduce_3_out_io,xor_reduce_2_out_io,xor_reduce_1_out_io}),
+        .trx_error({xor_reduce_3_trx,xor_reduce_2_trx, xor_reduce_1_trx}),
         .wbs_adr_i(wbs_adr_i),
         .valid_i(valid_i),
         .wbs_we_i(wbs_we_i),
-        .ready_o(ready_o),
-        .rdata_o(rdata_o)
+        .ready_o(ready_pmu),
+        .rdata_o(rdata_pmu)
+    );
+
+    PMU#(
+        .WORD_SIZE(WORD_SIZE),
+        .OUTPUTS(OUTPUTS),
+        .INPUTS(INPUTS),
+        .ADDRBASE (20'h3001_0)
+    )
+    PMU_inst_2(
+        .clk(clk),
+        .rst(rst),
+        .wstrb_i(wstrb_i),
+        .output_io_error({xor_reduce_3_out_io,xor_reduce_2_out_io,xor_reduce_1_out_io}),
+        .trx_error({xor_reduce_3_trx,xor_reduce_2_trx, xor_reduce_1_trx}),
+        .wdata_i(wdata_i),
+        .wbs_adr_i(wbs_adr_i),
+        .valid_i(valid_i),
+        .wbs_we_i(wbs_we_i),
+        .ready_o(ready_pmu_backup),
+        .rdata_o(rdata_pmu_backup)
     );
 
 endmodule

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 02a52cf..1702266 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -114,22 +114,22 @@
 
     // IO
     // IO MODE IO port connected to the 16 last 
-    assign io_out = {io_port_out,1'bx,trx,20'b0};
-    assign io_in = {io_port_in,rtx,1'bx,20'b0};
+    assign io_out = {12'b0,io_port_out,1'bx,trx,8'b0};
+    assign io_in = {12'b0,io_port_in,rtx,1'bx,8'b0};
     assign io_oeb = {(`MPRJ_IO_PADS-1){1'b0}};
 
     // IRQ
-    //assign irq = 3'b000;	// Unused
+    assign irq = 3'b000;	// Unused
 
     // LA
     assign la_data_out = {{(127-15){1'b0}}, la_out_value};
     // Assuming LA probes [63:32] are for controlling the count register  
     //assign la_write = ~la_oenb[63:32] & ~{WORD_SIZE{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
-    assign clk = wb_clk_i;
-    assign rst = wb_rst_i;
-    //assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
-    //assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+    //assign clk = wb_clk_i;
+    //assign rst = wb_rst_i;
+    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
 
    main_module #(
         .WORD_SIZE (WORD_SIZE),