last changes to adding the PMU
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json index c3de8af..c0ac816 100644 --- a/openlane/user_proj_example/config.json +++ b/openlane/user_proj_example/config.json
@@ -2,20 +2,20 @@ "PDK" : "sky130A", "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "counter.clk", + "CLOCK_NET" : "main_module.clk", "CLOCK_PERIOD" : "10", "CLOCK_PORT" : "wb_clk_i", "DESIGN_IS_CORE" : "0", "DESIGN_NAME" : "user_proj_example", - "DIE_AREA" : "0 0 900 600", + "DIE_AREA" : "0 0 900 900", "DIODE_INSERTION_STRATEGY" : "4", "FP_PIN_ORDER_CFG" : "pin_order.cfg", "FP_SIZING" : "absolute", "GLB_RT_MAXLAYER" : "5", "GND_NETS" : "vssd1", "PL_BASIC_PLACEMENT" : "1", - "PL_TARGET_DENSITY" : "0.05", + "PL_TARGET_DENSITY" : "0.45", "RUN_CVC" : "1", "VDD_NETS" : "vccd1", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"] + "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v", "../../verilog/rtl/controller/main_module.v", "../../verilog/rtl/controller/control_module.v", "../../verilog/rtl/controller/io_module.v", "../../verilog/rtl/controller/logic_control.v", "../../verilog/rtl/controller/status_sender_data.v","../../verilog/rtl/controller/pmu.v", "../../verilog/rtl/controller/UART_SERVER/uart.v", "../../verilog/rtl/controller/UART_SERVER/uart_rx.v", "../../verilog/rtl/UART_SERVER/uart_tx.v"] }
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index 94af8ba..b835ad6 100755 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -22,21 +22,30 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/user_proj_example.v\ + $script_dir/../../verilog/rtl/controller/main_module.v\ + $script_dir/../../verilog/rtl/controller/control_module.v\ + $script_dir/../../verilog/rtl/controller/io_module.v\ + $script_dir/../../verilog/rtl/controller/logic_control.v\ + $script_dir/../../verilog/rtl/controller/status_sender_data.v\ + $script_dir/../../verilog/rtl/controller/pmu.v\ + $script_dir/../../verilog/rtl/controller/UART_SERVER/uart.v\ + $script_dir/../../verilog/rtl/controller/UART_SERVER/uart_rx.v\ + $script_dir/../../verilog/rtl/controller/UART_SERVER/uart_tx.v" set ::env(DESIGN_IS_CORE) 0 set ::env(CLOCK_PORT) "wb_clk_i" -set ::env(CLOCK_NET) "counter.clk" +set ::env(CLOCK_NET) "main_module.clk" set ::env(CLOCK_PERIOD) "10" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 900 600" +set ::env(DIE_AREA) "0 0 900 900" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.05 +set ::env(PL_TARGET_DENSITY) 0.45 # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper)
diff --git a/verilog/rtl/UART_SERVER/COPYING b/verilog/rtl/controller/UART_SERVER/COPYING similarity index 100% rename from verilog/rtl/UART_SERVER/COPYING rename to verilog/rtl/controller/UART_SERVER/COPYING
diff --git a/verilog/rtl/UART_SERVER/uart.v b/verilog/rtl/controller/UART_SERVER/uart.v similarity index 100% rename from verilog/rtl/UART_SERVER/uart.v rename to verilog/rtl/controller/UART_SERVER/uart.v
diff --git a/verilog/rtl/UART_SERVER/uart_rx.v b/verilog/rtl/controller/UART_SERVER/uart_rx.v similarity index 100% rename from verilog/rtl/UART_SERVER/uart_rx.v rename to verilog/rtl/controller/UART_SERVER/uart_rx.v
diff --git a/verilog/rtl/UART_SERVER/uart_tx.v b/verilog/rtl/controller/UART_SERVER/uart_tx.v similarity index 100% rename from verilog/rtl/UART_SERVER/uart_tx.v rename to verilog/rtl/controller/UART_SERVER/uart_tx.v
diff --git a/verilog/rtl/control_module.v b/verilog/rtl/controller/control_module.v similarity index 81% rename from verilog/rtl/control_module.v rename to verilog/rtl/controller/control_module.v index ed8723a..67ded59 100644 --- a/verilog/rtl/control_module.v +++ b/verilog/rtl/controller/control_module.v
@@ -1,4 +1,5 @@ `timescale 1ns / 1ps +`default_nettype none ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: @@ -51,19 +52,19 @@ // connection wires - (* mark_debug = "true" *) wire busy_io_module; - (* mark_debug = "true" *) wire busy_sender_data; - (* mark_debug = "true" *) wire [INSTRUCTION_SIZE-1:0] instrucction; - (* mark_debug = "true" *) wire [SIZE_WORD_REGISTER-1:0] register; - (* mark_debug = "true" *) wire [AUXILIAR_SIZE-1:0] auxiliar_register; - (* mark_debug = "true" *) wire valid_instrucction; - (* mark_debug = "true" *) wire valid_control_value; + wire busy_io_module; + wire busy_sender_data; + wire [INSTRUCTION_SIZE-1:0] instrucction; + wire [SIZE_WORD_REGISTER-1:0] register; + wire [AUXILIAR_SIZE-1:0] auxiliar_register; + wire valid_instrucction; + wire valid_control_value; // control value - (* mark_debug = "true" *) wire [INPUT_DATA_SIZE-1:0] control_value; - (* mark_debug = "true" *) wire [WORD_SIZE-1:0] send_data_register; - (* mark_debug = "true" *) wire valid_data; - (* mark_debug = "true" *) wire [SIZE_WORD-1:0] size_line; - (* mark_debug = "true" *) wire [IO_OUTPUT_SIZE-1:0] result_input_io; + wire [INPUT_DATA_SIZE-1:0] control_value; + wire [WORD_SIZE-1:0] send_data_register; + wire valid_data; + wire [SIZE_WORD-1:0] size_line; + wire [IO_OUTPUT_SIZE-1:0] result_input_io; // assigments assign staus_control_module[4] = busy_io_module; @@ -139,3 +140,4 @@ ); endmodule +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/io_module.v b/verilog/rtl/controller/io_module.v similarity index 94% rename from verilog/rtl/io_module.v rename to verilog/rtl/controller/io_module.v index c6d9875..95654d6 100644 --- a/verilog/rtl/io_module.v +++ b/verilog/rtl/controller/io_module.v
@@ -22,7 +22,7 @@ module io_module # ( - parameter SIZE_WORD = 5, + parameter SIZE_WORD = 3, parameter WORD_SIZE = 32, parameter INSTRUCTION_SIZE = 3, parameter IO_OUTPUT_SIZE = 8, @@ -34,9 +34,9 @@ ( input clk, input rst, - (* mark_debug = "true" *)input [INSTRUCTION_SIZE-1:0] instrucction, - (* mark_debug = "true" *)input [SIZE_WORD-1:0] register, - (* mark_debug = "true" *)input [AUXILIAR_SIZE-1:0] auxiliar_register, + input [INSTRUCTION_SIZE-1:0] instrucction, + input [SIZE_WORD-1:0] register, + input [AUXILIAR_SIZE-1:0] auxiliar_register, input valid_instrucction, input [INPUTS-1:0] input_io, output busy, @@ -45,14 +45,14 @@ output [OUTPUTS-1:0] output_io ); reg busy; - (* mark_debug = "true" *) reg [IO_OUTPUT_SIZE-1:0] result_input_io; - (* mark_debug = "true" *) reg [OUTPUTS-1:0]output_io; - (* mark_debug = "true" *) reg valid_io; - (* mark_debug = "true" *) reg [AUXILIAR_SIZE-1:0] curent_clock; - (* mark_debug = "true" *) reg delay_maintained; + reg [IO_OUTPUT_SIZE-1:0] result_input_io; + reg [OUTPUTS-1:0]output_io; + reg valid_io; + reg [AUXILIAR_SIZE-1:0] curent_clock; + reg delay_maintained; - always @(posedge clk or posedge rst) begin + always @(posedge clk) begin if (rst) begin busy <= 0;
diff --git a/verilog/rtl/logic_control.v b/verilog/rtl/controller/logic_control.v similarity index 96% rename from verilog/rtl/logic_control.v rename to verilog/rtl/controller/logic_control.v index ea820a0..fe6a5a9 100644 --- a/verilog/rtl/logic_control.v +++ b/verilog/rtl/controller/logic_control.v
@@ -63,22 +63,22 @@ reg [WORD_SIZE-1:0] data_4 = {8'h0D, 8'h0A, 8'h20, 8'h31}; // status of the value to send - (* mark_debug = "true" *) reg valid_data; + reg valid_data; // fix size for now reg [SIZE_WORD-1:0] size_line = 3'h4; // send_data_register - (* mark_debug = "true" *) reg [WORD_SIZE-1:0] send_data_register; + reg [WORD_SIZE-1:0] send_data_register; // status of the IO module - (* mark_debug = "true" *) reg [1:0]send_petition_to_io; + reg [1:0]send_petition_to_io; reg valid_instrucction; reg [INSTRUCTION_SIZE-1:0] instrucction; reg [SIZE_WORD_REGISTER-1:0] register; reg [AUXILIAR_SIZE-1:0] auxiliar_register; - always @(posedge clk or posedge rst) begin + always @(posedge clk) begin if (rst) begin size_line <= 3'h4; send_data_register <= 0;
diff --git a/verilog/rtl/top_module.v b/verilog/rtl/controller/main_module.v similarity index 71% rename from verilog/rtl/top_module.v rename to verilog/rtl/controller/main_module.v index 0b3dbac..9f18648 100644 --- a/verilog/rtl/top_module.v +++ b/verilog/rtl/controller/main_module.v
@@ -1,4 +1,5 @@ `timescale 1ns / 1ps +`default_nettype none ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: @@ -7,38 +8,40 @@ // Design Name: // Module Name: top_module // Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: +// Target Devices: (* mark_debug = "true" *) // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// -module top_module # +module main_module # ( parameter WORD_SIZE = 32, parameter SIZE_WORD = 3, parameter INPUT_DATA_SIZE = 52, + parameter integer WHISBONE_ADR = 32, parameter STATUS_SIGNALS = 6, parameter DATA_WIDTH = 8, parameter BAUD_RATE = 115200, - parameter CLOCK_SPEED = 125000000, + parameter CLOCK_SPEED = 100000000, parameter OUTPUTS = 32, parameter INPUTS = 32 ) ( input clk, - input jc_1, - input btn, - input [3:0]sw, - output [3:0]led, - output jc_2 + input rtx, + input rst, + input [INPUTS-1:0] input_io_ports, + input wire [3 : 0] wstrb_i, + input wire [WORD_SIZE -1 : 0] wdata_i, + input wire [WHISBONE_ADR - 1 : 0] wbs_adr_i, + input wire valid_i, + input wire wbs_we_i, + output wire ready_o, + output wire [WORD_SIZE - 1 : 0] rdata_o, + output [OUTPUTS-1:0] output_io_ports, + output trx ); // prescalar reister fix for now reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH); @@ -46,7 +49,7 @@ // input IO wire [OUTPUTS - 1 : 0]input_io; // TMP assigment TODO change - assign sw = input_io[3:0]; + assign input_io_ports = input_io; // TRX triple redundancy // uart transtransmision wires @@ -55,7 +58,7 @@ wire uart_output_signal_inst_2; wire uart_output_signal_inst_3; // asignations - assign jc_2 = uart_output_signal; + assign trx = uart_output_signal; // auxiliar wires wire nand_1_trx; wire nand_2_trx; @@ -67,10 +70,10 @@ wire xor_reduce_2_trx; wire xor_reduce_3_trx; // uart transtransmision wires triple redundant - (* mark_debug = "true" *) assign nand_1_trx = ~(uart_output_signal_inst_1 & uart_output_signal_inst_2); - (* mark_debug = "true" *) assign nand_2_trx = ~(uart_output_signal_inst_2 & uart_output_signal_inst_3); - (* mark_debug = "true" *) assign nand_3_trx = ~(uart_output_signal_inst_1 & uart_output_signal_inst_3); - (* mark_debug = "true" *) assign uart_output_signal = ~(nand_1_trx & nand_2_trx & nand_3_trx); + assign nand_1_trx = ~(uart_output_signal_inst_1 & uart_output_signal_inst_2); + assign nand_2_trx = ~(uart_output_signal_inst_2 & uart_output_signal_inst_3); + assign nand_3_trx = ~(uart_output_signal_inst_1 & uart_output_signal_inst_3); + assign uart_output_signal = ~(nand_1_trx & nand_2_trx & nand_3_trx); // uart transtransmision wires triple redundant detection assign xor_1_trx = uart_output_signal_inst_1 ^ uart_output_signal_inst_2; assign xor_2_trx = uart_output_signal_inst_2 ^ uart_output_signal_inst_3; @@ -79,7 +82,9 @@ assign xor_reduce_2_trx = |xor_2_trx; assign xor_reduce_3_trx = |xor_3_trx; //end TRX - + + + // output_io triple redundancy wire [OUTPUTS - 1 : 0] output_io_signal; wire [OUTPUTS - 1 : 0] output_io_signal_inst_1; @@ -87,7 +92,7 @@ wire [OUTPUTS - 1 : 0] output_io_signal_inst_3; // asignations // TMP assigment TODO change - assign led = output_io_signal[3:0]; + assign output_io_ports = output_io_signal; // auxiliar wires wire [OUTPUTS - 1 : 0] nand_1_out_io; wire [OUTPUTS - 1 : 0] nand_2_out_io; @@ -100,10 +105,10 @@ wire xor_reduce_3_out_io; // Output IO wires triple redundant - (* mark_debug = "true" *) assign nand_1_out_io = ~(output_io_signal_inst_1 & output_io_signal_inst_2); - (* mark_debug = "true" *) assign nand_2_out_io = ~(output_io_signal_inst_2 & output_io_signal_inst_3); - (* mark_debug = "true" *) assign nand_3_out_io = ~(output_io_signal_inst_1 & output_io_signal_inst_3); - (* mark_debug = "true" *) assign output_io_signal = ~(nand_1_out_io & nand_2_out_io & nand_3_out_io); + assign nand_1_out_io = ~(output_io_signal_inst_1 & output_io_signal_inst_2); + assign nand_2_out_io = ~(output_io_signal_inst_2 & output_io_signal_inst_3); + assign nand_3_out_io = ~(output_io_signal_inst_1 & output_io_signal_inst_3); + assign output_io_signal = ~(nand_1_out_io & nand_2_out_io & nand_3_out_io); // Output IO wires triple redundant detection assign xor_1_out_io = output_io_signal_inst_1 ^ output_io_signal_inst_2; assign xor_2_out_io = output_io_signal_inst_2 ^ output_io_signal_inst_3; @@ -113,12 +118,6 @@ assign xor_reduce_3_out_io = |xor_3_out_io; // end output_io - - - //redundat_validation_o[0] <= (xor_reduce_1 ^ xor_reduce_2) | (xor_reduce_2 ^ xor_reduce_3); - //redundat_validation_o[1] <= xor_reduce_1 & xor_reduce_2 & xor_reduce_3 ; - //store_data_o <= ~(nand_1 & nand_2 & nand_3)}; - control_module #( .WORD_SIZE(WORD_SIZE), .SIZE_WORD(SIZE_WORD), @@ -130,8 +129,8 @@ ) control_module_inst_1( .clk(clk), - .rtx(jc_1), - .rst(btn), + .rtx(rtx), + .rst(rst), .preescalar_data_rate(preescalar_data_rate), .input_io(input_io), .staus_control_module(), @@ -151,8 +150,8 @@ ) control_module_inst_2( .clk(clk), - .rtx(jc_1), - .rst(btn), + .rtx(rtx), + .rst(rst), .preescalar_data_rate(preescalar_data_rate), .input_io(input_io), .staus_control_module(), @@ -172,8 +171,8 @@ ) control_module_inst_3( .clk(clk), - .rtx(jc_1), - .rst(btn), + .rtx(rtx), + .rst(rst), .preescalar_data_rate(preescalar_data_rate), .input_io(input_io), .staus_control_module(), @@ -182,4 +181,22 @@ .output_io(output_io_signal_inst_3) ); + PMU#( + .WORD_SIZE(WORD_SIZE), + .OUTPUTS(OUTPUTS), + .INPUTS(INPUTS) + ) + PMU_inst_1( + .clk(clk), + .rst(rst), + .wstrb_i(wstrb_i), + .wdata_i(wdata_i), + .wbs_adr_i(wbs_adr_i), + .valid_i(valid_i), + .wbs_we_i(wbs_we_i), + .ready_o(ready_o), + .rdata_o(rdata_o) + ); + endmodule +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/controller/pmu.v b/verilog/rtl/controller/pmu.v new file mode 100644 index 0000000..47060b1 --- /dev/null +++ b/verilog/rtl/controller/pmu.v
@@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +`default_nettype none + + +module PMU# +( + parameter WORD_SIZE = 32, + parameter OUTPUTS = 32, + parameter integer WHISBONE_ADR = 32, + parameter INPUTS = 32, + parameter integer COUNTERSIZE = 32, + parameter [19:0] ADDRBASE = 20'h3000_0 + +) +( + input wire clk, + input wire rst, + input wire [3 : 0] wstrb_i, + input wire [WORD_SIZE -1 : 0] wdata_i, + input wire [WHISBONE_ADR - 1 : 0] wbs_adr_i, + input wire valid_i, + input wire wbs_we_i, + output reg ready_o, + output reg [WORD_SIZE - 1 : 0] rdata_o + + +); + +reg [COUNTERSIZE-1:0] total_clk_pass; + +always @(posedge clk) begin + if(rst) begin + total_clk_pass <= {WORD_SIZE {1'b0}}; + end + else begin + total_clk_pass <= total_clk_pass + 1; + if (valid_i && wbs_adr_i[31:12] == ADDRBASE) begin + ready_o <= 1'b1; + if (wbs_we_i) begin + if (wstrb_i[0]) total_clk_pass[7:0] <= wdata_i[7:0]; + if (wstrb_i[1]) total_clk_pass[15:8] <= wdata_i[15:8]; + if (wstrb_i[2]) total_clk_pass[23:16] <= wdata_i[23:16]; + if (wstrb_i[3]) total_clk_pass[31:24] <= wdata_i[31:24]; + end + else begin + rdata_o <= {total_clk_pass}; + end + end + else begin + ready_o <= 1'b0; + end + end +end + +endmodule +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/status_sender_data.v b/verilog/rtl/controller/status_sender_data.v similarity index 91% rename from verilog/rtl/status_sender_data.v rename to verilog/rtl/controller/status_sender_data.v index adaed8a..b71b62f 100644 --- a/verilog/rtl/status_sender_data.v +++ b/verilog/rtl/controller/status_sender_data.v
@@ -52,21 +52,21 @@ //reg [15:0] preescalar_data_rate = CLOCK_SPEED/(BAUD_RATE*DATA_WIDTH); // create register for the input and output of the data - (* mark_debug = "true" *) reg [DATA_WIDTH-1:0] uart_tx_axis_tdata; - (* mark_debug = "true" *) reg uart_tx_axis_tvalid; - (* mark_debug = "true" *) wire uart_tx_axis_tready; + reg [DATA_WIDTH-1:0] uart_tx_axis_tdata; + reg uart_tx_axis_tvalid; + wire uart_tx_axis_tready; - //(* mark_debug = "true" *) - (* mark_debug = "true" *) wire [DATA_WIDTH-1:0] uart_rx_axis_tdata; - (* mark_debug = "true" *) wire uart_rx_axis_tvalid; - (* mark_debug = "true" *) reg uart_rx_axis_tready; + // + wire [DATA_WIDTH-1:0] uart_rx_axis_tdata; + wire uart_rx_axis_tvalid; + reg uart_rx_axis_tready; // create the register for control to remember last value send - (* mark_debug = "true" *) reg [INPUT_DATA_SIZE-1:0] output_value; + reg [INPUT_DATA_SIZE-1:0] output_value; // create the register for store the data to be send reg [WORD_SIZE-1:0] send_data_register; // register to now if is sending data - (* mark_debug = "true" *) reg sending_data; + reg sending_data; // regsiter to store the actual size reg [SIZE_WORD-1:0] data_size_actual; @@ -99,7 +99,7 @@ ); - always @(posedge clk or posedge rst) begin + always @(posedge clk) begin if (rst) begin uart_tx_axis_tdata <= 0; uart_rx_axis_tready <= 0;
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 3537de8..1065d78 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,13 @@ `else `include "user_project_wrapper.v" `include "user_proj_example.v" + `include "controller/top_module.v" + `include "controller/status_sender_data.v" + `include "controller/logic_control.v" + `include "controller/control_module.v" + `include "controller/io_module.v" + `include "controller/UART_SERVER/uart.v" + `include "controller/UART_SERVER/uart_rx.v" + `include "controller/UART_SERVER/uart_tx.v" + `include "controller/pmu.v" `endif \ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 26081e9..671ff2b 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -36,7 +36,15 @@ */ module user_proj_example #( - parameter BITS = 32 + parameter WORD_SIZE = 32, + parameter SIZE_WORD = 3, + parameter INPUT_DATA_SIZE = 52, + parameter STATUS_SIGNALS = 6, + parameter DATA_WIDTH = 8, + parameter BAUD_RATE = 115200, + parameter CLOCK_SPEED = 100000000, + parameter OUTPUTS = 32, + parameter INPUTS = 32 )( `ifdef USE_POWER_PINS inout vccd1, // User area 1 1.8V supply @@ -70,14 +78,15 @@ ); wire clk; wire rst; - + wire [15:0] io_port; + wire rtx; + wire trx; wire [`MPRJ_IO_PADS-1:0] io_in; wire [`MPRJ_IO_PADS-1:0] io_out; wire [`MPRJ_IO_PADS-1:0] io_oeb; wire [31:0] rdata; wire [31:0] wdata; - wire [BITS-1:0] count; wire valid; wire [3:0] wstrb; @@ -90,76 +99,48 @@ assign wdata = wbs_dat_i; // IO - assign io_out = count; + assign io_out = {io_port,rtx,trx,20'b0}; assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; // IRQ - assign irq = 3'b000; // Unused + //assign irq = 3'b000; // Unused // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; + //assign la_data_out = {{(127-BITS){1'b0}}, count}; // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; + //assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; + assign clk = wb_clk_i; + assign rst = wb_rst_i; + //assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; + //assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end + main_module #( + .WORD_SIZE (WORD_SIZE), + .SIZE_WORD (SIZE_WORD), + .INPUT_DATA_SIZE (INPUT_DATA_SIZE), + .STATUS_SIGNALS (STATUS_SIGNALS), + .DATA_WIDTH (DATA_WIDTH), + .BAUD_RATE (BAUD_RATE), + .CLOCK_SPEED (CLOCK_SPEED), + .OUTPUTS (OUTPUTS), + .INPUTS (INPUTS) + ) + main_module( + .clk(clk), + .rtx(rtx), + .rst(rst), + .input_io_ports({la_data_in[15:0],io_port}), + .output_io_ports({la_data_out[15:0],io_port}), + .trx(trx), + .wstrb_i(wstrb), + .wdata_i(wdata), + .wbs_adr_i(wbs_adr_i), + .valid_i(valid), + .wbs_we_i(wbs_we_i), + .ready_o(wbs_ack_o), + .rdata_o(rdata) + ); endmodule `default_nettype wire