Changed base address for OpenRAM to 0x30c00000.
diff --git a/verilog/dv/wb_openram/wb_openram.c b/verilog/dv/wb_openram/wb_openram.c
index fd265c0..488deed 100644
--- a/verilog/dv/wb_openram/wb_openram.c
+++ b/verilog/dv/wb_openram/wb_openram.c
@@ -20,8 +20,8 @@
#include "verilog/dv/caravel/stub.c"
// Caravel allows user project to use 0x30xx_xxxx address space on Wishbone bus
-// 0x3000_0000 till 3000_03ff -> 256 Words of OpenRAM (1024 Bytes)
-#define OPENRAM_BASE_ADDRESS 0x30000000
+// 0x30c0_0000 till 30c0_03ff -> 256 Words of OpenRAM (1024 Bytes)
+#define OPENRAM_BASE_ADDRESS 0x30c00000
#define OPENRAM_SIZE_DWORDS 256ul
#define OPENRAM_SIZE_BYTES (4ul * OPENRAM_SIZE_DWORDS)
#define OPENRAM_ADDRESS_MASK (OPENRAM_SIZE_BYTES - 1)
@@ -30,8 +30,9 @@
// Generates 32bits wide value out of address, not random
unsigned long generate_value(unsigned long address)
{
- return ((address & OPENRAM_ADDRESS_MASK) << 19) |
- ((~address & OPENRAM_ADDRESS_MASK) << 1);
+ return ((~address & OPENRAM_ADDRESS_MASK) << 19) +
+ ((~address & OPENRAM_ADDRESS_MASK) << 12) ^
+ ((~address & OPENRAM_ADDRESS_MASK) << 2);
}
void main()
@@ -76,21 +77,13 @@
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// Flag start of the test
- reg_mprj_datal = 0xAB600000;
+ reg_mprj_datal = 0xA8000000;
// Fill memory
for (address = 0; address < OPENRAM_SIZE_DWORDS; address += 32)
@@ -105,11 +98,11 @@
// check dword based on address
if (OPENRAM_MEM(address) != generate_value(address))
{
- reg_mprj_datal = 0xAB7E0000;
+ reg_mprj_datal = 0xAF000000;
return; // instant fail
}
}
- reg_mprj_datal = 0xAB700000; // pass
+ reg_mprj_datal = 0xAC000000; // pass
}
diff --git a/verilog/dv/wb_openram/wb_openram.hex b/verilog/dv/wb_openram/wb_openram.hex
index 3578b69..239832e 100755
--- a/verilog/dv/wb_openram/wb_openram.hex
+++ b/verilog/dv/wb_openram/wb_openram.hex
@@ -6,10 +6,10 @@
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 33
+13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 2D
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
-63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 15 2A
+63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 81 2A
01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
@@ -27,35 +27,28 @@
17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27
C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61
82 80 01 11 22 CE 00 10 23 26 A4 FE 83 27 C4 FE
-13 97 37 01 B7 07 F8 1F 7D 8F 83 27 C4 FE 93 C7
-F7 FF 86 07 93 F7 E7 7F D9 8F 3E 85 72 44 05 61
-82 80 01 11 06 CE 22 CC 26 CA 00 10 23 24 04 FE
-B7 07 00 24 29 67 09 07 98 C3 B7 07 00 26 93 87
-07 0A 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-C7 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-87 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-07 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-C7 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-87 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-07 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-C7 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-87 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-07 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-C7 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-87 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87
-47 06 09 67 13 07 97 80 98 C3 B7 07 00 26 05 47
-98 C3 01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE
-B7 07 00 26 B1 07 37 07 60 AB 98 C3 23 26 04 FE
-25 A0 83 27 C4 FE 13 F7 F7 3F B7 07 00 30 BA 97
-BE 84 03 25 C4 FE B5 3D AA 87 9C C0 83 27 C4 FE
-93 87 07 02 23 26 F4 FE 03 27 C4 FE 93 07 F0 0F
-E3 F9 E7 FC 23 26 04 FE 25 A8 83 27 C4 FE 13 F7
-F7 3F B7 07 00 30 BA 97 84 43 03 25 C4 FE 91 35
-AA 87 63 89 F4 00 B7 07 00 26 B1 07 37 07 7E AB
-98 C3 1D A0 83 27 C4 FE 93 87 07 02 23 26 F4 FE
-03 27 C4 FE 93 07 F0 0F E3 F1 E7 FC B7 07 00 26
-B1 07 37 07 70 AB 98 C3 F2 40 62 44 D2 44 05 61
-82 80 00 00
+93 C7 F7 FF 13 97 37 01 B7 07 F8 1F 7D 8F 83 27
+C4 FE 93 C7 F7 FF 93 96 C7 00 B7 F7 3F 00 F5 8F
+3E 97 83 27 C4 FE 93 C7 F7 FF 93 96 27 00 85 67
+F1 17 F5 8F B9 8F 3E 85 72 44 05 61 82 80 01 11
+06 CE 22 CC 26 CA 00 10 23 24 04 FE B7 07 00 24
+29 67 09 07 98 C3 B7 07 00 26 93 87 07 0A 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 C7 09 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 87 09 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 47 09 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 07 09 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 C7 08 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 87 08 09 67
+13 07 97 80 98 C3 B7 07 00 26 93 87 47 08 09 67
+13 07 97 80 98 C3 B7 07 00 26 05 47 98 C3 01 00
+B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07 00 26
+B1 07 37 07 00 A8 98 C3 23 26 04 FE 25 A0 83 27
+C4 FE 13 F7 F7 3F B7 07 C0 30 BA 97 BE 84 03 25
+C4 FE C5 35 AA 87 9C C0 83 27 C4 FE 93 87 07 02
+23 26 F4 FE 03 27 C4 FE 93 07 F0 0F E3 F9 E7 FC
+23 26 04 FE 25 A8 83 27 C4 FE 13 F7 F7 3F B7 07
+C0 30 BA 97 84 43 03 25 C4 FE 65 35 AA 87 63 89
+F4 00 B7 07 00 26 B1 07 37 07 00 AF 98 C3 1D A0
+83 27 C4 FE 93 87 07 02 23 26 F4 FE 03 27 C4 FE
+93 07 F0 0F E3 F1 E7 FC B7 07 00 26 B1 07 37 07
+00 AC 98 C3 F2 40 62 44 D2 44 05 61 82 80 00 00
diff --git a/verilog/dv/wb_openram/wb_openram_tb.v b/verilog/dv/wb_openram/wb_openram_tb.v
index 9bcf0d9..2888820 100644
--- a/verilog/dv/wb_openram/wb_openram_tb.v
+++ b/verilog/dv/wb_openram/wb_openram_tb.v
@@ -30,11 +30,11 @@
wire gpio;
wire [37:0] mprj_io;
- wire [11:0] checkpoint;
- wire [3:0] status;
+ wire [5:0] checkpoint;
+ wire [1:0] status;
- assign checkpoint = mprj_io[31:20];
- assign status = mprj_io[19:16];
+ assign checkpoint = mprj_io[31:26];
+ assign status = mprj_io[25:24];
// External clock is used by default. Make this artificially fast for the
@@ -67,14 +67,14 @@
end
initial begin
- wait(checkpoint == 12'h AB6);
+ wait(checkpoint == 6'b101010); // A8
`ifdef GL
$display("Monitor: Test OpenRAM Project IO (GL) Started");
`else
$display("Monitor: Test OpenRAM Project IO (RTL) Started");
`endif
- wait(checkpoint == 12'h AB7);
- if (status == 4'h 0) begin
+ wait(checkpoint == 6'b101011); // AC, AE, AF
+ if (status == 2'b00) begin
`ifdef GL
$display("Monitor: Test OpenRAM Project IO (GL) Passed");
`else
diff --git a/wb_openram_wrapper b/wb_openram_wrapper
index db174f4..07cb4ae 160000
--- a/wb_openram_wrapper
+++ b/wb_openram_wrapper
@@ -1 +1 @@
-Subproject commit db174f4483a12027fb8eb46bbf46410ce2d6121c
+Subproject commit 07cb4aeae3a4c293f6e0794aeb53bc91629d036b
