Added HyperRAM submodule (to be hardened as a macro).
diff --git a/.gitmodules b/.gitmodules
index 75fcba6..577155a 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,6 @@
[submodule "wb_ram_bus_mux"]
path = wb_ram_bus_mux
url = https://github.com/embelon/wb_ram_bus_mux.git
+[submodule "wb_hyperram"]
+ path = wb_hyperram
+ url = https://github.com/embelon/wb_hyperram.git
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 1e90b84..cbe2d2e 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -39,20 +39,21 @@
## Clock configurations
set ::env(CLOCK_PORT) [list {wb_clk_i user_clock2}]
-set ::env(CLOCK_NET) [list {openram_1kB.openram_clk0 wb_openram_wrapper.wb_clk_i wb_bus_mux.wb_clk_i}]
+set ::env(CLOCK_NET) [list {openram_1kB.openram_clk0 wb_openram_wrapper.wb_clk_i wb_bus_mux.wb_clk_i wb_hyperram.wb_clk_i}]
set ::env(CLOCK_PERIOD) "13"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
-set ::env(FP_PDN_CORE_RING) "1"
+## set ::env(FP_PDN_CORE_RING) "1"
## set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
set ::env(FP_PDN_MACRO_HOOKS) "\
wb_openram_wrapper vccd1 vssd1 \
openram_1kB vccd1 vssd1 \
- wb_bus_mux vccd1 vssd1 "
+ wb_bus_mux vccd1 vssd1 \
+ wb_hyperram vccd1 vssd1 "
set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
@@ -73,16 +74,19 @@
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
$script_dir/../../wb_openram_wrapper/src/wb_openram_wrapper.v \
$script_dir/../../wb_ram_bus_mux/src/wb_ram_bus_mux.v \
+ $script_dir/../../wb_hyperram/src/wb_hyperram.v \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../wb_openram_wrapper/lef/wb_openram_wrapper.lef \
$script_dir/../../wb_ram_bus_mux/lef/wb_ram_bus_mux.lef \
+ $script_dir/../../wb_hyperram/lef/wb_hyperram.lef \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../wb_openram_wrapper/gds/wb_openram_wrapper.gds \
$script_dir/../../wb_ram_bus_mux/gds/wb_ram_bus_mux.gds \
+ $script_dir/../../wb_hyperram/gds/wb_hyperram.gds \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
# use 4 cores
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 82b26d0..63a7bf5 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,3 +1,4 @@
openram_1kB 1000 1000 N
wb_openram_wrapper 1700 700 N
wb_bus_mux 2000 600 N
+wb_hyperram 2400 700 N
\ No newline at end of file
diff --git a/verilog/dv/wb_openram/wb_openram.c b/verilog/dv/wb_openram/wb_openram.c
index 488deed..589f1fe 100644
--- a/verilog/dv/wb_openram/wb_openram.c
+++ b/verilog/dv/wb_openram/wb_openram.c
@@ -20,6 +20,7 @@
#include "verilog/dv/caravel/stub.c"
// Caravel allows user project to use 0x30xx_xxxx address space on Wishbone bus
+// OpenRAM
// 0x30c0_0000 till 30c0_03ff -> 256 Words of OpenRAM (1024 Bytes)
#define OPENRAM_BASE_ADDRESS 0x30c00000
#define OPENRAM_SIZE_DWORDS 256ul
@@ -27,6 +28,26 @@
#define OPENRAM_ADDRESS_MASK (OPENRAM_SIZE_BYTES - 1)
#define OPENRAM_MEM(offset) (*(volatile uint32_t*)(OPENRAM_BASE_ADDRESS + (offset & OPENRAM_ADDRESS_MASK)))
+// Caravel allows user project to use 0x30xx_xxxx address space on Wishbone bus
+// HyperRAM has 8MB -> mask is 0x007fffff
+// 0x3000_0000 till 307f_ffff -> RAM / MEM inisde chip
+#define hyperram_mem_base_address 0x30000000
+#define hyperram_mem_mask 0x007fffff
+#define hyperram_mem(offset) (*(volatile uint32_t*)(hyperram_mem_base_address + (offset & hyperram_mem_mask)))
+// 0x3080_00xx -> register space inside chip
+#define hyperram_reg_base_address 0x30800000
+#define hyperram_reg_mask 0x0000ffff
+#define hyperram_reg(num) (*(volatile uint32_t*)(hyperram_reg_base_address + ((2 * num) & hyperram_reg_mask)))
+// 0x3081_00xx -> CSR space for driver / peripheral configuration
+#define hyperram_csr_base_address 0x30810000
+#define hyperram_csr_mask 0x0000ffff
+#define hyperram_csr_latency (*(volatile uint32_t*)(hyperram_csr_base_address + 0x00))
+#define hyperram_csr_tpre_tpost (*(volatile uint32_t*)(hyperram_csr_base_address + 0x04))
+#define hyperram_csr_tcsh (*(volatile uint32_t*)(hyperram_csr_base_address + 0x08))
+#define hyperram_csr_trmax (*(volatile uint32_t*)(hyperram_csr_base_address + 0x0c))
+#define hyperram_csr_status (*(volatile uint32_t*)(hyperram_csr_base_address + 0x10))
+
+
// Generates 32bits wide value out of address, not random
unsigned long generate_value(unsigned long address)
{
@@ -82,9 +103,17 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
+ // reset HyperRAM IP
+ reg_la0_oenb = 0;
+ reg_la0_iena = 0;
+ reg_la0_data = 1;
+ reg_la0_data = 0;
+
// Flag start of the test
reg_mprj_datal = 0xA8000000;
+ // OpenRAM test
+
// Fill memory
for (address = 0; address < OPENRAM_SIZE_DWORDS; address += 32)
{
@@ -103,6 +132,42 @@
}
}
+ // HyperRAM test
+
+ // write register space inside hyperram
+ hyperram_reg(0x2) = 0xa573;
+
+ // write memory, low addresses, default tacc (latency) is 6 cycles (default)
+ hyperram_mem(0x320) = 0xfecdba89;
+ hyperram_mem(0x1234) = 0x13579246;
+
+ // write latency csr
+ // fixed & double latency
+ // tacc = 4 cycles
+ hyperram_csr_latency = 0x34;
+ // read latency csr
+ volatile uint32_t read = hyperram_csr_latency;
+ // if write unsucessful, loop until timeout
+ if (read != 0x34)
+ {
+ reg_mprj_datal = 0xAF000000;
+ return; // instant fail
+ }
+
+ // write memory, high addresses, tacc should be now 4 cycles
+ hyperram_mem(0x123450) = 0x12874562;
+ hyperram_mem(0x7ffff4) = 0x77f77f77;
+
+ // try to read memory and trigger timeout - there's no chip connected
+ read = hyperram_mem(0x135);
+/*
+ read = hyperram_csr_status;
+ if (hyperram_csr_status != 1)
+ {
+ reg_mprj_datal = 0xAF000000;
+ return; // instant fail
+ }
+*/
reg_mprj_datal = 0xAC000000; // pass
}
diff --git a/verilog/dv/wb_openram/wb_openram.hex b/verilog/dv/wb_openram/wb_openram.hex
deleted file mode 100755
index 239832e..0000000
--- a/verilog/dv/wb_openram/wb_openram.hex
+++ /dev/null
@@ -1,54 +0,0 @@
-@00000000
-93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
-13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
-13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
-13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00
-13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
-13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
-13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 85 2D
-93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
-11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
-63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 81 2A
-01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
-A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
-23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
-F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
-00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
-93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
-93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
-23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
-FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
-A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC
-00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14
-F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE
-98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE
-22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87
-17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27
-C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61
-82 80 01 11 22 CE 00 10 23 26 A4 FE 83 27 C4 FE
-93 C7 F7 FF 13 97 37 01 B7 07 F8 1F 7D 8F 83 27
-C4 FE 93 C7 F7 FF 93 96 C7 00 B7 F7 3F 00 F5 8F
-3E 97 83 27 C4 FE 93 C7 F7 FF 93 96 27 00 85 67
-F1 17 F5 8F B9 8F 3E 85 72 44 05 61 82 80 01 11
-06 CE 22 CC 26 CA 00 10 23 24 04 FE B7 07 00 24
-29 67 09 07 98 C3 B7 07 00 26 93 87 07 0A 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 C7 09 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 87 09 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 47 09 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 07 09 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 C7 08 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 87 08 09 67
-13 07 97 80 98 C3 B7 07 00 26 93 87 47 08 09 67
-13 07 97 80 98 C3 B7 07 00 26 05 47 98 C3 01 00
-B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07 00 26
-B1 07 37 07 00 A8 98 C3 23 26 04 FE 25 A0 83 27
-C4 FE 13 F7 F7 3F B7 07 C0 30 BA 97 BE 84 03 25
-C4 FE C5 35 AA 87 9C C0 83 27 C4 FE 93 87 07 02
-23 26 F4 FE 03 27 C4 FE 93 07 F0 0F E3 F9 E7 FC
-23 26 04 FE 25 A8 83 27 C4 FE 13 F7 F7 3F B7 07
-C0 30 BA 97 84 43 03 25 C4 FE 65 35 AA 87 63 89
-F4 00 B7 07 00 26 B1 07 37 07 00 AF 98 C3 1D A0
-83 27 C4 FE 93 87 07 02 23 26 F4 FE 03 27 C4 FE
-93 07 F0 0F E3 F1 E7 FC B7 07 00 26 B1 07 37 07
-00 AC 98 C3 F2 40 62 44 D2 44 05 61 82 80 00 00
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index fb6fd06..bcf21d7 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -23,10 +23,16 @@
`include "gl/user_project_wrapper.v"
`include "../wb_openram_wrapper/src/wb_openram_wrapper.v"
`include "../wb_ram_bus_mux/src/wb_ram_bus_mux.v"
+ `include "../wb_hyperram/src/hyperram.v"
+ `include "../wb_hyperram/src/register_rw.v"
+ `include "../wb_hyperram/src/wb_hyperram.v"
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
`else
`include "user_project_wrapper.v"
`include "../../wb_openram_wrapper/src/wb_openram_wrapper.v"
`include "../../wb_ram_bus_mux/src/wb_ram_bus_mux.v"
+ `include "../../wb_hyperram/src/hyperram.v"
+ `include "../../wb_hyperram/src/register_rw.v"
+ `include "../../wb_hyperram/src/wb_hyperram.v"
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7418f42..b159322 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -100,6 +100,15 @@
wire wbs_or_ack;
wire [31:0] wbs_or_dat_o;
+// Signals connecting HyperRAM wrapper to Bus MUX
+wire wbs_hr_stb;
+wire wbs_hr_cyc;
+wire wbs_hr_we;
+wire [3:0] wbs_hr_sel;
+wire [31:0] wbs_hr_dat_i;
+wire wbs_hr_ack;
+wire [31:0] wbs_hr_dat_o;
+
sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
(
@@ -147,6 +156,48 @@
.ram_dout0 (openram_din0)
);
+
+wire hb_dq_oen;
+
+wb_hyperram hyperram
+(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1), // User area 1 1.8V supply
+ .vssd1 (vssd1), // User area 1 digital ground
+`endif
+
+ .wb_clk_i (wb_clk_i),
+ .wb_rst_i (wb_rst_i),
+
+ .wbs_stb_i (wbs_hr_stb),
+ .wbs_cyc_i (wbs_hr_cyc),
+ .wbs_we_i (wbs_hr_we),
+ .wbs_sel_i (wbs_hr_sel),
+ .wbs_dat_i (wbs_hr_dat_o),
+ .wbs_adr_i (wbs_adr_i),
+ .wbs_ack_o (wbs_hr_ack),
+ .wbs_dat_o (wbs_hr_dat_i),
+
+ .rst_i (la_data_in[0]),
+
+ .hb_rstn_o (io_out[8]),
+ .hb_csn_o (io_out[9]),
+ .hb_clk_o (io_out[10]),
+ .hb_clkn_o (io_out[11]),
+ .hb_rwds_o (io_out[12]),
+ .hb_rwds_oen (io_oeb[12]),
+ .hb_rwds_i (io_in[12]),
+ .hb_dq_o (io_out[20:13]),
+ .hb_dq_oen (hb_dq_oen),
+ .hb_dq_i (io_in[20:13])
+);
+
+assign io_oeb[20:13] = {8{hb_dq_oen}};
+
+// enable outputs for rst, csn, clk, clkn
+assign io_oeb[11:8] = 4'h0;
+
+
wb_ram_bus_mux wb_bus_mux
(
`ifdef USE_POWER_PINS
@@ -165,16 +216,15 @@
.wbs_ufp_adr_i (wbs_adr_i),
.wbs_ufp_ack_o (wbs_ack_o),
.wbs_ufp_dat_o (wbs_dat_o),
-/*
+
// Wishbone HR (Downward Facing Port) - HyperRAM driver
- output wbs_hr_stb_o,
- output wbs_hr_cyc_o,
- output wbs_hr_we_o,
- output [3:0] wbs_hr_sel_o,
- input [31:0] wbs_hr_dat_i,
- input wbs_hr_ack_i,
- output [31:0] wbs_hr_dat_o,
-*/
+ .wbs_hr_stb_o (wbs_hr_stb),
+ .wbs_hr_cyc_o (wbs_hr_cyc),
+ .wbs_hr_we_o (wbs_hr_we),
+ .wbs_hr_sel_o (wbs_hr_sel),
+ .wbs_hr_dat_i (wbs_hr_dat_i),
+ .wbs_hr_ack_i (wbs_hr_ack),
+ .wbs_hr_dat_o (wbs_hr_dat_o),
// Wishbone OR (Downward Facing Port) - OpenRAM
.wbs_or_stb_o (wbs_or_stb),
diff --git a/wb_hyperram b/wb_hyperram
new file mode 160000
index 0000000..3f7b51f
--- /dev/null
+++ b/wb_hyperram
@@ -0,0 +1 @@
+Subproject commit 3f7b51fd6d8a2a68ff8115949e1d3fde66f333f2
