Adjusted configuration for user_project_wrapper. Failing at step 35 / LVS checking.
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json deleted file mode 100644 index a7671cd..0000000 --- a/openlane/user_proj_example/config.json +++ /dev/null
@@ -1,19 +0,0 @@ -{ - "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "counter.clk", - "CLOCK_PERIOD" : "10", - "CLOCK_PORT" : "wb_clk_i", - "DESIGN_IS_CORE" : "0", - "DESIGN_NAME" : "user_proj_example", - "DIE_AREA" : "0 0 900 600", - "DIODE_INSERTION_STRATEGY" : "4", - "FP_PIN_ORDER_CFG" : "pin_order.cfg", - "FP_SIZING" : "absolute", - "GLB_RT_MAXLAYER" : "5", - "GND_NETS" : "vssd1", - "PL_BASIC_PLACEMENT" : "1", - "PL_TARGET_DENSITY" : "0.05", - "RUN_CVC" : "1", - "VDD_NETS" : "vccd1", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"] -}
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl deleted file mode 100755 index 2aa188c..0000000 --- a/openlane/user_proj_example/config.tcl +++ /dev/null
@@ -1,50 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set script_dir [file dirname [file normalize [info script]]] - -set ::env(DESIGN_NAME) user_proj_example - -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "wb_clk_i" -set ::env(CLOCK_NET) "counter.clk" -set ::env(CLOCK_PERIOD) "10" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 900 600" - -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.05 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -set ::env(GLB_RT_MAXLAYER) 5 - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg deleted file mode 100644 index 2fda806..0000000 --- a/openlane/user_proj_example/pin_order.cfg +++ /dev/null
@@ -1,10 +0,0 @@ -#BUS_SORT - -#S -wb_.* -wbs_.* -la_.* -irq.* - -#N -io_.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index c94b7a0..ac1d489 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -35,15 +35,15 @@ $script_dir/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_NET) "mprj.wb_clk_i" set ::env(CLOCK_PERIOD) "10" ## Internal Macros ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ - mprj vccd1 vssd1" + mprj vccd1 vccd2 vdda1 vdda2 vssd1 vssd2 vssa1 vssa2" ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg @@ -51,13 +51,16 @@ ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../wb_openram_wrapper/src/wb_openram_wrapper.v \ + $script_dir/../../openram_testchip/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v" set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" + $script_dir/../../wb_openram_wrapper/lef/wb_openram_wrapper.lef \ + $script_dir/../../openram_testchip/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef" set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" + $script_dir/../../wb_openram_wrapper/lef/wb_openram_wrapper.gds \ + $script_dir/../../openram_testchip/lef/sky130_sram_1kbyte_1rw1r_32x256_8.gds" set ::env(GLB_RT_MAXLAYER) 5
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index a7365ab..a01708d 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,2 @@ -mprj 1175 1690 N +openram_1kB 1000 1000 N +wb_openram_wrapper 2000 1000 N