fixed some more missing references

xschem/sar/dac/carray.sch

diff --git a/xschem/sar/dac/carray.sch b/xschem/sar/dac/carray.sch
index f344216..64c2f4d 100644
--- a/xschem/sar/dac/carray.sch
+++ b/xschem/sar/dac/carray.sch
@@ -59,7 +59,7 @@
 }
 C {xschem_library/devices/iopin.sym} 1870 -190 1 0 {name=p8 lab=n1
 }
-C {adc/unitcap/unitcap.sym} 2600 -220 0 0 {name=xdummy[83:0]
+C {sar/unitcap/unitcap.sym} 2600 -220 0 0 {name=xdummy[83:0]
 spice_ignore="tcleval($dummy_ignore)"
 }
 C {lab_wire.sym} 2610 -320 0 0 {name=l1 sig_type=std_logic lab=top

xschem/sar/latch/logic/inv_lvt.sch

diff --git a/xschem/sar/latch/logic/inv_lvt.sch b/xschem/sar/latch/logic/inv_lvt.sch
new file mode 100644
index 0000000..b0ca8e3
--- /dev/null
+++ b/xschem/sar/latch/logic/inv_lvt.sch
@@ -0,0 +1,59 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 170 -170 170 -110 { lab=out}
+N 170 -50 170 -20 { lab=vss}
+N 170 -20 170 -10 { lab=vss}
+N 80 -200 130 -200 { lab=in}
+N 80 -200 80 -80 { lab=in}
+N 80 -80 130 -80 { lab=in}
+N 170 -140 260 -140 { lab=out}
+N 170 -200 200 -200 { lab=vdd}
+N 170 -80 200 -80 { lab=vss}
+N 40 -140 80 -140 { lab=in}
+N 120 -10 170 -10 { lab=vss}
+N 120 -270 170 -270 { lab=vdd}
+N 170 -270 170 -230 { lab=vdd}
+C {sky130_primitives/nfet_01v8_lvt.sym} 150 -80 0 0 {name=M1
+L=0.4
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_primitives/pfet_01v8_lvt.sym} 150 -200 0 0 {name=M2
+L=0.4
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 200 -200 0 0 {name=l1 sig_type=std_logic lab=vdd
+}
+C {devices/lab_wire.sym} 200 -80 0 0 {name=l2 sig_type=std_logic lab=vss
+}
+C {devices/iopin.sym} 120 -270 2 0 {name=p1 lab=vdd
+}
+C {devices/iopin.sym} 120 -10 2 0 {name=p2 lab=vss
+}
+C {devices/ipin.sym} 40 -140 0 0 {name=p3 lab=in
+}
+C {devices/opin.sym} 260 -140 0 0 {name=p4 lab=out
+}

xschem/sar/latch/logic/inv_lvt.sym

diff --git a/xschem/sar/latch/logic/inv_lvt.sym b/xschem/sar/latch/logic/inv_lvt.sym
new file mode 100644
index 0000000..9010398
--- /dev/null
+++ b/xschem/sar/latch/logic/inv_lvt.sym
@@ -0,0 +1,21 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -150 -20 -130 -20 {}
+B 5 -112.5 -42.5 -107.5 -37.5 {name=vdd dir=inout }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=in dir=in }
+B 5 -72.5 -22.5 -67.5 -17.5 {name=out dir=out }
+B 5 -112.5 -2.5 -107.5 2.5 {name=vss dir=inout }
+A 4 -87.5 -20 2.549509756796392 258.6900675259798 360 {}
+P 4 4 -130 -40 -130 0 -90 -20 -130 -40 {}
+P 4 2 -110 -40 -110 -30 {}
+P 4 2 -110 -0 -110 -10 {}
+P 4 2 -70 -20 -85 -20 {}
+T {@symname} -91.5 -6 0 0 0.3 0.3 {}
+T {@name} -95 -52 0 0 0.2 0.2 {}