| commit | a74e4d888683d5ecbbc5e1efe66e351591195be8 | [log] [tgz] |
|---|---|---|
| author | chrische <christoph-weiser@gmx.de> | Thu Nov 11 20:27:17 2021 +0100 |
| committer | chrische <christoph-weiser@gmx.de> | Thu Nov 11 20:27:17 2021 +0100 |
| tree | 510d94f7ec1634e879d1e03a494b9b8b12c52534 | |
| parent | ee8624e3fbc5f2102f051e8723b93ec7b15071a9 [diff] |
added sar verilog code
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.