)]}'
{
  "commit": "a74e4d888683d5ecbbc5e1efe66e351591195be8",
  "tree": "510d94f7ec1634e879d1e03a494b9b8b12c52534",
  "parents": [
    "ee8624e3fbc5f2102f051e8723b93ec7b15071a9"
  ],
  "author": {
    "name": "chrische",
    "email": "christoph-weiser@gmx.de",
    "time": "Thu Nov 11 20:27:17 2021 +0100"
  },
  "committer": {
    "name": "chrische",
    "email": "christoph-weiser@gmx.de",
    "time": "Thu Nov 11 20:27:17 2021 +0100"
  },
  "message": "added sar verilog code\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "dbe53f54efb6d5b1784654ee6148bc508352c3d7",
      "new_mode": 33261,
      "new_path": "verilog/sarlogic.v"
    }
  ]
}