verilog/pin.cfg

#N
ctlp\[0\]
ctlp\[1\]
ctlp\[7\]
ctlp\[6\]
ctlp\[5\]
ctlp\[4\]
ctlp\[3\]
ctlp\[2\]

#S
ctln\[0\]
ctln\[1\]
ctln\[7\]
ctln\[6\]
ctln\[5\]
ctln\[4\]
ctln\[3\]
ctln\[2\]

#E
trim\[3\]
trim\[2\]
trim\[0\]
trim\[1\]
trim\[4\]
clkc
comp
trimb\[4\]
trimb\[1\]
trimb\[0\]
trimb\[2\]
trimb\[3\]

#W
rstn
clk
en
cal
valid
sample
result.*