| commit | 4179c002b5a6cae9193fdb71b36bea43dca57d11 | [log] [tgz] |
|---|---|---|
| author | chrische <christoph-weiser@gmx.de> | Wed Nov 24 22:55:57 2021 +0100 |
| committer | chrische <christoph-weiser@gmx.de> | Wed Nov 24 22:55:57 2021 +0100 |
| tree | 9f74145965d0ef44e0934f995ede8153f4d3b060 | |
| parent | 6f3164727bb70f928db22526b75e6172093b7d16 [diff] |
general improvements for project startup
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The Schematics are created using xschem, which also serves as the simulation framework. 
The SAR schematic: 
The simulation output can then be viewed in both analog and digital domain.
Digital waveforms displayed using GTKWave 
Analog waveforms displayed using Gnuplot in interactive mode. 