Add files via upload
diff --git a/signoff/user_proj_example/OPENLANE_VERSION b/signoff/user_proj_example/OPENLANE_VERSION
new file mode 100644
index 0000000..ba96224
--- /dev/null
+++ b/signoff/user_proj_example/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane 2021.09.19_20.25.16
diff --git a/signoff/user_proj_example/PDK_SOURCES b/signoff/user_proj_example/PDK_SOURCES
new file mode 100644
index 0000000..22b75cd
--- /dev/null
+++ b/signoff/user_proj_example/PDK_SOURCES
@@ -0,0 +1,4 @@
+-ne skywater-pdk
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv
new file mode 100644
index 0000000..8af7e1e
--- /dev/null
+++ b/signoff/user_proj_example/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h30m23s,0h29m52s,19566.666666666668,0.06,9783.333333333334,7.38,595.85,587,0,0,0,0,0,0,0,0,0,0,-1,32753,5481,0.0,0.0,0.0,0.0,-0.89,0.0,0.0,0.0,0.0,-1.56,8585491.0,1.89,9.81,8.07,6.52,2.23,-1,698,1775,160,1237,0,0,0,557,0,0,0,0,0,0,0,4,37,37,26,130,737,0,867,32.372936225315634,30.89,30,AREA 0,5,50,1,153.6,153.18,0.6,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
new file mode 100644
index 0000000..ba96224
--- /dev/null
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane 2021.09.19_20.25.16
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
new file mode 100644
index 0000000..22b75cd
--- /dev/null
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -0,0 +1,4 @@
+-ne skywater-pdk
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks
+6c05bc48dc88784f9d98b89d6791cdfd91526676
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
new file mode 100644
index 0000000..b07d629
--- /dev/null
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h3m0s,0h2m12s,0.19458281444582815,10.2784,0.09729140722291407,-1,506.09,1,0,0,0,0,0,0,0,0,0,-1,-1,1439077,2421,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,40161.95,1.5,4.14,0.26,0.15,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
