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diff --git a/caravel/verilog/dv/caravel/defs.h b/caravel/verilog/dv/caravel/defs.h
new file mode 100644
index 0000000..a9d27ec
--- /dev/null
+++ b/caravel/verilog/dv/caravel/defs.h
@@ -0,0 +1,216 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_oenb (*(volatile uint32_t*)0x25000010)
+#define reg_la1_oenb (*(volatile uint32_t*)0x25000014)
+#define reg_la2_oenb (*(volatile uint32_t*)0x25000018)
+#define reg_la3_oenb (*(volatile uint32_t*)0x2500001c)
+
+#define reg_la0_iena (*(volatile uint32_t*)0x25000020)
+#define reg_la1_iena (*(volatile uint32_t*)0x25000024)
+#define reg_la2_iena (*(volatile uint32_t*)0x25000028)
+#define reg_la3_iena (*(volatile uint32_t*)0x2500002c)
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_irq (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x2600003c)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x2600004c)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x2600005c)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x2600006c)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x2600007c)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000088)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x2600008c)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x260000a0)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b4)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b8)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0 0x00000001
+#define FLASH_BITBANG_IO1 0x00000002
+#define FLASH_BITBANG_CLK 0x00000010
+#define FLASH_BITBANG_CSB 0x00000020
+#define FLASH_BITBANG_OEB0 0x00000100
+#define FLASH_BITBANG_OEB1 0x00000200
+#define FLASH_ENABLE 0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE 0x01
+#define TIMER_ONESHOT 0x02
+#define TIMER_UPCOUNT 0x04
+#define TIMER_CHAIN 0x08
+#define TIMER_IRQ_ENABLE 0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK 0x00ff
+#define SPI_MASTER_MLB 0x0100
+#define SPI_MASTER_INV_CSB 0x0200
+#define SPI_MASTER_INV_CLK 0x0400
+#define SPI_MASTER_MODE_1 0x0800
+#define SPI_MASTER_STREAM 0x1000
+#define SPI_MASTER_ENABLE 0x2000
+#define SPI_MASTER_IRQ_ENABLE 0x4000
+#define SPI_HOUSEKEEPING_CONN 0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE 0x0001
+#define OUTPUT_DISABLE 0x0002
+#define HOLD_OVERRIDE 0x0004
+#define INPUT_DISABLE 0x0008
+#define MODE_SELECT 0x0010
+#define ANALOG_ENABLE 0x0020
+#define ANALOG_SELECT 0x0040
+#define ANALOG_POLARITY 0x0080
+#define SLOW_SLEW_MODE 0x0100
+#define TRIPPOINT_SEL 0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG 0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL 0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED 0x1802
+#define GPIO_MODE_USER_STD_ANALOG 0x000a
+
+// --------------------------------------------------------
+#endif
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
new file mode 100644
index 0000000..feca129
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ * Caravan GPIO Test
+ *
+ * This is mainly a test of the digital I/O surrounding the analog
+ * pinouts on the caravan chip to make sure that they are connected
+ * properly after the middle GPIO pads and serial loader blocks are
+ * clipped out from the caravel design.
+ *
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+ int i;
+
+ /* Set data out to zero */
+ reg_mprj_datal = 0;
+
+ /* GPIO 14 to 24 have been replaced by analog and should be set */
+ /* to mode output to keep the input from floating. */
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // change the pull up and pull down (checked by the TB)
+ reg_mprj_datal = 0xa0000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_datal = 0x0a000000;
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // read the lower 8 pins, add 1 then output the result
+ // checked by the TB
+ reg_mprj_datal = 0xaa000000;
+
+ while (1) {
+ int x = (reg_mprj_datal & 0x3f80) >> 7;
+ reg_mprj_datal = (x+1) << 25;
+ }
+}
+
diff --git a/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
new file mode 100644
index 0000000..1b32be2
--- /dev/null
+++ b/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -0,0 +1,214 @@
+`default_nettype none
+/*
+ * SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
+ *
+ * StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+
+module caravan_tb;
+
+ reg clock;
+ reg power1;
+ reg power2;
+
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock <= 0;
+ end
+
+ initial begin
+ $dumpfile("caravan.vcd");
+ $dumpvars(0, caravan_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (25) begin
+ repeat (1000) @(posedge clock);
+ $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ wire [37:0] mprj_io; // Most of these are no-connects
+ wire [6:0] checkbits_hi; // Upper 7 valid GPIO bits
+ wire [7:0] checkbits_lo; // Lower 6 valid GPIO bits (read)
+
+ reg [7:0] setbits_lo; // Lower 6 valid GPIO bits (write)
+
+ assign mprj_io[13:7] = setbits_lo;
+ assign checkbits_lo = mprj_io[13:7];
+ assign checkbits_hi = mprj_io[31:25];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire gpio;
+
+ reg RSTB;
+
+ // Transactor
+ initial begin
+ setbits_lo <= {7{1'bz}};
+ wait(checkbits_hi == 7'h50);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h30;
+ wait(checkbits_hi == 7'h05);
+ repeat (500) @(posedge clock);
+ setbits_lo <= 7'h0f;
+ wait(checkbits_hi == 7'h55);
+ repeat (1000) @(posedge clock);
+ setbits_lo <= 7'h00;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h01;
+ repeat (1300) @(posedge clock);
+ setbits_lo <= 7'h03;
+ end
+
+ // Monitor
+ initial begin
+ wait(checkbits_hi == 7'h50); // 1st pull test
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Started");
+ `else
+ $display("Monitor: Test GPIO (RTL) Started");
+ `endif
+ wait(checkbits_lo == 7'h30); // (1st pull test result)
+ $display("Monitor: Check 1 seen");
+ wait(checkbits_hi == 7'h05); // 2nd pull test
+ $display("Monitor: Check 2 seen");
+ wait(checkbits_lo == 7'h0F); // (2nd pull test result)
+ $display("Monitor: Check 3 seen");
+ wait(checkbits_hi == 7'h55); // loopback test
+ $display("Monitor: Check 4 seen");
+ wait(checkbits_lo == 7'h00); // 1st value set
+ $display("Monitor: Check 5 seen");
+ wait(checkbits_hi == 7'h01); // 1st loopback read
+ $display("Monitor: Check 6 seen");
+ wait(checkbits_lo == 7'h01); // 2nd value set
+ $display("Monitor: Check 7 seen");
+ wait(checkbits_hi == 7'h02); // 2nd loopback read
+ $display("Monitor: Check 8 seen");
+ wait(checkbits_lo == 7'h03); // 3rd value set
+ $display("Monitor: Check 9 seen");
+ wait(checkbits_hi == 7'h04); // 3rd loopback read
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
+ end
+
+ initial begin // Power-up
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+
+ always @(mprj_io) begin
+ #1 $display("GPIO state = %b (%d - %d)", mprj_io,
+ checkbits_hi, checkbits_lo);
+ end
+
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("caravan.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
