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diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..49cd280
--- /dev/null
+++ b/verilog/dv/README.md

@@ -0,0 +1,30 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+# DV Tests
+
+Organized into two subdirectories:
+  * caravel: contains tests for both the mangement SoC and an example user project.
+  * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
+
+<pre>
+├── caravel
+│   ├── mgmt_soc
+│   ├── user_proj_example
+└── wb_utests
+</pre>
+

diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
new file mode 100644
index 0000000..a9d27ec
--- /dev/null
+++ b/verilog/dv/caravel/defs.h

@@ -0,0 +1,216 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena  (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_oenb (*(volatile uint32_t*)0x25000010)
+#define reg_la1_oenb (*(volatile uint32_t*)0x25000014)
+#define reg_la2_oenb (*(volatile uint32_t*)0x25000018)
+#define reg_la3_oenb (*(volatile uint32_t*)0x2500001c)
+
+#define reg_la0_iena (*(volatile uint32_t*)0x25000020)
+#define reg_la1_iena (*(volatile uint32_t*)0x25000024)
+#define reg_la2_iena (*(volatile uint32_t*)0x25000028)
+#define reg_la3_iena (*(volatile uint32_t*)0x2500002c)
+
+#define reg_la_sample (*(volatile uint32_t*)0x25000030)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr  (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_irq  (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datal (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000010)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x2600003c)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x2600004c)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x2600005c)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x2600006c)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x2600007c)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000088)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x2600008c)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x260000a0)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b4)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b8)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)         
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0	0x00000001
+#define FLASH_BITBANG_IO1	0x00000002
+#define FLASH_BITBANG_CLK	0x00000010
+#define FLASH_BITBANG_CSB	0x00000020
+#define FLASH_BITBANG_OEB0	0x00000100
+#define FLASH_BITBANG_OEB1	0x00000200
+#define FLASH_ENABLE		0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value  (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data   (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value  (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data   (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE		0x01
+#define TIMER_ONESHOT		0x02
+#define TIMER_UPCOUNT		0x04
+#define TIMER_CHAIN		0x08
+#define TIMER_IRQ_ENABLE	0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data   (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK	0x00ff
+#define SPI_MASTER_MLB		0x0100
+#define SPI_MASTER_INV_CSB	0x0200
+#define SPI_MASTER_INV_CLK	0x0400
+#define SPI_MASTER_MODE_1	0x0800
+#define SPI_MASTER_STREAM	0x1000
+#define SPI_MASTER_ENABLE	0x2000
+#define SPI_MASTER_IRQ_ENABLE	0x4000
+#define SPI_HOUSEKEEPING_CONN	0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good    (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest  (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source    (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE	  0x0001
+#define OUTPUT_DISABLE	  0x0002
+#define HOLD_OVERRIDE	  0x0004
+#define INPUT_DISABLE	  0x0008
+#define MODE_SELECT	  0x0010
+#define ANALOG_ENABLE	  0x0020
+#define ANALOG_SELECT	  0x0040
+#define ANALOG_POLARITY	  0x0080
+#define SLOW_SLEW_MODE	  0x0100
+#define TRIPPOINT_SEL	  0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL    0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP	   0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1809
+#define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   0x1801
+#define GPIO_MODE_MGMT_STD_ANALOG   	   0x000b
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL	   0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN  0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP	   0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT	   0x1808
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL   0x1800
+#define GPIO_MODE_USER_STD_OUT_MONITORED   0x1802
+#define GPIO_MODE_USER_STD_ANALOG   	   0x000a
+
+// --------------------------------------------------------
+#endif

diff --git a/verilog/dv/caravel/mgmt_soc/Makefile b/verilog/dv/caravel/mgmt_soc/Makefile
new file mode 100644
index 0000000..7706531
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/Makefile

@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_mgmt gpio mem uart perf hkspi sysctrl mprj_ctrl pass_thru timer timer2 pll storage qspi caravan irq user_pass_thru
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+		( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all

diff --git a/verilog/dv/caravel/mgmt_soc/caravan/Makefile b/verilog/dv/caravel/mgmt_soc/caravan/Makefile
new file mode 100644
index 0000000..285e337
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/caravan/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = caravan
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/caravan/README b/verilog/dv/caravel/mgmt_soc/caravan/README
new file mode 100644
index 0000000..a39b365
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/caravan/README

@@ -0,0 +1,27 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravan
+basic testbench
+------------------------------------------------
+
+This testbench exercises the basic use of the Caravan analog project
+harness, which is equivalent to the Caravel chip with 11 GPIOs
+removed from the top of the padframe and replaced with straight-through
+connections to pads.
+

diff --git a/verilog/dv/caravel/mgmt_soc/caravan/caravan.c b/verilog/dv/caravel/mgmt_soc/caravan/caravan.c
new file mode 100644
index 0000000..feca129
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/caravan/caravan.c

@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	Caravan GPIO Test
+ *
+ *	This is mainly a test of the digital I/O surrounding the analog
+ *	pinouts on the caravan chip to make sure that they are connected
+ *	properly after the middle GPIO pads and serial loader blocks are
+ *	clipped out from the caravel design.
+ *
+ *	Tests PU and PD on the lower 8 pins while being driven from outside
+ *	Tests Writing to the upper 8 pins
+ *	Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+	int i;
+
+	/* Set data out to zero */
+	reg_mprj_datal = 0;
+
+	/* GPIO 14 to 24 have been replaced by analog and should be set	*/
+	/* to mode output to keep the input from floating.		*/
+	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	/* Lower 8 pins are input and upper 8 pins are output */
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	// change the pull up and pull down (checked by the TB)
+	reg_mprj_datal = 0xa0000000;
+
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	reg_mprj_datal = 0x0a000000;
+
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	// read the lower 8 pins, add 1 then output the result
+	// checked by the TB
+	reg_mprj_datal = 0xaa000000;
+
+	while (1) {
+		int x = (reg_mprj_datal & 0x3f80) >> 7;
+		reg_mprj_datal = (x+1) << 25;
+	}
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
new file mode 100644
index 0000000..1b32be2
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v

@@ -0,0 +1,214 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+
+module caravan_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("caravan.vcd");
+		$dumpvars(0, caravan_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;		// Most of these are no-connects
+	wire [6:0]  checkbits_hi;	// Upper 7 valid GPIO bits
+	wire [7:0]  checkbits_lo;	// Lower 6 valid GPIO bits (read)
+
+	reg  [7:0] setbits_lo;		// Lower 6 valid GPIO bits (write)
+
+	assign mprj_io[13:7] = setbits_lo;
+	assign checkbits_lo = mprj_io[13:7];
+	assign checkbits_hi = mprj_io[31:25];
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	reg RSTB;
+
+	// Transactor
+	initial begin
+		setbits_lo <= {7{1'bz}};
+		wait(checkbits_hi == 7'h50);
+		repeat (500) @(posedge clock);
+		setbits_lo <= 7'h30;
+		wait(checkbits_hi == 7'h05);
+		repeat (500) @(posedge clock);
+		setbits_lo <= 7'h0f;
+		wait(checkbits_hi == 7'h55);
+		repeat (1000) @(posedge clock);
+		setbits_lo <= 7'h00;
+		repeat (1300) @(posedge clock);
+		setbits_lo <= 7'h01;
+		repeat (1300) @(posedge clock);
+		setbits_lo <= 7'h03;
+	end
+
+	// Monitor
+	initial begin
+		wait(checkbits_hi == 7'h50);	// 1st pull test
+		`ifdef GL
+			$display("Monitor: Test GPIO (GL) Started");
+		`else
+			$display("Monitor: Test GPIO (RTL) Started");
+		`endif
+		wait(checkbits_lo == 7'h30);	// (1st pull test result)
+		$display("Monitor: Check 1 seen");
+		wait(checkbits_hi == 7'h05);	// 2nd pull test
+		$display("Monitor: Check 2 seen");
+		wait(checkbits_lo == 7'h0F);	// (2nd pull test result)
+		$display("Monitor: Check 3 seen");
+		wait(checkbits_hi == 7'h55);	// loopback test
+		$display("Monitor: Check 4 seen");
+		wait(checkbits_lo == 7'h00);	// 1st value set
+		$display("Monitor: Check 5 seen");
+		wait(checkbits_hi == 7'h01);	// 1st loopback read
+		$display("Monitor: Check 6 seen");
+		wait(checkbits_lo == 7'h01);	// 2nd value set
+		$display("Monitor: Check 7 seen");
+		wait(checkbits_hi == 7'h02);	// 2nd loopback read
+		$display("Monitor: Check 8 seen");
+		wait(checkbits_lo == 7'h03);	// 3rd value set
+		$display("Monitor: Check 9 seen");
+		wait(checkbits_hi == 7'h04);	// 3rd loopback read
+		`ifdef GL
+			$display("Monitor: Test GPIO (GL) Passed");
+		`else
+			$display("Monitor: Test GPIO (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+		
+
+	always @(mprj_io) begin
+		#1 $display("GPIO state = %b (%d - %d)", mprj_io,
+				checkbits_hi, checkbits_lo);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravan uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("caravan.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
new file mode 100644
index 0000000..7346f4e
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/README b/verilog/dv/caravel/mgmt_soc/gpio/README
new file mode 100644
index 0000000..baadc1f
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/README

@@ -0,0 +1,44 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio testbench
+------------------------------------------------
+
+This testbench exercises the fundamental use of the Caravel
+management SoC to drive the I/O in the user area as general
+purpose I/O on startup.
+
+On startup, all GPIO are configured as input to the management
+region (so as to be high impedence to the external world) and
+decoupled from the user project area.
+
+To configure any GPIO as output, the appropriate memory-mapped
+location for the I/O must be properly configured.  Since the
+I/O configuration is stored in two places, in the SoC, but
+also locally at each I/O pad, the "transfer" bit must be
+applied, which initiates a transfer of the configuration data
+around the padframe.
+
+The testbench takes 16 pins from the user area and checks
+functionality by applying input values on 8 of these pins from
+the testbench verilog, detecting them in the C program, then
+copying the values to the other 8 pins, and detecting those
+values in the testbench verilog.
+
+If any of that does not work, then the testbench will fail.

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
new file mode 100644
index 0000000..73dd397
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c

@@ -0,0 +1,115 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	GPIO Test
+ *		Tests PU and PD on the lower 8 pins while being driven from outside
+ *		Tests Writing to the upper 8 pins
+ *		Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+	int i;
+
+	/* Set data out to zero */
+	reg_mprj_datal = 0;
+
+	/* Lower 8 pins are input and upper 8 pins are output */
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	// change the pull up and pull down (checked by the TB)
+	reg_mprj_datal = 0xa0000000;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	reg_mprj_datal = 0x0b000000;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	// read the lower 8 pins, add 1 then output the result
+	// checked by the TB
+	reg_mprj_datal = 0xab000000;
+
+	while (1){
+		int x = (reg_mprj_datal & 0xff0000) >> 16;
+		reg_mprj_datal = (x+1) << 24;
+	}
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
new file mode 100644
index 0000000..a6bd94d
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v

@@ -0,0 +1,196 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("gpio.vcd");
+		$dumpvars(0, gpio_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [15:0] checkbits;
+	reg  [7:0] checkbits_lo;
+	wire [7:0] checkbits_hi;
+
+	assign mprj_io[23:16] = checkbits_lo;
+	assign checkbits = mprj_io[31:16];
+	assign checkbits_hi = checkbits[15:8];
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	reg RSTB;
+
+	// Transactor
+	initial begin
+		checkbits_lo <= {8{1'bz}};
+		wait(checkbits_hi == 8'hA0);
+		checkbits_lo <= 8'hF0;
+		wait(checkbits_hi == 8'h0B);
+		checkbits_lo <= 8'h0F;
+		wait(checkbits_hi == 8'hAB);
+		checkbits_lo <= 8'h0;
+		repeat (1000) @(posedge clock);
+		checkbits_lo <= 8'h1;
+		repeat (1000) @(posedge clock);
+		checkbits_lo <= 8'h3;
+	end
+
+	// Monitor
+	initial begin
+		wait(checkbits_hi == 8'hA0);
+		wait(checkbits[7:0]  == 8'hF0);
+		wait(checkbits_hi == 8'h0B);
+		wait(checkbits[7:0]  == 8'h0F);
+		wait(checkbits_hi == 8'hAB);
+		wait(checkbits[7:0]  == 8'h00);
+		wait(checkbits_hi == 8'h01);
+		wait(checkbits[7:0]  == 8'h01);
+		wait(checkbits_hi == 8'h02);
+		wait(checkbits[7:0]  == 8'h03);
+		wait(checkbits_hi == 8'h04);
+		`ifdef GL
+			$display("Monitor: Test GPIO (GL) Passed");
+		`else
+			$display("Monitor: Test GPIO (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+		
+
+	always @(checkbits) begin
+		#1 $display("GPIO state = %b (%d - %d)", checkbits,
+				checkbits_hi, checkbits_lo);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("gpio.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile
new file mode 100644
index 0000000..a4ae097
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = gpio_mgmt
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README
new file mode 100644
index 0000000..c8dcd45
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README

@@ -0,0 +1,27 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+gpio_mgmt testbench
+------------------------------------------------
+
+This testbench is the simplest "wake-up call" for the development
+board.  It toggles the single "gpio" pin under exclusive control
+of the management SoC;  first a few times quickly (so it can be
+seen in simulation) then continuously at a slow pulse rate, so it
+will blink the LED on the prototype board.

diff --git a/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c
new file mode 100644
index 0000000..3a3265c
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c

@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	Management SoC GPIO Pin Test
+ *		Tests writing to the GPIO pin.
+ */
+
+void main()
+{
+	int i;
+
+	reg_gpio_data = 0;
+	reg_gpio_ena = 0;
+	reg_gpio_pu = 0;
+	reg_gpio_pd = 0;
+
+	for (i = 0; i < 10; i++) {
+		/* Fast blink for simulation */
+		reg_gpio_data = 1;
+		reg_gpio_data = 0;
+	}
+
+	while (1) {
+		/* Slow blink for demonstration board */
+		for (i = 0; i < 30000; i++) {
+			reg_gpio_data = 1;
+		}
+		for (i = 0; i < 30000; i++) {
+			reg_gpio_data = 0;
+		}
+	}
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v
new file mode 100644
index 0000000..b181dc3
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v

@@ -0,0 +1,200 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module gpio_mgmt_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("gpio_mgmt.vcd");
+		$dumpvars(0, gpio_mgmt_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mgmt GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mgmt GPIO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [15:0] checkbits;
+	reg  [7:0] checkbits_lo;
+	wire [7:0] checkbits_hi;
+
+	assign mprj_io[23:16] = checkbits_lo;
+	assign checkbits = mprj_io[31:16];
+	assign checkbits_hi = checkbits[15:8];
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	reg RSTB;
+
+	// Monitor
+	initial begin
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		$display("Blink.");
+		wait(gpio == 1'b1);
+		wait(gpio == 1'b0);
+		`ifdef GL
+			$display("Monitor: Test Mgmt GPIO (GL) Passed");
+		`else
+			$display("Monitor: Test Mgmt GPIO (RTL) Passed");
+		`endif
+		#2000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+		
+
+	always @(checkbits) begin
+		#1 $display("Mgmt GPIO state = %b (%d - %d)", checkbits,
+				checkbits_hi, checkbits_lo);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("gpio_mgmt.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
new file mode 100644
index 0000000..2eae1ec
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = hkspi
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
new file mode 100644
index 0000000..3bfac32
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c

@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+    // This program is just to keep the processor busy while the
+    // housekeeping SPI is being accessed, to show that the
+    // processor is interrupted only when the reset is applied
+    // through the SPI.
+
+    // Configure I/O:  High 16 bits of user area used for a 16-bit
+    // word to write and be detected by the testbench verilog.
+    // Only serial Tx line is used in this testbench.  It connects
+    // to mprj_io[6].  Since all lines of the chip are input or
+    // high impedence on startup, the I/O has to be configured
+    // for output
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xa0000000;
+
+    // Set clock to 64 kbaud and enable the UART
+    reg_uart_clkdiv = 625;
+    reg_uart_enable = 1;
+
+    // Test message
+    print("\n");
+    print("  ____  _          ____         ____\n");
+    print(" |  _ \\(_) ___ ___/ ___|  ___  / ___|\n");
+    print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
+    print(" |  __/| | (_| (_) |__) | (_) | |___\n");
+    print(" |_|   |_|\\___\\___/____/ \\___/ \\____|\n");
+
+    reg_mprj_datal = 0xab000000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
new file mode 100644
index 0000000..b895381
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v

@@ -0,0 +1,431 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*	
+	StriVe housekeeping SPI testbench.
+*/
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module hkspi_tb;
+	reg clock;
+	reg SDI, CSB, SCK, RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire uart_tx;
+	wire uart_rx;
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	wire SDO;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    // The main testbench is here.  Put the housekeeping SPI into
+    // pass-thru mode and read several bytes from the flash SPI.
+
+    // First define tasks for SPI functions
+
+	task start_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b0;
+		#50;
+	    end
+	endtask
+
+	task end_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b1;
+		#50;
+	    end
+	endtask
+
+	task write_byte;
+	    input [7:0] odata;
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_byte;
+	    output [7:0] idata;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_write_byte
+	    (input [7:0] odata,
+	    output [7:0] idata);
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+	
+	integer i;
+
+    // Now drive the digital signals on the housekeeping SPI
+	reg [7:0] tbdata;
+
+	initial begin
+	    $dumpfile("hkspi.vcd");
+	    $dumpvars(0, hkspi_tb);
+
+	    CSB <= 1'b1;
+	    SCK <= 1'b0;
+	    SDI <= 1'b0;
+	    RSTB <= 1'b0;
+
+	    // Delay, then bring chip out of reset
+	    #1000;
+	    RSTB <= 1'b1;
+	    #2000;
+
+            // First do a normal read from the housekeeping SPI to
+	    // make sure the housekeeping SPI works.
+
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
+
+	    // Toggle external reset
+	    start_csb();
+	    write_byte(8'h80);	// Write stream command
+	    write_byte(8'h0b);	// Address (register 7 = external reset)
+	    write_byte(8'h01);	// Data = 0x01 (apply external reset)
+	    end_csb();
+
+	    start_csb();
+	    write_byte(8'h80);	// Write stream command
+	    write_byte(8'h0b);	// Address (register 7 = external reset)
+	    write_byte(8'h00);	// Data = 0x00 (release external reset)
+	    end_csb();
+
+	    // Read all registers (0 to 18)
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h00);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+
+	    $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
+		if(tbdata !== 8'h04) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
+		if(tbdata !== 8'h56) begin
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
+		if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
+		if(tbdata !== 8'h02) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
+		if(tbdata !== 8'h01) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
+		if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
+		if(tbdata !== 8'hff) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
+		if(tbdata !== 8'hef) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
+		if(tbdata !== 8'hff) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
+		if(tbdata !== 8'h03) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
+		if(tbdata !== 8'h12) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
+		if(tbdata !== 8'h04) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI (RTL) Failed"); $finish; 
+			`endif
+		end
+		
+        end_csb();
+
+		`ifdef GL
+			$display("Monitor: Test HK SPI (GL) Passed");
+		`else
+			$display("Monitor: Test HK SPI (RTL) Passed");
+		`endif
+
+	    #10000;
+ 	    $finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	wire hk_sck;
+	wire hk_csb;
+	wire hk_sdi;
+
+	assign hk_sck = SCK;
+	assign hk_csb = CSB;
+	assign hk_sdi = SDI;
+
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = uart_rx;
+	assign mprj_io[4] = hk_sck;
+	assign mprj_io[3] = hk_csb;
+	assign mprj_io[2] = hk_sdi;
+	assign SDO = mprj_io[1];
+	
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("hkspi.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+		
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/irq/Makefile b/verilog/dv/caravel/mgmt_soc/irq/Makefile
new file mode 100644
index 0000000..4520f98
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/Makefile

@@ -0,0 +1,82 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+PDK_PATH = $(PDK_ROOT)/sky130A
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = irq
+
+all:  ${PATTERN:=.vcd}
+
+ex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+%.elf: %.c sections.lds start.S check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ start.S $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all

diff --git a/verilog/dv/caravel/mgmt_soc/irq/README b/verilog/dv/caravel/mgmt_soc/irq/README
new file mode 100644
index 0000000..99d3cf9
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/README

@@ -0,0 +1,32 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+irq testbench
+------------------------------------------------
+
+This testbench demonstrates how to use the interrupts on the
+picoRV32.  It uses the internal picoRV32 counter to set up an
+interval timer.  At each timer expiration, an interrupt is
+generated, and the assembler code in start.S runs and captures
+data from a routine emulating a Digilent PMOD MIC-3 microphone
+module.  Data are accumulated in a ring buffer reserved in the
+top of memory.  The main loop of the program queries the
+current ring buffer position, reads the data there, and
+displays the value on the GPIO (upper 16 of the lower 32 GPIO
+channels).

diff --git a/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S b/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S
new file mode 100644
index 0000000..e3d1e2d
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S

@@ -0,0 +1,116 @@
+/*
+ *  SPDX-FileCopyrightText: 2015 Clifford Wolf
+ *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ *  Copyright (C) 2015  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+#define regnum_q0   0
+#define regnum_q1   1
+#define regnum_q2   2
+#define regnum_q3   3
+
+#define regnum_x0   0
+#define regnum_x1   1
+#define regnum_x2   2
+#define regnum_x3   3
+#define regnum_x4   4
+#define regnum_x5   5
+#define regnum_x6   6
+#define regnum_x7   7
+#define regnum_x8   8
+#define regnum_x9   9
+#define regnum_x10 10
+#define regnum_x11 11
+#define regnum_x12 12
+#define regnum_x13 13
+#define regnum_x14 14
+#define regnum_x15 15
+#define regnum_x16 16
+#define regnum_x17 17
+#define regnum_x18 18
+#define regnum_x19 19
+#define regnum_x20 20
+#define regnum_x21 21
+#define regnum_x22 22
+#define regnum_x23 23
+#define regnum_x24 24
+#define regnum_x25 25
+#define regnum_x26 26
+#define regnum_x27 27
+#define regnum_x28 28
+#define regnum_x29 29
+#define regnum_x30 30
+#define regnum_x31 31
+
+#define regnum_zero 0
+#define regnum_ra   1
+#define regnum_sp   2
+#define regnum_gp   3
+#define regnum_tp   4
+#define regnum_t0   5
+#define regnum_t1   6
+#define regnum_t2   7
+#define regnum_s0   8
+#define regnum_s1   9
+#define regnum_a0  10
+#define regnum_a1  11
+#define regnum_a2  12
+#define regnum_a3  13
+#define regnum_a4  14
+#define regnum_a5  15
+#define regnum_a6  16
+#define regnum_a7  17
+#define regnum_s2  18
+#define regnum_s3  19
+#define regnum_s4  20
+#define regnum_s5  21
+#define regnum_s6  22
+#define regnum_s7  23
+#define regnum_s8  24
+#define regnum_s9  25
+#define regnum_s10 26
+#define regnum_s11 27
+#define regnum_t3  28
+#define regnum_t4  29
+#define regnum_t5  30
+#define regnum_t6  31
+
+// x8 is s0 and also fp
+#define regnum_fp   8
+
+#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
+.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
+
+#define picorv32_getq_insn(_rd, _qs) \
+r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_setq_insn(_qd, _rs) \
+r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
+
+#define picorv32_retirq_insn() \
+r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
+
+#define picorv32_maskirq_insn(_rd, _rs) \
+r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_waitirq_insn(_rd) \
+r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
+
+#define picorv32_timer_insn(_rd, _rs) \
+r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
+

diff --git a/verilog/dv/caravel/mgmt_soc/irq/irq.c b/verilog/dv/caravel/mgmt_soc/irq/irq.c
new file mode 100644
index 0000000..61dfcdd
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/irq.c

@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// -------------------------------------------------------------------------
+// Test IRQ callback
+// -------------------------------------------------------------------------
+
+uint16_t flag;
+
+void irq_callback()
+{
+    /* If this routine is called, then the test passes the 1st stage */
+    reg_mprj_datah = 0xa;	// Signal end of test 1st stage 
+    reg_mprj_datal = 0x20000;
+    flag = 1;
+    return;
+}
+
+void main()
+{
+    uint16_t data;
+    int i;
+
+    // Configure GPIO upper bits to assert the test code
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* Apply the GPIO configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_datah = 0x5;	// Signal start of test
+    reg_mprj_datal = 0;
+    flag = 0;
+
+    // Loop, waiting for the interrupt to change reg_mprj_datah
+
+    while (flag == 0) {
+        reg_mprj_datal = 0x10000;
+    }
+    reg_mprj_datal = 0x40000;
+    reg_mprj_datah = 0xc;	// Signal end of test
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v b/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v
new file mode 100644
index 0000000..0e03d6d
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v

@@ -0,0 +1,172 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  Caravel - A full example SoC using PicoRV32 in SkyWater sky130
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2021  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module irq_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("irq.vcd");
+		$dumpvars(0, irq_tb);
+		
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (12) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test IRQ (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test IRQ (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [3:0]  status;
+	wire [3:0] checkbits;
+
+	assign checkbits = mprj_io[19:16];
+	assign status = mprj_io[35:32];
+	assign mprj_io[3] = 1'b1;	// Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	reg RSTB;
+
+	// Monitor
+	initial begin
+		wait(status == 4'h5);
+		`ifdef GL
+			$display("Monitor: Test IRQ (GL) Started");
+		`else
+			$display("Monitor: Test IRQ (RTL) Started");
+		`endif
+		wait(status == 4'ha);
+		wait(status == 4'hc);
+		`ifdef GL
+			$display("Monitor: Test IRQ (GL) Passed");
+		`else
+			$display("Monitor: Test IRQ (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;		// Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+               
+	always @(checkbits, status) begin
+		#1 $display("GPIO state = %b (%b)", checkbits, status);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio    (VSS),
+		.vdda     (VDD3V3),
+		.vssa     (VSS),
+		.vccd     (VDD1V8),
+		.vssd     (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1    (VSS),
+		.vssa2    (VSS),
+		.vccd1    (VDD1V8),
+		.vccd2    (VDD1V8),
+		.vssd1    (VSS),
+		.vssd2    (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb   (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("irq.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule

diff --git a/verilog/dv/caravel/mgmt_soc/irq/sections.lds b/verilog/dv/caravel/mgmt_soc/irq/sections.lds
new file mode 100644
index 0000000..c328222
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/sections.lds

@@ -0,0 +1,83 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+/*
+ *-------------------------------------------------------------------------
+ * Note:  This is like the default sections.lds file for Caravel, but moves
+ * the start of SRAM used by the compiler to address 0x80 to make room for
+ * memory used by the firmware routines defined in the local start.S file.
+ *-------------------------------------------------------------------------
+ */
+
+MEMORY {
+	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000080, LENGTH = 0x0380		/* 256 words (1 KB) */ 
+}
+
+SECTIONS {
+	/* The program code and other data goes into FLASH */
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)	/* .text sections (code) */
+		*(.text*)	/* .text* sections (code) */
+		*(.rodata)	/* .rodata sections (constants, strings, etc.) */
+		*(.rodata*)	/* .rodata* sections (constants, strings, etc.) */
+		*(.srodata)	/* .srodata sections (constants, strings, etc.) */
+		*(.srodata*)	/* .srodata*sections (constants, strings, etc.) */
+		. = ALIGN(4);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+	} >FLASH
+
+	/* Initialized data section */
+	.data : AT ( _sidata )
+	{
+		. = ALIGN(4);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(4);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(4);
+		_edata = .;
+	} >RAM
+
+	/* Uninitialized data section */
+	.bss :
+	{
+		. = ALIGN(4);
+		_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(.sbss)
+		*(.sbss*)
+		*(COMMON)
+
+		. = ALIGN(4);
+		_ebss = .;
+	} >RAM
+
+	/* Define the start of the heap */
+	.heap :
+	{
+		. = ALIGN(4);
+		_heap_start = .;
+	} >RAM
+}

diff --git a/verilog/dv/caravel/mgmt_soc/irq/start.S b/verilog/dv/caravel/mgmt_soc/irq/start.S
new file mode 100644
index 0000000..7c1c8a5
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/irq/start.S

@@ -0,0 +1,195 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*-----------------------------------------------*/
+/* Start code that enables and handles an IRQ 	 */
+/*-----------------------------------------------*/
+
+#undef ENABLE_FASTIRQ
+
+#include "custom_ops.S"
+
+.section .text
+.global irq
+
+reset_vec:
+	j start
+
+/* Interrupt handler @ 0x10000004 */
+/* Requires defining a routine called irq_callback in the C code */
+
+.balign 4
+irq_vec:
+        sw gp,   0*4+0x10(zero)
+        sw t0,   1*4+0x10(zero)
+        sw t1,   2*4+0x10(zero)
+        sw t2,   3*4+0x10(zero)
+        sw t4,   4*4+0x10(zero)
+        sw t5,   5*4+0x10(zero)
+
+	call irq_callback
+
+        lw gp,   0*4+0x10(zero)
+        lw t0,   1*4+0x10(zero)
+        lw t1,   2*4+0x10(zero)
+        lw t2,   3*4+0x10(zero)
+        lw t4,   4*4+0x10(zero)
+        lw t5,   5*4+0x10(zero)
+
+        picorv32_retirq_insn()
+
+irq_regs:
+	.fill 32,8
+
+
+/* Main program */
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# Write these instructions to memory location zero and following:
+# lui t4, 0x10000	= 10000eb7
+# addi t4, t4, 4	= 0e91
+# jalr t4, 0		= 000e80e7
+#
+# These three instructions jump to 0x10000004, which is the location
+# of the interrupt handler.  For a fast interrupt handler, the whole
+# handler should be moved into SRAM.
+
+li  t4, 0x10000eb7
+sw  t4, 0(zero)
+li  t4, 0x80e70e91
+sw  t4, 4(zero)
+li  t4, 0x000e
+sw  t4, 8(zero)
+
+# Enable the timer IRQ only
+li   t4, 0xfff0
+picorv32_maskirq_insn(t4, t4)
+
+# Set the picorv32 32-bit counter/timer to trigger one interrupt.
+
+li t4, 0x1200
+picorv32_timer_insn(t4, t4)
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li   t0, 0x02000000
+
+# Set CS high, IO0 is output
+li   t1, 0x120
+sh   t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb   zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li   t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb   t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+beqz a1, flashio_worker_L3
+li   t5, 8
+lbu  t2, 0(a0)
+flashio_worker_L2:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+lbu  t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or   t2, t2, t4
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L2
+sb   t2, 0(a0)
+addi a0, a0, 1
+addi a1, a1, -1
+j    flashio_worker_L1
+flashio_worker_L3:
+
+# Back to MEMIO mode
+li   t1, 0x80
+sb   t1, 3(t0)
+
+ret
+flashio_worker_end:
+

diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
new file mode 100644
index 0000000..7ea6ed8
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
new file mode 100644
index 0000000..a3b6fcc
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c

@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Memory Test
+	It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[10];
+unsigned short shorts[10];
+unsigned char bytes[10];
+
+void main()
+{
+    int i;
+
+    /* Upper 16 user area pins are configured to be GPIO output */
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // start test
+    reg_mprj_datal = 0xA0400000;
+
+    // Test Word R/W
+    for (i=0; i<10; i++)
+	ints[i] = i*5000 + 10000;
+	
+    for (i=0; i<10; i++)
+	if ((i*5000+10000) != ints[i])
+	    reg_mprj_datal = 0xAB400000;
+
+    reg_mprj_datal = 0xAB410000;
+	
+    // Test Half Word R/W
+    reg_mprj_datal = 0xA0200000;
+    for (i=0; i<10; i++)
+	shorts[i] = i*500 + 100;
+	
+    for(i=0; i<10; i++)
+	if((i*500+100) != shorts[i])
+	    reg_mprj_datal = 0xAB200000;
+
+    reg_mprj_datal = 0xAB210000;
+
+    // Test byte R/W
+    reg_mprj_datal = 0xA0100000;
+    for(i=0; i<10; i++)
+	bytes[i] = i*5 + 10;
+	
+    for(i=0; i<10; i++)
+	if((i*5+10) != bytes[i])
+	    reg_mprj_datal = 0xAB100000;
+
+    reg_mprj_datal = 0xAB110000;
+}
\ No newline at end of file

diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
new file mode 100644
index 0000000..4aa244a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v

@@ -0,0 +1,203 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mem_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+        wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	assign checkbits = mprj_io[31:16];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("mem.vcd");
+		$dumpvars(0, mem_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge clock);
+			//$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test MEM (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test MEM (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		if(checkbits == 16'hA040) begin
+			$display("Mem Test (word rw) started");
+		end
+		else if(checkbits == 16'hAB40) begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [word rw] failed");
+			`endif
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(checkbits == 16'hAB41) begin
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [word rw]  passed");
+			`endif
+		end
+		else if(checkbits == 16'hA020) begin
+			$display("Mem Test (short rw) started");
+		end
+		else if(checkbits == 16'hAB20) begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [short rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [short rw] failed");
+			`endif
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(checkbits == 16'hAB21) begin
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [short rw]  passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [short rw]  passed");
+			`endif
+		end
+		else if(checkbits == 16'hA010) begin
+			$display("Mem Test (byte rw) started");
+		end
+		else if(checkbits == 16'hAB10) begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [byte rw] failed");
+			`else
+				$display("Monitor: Test MEM (RTL) [byte rw] failed");
+			`endif
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(checkbits == 16'hAB11) begin
+			`ifdef GL
+				$display("Monitor: Test MEM (GL) [byte rw] passed");
+			`else
+				$display("Monitor: Test MEM (RTL) [byte rw] passed");
+			`endif
+			$finish;
+		end
+
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mem.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
new file mode 100644
index 0000000..a27ef40
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
new file mode 100644
index 0000000..1d7a140
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c

@@ -0,0 +1,108 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	User Project IO Control Test
+ */
+
+void main()
+{
+    /* All GPIO pins are configured to be output	*/
+    /* The lower 28 bits are connected to the user	*/
+    /* project to output the counter result, and the	*/
+    /* upper 4 bits are connected to the management	*/
+    /* SoC to apply values that can be flagged by the	*/
+    /* testbench for specific benchmark tests.		*/
+
+    /* GPIOs 31 to 16 are connected to the management SoC */
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* GPIOs 27 to 0 are connected to the user area */
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_6  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    // reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_datal = 0;
+
+    // start test
+    reg_mprj_datal = 0x50000000;
+
+    // Write to IO Control
+    reg_mprj_io_0 = 0x004F;
+    if (reg_mprj_io_0 != 0x004F)
+	reg_mprj_datal = 0x60000000;
+     else
+	reg_mprj_datal = 0x70000000;
+
+    // Write to IO Control 
+    reg_mprj_io_1 = 0x005F;
+    if (reg_mprj_io_1 != 0x005F)
+	reg_mprj_datal = 0x80000000;
+    else
+	reg_mprj_datal = 0x90000000;
+
+    // Write to IO Control
+    reg_mprj_io_2 = 0x006F;
+    if (reg_mprj_io_2 != 0x006F)
+	reg_mprj_datal = 0xA0000000;
+    else
+	reg_mprj_datal = 0xb0000000;
+
+    // Write to IO Control (NOTE:  Only 13 bits are valid)
+    reg_mprj_io_3 = 0xF0F5;
+    if (reg_mprj_io_3 != 0x10F5)
+	reg_mprj_datal = 0xc0000000;
+    else
+	reg_mprj_datal = 0xd0000000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..6ddfca3
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v

@@ -0,0 +1,176 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module mprj_ctrl_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] user_io;
+	wire SDO;
+
+	wire [3:0] checkbits;
+
+	assign checkbits = user_io[31:28];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("mprj_ctrl.vcd");
+		$dumpvars(0, mprj_ctrl_tb);
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test User Project (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test User Project (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	always @(checkbits) begin
+		if(checkbits == 4'h5) begin
+			$display("User Project control Test started");
+		end else if(checkbits == 4'h6) begin
+			$display("%c[1;31m",27);
+			$display("Monitor: IO control R/W failed (check 6)");
+			$display("%c[0m",27);
+			$finish;
+		end else if(checkbits == 4'h7) begin
+			$display("Monitor: IO control R/W passed (check 7)");
+		end else if(checkbits == 4'h8) begin
+            		$display("%c[1;31m",27);
+			$display("Monitor: power control R/W failed (check 8)");
+			$display("%c[0m",27);
+			$finish;
+        	end else if(checkbits == 4'h9) begin
+			$display("Monitor: power control R/W passed (check 9)");
+		end else if(checkbits == 4'ha) begin
+            		$display("%c[1;31m",27);
+			$display("Monitor: power control R/W failed (check 10)");
+			$display("%c[0m",27);
+			$finish;
+        	end else if(checkbits == 4'hb) begin
+			$display("Monitor: power control R/W passed (check 11)");
+		end else if(checkbits == 4'hc) begin
+            		$display("%c[1;31m",27);
+			$display("Monitor: power control R/W failed (check 12)");
+			$display("%c[0m",27);
+			$finish;
+        	end else if(checkbits == 4'hd) begin
+
+			$display("Monitor: power control R/W passed (check 13)");
+			`ifdef GL
+            	$display("Monitor: User Project control (GL) test passed.");
+			`else
+			    $display("Monitor: User Project control (RTL) test passed.");
+			`endif
+            $finish;
+        	end			
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(gpio) begin
+		#1 $display("GPIO state = %b ", gpio);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	assign user_io[3] = 1'b1;
+	
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	   (clock),
+		.gpio      (gpio),
+		.mprj_io   (user_io),
+		.flash_csb (flash_csb),
+		.flash_clk (flash_clk),
+		.flash_io0 (flash_io0),
+		.flash_io1 (flash_io1),
+		.resetb	   (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("mprj_ctrl.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
new file mode 100644
index 0000000..59ee63c
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pass_thru
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c
new file mode 100644
index 0000000..33a981d
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+    // This program is just to keep the processor busy while the
+    // housekeeping SPI is being accessed. to show that the
+    // processor is halted while the SPI is accessing the
+    // flash SPI in pass-through mode.
+
+    // Configure I/O:  High 16 bits of user area used for a 16-bit
+    // word to write and be detected by the testbench verilog.
+    // Only serial Tx line is used in this testbench.  It connects
+    // to mprj_io[6].  Since all lines of the chip are input or
+    // high impedence on startup, the I/O has to be configured
+    // for output
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xa0000000;
+
+    // Set clock to 64 kbaud and enable the UART
+    reg_uart_clkdiv = 625;
+    reg_uart_enable = 1;
+
+    // Test in progress
+    reg_mprj_datal = 0xa5000000;
+
+    // Test message
+    print("Test message\n");
+
+    // End test
+    reg_mprj_datal = 0xab000000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
new file mode 100644
index 0000000..4ab65de
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v

@@ -0,0 +1,351 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*	
+ *	StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module pass_thru_tb;
+	reg clock;
+	reg SDI, CSB, SCK, RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire uart_tx;
+	wire uart_rx;
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	wire SDO;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    // The main testbench is here.  Put the housekeeping SPI into
+    // pass-thru mode and read several bytes from the flash SPI.
+
+    // First define tasks for SPI functions
+
+	task start_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b0;
+		#50;
+	    end
+	endtask
+
+	task end_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b1;
+		#50;
+	    end
+	endtask
+
+	task write_byte;
+	    input [7:0] odata;
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_byte;
+	    output [7:0] idata;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_write_byte
+	    (input [7:0] odata,
+	    output [7:0] idata);
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+	
+	integer i;
+
+    // Now drive the digital signals on the housekeeping SPI
+	reg [7:0] tbdata;
+
+	initial begin
+	    $dumpfile("pass_thru.vcd");
+	    $dumpvars(0, pass_thru_tb);
+
+	    CSB <= 1'b1;
+	    SCK <= 1'b0;
+	    SDI <= 1'b0;
+	    RSTB <= 1'b0;
+
+	    #2000;
+
+	    RSTB <= 1'b1;
+
+	    // Wait on start of program execution
+	    wait(checkbits == 16'hA000);
+
+            // First do a normal read from the housekeeping SPI to
+	    // make sure the housekeeping SPI works.
+
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+	    // Now write a command directly to the SPI flash.
+	    start_csb();
+	    write_byte(8'hc4);	// Pass-thru mode
+	    write_byte(8'h03);	// Command 03 (read values w/3-byte address
+	    write_byte(8'h00);	// Address is next three bytes (0x000000)
+	    write_byte(8'h00);
+	    write_byte(8'h00);
+
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+	    if(tbdata !== 8'h01) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+	    end_csb();
+
+	    // Wait for processor to restart
+	    wait(checkbits == 16'hA000);
+
+	    // Read product ID register again
+
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+		`ifdef GL
+	    	$display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+		`else
+			$display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+		`endif
+		
+	    #10000;
+ 	    $finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	wire hk_sck;
+	wire hk_csb;
+	wire hk_sdi;
+
+	assign hk_sck = SCK;
+	assign hk_csb = CSB;
+	assign hk_sdi = SDI;
+
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = uart_rx;
+	assign mprj_io[4] = hk_sck;
+	assign mprj_io[3] = hk_csb;
+	assign mprj_io[2] = hk_sdi;
+	assign SDO = mprj_io[1];
+	
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("pass_thru.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+		
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
new file mode 100644
index 0000000..e96935a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = perf
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf.c b/verilog/dv/caravel/mgmt_soc/perf/perf.c
new file mode 100644
index 0000000..5a17ba2
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf.c

@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Performance Test
+	It uses GPIO to flag the success or failure of the test
+*/
+unsigned int ints[50];
+unsigned short shorts[50];
+unsigned char bytes[50];
+
+int main()
+{
+    int i;
+    int sum = 0;
+
+    /* Upper 16 user area pins are configured to be GPIO output */
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_datal = 0;
+
+    // start test
+    reg_mprj_datal = 0xA0000000;
+	
+    for (i=0; i<100; i++)
+        sum += (sum + i);
+    
+    reg_mprj_datal = 0xAB000000;
+    
+    return sum;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
new file mode 100644
index 0000000..25798ec
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v

@@ -0,0 +1,159 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module perf_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	assign checkbits = mprj_io[31:16];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	reg [31:0] kcycles;
+
+	initial begin
+		$dumpfile("perf.vcd");
+		$dumpvars(0, perf_tb);
+
+		kcycles = 0;
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (150) begin
+			repeat (1000) @(posedge clock);
+			//$display("+1000 cycles");
+			kcycles <= kcycles + 1;
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Performance (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Performance (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		//#1 $display("GPIO state = %X ", gpio);
+		if(checkbits == 16'hA000) begin
+			kcycles = 0;
+			$display("Performance Test started");
+		end
+		else if(checkbits == 16'hAB00) begin
+			//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
+			`ifdef GL
+				$display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+			`else
+				$display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+			`endif
+			$finish;
+		end
+	end
+	
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("perf.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
new file mode 100644
index 0000000..965ce0a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile

@@ -0,0 +1,79 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = pll
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll.c b/verilog/dv/caravel/mgmt_soc/pll/pll.c
new file mode 100644
index 0000000..81a1fc6
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll.c

@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	PLL Test (self-switching)
+ *	- Enables SPI master
+ *	- Uses SPI master to internally access the housekeeping SPI
+ *      - Switches PLL bypass
+ *	- Changes PLL divider
+ *
+ * 	Tesbench mostly copied from sysctrl
+ */
+void main()
+{
+    int i;
+
+    reg_mprj_datal = 0;
+
+    // Configure upper 16 bits of user GPIO for generating testbench
+    // checkpoints.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xA0400000;
+
+    // Enable SPI master
+    // SPI master configuration bits:
+    // bits 7-0:	Clock prescaler value (default 2)
+    // bit  8:		MSB/LSB first (0 = MSB first, 1 = LSB first)
+    // bit  9:		CSB sense (0 = inverted, 1 = noninverted)
+    // bit 10:		SCK sense (0 = noninverted, 1 = inverted)
+    // bit 11:		mode (0 = read/write opposite edges, 1 = same edges)
+    // bit 12:		stream (1 = CSB ends transmission)
+    // bit 13:		enable (1 = enabled)
+    // bit 14:		IRQ enable (1 = enabled)
+    // bit 15:		Connect to housekeeping SPI (1 = connected)
+
+    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+					// connect to housekeeping SPI
+
+    // Apply stream read (0x40 + 0x03) and read back one byte 
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
+    reg_spimaster_data = 0x08;		// Write 0x18 (start address)
+    reg_spimaster_data = 0x01;		// Write 0x01 to PLL enable, no DCO mode
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
+    reg_spimaster_data = 0x11;		// Write 0x11 (start address)
+    reg_spimaster_data = 0x03;		// Write 0x03 to PLL output divider
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
+    reg_spimaster_data = 0x09;		// Write 0x09 (start address)
+    reg_spimaster_data = 0x00;		// Write 0x00 to clock from PLL (no bypass)
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+
+    // Write checkpoint
+    reg_mprj_datal = 0xA0410000;
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
+    reg_spimaster_data = 0x12;		// Write 0x12 (start address)
+    reg_spimaster_data = 0x03;		// Write 0x03 to feedback divider (was 0x04)
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+
+    // Write checkpoint
+    reg_mprj_datal = 0xA0420000;
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x80;		// Write 0x80 (write mode)
+    reg_spimaster_data = 0x11;		// Write 0x11 (start address)
+    reg_spimaster_data = 0x04;		// Write 0x04 to PLL output divider
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+
+    reg_spimaster_config = 0x2102;	// Release housekeeping SPI
+
+    // End test
+    reg_mprj_datal = 0xA0900000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
new file mode 100644
index 0000000..5c037b0
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v

@@ -0,0 +1,158 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module pll_tb;
+	reg clock;
+	reg power1;
+	reg power2;
+	reg RSTB;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [7:0] spivalue;
+	wire [37:0] mprj_io;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire SDO;
+
+	assign checkbits = mprj_io[31:16];
+	assign spivalue  = mprj_io[15:8];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("pll.vcd");
+		$dumpvars(0, pll_tb);
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test PLL (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	// Monitor
+	initial begin
+	    wait(checkbits == 16'hA040);
+		
+		$display("Monitor: Test PLL (RTL) Started");
+		
+	    wait(checkbits == 16'hA041);
+            // $display("   SPI value = 0x%x (should be 0x04)", spivalue);
+            // if(spivalue !== 32'h04) begin
+            //     $display("Monitor: Test PLL (RTL) Failed");
+            //     $finish;
+            // end
+	    wait(checkbits == 16'hA042);
+            // $display("   SPI value = 0x%x (should be 0x56)", spivalue);
+            // if(spivalue !== 32'h56) begin
+            //     $display("Monitor: Test PLL (RTL) Failed");
+            //     $finish;
+            // end
+
+	    wait(checkbits == 16'hA090);
+
+		$display("Monitor: Test PLL (RTL) Passed");
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		#1 $display("GPIO state = %b ", checkbits);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("pll.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/qspi/Makefile b/verilog/dv/caravel/mgmt_soc/qspi/Makefile
new file mode 100644
index 0000000..d94dd33
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/qspi/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = qspi
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/qspi/README b/verilog/dv/caravel/mgmt_soc/qspi/README
new file mode 100644
index 0000000..4b3644a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/qspi/README

@@ -0,0 +1,28 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+------------------------------------------------
+Caravel
+qspi testbench
+------------------------------------------------
+
+This testbench is mainly a copy of the gpio testbench and uses the
+same checks for pass/fail status.  The difference is that the startup
+C code puts the SPI flash into QSPI/DDR/CRM modes for fastest access
+and enables the GPIO channels 36 and 37 to work as the flash IO2 and
+IO3 channels.  If the channel and spimemio setup works correctly,
+then the testbench simulation will pass.

diff --git a/verilog/dv/caravel/mgmt_soc/qspi/qspi.c b/verilog/dv/caravel/mgmt_soc/qspi/qspi.c
new file mode 100644
index 0000000..597e45f
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/qspi/qspi.c

@@ -0,0 +1,132 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	GPIO Test
+ *		Tests PU and PD on the lower 8 pins while being driven from outside
+ *		Tests Writing to the upper 8 pins
+ *		Tests reading from the lower 8 pins
+ */
+
+void main()
+{
+	int i;
+
+	/* Set SPI flash latency to 8 for use with the spiflash.v
+	 * module (note that spiflash.v does not have configuration
+	 * registers emulated, so the external flash cannot be
+	 * changed from its default of 8).
+	 */
+
+	/* Set data out to zero */
+	reg_mprj_datal = 0;
+
+	/* Lower 8 pins are input and upper 8 pins are output */
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Now the flash SPI controller can be put in qspi/ddr/crm mode */
+	/* First run DSPI + CRM */
+	reg_spictrl = 0x80580000;	// DSPI + CRM
+	
+
+	// change the pull up and pull down (checked by the TB)
+	reg_mprj_datal = 0xa0000000;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Now run QSPI + CRM */
+	reg_spictrl = 0x80380000;	// QSPI + CRM
+
+	reg_mprj_datal = 0x0b000000;
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Now run QSPI + DDR + CRM */
+	reg_spictrl = 0x80780000;	// QSPI + DDR + CRM
+
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	// read the lower 8 pins, add 1 then output the result
+	// checked by the TB
+	reg_mprj_datal = 0xab000000;
+
+	while (1){
+		int x = (reg_mprj_datal & 0xff0000) >> 16;
+		reg_mprj_datal = (x+1) << 24;
+	}
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
new file mode 100644
index 0000000..d8683b9
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v

@@ -0,0 +1,205 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module qspi_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("qspi.vcd");
+		$dumpvars(0, qspi_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [35:0] mprj_io;	// Most of these are no-connects
+	wire [15:0] checkbits;
+	reg  [7:0] checkbits_lo;
+	wire [7:0] checkbits_hi;
+
+	assign mprj_io[23:16] = checkbits_lo;
+	assign checkbits = mprj_io[31:16];
+	assign checkbits_hi = checkbits[15:8];
+	assign mprj_io[3] = 1'b1;       // Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+	wire gpio;
+
+	reg RSTB;
+
+	// Transactor
+	initial begin
+		checkbits_lo <= {8{1'bz}};
+		wait(checkbits_hi == 8'hA0);
+		checkbits_lo <= 8'hF0;
+		wait(checkbits_hi == 8'h0B);
+		checkbits_lo <= 8'h0F;
+		wait(checkbits_hi == 8'hAB);
+		checkbits_lo <= 8'h0;
+		repeat (1000) @(posedge clock);
+		checkbits_lo <= 8'h1;
+		repeat (1000) @(posedge clock);
+		checkbits_lo <= 8'h3;
+	end
+
+	// Monitor
+	initial begin
+		wait(checkbits_hi == 8'hA0);
+		`ifdef GL
+			$display("Monitor: Test QSPI (GL) Started");
+		`else
+			$display("Monitor: Test QSPI (RTL) Started");
+		`endif
+		wait(checkbits[7:0]  == 8'hF0);
+		wait(checkbits_hi == 8'h0B);
+		wait(checkbits[7:0]  == 8'h0F);
+		wait(checkbits_hi == 8'hAB);
+		wait(checkbits[7:0]  == 8'h00);
+		wait(checkbits_hi == 8'h01);
+		wait(checkbits[7:0]  == 8'h01);
+		wait(checkbits_hi == 8'h02);
+		wait(checkbits[7:0]  == 8'h03);
+		wait(checkbits_hi == 8'h04);
+		`ifdef GL
+			$display("Monitor: Test QSPI (GL) Passed");
+		`else
+			$display("Monitor: Test QSPI (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+		
+
+	always @(checkbits) begin
+		#1 $display("GPIO state = %b (%d - %d)", checkbits,
+				checkbits_hi, checkbits_lo);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+	// flash_io2 = mgmt_gpio_io[36]		    (inout)
+	// flash_io3 = mgmt_gpio_io[37]		    (inout)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  ({flash_io3, flash_io2, mprj_io}),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("qspi.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(flash_io2),
+		.io3(flash_io3)
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile
new file mode 100644
index 0000000..d0657a3
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage.c b/verilog/dv/caravel/mgmt_soc/storage/storage.c
new file mode 100644
index 0000000..55fdd98
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage.c

@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+	Storage area Test
+	It uses GPIO to flag the success or failure of the test
+*/
+
+void main()
+{
+    int i;
+    volatile uint32_t* ram_addr; 
+    /* Upper 16 user area pins are configured to be GPIO output */
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // start test
+    reg_mprj_datal = 0xA0400000;
+
+    // Test Management R/W block0
+    for (i=0; i<10; i++){
+        ram_addr = &reg_rw_block0 + i;
+        *ram_addr = i*5000 + 10000;
+    }
+	
+    for (i=0; i<10; i++){
+        ram_addr = &reg_rw_block0 + i;
+        if ((i*5000+10000) != *ram_addr) 
+	    reg_mprj_datal = 0xAB400000;
+    }
+	
+    reg_mprj_datal = 0xAB410000;
+	
+    // Test Management R/W block1
+    reg_mprj_datal = 0xA0200000;
+    for (i=0; i<10; i++){
+        ram_addr = &reg_rw_block1 + i;
+        *ram_addr = i*5000 + 10000;
+    }
+	
+    for (i=0; i<10; i++){
+        ram_addr = &reg_rw_block1 + i;
+        if ((i*5000+10000) != *ram_addr) 
+	    reg_mprj_datal = 0xAB200000;
+    }
+    
+    reg_mprj_datal = 0xAB210000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
new file mode 100644
index 0000000..0adee87
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v

@@ -0,0 +1,190 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module storage_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+    wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	assign checkbits = mprj_io[31:16];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("storage.vcd");
+		$dumpvars(0, storage_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge clock);
+			//$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Storage (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Storage (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		if(checkbits == 16'hA040) begin
+			`ifdef GL
+				$display("Mem Test storage MGMT block0 (GL) [word rw] started");
+			`else
+				$display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+			`endif
+		end
+		else if(checkbits == 16'hAB40) begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+			`endif
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(checkbits == 16'hAB41) begin
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block0 (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test storage MGMT block0 (RTL) [word rw]  passed");
+			`endif
+		end
+		else if(checkbits == 16'hA020) begin
+			`ifdef GL
+				$display("Mem Test storage MGMT block1 (GL) [word rw] started");
+			`else
+				$display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+			`endif
+		end
+		else if(checkbits == 16'hAB20) begin
+			$display("%c[1;31m",27);
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+			`else
+				$display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+			`endif
+			$display("%c[0m",27);
+			$finish;
+		end
+		else if(checkbits == 16'hAB21) begin
+			`ifdef GL
+				$display("Monitor: Test storage MGMT block1 (GL) [word rw]  passed");
+			`else
+				$display("Monitor: Test storage MGMT block1 (RTL) [word rw]  passed");
+			`endif
+            $finish;
+		end
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VSS = 1'b0;
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("storage.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
new file mode 100644
index 0000000..0566b44
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = sysctrl
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
new file mode 100644
index 0000000..0f5d56d
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c

@@ -0,0 +1,165 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	System Control Test
+ *	- Enables SPI master
+ *	- Uses SPI master to internally access the housekeeping SPI
+ *      - Reads default value of SPI-Controlled registers
+ *      - Flags failure/success using mprj_io
+ */
+void main()
+{
+    int i;
+    uint32_t value;
+
+    reg_mprj_datal = 0;
+
+    // Configure upper 16 bits of user GPIO for generating testbench
+    // checkpoints.
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Configure next 8 bits for writing the SPI value read on GPIO
+    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xA0400000;
+
+    // Enable SPI master
+    // SPI master configuration bits:
+    // bits 7-0:	Clock prescaler value (default 2)
+    // bit  8:		MSB/LSB first (0 = MSB first, 1 = LSB first)
+    // bit  9:		CSB sense (0 = inverted, 1 = noninverted)
+    // bit 10:		SCK sense (0 = noninverted, 1 = inverted)
+    // bit 11:		mode (0 = read/write opposite edges, 1 = same edges)
+    // bit 12:		stream (1 = CSB ends transmission)
+    // bit 13:		enable (1 = enabled)
+    // bit 14:		IRQ enable (1 = enabled)
+    // bit 15:		Connect to housekeeping SPI (1 = connected)
+
+    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+					// connect to housekeeping SPI
+
+    // Apply stream read (0x40 + 0x03) and read back one byte 
+
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
+    reg_spimaster_data = 0x01;		// Write 0x01 (start address)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0410000 | (value << 8);	// Mfgr ID (high)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0420000 | (value << 8);	// Mfgr ID (low)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0430000 | (value << 8);	// Prod ID
+
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
+    reg_spimaster_data = 0x08;		// Write 0x08 (start address)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0440000 | (value << 8);	// PLL enable
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0450000 | (value << 8);	// PLL bypass
+
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+    reg_spimaster_config = 0xb002;	// Apply stream mode
+    reg_spimaster_data = 0x40;		// Write 0x40 (read mode)
+    reg_spimaster_data = 0x0d;		// Write 0x0d (start address)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0460000 | (value << 8);	// PLL trim (2 high bits)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0470000 | (value << 8);	// PLL trim (2nd byte)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0480000 | (value << 8);	// PLL trim (3rd byte)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA0490000 | (value << 8);	// PLL trim (low byte)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA04a0000 | (value << 8);	// PLL select (3 lowest bits)
+
+    reg_spimaster_data = 0x00;		// Write 0x00 for read
+    value = reg_spimaster_data;		// Read back byte
+    // Write checkpoint
+    reg_mprj_datal = 0xA04b0000 | (value << 8);	// PLL divider (5 lowest bits)
+
+    reg_spimaster_config = 0xa102;	// Release CSB (ends stream mode)
+    reg_spimaster_config = 0x2102;	// Release housekeeping SPI
+
+    // End test
+    reg_mprj_datal = 0xA0900000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
new file mode 100644
index 0000000..295c029
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v

@@ -0,0 +1,224 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module sysctrl_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [7:0] spivalue;
+	wire [37:0] mprj_io;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire SDO;
+
+	assign checkbits = mprj_io[31:16];
+	assign spivalue  = mprj_io[15:8];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("sysctrl.vcd");
+		$dumpvars(0, sysctrl_tb);
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+		`endif
+		 $display("%c[0m",27);
+		$finish;
+	end
+
+	// Monitor
+	initial begin
+	    wait(checkbits == 16'hA040);
+			`ifdef GL
+            	$display("Monitor: Test Sysctrl (GL) Started");
+			`else
+			    $display("Monitor: Test Sysctrl (RTL) Started");
+			`endif
+	    wait(checkbits == 16'hA041);
+            $display("   SPI value = 0x%x (should be 0x04)", spivalue);
+            if(spivalue !== 32'h04) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA042);
+            $display("   SPI value = 0x%x (should be 0x56)", spivalue);
+            if(spivalue !== 32'h56) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA043);
+            $display("   SPI value = 0x%x (should be 0x10)", spivalue);
+            if(spivalue !== 32'h10) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA044);
+            $display("   SPI value = 0x%x (should be 0x02)", spivalue);
+            if(spivalue !== 32'h02) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA045);
+            $display("   SPI value = 0x%x (should be 0x01)", spivalue);
+            if(spivalue !== 32'h01) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA046);
+            $display("   SPI value = 0x%x (should be 0xff)", spivalue);
+            if(spivalue !== 32'hff) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA047);
+            $display("   SPI value = 0x%x (should be 0xef)", spivalue);
+            if(spivalue !== 32'hef) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA048);
+            $display("   SPI value = 0x%x (should be 0xff)", spivalue);
+            if(spivalue !== 32'hff) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA049);
+            $display("   SPI value = 0x%x (should be 0x03)", spivalue);
+            if(spivalue !== 32'h03) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA04a);
+            $display("   SPI value = 0x%x (should be 0x12)", spivalue);
+            if(spivalue !== 32'h12) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+	    wait(checkbits == 16'hA04b);
+            $display("   SPI value = 0x%x (should be 0x04)", spivalue);
+            if(spivalue !== 32'h04) begin
+                $display("Monitor: Test Sysctrl Failed");
+                $finish;
+            end
+
+	    wait(checkbits == 16'hA090);
+		 	`ifdef GL
+            	$display("Monitor: Test Sysctrl (GL) Passed");
+			`else
+		        $display("Monitor: Test Sysctrl (RTL) Passed");
+			`endif
+            $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		#1 $display("GPIO state = %b ", checkbits);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	assign mprj_io[3] = 1'b1;
+	
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("sysctrl.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile
new file mode 100644
index 0000000..aa978e5
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer.c b/verilog/dv/caravel/mgmt_soc/timer/timer.c
new file mode 100644
index 0000000..e01ed7f
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer.c

@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	Timer Test
+ */
+
+void main()
+{
+	int i;
+	uint32_t value;
+
+	/* Initialize output data vector to zero */
+	reg_mprj_datah = 0x00000000;
+	reg_mprj_datal = 0x00000000;
+
+	/* Apply all 38 bits to management standard output.	*/
+
+	/* The lower 32 will be used to output the count value	*/
+	/* from the timer.  The top 5 bits will be used	to mark	*/
+	/* specific checkpoints for the testbench simulation.	*/
+
+	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_7  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_5  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_4  = GPIO_MODE_MGMT_STD_OUTPUT;
+	// reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Present start marker (see testbench verilog) */
+	reg_mprj_datah = 0x0a;
+
+	/* Configure timer for a single-shot countdown */
+	reg_timer0_value = 0xdcba9876;
+
+	/* Timer configuration bits:				*/
+	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
+	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
+	/* 2 = up/down (1 = count up, 0 = count down)		*/
+	/* 3 = chain (1 = enabled, 0 = disabled)		*/
+	/* 4 = IRQ enable (1 = enabled, 0 = disabled)		*/
+
+	reg_timer0_config = 3;	/* Enabled, one-shot, down count */
+
+	for (i = 0; i < 8; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_timer0_config = 0;	/* Disabled */
+
+	reg_mprj_datah = 0x01;	/* Check value in testbench */
+
+	reg_timer0_value = 0x00000011;
+	reg_timer0_config = 7;	/* Enabled, one-shot, count up */
+	
+	for (i = 0; i < 3; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x02;	/* Check value in testbench */
+	
+	reg_timer0_data = 0x00000101;	// Set value (will be reset)
+	reg_timer0_config = 2;	/* Disabled, one-shot, count up */
+	reg_timer0_config = 5;	/* Enabled, continuous, count down */
+	
+	for (i = 0; i < 5; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x03;	/* Check value in testbench */
+
+	reg_timer0_data = 0x00000145;	// Force new value
+
+	reg_mprj_datah = 0x04;	/* Check value in testbench */
+	
+	for (i = 0; i < 5; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+	
+	/* Present end marker (see testbench verilog) */
+	reg_mprj_datah = 0x05;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
new file mode 100644
index 0000000..3865bf3
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

@@ -0,0 +1,201 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer_tb;
+
+	reg RSTB;
+	reg clock;
+	reg power1, power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("timer.vcd");
+		$dumpvars(0, timer_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (50) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test GPIO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+		`endif
+		 $display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [5:0] checkbits;
+	wire [31:0] countbits;
+
+	assign checkbits = mprj_io[37:32];
+	assign countbits = mprj_io[31:0];
+
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	// Monitor
+	initial begin
+		wait(checkbits == 6'h0a);
+		`ifdef GL
+			$display("Monitor: Test Timer (GL) Started");
+		`else 
+			$display("Monitor: Test Timer (RTL) Started");
+		`endif
+		/* Add checks here */
+		wait(checkbits == 6'h01);
+		$display("   countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+		if(countbits !== 32'hdcba7cfb) begin
+		    $display("Monitor: Test Timer Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h02);
+		$display("   countbits = 0x%x (should be 0x19)", countbits);
+		if(countbits !== 32'h19) begin
+		    $display("Monitor: Test Timer Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h03);
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== ((32'h0f) | (3'b100))) begin
+		    $display("Monitor: Test Timer Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h04);
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== ((32'h0f) | (3'b100))) begin
+		    $display("Monitor: Test Timer Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h05);
+		$display("   countbits = %x (should be 0x12bc)", countbits);
+		if(countbits !== 32'h12bc) begin
+		    $display("Monitor: Test Timer Failed");
+		    $finish;
+		end
+		
+		`ifdef GL
+			$display("Monitor: Test Timer (GL) Passed");
+		`else
+			$display("Monitor: Test Timer (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		#1 $display("Timer state = %b (%d)", countbits, countbits);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("timer.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
new file mode 100644
index 0000000..206be56
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = timer2
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2.c b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
new file mode 100644
index 0000000..6d598ac
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c

@@ -0,0 +1,214 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+/*
+ *	Timer2 Test --- This runs the same testbench as the
+ *	other timer, on the 2nd counter/timer module instance.
+ */
+
+void main()
+{
+	int i;
+	uint32_t value;
+
+	/* Initialize output data vector to zero */
+	reg_mprj_datah = 0x00000000;
+	reg_mprj_datal = 0x00000000;
+
+	/* Apply all 38 bits to management standard output.	*/
+
+	/* The lower 32 will be used to output the count value	*/
+	/* from the timer.  The top 5 bits will be used	to mark	*/
+	/* specific checkpoints for the testbench simulation.	*/
+
+	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_9  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_8  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_7  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_5  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_4  = GPIO_MODE_MGMT_STD_OUTPUT;
+	// reg_mprj_io_3  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_2  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_1  = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_0  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Present start marker (see testbench verilog) */
+	reg_mprj_datah = 0x0a;
+
+	/* Configure timer for a single-shot countdown */
+	reg_timer1_value = 0xdcba9876;
+
+	/* Timer configuration bits:				*/
+	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
+	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
+	/* 2 = up/down (1 = count up, 0 = count down)		*/
+	/* 3 = IRQ enable (1 = enabled, 0 = disabled)		*/
+
+	reg_timer1_config = 3;	/* Enabled, one-shot, down count */
+
+	for (i = 0; i < 8; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_timer1_config = 0;	/* Disabled */
+
+	reg_mprj_datah = 0x01;	/* Check value in testbench */
+
+	reg_timer1_value = 0x00000011;
+	reg_timer1_config = 7;	/* Enabled, one-shot, count up */
+	
+	for (i = 0; i < 3; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x02;	/* Check value in testbench */
+	
+	reg_timer1_data = 0x00000101;	// Set value (will be reset)
+	reg_timer1_config = 2;	/* Disabled, one-shot, count up */
+	reg_timer1_config = 5;	/* Enabled, continuous, count down */
+	
+	for (i = 0; i < 5; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x03;	/* Check value in testbench */
+
+	reg_timer1_data = 0x00000145;	// Force new value
+
+	reg_mprj_datah = 0x04;	/* Check value in testbench */
+	
+	for (i = 0; i < 5; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x05;	/* Check value in testbench */
+
+	/* Now, set up chained 64 bit timer.  Check count-up	*/
+	/* value and count-down value crossing the 32-bit	*/
+	/* boundary.						*/
+
+	/* First disable both counters, and set the "chained"	*/
+	/* property so that enable/disable will be synchronized	*/
+
+	reg_timer1_config = 8;	/* Disabled, chained */
+	reg_timer0_config = 8;	/* Disabled, chained */
+
+	/* Configure timer for a chained single-shot countdown. */
+	/* Count start = 0x0000000100001000, end = 0x0		*/
+
+	reg_timer1_value = 0x00000055;
+	reg_timer0_value = 0x00001000;
+
+	/* Timer configuration bits:				*/
+	/* 0 = timer enable (1 = enabled, 0 = disabled)		*/
+	/* 1 = one-shot mode (1 = oneshot, 0 = continuous)	*/
+	/* 2 = up/down (1 = count up, 0 = count down)		*/
+	/* 3 = chain (1 = enabled, 0 = disabled)		*/
+	/* 4 = IRQ enable (1 = enabled, 0 = disabled)		*/
+
+	reg_timer1_config = 11;	/* Enabled, one-shot, down count, chained */
+	reg_timer0_config = 11;	/* Enabled, one-shot, down count, chained */
+
+	for (i = 0; i < 1; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x06;	/* Check value in testbench */
+
+	// Skip to the end. . .
+	reg_timer1_data = 0x00000000;
+	reg_timer0_data = 0x00000200;
+
+	for (i = 0; i < 4; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x07;	/* Check value in testbench */
+
+	reg_timer1_config = 14;	/* Disabled, one-shot, up count, chained */
+	reg_timer0_config = 14;	/* Disabled, one-shot, up count, chained */
+
+	reg_timer1_value = 0x00000002;
+	reg_timer0_value = 0x00000000;
+
+	reg_timer1_config = 15;	/* Enabled, one-shot, up count, chained */
+	reg_timer0_config = 15;	/* Enabled, one-shot, up count, chained */
+
+	for (i = 0; i < 1; i++) {
+	    value = reg_timer0_data;
+	    reg_mprj_datal = value;	// Put count value on GPIO
+	}
+
+	reg_mprj_datah = 0x08;	/* Check value in testbench */
+
+	// Skip to the end. . . 
+	/* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
+
+	reg_timer1_data = 0x00000001;	// Set value (will be reset)
+	reg_timer0_data = 0xffffff00;	// Set value (will be reset)
+
+	for (i = 0; i < 4; i++) {
+	    value = reg_timer1_data;
+	    reg_mprj_datal = value;	// Put timer1 count value on GPIO
+	}
+
+	/* Present end marker (see testbench verilog) */
+	reg_mprj_datah = 0x10;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
new file mode 100644
index 0000000..a53e216
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

@@ -0,0 +1,229 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module timer2_tb;
+
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("timer2.vcd");
+		$dumpvars(0, timer2_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (60) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [5:0] checkbits;
+	wire [31:0] countbits;
+
+	assign checkbits = mprj_io[37:32];
+	assign countbits = mprj_io[31:0];
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	// Monitor
+	initial begin
+		wait(checkbits == 6'h0a);
+		`ifdef GL
+			$display("Monitor: Test Timer2 (GL) Started");
+		`else
+			$display("Monitor: Test Timer2 (RTL) Started");
+		`endif
+		/* Add checks here */
+		wait(checkbits == 6'h01);
+		$display("   countbits = 0x%x (should be 0xdcba7cfb)", countbits);
+		if(countbits !== 32'hdcba7cfb) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h02);
+		$display("   countbits = 0x%x (should be 0x19)", countbits);
+		if(countbits !== 32'h19) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h03);
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
+		    $display("Monitor: Test Timer (RTL) Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h04);
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+		wait(checkbits == 6'h05);
+		$display("   countbits = %x (should be 0x12bc)", countbits);
+		if(countbits !== 32'h12bc) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+
+		wait(checkbits == 6'h06);
+		$display("   countbits = %x (should be 0x005d)", countbits);
+		if(countbits !== 32'h005d) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+
+		wait(checkbits == 6'h07);
+		$display("   countbits = %x (should be 0x0008)", countbits);
+		if(countbits !== 32'h0008) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+
+		wait(checkbits == 6'h08);
+		$display("   countbits = %x (should be 0x0259)", countbits);
+		if(countbits !== 32'h0259) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+
+		wait(checkbits == 6'h10);
+		$display("   countbits = %x (should be 0x000a)", countbits);
+		if(countbits !== 32'h000a) begin
+		    $display("Monitor: Test Timer2 (RTL) Failed");
+		    $finish;
+		end
+
+		`ifdef GL
+			$display("Monitor: Test Timer2 (GL) Passed");
+		`else
+			$display("Monitor: Test Timer2 (RTL) Passed");
+		`endif
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		#1 $display("Timer state = %b (%d)", countbits, countbits);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+	
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("timer2.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
new file mode 100644
index 0000000..e8bd40a
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = uart
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c
new file mode 100644
index 0000000..13cee0f
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart.c

@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+void main()
+{
+    int j;
+
+    // Configure I/O:  High 16 bits of user area used for a 16-bit
+    // word to write and be detected by the testbench verilog.
+    // Only serial Tx line is used in this testbench.  It connects
+    // to mprj_io[6].  Since all lines of the chip are input or
+    // high impedence on startup, the I/O has to be configured
+    // for output
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Set clock to 64 kbaud and enable the UART.  It is important to do this
+    // before applying the configuration, or else the Tx line initializes as
+    // zero, which indicates the start of a byte to the receiver.
+
+    reg_uart_clkdiv = 625;
+    reg_uart_enable = 1;
+
+    // Now, apply the configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xa0000000;
+
+    // This should appear at the output, received by the testbench UART.
+    // (Makes simulation time long.)
+    print("Monitor: Test UART (RTL) passed\n");
+
+    // Allow transmission to complete before signalling that the program
+    // has ended.
+    for (j = 0; j < 20; j++);
+    reg_mprj_datal = 0xab000000;
+}

diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
new file mode 100644
index 0000000..d8bbd35
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v

@@ -0,0 +1,150 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module uart_tb;
+	reg clock;
+	reg RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+	wire uart_tx;
+	wire SDO;
+
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("uart.vcd");
+		$dumpvars(0, uart_tb);
+
+		$display("Wait for UART o/p");
+		repeat (150) begin
+			repeat (10000) @(posedge clock);
+			// Diagnostic. . . interrupts output pattern.
+		end
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+	always @(checkbits) begin
+		if(checkbits == 16'hA000) begin
+			$display("UART Test started");
+		end
+		else if(checkbits == 16'hAB00) begin
+			`ifdef GL
+				$display("UART Test (GL) passed");
+			`else
+				$display("UART Test (RTL) passed");
+			`endif
+			$finish;
+		end
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+	
+	assign mprj_io[3] = 1'b1;  // Force CSB high.
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("uart.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Testbench UART
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+		
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile
new file mode 100644
index 0000000..074b999
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile

@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
+BEHAVIOURAL_MODELS = ../../ 
+
+FIRMWARE_PATH = ../..
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = user_pass_thru
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+else  
+	iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
+	-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
+

diff --git a/verilog/dv/caravel/mgmt_soc/user_pass_thru/README b/verilog/dv/caravel/mgmt_soc/user_pass_thru/README
new file mode 100644
index 0000000..e4072d6
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/user_pass_thru/README

@@ -0,0 +1,14 @@
+------------------------------------
+user_pass_thru test bench
+------------------------------------
+
+This test bench exercises the pass-thru mode to the GPIO pins
+that are reserved for use by a user project for connecting to
+an SPI flash.  The pass-thru mode allows the SPI flash to be
+programmed using the housekeeping SPI.
+
+The testbench is essentially the same as the pass_thru test
+bench, but using the pins specified for the secondary SPI
+flash.  Note that the testbench does not define a controller
+on the user side to access the SPI flash (which would be a
+useful thing to add to the testbench).

diff --git a/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c b/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c
new file mode 100644
index 0000000..011102c
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c

@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../../defs.h"
+
+// --------------------------------------------------------
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
+// --------------------------------------------------------
+
+void main()
+{
+    // This program is just to keep the processor busy while the
+    // housekeeping SPI is being accessed. to show that the
+    // processor is halted while the SPI is accessing the
+    // flash SPI in pass-through mode.
+
+    // Configure I/O:  High 16 bits of user area used for a 16-bit
+    // word to write and be detected by the testbench verilog.
+    // Only serial Tx line is used in this testbench.  It connects
+    // to mprj_io[6].  Since all lines of the chip are input or
+    // high impedence on startup, the I/O has to be configured
+    // for output
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Management needs to apply output on these pads to access the user area SPI flash
+    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    // Start test
+    reg_mprj_datal = 0xa0000000;
+
+    // Set clock to 64 kbaud and enable the UART
+    reg_uart_clkdiv = 625;
+    reg_uart_enable = 1;
+
+    // Test in progress
+    reg_mprj_datal = 0xa5000000;
+
+    // Test message
+    print("Test message\n");
+
+    // End test
+    reg_mprj_datal = 0xab000000;
+}
+

diff --git a/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v
new file mode 100644
index 0000000..6407813
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v

@@ -0,0 +1,399 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*	
+ *	StriVe housekeeping pass-thru mode SPI testbench.
+ */
+
+`timescale 1 ns / 1 ps
+
+`include "__uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module user_pass_thru_tb;
+	reg clock;
+	reg SDI, CSB, SCK, RSTB;
+	reg power1, power2;
+
+	wire gpio;
+	wire [15:0] checkbits;
+	wire [37:0] mprj_io;
+	wire uart_tx;
+	wire uart_rx;
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire flash_io2;
+	wire flash_io3;
+
+	wire user_csb;
+	wire user_clk;
+	wire user_io0;
+	wire user_io1;
+
+	wire SDO;
+
+	always #10 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    // The main testbench is here.  Put the housekeeping SPI into
+    // pass-thru mode and read several bytes from the flash SPI.
+
+    // First define tasks for SPI functions
+
+	task start_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b0;
+		#50;
+	    end
+	endtask
+
+	task end_csb;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		CSB <= 1'b1;
+		#50;
+	    end
+	endtask
+
+	task write_byte;
+	    input [7:0] odata;
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_byte;
+	    output [7:0] idata;
+	    begin
+		SCK <= 1'b0;
+		SDI <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+
+	task read_write_byte
+	    (input [7:0] odata,
+	    output [7:0] idata);
+	    begin
+		SCK <= 1'b0;
+		for (i=7; i >= 0; i--) begin
+		    #50;
+		    SDI <= odata[i];
+                    idata[i] = SDO;
+                    #50;
+		    SCK <= 1'b1;
+                    #100;
+		    SCK <= 1'b0;
+		end
+	    end
+	endtask
+	
+	integer i;
+
+    // Now drive the digital signals on the housekeeping SPI
+	reg [7:0] tbdata;
+
+	initial begin
+	    $dumpfile("user_pass_thru.vcd");
+	    $dumpvars(0, user_pass_thru_tb);
+
+	    CSB <= 1'b1;
+	    SCK <= 1'b0;
+	    SDI <= 1'b0;
+	    RSTB <= 1'b0;
+
+	    #2000;
+
+	    RSTB <= 1'b1;
+
+	    // Wait on start of program execution
+	    wait(checkbits == 16'hA000);
+
+            // First do a normal read from the housekeeping SPI to
+	    // make sure the housekeeping SPI works.
+
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+
+	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+	    // The SPI flash may need to be reset.
+	    start_csb();
+	    write_byte(8'hc2);	// Apply user pass-thru command to housekeeping SPI
+	    write_byte(8'hff);	// SPI flash command ff
+	    end_csb();
+
+	    start_csb();
+	    write_byte(8'hc2);	// Apply user pass-thru command to housekeeping SPI
+	    write_byte(8'hab);	// SPI flash command ab
+	    end_csb();
+
+	    start_csb();
+	    write_byte(8'hc2); // Apply user pass-thru command to housekeeping SPI
+	    write_byte(8'h03);	// Command 03 (read values w/3-byte address)
+	    write_byte(8'h00);	// Address is next three bytes (0x000000)
+	    write_byte(8'h00);
+	    write_byte(8'h00);
+
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
+	    if(tbdata !== 8'h93) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
+	    if(tbdata !== 8'h01) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+	    read_byte(tbdata);
+	    $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
+	    if(tbdata !== 8'h00) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+	    end_csb();
+
+	    // Reset processor
+	    start_csb();
+	    write_byte(8'h80);	// Write stream command
+	    write_byte(8'h0b);	// Address (register 11 = reset)
+	    write_byte(8'h01);	// Data (value 1 = apply reset)
+	    end_csb();
+
+	    start_csb();
+	    write_byte(8'h80);	// Write stream command
+	    write_byte(8'h0b);	// Address (register 11 = reset)
+	    write_byte(8'h00);	// Data (value 1 = apply reset)
+	    end_csb();
+
+	    // Wait for processor to restart
+	    wait(checkbits == 16'hA000);
+
+	    // Read product ID register again
+
+	    start_csb();
+	    write_byte(8'h40);	// Read stream command
+	    write_byte(8'h03);	// Address (register 3 = product ID)
+	    read_byte(tbdata);
+	    end_csb();
+	    #10;
+	    $display("Read data = 0x%02x (should be 0x10)", tbdata);
+	    if(tbdata !== 8'h10) begin 
+			`ifdef GL
+				$display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; 
+			`else
+				$display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; 
+			`endif
+		end
+
+		`ifdef GL
+	    	$display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+		`else
+			$display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+		`endif
+		
+	    #10000;
+ 	    $finish;
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	wire hk_sck;
+	wire hk_csb;
+	wire hk_sdi;
+
+	assign hk_sck = SCK;
+	assign hk_csb = CSB;
+	assign hk_sdi = SDI;
+
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+	assign mprj_io[5] = uart_rx;
+	assign mprj_io[4] = hk_sck;
+	assign mprj_io[3] = hk_csb;
+	assign mprj_io[2] = hk_sdi;
+	assign SDO = mprj_io[1];
+
+	assign user_csb = mprj_io[8];
+	assign user_clk = mprj_io[9];
+	assign user_io0 = mprj_io[10];
+	assign mprj_io[11] = user_io1;
+	
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("user_pass_thru.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	// Use the same flash; this is just to put known data in memory that can be
+	// checked by reading it back through a pass-through command.
+	spiflash #(
+		.FILENAME("user_pass_thru.hex")
+	) secondary (
+		.csb(user_csb),
+		.clk(user_clk),
+		.io0(user_io0),
+		.io1(user_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+
+	tbuart tbuart (
+		.ser_rx(uart_tx)
+	);
+		
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/caravel/sections.lds b/verilog/dv/caravel/sections.lds
new file mode 100644
index 0000000..2d8c048
--- /dev/null
+++ b/verilog/dv/caravel/sections.lds

@@ -0,0 +1,75 @@
+/*
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+*/
+
+MEMORY {
+	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x0400		/* 256 words (1 KB) */ 
+}
+
+SECTIONS {
+	/* The program code and other data goes into FLASH */
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)	/* .text sections (code) */
+		*(.text*)	/* .text* sections (code) */
+		*(.rodata)	/* .rodata sections (constants, strings, etc.) */
+		*(.rodata*)	/* .rodata* sections (constants, strings, etc.) */
+		*(.srodata)	/* .srodata sections (constants, strings, etc.) */
+		*(.srodata*)	/* .srodata*sections (constants, strings, etc.) */
+		. = ALIGN(4);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+	} >FLASH
+
+	/* Initialized data section */
+	.data : AT ( _sidata )
+	{
+		. = ALIGN(4);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(4);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(4);
+		_edata = .;
+	} >RAM
+
+	/* Uninitialized data section */
+	.bss :
+	{
+		. = ALIGN(4);
+		_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(.sbss)
+		*(.sbss*)
+		*(COMMON)
+
+		. = ALIGN(4);
+		_ebss = .;
+	} >RAM
+
+	/* Define the start of the heap */
+	.heap :
+	{
+		. = ALIGN(4);
+		_heap_start = .;
+	} >RAM
+}

diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
new file mode 100644
index 0000000..6aa29ba
--- /dev/null
+++ b/verilog/dv/caravel/spiflash.v

@@ -0,0 +1,447 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+//    AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+//    Cypress S25FL064L http://www.cypress.com/file/316661/download
+//    Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+	parameter FILENAME = "firmware.hex"
+)(
+	input csb,
+	input clk,
+	inout io0, // MOSI
+	inout io1, // MISO
+	inout io2,
+	inout io3
+);
+	localparam verbose = 0;
+	localparam integer latency = 8;
+	
+	reg [7:0] buffer;
+	reg [3:0] reset_count = 0;
+	reg [3:0] reset_monitor = 0;
+	integer bitcount = 0;
+	integer bytecount = 0;
+	integer dummycount = 0;
+
+	reg [7:0] spi_cmd;
+	reg [7:0] xip_cmd = 0;
+	reg [23:0] spi_addr;
+
+	reg [7:0] spi_in;
+	reg [7:0] spi_out;
+	reg spi_io_vld;
+
+	reg powered_up = 0;
+
+	localparam [3:0] mode_spi         = 1;
+	localparam [3:0] mode_dspi_rd     = 2;
+	localparam [3:0] mode_dspi_wr     = 3;
+	localparam [3:0] mode_qspi_rd     = 4;
+	localparam [3:0] mode_qspi_wr     = 5;
+	localparam [3:0] mode_qspi_ddr_rd = 6;
+	localparam [3:0] mode_qspi_ddr_wr = 7;
+
+	reg [3:0] mode = 0;
+	reg [3:0] next_mode = 0;
+
+	reg io0_oe = 0;
+	reg io1_oe = 0;
+	reg io2_oe = 0;
+	reg io3_oe = 0;
+
+	reg io0_dout = 0;
+	reg io1_dout = 0;
+	reg io2_dout = 0;
+	reg io3_dout = 0;
+
+	assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+	assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+	assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+	assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+	wire io0_delayed;
+	wire io1_delayed;
+	wire io2_delayed;
+	wire io3_delayed;
+
+	assign #1 io0_delayed = io0;
+	assign #1 io1_delayed = io1;
+	assign #1 io2_delayed = io2;
+	assign #1 io3_delayed = io3;
+
+	// 16 MB (128Mb) Flash
+	reg [7:0] memory [0:16*1024*1024-1];
+
+	initial begin
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+		$display("Reading %s",  FILENAME);
+		$readmemh(FILENAME, memory);
+		$display("%s loaded into memory", FILENAME);
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+	end
+
+	task spi_action;
+		begin
+			spi_in = buffer;
+
+			if (bytecount == 1) begin
+				spi_cmd = buffer;
+
+				if (spi_cmd == 8'h ab)
+					powered_up = 1;
+
+				if (spi_cmd == 8'h b9)
+					powered_up = 0;
+
+				if (spi_cmd == 8'h ff)
+					xip_cmd = 0;
+			end
+
+			if (powered_up && spi_cmd == 'h 03) begin
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount >= 4) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h bb) begin
+				if (bytecount == 1)
+					mode = mode_dspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_dspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h eb) begin
+				if (bytecount == 1)
+					mode = mode_qspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h ed) begin
+				if (bytecount == 1)
+					next_mode = mode_qspi_ddr_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_ddr_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			spi_out = buffer;
+			spi_io_vld = 1;
+
+			if (verbose) begin
+				if (bytecount == 1)
+					$write("<SPI-START>");
+				$write("<SPI:%02x:%02x>", spi_in, spi_out);
+			end
+
+		end
+	endtask
+
+	task ddr_rd_edge;
+		begin
+			buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	task ddr_wr_edge;
+		begin
+			io0_oe = 1;
+			io1_oe = 1;
+			io2_oe = 1;
+			io3_oe = 1;
+
+			io0_dout = buffer[4];
+			io1_dout = buffer[5];
+			io2_dout = buffer[6];
+			io3_dout = buffer[7];
+
+			buffer = {buffer, 4'h 0};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	always @(csb) begin
+		if (csb) begin
+			if (verbose) begin
+				$display("");
+				$fflush;
+			end
+			buffer = 0;
+			bitcount = 0;
+			bytecount = 0;
+			mode = mode_spi;
+			io0_oe = 0;
+			io1_oe = 0;
+			io2_oe = 0;
+			io3_oe = 0;
+
+			// Handle MBR.  If in XIP continuous mode, the following
+			// 8 clock cycles are normally not expected to be a command.
+			// If followed by CSB high, however, if the address bits
+			// are consistent with io0 == 1 for 8 clk cycles, then an
+			// MBR has been issued and the system must exit XIP
+			// continuous mode.
+			if (xip_cmd == 8'hbb || xip_cmd == 8'heb
+					|| xip_cmd == 8'hed) begin
+				if (reset_count == 4'h8 && reset_monitor == 4'h8) begin
+					xip_cmd = 8'h00;
+					spi_cmd = 8'h03;
+				end
+			end
+		end else
+		if (xip_cmd) begin
+			buffer = xip_cmd;
+			bitcount = 0;
+			bytecount = 1;
+			spi_action;
+		end
+	end
+
+	always @(posedge clk or posedge csb) begin
+		if (csb == 1'b1) begin
+			reset_count = 0;
+			reset_monitor = 0;
+		end else begin
+			if (reset_count < 4'h9) begin
+				reset_count = reset_count + 1;
+				if (io0_delayed == 1'b1) begin
+				    reset_monitor = reset_monitor + 1;
+				end
+			end
+		end
+	end
+
+	always @(csb, clk) begin
+		spi_io_vld = 0;
+		if (!csb && !clk) begin
+			if (dummycount > 0) begin
+				io0_oe = 0;
+				io1_oe = 0;
+				io2_oe = 0;
+				io3_oe = 0;
+			end else
+			case (mode)
+				mode_spi: begin
+					io0_oe = 0;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io1_dout = buffer[7];
+				end
+				mode_dspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_dspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io0_dout = buffer[6];
+					io1_dout = buffer[7];
+				end
+				mode_qspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_qspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 1;
+					io3_oe = 1;
+					io0_dout = buffer[4];
+					io1_dout = buffer[5];
+					io2_dout = buffer[6];
+					io3_dout = buffer[7];
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+			if (next_mode) begin
+				case (next_mode)
+					mode_qspi_ddr_rd: begin
+						io0_oe = 0;
+						io1_oe = 0;
+						io2_oe = 0;
+						io3_oe = 0;
+					end
+					mode_qspi_ddr_wr: begin
+						io0_oe = 1;
+						io1_oe = 1;
+						io2_oe = 1;
+						io3_oe = 1;
+						io0_dout = buffer[4];
+						io1_dout = buffer[5];
+						io2_dout = buffer[6];
+						io3_dout = buffer[7];
+					end
+				endcase
+				mode = next_mode;
+				next_mode = 0;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!csb) begin
+			if (dummycount > 0) begin
+				dummycount = dummycount - 1;
+			end else
+			case (mode)
+				mode_spi: begin
+					buffer = {buffer, io0};
+					bitcount = bitcount + 1;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_dspi_rd, mode_dspi_wr: begin
+					buffer = {buffer, io1, io0};
+					bitcount = bitcount + 2;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_rd, mode_qspi_wr: begin
+					buffer = {buffer, io3, io2, io1, io0};
+					bitcount = bitcount + 4;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+		end
+	end
+endmodule

diff --git a/verilog/dv/caravel/start.s b/verilog/dv/caravel/start.s
new file mode 100644
index 0000000..287cba2
--- /dev/null
+++ b/verilog/dv/caravel/start.s

@@ -0,0 +1,174 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li   t0, 0x28000000
+
+# Set CS high, IO0 is output
+li   t1, 0x120
+sh   t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb   zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li   t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb   t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li   t5, 32
+# Load t2 from address a0 (4 bytes)
+lw   t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li   t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+lbu  t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or   t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw   t2, 0(a0)
+addi a0, a0, 4
+lw   t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw   t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li   t1, 0x80
+sb   t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+

diff --git a/verilog/dv/caravel/stub.c b/verilog/dv/caravel/stub.c
new file mode 100644
index 0000000..575cfc3
--- /dev/null
+++ b/verilog/dv/caravel/stub.c

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
\ No newline at end of file

diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
new file mode 100644
index 0000000..bac9480
--- /dev/null
+++ b/verilog/dv/caravel/tbuart.v

@@ -0,0 +1,93 @@
+`default_nettype none
+/*
+ *  SPDX-FileCopyrightText: 2017 Clifford Wolf
+ *
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+	reg [8*50-1:0] recv_buf_data;	// 50 characters.  Increase as needed for tests.
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+		recv_buf_data <= 0;
+	end
+
+	// NOTE:  Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+	// bit ~= 64 kbaud. Not tuned to any particular UART.  Most run at
+	// 9600 baud default and will bounce up to higher baud rates when
+	// passed specific command words.
+
+	always #1500 clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					// 0x0a = '\n'
+					if (recv_pattern == 8'h0a) begin
+						$display("output: %s", recv_buf_data);
+					end else begin
+						recv_buf_data <= {recv_buf_data, recv_pattern};
+					end
+					recv_state <= 0;
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule

diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
new file mode 100644
index 0000000..be068fc
--- /dev/null
+++ b/verilog/dv/dummy_slave.v

@@ -0,0 +1,49 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+module dummy_slave(
+    input wb_clk_i,
+    input wb_rst_i,
+    
+    input wb_stb_i,
+    input wb_cyc_i,
+    input wb_we_i,
+    input [3:0] wb_sel_i,
+    input [31:0] wb_adr_i,
+    input [31:0] wb_dat_i,
+    
+    output reg [31:0] wb_dat_o,
+    output reg wb_ack_o
+);
+    reg [31:0] store;
+
+    wire valid = wb_cyc_i & wb_stb_i;
+
+    always @(posedge wb_clk_i) begin
+        if (wb_rst_i == 1'b 1) begin
+            wb_ack_o <= 1'b 0;
+        end else begin
+            if (wb_we_i == 1'b 1) begin
+                if (wb_sel_i[0]) store[7:0]   <= wb_dat_i[7:0];
+                if (wb_sel_i[1]) store[15:8]  <= wb_dat_i[15:8];
+                if (wb_sel_i[2]) store[23:16] <= wb_dat_i[23:16];
+                if (wb_sel_i[3]) store[31:24] <= wb_dat_i[31:24];
+            end
+            wb_dat_o <= store;
+            wb_ack_o <= valid & !wb_ack_o;
+        end
+    end
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/Makefile b/verilog/dv/wb_utests/Makefile
new file mode 100644
index 0000000..cd86cb8
--- /dev/null
+++ b/verilog/dv/wb_utests/Makefile

@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = gpio_wb intercon_wb la_wb mem_wb mprj_ctrl spi_sysctrl_wb spimemio_wb uart_wb storage_wb mgmt_protect chip_io
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/chip_io/Makefile b/verilog/dv/wb_utests/chip_io/Makefile
new file mode 100644
index 0000000..4bd731a
--- /dev/null
+++ b/verilog/dv/wb_utests/chip_io/Makefile

@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH = $(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = chip_io
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+ifeq ($(SIM),SPLIT_BUS)
+	iverilog -Ttyp  -DFUNCTIONAL -DSPLIT_BUS -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+ifeq ($(SIM),GL)
+	iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/chip_io/chip_io_split.v b/verilog/dv/wb_utests/chip_io/chip_io_split.v
new file mode 100644
index 0000000..62a1cb2
--- /dev/null
+++ b/verilog/dv/wb_utests/chip_io/chip_io_split.v

@@ -0,0 +1,4218 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module chip_io(vddio, vssio, vccd, vssd, vdda, vssa, vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1, porb_h, por, resetb_core_h, clock_core, gpio_out_core, gpio_in_core, gpio_mode0_core, gpio_mode1_core, gpio_outenb_core, gpio_inenb_core, flash_csb_core, flash_clk_core, flash_csb_oeb_core, flash_clk_oeb_core, flash_io0_oeb_core, flash_io1_oeb_core, flash_csb_ieb_core, flash_clk_ieb_core, flash_io0_ieb_core, flash_io1_ieb_core, flash_io0_do_core, flash_io1_do_core, flash_io0_di_core, flash_io1_di_core, \mprj_io[0] , \mprj_io[1] , \mprj_io[2] , \mprj_io[3] , \mprj_io[4] , \mprj_io[5] , \mprj_io[6] , \mprj_io[7] , \mprj_io[8] , \mprj_io[9] , \mprj_io[10] , \mprj_io[11] , \mprj_io[12] , \mprj_io[13] , \mprj_io[14] , \mprj_io[15] , \mprj_io[16] , \mprj_io[17] , \mprj_io[18] , \mprj_io[19] , \mprj_io[20] , \mprj_io[21] , \mprj_io[22] , \mprj_io[23] , \mprj_io[24] , \mprj_io[25] , \mprj_io[26] , \mprj_io[27] , \mprj_io[28] , \mprj_io[29] , \mprj_io[30] , \mprj_io[31] , \mprj_io[32] , \mprj_io[33] , \mprj_io[34] , \mprj_io[35] , \mprj_io[36] , \mprj_io[37] , \mprj_io_out[0] , \mprj_io_out[1] , \mprj_io_out[2] , \mprj_io_out[3] , \mprj_io_out[4] , \mprj_io_out[5] , \mprj_io_out[6] , \mprj_io_out[7] , \mprj_io_out[8] , \mprj_io_out[9] , \mprj_io_out[10] , \mprj_io_out[11] , \mprj_io_out[12] , \mprj_io_out[13] , \mprj_io_out[14] , \mprj_io_out[15] , \mprj_io_out[16] , \mprj_io_out[17] , \mprj_io_out[18] , \mprj_io_out[19] , \mprj_io_out[20] , \mprj_io_out[21] , \mprj_io_out[22] , \mprj_io_out[23] , \mprj_io_out[24] , \mprj_io_out[25] , \mprj_io_out[26] , \mprj_io_out[27] , \mprj_io_out[28] , \mprj_io_out[29] , \mprj_io_out[30] , \mprj_io_out[31] , \mprj_io_out[32] , \mprj_io_out[33] , \mprj_io_out[34] , \mprj_io_out[35] , \mprj_io_out[36] , \mprj_io_out[37] , \mprj_io_oeb[0] , \mprj_io_oeb[1] , \mprj_io_oeb[2] , \mprj_io_oeb[3] , \mprj_io_oeb[4] , \mprj_io_oeb[5] , \mprj_io_oeb[6] , \mprj_io_oeb[7] , \mprj_io_oeb[8] , \mprj_io_oeb[9] , \mprj_io_oeb[10] , \mprj_io_oeb[11] , \mprj_io_oeb[12] , \mprj_io_oeb[13] , \mprj_io_oeb[14] , \mprj_io_oeb[15] , \mprj_io_oeb[16] , \mprj_io_oeb[17] , \mprj_io_oeb[18] , \mprj_io_oeb[19] , \mprj_io_oeb[20] , \mprj_io_oeb[21] , \mprj_io_oeb[22] , \mprj_io_oeb[23] , \mprj_io_oeb[24] , \mprj_io_oeb[25] , \mprj_io_oeb[26] , \mprj_io_oeb[27] , \mprj_io_oeb[28] , \mprj_io_oeb[29] , \mprj_io_oeb[30] , \mprj_io_oeb[31] , \mprj_io_oeb[32] , \mprj_io_oeb[33] , \mprj_io_oeb[34] , \mprj_io_oeb[35] , \mprj_io_oeb[36] , \mprj_io_oeb[37] , \mprj_io_hldh_n[0] , \mprj_io_hldh_n[1] , \mprj_io_hldh_n[2] , \mprj_io_hldh_n[3] , \mprj_io_hldh_n[4] , \mprj_io_hldh_n[5] , \mprj_io_hldh_n[6] , \mprj_io_hldh_n[7] , \mprj_io_hldh_n[8] , \mprj_io_hldh_n[9] , \mprj_io_hldh_n[10] , \mprj_io_hldh_n[11] , \mprj_io_hldh_n[12] , \mprj_io_hldh_n[13] , \mprj_io_hldh_n[14] , \mprj_io_hldh_n[15] , \mprj_io_hldh_n[16] , \mprj_io_hldh_n[17] , \mprj_io_hldh_n[18] , \mprj_io_hldh_n[19] , \mprj_io_hldh_n[20] , \mprj_io_hldh_n[21] , \mprj_io_hldh_n[22] , \mprj_io_hldh_n[23] , \mprj_io_hldh_n[24] , \mprj_io_hldh_n[25] , \mprj_io_hldh_n[26] , \mprj_io_hldh_n[27] , \mprj_io_hldh_n[28] , \mprj_io_hldh_n[29] , \mprj_io_hldh_n[30] , \mprj_io_hldh_n[31] , \mprj_io_hldh_n[32] , \mprj_io_hldh_n[33] , \mprj_io_hldh_n[34] , \mprj_io_hldh_n[35] , \mprj_io_hldh_n[36] , \mprj_io_hldh_n[37] , \mprj_io_enh[0] , \mprj_io_enh[1] , \mprj_io_enh[2] , \mprj_io_enh[3] , \mprj_io_enh[4] , \mprj_io_enh[5] , \mprj_io_enh[6] , \mprj_io_enh[7] , \mprj_io_enh[8] , \mprj_io_enh[9] , \mprj_io_enh[10] , \mprj_io_enh[11] , \mprj_io_enh[12] , \mprj_io_enh[13] , \mprj_io_enh[14] , \mprj_io_enh[15] , \mprj_io_enh[16] , \mprj_io_enh[17] , \mprj_io_enh[18] , \mprj_io_enh[19] , \mprj_io_enh[20] , \mprj_io_enh[21] , \mprj_io_enh[22] , \mprj_io_enh[23] , \mprj_io_enh[24] , \mprj_io_enh[25] , \mprj_io_enh[26] , \mprj_io_enh[27] , \mprj_io_enh[28] , \mprj_io_enh[29] , \mprj_io_enh[30] , \mprj_io_enh[31] , \mprj_io_enh[32] , \mprj_io_enh[33] , \mprj_io_enh[34] , \mprj_io_enh[35] , \mprj_io_enh[36] , \mprj_io_enh[37] , \mprj_io_inp_dis[0] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[37] , \mprj_io_ib_mode_sel[0] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[37] , \mprj_io_vtrip_sel[0] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[37] , \mprj_io_slow_sel[0] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[37] , \mprj_io_holdover[0] , \mprj_io_holdover[1] , \mprj_io_holdover[2] , \mprj_io_holdover[3] , \mprj_io_holdover[4] , \mprj_io_holdover[5] , \mprj_io_holdover[6] , \mprj_io_holdover[7] , \mprj_io_holdover[8] , \mprj_io_holdover[9] , \mprj_io_holdover[10] , \mprj_io_holdover[11] , \mprj_io_holdover[12] , \mprj_io_holdover[13] , \mprj_io_holdover[14] , \mprj_io_holdover[15] , \mprj_io_holdover[16] , \mprj_io_holdover[17] , \mprj_io_holdover[18] , \mprj_io_holdover[19] , \mprj_io_holdover[20] , \mprj_io_holdover[21] , \mprj_io_holdover[22] , \mprj_io_holdover[23] , \mprj_io_holdover[24] , \mprj_io_holdover[25] , \mprj_io_holdover[26] , \mprj_io_holdover[27] , \mprj_io_holdover[28] , \mprj_io_holdover[29] , \mprj_io_holdover[30] , \mprj_io_holdover[31] , \mprj_io_holdover[32] , \mprj_io_holdover[33] , \mprj_io_holdover[34] , \mprj_io_holdover[35] , \mprj_io_holdover[36] , \mprj_io_holdover[37] , \mprj_io_analog_en[0] , \mprj_io_analog_en[1] , \mprj_io_analog_en[2] , \mprj_io_analog_en[3] , \mprj_io_analog_en[4] , \mprj_io_analog_en[5] , \mprj_io_analog_en[6] , \mprj_io_analog_en[7] , \mprj_io_analog_en[8] , \mprj_io_analog_en[9] , \mprj_io_analog_en[10] , \mprj_io_analog_en[11] , \mprj_io_analog_en[12] , \mprj_io_analog_en[13] , \mprj_io_analog_en[14] , \mprj_io_analog_en[15] , \mprj_io_analog_en[16] , \mprj_io_analog_en[17] , \mprj_io_analog_en[18] , \mprj_io_analog_en[19] , \mprj_io_analog_en[20] , \mprj_io_analog_en[21] , \mprj_io_analog_en[22] , \mprj_io_analog_en[23] , \mprj_io_analog_en[24] , \mprj_io_analog_en[25] , \mprj_io_analog_en[26] , \mprj_io_analog_en[27] , \mprj_io_analog_en[28] , \mprj_io_analog_en[29] , \mprj_io_analog_en[30] , \mprj_io_analog_en[31] , \mprj_io_analog_en[32] , \mprj_io_analog_en[33] , \mprj_io_analog_en[34] , \mprj_io_analog_en[35] , \mprj_io_analog_en[36] , \mprj_io_analog_en[37] , \mprj_io_analog_sel[0] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[37] , \mprj_io_analog_pol[0] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[37] , \mprj_io_dm[0] , \mprj_io_dm[1] , \mprj_io_dm[2] , \mprj_io_dm[3] , \mprj_io_dm[4] , \mprj_io_dm[5] , \mprj_io_dm[6] , \mprj_io_dm[7] , \mprj_io_dm[8] , \mprj_io_dm[9] , \mprj_io_dm[10] , \mprj_io_dm[11] , \mprj_io_dm[12] , \mprj_io_dm[13] , \mprj_io_dm[14] , \mprj_io_dm[15] , \mprj_io_dm[16] , \mprj_io_dm[17] , \mprj_io_dm[18] , \mprj_io_dm[19] , \mprj_io_dm[20] , \mprj_io_dm[21] , \mprj_io_dm[22] , \mprj_io_dm[23] , \mprj_io_dm[24] , \mprj_io_dm[25] , \mprj_io_dm[26] , \mprj_io_dm[27] , \mprj_io_dm[28] , \mprj_io_dm[29] , \mprj_io_dm[30] , \mprj_io_dm[31] , \mprj_io_dm[32] , \mprj_io_dm[33] , \mprj_io_dm[34] , \mprj_io_dm[35] , \mprj_io_dm[36] , \mprj_io_dm[37] , \mprj_io_dm[38] , \mprj_io_dm[39] , \mprj_io_dm[40] , \mprj_io_dm[41] , \mprj_io_dm[42] , \mprj_io_dm[43] , \mprj_io_dm[44] , \mprj_io_dm[45] , \mprj_io_dm[46] , \mprj_io_dm[47] , \mprj_io_dm[48] , \mprj_io_dm[49] , \mprj_io_dm[50] , \mprj_io_dm[51] , \mprj_io_dm[52] , \mprj_io_dm[53] , \mprj_io_dm[54] , \mprj_io_dm[55] , \mprj_io_dm[56] , \mprj_io_dm[57] , \mprj_io_dm[58] , \mprj_io_dm[59] , \mprj_io_dm[60] , \mprj_io_dm[61] , \mprj_io_dm[62] , \mprj_io_dm[63] , \mprj_io_dm[64] , \mprj_io_dm[65] , \mprj_io_dm[66] , \mprj_io_dm[67] , \mprj_io_dm[68] , \mprj_io_dm[69] , \mprj_io_dm[70] , \mprj_io_dm[71] , \mprj_io_dm[72] , \mprj_io_dm[73] , \mprj_io_dm[74] , \mprj_io_dm[75] , \mprj_io_dm[76] , \mprj_io_dm[77] , \mprj_io_dm[78] , \mprj_io_dm[79] , \mprj_io_dm[80] , \mprj_io_dm[81] , \mprj_io_dm[82] , \mprj_io_dm[83] , \mprj_io_dm[84] , \mprj_io_dm[85] , \mprj_io_dm[86] , \mprj_io_dm[87] , \mprj_io_dm[88] , \mprj_io_dm[89] , \mprj_io_dm[90] , \mprj_io_dm[91] , \mprj_io_dm[92] , \mprj_io_dm[93] , \mprj_io_dm[94] , \mprj_io_dm[95] , \mprj_io_dm[96] , \mprj_io_dm[97] , \mprj_io_dm[98] , \mprj_io_dm[99] , \mprj_io_dm[100] , \mprj_io_dm[101] , \mprj_io_dm[102] , \mprj_io_dm[103] , \mprj_io_dm[104] , \mprj_io_dm[105] , \mprj_io_dm[106] , \mprj_io_dm[107] , \mprj_io_dm[108] , \mprj_io_dm[109] , \mprj_io_dm[110] , \mprj_io_dm[111] , \mprj_io_dm[112] , \mprj_io_dm[113] , \mprj_io_in[0] , \mprj_io_in[1] , \mprj_io_in[2] , \mprj_io_in[3] , \mprj_io_in[4] , \mprj_io_in[5] , \mprj_io_in[6] , \mprj_io_in[7] , \mprj_io_in[8] , \mprj_io_in[9] , \mprj_io_in[10] , \mprj_io_in[11] , \mprj_io_in[12] , \mprj_io_in[13] , \mprj_io_in[14] , \mprj_io_in[15] , \mprj_io_in[16] , \mprj_io_in[17] , \mprj_io_in[18] , \mprj_io_in[19] , \mprj_io_in[20] , \mprj_io_in[21] , \mprj_io_in[22] , \mprj_io_in[23] , \mprj_io_in[24] , \mprj_io_in[25] , \mprj_io_in[26] , \mprj_io_in[27] , \mprj_io_in[28] , \mprj_io_in[29] , \mprj_io_in[30] , \mprj_io_in[31] , \mprj_io_in[32] , \mprj_io_in[33] , \mprj_io_in[34] , \mprj_io_in[35] , \mprj_io_in[36] , \mprj_io_in[37] , \mprj_analog_io[0] , \mprj_analog_io[1] , \mprj_analog_io[2] , \mprj_analog_io[3] , \mprj_analog_io[4] , \mprj_analog_io[5] , \mprj_analog_io[6] , \mprj_analog_io[7] , \mprj_analog_io[8] , \mprj_analog_io[9] , \mprj_analog_io[10] , \mprj_analog_io[11] , \mprj_analog_io[12] , \mprj_analog_io[13] , \mprj_analog_io[14] , \mprj_analog_io[15] , \mprj_analog_io[16] , \mprj_analog_io[17] , \mprj_analog_io[18] , \mprj_analog_io[19] , \mprj_analog_io[20] , \mprj_analog_io[21] , \mprj_analog_io[22] , \mprj_analog_io[23] , \mprj_analog_io[24] , \mprj_analog_io[25] , \mprj_analog_io[26] , \mprj_analog_io[27] , \mprj_analog_io[28] , \mprj_analog_io[29] , \mprj_analog_io[30] );
+  wire analog_a;
+  wire analog_b;
+  input clock;
+  output clock_core;
+  wire \dm_all[0] ;
+  wire \dm_all[1] ;
+  wire \dm_all[2] ;
+  output flash_clk;
+  input flash_clk_core;
+  input flash_clk_ieb_core;
+  input flash_clk_oeb_core;
+  output flash_csb;
+  input flash_csb_core;
+  input flash_csb_ieb_core;
+  input flash_csb_oeb_core;
+  inout flash_io0;
+  output flash_io0_di_core;
+  input flash_io0_do_core;
+  input flash_io0_ieb_core;
+  wire \flash_io0_mode[0] ;
+  wire \flash_io0_mode[1] ;
+  wire \flash_io0_mode[2] ;
+  input flash_io0_oeb_core;
+  inout flash_io1;
+  output flash_io1_di_core;
+  input flash_io1_do_core;
+  input flash_io1_ieb_core;
+  wire \flash_io1_mode[0] ;
+  wire \flash_io1_mode[1] ;
+  wire \flash_io1_mode[2] ;
+  input flash_io1_oeb_core;
+  inout gpio;
+  output gpio_in_core;
+  input gpio_inenb_core;
+  input gpio_mode0_core;
+  input gpio_mode1_core;
+  input gpio_out_core;
+  input gpio_outenb_core;
+  wire loop_clock;
+  wire loop_flash_clk;
+  wire loop_flash_csb;
+  wire loop_flash_io0;
+  wire loop_flash_io1;
+  wire loop_gpio;
+  inout \mprj_analog_io[0] ;
+  inout \mprj_analog_io[10] ;
+  inout \mprj_analog_io[11] ;
+  inout \mprj_analog_io[12] ;
+  inout \mprj_analog_io[13] ;
+  inout \mprj_analog_io[14] ;
+  inout \mprj_analog_io[15] ;
+  inout \mprj_analog_io[16] ;
+  inout \mprj_analog_io[17] ;
+  inout \mprj_analog_io[18] ;
+  inout \mprj_analog_io[19] ;
+  inout \mprj_analog_io[1] ;
+  inout \mprj_analog_io[20] ;
+  inout \mprj_analog_io[21] ;
+  inout \mprj_analog_io[22] ;
+  inout \mprj_analog_io[23] ;
+  inout \mprj_analog_io[24] ;
+  inout \mprj_analog_io[25] ;
+  inout \mprj_analog_io[26] ;
+  inout \mprj_analog_io[27] ;
+  inout \mprj_analog_io[28] ;
+  inout \mprj_analog_io[29] ;
+  inout \mprj_analog_io[2] ;
+  inout \mprj_analog_io[30] ;
+  inout \mprj_analog_io[3] ;
+  inout \mprj_analog_io[4] ;
+  inout \mprj_analog_io[5] ;
+  inout \mprj_analog_io[6] ;
+  inout \mprj_analog_io[7] ;
+  inout \mprj_analog_io[8] ;
+  inout \mprj_analog_io[9] ;
+  inout \mprj_io[0] ;
+  inout \mprj_io[10] ;
+  inout \mprj_io[11] ;
+  inout \mprj_io[12] ;
+  inout \mprj_io[13] ;
+  inout \mprj_io[14] ;
+  inout \mprj_io[15] ;
+  inout \mprj_io[16] ;
+  inout \mprj_io[17] ;
+  inout \mprj_io[18] ;
+  inout \mprj_io[19] ;
+  inout \mprj_io[1] ;
+  inout \mprj_io[20] ;
+  inout \mprj_io[21] ;
+  inout \mprj_io[22] ;
+  inout \mprj_io[23] ;
+  inout \mprj_io[24] ;
+  inout \mprj_io[25] ;
+  inout \mprj_io[26] ;
+  inout \mprj_io[27] ;
+  inout \mprj_io[28] ;
+  inout \mprj_io[29] ;
+  inout \mprj_io[2] ;
+  inout \mprj_io[30] ;
+  inout \mprj_io[31] ;
+  inout \mprj_io[32] ;
+  inout \mprj_io[33] ;
+  inout \mprj_io[34] ;
+  inout \mprj_io[35] ;
+  inout \mprj_io[36] ;
+  inout \mprj_io[37] ;
+  inout \mprj_io[3] ;
+  inout \mprj_io[4] ;
+  inout \mprj_io[5] ;
+  inout \mprj_io[6] ;
+  inout \mprj_io[7] ;
+  inout \mprj_io[8] ;
+  inout \mprj_io[9] ;
+  input \mprj_io_analog_en[0] ;
+  input \mprj_io_analog_en[10] ;
+  input \mprj_io_analog_en[11] ;
+  input \mprj_io_analog_en[12] ;
+  input \mprj_io_analog_en[13] ;
+  input \mprj_io_analog_en[14] ;
+  input \mprj_io_analog_en[15] ;
+  input \mprj_io_analog_en[16] ;
+  input \mprj_io_analog_en[17] ;
+  input \mprj_io_analog_en[18] ;
+  input \mprj_io_analog_en[19] ;
+  input \mprj_io_analog_en[1] ;
+  input \mprj_io_analog_en[20] ;
+  input \mprj_io_analog_en[21] ;
+  input \mprj_io_analog_en[22] ;
+  input \mprj_io_analog_en[23] ;
+  input \mprj_io_analog_en[24] ;
+  input \mprj_io_analog_en[25] ;
+  input \mprj_io_analog_en[26] ;
+  input \mprj_io_analog_en[27] ;
+  input \mprj_io_analog_en[28] ;
+  input \mprj_io_analog_en[29] ;
+  input \mprj_io_analog_en[2] ;
+  input \mprj_io_analog_en[30] ;
+  input \mprj_io_analog_en[31] ;
+  input \mprj_io_analog_en[32] ;
+  input \mprj_io_analog_en[33] ;
+  input \mprj_io_analog_en[34] ;
+  input \mprj_io_analog_en[35] ;
+  input \mprj_io_analog_en[36] ;
+  input \mprj_io_analog_en[37] ;
+  input \mprj_io_analog_en[3] ;
+  input \mprj_io_analog_en[4] ;
+  input \mprj_io_analog_en[5] ;
+  input \mprj_io_analog_en[6] ;
+  input \mprj_io_analog_en[7] ;
+  input \mprj_io_analog_en[8] ;
+  input \mprj_io_analog_en[9] ;
+  input \mprj_io_analog_pol[0] ;
+  input \mprj_io_analog_pol[10] ;
+  input \mprj_io_analog_pol[11] ;
+  input \mprj_io_analog_pol[12] ;
+  input \mprj_io_analog_pol[13] ;
+  input \mprj_io_analog_pol[14] ;
+  input \mprj_io_analog_pol[15] ;
+  input \mprj_io_analog_pol[16] ;
+  input \mprj_io_analog_pol[17] ;
+  input \mprj_io_analog_pol[18] ;
+  input \mprj_io_analog_pol[19] ;
+  input \mprj_io_analog_pol[1] ;
+  input \mprj_io_analog_pol[20] ;
+  input \mprj_io_analog_pol[21] ;
+  input \mprj_io_analog_pol[22] ;
+  input \mprj_io_analog_pol[23] ;
+  input \mprj_io_analog_pol[24] ;
+  input \mprj_io_analog_pol[25] ;
+  input \mprj_io_analog_pol[26] ;
+  input \mprj_io_analog_pol[27] ;
+  input \mprj_io_analog_pol[28] ;
+  input \mprj_io_analog_pol[29] ;
+  input \mprj_io_analog_pol[2] ;
+  input \mprj_io_analog_pol[30] ;
+  input \mprj_io_analog_pol[31] ;
+  input \mprj_io_analog_pol[32] ;
+  input \mprj_io_analog_pol[33] ;
+  input \mprj_io_analog_pol[34] ;
+  input \mprj_io_analog_pol[35] ;
+  input \mprj_io_analog_pol[36] ;
+  input \mprj_io_analog_pol[37] ;
+  input \mprj_io_analog_pol[3] ;
+  input \mprj_io_analog_pol[4] ;
+  input \mprj_io_analog_pol[5] ;
+  input \mprj_io_analog_pol[6] ;
+  input \mprj_io_analog_pol[7] ;
+  input \mprj_io_analog_pol[8] ;
+  input \mprj_io_analog_pol[9] ;
+  input \mprj_io_analog_sel[0] ;
+  input \mprj_io_analog_sel[10] ;
+  input \mprj_io_analog_sel[11] ;
+  input \mprj_io_analog_sel[12] ;
+  input \mprj_io_analog_sel[13] ;
+  input \mprj_io_analog_sel[14] ;
+  input \mprj_io_analog_sel[15] ;
+  input \mprj_io_analog_sel[16] ;
+  input \mprj_io_analog_sel[17] ;
+  input \mprj_io_analog_sel[18] ;
+  input \mprj_io_analog_sel[19] ;
+  input \mprj_io_analog_sel[1] ;
+  input \mprj_io_analog_sel[20] ;
+  input \mprj_io_analog_sel[21] ;
+  input \mprj_io_analog_sel[22] ;
+  input \mprj_io_analog_sel[23] ;
+  input \mprj_io_analog_sel[24] ;
+  input \mprj_io_analog_sel[25] ;
+  input \mprj_io_analog_sel[26] ;
+  input \mprj_io_analog_sel[27] ;
+  input \mprj_io_analog_sel[28] ;
+  input \mprj_io_analog_sel[29] ;
+  input \mprj_io_analog_sel[2] ;
+  input \mprj_io_analog_sel[30] ;
+  input \mprj_io_analog_sel[31] ;
+  input \mprj_io_analog_sel[32] ;
+  input \mprj_io_analog_sel[33] ;
+  input \mprj_io_analog_sel[34] ;
+  input \mprj_io_analog_sel[35] ;
+  input \mprj_io_analog_sel[36] ;
+  input \mprj_io_analog_sel[37] ;
+  input \mprj_io_analog_sel[3] ;
+  input \mprj_io_analog_sel[4] ;
+  input \mprj_io_analog_sel[5] ;
+  input \mprj_io_analog_sel[6] ;
+  input \mprj_io_analog_sel[7] ;
+  input \mprj_io_analog_sel[8] ;
+  input \mprj_io_analog_sel[9] ;
+  input \mprj_io_dm[0] ;
+  input \mprj_io_dm[100] ;
+  input \mprj_io_dm[101] ;
+  input \mprj_io_dm[102] ;
+  input \mprj_io_dm[103] ;
+  input \mprj_io_dm[104] ;
+  input \mprj_io_dm[105] ;
+  input \mprj_io_dm[106] ;
+  input \mprj_io_dm[107] ;
+  input \mprj_io_dm[108] ;
+  input \mprj_io_dm[109] ;
+  input \mprj_io_dm[10] ;
+  input \mprj_io_dm[110] ;
+  input \mprj_io_dm[111] ;
+  input \mprj_io_dm[112] ;
+  input \mprj_io_dm[113] ;
+  input \mprj_io_dm[11] ;
+  input \mprj_io_dm[12] ;
+  input \mprj_io_dm[13] ;
+  input \mprj_io_dm[14] ;
+  input \mprj_io_dm[15] ;
+  input \mprj_io_dm[16] ;
+  input \mprj_io_dm[17] ;
+  input \mprj_io_dm[18] ;
+  input \mprj_io_dm[19] ;
+  input \mprj_io_dm[1] ;
+  input \mprj_io_dm[20] ;
+  input \mprj_io_dm[21] ;
+  input \mprj_io_dm[22] ;
+  input \mprj_io_dm[23] ;
+  input \mprj_io_dm[24] ;
+  input \mprj_io_dm[25] ;
+  input \mprj_io_dm[26] ;
+  input \mprj_io_dm[27] ;
+  input \mprj_io_dm[28] ;
+  input \mprj_io_dm[29] ;
+  input \mprj_io_dm[2] ;
+  input \mprj_io_dm[30] ;
+  input \mprj_io_dm[31] ;
+  input \mprj_io_dm[32] ;
+  input \mprj_io_dm[33] ;
+  input \mprj_io_dm[34] ;
+  input \mprj_io_dm[35] ;
+  input \mprj_io_dm[36] ;
+  input \mprj_io_dm[37] ;
+  input \mprj_io_dm[38] ;
+  input \mprj_io_dm[39] ;
+  input \mprj_io_dm[3] ;
+  input \mprj_io_dm[40] ;
+  input \mprj_io_dm[41] ;
+  input \mprj_io_dm[42] ;
+  input \mprj_io_dm[43] ;
+  input \mprj_io_dm[44] ;
+  input \mprj_io_dm[45] ;
+  input \mprj_io_dm[46] ;
+  input \mprj_io_dm[47] ;
+  input \mprj_io_dm[48] ;
+  input \mprj_io_dm[49] ;
+  input \mprj_io_dm[4] ;
+  input \mprj_io_dm[50] ;
+  input \mprj_io_dm[51] ;
+  input \mprj_io_dm[52] ;
+  input \mprj_io_dm[53] ;
+  input \mprj_io_dm[54] ;
+  input \mprj_io_dm[55] ;
+  input \mprj_io_dm[56] ;
+  input \mprj_io_dm[57] ;
+  input \mprj_io_dm[58] ;
+  input \mprj_io_dm[59] ;
+  input \mprj_io_dm[5] ;
+  input \mprj_io_dm[60] ;
+  input \mprj_io_dm[61] ;
+  input \mprj_io_dm[62] ;
+  input \mprj_io_dm[63] ;
+  input \mprj_io_dm[64] ;
+  input \mprj_io_dm[65] ;
+  input \mprj_io_dm[66] ;
+  input \mprj_io_dm[67] ;
+  input \mprj_io_dm[68] ;
+  input \mprj_io_dm[69] ;
+  input \mprj_io_dm[6] ;
+  input \mprj_io_dm[70] ;
+  input \mprj_io_dm[71] ;
+  input \mprj_io_dm[72] ;
+  input \mprj_io_dm[73] ;
+  input \mprj_io_dm[74] ;
+  input \mprj_io_dm[75] ;
+  input \mprj_io_dm[76] ;
+  input \mprj_io_dm[77] ;
+  input \mprj_io_dm[78] ;
+  input \mprj_io_dm[79] ;
+  input \mprj_io_dm[7] ;
+  input \mprj_io_dm[80] ;
+  input \mprj_io_dm[81] ;
+  input \mprj_io_dm[82] ;
+  input \mprj_io_dm[83] ;
+  input \mprj_io_dm[84] ;
+  input \mprj_io_dm[85] ;
+  input \mprj_io_dm[86] ;
+  input \mprj_io_dm[87] ;
+  input \mprj_io_dm[88] ;
+  input \mprj_io_dm[89] ;
+  input \mprj_io_dm[8] ;
+  input \mprj_io_dm[90] ;
+  input \mprj_io_dm[91] ;
+  input \mprj_io_dm[92] ;
+  input \mprj_io_dm[93] ;
+  input \mprj_io_dm[94] ;
+  input \mprj_io_dm[95] ;
+  input \mprj_io_dm[96] ;
+  input \mprj_io_dm[97] ;
+  input \mprj_io_dm[98] ;
+  input \mprj_io_dm[99] ;
+  input \mprj_io_dm[9] ;
+  input \mprj_io_enh[0] ;
+  input \mprj_io_enh[10] ;
+  input \mprj_io_enh[11] ;
+  input \mprj_io_enh[12] ;
+  input \mprj_io_enh[13] ;
+  input \mprj_io_enh[14] ;
+  input \mprj_io_enh[15] ;
+  input \mprj_io_enh[16] ;
+  input \mprj_io_enh[17] ;
+  input \mprj_io_enh[18] ;
+  input \mprj_io_enh[19] ;
+  input \mprj_io_enh[1] ;
+  input \mprj_io_enh[20] ;
+  input \mprj_io_enh[21] ;
+  input \mprj_io_enh[22] ;
+  input \mprj_io_enh[23] ;
+  input \mprj_io_enh[24] ;
+  input \mprj_io_enh[25] ;
+  input \mprj_io_enh[26] ;
+  input \mprj_io_enh[27] ;
+  input \mprj_io_enh[28] ;
+  input \mprj_io_enh[29] ;
+  input \mprj_io_enh[2] ;
+  input \mprj_io_enh[30] ;
+  input \mprj_io_enh[31] ;
+  input \mprj_io_enh[32] ;
+  input \mprj_io_enh[33] ;
+  input \mprj_io_enh[34] ;
+  input \mprj_io_enh[35] ;
+  input \mprj_io_enh[36] ;
+  input \mprj_io_enh[37] ;
+  input \mprj_io_enh[3] ;
+  input \mprj_io_enh[4] ;
+  input \mprj_io_enh[5] ;
+  input \mprj_io_enh[6] ;
+  input \mprj_io_enh[7] ;
+  input \mprj_io_enh[8] ;
+  input \mprj_io_enh[9] ;
+  input \mprj_io_hldh_n[0] ;
+  input \mprj_io_hldh_n[10] ;
+  input \mprj_io_hldh_n[11] ;
+  input \mprj_io_hldh_n[12] ;
+  input \mprj_io_hldh_n[13] ;
+  input \mprj_io_hldh_n[14] ;
+  input \mprj_io_hldh_n[15] ;
+  input \mprj_io_hldh_n[16] ;
+  input \mprj_io_hldh_n[17] ;
+  input \mprj_io_hldh_n[18] ;
+  input \mprj_io_hldh_n[19] ;
+  input \mprj_io_hldh_n[1] ;
+  input \mprj_io_hldh_n[20] ;
+  input \mprj_io_hldh_n[21] ;
+  input \mprj_io_hldh_n[22] ;
+  input \mprj_io_hldh_n[23] ;
+  input \mprj_io_hldh_n[24] ;
+  input \mprj_io_hldh_n[25] ;
+  input \mprj_io_hldh_n[26] ;
+  input \mprj_io_hldh_n[27] ;
+  input \mprj_io_hldh_n[28] ;
+  input \mprj_io_hldh_n[29] ;
+  input \mprj_io_hldh_n[2] ;
+  input \mprj_io_hldh_n[30] ;
+  input \mprj_io_hldh_n[31] ;
+  input \mprj_io_hldh_n[32] ;
+  input \mprj_io_hldh_n[33] ;
+  input \mprj_io_hldh_n[34] ;
+  input \mprj_io_hldh_n[35] ;
+  input \mprj_io_hldh_n[36] ;
+  input \mprj_io_hldh_n[37] ;
+  input \mprj_io_hldh_n[3] ;
+  input \mprj_io_hldh_n[4] ;
+  input \mprj_io_hldh_n[5] ;
+  input \mprj_io_hldh_n[6] ;
+  input \mprj_io_hldh_n[7] ;
+  input \mprj_io_hldh_n[8] ;
+  input \mprj_io_hldh_n[9] ;
+  input \mprj_io_holdover[0] ;
+  input \mprj_io_holdover[10] ;
+  input \mprj_io_holdover[11] ;
+  input \mprj_io_holdover[12] ;
+  input \mprj_io_holdover[13] ;
+  input \mprj_io_holdover[14] ;
+  input \mprj_io_holdover[15] ;
+  input \mprj_io_holdover[16] ;
+  input \mprj_io_holdover[17] ;
+  input \mprj_io_holdover[18] ;
+  input \mprj_io_holdover[19] ;
+  input \mprj_io_holdover[1] ;
+  input \mprj_io_holdover[20] ;
+  input \mprj_io_holdover[21] ;
+  input \mprj_io_holdover[22] ;
+  input \mprj_io_holdover[23] ;
+  input \mprj_io_holdover[24] ;
+  input \mprj_io_holdover[25] ;
+  input \mprj_io_holdover[26] ;
+  input \mprj_io_holdover[27] ;
+  input \mprj_io_holdover[28] ;
+  input \mprj_io_holdover[29] ;
+  input \mprj_io_holdover[2] ;
+  input \mprj_io_holdover[30] ;
+  input \mprj_io_holdover[31] ;
+  input \mprj_io_holdover[32] ;
+  input \mprj_io_holdover[33] ;
+  input \mprj_io_holdover[34] ;
+  input \mprj_io_holdover[35] ;
+  input \mprj_io_holdover[36] ;
+  input \mprj_io_holdover[37] ;
+  input \mprj_io_holdover[3] ;
+  input \mprj_io_holdover[4] ;
+  input \mprj_io_holdover[5] ;
+  input \mprj_io_holdover[6] ;
+  input \mprj_io_holdover[7] ;
+  input \mprj_io_holdover[8] ;
+  input \mprj_io_holdover[9] ;
+  input \mprj_io_ib_mode_sel[0] ;
+  input \mprj_io_ib_mode_sel[10] ;
+  input \mprj_io_ib_mode_sel[11] ;
+  input \mprj_io_ib_mode_sel[12] ;
+  input \mprj_io_ib_mode_sel[13] ;
+  input \mprj_io_ib_mode_sel[14] ;
+  input \mprj_io_ib_mode_sel[15] ;
+  input \mprj_io_ib_mode_sel[16] ;
+  input \mprj_io_ib_mode_sel[17] ;
+  input \mprj_io_ib_mode_sel[18] ;
+  input \mprj_io_ib_mode_sel[19] ;
+  input \mprj_io_ib_mode_sel[1] ;
+  input \mprj_io_ib_mode_sel[20] ;
+  input \mprj_io_ib_mode_sel[21] ;
+  input \mprj_io_ib_mode_sel[22] ;
+  input \mprj_io_ib_mode_sel[23] ;
+  input \mprj_io_ib_mode_sel[24] ;
+  input \mprj_io_ib_mode_sel[25] ;
+  input \mprj_io_ib_mode_sel[26] ;
+  input \mprj_io_ib_mode_sel[27] ;
+  input \mprj_io_ib_mode_sel[28] ;
+  input \mprj_io_ib_mode_sel[29] ;
+  input \mprj_io_ib_mode_sel[2] ;
+  input \mprj_io_ib_mode_sel[30] ;
+  input \mprj_io_ib_mode_sel[31] ;
+  input \mprj_io_ib_mode_sel[32] ;
+  input \mprj_io_ib_mode_sel[33] ;
+  input \mprj_io_ib_mode_sel[34] ;
+  input \mprj_io_ib_mode_sel[35] ;
+  input \mprj_io_ib_mode_sel[36] ;
+  input \mprj_io_ib_mode_sel[37] ;
+  input \mprj_io_ib_mode_sel[3] ;
+  input \mprj_io_ib_mode_sel[4] ;
+  input \mprj_io_ib_mode_sel[5] ;
+  input \mprj_io_ib_mode_sel[6] ;
+  input \mprj_io_ib_mode_sel[7] ;
+  input \mprj_io_ib_mode_sel[8] ;
+  input \mprj_io_ib_mode_sel[9] ;
+  output \mprj_io_in[0] ;
+  output \mprj_io_in[10] ;
+  output \mprj_io_in[11] ;
+  output \mprj_io_in[12] ;
+  output \mprj_io_in[13] ;
+  output \mprj_io_in[14] ;
+  output \mprj_io_in[15] ;
+  output \mprj_io_in[16] ;
+  output \mprj_io_in[17] ;
+  output \mprj_io_in[18] ;
+  output \mprj_io_in[19] ;
+  output \mprj_io_in[1] ;
+  output \mprj_io_in[20] ;
+  output \mprj_io_in[21] ;
+  output \mprj_io_in[22] ;
+  output \mprj_io_in[23] ;
+  output \mprj_io_in[24] ;
+  output \mprj_io_in[25] ;
+  output \mprj_io_in[26] ;
+  output \mprj_io_in[27] ;
+  output \mprj_io_in[28] ;
+  output \mprj_io_in[29] ;
+  output \mprj_io_in[2] ;
+  output \mprj_io_in[30] ;
+  output \mprj_io_in[31] ;
+  output \mprj_io_in[32] ;
+  output \mprj_io_in[33] ;
+  output \mprj_io_in[34] ;
+  output \mprj_io_in[35] ;
+  output \mprj_io_in[36] ;
+  output \mprj_io_in[37] ;
+  output \mprj_io_in[3] ;
+  output \mprj_io_in[4] ;
+  output \mprj_io_in[5] ;
+  output \mprj_io_in[6] ;
+  output \mprj_io_in[7] ;
+  output \mprj_io_in[8] ;
+  output \mprj_io_in[9] ;
+  input \mprj_io_inp_dis[0] ;
+  input \mprj_io_inp_dis[10] ;
+  input \mprj_io_inp_dis[11] ;
+  input \mprj_io_inp_dis[12] ;
+  input \mprj_io_inp_dis[13] ;
+  input \mprj_io_inp_dis[14] ;
+  input \mprj_io_inp_dis[15] ;
+  input \mprj_io_inp_dis[16] ;
+  input \mprj_io_inp_dis[17] ;
+  input \mprj_io_inp_dis[18] ;
+  input \mprj_io_inp_dis[19] ;
+  input \mprj_io_inp_dis[1] ;
+  input \mprj_io_inp_dis[20] ;
+  input \mprj_io_inp_dis[21] ;
+  input \mprj_io_inp_dis[22] ;
+  input \mprj_io_inp_dis[23] ;
+  input \mprj_io_inp_dis[24] ;
+  input \mprj_io_inp_dis[25] ;
+  input \mprj_io_inp_dis[26] ;
+  input \mprj_io_inp_dis[27] ;
+  input \mprj_io_inp_dis[28] ;
+  input \mprj_io_inp_dis[29] ;
+  input \mprj_io_inp_dis[2] ;
+  input \mprj_io_inp_dis[30] ;
+  input \mprj_io_inp_dis[31] ;
+  input \mprj_io_inp_dis[32] ;
+  input \mprj_io_inp_dis[33] ;
+  input \mprj_io_inp_dis[34] ;
+  input \mprj_io_inp_dis[35] ;
+  input \mprj_io_inp_dis[36] ;
+  input \mprj_io_inp_dis[37] ;
+  input \mprj_io_inp_dis[3] ;
+  input \mprj_io_inp_dis[4] ;
+  input \mprj_io_inp_dis[5] ;
+  input \mprj_io_inp_dis[6] ;
+  input \mprj_io_inp_dis[7] ;
+  input \mprj_io_inp_dis[8] ;
+  input \mprj_io_inp_dis[9] ;
+  input \mprj_io_oeb[0] ;
+  input \mprj_io_oeb[10] ;
+  input \mprj_io_oeb[11] ;
+  input \mprj_io_oeb[12] ;
+  input \mprj_io_oeb[13] ;
+  input \mprj_io_oeb[14] ;
+  input \mprj_io_oeb[15] ;
+  input \mprj_io_oeb[16] ;
+  input \mprj_io_oeb[17] ;
+  input \mprj_io_oeb[18] ;
+  input \mprj_io_oeb[19] ;
+  input \mprj_io_oeb[1] ;
+  input \mprj_io_oeb[20] ;
+  input \mprj_io_oeb[21] ;
+  input \mprj_io_oeb[22] ;
+  input \mprj_io_oeb[23] ;
+  input \mprj_io_oeb[24] ;
+  input \mprj_io_oeb[25] ;
+  input \mprj_io_oeb[26] ;
+  input \mprj_io_oeb[27] ;
+  input \mprj_io_oeb[28] ;
+  input \mprj_io_oeb[29] ;
+  input \mprj_io_oeb[2] ;
+  input \mprj_io_oeb[30] ;
+  input \mprj_io_oeb[31] ;
+  input \mprj_io_oeb[32] ;
+  input \mprj_io_oeb[33] ;
+  input \mprj_io_oeb[34] ;
+  input \mprj_io_oeb[35] ;
+  input \mprj_io_oeb[36] ;
+  input \mprj_io_oeb[37] ;
+  input \mprj_io_oeb[3] ;
+  input \mprj_io_oeb[4] ;
+  input \mprj_io_oeb[5] ;
+  input \mprj_io_oeb[6] ;
+  input \mprj_io_oeb[7] ;
+  input \mprj_io_oeb[8] ;
+  input \mprj_io_oeb[9] ;
+  input \mprj_io_out[0] ;
+  input \mprj_io_out[10] ;
+  input \mprj_io_out[11] ;
+  input \mprj_io_out[12] ;
+  input \mprj_io_out[13] ;
+  input \mprj_io_out[14] ;
+  input \mprj_io_out[15] ;
+  input \mprj_io_out[16] ;
+  input \mprj_io_out[17] ;
+  input \mprj_io_out[18] ;
+  input \mprj_io_out[19] ;
+  input \mprj_io_out[1] ;
+  input \mprj_io_out[20] ;
+  input \mprj_io_out[21] ;
+  input \mprj_io_out[22] ;
+  input \mprj_io_out[23] ;
+  input \mprj_io_out[24] ;
+  input \mprj_io_out[25] ;
+  input \mprj_io_out[26] ;
+  input \mprj_io_out[27] ;
+  input \mprj_io_out[28] ;
+  input \mprj_io_out[29] ;
+  input \mprj_io_out[2] ;
+  input \mprj_io_out[30] ;
+  input \mprj_io_out[31] ;
+  input \mprj_io_out[32] ;
+  input \mprj_io_out[33] ;
+  input \mprj_io_out[34] ;
+  input \mprj_io_out[35] ;
+  input \mprj_io_out[36] ;
+  input \mprj_io_out[37] ;
+  input \mprj_io_out[3] ;
+  input \mprj_io_out[4] ;
+  input \mprj_io_out[5] ;
+  input \mprj_io_out[6] ;
+  input \mprj_io_out[7] ;
+  input \mprj_io_out[8] ;
+  input \mprj_io_out[9] ;
+  input \mprj_io_slow_sel[0] ;
+  input \mprj_io_slow_sel[10] ;
+  input \mprj_io_slow_sel[11] ;
+  input \mprj_io_slow_sel[12] ;
+  input \mprj_io_slow_sel[13] ;
+  input \mprj_io_slow_sel[14] ;
+  input \mprj_io_slow_sel[15] ;
+  input \mprj_io_slow_sel[16] ;
+  input \mprj_io_slow_sel[17] ;
+  input \mprj_io_slow_sel[18] ;
+  input \mprj_io_slow_sel[19] ;
+  input \mprj_io_slow_sel[1] ;
+  input \mprj_io_slow_sel[20] ;
+  input \mprj_io_slow_sel[21] ;
+  input \mprj_io_slow_sel[22] ;
+  input \mprj_io_slow_sel[23] ;
+  input \mprj_io_slow_sel[24] ;
+  input \mprj_io_slow_sel[25] ;
+  input \mprj_io_slow_sel[26] ;
+  input \mprj_io_slow_sel[27] ;
+  input \mprj_io_slow_sel[28] ;
+  input \mprj_io_slow_sel[29] ;
+  input \mprj_io_slow_sel[2] ;
+  input \mprj_io_slow_sel[30] ;
+  input \mprj_io_slow_sel[31] ;
+  input \mprj_io_slow_sel[32] ;
+  input \mprj_io_slow_sel[33] ;
+  input \mprj_io_slow_sel[34] ;
+  input \mprj_io_slow_sel[35] ;
+  input \mprj_io_slow_sel[36] ;
+  input \mprj_io_slow_sel[37] ;
+  input \mprj_io_slow_sel[3] ;
+  input \mprj_io_slow_sel[4] ;
+  input \mprj_io_slow_sel[5] ;
+  input \mprj_io_slow_sel[6] ;
+  input \mprj_io_slow_sel[7] ;
+  input \mprj_io_slow_sel[8] ;
+  input \mprj_io_slow_sel[9] ;
+  input \mprj_io_vtrip_sel[0] ;
+  input \mprj_io_vtrip_sel[10] ;
+  input \mprj_io_vtrip_sel[11] ;
+  input \mprj_io_vtrip_sel[12] ;
+  input \mprj_io_vtrip_sel[13] ;
+  input \mprj_io_vtrip_sel[14] ;
+  input \mprj_io_vtrip_sel[15] ;
+  input \mprj_io_vtrip_sel[16] ;
+  input \mprj_io_vtrip_sel[17] ;
+  input \mprj_io_vtrip_sel[18] ;
+  input \mprj_io_vtrip_sel[19] ;
+  input \mprj_io_vtrip_sel[1] ;
+  input \mprj_io_vtrip_sel[20] ;
+  input \mprj_io_vtrip_sel[21] ;
+  input \mprj_io_vtrip_sel[22] ;
+  input \mprj_io_vtrip_sel[23] ;
+  input \mprj_io_vtrip_sel[24] ;
+  input \mprj_io_vtrip_sel[25] ;
+  input \mprj_io_vtrip_sel[26] ;
+  input \mprj_io_vtrip_sel[27] ;
+  input \mprj_io_vtrip_sel[28] ;
+  input \mprj_io_vtrip_sel[29] ;
+  input \mprj_io_vtrip_sel[2] ;
+  input \mprj_io_vtrip_sel[30] ;
+  input \mprj_io_vtrip_sel[31] ;
+  input \mprj_io_vtrip_sel[32] ;
+  input \mprj_io_vtrip_sel[33] ;
+  input \mprj_io_vtrip_sel[34] ;
+  input \mprj_io_vtrip_sel[35] ;
+  input \mprj_io_vtrip_sel[36] ;
+  input \mprj_io_vtrip_sel[37] ;
+  input \mprj_io_vtrip_sel[3] ;
+  input \mprj_io_vtrip_sel[4] ;
+  input \mprj_io_vtrip_sel[5] ;
+  input \mprj_io_vtrip_sel[6] ;
+  input \mprj_io_vtrip_sel[7] ;
+  input \mprj_io_vtrip_sel[8] ;
+  input \mprj_io_vtrip_sel[9] ;
+  wire \mprj_pads.analog_a ;
+  wire \mprj_pads.analog_b ;
+  wire \mprj_pads.analog_en[0] ;
+  wire \mprj_pads.analog_en[10] ;
+  wire \mprj_pads.analog_en[11] ;
+  wire \mprj_pads.analog_en[12] ;
+  wire \mprj_pads.analog_en[13] ;
+  wire \mprj_pads.analog_en[14] ;
+  wire \mprj_pads.analog_en[15] ;
+  wire \mprj_pads.analog_en[16] ;
+  wire \mprj_pads.analog_en[17] ;
+  wire \mprj_pads.analog_en[18] ;
+  wire \mprj_pads.analog_en[19] ;
+  wire \mprj_pads.analog_en[1] ;
+  wire \mprj_pads.analog_en[20] ;
+  wire \mprj_pads.analog_en[21] ;
+  wire \mprj_pads.analog_en[22] ;
+  wire \mprj_pads.analog_en[23] ;
+  wire \mprj_pads.analog_en[24] ;
+  wire \mprj_pads.analog_en[25] ;
+  wire \mprj_pads.analog_en[26] ;
+  wire \mprj_pads.analog_en[27] ;
+  wire \mprj_pads.analog_en[28] ;
+  wire \mprj_pads.analog_en[29] ;
+  wire \mprj_pads.analog_en[2] ;
+  wire \mprj_pads.analog_en[30] ;
+  wire \mprj_pads.analog_en[31] ;
+  wire \mprj_pads.analog_en[32] ;
+  wire \mprj_pads.analog_en[33] ;
+  wire \mprj_pads.analog_en[34] ;
+  wire \mprj_pads.analog_en[35] ;
+  wire \mprj_pads.analog_en[36] ;
+  wire \mprj_pads.analog_en[37] ;
+  wire \mprj_pads.analog_en[3] ;
+  wire \mprj_pads.analog_en[4] ;
+  wire \mprj_pads.analog_en[5] ;
+  wire \mprj_pads.analog_en[6] ;
+  wire \mprj_pads.analog_en[7] ;
+  wire \mprj_pads.analog_en[8] ;
+  wire \mprj_pads.analog_en[9] ;
+  wire \mprj_pads.analog_io[0] ;
+  wire \mprj_pads.analog_io[10] ;
+  wire \mprj_pads.analog_io[11] ;
+  wire \mprj_pads.analog_io[12] ;
+  wire \mprj_pads.analog_io[13] ;
+  wire \mprj_pads.analog_io[14] ;
+  wire \mprj_pads.analog_io[15] ;
+  wire \mprj_pads.analog_io[16] ;
+  wire \mprj_pads.analog_io[17] ;
+  wire \mprj_pads.analog_io[18] ;
+  wire \mprj_pads.analog_io[19] ;
+  wire \mprj_pads.analog_io[1] ;
+  wire \mprj_pads.analog_io[20] ;
+  wire \mprj_pads.analog_io[21] ;
+  wire \mprj_pads.analog_io[22] ;
+  wire \mprj_pads.analog_io[23] ;
+  wire \mprj_pads.analog_io[24] ;
+  wire \mprj_pads.analog_io[25] ;
+  wire \mprj_pads.analog_io[26] ;
+  wire \mprj_pads.analog_io[27] ;
+  wire \mprj_pads.analog_io[28] ;
+  wire \mprj_pads.analog_io[29] ;
+  wire \mprj_pads.analog_io[2] ;
+  wire \mprj_pads.analog_io[30] ;
+  wire \mprj_pads.analog_io[3] ;
+  wire \mprj_pads.analog_io[4] ;
+  wire \mprj_pads.analog_io[5] ;
+  wire \mprj_pads.analog_io[6] ;
+  wire \mprj_pads.analog_io[7] ;
+  wire \mprj_pads.analog_io[8] ;
+  wire \mprj_pads.analog_io[9] ;
+  wire \mprj_pads.analog_pol[0] ;
+  wire \mprj_pads.analog_pol[10] ;
+  wire \mprj_pads.analog_pol[11] ;
+  wire \mprj_pads.analog_pol[12] ;
+  wire \mprj_pads.analog_pol[13] ;
+  wire \mprj_pads.analog_pol[14] ;
+  wire \mprj_pads.analog_pol[15] ;
+  wire \mprj_pads.analog_pol[16] ;
+  wire \mprj_pads.analog_pol[17] ;
+  wire \mprj_pads.analog_pol[18] ;
+  wire \mprj_pads.analog_pol[19] ;
+  wire \mprj_pads.analog_pol[1] ;
+  wire \mprj_pads.analog_pol[20] ;
+  wire \mprj_pads.analog_pol[21] ;
+  wire \mprj_pads.analog_pol[22] ;
+  wire \mprj_pads.analog_pol[23] ;
+  wire \mprj_pads.analog_pol[24] ;
+  wire \mprj_pads.analog_pol[25] ;
+  wire \mprj_pads.analog_pol[26] ;
+  wire \mprj_pads.analog_pol[27] ;
+  wire \mprj_pads.analog_pol[28] ;
+  wire \mprj_pads.analog_pol[29] ;
+  wire \mprj_pads.analog_pol[2] ;
+  wire \mprj_pads.analog_pol[30] ;
+  wire \mprj_pads.analog_pol[31] ;
+  wire \mprj_pads.analog_pol[32] ;
+  wire \mprj_pads.analog_pol[33] ;
+  wire \mprj_pads.analog_pol[34] ;
+  wire \mprj_pads.analog_pol[35] ;
+  wire \mprj_pads.analog_pol[36] ;
+  wire \mprj_pads.analog_pol[37] ;
+  wire \mprj_pads.analog_pol[3] ;
+  wire \mprj_pads.analog_pol[4] ;
+  wire \mprj_pads.analog_pol[5] ;
+  wire \mprj_pads.analog_pol[6] ;
+  wire \mprj_pads.analog_pol[7] ;
+  wire \mprj_pads.analog_pol[8] ;
+  wire \mprj_pads.analog_pol[9] ;
+  wire \mprj_pads.analog_sel[0] ;
+  wire \mprj_pads.analog_sel[10] ;
+  wire \mprj_pads.analog_sel[11] ;
+  wire \mprj_pads.analog_sel[12] ;
+  wire \mprj_pads.analog_sel[13] ;
+  wire \mprj_pads.analog_sel[14] ;
+  wire \mprj_pads.analog_sel[15] ;
+  wire \mprj_pads.analog_sel[16] ;
+  wire \mprj_pads.analog_sel[17] ;
+  wire \mprj_pads.analog_sel[18] ;
+  wire \mprj_pads.analog_sel[19] ;
+  wire \mprj_pads.analog_sel[1] ;
+  wire \mprj_pads.analog_sel[20] ;
+  wire \mprj_pads.analog_sel[21] ;
+  wire \mprj_pads.analog_sel[22] ;
+  wire \mprj_pads.analog_sel[23] ;
+  wire \mprj_pads.analog_sel[24] ;
+  wire \mprj_pads.analog_sel[25] ;
+  wire \mprj_pads.analog_sel[26] ;
+  wire \mprj_pads.analog_sel[27] ;
+  wire \mprj_pads.analog_sel[28] ;
+  wire \mprj_pads.analog_sel[29] ;
+  wire \mprj_pads.analog_sel[2] ;
+  wire \mprj_pads.analog_sel[30] ;
+  wire \mprj_pads.analog_sel[31] ;
+  wire \mprj_pads.analog_sel[32] ;
+  wire \mprj_pads.analog_sel[33] ;
+  wire \mprj_pads.analog_sel[34] ;
+  wire \mprj_pads.analog_sel[35] ;
+  wire \mprj_pads.analog_sel[36] ;
+  wire \mprj_pads.analog_sel[37] ;
+  wire \mprj_pads.analog_sel[3] ;
+  wire \mprj_pads.analog_sel[4] ;
+  wire \mprj_pads.analog_sel[5] ;
+  wire \mprj_pads.analog_sel[6] ;
+  wire \mprj_pads.analog_sel[7] ;
+  wire \mprj_pads.analog_sel[8] ;
+  wire \mprj_pads.analog_sel[9] ;
+  wire \mprj_pads.dm[0] ;
+  wire \mprj_pads.dm[100] ;
+  wire \mprj_pads.dm[101] ;
+  wire \mprj_pads.dm[102] ;
+  wire \mprj_pads.dm[103] ;
+  wire \mprj_pads.dm[104] ;
+  wire \mprj_pads.dm[105] ;
+  wire \mprj_pads.dm[106] ;
+  wire \mprj_pads.dm[107] ;
+  wire \mprj_pads.dm[108] ;
+  wire \mprj_pads.dm[109] ;
+  wire \mprj_pads.dm[10] ;
+  wire \mprj_pads.dm[110] ;
+  wire \mprj_pads.dm[111] ;
+  wire \mprj_pads.dm[112] ;
+  wire \mprj_pads.dm[113] ;
+  wire \mprj_pads.dm[11] ;
+  wire \mprj_pads.dm[12] ;
+  wire \mprj_pads.dm[13] ;
+  wire \mprj_pads.dm[14] ;
+  wire \mprj_pads.dm[15] ;
+  wire \mprj_pads.dm[16] ;
+  wire \mprj_pads.dm[17] ;
+  wire \mprj_pads.dm[18] ;
+  wire \mprj_pads.dm[19] ;
+  wire \mprj_pads.dm[1] ;
+  wire \mprj_pads.dm[20] ;
+  wire \mprj_pads.dm[21] ;
+  wire \mprj_pads.dm[22] ;
+  wire \mprj_pads.dm[23] ;
+  wire \mprj_pads.dm[24] ;
+  wire \mprj_pads.dm[25] ;
+  wire \mprj_pads.dm[26] ;
+  wire \mprj_pads.dm[27] ;
+  wire \mprj_pads.dm[28] ;
+  wire \mprj_pads.dm[29] ;
+  wire \mprj_pads.dm[2] ;
+  wire \mprj_pads.dm[30] ;
+  wire \mprj_pads.dm[31] ;
+  wire \mprj_pads.dm[32] ;
+  wire \mprj_pads.dm[33] ;
+  wire \mprj_pads.dm[34] ;
+  wire \mprj_pads.dm[35] ;
+  wire \mprj_pads.dm[36] ;
+  wire \mprj_pads.dm[37] ;
+  wire \mprj_pads.dm[38] ;
+  wire \mprj_pads.dm[39] ;
+  wire \mprj_pads.dm[3] ;
+  wire \mprj_pads.dm[40] ;
+  wire \mprj_pads.dm[41] ;
+  wire \mprj_pads.dm[42] ;
+  wire \mprj_pads.dm[43] ;
+  wire \mprj_pads.dm[44] ;
+  wire \mprj_pads.dm[45] ;
+  wire \mprj_pads.dm[46] ;
+  wire \mprj_pads.dm[47] ;
+  wire \mprj_pads.dm[48] ;
+  wire \mprj_pads.dm[49] ;
+  wire \mprj_pads.dm[4] ;
+  wire \mprj_pads.dm[50] ;
+  wire \mprj_pads.dm[51] ;
+  wire \mprj_pads.dm[52] ;
+  wire \mprj_pads.dm[53] ;
+  wire \mprj_pads.dm[54] ;
+  wire \mprj_pads.dm[55] ;
+  wire \mprj_pads.dm[56] ;
+  wire \mprj_pads.dm[57] ;
+  wire \mprj_pads.dm[58] ;
+  wire \mprj_pads.dm[59] ;
+  wire \mprj_pads.dm[5] ;
+  wire \mprj_pads.dm[60] ;
+  wire \mprj_pads.dm[61] ;
+  wire \mprj_pads.dm[62] ;
+  wire \mprj_pads.dm[63] ;
+  wire \mprj_pads.dm[64] ;
+  wire \mprj_pads.dm[65] ;
+  wire \mprj_pads.dm[66] ;
+  wire \mprj_pads.dm[67] ;
+  wire \mprj_pads.dm[68] ;
+  wire \mprj_pads.dm[69] ;
+  wire \mprj_pads.dm[6] ;
+  wire \mprj_pads.dm[70] ;
+  wire \mprj_pads.dm[71] ;
+  wire \mprj_pads.dm[72] ;
+  wire \mprj_pads.dm[73] ;
+  wire \mprj_pads.dm[74] ;
+  wire \mprj_pads.dm[75] ;
+  wire \mprj_pads.dm[76] ;
+  wire \mprj_pads.dm[77] ;
+  wire \mprj_pads.dm[78] ;
+  wire \mprj_pads.dm[79] ;
+  wire \mprj_pads.dm[7] ;
+  wire \mprj_pads.dm[80] ;
+  wire \mprj_pads.dm[81] ;
+  wire \mprj_pads.dm[82] ;
+  wire \mprj_pads.dm[83] ;
+  wire \mprj_pads.dm[84] ;
+  wire \mprj_pads.dm[85] ;
+  wire \mprj_pads.dm[86] ;
+  wire \mprj_pads.dm[87] ;
+  wire \mprj_pads.dm[88] ;
+  wire \mprj_pads.dm[89] ;
+  wire \mprj_pads.dm[8] ;
+  wire \mprj_pads.dm[90] ;
+  wire \mprj_pads.dm[91] ;
+  wire \mprj_pads.dm[92] ;
+  wire \mprj_pads.dm[93] ;
+  wire \mprj_pads.dm[94] ;
+  wire \mprj_pads.dm[95] ;
+  wire \mprj_pads.dm[96] ;
+  wire \mprj_pads.dm[97] ;
+  wire \mprj_pads.dm[98] ;
+  wire \mprj_pads.dm[99] ;
+  wire \mprj_pads.dm[9] ;
+  wire \mprj_pads.enh[0] ;
+  wire \mprj_pads.enh[10] ;
+  wire \mprj_pads.enh[11] ;
+  wire \mprj_pads.enh[12] ;
+  wire \mprj_pads.enh[13] ;
+  wire \mprj_pads.enh[14] ;
+  wire \mprj_pads.enh[15] ;
+  wire \mprj_pads.enh[16] ;
+  wire \mprj_pads.enh[17] ;
+  wire \mprj_pads.enh[18] ;
+  wire \mprj_pads.enh[19] ;
+  wire \mprj_pads.enh[1] ;
+  wire \mprj_pads.enh[20] ;
+  wire \mprj_pads.enh[21] ;
+  wire \mprj_pads.enh[22] ;
+  wire \mprj_pads.enh[23] ;
+  wire \mprj_pads.enh[24] ;
+  wire \mprj_pads.enh[25] ;
+  wire \mprj_pads.enh[26] ;
+  wire \mprj_pads.enh[27] ;
+  wire \mprj_pads.enh[28] ;
+  wire \mprj_pads.enh[29] ;
+  wire \mprj_pads.enh[2] ;
+  wire \mprj_pads.enh[30] ;
+  wire \mprj_pads.enh[31] ;
+  wire \mprj_pads.enh[32] ;
+  wire \mprj_pads.enh[33] ;
+  wire \mprj_pads.enh[34] ;
+  wire \mprj_pads.enh[35] ;
+  wire \mprj_pads.enh[36] ;
+  wire \mprj_pads.enh[37] ;
+  wire \mprj_pads.enh[3] ;
+  wire \mprj_pads.enh[4] ;
+  wire \mprj_pads.enh[5] ;
+  wire \mprj_pads.enh[6] ;
+  wire \mprj_pads.enh[7] ;
+  wire \mprj_pads.enh[8] ;
+  wire \mprj_pads.enh[9] ;
+  wire \mprj_pads.hldh_n[0] ;
+  wire \mprj_pads.hldh_n[10] ;
+  wire \mprj_pads.hldh_n[11] ;
+  wire \mprj_pads.hldh_n[12] ;
+  wire \mprj_pads.hldh_n[13] ;
+  wire \mprj_pads.hldh_n[14] ;
+  wire \mprj_pads.hldh_n[15] ;
+  wire \mprj_pads.hldh_n[16] ;
+  wire \mprj_pads.hldh_n[17] ;
+  wire \mprj_pads.hldh_n[18] ;
+  wire \mprj_pads.hldh_n[19] ;
+  wire \mprj_pads.hldh_n[1] ;
+  wire \mprj_pads.hldh_n[20] ;
+  wire \mprj_pads.hldh_n[21] ;
+  wire \mprj_pads.hldh_n[22] ;
+  wire \mprj_pads.hldh_n[23] ;
+  wire \mprj_pads.hldh_n[24] ;
+  wire \mprj_pads.hldh_n[25] ;
+  wire \mprj_pads.hldh_n[26] ;
+  wire \mprj_pads.hldh_n[27] ;
+  wire \mprj_pads.hldh_n[28] ;
+  wire \mprj_pads.hldh_n[29] ;
+  wire \mprj_pads.hldh_n[2] ;
+  wire \mprj_pads.hldh_n[30] ;
+  wire \mprj_pads.hldh_n[31] ;
+  wire \mprj_pads.hldh_n[32] ;
+  wire \mprj_pads.hldh_n[33] ;
+  wire \mprj_pads.hldh_n[34] ;
+  wire \mprj_pads.hldh_n[35] ;
+  wire \mprj_pads.hldh_n[36] ;
+  wire \mprj_pads.hldh_n[37] ;
+  wire \mprj_pads.hldh_n[3] ;
+  wire \mprj_pads.hldh_n[4] ;
+  wire \mprj_pads.hldh_n[5] ;
+  wire \mprj_pads.hldh_n[6] ;
+  wire \mprj_pads.hldh_n[7] ;
+  wire \mprj_pads.hldh_n[8] ;
+  wire \mprj_pads.hldh_n[9] ;
+  wire \mprj_pads.holdover[0] ;
+  wire \mprj_pads.holdover[10] ;
+  wire \mprj_pads.holdover[11] ;
+  wire \mprj_pads.holdover[12] ;
+  wire \mprj_pads.holdover[13] ;
+  wire \mprj_pads.holdover[14] ;
+  wire \mprj_pads.holdover[15] ;
+  wire \mprj_pads.holdover[16] ;
+  wire \mprj_pads.holdover[17] ;
+  wire \mprj_pads.holdover[18] ;
+  wire \mprj_pads.holdover[19] ;
+  wire \mprj_pads.holdover[1] ;
+  wire \mprj_pads.holdover[20] ;
+  wire \mprj_pads.holdover[21] ;
+  wire \mprj_pads.holdover[22] ;
+  wire \mprj_pads.holdover[23] ;
+  wire \mprj_pads.holdover[24] ;
+  wire \mprj_pads.holdover[25] ;
+  wire \mprj_pads.holdover[26] ;
+  wire \mprj_pads.holdover[27] ;
+  wire \mprj_pads.holdover[28] ;
+  wire \mprj_pads.holdover[29] ;
+  wire \mprj_pads.holdover[2] ;
+  wire \mprj_pads.holdover[30] ;
+  wire \mprj_pads.holdover[31] ;
+  wire \mprj_pads.holdover[32] ;
+  wire \mprj_pads.holdover[33] ;
+  wire \mprj_pads.holdover[34] ;
+  wire \mprj_pads.holdover[35] ;
+  wire \mprj_pads.holdover[36] ;
+  wire \mprj_pads.holdover[37] ;
+  wire \mprj_pads.holdover[3] ;
+  wire \mprj_pads.holdover[4] ;
+  wire \mprj_pads.holdover[5] ;
+  wire \mprj_pads.holdover[6] ;
+  wire \mprj_pads.holdover[7] ;
+  wire \mprj_pads.holdover[8] ;
+  wire \mprj_pads.holdover[9] ;
+  wire \mprj_pads.ib_mode_sel[0] ;
+  wire \mprj_pads.ib_mode_sel[10] ;
+  wire \mprj_pads.ib_mode_sel[11] ;
+  wire \mprj_pads.ib_mode_sel[12] ;
+  wire \mprj_pads.ib_mode_sel[13] ;
+  wire \mprj_pads.ib_mode_sel[14] ;
+  wire \mprj_pads.ib_mode_sel[15] ;
+  wire \mprj_pads.ib_mode_sel[16] ;
+  wire \mprj_pads.ib_mode_sel[17] ;
+  wire \mprj_pads.ib_mode_sel[18] ;
+  wire \mprj_pads.ib_mode_sel[19] ;
+  wire \mprj_pads.ib_mode_sel[1] ;
+  wire \mprj_pads.ib_mode_sel[20] ;
+  wire \mprj_pads.ib_mode_sel[21] ;
+  wire \mprj_pads.ib_mode_sel[22] ;
+  wire \mprj_pads.ib_mode_sel[23] ;
+  wire \mprj_pads.ib_mode_sel[24] ;
+  wire \mprj_pads.ib_mode_sel[25] ;
+  wire \mprj_pads.ib_mode_sel[26] ;
+  wire \mprj_pads.ib_mode_sel[27] ;
+  wire \mprj_pads.ib_mode_sel[28] ;
+  wire \mprj_pads.ib_mode_sel[29] ;
+  wire \mprj_pads.ib_mode_sel[2] ;
+  wire \mprj_pads.ib_mode_sel[30] ;
+  wire \mprj_pads.ib_mode_sel[31] ;
+  wire \mprj_pads.ib_mode_sel[32] ;
+  wire \mprj_pads.ib_mode_sel[33] ;
+  wire \mprj_pads.ib_mode_sel[34] ;
+  wire \mprj_pads.ib_mode_sel[35] ;
+  wire \mprj_pads.ib_mode_sel[36] ;
+  wire \mprj_pads.ib_mode_sel[37] ;
+  wire \mprj_pads.ib_mode_sel[3] ;
+  wire \mprj_pads.ib_mode_sel[4] ;
+  wire \mprj_pads.ib_mode_sel[5] ;
+  wire \mprj_pads.ib_mode_sel[6] ;
+  wire \mprj_pads.ib_mode_sel[7] ;
+  wire \mprj_pads.ib_mode_sel[8] ;
+  wire \mprj_pads.ib_mode_sel[9] ;
+  wire \mprj_pads.inp_dis[0] ;
+  wire \mprj_pads.inp_dis[10] ;
+  wire \mprj_pads.inp_dis[11] ;
+  wire \mprj_pads.inp_dis[12] ;
+  wire \mprj_pads.inp_dis[13] ;
+  wire \mprj_pads.inp_dis[14] ;
+  wire \mprj_pads.inp_dis[15] ;
+  wire \mprj_pads.inp_dis[16] ;
+  wire \mprj_pads.inp_dis[17] ;
+  wire \mprj_pads.inp_dis[18] ;
+  wire \mprj_pads.inp_dis[19] ;
+  wire \mprj_pads.inp_dis[1] ;
+  wire \mprj_pads.inp_dis[20] ;
+  wire \mprj_pads.inp_dis[21] ;
+  wire \mprj_pads.inp_dis[22] ;
+  wire \mprj_pads.inp_dis[23] ;
+  wire \mprj_pads.inp_dis[24] ;
+  wire \mprj_pads.inp_dis[25] ;
+  wire \mprj_pads.inp_dis[26] ;
+  wire \mprj_pads.inp_dis[27] ;
+  wire \mprj_pads.inp_dis[28] ;
+  wire \mprj_pads.inp_dis[29] ;
+  wire \mprj_pads.inp_dis[2] ;
+  wire \mprj_pads.inp_dis[30] ;
+  wire \mprj_pads.inp_dis[31] ;
+  wire \mprj_pads.inp_dis[32] ;
+  wire \mprj_pads.inp_dis[33] ;
+  wire \mprj_pads.inp_dis[34] ;
+  wire \mprj_pads.inp_dis[35] ;
+  wire \mprj_pads.inp_dis[36] ;
+  wire \mprj_pads.inp_dis[37] ;
+  wire \mprj_pads.inp_dis[3] ;
+  wire \mprj_pads.inp_dis[4] ;
+  wire \mprj_pads.inp_dis[5] ;
+  wire \mprj_pads.inp_dis[6] ;
+  wire \mprj_pads.inp_dis[7] ;
+  wire \mprj_pads.inp_dis[8] ;
+  wire \mprj_pads.inp_dis[9] ;
+  wire \mprj_pads.io[0] ;
+  wire \mprj_pads.io[10] ;
+  wire \mprj_pads.io[11] ;
+  wire \mprj_pads.io[12] ;
+  wire \mprj_pads.io[13] ;
+  wire \mprj_pads.io[14] ;
+  wire \mprj_pads.io[15] ;
+  wire \mprj_pads.io[16] ;
+  wire \mprj_pads.io[17] ;
+  wire \mprj_pads.io[18] ;
+  wire \mprj_pads.io[19] ;
+  wire \mprj_pads.io[1] ;
+  wire \mprj_pads.io[20] ;
+  wire \mprj_pads.io[21] ;
+  wire \mprj_pads.io[22] ;
+  wire \mprj_pads.io[23] ;
+  wire \mprj_pads.io[24] ;
+  wire \mprj_pads.io[25] ;
+  wire \mprj_pads.io[26] ;
+  wire \mprj_pads.io[27] ;
+  wire \mprj_pads.io[28] ;
+  wire \mprj_pads.io[29] ;
+  wire \mprj_pads.io[2] ;
+  wire \mprj_pads.io[30] ;
+  wire \mprj_pads.io[31] ;
+  wire \mprj_pads.io[32] ;
+  wire \mprj_pads.io[33] ;
+  wire \mprj_pads.io[34] ;
+  wire \mprj_pads.io[35] ;
+  wire \mprj_pads.io[36] ;
+  wire \mprj_pads.io[37] ;
+  wire \mprj_pads.io[3] ;
+  wire \mprj_pads.io[4] ;
+  wire \mprj_pads.io[5] ;
+  wire \mprj_pads.io[6] ;
+  wire \mprj_pads.io[7] ;
+  wire \mprj_pads.io[8] ;
+  wire \mprj_pads.io[9] ;
+  wire \mprj_pads.io_in[0] ;
+  wire \mprj_pads.io_in[10] ;
+  wire \mprj_pads.io_in[11] ;
+  wire \mprj_pads.io_in[12] ;
+  wire \mprj_pads.io_in[13] ;
+  wire \mprj_pads.io_in[14] ;
+  wire \mprj_pads.io_in[15] ;
+  wire \mprj_pads.io_in[16] ;
+  wire \mprj_pads.io_in[17] ;
+  wire \mprj_pads.io_in[18] ;
+  wire \mprj_pads.io_in[19] ;
+  wire \mprj_pads.io_in[1] ;
+  wire \mprj_pads.io_in[20] ;
+  wire \mprj_pads.io_in[21] ;
+  wire \mprj_pads.io_in[22] ;
+  wire \mprj_pads.io_in[23] ;
+  wire \mprj_pads.io_in[24] ;
+  wire \mprj_pads.io_in[25] ;
+  wire \mprj_pads.io_in[26] ;
+  wire \mprj_pads.io_in[27] ;
+  wire \mprj_pads.io_in[28] ;
+  wire \mprj_pads.io_in[29] ;
+  wire \mprj_pads.io_in[2] ;
+  wire \mprj_pads.io_in[30] ;
+  wire \mprj_pads.io_in[31] ;
+  wire \mprj_pads.io_in[32] ;
+  wire \mprj_pads.io_in[33] ;
+  wire \mprj_pads.io_in[34] ;
+  wire \mprj_pads.io_in[35] ;
+  wire \mprj_pads.io_in[36] ;
+  wire \mprj_pads.io_in[37] ;
+  wire \mprj_pads.io_in[3] ;
+  wire \mprj_pads.io_in[4] ;
+  wire \mprj_pads.io_in[5] ;
+  wire \mprj_pads.io_in[6] ;
+  wire \mprj_pads.io_in[7] ;
+  wire \mprj_pads.io_in[8] ;
+  wire \mprj_pads.io_in[9] ;
+  wire \mprj_pads.io_out[0] ;
+  wire \mprj_pads.io_out[10] ;
+  wire \mprj_pads.io_out[11] ;
+  wire \mprj_pads.io_out[12] ;
+  wire \mprj_pads.io_out[13] ;
+  wire \mprj_pads.io_out[14] ;
+  wire \mprj_pads.io_out[15] ;
+  wire \mprj_pads.io_out[16] ;
+  wire \mprj_pads.io_out[17] ;
+  wire \mprj_pads.io_out[18] ;
+  wire \mprj_pads.io_out[19] ;
+  wire \mprj_pads.io_out[1] ;
+  wire \mprj_pads.io_out[20] ;
+  wire \mprj_pads.io_out[21] ;
+  wire \mprj_pads.io_out[22] ;
+  wire \mprj_pads.io_out[23] ;
+  wire \mprj_pads.io_out[24] ;
+  wire \mprj_pads.io_out[25] ;
+  wire \mprj_pads.io_out[26] ;
+  wire \mprj_pads.io_out[27] ;
+  wire \mprj_pads.io_out[28] ;
+  wire \mprj_pads.io_out[29] ;
+  wire \mprj_pads.io_out[2] ;
+  wire \mprj_pads.io_out[30] ;
+  wire \mprj_pads.io_out[31] ;
+  wire \mprj_pads.io_out[32] ;
+  wire \mprj_pads.io_out[33] ;
+  wire \mprj_pads.io_out[34] ;
+  wire \mprj_pads.io_out[35] ;
+  wire \mprj_pads.io_out[36] ;
+  wire \mprj_pads.io_out[37] ;
+  wire \mprj_pads.io_out[3] ;
+  wire \mprj_pads.io_out[4] ;
+  wire \mprj_pads.io_out[5] ;
+  wire \mprj_pads.io_out[6] ;
+  wire \mprj_pads.io_out[7] ;
+  wire \mprj_pads.io_out[8] ;
+  wire \mprj_pads.io_out[9] ;
+  wire \mprj_pads.loop1_io[0] ;
+  wire \mprj_pads.loop1_io[10] ;
+  wire \mprj_pads.loop1_io[11] ;
+  wire \mprj_pads.loop1_io[12] ;
+  wire \mprj_pads.loop1_io[13] ;
+  wire \mprj_pads.loop1_io[14] ;
+  wire \mprj_pads.loop1_io[15] ;
+  wire \mprj_pads.loop1_io[16] ;
+  wire \mprj_pads.loop1_io[17] ;
+  wire \mprj_pads.loop1_io[18] ;
+  wire \mprj_pads.loop1_io[19] ;
+  wire \mprj_pads.loop1_io[1] ;
+  wire \mprj_pads.loop1_io[20] ;
+  wire \mprj_pads.loop1_io[21] ;
+  wire \mprj_pads.loop1_io[22] ;
+  wire \mprj_pads.loop1_io[23] ;
+  wire \mprj_pads.loop1_io[24] ;
+  wire \mprj_pads.loop1_io[25] ;
+  wire \mprj_pads.loop1_io[26] ;
+  wire \mprj_pads.loop1_io[27] ;
+  wire \mprj_pads.loop1_io[28] ;
+  wire \mprj_pads.loop1_io[29] ;
+  wire \mprj_pads.loop1_io[2] ;
+  wire \mprj_pads.loop1_io[30] ;
+  wire \mprj_pads.loop1_io[31] ;
+  wire \mprj_pads.loop1_io[32] ;
+  wire \mprj_pads.loop1_io[33] ;
+  wire \mprj_pads.loop1_io[34] ;
+  wire \mprj_pads.loop1_io[35] ;
+  wire \mprj_pads.loop1_io[36] ;
+  wire \mprj_pads.loop1_io[37] ;
+  wire \mprj_pads.loop1_io[3] ;
+  wire \mprj_pads.loop1_io[4] ;
+  wire \mprj_pads.loop1_io[5] ;
+  wire \mprj_pads.loop1_io[6] ;
+  wire \mprj_pads.loop1_io[7] ;
+  wire \mprj_pads.loop1_io[8] ;
+  wire \mprj_pads.loop1_io[9] ;
+  wire \mprj_pads.no_connect[0] ;
+  wire \mprj_pads.no_connect[1] ;
+  wire \mprj_pads.no_connect[2] ;
+  wire \mprj_pads.no_connect[3] ;
+  wire \mprj_pads.no_connect[4] ;
+  wire \mprj_pads.no_connect[5] ;
+  wire \mprj_pads.no_connect[6] ;
+  wire \mprj_pads.oeb[0] ;
+  wire \mprj_pads.oeb[10] ;
+  wire \mprj_pads.oeb[11] ;
+  wire \mprj_pads.oeb[12] ;
+  wire \mprj_pads.oeb[13] ;
+  wire \mprj_pads.oeb[14] ;
+  wire \mprj_pads.oeb[15] ;
+  wire \mprj_pads.oeb[16] ;
+  wire \mprj_pads.oeb[17] ;
+  wire \mprj_pads.oeb[18] ;
+  wire \mprj_pads.oeb[19] ;
+  wire \mprj_pads.oeb[1] ;
+  wire \mprj_pads.oeb[20] ;
+  wire \mprj_pads.oeb[21] ;
+  wire \mprj_pads.oeb[22] ;
+  wire \mprj_pads.oeb[23] ;
+  wire \mprj_pads.oeb[24] ;
+  wire \mprj_pads.oeb[25] ;
+  wire \mprj_pads.oeb[26] ;
+  wire \mprj_pads.oeb[27] ;
+  wire \mprj_pads.oeb[28] ;
+  wire \mprj_pads.oeb[29] ;
+  wire \mprj_pads.oeb[2] ;
+  wire \mprj_pads.oeb[30] ;
+  wire \mprj_pads.oeb[31] ;
+  wire \mprj_pads.oeb[32] ;
+  wire \mprj_pads.oeb[33] ;
+  wire \mprj_pads.oeb[34] ;
+  wire \mprj_pads.oeb[35] ;
+  wire \mprj_pads.oeb[36] ;
+  wire \mprj_pads.oeb[37] ;
+  wire \mprj_pads.oeb[3] ;
+  wire \mprj_pads.oeb[4] ;
+  wire \mprj_pads.oeb[5] ;
+  wire \mprj_pads.oeb[6] ;
+  wire \mprj_pads.oeb[7] ;
+  wire \mprj_pads.oeb[8] ;
+  wire \mprj_pads.oeb[9] ;
+  wire \mprj_pads.porb_h ;
+  wire \mprj_pads.slow_sel[0] ;
+  wire \mprj_pads.slow_sel[10] ;
+  wire \mprj_pads.slow_sel[11] ;
+  wire \mprj_pads.slow_sel[12] ;
+  wire \mprj_pads.slow_sel[13] ;
+  wire \mprj_pads.slow_sel[14] ;
+  wire \mprj_pads.slow_sel[15] ;
+  wire \mprj_pads.slow_sel[16] ;
+  wire \mprj_pads.slow_sel[17] ;
+  wire \mprj_pads.slow_sel[18] ;
+  wire \mprj_pads.slow_sel[19] ;
+  wire \mprj_pads.slow_sel[1] ;
+  wire \mprj_pads.slow_sel[20] ;
+  wire \mprj_pads.slow_sel[21] ;
+  wire \mprj_pads.slow_sel[22] ;
+  wire \mprj_pads.slow_sel[23] ;
+  wire \mprj_pads.slow_sel[24] ;
+  wire \mprj_pads.slow_sel[25] ;
+  wire \mprj_pads.slow_sel[26] ;
+  wire \mprj_pads.slow_sel[27] ;
+  wire \mprj_pads.slow_sel[28] ;
+  wire \mprj_pads.slow_sel[29] ;
+  wire \mprj_pads.slow_sel[2] ;
+  wire \mprj_pads.slow_sel[30] ;
+  wire \mprj_pads.slow_sel[31] ;
+  wire \mprj_pads.slow_sel[32] ;
+  wire \mprj_pads.slow_sel[33] ;
+  wire \mprj_pads.slow_sel[34] ;
+  wire \mprj_pads.slow_sel[35] ;
+  wire \mprj_pads.slow_sel[36] ;
+  wire \mprj_pads.slow_sel[37] ;
+  wire \mprj_pads.slow_sel[3] ;
+  wire \mprj_pads.slow_sel[4] ;
+  wire \mprj_pads.slow_sel[5] ;
+  wire \mprj_pads.slow_sel[6] ;
+  wire \mprj_pads.slow_sel[7] ;
+  wire \mprj_pads.slow_sel[8] ;
+  wire \mprj_pads.slow_sel[9] ;
+  wire \mprj_pads.vccd ;
+  wire \mprj_pads.vccd1 ;
+  wire \mprj_pads.vccd2 ;
+  wire \mprj_pads.vdda ;
+  wire \mprj_pads.vdda1 ;
+  wire \mprj_pads.vdda2 ;
+  wire \mprj_pads.vddio ;
+  wire \mprj_pads.vddio_q ;
+  wire \mprj_pads.vssa ;
+  wire \mprj_pads.vssa1 ;
+  wire \mprj_pads.vssa2 ;
+  wire \mprj_pads.vssd ;
+  wire \mprj_pads.vssd1 ;
+  wire \mprj_pads.vssd2 ;
+  wire \mprj_pads.vssio ;
+  wire \mprj_pads.vssio_q ;
+  wire \mprj_pads.vtrip_sel[0] ;
+  wire \mprj_pads.vtrip_sel[10] ;
+  wire \mprj_pads.vtrip_sel[11] ;
+  wire \mprj_pads.vtrip_sel[12] ;
+  wire \mprj_pads.vtrip_sel[13] ;
+  wire \mprj_pads.vtrip_sel[14] ;
+  wire \mprj_pads.vtrip_sel[15] ;
+  wire \mprj_pads.vtrip_sel[16] ;
+  wire \mprj_pads.vtrip_sel[17] ;
+  wire \mprj_pads.vtrip_sel[18] ;
+  wire \mprj_pads.vtrip_sel[19] ;
+  wire \mprj_pads.vtrip_sel[1] ;
+  wire \mprj_pads.vtrip_sel[20] ;
+  wire \mprj_pads.vtrip_sel[21] ;
+  wire \mprj_pads.vtrip_sel[22] ;
+  wire \mprj_pads.vtrip_sel[23] ;
+  wire \mprj_pads.vtrip_sel[24] ;
+  wire \mprj_pads.vtrip_sel[25] ;
+  wire \mprj_pads.vtrip_sel[26] ;
+  wire \mprj_pads.vtrip_sel[27] ;
+  wire \mprj_pads.vtrip_sel[28] ;
+  wire \mprj_pads.vtrip_sel[29] ;
+  wire \mprj_pads.vtrip_sel[2] ;
+  wire \mprj_pads.vtrip_sel[30] ;
+  wire \mprj_pads.vtrip_sel[31] ;
+  wire \mprj_pads.vtrip_sel[32] ;
+  wire \mprj_pads.vtrip_sel[33] ;
+  wire \mprj_pads.vtrip_sel[34] ;
+  wire \mprj_pads.vtrip_sel[35] ;
+  wire \mprj_pads.vtrip_sel[36] ;
+  wire \mprj_pads.vtrip_sel[37] ;
+  wire \mprj_pads.vtrip_sel[3] ;
+  wire \mprj_pads.vtrip_sel[4] ;
+  wire \mprj_pads.vtrip_sel[5] ;
+  wire \mprj_pads.vtrip_sel[6] ;
+  wire \mprj_pads.vtrip_sel[7] ;
+  wire \mprj_pads.vtrip_sel[8] ;
+  wire \mprj_pads.vtrip_sel[9] ;
+  input por;
+  input porb_h;
+  input resetb;
+  output resetb_core_h;
+  inout vccd;
+  inout vccd1;
+  inout vccd2;
+  inout vdda;
+  inout vdda1;
+  inout vdda2;
+  inout vddio;
+  wire vddio_q;
+  inout vssa;
+  inout vssa1;
+  inout vssa2;
+  inout vssd;
+  inout vssd1;
+  inout vssd2;
+  inout vssio;
+  wire vssio_q;
+  wire xresloop;
+  sky130_ef_io__gpiov2_pad_wrapped clock_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ vssd, vssd, vccd }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_clock),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(clock_core),
+    .INP_DIS(por),
+    .IN_H(),
+    .OE_N(vccd),
+    .OUT(vssd),
+    .PAD(clock),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_clock),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped flash_clk_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ vccd, vccd, vssd }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_flash_clk),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(),
+    .INP_DIS(flash_clk_ieb_core),
+    .IN_H(),
+    .OE_N(flash_clk_oeb_core),
+    .OUT(flash_clk_core),
+    .PAD(flash_clk),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_flash_clk),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped flash_csb_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ vccd, vccd, vssd }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_flash_csb),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(),
+    .INP_DIS(flash_csb_ieb_core),
+    .IN_H(),
+    .OE_N(flash_csb_oeb_core),
+    .OUT(flash_csb_core),
+    .PAD(flash_csb),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_flash_csb),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped flash_io0_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_flash_io0),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(flash_io0_di_core),
+    .INP_DIS(flash_io0_ieb_core),
+    .IN_H(),
+    .OE_N(flash_io0_oeb_core),
+    .OUT(flash_io0_do_core),
+    .PAD(flash_io0),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_flash_io0),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped flash_io1_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_flash_io1),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(flash_io1_di_core),
+    .INP_DIS(flash_io1_ieb_core),
+    .IN_H(),
+    .OE_N(flash_io1_oeb_core),
+    .OUT(flash_io1_do_core),
+    .PAD(flash_io1),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_flash_io1),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped gpio_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(vssd),
+    .ANALOG_POL(vssd),
+    .ANALOG_SEL(vssd),
+    .DM({ gpio_mode1_core, gpio_mode1_core, gpio_mode0_core }),
+    .ENABLE_H(porb_h),
+    .ENABLE_INP_H(loop_gpio),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssa),
+    .HLD_H_N(vddio),
+    .HLD_OVR(vssd),
+    .IB_MODE_SEL(vssd),
+    .IN(gpio_in_core),
+    .INP_DIS(gpio_inenb_core),
+    .IN_H(),
+    .OE_N(gpio_outenb_core),
+    .OUT(gpio_out_core),
+    .PAD(gpio),
+    .PAD_A_ESD_0_H(),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(vssd),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(loop_gpio),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(vssd)
+  );
+  sky130_ef_io__corner_pad \mgmt_corner[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__corner_pad \mgmt_corner[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclmap_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[0] ),
+    .ANALOG_POL(\mprj_io_analog_pol[0] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[0] ),
+    .DM({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0]  }),
+    .ENABLE_H(\mprj_io_enh[0] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[0] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[0] ),
+    .HLD_OVR(\mprj_io_holdover[0] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[0] ),
+    .IN(\mprj_pads.io_in[0] ),
+    .INP_DIS(\mprj_io_inp_dis[0] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[0] ),
+    .OUT(\mprj_io_out[0] ),
+    .PAD(\mprj_io[0] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[0] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[0] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[0] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[0] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[10]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[10] ),
+    .ANALOG_POL(\mprj_io_analog_pol[10] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[10] ),
+    .DM({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30]  }),
+    .ENABLE_H(\mprj_io_enh[10] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[10] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[10] ),
+    .HLD_OVR(\mprj_io_holdover[10] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[10] ),
+    .IN(\mprj_pads.io_in[10] ),
+    .INP_DIS(\mprj_io_inp_dis[10] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[10] ),
+    .OUT(\mprj_io_out[10] ),
+    .PAD(\mprj_io[10] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[3] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[10] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[10] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[10] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[11]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[11] ),
+    .ANALOG_POL(\mprj_io_analog_pol[11] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[11] ),
+    .DM({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33]  }),
+    .ENABLE_H(\mprj_io_enh[11] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[11] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[11] ),
+    .HLD_OVR(\mprj_io_holdover[11] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[11] ),
+    .IN(\mprj_pads.io_in[11] ),
+    .INP_DIS(\mprj_io_inp_dis[11] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[11] ),
+    .OUT(\mprj_io_out[11] ),
+    .PAD(\mprj_io[11] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[4] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[11] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[11] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[11] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[12]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[12] ),
+    .ANALOG_POL(\mprj_io_analog_pol[12] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[12] ),
+    .DM({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36]  }),
+    .ENABLE_H(\mprj_io_enh[12] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[12] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[12] ),
+    .HLD_OVR(\mprj_io_holdover[12] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[12] ),
+    .IN(\mprj_pads.io_in[12] ),
+    .INP_DIS(\mprj_io_inp_dis[12] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[12] ),
+    .OUT(\mprj_io_out[12] ),
+    .PAD(\mprj_io[12] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[5] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[12] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[12] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[12] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[13]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[13] ),
+    .ANALOG_POL(\mprj_io_analog_pol[13] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[13] ),
+    .DM({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39]  }),
+    .ENABLE_H(\mprj_io_enh[13] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[13] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[13] ),
+    .HLD_OVR(\mprj_io_holdover[13] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[13] ),
+    .IN(\mprj_pads.io_in[13] ),
+    .INP_DIS(\mprj_io_inp_dis[13] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[13] ),
+    .OUT(\mprj_io_out[13] ),
+    .PAD(\mprj_io[13] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[6] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[13] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[13] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[13] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[14]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[14] ),
+    .ANALOG_POL(\mprj_io_analog_pol[14] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[14] ),
+    .DM({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42]  }),
+    .ENABLE_H(\mprj_io_enh[14] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[14] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[14] ),
+    .HLD_OVR(\mprj_io_holdover[14] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[14] ),
+    .IN(\mprj_pads.io_in[14] ),
+    .INP_DIS(\mprj_io_inp_dis[14] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[14] ),
+    .OUT(\mprj_io_out[14] ),
+    .PAD(\mprj_io[14] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[7] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[14] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[14] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[14] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[15]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[15] ),
+    .ANALOG_POL(\mprj_io_analog_pol[15] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[15] ),
+    .DM({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45]  }),
+    .ENABLE_H(\mprj_io_enh[15] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[15] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[15] ),
+    .HLD_OVR(\mprj_io_holdover[15] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[15] ),
+    .IN(\mprj_pads.io_in[15] ),
+    .INP_DIS(\mprj_io_inp_dis[15] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[15] ),
+    .OUT(\mprj_io_out[15] ),
+    .PAD(\mprj_io[15] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[8] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[15] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[15] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[15] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[16]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[16] ),
+    .ANALOG_POL(\mprj_io_analog_pol[16] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[16] ),
+    .DM({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48]  }),
+    .ENABLE_H(\mprj_io_enh[16] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[16] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[16] ),
+    .HLD_OVR(\mprj_io_holdover[16] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[16] ),
+    .IN(\mprj_pads.io_in[16] ),
+    .INP_DIS(\mprj_io_inp_dis[16] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[16] ),
+    .OUT(\mprj_io_out[16] ),
+    .PAD(\mprj_io[16] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[9] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[16] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[16] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[16] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[17]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[17] ),
+    .ANALOG_POL(\mprj_io_analog_pol[17] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[17] ),
+    .DM({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51]  }),
+    .ENABLE_H(\mprj_io_enh[17] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[17] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[17] ),
+    .HLD_OVR(\mprj_io_holdover[17] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[17] ),
+    .IN(\mprj_pads.io_in[17] ),
+    .INP_DIS(\mprj_io_inp_dis[17] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[17] ),
+    .OUT(\mprj_io_out[17] ),
+    .PAD(\mprj_io[17] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[10] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[17] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[17] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[17] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[1] ),
+    .ANALOG_POL(\mprj_io_analog_pol[1] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[1] ),
+    .DM({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3]  }),
+    .ENABLE_H(\mprj_io_enh[1] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[1] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[1] ),
+    .HLD_OVR(\mprj_io_holdover[1] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[1] ),
+    .IN(\mprj_pads.io_in[1] ),
+    .INP_DIS(\mprj_io_inp_dis[1] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[1] ),
+    .OUT(\mprj_io_out[1] ),
+    .PAD(\mprj_io[1] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[1] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[1] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[1] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[1] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[2]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[2] ),
+    .ANALOG_POL(\mprj_io_analog_pol[2] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[2] ),
+    .DM({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6]  }),
+    .ENABLE_H(\mprj_io_enh[2] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[2] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[2] ),
+    .HLD_OVR(\mprj_io_holdover[2] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[2] ),
+    .IN(\mprj_pads.io_in[2] ),
+    .INP_DIS(\mprj_io_inp_dis[2] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[2] ),
+    .OUT(\mprj_io_out[2] ),
+    .PAD(\mprj_io[2] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[2] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[2] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[2] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[2] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[3]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[3] ),
+    .ANALOG_POL(\mprj_io_analog_pol[3] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[3] ),
+    .DM({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9]  }),
+    .ENABLE_H(\mprj_io_enh[3] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[3] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[3] ),
+    .HLD_OVR(\mprj_io_holdover[3] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[3] ),
+    .IN(\mprj_pads.io_in[3] ),
+    .INP_DIS(\mprj_io_inp_dis[3] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[3] ),
+    .OUT(\mprj_io_out[3] ),
+    .PAD(\mprj_io[3] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[3] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[3] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[3] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[3] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[4]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[4] ),
+    .ANALOG_POL(\mprj_io_analog_pol[4] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[4] ),
+    .DM({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12]  }),
+    .ENABLE_H(\mprj_io_enh[4] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[4] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[4] ),
+    .HLD_OVR(\mprj_io_holdover[4] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[4] ),
+    .IN(\mprj_pads.io_in[4] ),
+    .INP_DIS(\mprj_io_inp_dis[4] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[4] ),
+    .OUT(\mprj_io_out[4] ),
+    .PAD(\mprj_io[4] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[4] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[4] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[4] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[4] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[5]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[5] ),
+    .ANALOG_POL(\mprj_io_analog_pol[5] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[5] ),
+    .DM({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15]  }),
+    .ENABLE_H(\mprj_io_enh[5] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[5] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[5] ),
+    .HLD_OVR(\mprj_io_holdover[5] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[5] ),
+    .IN(\mprj_pads.io_in[5] ),
+    .INP_DIS(\mprj_io_inp_dis[5] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[5] ),
+    .OUT(\mprj_io_out[5] ),
+    .PAD(\mprj_io[5] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[5] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[5] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[5] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[5] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[6]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[6] ),
+    .ANALOG_POL(\mprj_io_analog_pol[6] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[6] ),
+    .DM({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18]  }),
+    .ENABLE_H(\mprj_io_enh[6] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[6] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[6] ),
+    .HLD_OVR(\mprj_io_holdover[6] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[6] ),
+    .IN(\mprj_pads.io_in[6] ),
+    .INP_DIS(\mprj_io_inp_dis[6] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[6] ),
+    .OUT(\mprj_io_out[6] ),
+    .PAD(\mprj_io[6] ),
+    .PAD_A_ESD_0_H(\mprj_pads.no_connect[6] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[6] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[6] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[6] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[7]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[7] ),
+    .ANALOG_POL(\mprj_io_analog_pol[7] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[7] ),
+    .DM({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21]  }),
+    .ENABLE_H(\mprj_io_enh[7] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[7] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[7] ),
+    .HLD_OVR(\mprj_io_holdover[7] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[7] ),
+    .IN(\mprj_pads.io_in[7] ),
+    .INP_DIS(\mprj_io_inp_dis[7] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[7] ),
+    .OUT(\mprj_io_out[7] ),
+    .PAD(\mprj_io[7] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[0] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[7] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[7] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[7] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[8]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[8] ),
+    .ANALOG_POL(\mprj_io_analog_pol[8] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[8] ),
+    .DM({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24]  }),
+    .ENABLE_H(\mprj_io_enh[8] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[8] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[8] ),
+    .HLD_OVR(\mprj_io_holdover[8] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[8] ),
+    .IN(\mprj_pads.io_in[8] ),
+    .INP_DIS(\mprj_io_inp_dis[8] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[8] ),
+    .OUT(\mprj_io_out[8] ),
+    .PAD(\mprj_io[8] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[1] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[8] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[8] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[8] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area1_io_pad[9]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[9] ),
+    .ANALOG_POL(\mprj_io_analog_pol[9] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[9] ),
+    .DM({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27]  }),
+    .ENABLE_H(\mprj_io_enh[9] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[9] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[9] ),
+    .HLD_OVR(\mprj_io_holdover[9] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[9] ),
+    .IN(\mprj_pads.io_in[9] ),
+    .INP_DIS(\mprj_io_inp_dis[9] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[9] ),
+    .OUT(\mprj_io_out[9] ),
+    .PAD(\mprj_io[9] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[2] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[9] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[9] ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[9] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[18] ),
+    .ANALOG_POL(\mprj_io_analog_pol[18] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[18] ),
+    .DM({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54]  }),
+    .ENABLE_H(\mprj_io_enh[18] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[18] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[18] ),
+    .HLD_OVR(\mprj_io_holdover[18] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[18] ),
+    .IN(\mprj_pads.io_in[18] ),
+    .INP_DIS(\mprj_io_inp_dis[18] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[18] ),
+    .OUT(\mprj_io_out[18] ),
+    .PAD(\mprj_io[18] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[11] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[18] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[18] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[18] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[10]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[28] ),
+    .ANALOG_POL(\mprj_io_analog_pol[28] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[28] ),
+    .DM({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84]  }),
+    .ENABLE_H(\mprj_io_enh[28] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[28] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[28] ),
+    .HLD_OVR(\mprj_io_holdover[28] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[28] ),
+    .IN(\mprj_pads.io_in[28] ),
+    .INP_DIS(\mprj_io_inp_dis[28] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[28] ),
+    .OUT(\mprj_io_out[28] ),
+    .PAD(\mprj_io[28] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[21] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[28] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[28] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[28] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[11]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[29] ),
+    .ANALOG_POL(\mprj_io_analog_pol[29] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[29] ),
+    .DM({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87]  }),
+    .ENABLE_H(\mprj_io_enh[29] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[29] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[29] ),
+    .HLD_OVR(\mprj_io_holdover[29] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[29] ),
+    .IN(\mprj_pads.io_in[29] ),
+    .INP_DIS(\mprj_io_inp_dis[29] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[29] ),
+    .OUT(\mprj_io_out[29] ),
+    .PAD(\mprj_io[29] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[22] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[29] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[29] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[29] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[12]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[30] ),
+    .ANALOG_POL(\mprj_io_analog_pol[30] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[30] ),
+    .DM({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90]  }),
+    .ENABLE_H(\mprj_io_enh[30] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[30] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[30] ),
+    .HLD_OVR(\mprj_io_holdover[30] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[30] ),
+    .IN(\mprj_pads.io_in[30] ),
+    .INP_DIS(\mprj_io_inp_dis[30] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[30] ),
+    .OUT(\mprj_io_out[30] ),
+    .PAD(\mprj_io[30] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[23] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[30] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[30] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[30] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[13]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[31] ),
+    .ANALOG_POL(\mprj_io_analog_pol[31] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[31] ),
+    .DM({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93]  }),
+    .ENABLE_H(\mprj_io_enh[31] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[31] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[31] ),
+    .HLD_OVR(\mprj_io_holdover[31] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[31] ),
+    .IN(\mprj_pads.io_in[31] ),
+    .INP_DIS(\mprj_io_inp_dis[31] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[31] ),
+    .OUT(\mprj_io_out[31] ),
+    .PAD(\mprj_io[31] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[24] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[31] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[31] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[31] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[14]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[32] ),
+    .ANALOG_POL(\mprj_io_analog_pol[32] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[32] ),
+    .DM({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96]  }),
+    .ENABLE_H(\mprj_io_enh[32] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[32] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[32] ),
+    .HLD_OVR(\mprj_io_holdover[32] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[32] ),
+    .IN(\mprj_pads.io_in[32] ),
+    .INP_DIS(\mprj_io_inp_dis[32] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[32] ),
+    .OUT(\mprj_io_out[32] ),
+    .PAD(\mprj_io[32] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[25] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[32] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[32] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[32] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[15]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[33] ),
+    .ANALOG_POL(\mprj_io_analog_pol[33] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[33] ),
+    .DM({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99]  }),
+    .ENABLE_H(\mprj_io_enh[33] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[33] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[33] ),
+    .HLD_OVR(\mprj_io_holdover[33] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[33] ),
+    .IN(\mprj_pads.io_in[33] ),
+    .INP_DIS(\mprj_io_inp_dis[33] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[33] ),
+    .OUT(\mprj_io_out[33] ),
+    .PAD(\mprj_io[33] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[26] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[33] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[33] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[33] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[16]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[34] ),
+    .ANALOG_POL(\mprj_io_analog_pol[34] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[34] ),
+    .DM({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102]  }),
+    .ENABLE_H(\mprj_io_enh[34] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[34] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[34] ),
+    .HLD_OVR(\mprj_io_holdover[34] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[34] ),
+    .IN(\mprj_pads.io_in[34] ),
+    .INP_DIS(\mprj_io_inp_dis[34] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[34] ),
+    .OUT(\mprj_io_out[34] ),
+    .PAD(\mprj_io[34] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[27] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[34] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[34] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[34] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[17]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[35] ),
+    .ANALOG_POL(\mprj_io_analog_pol[35] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[35] ),
+    .DM({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105]  }),
+    .ENABLE_H(\mprj_io_enh[35] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[35] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[35] ),
+    .HLD_OVR(\mprj_io_holdover[35] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[35] ),
+    .IN(\mprj_pads.io_in[35] ),
+    .INP_DIS(\mprj_io_inp_dis[35] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[35] ),
+    .OUT(\mprj_io_out[35] ),
+    .PAD(\mprj_io[35] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[28] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[35] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[35] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[35] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[18]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[36] ),
+    .ANALOG_POL(\mprj_io_analog_pol[36] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[36] ),
+    .DM({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108]  }),
+    .ENABLE_H(\mprj_io_enh[36] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[36] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[36] ),
+    .HLD_OVR(\mprj_io_holdover[36] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[36] ),
+    .IN(\mprj_pads.io_in[36] ),
+    .INP_DIS(\mprj_io_inp_dis[36] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[36] ),
+    .OUT(\mprj_io_out[36] ),
+    .PAD(\mprj_io[36] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[29] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[36] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[36] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[36] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[19]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[37] ),
+    .ANALOG_POL(\mprj_io_analog_pol[37] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[37] ),
+    .DM({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111]  }),
+    .ENABLE_H(\mprj_io_enh[37] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[37] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[37] ),
+    .HLD_OVR(\mprj_io_holdover[37] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[37] ),
+    .IN(\mprj_pads.io_in[37] ),
+    .INP_DIS(\mprj_io_inp_dis[37] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[37] ),
+    .OUT(\mprj_io_out[37] ),
+    .PAD(\mprj_io[37] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[30] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[37] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[37] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[37] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[19] ),
+    .ANALOG_POL(\mprj_io_analog_pol[19] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[19] ),
+    .DM({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57]  }),
+    .ENABLE_H(\mprj_io_enh[19] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[19] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[19] ),
+    .HLD_OVR(\mprj_io_holdover[19] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[19] ),
+    .IN(\mprj_pads.io_in[19] ),
+    .INP_DIS(\mprj_io_inp_dis[19] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[19] ),
+    .OUT(\mprj_io_out[19] ),
+    .PAD(\mprj_io[19] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[12] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[19] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[19] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[19] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[2]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[20] ),
+    .ANALOG_POL(\mprj_io_analog_pol[20] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[20] ),
+    .DM({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60]  }),
+    .ENABLE_H(\mprj_io_enh[20] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[20] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[20] ),
+    .HLD_OVR(\mprj_io_holdover[20] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[20] ),
+    .IN(\mprj_pads.io_in[20] ),
+    .INP_DIS(\mprj_io_inp_dis[20] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[20] ),
+    .OUT(\mprj_io_out[20] ),
+    .PAD(\mprj_io[20] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[13] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[20] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[20] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[20] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[3]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[21] ),
+    .ANALOG_POL(\mprj_io_analog_pol[21] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[21] ),
+    .DM({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63]  }),
+    .ENABLE_H(\mprj_io_enh[21] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[21] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[21] ),
+    .HLD_OVR(\mprj_io_holdover[21] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[21] ),
+    .IN(\mprj_pads.io_in[21] ),
+    .INP_DIS(\mprj_io_inp_dis[21] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[21] ),
+    .OUT(\mprj_io_out[21] ),
+    .PAD(\mprj_io[21] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[14] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[21] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[21] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[21] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[4]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[22] ),
+    .ANALOG_POL(\mprj_io_analog_pol[22] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[22] ),
+    .DM({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66]  }),
+    .ENABLE_H(\mprj_io_enh[22] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[22] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[22] ),
+    .HLD_OVR(\mprj_io_holdover[22] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[22] ),
+    .IN(\mprj_pads.io_in[22] ),
+    .INP_DIS(\mprj_io_inp_dis[22] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[22] ),
+    .OUT(\mprj_io_out[22] ),
+    .PAD(\mprj_io[22] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[15] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[22] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[22] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[22] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[5]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[23] ),
+    .ANALOG_POL(\mprj_io_analog_pol[23] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[23] ),
+    .DM({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69]  }),
+    .ENABLE_H(\mprj_io_enh[23] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[23] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[23] ),
+    .HLD_OVR(\mprj_io_holdover[23] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[23] ),
+    .IN(\mprj_pads.io_in[23] ),
+    .INP_DIS(\mprj_io_inp_dis[23] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[23] ),
+    .OUT(\mprj_io_out[23] ),
+    .PAD(\mprj_io[23] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[16] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[23] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[23] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[23] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[6]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[24] ),
+    .ANALOG_POL(\mprj_io_analog_pol[24] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[24] ),
+    .DM({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72]  }),
+    .ENABLE_H(\mprj_io_enh[24] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[24] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[24] ),
+    .HLD_OVR(\mprj_io_holdover[24] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[24] ),
+    .IN(\mprj_pads.io_in[24] ),
+    .INP_DIS(\mprj_io_inp_dis[24] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[24] ),
+    .OUT(\mprj_io_out[24] ),
+    .PAD(\mprj_io[24] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[17] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[24] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[24] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[24] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[7]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[25] ),
+    .ANALOG_POL(\mprj_io_analog_pol[25] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[25] ),
+    .DM({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75]  }),
+    .ENABLE_H(\mprj_io_enh[25] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[25] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[25] ),
+    .HLD_OVR(\mprj_io_holdover[25] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[25] ),
+    .IN(\mprj_pads.io_in[25] ),
+    .INP_DIS(\mprj_io_inp_dis[25] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[25] ),
+    .OUT(\mprj_io_out[25] ),
+    .PAD(\mprj_io[25] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[18] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[25] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[25] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[25] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[8]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[26] ),
+    .ANALOG_POL(\mprj_io_analog_pol[26] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[26] ),
+    .DM({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78]  }),
+    .ENABLE_H(\mprj_io_enh[26] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[26] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[26] ),
+    .HLD_OVR(\mprj_io_holdover[26] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[26] ),
+    .IN(\mprj_pads.io_in[26] ),
+    .INP_DIS(\mprj_io_inp_dis[26] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[26] ),
+    .OUT(\mprj_io_out[26] ),
+    .PAD(\mprj_io[26] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[19] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[26] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[26] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[26] )
+  );
+  sky130_ef_io__gpiov2_pad_wrapped \mprj_pads.area2_io_pad[9]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .ANALOG_EN(\mprj_io_analog_en[27] ),
+    .ANALOG_POL(\mprj_io_analog_pol[27] ),
+    .ANALOG_SEL(\mprj_io_analog_sel[27] ),
+    .DM({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81]  }),
+    .ENABLE_H(\mprj_io_enh[27] ),
+    .ENABLE_INP_H(\mprj_pads.loop1_io[27] ),
+    .ENABLE_VDDA_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .ENABLE_VSWITCH_H(vssio),
+    .HLD_H_N(\mprj_io_hldh_n[27] ),
+    .HLD_OVR(\mprj_io_holdover[27] ),
+    .IB_MODE_SEL(\mprj_io_ib_mode_sel[27] ),
+    .IN(\mprj_pads.io_in[27] ),
+    .INP_DIS(\mprj_io_inp_dis[27] ),
+    .IN_H(),
+    .OE_N(\mprj_io_oeb[27] ),
+    .OUT(\mprj_io_out[27] ),
+    .PAD(\mprj_io[27] ),
+    .PAD_A_ESD_0_H(\mprj_analog_io[20] ),
+    .PAD_A_ESD_1_H(),
+    .PAD_A_NOESD_H(),
+    .SLOW(\mprj_io_slow_sel[27] ),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(\mprj_pads.loop1_io[27] ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .VTRIP_SEL(\mprj_io_vtrip_sel[27] )
+  );
+  sky130_fd_io__top_xres4v2 resetb_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .DISABLE_PULLUP_H(vssio),
+    .ENABLE_H(porb_h),
+    .ENABLE_VDDIO(vccd),
+    .EN_VDDIO_SIG_H(vssio),
+    .FILT_IN_H(vssio),
+    .INP_SEL_H(vssio),
+    .PAD(resetb),
+    .PAD_A_ESD_H(xresloop),
+    .PULLUP_H(vssio),
+    .TIE_HI_ESD(),
+    .TIE_LO_ESD(),
+    .TIE_WEAK_HI_H(xresloop),
+    .VCCD(vccd),
+    .VCCHIB(vccd),
+    .VDDA(vdda),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa),
+    .VSSD(vssd),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio),
+    .XRES_H_N(resetb_core_h)
+  );
+  sky130_ef_io__corner_pad user1_corner (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vccd_lvc_clamped2_pad user1_vccd_lvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1]  (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssd_lvc_clamped2_pad user1_vssd_lvclmap_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd1),
+    .VCCHIB(vccd),
+    .VDDA(vdda1),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa1),
+    .VSSD(vssd1),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__corner_pad user2_corner (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vccd_lvc_clamped2_pad user2_vccd_lvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  sky130_ef_io__vssd_lvc_clamped2_pad user2_vssd_lvclmap_pad (
+    .AMUXBUS_A(\mprj_pads.analog_a ),
+    .AMUXBUS_B(\mprj_pads.analog_b ),
+    .VCCD(vccd2),
+    .VCCHIB(vccd),
+    .VDDA(vdda2),
+    .VDDIO(vddio),
+    .VDDIO_Q(\mprj_pads.vddio_q ),
+    .VSSA(vssa2),
+    .VSSD(vssd2),
+    .VSSIO(vssio),
+    .VSSIO_Q(\mprj_pads.vssio_q ),
+    .VSWITCH(vddio)
+  );
+  assign \mprj_pads.slow_sel[19]  = \mprj_io_slow_sel[19] ;
+  assign \mprj_pads.slow_sel[18]  = \mprj_io_slow_sel[18] ;
+  assign \mprj_pads.slow_sel[17]  = \mprj_io_slow_sel[17] ;
+  assign \mprj_pads.slow_sel[16]  = \mprj_io_slow_sel[16] ;
+  assign \mprj_pads.slow_sel[15]  = \mprj_io_slow_sel[15] ;
+  assign \mprj_pads.slow_sel[14]  = \mprj_io_slow_sel[14] ;
+  assign \mprj_pads.slow_sel[13]  = \mprj_io_slow_sel[13] ;
+  assign \mprj_pads.slow_sel[12]  = \mprj_io_slow_sel[12] ;
+  assign \mprj_pads.slow_sel[11]  = \mprj_io_slow_sel[11] ;
+  assign \mprj_pads.slow_sel[10]  = \mprj_io_slow_sel[10] ;
+  assign \mprj_pads.slow_sel[9]  = \mprj_io_slow_sel[9] ;
+  assign \mprj_pads.slow_sel[8]  = \mprj_io_slow_sel[8] ;
+  assign \mprj_pads.slow_sel[7]  = \mprj_io_slow_sel[7] ;
+  assign \mprj_pads.slow_sel[6]  = \mprj_io_slow_sel[6] ;
+  assign \mprj_pads.slow_sel[5]  = \mprj_io_slow_sel[5] ;
+  assign \mprj_pads.slow_sel[4]  = \mprj_io_slow_sel[4] ;
+  assign \mprj_pads.slow_sel[3]  = \mprj_io_slow_sel[3] ;
+  assign \mprj_pads.slow_sel[2]  = \mprj_io_slow_sel[2] ;
+  assign \mprj_pads.slow_sel[1]  = \mprj_io_slow_sel[1] ;
+  assign \mprj_pads.slow_sel[0]  = \mprj_io_slow_sel[0] ;
+  assign \mprj_pads.enh[37]  = \mprj_io_enh[37] ;
+  assign \mprj_pads.enh[36]  = \mprj_io_enh[36] ;
+  assign \mprj_pads.enh[35]  = \mprj_io_enh[35] ;
+  assign \mprj_pads.enh[34]  = \mprj_io_enh[34] ;
+  assign \mprj_pads.enh[33]  = \mprj_io_enh[33] ;
+  assign \mprj_pads.enh[32]  = \mprj_io_enh[32] ;
+  assign \mprj_pads.enh[31]  = \mprj_io_enh[31] ;
+  assign \mprj_pads.enh[30]  = \mprj_io_enh[30] ;
+  assign \mprj_pads.enh[29]  = \mprj_io_enh[29] ;
+  assign \mprj_pads.enh[28]  = \mprj_io_enh[28] ;
+  assign \mprj_pads.enh[27]  = \mprj_io_enh[27] ;
+  assign \mprj_pads.enh[26]  = \mprj_io_enh[26] ;
+  assign \mprj_pads.enh[25]  = \mprj_io_enh[25] ;
+  assign \mprj_pads.enh[24]  = \mprj_io_enh[24] ;
+  assign \mprj_pads.enh[23]  = \mprj_io_enh[23] ;
+  assign \mprj_pads.enh[22]  = \mprj_io_enh[22] ;
+  assign \mprj_pads.enh[21]  = \mprj_io_enh[21] ;
+  assign \mprj_pads.enh[20]  = \mprj_io_enh[20] ;
+  assign \mprj_pads.enh[19]  = \mprj_io_enh[19] ;
+  assign \mprj_pads.enh[18]  = \mprj_io_enh[18] ;
+  assign \mprj_pads.enh[17]  = \mprj_io_enh[17] ;
+  assign \mprj_pads.enh[16]  = \mprj_io_enh[16] ;
+  assign \mprj_pads.enh[15]  = \mprj_io_enh[15] ;
+  assign \mprj_pads.enh[14]  = \mprj_io_enh[14] ;
+  assign \mprj_pads.enh[13]  = \mprj_io_enh[13] ;
+  assign \mprj_pads.enh[12]  = \mprj_io_enh[12] ;
+  assign \mprj_pads.enh[11]  = \mprj_io_enh[11] ;
+  assign \mprj_pads.enh[10]  = \mprj_io_enh[10] ;
+  assign \mprj_pads.enh[9]  = \mprj_io_enh[9] ;
+  assign \mprj_pads.enh[8]  = \mprj_io_enh[8] ;
+  assign \mprj_pads.enh[7]  = \mprj_io_enh[7] ;
+  assign \mprj_pads.enh[6]  = \mprj_io_enh[6] ;
+  assign \mprj_pads.enh[5]  = \mprj_io_enh[5] ;
+  assign \mprj_pads.enh[4]  = \mprj_io_enh[4] ;
+  assign \mprj_pads.enh[3]  = \mprj_io_enh[3] ;
+  assign \mprj_pads.enh[2]  = \mprj_io_enh[2] ;
+  assign \mprj_pads.enh[1]  = \mprj_io_enh[1] ;
+  assign \mprj_pads.enh[0]  = \mprj_io_enh[0] ;
+  assign \mprj_pads.hldh_n[37]  = \mprj_io_hldh_n[37] ;
+  assign \mprj_pads.hldh_n[36]  = \mprj_io_hldh_n[36] ;
+  assign \mprj_pads.hldh_n[35]  = \mprj_io_hldh_n[35] ;
+  assign \mprj_pads.hldh_n[34]  = \mprj_io_hldh_n[34] ;
+  assign \mprj_pads.hldh_n[33]  = \mprj_io_hldh_n[33] ;
+  assign \mprj_pads.hldh_n[32]  = \mprj_io_hldh_n[32] ;
+  assign \mprj_pads.hldh_n[31]  = \mprj_io_hldh_n[31] ;
+  assign \mprj_pads.hldh_n[30]  = \mprj_io_hldh_n[30] ;
+  assign \mprj_pads.hldh_n[29]  = \mprj_io_hldh_n[29] ;
+  assign \mprj_pads.hldh_n[28]  = \mprj_io_hldh_n[28] ;
+  assign \mprj_pads.hldh_n[27]  = \mprj_io_hldh_n[27] ;
+  assign \mprj_pads.hldh_n[26]  = \mprj_io_hldh_n[26] ;
+  assign \mprj_pads.hldh_n[25]  = \mprj_io_hldh_n[25] ;
+  assign \mprj_pads.hldh_n[24]  = \mprj_io_hldh_n[24] ;
+  assign \mprj_pads.hldh_n[23]  = \mprj_io_hldh_n[23] ;
+  assign \mprj_pads.hldh_n[22]  = \mprj_io_hldh_n[22] ;
+  assign \mprj_pads.hldh_n[21]  = \mprj_io_hldh_n[21] ;
+  assign \mprj_pads.hldh_n[20]  = \mprj_io_hldh_n[20] ;
+  assign \mprj_pads.hldh_n[19]  = \mprj_io_hldh_n[19] ;
+  assign \mprj_pads.hldh_n[18]  = \mprj_io_hldh_n[18] ;
+  assign \mprj_pads.hldh_n[17]  = \mprj_io_hldh_n[17] ;
+  assign \mprj_pads.hldh_n[16]  = \mprj_io_hldh_n[16] ;
+  assign \mprj_pads.hldh_n[15]  = \mprj_io_hldh_n[15] ;
+  assign \mprj_pads.hldh_n[14]  = \mprj_io_hldh_n[14] ;
+  assign \mprj_pads.hldh_n[13]  = \mprj_io_hldh_n[13] ;
+  assign \mprj_pads.hldh_n[12]  = \mprj_io_hldh_n[12] ;
+  assign \mprj_pads.hldh_n[11]  = \mprj_io_hldh_n[11] ;
+  assign \mprj_pads.hldh_n[10]  = \mprj_io_hldh_n[10] ;
+  assign \mprj_pads.hldh_n[9]  = \mprj_io_hldh_n[9] ;
+  assign \mprj_pads.hldh_n[8]  = \mprj_io_hldh_n[8] ;
+  assign \mprj_pads.hldh_n[7]  = \mprj_io_hldh_n[7] ;
+  assign \mprj_pads.hldh_n[6]  = \mprj_io_hldh_n[6] ;
+  assign \mprj_pads.hldh_n[5]  = \mprj_io_hldh_n[5] ;
+  assign \mprj_pads.hldh_n[4]  = \mprj_io_hldh_n[4] ;
+  assign \mprj_pads.hldh_n[3]  = \mprj_io_hldh_n[3] ;
+  assign \mprj_pads.hldh_n[2]  = \mprj_io_hldh_n[2] ;
+  assign \mprj_pads.hldh_n[1]  = \mprj_io_hldh_n[1] ;
+  assign \mprj_pads.hldh_n[0]  = \mprj_io_hldh_n[0] ;
+  assign \mprj_pads.io[37]  = \mprj_io[37] ;
+  assign \mprj_pads.io[36]  = \mprj_io[36] ;
+  assign \mprj_pads.io[35]  = \mprj_io[35] ;
+  assign \mprj_pads.io[34]  = \mprj_io[34] ;
+  assign \mprj_pads.io[33]  = \mprj_io[33] ;
+  assign \mprj_pads.io[32]  = \mprj_io[32] ;
+  assign \mprj_pads.io[31]  = \mprj_io[31] ;
+  assign \mprj_pads.io[30]  = \mprj_io[30] ;
+  assign \mprj_pads.io[29]  = \mprj_io[29] ;
+  assign \mprj_pads.io[28]  = \mprj_io[28] ;
+  assign \mprj_pads.io[27]  = \mprj_io[27] ;
+  assign \mprj_pads.io[26]  = \mprj_io[26] ;
+  assign \mprj_pads.io[25]  = \mprj_io[25] ;
+  assign \mprj_pads.io[24]  = \mprj_io[24] ;
+  assign \mprj_pads.io[23]  = \mprj_io[23] ;
+  assign \mprj_pads.io[22]  = \mprj_io[22] ;
+  assign \mprj_pads.io[21]  = \mprj_io[21] ;
+  assign \mprj_pads.io[20]  = \mprj_io[20] ;
+  assign \mprj_pads.io[19]  = \mprj_io[19] ;
+  assign \mprj_pads.io[18]  = \mprj_io[18] ;
+  assign \mprj_pads.io[17]  = \mprj_io[17] ;
+  assign \mprj_pads.io[16]  = \mprj_io[16] ;
+  assign \mprj_pads.io[15]  = \mprj_io[15] ;
+  assign \mprj_pads.io[14]  = \mprj_io[14] ;
+  assign \mprj_pads.io[13]  = \mprj_io[13] ;
+  assign \mprj_pads.io[12]  = \mprj_io[12] ;
+  assign \mprj_pads.io[11]  = \mprj_io[11] ;
+  assign \mprj_pads.io[10]  = \mprj_io[10] ;
+  assign \mprj_pads.io[9]  = \mprj_io[9] ;
+  assign \mprj_pads.io[8]  = \mprj_io[8] ;
+  assign \mprj_pads.io[7]  = \mprj_io[7] ;
+  assign \mprj_pads.io[6]  = \mprj_io[6] ;
+  assign \mprj_pads.io[5]  = \mprj_io[5] ;
+  assign \mprj_pads.io[4]  = \mprj_io[4] ;
+  assign \mprj_pads.io[3]  = \mprj_io[3] ;
+  assign \mprj_pads.io[2]  = \mprj_io[2] ;
+  assign \mprj_pads.io[1]  = \mprj_io[1] ;
+  assign \mprj_pads.io[0]  = \mprj_io[0] ;
+  assign \mprj_pads.analog_io[30]  = \mprj_analog_io[30] ;
+  assign \mprj_pads.analog_io[29]  = \mprj_analog_io[29] ;
+  assign \mprj_pads.analog_io[28]  = \mprj_analog_io[28] ;
+  assign \mprj_pads.analog_io[27]  = \mprj_analog_io[27] ;
+  assign \mprj_pads.analog_io[26]  = \mprj_analog_io[26] ;
+  assign \mprj_pads.analog_io[25]  = \mprj_analog_io[25] ;
+  assign \mprj_pads.analog_io[24]  = \mprj_analog_io[24] ;
+  assign \mprj_pads.analog_io[23]  = \mprj_analog_io[23] ;
+  assign \mprj_pads.analog_io[22]  = \mprj_analog_io[22] ;
+  assign \mprj_pads.analog_io[21]  = \mprj_analog_io[21] ;
+  assign \mprj_pads.analog_io[20]  = \mprj_analog_io[20] ;
+  assign \mprj_pads.analog_io[19]  = \mprj_analog_io[19] ;
+  assign \mprj_pads.analog_io[18]  = \mprj_analog_io[18] ;
+  assign \mprj_pads.analog_io[17]  = \mprj_analog_io[17] ;
+  assign \mprj_pads.analog_io[16]  = \mprj_analog_io[16] ;
+  assign \mprj_pads.analog_io[15]  = \mprj_analog_io[15] ;
+  assign \mprj_pads.analog_io[14]  = \mprj_analog_io[14] ;
+  assign \mprj_pads.analog_io[13]  = \mprj_analog_io[13] ;
+  assign \mprj_pads.analog_io[12]  = \mprj_analog_io[12] ;
+  assign \mprj_pads.analog_io[11]  = \mprj_analog_io[11] ;
+  assign \mprj_pads.analog_io[10]  = \mprj_analog_io[10] ;
+  assign \mprj_pads.analog_io[9]  = \mprj_analog_io[9] ;
+  assign \mprj_pads.analog_io[8]  = \mprj_analog_io[8] ;
+  assign \mprj_pads.analog_io[7]  = \mprj_analog_io[7] ;
+  assign \mprj_pads.analog_io[6]  = \mprj_analog_io[6] ;
+  assign \mprj_pads.analog_io[5]  = \mprj_analog_io[5] ;
+  assign \mprj_pads.analog_io[4]  = \mprj_analog_io[4] ;
+  assign \mprj_pads.analog_io[3]  = \mprj_analog_io[3] ;
+  assign \mprj_pads.analog_io[2]  = \mprj_analog_io[2] ;
+  assign \mprj_pads.analog_io[1]  = \mprj_analog_io[1] ;
+  assign \mprj_pads.analog_io[0]  = \mprj_analog_io[0] ;
+  assign \flash_io1_mode[2]  = flash_io1_ieb_core;
+  assign \flash_io1_mode[1]  = flash_io1_ieb_core;
+  assign \flash_io1_mode[0]  = flash_io1_oeb_core;
+  assign \dm_all[2]  = gpio_mode1_core;
+  assign \dm_all[1]  = gpio_mode1_core;
+  assign \dm_all[0]  = gpio_mode0_core;
+  assign \mprj_pads.analog_sel[37]  = \mprj_io_analog_sel[37] ;
+  assign \mprj_pads.analog_sel[36]  = \mprj_io_analog_sel[36] ;
+  assign \mprj_pads.analog_sel[35]  = \mprj_io_analog_sel[35] ;
+  assign \mprj_pads.analog_sel[34]  = \mprj_io_analog_sel[34] ;
+  assign \mprj_pads.analog_sel[33]  = \mprj_io_analog_sel[33] ;
+  assign \mprj_pads.analog_sel[32]  = \mprj_io_analog_sel[32] ;
+  assign \mprj_pads.analog_sel[31]  = \mprj_io_analog_sel[31] ;
+  assign \mprj_pads.analog_sel[30]  = \mprj_io_analog_sel[30] ;
+  assign \mprj_pads.analog_sel[29]  = \mprj_io_analog_sel[29] ;
+  assign \mprj_pads.analog_sel[28]  = \mprj_io_analog_sel[28] ;
+  assign \mprj_pads.analog_sel[27]  = \mprj_io_analog_sel[27] ;
+  assign \mprj_pads.analog_sel[26]  = \mprj_io_analog_sel[26] ;
+  assign \mprj_pads.analog_sel[25]  = \mprj_io_analog_sel[25] ;
+  assign \mprj_pads.analog_sel[24]  = \mprj_io_analog_sel[24] ;
+  assign \mprj_pads.analog_sel[23]  = \mprj_io_analog_sel[23] ;
+  assign \mprj_pads.analog_sel[22]  = \mprj_io_analog_sel[22] ;
+  assign \mprj_pads.analog_sel[21]  = \mprj_io_analog_sel[21] ;
+  assign \mprj_pads.analog_sel[20]  = \mprj_io_analog_sel[20] ;
+  assign \mprj_pads.analog_sel[19]  = \mprj_io_analog_sel[19] ;
+  assign \mprj_pads.analog_sel[18]  = \mprj_io_analog_sel[18] ;
+  assign \mprj_pads.analog_sel[17]  = \mprj_io_analog_sel[17] ;
+  assign \mprj_pads.analog_sel[16]  = \mprj_io_analog_sel[16] ;
+  assign \mprj_pads.analog_sel[15]  = \mprj_io_analog_sel[15] ;
+  assign \mprj_pads.analog_sel[14]  = \mprj_io_analog_sel[14] ;
+  assign \mprj_pads.analog_sel[13]  = \mprj_io_analog_sel[13] ;
+  assign \mprj_pads.analog_sel[12]  = \mprj_io_analog_sel[12] ;
+  assign \mprj_pads.analog_sel[11]  = \mprj_io_analog_sel[11] ;
+  assign \mprj_pads.analog_sel[10]  = \mprj_io_analog_sel[10] ;
+  assign \mprj_pads.analog_sel[9]  = \mprj_io_analog_sel[9] ;
+  assign \mprj_pads.analog_sel[8]  = \mprj_io_analog_sel[8] ;
+  assign \mprj_pads.analog_sel[7]  = \mprj_io_analog_sel[7] ;
+  assign \mprj_pads.analog_sel[6]  = \mprj_io_analog_sel[6] ;
+  assign \mprj_pads.analog_sel[5]  = \mprj_io_analog_sel[5] ;
+  assign \mprj_pads.analog_sel[4]  = \mprj_io_analog_sel[4] ;
+  assign \mprj_pads.analog_sel[3]  = \mprj_io_analog_sel[3] ;
+  assign \mprj_pads.analog_sel[2]  = \mprj_io_analog_sel[2] ;
+  assign \mprj_pads.analog_sel[1]  = \mprj_io_analog_sel[1] ;
+  assign \mprj_pads.analog_sel[0]  = \mprj_io_analog_sel[0] ;
+  assign \mprj_pads.vtrip_sel[37]  = \mprj_io_vtrip_sel[37] ;
+  assign \mprj_pads.vtrip_sel[36]  = \mprj_io_vtrip_sel[36] ;
+  assign \mprj_pads.vtrip_sel[35]  = \mprj_io_vtrip_sel[35] ;
+  assign \mprj_pads.vtrip_sel[34]  = \mprj_io_vtrip_sel[34] ;
+  assign \mprj_pads.vtrip_sel[33]  = \mprj_io_vtrip_sel[33] ;
+  assign \mprj_pads.vtrip_sel[32]  = \mprj_io_vtrip_sel[32] ;
+  assign \mprj_pads.vtrip_sel[31]  = \mprj_io_vtrip_sel[31] ;
+  assign \mprj_pads.vtrip_sel[30]  = \mprj_io_vtrip_sel[30] ;
+  assign \mprj_pads.vtrip_sel[29]  = \mprj_io_vtrip_sel[29] ;
+  assign \mprj_pads.vtrip_sel[28]  = \mprj_io_vtrip_sel[28] ;
+  assign \mprj_pads.vtrip_sel[27]  = \mprj_io_vtrip_sel[27] ;
+  assign \mprj_pads.vtrip_sel[26]  = \mprj_io_vtrip_sel[26] ;
+  assign \mprj_pads.vtrip_sel[25]  = \mprj_io_vtrip_sel[25] ;
+  assign \mprj_pads.vtrip_sel[24]  = \mprj_io_vtrip_sel[24] ;
+  assign \mprj_pads.vtrip_sel[23]  = \mprj_io_vtrip_sel[23] ;
+  assign \mprj_pads.vtrip_sel[22]  = \mprj_io_vtrip_sel[22] ;
+  assign \mprj_pads.vtrip_sel[21]  = \mprj_io_vtrip_sel[21] ;
+  assign \mprj_pads.vtrip_sel[20]  = \mprj_io_vtrip_sel[20] ;
+  assign \mprj_pads.vtrip_sel[19]  = \mprj_io_vtrip_sel[19] ;
+  assign \mprj_pads.vtrip_sel[18]  = \mprj_io_vtrip_sel[18] ;
+  assign \mprj_pads.vtrip_sel[17]  = \mprj_io_vtrip_sel[17] ;
+  assign \mprj_pads.vtrip_sel[16]  = \mprj_io_vtrip_sel[16] ;
+  assign \mprj_pads.vtrip_sel[15]  = \mprj_io_vtrip_sel[15] ;
+  assign \mprj_pads.vtrip_sel[14]  = \mprj_io_vtrip_sel[14] ;
+  assign \mprj_pads.vtrip_sel[13]  = \mprj_io_vtrip_sel[13] ;
+  assign \mprj_pads.vtrip_sel[12]  = \mprj_io_vtrip_sel[12] ;
+  assign \mprj_pads.vtrip_sel[11]  = \mprj_io_vtrip_sel[11] ;
+  assign \mprj_pads.vtrip_sel[10]  = \mprj_io_vtrip_sel[10] ;
+  assign \mprj_pads.vtrip_sel[9]  = \mprj_io_vtrip_sel[9] ;
+  assign \mprj_pads.vtrip_sel[8]  = \mprj_io_vtrip_sel[8] ;
+  assign \mprj_pads.vtrip_sel[7]  = \mprj_io_vtrip_sel[7] ;
+  assign \mprj_pads.vtrip_sel[6]  = \mprj_io_vtrip_sel[6] ;
+  assign \mprj_pads.vtrip_sel[5]  = \mprj_io_vtrip_sel[5] ;
+  assign \mprj_pads.vtrip_sel[4]  = \mprj_io_vtrip_sel[4] ;
+  assign \mprj_pads.vtrip_sel[3]  = \mprj_io_vtrip_sel[3] ;
+  assign \mprj_pads.vtrip_sel[2]  = \mprj_io_vtrip_sel[2] ;
+  assign \mprj_pads.vtrip_sel[1]  = \mprj_io_vtrip_sel[1] ;
+  assign \mprj_pads.vtrip_sel[0]  = \mprj_io_vtrip_sel[0] ;
+  assign \mprj_pads.analog_pol[37]  = \mprj_io_analog_pol[37] ;
+  assign \mprj_pads.analog_pol[36]  = \mprj_io_analog_pol[36] ;
+  assign \mprj_pads.analog_pol[35]  = \mprj_io_analog_pol[35] ;
+  assign \mprj_pads.analog_pol[34]  = \mprj_io_analog_pol[34] ;
+  assign \mprj_pads.analog_pol[33]  = \mprj_io_analog_pol[33] ;
+  assign \mprj_pads.analog_pol[32]  = \mprj_io_analog_pol[32] ;
+  assign \mprj_pads.analog_pol[31]  = \mprj_io_analog_pol[31] ;
+  assign \mprj_pads.analog_pol[30]  = \mprj_io_analog_pol[30] ;
+  assign \mprj_pads.analog_pol[29]  = \mprj_io_analog_pol[29] ;
+  assign \mprj_pads.analog_pol[28]  = \mprj_io_analog_pol[28] ;
+  assign \mprj_pads.analog_pol[27]  = \mprj_io_analog_pol[27] ;
+  assign \mprj_pads.analog_pol[26]  = \mprj_io_analog_pol[26] ;
+  assign \mprj_pads.analog_pol[25]  = \mprj_io_analog_pol[25] ;
+  assign \mprj_pads.analog_pol[24]  = \mprj_io_analog_pol[24] ;
+  assign \mprj_pads.analog_pol[23]  = \mprj_io_analog_pol[23] ;
+  assign \mprj_pads.analog_pol[22]  = \mprj_io_analog_pol[22] ;
+  assign \mprj_pads.analog_pol[21]  = \mprj_io_analog_pol[21] ;
+  assign \mprj_pads.analog_pol[20]  = \mprj_io_analog_pol[20] ;
+  assign \mprj_pads.analog_pol[19]  = \mprj_io_analog_pol[19] ;
+  assign \mprj_pads.analog_pol[18]  = \mprj_io_analog_pol[18] ;
+  assign \mprj_pads.analog_pol[17]  = \mprj_io_analog_pol[17] ;
+  assign \mprj_pads.analog_pol[16]  = \mprj_io_analog_pol[16] ;
+  assign \mprj_pads.analog_pol[15]  = \mprj_io_analog_pol[15] ;
+  assign \mprj_pads.analog_pol[14]  = \mprj_io_analog_pol[14] ;
+  assign \mprj_pads.analog_pol[13]  = \mprj_io_analog_pol[13] ;
+  assign \mprj_pads.analog_pol[12]  = \mprj_io_analog_pol[12] ;
+  assign \mprj_pads.analog_pol[11]  = \mprj_io_analog_pol[11] ;
+  assign \mprj_pads.analog_pol[10]  = \mprj_io_analog_pol[10] ;
+  assign \mprj_pads.analog_pol[9]  = \mprj_io_analog_pol[9] ;
+  assign \mprj_pads.analog_pol[8]  = \mprj_io_analog_pol[8] ;
+  assign \mprj_pads.analog_pol[7]  = \mprj_io_analog_pol[7] ;
+  assign \mprj_pads.analog_pol[6]  = \mprj_io_analog_pol[6] ;
+  assign \mprj_pads.analog_pol[5]  = \mprj_io_analog_pol[5] ;
+  assign \mprj_pads.analog_pol[4]  = \mprj_io_analog_pol[4] ;
+  assign \mprj_pads.analog_pol[3]  = \mprj_io_analog_pol[3] ;
+  assign \mprj_pads.analog_pol[2]  = \mprj_io_analog_pol[2] ;
+  assign \mprj_pads.analog_pol[1]  = \mprj_io_analog_pol[1] ;
+  assign \mprj_pads.analog_pol[0]  = \mprj_io_analog_pol[0] ;
+  assign \mprj_pads.oeb[37]  = \mprj_io_oeb[37] ;
+  assign \mprj_pads.oeb[36]  = \mprj_io_oeb[36] ;
+  assign \mprj_pads.oeb[35]  = \mprj_io_oeb[35] ;
+  assign \mprj_pads.oeb[34]  = \mprj_io_oeb[34] ;
+  assign \mprj_pads.oeb[33]  = \mprj_io_oeb[33] ;
+  assign \mprj_pads.oeb[32]  = \mprj_io_oeb[32] ;
+  assign \mprj_pads.oeb[31]  = \mprj_io_oeb[31] ;
+  assign \mprj_pads.oeb[30]  = \mprj_io_oeb[30] ;
+  assign \mprj_pads.oeb[29]  = \mprj_io_oeb[29] ;
+  assign \mprj_pads.oeb[28]  = \mprj_io_oeb[28] ;
+  assign \mprj_pads.oeb[27]  = \mprj_io_oeb[27] ;
+  assign \mprj_pads.oeb[26]  = \mprj_io_oeb[26] ;
+  assign \mprj_pads.oeb[25]  = \mprj_io_oeb[25] ;
+  assign \mprj_pads.oeb[24]  = \mprj_io_oeb[24] ;
+  assign \mprj_pads.oeb[23]  = \mprj_io_oeb[23] ;
+  assign \mprj_pads.oeb[22]  = \mprj_io_oeb[22] ;
+  assign \mprj_pads.oeb[21]  = \mprj_io_oeb[21] ;
+  assign \mprj_pads.oeb[20]  = \mprj_io_oeb[20] ;
+  assign \mprj_pads.oeb[19]  = \mprj_io_oeb[19] ;
+  assign \mprj_pads.oeb[18]  = \mprj_io_oeb[18] ;
+  assign \mprj_pads.oeb[17]  = \mprj_io_oeb[17] ;
+  assign \mprj_pads.oeb[16]  = \mprj_io_oeb[16] ;
+  assign \mprj_pads.oeb[15]  = \mprj_io_oeb[15] ;
+  assign \mprj_pads.oeb[14]  = \mprj_io_oeb[14] ;
+  assign \mprj_pads.oeb[13]  = \mprj_io_oeb[13] ;
+  assign \mprj_pads.oeb[12]  = \mprj_io_oeb[12] ;
+  assign \mprj_pads.oeb[11]  = \mprj_io_oeb[11] ;
+  assign \mprj_pads.oeb[10]  = \mprj_io_oeb[10] ;
+  assign \mprj_pads.oeb[9]  = \mprj_io_oeb[9] ;
+  assign \mprj_pads.oeb[8]  = \mprj_io_oeb[8] ;
+  assign \mprj_pads.oeb[7]  = \mprj_io_oeb[7] ;
+  assign \mprj_pads.oeb[6]  = \mprj_io_oeb[6] ;
+  assign \mprj_pads.oeb[5]  = \mprj_io_oeb[5] ;
+  assign \mprj_pads.oeb[4]  = \mprj_io_oeb[4] ;
+  assign \mprj_pads.oeb[3]  = \mprj_io_oeb[3] ;
+  assign \mprj_pads.oeb[2]  = \mprj_io_oeb[2] ;
+  assign \mprj_pads.oeb[1]  = \mprj_io_oeb[1] ;
+  assign \mprj_pads.oeb[0]  = \mprj_io_oeb[0] ;
+  assign \mprj_pads.analog_en[37]  = \mprj_io_analog_en[37] ;
+  assign \mprj_pads.analog_en[36]  = \mprj_io_analog_en[36] ;
+  assign \mprj_pads.analog_en[35]  = \mprj_io_analog_en[35] ;
+  assign \mprj_pads.analog_en[34]  = \mprj_io_analog_en[34] ;
+  assign \mprj_pads.analog_en[33]  = \mprj_io_analog_en[33] ;
+  assign \mprj_pads.analog_en[32]  = \mprj_io_analog_en[32] ;
+  assign \mprj_pads.analog_en[31]  = \mprj_io_analog_en[31] ;
+  assign \mprj_pads.analog_en[30]  = \mprj_io_analog_en[30] ;
+  assign \mprj_pads.analog_en[29]  = \mprj_io_analog_en[29] ;
+  assign \mprj_pads.analog_en[28]  = \mprj_io_analog_en[28] ;
+  assign \mprj_pads.analog_en[27]  = \mprj_io_analog_en[27] ;
+  assign \mprj_pads.analog_en[26]  = \mprj_io_analog_en[26] ;
+  assign \mprj_pads.analog_en[25]  = \mprj_io_analog_en[25] ;
+  assign \mprj_pads.analog_en[24]  = \mprj_io_analog_en[24] ;
+  assign \mprj_pads.analog_en[23]  = \mprj_io_analog_en[23] ;
+  assign \mprj_pads.analog_en[22]  = \mprj_io_analog_en[22] ;
+  assign \mprj_pads.analog_en[21]  = \mprj_io_analog_en[21] ;
+  assign \mprj_pads.analog_en[20]  = \mprj_io_analog_en[20] ;
+  assign \mprj_pads.analog_en[19]  = \mprj_io_analog_en[19] ;
+  assign \mprj_pads.analog_en[18]  = \mprj_io_analog_en[18] ;
+  assign \mprj_pads.analog_en[17]  = \mprj_io_analog_en[17] ;
+  assign \mprj_pads.analog_en[16]  = \mprj_io_analog_en[16] ;
+  assign \mprj_pads.analog_en[15]  = \mprj_io_analog_en[15] ;
+  assign \mprj_pads.analog_en[14]  = \mprj_io_analog_en[14] ;
+  assign \mprj_pads.analog_en[13]  = \mprj_io_analog_en[13] ;
+  assign \mprj_pads.analog_en[12]  = \mprj_io_analog_en[12] ;
+  assign \mprj_pads.analog_en[11]  = \mprj_io_analog_en[11] ;
+  assign \mprj_pads.analog_en[10]  = \mprj_io_analog_en[10] ;
+  assign \mprj_pads.analog_en[9]  = \mprj_io_analog_en[9] ;
+  assign \mprj_pads.analog_en[8]  = \mprj_io_analog_en[8] ;
+  assign \mprj_pads.analog_en[7]  = \mprj_io_analog_en[7] ;
+  assign \mprj_pads.analog_en[6]  = \mprj_io_analog_en[6] ;
+  assign \mprj_pads.analog_en[5]  = \mprj_io_analog_en[5] ;
+  assign \mprj_pads.analog_en[4]  = \mprj_io_analog_en[4] ;
+  assign \mprj_pads.analog_en[3]  = \mprj_io_analog_en[3] ;
+  assign \mprj_pads.analog_en[2]  = \mprj_io_analog_en[2] ;
+  assign \mprj_pads.analog_en[1]  = \mprj_io_analog_en[1] ;
+  assign \mprj_pads.analog_en[0]  = \mprj_io_analog_en[0] ;
+  assign \mprj_pads.dm[113]  = \mprj_io_dm[113] ;
+  assign \mprj_pads.dm[112]  = \mprj_io_dm[112] ;
+  assign \mprj_pads.dm[111]  = \mprj_io_dm[111] ;
+  assign \mprj_pads.dm[110]  = \mprj_io_dm[110] ;
+  assign \mprj_pads.dm[109]  = \mprj_io_dm[109] ;
+  assign \mprj_pads.dm[108]  = \mprj_io_dm[108] ;
+  assign \mprj_pads.dm[107]  = \mprj_io_dm[107] ;
+  assign \mprj_pads.dm[106]  = \mprj_io_dm[106] ;
+  assign \mprj_pads.dm[105]  = \mprj_io_dm[105] ;
+  assign \mprj_pads.dm[104]  = \mprj_io_dm[104] ;
+  assign \mprj_pads.dm[103]  = \mprj_io_dm[103] ;
+  assign \mprj_pads.dm[102]  = \mprj_io_dm[102] ;
+  assign \mprj_pads.dm[101]  = \mprj_io_dm[101] ;
+  assign \mprj_pads.dm[100]  = \mprj_io_dm[100] ;
+  assign \mprj_pads.dm[99]  = \mprj_io_dm[99] ;
+  assign \mprj_pads.dm[98]  = \mprj_io_dm[98] ;
+  assign \mprj_pads.dm[97]  = \mprj_io_dm[97] ;
+  assign \mprj_pads.dm[96]  = \mprj_io_dm[96] ;
+  assign \mprj_pads.dm[95]  = \mprj_io_dm[95] ;
+  assign \mprj_pads.dm[94]  = \mprj_io_dm[94] ;
+  assign \mprj_pads.dm[93]  = \mprj_io_dm[93] ;
+  assign \mprj_pads.dm[92]  = \mprj_io_dm[92] ;
+  assign \mprj_pads.dm[91]  = \mprj_io_dm[91] ;
+  assign \mprj_pads.dm[90]  = \mprj_io_dm[90] ;
+  assign \mprj_pads.dm[89]  = \mprj_io_dm[89] ;
+  assign \mprj_pads.dm[88]  = \mprj_io_dm[88] ;
+  assign \mprj_pads.dm[87]  = \mprj_io_dm[87] ;
+  assign \mprj_pads.dm[86]  = \mprj_io_dm[86] ;
+  assign \mprj_pads.dm[85]  = \mprj_io_dm[85] ;
+  assign \mprj_pads.dm[84]  = \mprj_io_dm[84] ;
+  assign \mprj_pads.dm[83]  = \mprj_io_dm[83] ;
+  assign \mprj_pads.dm[82]  = \mprj_io_dm[82] ;
+  assign \mprj_pads.dm[81]  = \mprj_io_dm[81] ;
+  assign \mprj_pads.dm[80]  = \mprj_io_dm[80] ;
+  assign \mprj_pads.dm[79]  = \mprj_io_dm[79] ;
+  assign \mprj_pads.dm[78]  = \mprj_io_dm[78] ;
+  assign \mprj_pads.dm[77]  = \mprj_io_dm[77] ;
+  assign \mprj_pads.dm[76]  = \mprj_io_dm[76] ;
+  assign \mprj_pads.dm[75]  = \mprj_io_dm[75] ;
+  assign \mprj_pads.dm[74]  = \mprj_io_dm[74] ;
+  assign \mprj_pads.dm[73]  = \mprj_io_dm[73] ;
+  assign \mprj_pads.dm[72]  = \mprj_io_dm[72] ;
+  assign \mprj_pads.dm[71]  = \mprj_io_dm[71] ;
+  assign \mprj_pads.dm[70]  = \mprj_io_dm[70] ;
+  assign \mprj_pads.dm[69]  = \mprj_io_dm[69] ;
+  assign \mprj_pads.dm[68]  = \mprj_io_dm[68] ;
+  assign \mprj_pads.dm[67]  = \mprj_io_dm[67] ;
+  assign \mprj_pads.dm[66]  = \mprj_io_dm[66] ;
+  assign \mprj_pads.dm[65]  = \mprj_io_dm[65] ;
+  assign \mprj_pads.dm[64]  = \mprj_io_dm[64] ;
+  assign \mprj_pads.dm[63]  = \mprj_io_dm[63] ;
+  assign \mprj_pads.dm[62]  = \mprj_io_dm[62] ;
+  assign \mprj_pads.dm[61]  = \mprj_io_dm[61] ;
+  assign \mprj_pads.dm[60]  = \mprj_io_dm[60] ;
+  assign \mprj_pads.dm[59]  = \mprj_io_dm[59] ;
+  assign \mprj_pads.dm[58]  = \mprj_io_dm[58] ;
+  assign \mprj_pads.dm[57]  = \mprj_io_dm[57] ;
+  assign \mprj_pads.dm[56]  = \mprj_io_dm[56] ;
+  assign \mprj_pads.dm[55]  = \mprj_io_dm[55] ;
+  assign \mprj_pads.dm[54]  = \mprj_io_dm[54] ;
+  assign \mprj_pads.dm[53]  = \mprj_io_dm[53] ;
+  assign \mprj_pads.dm[52]  = \mprj_io_dm[52] ;
+  assign \mprj_pads.dm[51]  = \mprj_io_dm[51] ;
+  assign \mprj_pads.dm[50]  = \mprj_io_dm[50] ;
+  assign \mprj_pads.dm[49]  = \mprj_io_dm[49] ;
+  assign \mprj_pads.dm[48]  = \mprj_io_dm[48] ;
+  assign \mprj_pads.dm[47]  = \mprj_io_dm[47] ;
+  assign \mprj_pads.dm[46]  = \mprj_io_dm[46] ;
+  assign \mprj_pads.dm[45]  = \mprj_io_dm[45] ;
+  assign \mprj_pads.dm[44]  = \mprj_io_dm[44] ;
+  assign \mprj_pads.dm[43]  = \mprj_io_dm[43] ;
+  assign \mprj_pads.dm[42]  = \mprj_io_dm[42] ;
+  assign \mprj_pads.dm[41]  = \mprj_io_dm[41] ;
+  assign \mprj_pads.dm[40]  = \mprj_io_dm[40] ;
+  assign \mprj_pads.dm[39]  = \mprj_io_dm[39] ;
+  assign \mprj_pads.dm[38]  = \mprj_io_dm[38] ;
+  assign \mprj_pads.dm[37]  = \mprj_io_dm[37] ;
+  assign \mprj_pads.dm[36]  = \mprj_io_dm[36] ;
+  assign \mprj_pads.dm[35]  = \mprj_io_dm[35] ;
+  assign \mprj_pads.dm[34]  = \mprj_io_dm[34] ;
+  assign \mprj_pads.dm[33]  = \mprj_io_dm[33] ;
+  assign \mprj_pads.dm[32]  = \mprj_io_dm[32] ;
+  assign \mprj_pads.dm[31]  = \mprj_io_dm[31] ;
+  assign \mprj_pads.dm[30]  = \mprj_io_dm[30] ;
+  assign \mprj_pads.dm[29]  = \mprj_io_dm[29] ;
+  assign \mprj_pads.dm[28]  = \mprj_io_dm[28] ;
+  assign \mprj_pads.dm[27]  = \mprj_io_dm[27] ;
+  assign \mprj_pads.dm[26]  = \mprj_io_dm[26] ;
+  assign \mprj_pads.dm[25]  = \mprj_io_dm[25] ;
+  assign \mprj_pads.dm[24]  = \mprj_io_dm[24] ;
+  assign \mprj_pads.dm[23]  = \mprj_io_dm[23] ;
+  assign \mprj_pads.dm[22]  = \mprj_io_dm[22] ;
+  assign \mprj_pads.dm[21]  = \mprj_io_dm[21] ;
+  assign \mprj_pads.dm[20]  = \mprj_io_dm[20] ;
+  assign \mprj_pads.dm[19]  = \mprj_io_dm[19] ;
+  assign \mprj_pads.dm[18]  = \mprj_io_dm[18] ;
+  assign \mprj_pads.dm[17]  = \mprj_io_dm[17] ;
+  assign \mprj_pads.dm[16]  = \mprj_io_dm[16] ;
+  assign \mprj_pads.dm[15]  = \mprj_io_dm[15] ;
+  assign \mprj_pads.dm[14]  = \mprj_io_dm[14] ;
+  assign \mprj_pads.dm[13]  = \mprj_io_dm[13] ;
+  assign \mprj_pads.dm[12]  = \mprj_io_dm[12] ;
+  assign \mprj_pads.dm[11]  = \mprj_io_dm[11] ;
+  assign \mprj_pads.dm[10]  = \mprj_io_dm[10] ;
+  assign \mprj_pads.dm[9]  = \mprj_io_dm[9] ;
+  assign \mprj_pads.dm[8]  = \mprj_io_dm[8] ;
+  assign \mprj_pads.dm[7]  = \mprj_io_dm[7] ;
+  assign \mprj_pads.dm[6]  = \mprj_io_dm[6] ;
+  assign \mprj_pads.dm[5]  = \mprj_io_dm[5] ;
+  assign \mprj_pads.dm[4]  = \mprj_io_dm[4] ;
+  assign \mprj_pads.dm[3]  = \mprj_io_dm[3] ;
+  assign \mprj_pads.dm[2]  = \mprj_io_dm[2] ;
+  assign \mprj_pads.dm[1]  = \mprj_io_dm[1] ;
+  assign \mprj_pads.dm[0]  = \mprj_io_dm[0] ;
+  assign \mprj_pads.inp_dis[37]  = \mprj_io_inp_dis[37] ;
+  assign \mprj_pads.inp_dis[36]  = \mprj_io_inp_dis[36] ;
+  assign \mprj_pads.inp_dis[35]  = \mprj_io_inp_dis[35] ;
+  assign \mprj_pads.inp_dis[34]  = \mprj_io_inp_dis[34] ;
+  assign \mprj_pads.inp_dis[33]  = \mprj_io_inp_dis[33] ;
+  assign \mprj_pads.inp_dis[32]  = \mprj_io_inp_dis[32] ;
+  assign \mprj_pads.inp_dis[31]  = \mprj_io_inp_dis[31] ;
+  assign \mprj_pads.inp_dis[30]  = \mprj_io_inp_dis[30] ;
+  assign \mprj_pads.inp_dis[29]  = \mprj_io_inp_dis[29] ;
+  assign \mprj_pads.inp_dis[28]  = \mprj_io_inp_dis[28] ;
+  assign \mprj_pads.inp_dis[27]  = \mprj_io_inp_dis[27] ;
+  assign \mprj_pads.inp_dis[26]  = \mprj_io_inp_dis[26] ;
+  assign \mprj_pads.inp_dis[25]  = \mprj_io_inp_dis[25] ;
+  assign \mprj_pads.inp_dis[24]  = \mprj_io_inp_dis[24] ;
+  assign \mprj_pads.inp_dis[23]  = \mprj_io_inp_dis[23] ;
+  assign \mprj_pads.inp_dis[22]  = \mprj_io_inp_dis[22] ;
+  assign \mprj_pads.inp_dis[21]  = \mprj_io_inp_dis[21] ;
+  assign \mprj_pads.inp_dis[20]  = \mprj_io_inp_dis[20] ;
+  assign \mprj_pads.inp_dis[19]  = \mprj_io_inp_dis[19] ;
+  assign \mprj_pads.inp_dis[18]  = \mprj_io_inp_dis[18] ;
+  assign \mprj_pads.inp_dis[17]  = \mprj_io_inp_dis[17] ;
+  assign \mprj_pads.inp_dis[16]  = \mprj_io_inp_dis[16] ;
+  assign \mprj_pads.inp_dis[15]  = \mprj_io_inp_dis[15] ;
+  assign \mprj_pads.inp_dis[14]  = \mprj_io_inp_dis[14] ;
+  assign \mprj_pads.inp_dis[13]  = \mprj_io_inp_dis[13] ;
+  assign \mprj_pads.inp_dis[12]  = \mprj_io_inp_dis[12] ;
+  assign \mprj_pads.inp_dis[11]  = \mprj_io_inp_dis[11] ;
+  assign \mprj_pads.inp_dis[10]  = \mprj_io_inp_dis[10] ;
+  assign \mprj_pads.inp_dis[9]  = \mprj_io_inp_dis[9] ;
+  assign \mprj_pads.inp_dis[8]  = \mprj_io_inp_dis[8] ;
+  assign \mprj_pads.inp_dis[7]  = \mprj_io_inp_dis[7] ;
+  assign \mprj_pads.inp_dis[6]  = \mprj_io_inp_dis[6] ;
+  assign \mprj_pads.inp_dis[5]  = \mprj_io_inp_dis[5] ;
+  assign \mprj_pads.inp_dis[4]  = \mprj_io_inp_dis[4] ;
+  assign \mprj_pads.inp_dis[3]  = \mprj_io_inp_dis[3] ;
+  assign \mprj_pads.inp_dis[2]  = \mprj_io_inp_dis[2] ;
+  assign \mprj_pads.inp_dis[1]  = \mprj_io_inp_dis[1] ;
+  assign \mprj_pads.inp_dis[0]  = \mprj_io_inp_dis[0] ;
+  assign \mprj_pads.io_out[37]  = \mprj_io_out[37] ;
+  assign \mprj_pads.io_out[36]  = \mprj_io_out[36] ;
+  assign \mprj_pads.io_out[35]  = \mprj_io_out[35] ;
+  assign \mprj_pads.io_out[34]  = \mprj_io_out[34] ;
+  assign \mprj_pads.io_out[33]  = \mprj_io_out[33] ;
+  assign \mprj_pads.io_out[32]  = \mprj_io_out[32] ;
+  assign \mprj_pads.io_out[31]  = \mprj_io_out[31] ;
+  assign \mprj_pads.io_out[30]  = \mprj_io_out[30] ;
+  assign \mprj_pads.io_out[29]  = \mprj_io_out[29] ;
+  assign \mprj_pads.io_out[28]  = \mprj_io_out[28] ;
+  assign \mprj_pads.io_out[27]  = \mprj_io_out[27] ;
+  assign \mprj_pads.io_out[26]  = \mprj_io_out[26] ;
+  assign \mprj_pads.io_out[25]  = \mprj_io_out[25] ;
+  assign \mprj_pads.io_out[24]  = \mprj_io_out[24] ;
+  assign \mprj_pads.io_out[23]  = \mprj_io_out[23] ;
+  assign \mprj_pads.io_out[22]  = \mprj_io_out[22] ;
+  assign \mprj_pads.io_out[21]  = \mprj_io_out[21] ;
+  assign \mprj_pads.io_out[20]  = \mprj_io_out[20] ;
+  assign \mprj_pads.io_out[19]  = \mprj_io_out[19] ;
+  assign \mprj_pads.io_out[18]  = \mprj_io_out[18] ;
+  assign \mprj_pads.io_out[17]  = \mprj_io_out[17] ;
+  assign \mprj_pads.io_out[16]  = \mprj_io_out[16] ;
+  assign \mprj_pads.io_out[15]  = \mprj_io_out[15] ;
+  assign \mprj_pads.io_out[14]  = \mprj_io_out[14] ;
+  assign \mprj_pads.io_out[13]  = \mprj_io_out[13] ;
+  assign \mprj_pads.io_out[12]  = \mprj_io_out[12] ;
+  assign \mprj_pads.io_out[11]  = \mprj_io_out[11] ;
+  assign \mprj_pads.io_out[10]  = \mprj_io_out[10] ;
+  assign \mprj_pads.io_out[9]  = \mprj_io_out[9] ;
+  assign \mprj_pads.io_out[8]  = \mprj_io_out[8] ;
+  assign \mprj_pads.io_out[7]  = \mprj_io_out[7] ;
+  assign \mprj_pads.io_out[6]  = \mprj_io_out[6] ;
+  assign \mprj_pads.io_out[5]  = \mprj_io_out[5] ;
+  assign \mprj_pads.io_out[4]  = \mprj_io_out[4] ;
+  assign \mprj_pads.io_out[3]  = \mprj_io_out[3] ;
+  assign \mprj_pads.io_out[2]  = \mprj_io_out[2] ;
+  assign \mprj_pads.io_out[1]  = \mprj_io_out[1] ;
+  assign \mprj_pads.io_out[0]  = \mprj_io_out[0] ;
+  assign \mprj_pads.holdover[37]  = \mprj_io_holdover[37] ;
+  assign \mprj_pads.holdover[36]  = \mprj_io_holdover[36] ;
+  assign \mprj_pads.holdover[35]  = \mprj_io_holdover[35] ;
+  assign \mprj_pads.holdover[34]  = \mprj_io_holdover[34] ;
+  assign \mprj_pads.holdover[33]  = \mprj_io_holdover[33] ;
+  assign \mprj_pads.holdover[32]  = \mprj_io_holdover[32] ;
+  assign \mprj_pads.holdover[31]  = \mprj_io_holdover[31] ;
+  assign \mprj_pads.holdover[30]  = \mprj_io_holdover[30] ;
+  assign \mprj_pads.holdover[29]  = \mprj_io_holdover[29] ;
+  assign \mprj_pads.holdover[28]  = \mprj_io_holdover[28] ;
+  assign \mprj_pads.holdover[27]  = \mprj_io_holdover[27] ;
+  assign \mprj_pads.holdover[26]  = \mprj_io_holdover[26] ;
+  assign \mprj_pads.holdover[25]  = \mprj_io_holdover[25] ;
+  assign \mprj_pads.holdover[24]  = \mprj_io_holdover[24] ;
+  assign \mprj_pads.holdover[23]  = \mprj_io_holdover[23] ;
+  assign \mprj_pads.holdover[22]  = \mprj_io_holdover[22] ;
+  assign \mprj_pads.holdover[21]  = \mprj_io_holdover[21] ;
+  assign \mprj_pads.holdover[20]  = \mprj_io_holdover[20] ;
+  assign \mprj_pads.holdover[19]  = \mprj_io_holdover[19] ;
+  assign \mprj_pads.holdover[18]  = \mprj_io_holdover[18] ;
+  assign \mprj_pads.holdover[17]  = \mprj_io_holdover[17] ;
+  assign \mprj_pads.holdover[16]  = \mprj_io_holdover[16] ;
+  assign \mprj_pads.holdover[15]  = \mprj_io_holdover[15] ;
+  assign \mprj_pads.holdover[14]  = \mprj_io_holdover[14] ;
+  assign \mprj_pads.holdover[13]  = \mprj_io_holdover[13] ;
+  assign \mprj_pads.holdover[12]  = \mprj_io_holdover[12] ;
+  assign \mprj_pads.holdover[11]  = \mprj_io_holdover[11] ;
+  assign \mprj_pads.holdover[10]  = \mprj_io_holdover[10] ;
+  assign \mprj_pads.holdover[9]  = \mprj_io_holdover[9] ;
+  assign \mprj_pads.holdover[8]  = \mprj_io_holdover[8] ;
+  assign \mprj_pads.holdover[7]  = \mprj_io_holdover[7] ;
+  assign \mprj_pads.holdover[6]  = \mprj_io_holdover[6] ;
+  assign \mprj_pads.holdover[5]  = \mprj_io_holdover[5] ;
+  assign \mprj_pads.holdover[4]  = \mprj_io_holdover[4] ;
+  assign \mprj_pads.holdover[3]  = \mprj_io_holdover[3] ;
+  assign \mprj_pads.holdover[2]  = \mprj_io_holdover[2] ;
+  assign \mprj_pads.holdover[1]  = \mprj_io_holdover[1] ;
+  assign \mprj_pads.holdover[0]  = \mprj_io_holdover[0] ;
+  assign \mprj_pads.ib_mode_sel[37]  = \mprj_io_ib_mode_sel[37] ;
+  assign \mprj_pads.ib_mode_sel[36]  = \mprj_io_ib_mode_sel[36] ;
+  assign \mprj_pads.ib_mode_sel[35]  = \mprj_io_ib_mode_sel[35] ;
+  assign \mprj_pads.ib_mode_sel[34]  = \mprj_io_ib_mode_sel[34] ;
+  assign \mprj_pads.ib_mode_sel[33]  = \mprj_io_ib_mode_sel[33] ;
+  assign \mprj_pads.ib_mode_sel[32]  = \mprj_io_ib_mode_sel[32] ;
+  assign \mprj_pads.ib_mode_sel[31]  = \mprj_io_ib_mode_sel[31] ;
+  assign \mprj_pads.ib_mode_sel[30]  = \mprj_io_ib_mode_sel[30] ;
+  assign \mprj_pads.ib_mode_sel[29]  = \mprj_io_ib_mode_sel[29] ;
+  assign \mprj_pads.ib_mode_sel[28]  = \mprj_io_ib_mode_sel[28] ;
+  assign \mprj_pads.ib_mode_sel[27]  = \mprj_io_ib_mode_sel[27] ;
+  assign \mprj_pads.ib_mode_sel[26]  = \mprj_io_ib_mode_sel[26] ;
+  assign \mprj_pads.ib_mode_sel[25]  = \mprj_io_ib_mode_sel[25] ;
+  assign \mprj_pads.ib_mode_sel[24]  = \mprj_io_ib_mode_sel[24] ;
+  assign \mprj_pads.ib_mode_sel[23]  = \mprj_io_ib_mode_sel[23] ;
+  assign \mprj_pads.ib_mode_sel[22]  = \mprj_io_ib_mode_sel[22] ;
+  assign \mprj_pads.ib_mode_sel[21]  = \mprj_io_ib_mode_sel[21] ;
+  assign \mprj_pads.ib_mode_sel[20]  = \mprj_io_ib_mode_sel[20] ;
+  assign \mprj_pads.ib_mode_sel[19]  = \mprj_io_ib_mode_sel[19] ;
+  assign \mprj_pads.ib_mode_sel[18]  = \mprj_io_ib_mode_sel[18] ;
+  assign \mprj_pads.ib_mode_sel[17]  = \mprj_io_ib_mode_sel[17] ;
+  assign \mprj_pads.ib_mode_sel[16]  = \mprj_io_ib_mode_sel[16] ;
+  assign \mprj_pads.ib_mode_sel[15]  = \mprj_io_ib_mode_sel[15] ;
+  assign \mprj_pads.ib_mode_sel[14]  = \mprj_io_ib_mode_sel[14] ;
+  assign \mprj_pads.ib_mode_sel[13]  = \mprj_io_ib_mode_sel[13] ;
+  assign \mprj_pads.ib_mode_sel[12]  = \mprj_io_ib_mode_sel[12] ;
+  assign \mprj_pads.ib_mode_sel[11]  = \mprj_io_ib_mode_sel[11] ;
+  assign \mprj_pads.ib_mode_sel[10]  = \mprj_io_ib_mode_sel[10] ;
+  assign \mprj_pads.ib_mode_sel[9]  = \mprj_io_ib_mode_sel[9] ;
+  assign \mprj_pads.ib_mode_sel[8]  = \mprj_io_ib_mode_sel[8] ;
+  assign \mprj_pads.ib_mode_sel[7]  = \mprj_io_ib_mode_sel[7] ;
+  assign \mprj_pads.ib_mode_sel[6]  = \mprj_io_ib_mode_sel[6] ;
+  assign \mprj_pads.ib_mode_sel[5]  = \mprj_io_ib_mode_sel[5] ;
+  assign \mprj_pads.ib_mode_sel[4]  = \mprj_io_ib_mode_sel[4] ;
+  assign \mprj_pads.ib_mode_sel[3]  = \mprj_io_ib_mode_sel[3] ;
+  assign \mprj_pads.ib_mode_sel[2]  = \mprj_io_ib_mode_sel[2] ;
+  assign \mprj_pads.ib_mode_sel[1]  = \mprj_io_ib_mode_sel[1] ;
+  assign \mprj_pads.ib_mode_sel[0]  = \mprj_io_ib_mode_sel[0] ;
+  assign \mprj_pads.vddio  = vddio;
+  assign \mprj_pads.vssio  = vssio;
+  assign \mprj_pads.vccd  = vccd;
+  assign \mprj_pads.vssd  = vssd;
+  assign \mprj_pads.vdda1  = vdda1;
+  assign \mprj_pads.vdda2  = vdda2;
+  assign \mprj_pads.vssa1  = vssa1;
+  assign \mprj_pads.vssa2  = vssa2;
+  assign \mprj_pads.vccd1  = vccd1;
+  assign \mprj_pads.vccd2  = vccd2;
+  assign \mprj_pads.vssd1  = vssd1;
+  assign \mprj_pads.vssd2  = vssd2;
+  assign \mprj_pads.porb_h  = porb_h;
+  assign \mprj_pads.slow_sel[36]  = \mprj_io_slow_sel[36] ;
+  assign \mprj_pads.slow_sel[23]  = \mprj_io_slow_sel[23] ;
+  assign \mprj_pads.slow_sel[28]  = \mprj_io_slow_sel[28] ;
+  assign \mprj_pads.slow_sel[37]  = \mprj_io_slow_sel[37] ;
+  assign \flash_io0_mode[0]  = flash_io0_oeb_core;
+  assign \mprj_pads.slow_sel[24]  = \mprj_io_slow_sel[24] ;
+  assign \mprj_pads.slow_sel[21]  = \mprj_io_slow_sel[21] ;
+  assign \mprj_pads.slow_sel[31]  = \mprj_io_slow_sel[31] ;
+  assign \flash_io0_mode[1]  = flash_io0_ieb_core;
+  assign \mprj_pads.slow_sel[22]  = \mprj_io_slow_sel[22] ;
+  assign \mprj_pads.slow_sel[27]  = \mprj_io_slow_sel[27] ;
+  assign \mprj_pads.slow_sel[32]  = \mprj_io_slow_sel[32] ;
+  assign \mprj_pads.slow_sel[30]  = \mprj_io_slow_sel[30] ;
+  assign \mprj_pads.slow_sel[26]  = \mprj_io_slow_sel[26] ;
+  assign \mprj_pads.slow_sel[29]  = \mprj_io_slow_sel[29] ;
+  assign \mprj_pads.slow_sel[35]  = \mprj_io_slow_sel[35] ;
+  assign \mprj_pads.slow_sel[25]  = \mprj_io_slow_sel[25] ;
+  assign \mprj_pads.slow_sel[20]  = \mprj_io_slow_sel[20] ;
+  assign \mprj_pads.slow_sel[34]  = \mprj_io_slow_sel[34] ;
+  assign \flash_io0_mode[2]  = flash_io0_ieb_core;
+  assign \mprj_pads.slow_sel[33]  = \mprj_io_slow_sel[33] ;
+  assign vssio_q = \mprj_pads.vssio_q ;
+  assign vddio_q = \mprj_pads.vddio_q ;
+  assign analog_b = \mprj_pads.analog_b ;
+  assign analog_a = \mprj_pads.analog_a ;
+  assign { \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0]  } =
+                  { \mprj_pads.io_in[37] , \mprj_pads.io_in[36] , \mprj_pads.io_in[35] , \mprj_pads.io_in[34] , \mprj_pads.io_in[33] , \mprj_pads.io_in[32] , \mprj_pads.io_in[31] , \mprj_pads.io_in[30] , \mprj_pads.io_in[29] , \mprj_pads.io_in[28] , \mprj_pads.io_in[27] , \mprj_pads.io_in[26] , \mprj_pads.io_in[25] , \mprj_pads.io_in[24] , \mprj_pads.io_in[23] , \mprj_pads.io_in[22] , \mprj_pads.io_in[21] , \mprj_pads.io_in[20] , \mprj_pads.io_in[19] , \mprj_pads.io_in[18] , \mprj_pads.io_in[17] , \mprj_pads.io_in[16] , \mprj_pads.io_in[15] , \mprj_pads.io_in[14] , \mprj_pads.io_in[13] , \mprj_pads.io_in[12] , \mprj_pads.io_in[11] , \mprj_pads.io_in[10] , \mprj_pads.io_in[9] , \mprj_pads.io_in[8] , \mprj_pads.io_in[7] , \mprj_pads.io_in[6] , \mprj_pads.io_in[5] , \mprj_pads.io_in[4] , \mprj_pads.io_in[3] , \mprj_pads.io_in[2] , \mprj_pads.io_in[1] , \mprj_pads.io_in[0]  };
+endmodule

diff --git a/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
new file mode 100644
index 0000000..400c5ab
--- /dev/null
+++ b/verilog/dv/wb_utests/chip_io/chip_io_tb.v

@@ -0,0 +1,377 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
+
+`include "defines.v"
+
+`ifdef GL
+    `include "gl/chip_io.v"
+`else
+    `ifdef SPLIT_BUS
+        `include "ports.v"
+        `include "chip_io_split.v"
+    `else
+        `include "pads.v"
+        `include "mprj_io.v"
+        `include "chip_io.v"
+    `endif
+`endif 
+
+module chip_io_tb;
+    
+    wire clock_core;
+    reg clock;
+
+    wire rstb_h;
+    reg RSTB;
+    
+    reg porb_h;
+    wire por_l;
+
+    wire gpio;
+    reg gpio_out_core;
+    reg gpio_inenb_core;
+    reg gpio_outenb_core;
+
+    wire flash_csb;
+    reg flash_csb_core;
+    reg flash_csb_ieb_core;        
+    reg flash_csb_oeb_core; 
+    
+    wire flash_clk;
+    reg flash_clk_core;
+    reg flash_clk_ieb_core;       
+    reg flash_clk_oeb_core; 
+
+    wire flash_io0;
+    wire flash_io0_di_core;
+    reg flash_io0_do_core;
+    reg flash_io0_ieb_core;
+    reg flash_io0_oeb_core;
+
+    wire flash_io1;
+    wire flash_io1_di_core;
+    reg flash_io1_do_core;
+    reg flash_io1_ieb_core;
+    reg flash_io1_oeb_core;
+    
+    wire gpio_in_core;
+    wire gpio_mode0_core;
+    wire gpio_mode1_core;
+
+    wire [`MPRJ_IO_PADS-1:0] mprj_io;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    reg [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_out;
+    
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+    wire [`MPRJ_IO_PADS-10:0] mprj_analog_io;
+
+    always #12.5 clock <= (clock === 1'b0);
+
+    initial begin
+        clock  = 0;
+        porb_h = 0;
+        flash_csb_core = 0;
+        flash_csb_ieb_core = 1;
+        flash_csb_oeb_core = 0;
+        flash_clk_ieb_core = 1;
+        flash_clk_oeb_core = 0;
+        mprj_io_ib_mode_sel = {38{1'b0}};
+        mprj_io_vtrip_sel = {38{1'b0}};
+        mprj_io_slow_sel  = {38{1'b0}};
+        mprj_io_holdover  = {38{1'b0}};
+        mprj_io_analog_en  = {38{1'b0}};
+        mprj_io_analog_sel = {38{1'b0}};
+        mprj_io_analog_pol = {38{1'b0}};
+    end
+
+    wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+	
+    reg power1, power2;
+
+    initial begin
+		RSTB   <= 1'b0;
+        porb_h <= 1'b0;
+        #500;
+        porb_h <= 1'b1;
+		#500;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    initial begin
+        $dumpfile("chip_io.vcd");
+        $dumpvars(0, chip_io_tb);
+        #(`SIM_TIME);
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Management Protect Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [2:0] dm_all;
+    reg gpio_bit;
+    
+    assign gpio = gpio_bit;
+    assign gpio_mode0_core = dm_all[0];
+    assign gpio_mode1_core = dm_all[1];
+
+    reg flash_io0_bit;
+    reg flash_io1_bit;
+
+    assign flash_io0 = flash_io0_bit;
+    assign flash_io1 = flash_io1_bit;
+
+    reg [`MPRJ_IO_PADS-1:0] mprj_io_bits;
+
+    assign mprj_io = mprj_io_bits;
+
+    initial begin
+        wait(RSTB == 1'b1);        // wait for reset 
+        #25;
+        // Clock & Reset Pads 
+        if (clock !== clock_core) begin
+            $display("Error: Clock Pad Test Failed."); $finish; 
+        end
+        if (RSTB !== rstb_h) begin
+            $display("Error: Reset Pad Test Failed."); $finish; 
+        end
+        
+        // Management GPIO Pad
+        gpio_bit = 1'b1;
+        gpio_out_core = 1'b0;  
+        gpio_inenb_core = 1'b0;
+        gpio_outenb_core = 1'b1;
+        dm_all = 3'b001;            // input-only
+        #25;
+        if (gpio_in_core !== gpio) begin
+            $display("Error: GPIO Pad Input Test Failed."); $finish;
+        end
+
+        gpio_bit = 1'bz;
+        gpio_out_core    = 1'b1;   
+        gpio_inenb_core  = 1'b1;
+        gpio_outenb_core = 1'b0;
+        dm_all = 3'b110;            // output-only
+        #25;
+        if (gpio_out_core !== gpio) begin
+            $display("Error: GPIO Pad Output Test Failed."); $finish;
+        end
+
+        // Flash Output Pads
+        flash_csb_core = 1'b1;        // CSB Pad
+        #25;
+        if (flash_csb !== flash_csb_core) begin
+            $display("Error: Flash CSB Pad Test Failed."); $finish;
+        end
+
+        flash_clk_core = 1'b1;         // CLK Pad
+        #25;
+        if (flash_clk !== flash_clk_core) begin
+            $display("Error: Flash CLK Pad Test Failed."); $finish;
+        end
+
+        // Flash Inout Pads
+        flash_io0_bit = 1'b1;            
+        flash_io0_ieb_core = 1'b0;     // Input
+        flash_io0_oeb_core = 1'b1;
+        #25;
+        if (flash_io0_di_core !== flash_io0_bit) begin
+            $display("Error: Flash io0 Pad Input Test Failed."); $finish;
+        end
+
+        flash_io0_bit = 1'bz;   
+        flash_io0_do_core = 1'b1;       
+        flash_io0_ieb_core = 1'b1;     
+        flash_io0_oeb_core = 1'b0;    // Output
+        #25
+        if (flash_io0 !== flash_io0_do_core) begin
+            $display("Error: Flash io0 Pad Output Test Failed."); $finish;
+        end
+
+        // User Project Pads - All Outputs
+        mprj_io_bits = {38{1'bz}};
+        mprj_io_out = {6'b10101, 32'hF0F0};
+        mprj_io_oeb = {38{1'b0}};
+        mprj_io_inp_dis = {38{1'b1}};
+        mprj_io_dm = {38*3{3'b110}};
+
+        #25;
+        if (mprj_io !== mprj_io_out) begin
+            $display("Error: User Project Pads Output Test Failed."); $finish;
+        end
+        
+        // User Project Pads - All Inputs
+        mprj_io_bits = {6'b01010, 32'hFF0F};
+        mprj_io_out  = {38{1'b0}};
+        mprj_io_oeb  = {38{1'b1}};
+        mprj_io_inp_dis = {38{1'b0}};
+        mprj_io_dm = {38*3{3'b001}};
+
+        #25;
+        if (mprj_io_in !== mprj_io_bits) begin
+            $display("Error: User Project Pads Input Test Failed."); $finish;
+        end
+        
+        // User Project Pads - All Bidirectional
+        mprj_io_bits = {6'b01010, 32'hF00F};  // drive input signal
+        mprj_io_out  = {38{1'bz}}; 
+        mprj_io_oeb  = {38{1'b1}};
+        mprj_io_inp_dis = {38{1'b0}};
+        mprj_io_dm = {38{3'b110}};
+
+        #25;
+        if (mprj_io_in !== mprj_io_bits) begin
+            $display("Error: User Project Pads Bidirectional Test Failed."); $finish;
+        end
+        
+        mprj_io_bits = {38{1'bz}};  
+        mprj_io_out  = {6'b01110, 32'h0FF0};  // drive output signal
+        mprj_io_oeb  = {38{1'b0}};
+        mprj_io_inp_dis = {38{1'b0}};
+        mprj_io_dm = {38{3'b110}};
+
+        #25;
+        if (mprj_io !== mprj_io_out) begin
+            $display("Error: User Project Pads Output Test Failed."); $finish;
+        end
+        $display("Success");
+        $display("Monitor: Chip IO Test Passed.");
+        #2000;
+        $finish;
+    end
+
+    assign por_l = ~porb_h;
+
+    chip_io uut (
+        // Package Pins
+        .vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+
+        .gpio(gpio),
+        .clock(clock),
+        .resetb(RSTB),
+        .flash_csb(flash_csb),
+        .flash_clk(flash_clk),
+        .flash_io0(flash_io0),
+        .flash_io1(flash_io1),
+        // SoC Core Interface
+        .porb_h(porb_h),
+        .por(por_l),
+        .resetb_core_h(rstb_h),
+        .clock_core(clock_core),
+        .gpio_out_core(gpio_out_core),
+        .gpio_in_core(gpio_in_core),
+        .gpio_mode0_core(gpio_mode0_core),
+        .gpio_mode1_core(gpio_mode1_core),
+        .gpio_outenb_core(gpio_outenb_core),
+        .gpio_inenb_core(gpio_inenb_core),
+        .flash_csb_core(flash_csb_core),
+        .flash_clk_core(flash_clk_core),
+        .flash_csb_oeb_core(flash_csb_oeb_core),
+        .flash_clk_oeb_core(flash_clk_oeb_core),
+        .flash_io0_oeb_core(flash_io0_oeb_core),
+        .flash_io1_oeb_core(flash_io1_oeb_core),
+        .flash_csb_ieb_core(flash_csb_ieb_core),
+        .flash_clk_ieb_core(flash_clk_ieb_core),
+        .flash_io0_ieb_core(flash_io0_ieb_core),
+        .flash_io1_ieb_core(flash_io1_ieb_core),
+        .flash_io0_do_core(flash_io0_do_core),
+        .flash_io1_do_core(flash_io1_do_core),
+        .flash_io0_di_core(flash_io0_di_core),
+        .flash_io1_di_core(flash_io1_di_core),        
+ `ifdef SPLIT_BUS
+        `MPRJ_IO,
+        `MPRJ_IO_IN,
+        `MPRJ_IO_OUT,
+        `MPRJ_IO_OEB,
+        `MPRJ_IO_INP_DIS,
+        `MPRJ_IO_IB_MODE_SEL,
+        `MPRJ_IO_VTRIP_SEL,
+        `MPRJ_IO_SLOW_SEL,
+        `MPRJ_IO_HOLDOVER,
+        `MPRJ_IO_ANALOG_EN,
+        `MPRJ_IO_ANALOG_SEL,
+        `MPRJ_IO_ANALOG_POL,
+        `MPRJ_IO_DM,
+        `MPRJ_IO_ANALOG
+ `else
+        .mprj_io(mprj_io),
+        .mprj_io_in(mprj_io_in),
+        .mprj_io_out(mprj_io_out),
+        .mprj_io_oeb(mprj_io_oeb),
+        .mprj_io_inp_dis(mprj_io_inp_dis),
+        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+        .mprj_io_slow_sel(mprj_io_slow_sel),
+        .mprj_io_holdover(mprj_io_holdover),
+        .mprj_io_analog_en(mprj_io_analog_en),
+        .mprj_io_analog_sel(mprj_io_analog_sel),
+        .mprj_io_analog_pol(mprj_io_analog_pol),
+        .mprj_io_dm(mprj_io_dm),
+        .mprj_analog_io(mprj_analog_io)
+`endif
+    );
+
+endmodule

diff --git a/verilog/dv/wb_utests/chip_io/ports.v b/verilog/dv/wb_utests/chip_io/ports.v
new file mode 100644
index 0000000..6516802
--- /dev/null
+++ b/verilog/dv/wb_utests/chip_io/ports.v

@@ -0,0 +1,727 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`define MPRJ_IO \
+.\mprj_io[0] (mprj_io[0]),\
+.\mprj_io[1] (mprj_io[1]),\
+.\mprj_io[2] (mprj_io[2]),\
+.\mprj_io[3] (mprj_io[3]),\
+.\mprj_io[4] (mprj_io[4]),\
+.\mprj_io[5] (mprj_io[5]),\
+.\mprj_io[6] (mprj_io[6]),\
+.\mprj_io[7] (mprj_io[7]),\   
+.\mprj_io[8] (mprj_io[8]),\  
+.\mprj_io[9] (mprj_io[9]),\  
+.\mprj_io[10] (mprj_io[10]),\  
+.\mprj_io[11] (mprj_io[11]),\  
+.\mprj_io[12] (mprj_io[12]),\  
+.\mprj_io[13] (mprj_io[13]),\  
+.\mprj_io[14] (mprj_io[14]),\  
+.\mprj_io[15] (mprj_io[15]),\  
+.\mprj_io[16] (mprj_io[16]),\  
+.\mprj_io[17] (mprj_io[17]),\  
+.\mprj_io[18] (mprj_io[18]),\  
+.\mprj_io[19] (mprj_io[19]),\  
+.\mprj_io[20] (mprj_io[20]),\  
+.\mprj_io[21] (mprj_io[21]),\  
+.\mprj_io[22] (mprj_io[22]),\  
+.\mprj_io[23] (mprj_io[23]),\  
+.\mprj_io[24] (mprj_io[24]),\  
+.\mprj_io[25] (mprj_io[25]),\  
+.\mprj_io[26] (mprj_io[26]),\  
+.\mprj_io[27] (mprj_io[27]),\  
+.\mprj_io[28] (mprj_io[28]),\  
+.\mprj_io[29] (mprj_io[29]),\  
+.\mprj_io[30] (mprj_io[30]),\  
+.\mprj_io[31] (mprj_io[31]),\  
+.\mprj_io[32] (mprj_io[32]),\  
+.\mprj_io[33] (mprj_io[33]),\  
+.\mprj_io[34] (mprj_io[34]),\  
+.\mprj_io[35] (mprj_io[35]),\  
+.\mprj_io[36] (mprj_io[36]),\  
+.\mprj_io[37] (mprj_io[37])
+
+`define MPRJ_IO_IN \
+.\mprj_io_in[0] (mprj_io_in[0]),\
+.\mprj_io_in[1] (mprj_io_in[1]),\
+.\mprj_io_in[2] (mprj_io_in[2]),\
+.\mprj_io_in[3] (mprj_io_in[3]),\
+.\mprj_io_in[4] (mprj_io_in[4]),\
+.\mprj_io_in[5] (mprj_io_in[5]),\
+.\mprj_io_in[6] (mprj_io_in[6]),\
+.\mprj_io_in[7] (mprj_io_in[7]),\
+.\mprj_io_in[8] (mprj_io_in[8]),\
+.\mprj_io_in[9] (mprj_io_in[9]),\
+.\mprj_io_in[10] (mprj_io_in[10]),\
+.\mprj_io_in[11] (mprj_io_in[11]),\
+.\mprj_io_in[12] (mprj_io_in[12]),\
+.\mprj_io_in[13] (mprj_io_in[13]),\
+.\mprj_io_in[14] (mprj_io_in[14]),\
+.\mprj_io_in[15] (mprj_io_in[15]),\
+.\mprj_io_in[16] (mprj_io_in[16]),\
+.\mprj_io_in[17] (mprj_io_in[17]),\
+.\mprj_io_in[18] (mprj_io_in[18]),\
+.\mprj_io_in[19] (mprj_io_in[19]),\
+.\mprj_io_in[20] (mprj_io_in[20]),\
+.\mprj_io_in[21] (mprj_io_in[21]),\
+.\mprj_io_in[22] (mprj_io_in[22]),\
+.\mprj_io_in[23] (mprj_io_in[23]),\
+.\mprj_io_in[24] (mprj_io_in[24]),\
+.\mprj_io_in[25] (mprj_io_in[25]),\
+.\mprj_io_in[26] (mprj_io_in[26]),\
+.\mprj_io_in[27] (mprj_io_in[27]),\
+.\mprj_io_in[28] (mprj_io_in[28]),\
+.\mprj_io_in[29] (mprj_io_in[29]),\
+.\mprj_io_in[30] (mprj_io_in[30]),\
+.\mprj_io_in[31] (mprj_io_in[31]),\
+.\mprj_io_in[32] (mprj_io_in[32]),\
+.\mprj_io_in[33] (mprj_io_in[33]),\
+.\mprj_io_in[34] (mprj_io_in[34]),\
+.\mprj_io_in[35] (mprj_io_in[35]),\
+.\mprj_io_in[36] (mprj_io_in[36]),\
+.\mprj_io_in[37] (mprj_io_in[37])
+
+
+`define MPRJ_IO_OUT \
+.\mprj_io_out[0] (mprj_io_out[0]),\
+.\mprj_io_out[1] (mprj_io_out[1]),\
+.\mprj_io_out[2] (mprj_io_out[2]),\
+.\mprj_io_out[3] (mprj_io_out[3]),\
+.\mprj_io_out[4] (mprj_io_out[4]),\
+.\mprj_io_out[5] (mprj_io_out[5]),\
+.\mprj_io_out[6] (mprj_io_out[6]),\
+.\mprj_io_out[7] (mprj_io_out[7]),\
+.\mprj_io_out[8] (mprj_io_out[8]),\
+.\mprj_io_out[9] (mprj_io_out[9]),\
+.\mprj_io_out[10] (mprj_io_out[10]),\
+.\mprj_io_out[11] (mprj_io_out[11]),\
+.\mprj_io_out[12] (mprj_io_out[12]),\
+.\mprj_io_out[13] (mprj_io_out[13]),\
+.\mprj_io_out[14] (mprj_io_out[14]),\
+.\mprj_io_out[15] (mprj_io_out[15]),\
+.\mprj_io_out[16] (mprj_io_out[16]),\
+.\mprj_io_out[17] (mprj_io_out[17]),\
+.\mprj_io_out[18] (mprj_io_out[18]),\
+.\mprj_io_out[19] (mprj_io_out[19]),\
+.\mprj_io_out[20] (mprj_io_out[20]),\
+.\mprj_io_out[21] (mprj_io_out[21]),\
+.\mprj_io_out[22] (mprj_io_out[22]),\
+.\mprj_io_out[23] (mprj_io_out[23]),\
+.\mprj_io_out[24] (mprj_io_out[24]),\
+.\mprj_io_out[25] (mprj_io_out[25]),\
+.\mprj_io_out[26] (mprj_io_out[26]),\
+.\mprj_io_out[27] (mprj_io_out[27]),\
+.\mprj_io_out[28] (mprj_io_out[28]),\
+.\mprj_io_out[29] (mprj_io_out[29]),\
+.\mprj_io_out[30] (mprj_io_out[30]),\
+.\mprj_io_out[31] (mprj_io_out[31]),\
+.\mprj_io_out[32] (mprj_io_out[32]),\
+.\mprj_io_out[33] (mprj_io_out[33]),\
+.\mprj_io_out[34] (mprj_io_out[34]),\
+.\mprj_io_out[35] (mprj_io_out[35]),\
+.\mprj_io_out[36] (mprj_io_out[36]),\
+.\mprj_io_out[37] (mprj_io_out[37])
+
+`define MPRJ_IO_OEB \
+.\mprj_io_oeb[0] (mprj_io_oeb[0]),\
+.\mprj_io_oeb[1] (mprj_io_oeb[1]),\
+.\mprj_io_oeb[2] (mprj_io_oeb[2]),\
+.\mprj_io_oeb[3] (mprj_io_oeb[3]),\
+.\mprj_io_oeb[4] (mprj_io_oeb[4]),\
+.\mprj_io_oeb[5] (mprj_io_oeb[5]),\
+.\mprj_io_oeb[6] (mprj_io_oeb[6]),\
+.\mprj_io_oeb[7] (mprj_io_oeb[7]),\
+.\mprj_io_oeb[8] (mprj_io_oeb[8]),\
+.\mprj_io_oeb[9] (mprj_io_oeb[9]),\
+.\mprj_io_oeb[10] (mprj_io_oeb[10]),\
+.\mprj_io_oeb[11] (mprj_io_oeb[11]),\
+.\mprj_io_oeb[12] (mprj_io_oeb[12]),\
+.\mprj_io_oeb[13] (mprj_io_oeb[13]),\
+.\mprj_io_oeb[14] (mprj_io_oeb[14]),\
+.\mprj_io_oeb[15] (mprj_io_oeb[15]),\
+.\mprj_io_oeb[16] (mprj_io_oeb[16]),\
+.\mprj_io_oeb[17] (mprj_io_oeb[17]),\
+.\mprj_io_oeb[18] (mprj_io_oeb[18]),\
+.\mprj_io_oeb[19] (mprj_io_oeb[19]),\
+.\mprj_io_oeb[20] (mprj_io_oeb[20]),\
+.\mprj_io_oeb[21] (mprj_io_oeb[21]),\
+.\mprj_io_oeb[22] (mprj_io_oeb[22]),\
+.\mprj_io_oeb[23] (mprj_io_oeb[23]),\
+.\mprj_io_oeb[24] (mprj_io_oeb[24]),\
+.\mprj_io_oeb[25] (mprj_io_oeb[25]),\
+.\mprj_io_oeb[26] (mprj_io_oeb[26]),\
+.\mprj_io_oeb[27] (mprj_io_oeb[27]),\
+.\mprj_io_oeb[28] (mprj_io_oeb[28]),\
+.\mprj_io_oeb[29] (mprj_io_oeb[29]),\
+.\mprj_io_oeb[30] (mprj_io_oeb[30]),\
+.\mprj_io_oeb[31] (mprj_io_oeb[31]),\
+.\mprj_io_oeb[32] (mprj_io_oeb[32]),\
+.\mprj_io_oeb[33] (mprj_io_oeb[33]),\
+.\mprj_io_oeb[34] (mprj_io_oeb[34]),\
+.\mprj_io_oeb[35] (mprj_io_oeb[35]),\
+.\mprj_io_oeb[36] (mprj_io_oeb[36]),\
+.\mprj_io_oeb[37] (mprj_io_oeb[37])
+
+`define MPRJ_IO_HLDH_N \
+.\mprj_io_hldh_n[0] (mprj_io_hldh_n[0]),\
+.\mprj_io_hldh_n[1] (mprj_io_hldh_n[1]),\
+.\mprj_io_hldh_n[2] (mprj_io_hldh_n[2]),\
+.\mprj_io_hldh_n[3] (mprj_io_hldh_n[3]),\
+.\mprj_io_hldh_n[4] (mprj_io_hldh_n[4]),\
+.\mprj_io_hldh_n[5] (mprj_io_hldh_n[5]),\
+.\mprj_io_hldh_n[6] (mprj_io_hldh_n[6]),\
+.\mprj_io_hldh_n[7] (mprj_io_hldh_n[7]),\
+.\mprj_io_hldh_n[8] (mprj_io_hldh_n[8]),\
+.\mprj_io_hldh_n[9] (mprj_io_hldh_n[9]),\
+.\mprj_io_hldh_n[10] (mprj_io_hldh_n[10]),\
+.\mprj_io_hldh_n[11] (mprj_io_hldh_n[11]),\
+.\mprj_io_hldh_n[12] (mprj_io_hldh_n[12]),\
+.\mprj_io_hldh_n[13] (mprj_io_hldh_n[13]),\
+.\mprj_io_hldh_n[14] (mprj_io_hldh_n[14]),\
+.\mprj_io_hldh_n[15] (mprj_io_hldh_n[15]),\
+.\mprj_io_hldh_n[16] (mprj_io_hldh_n[16]),\
+.\mprj_io_hldh_n[17] (mprj_io_hldh_n[17]),\
+.\mprj_io_hldh_n[18] (mprj_io_hldh_n[18]),\
+.\mprj_io_hldh_n[19] (mprj_io_hldh_n[19]),\
+.\mprj_io_hldh_n[20] (mprj_io_hldh_n[20]),\
+.\mprj_io_hldh_n[21] (mprj_io_hldh_n[21]),\
+.\mprj_io_hldh_n[22] (mprj_io_hldh_n[22]),\
+.\mprj_io_hldh_n[23] (mprj_io_hldh_n[23]),\
+.\mprj_io_hldh_n[24] (mprj_io_hldh_n[24]),\
+.\mprj_io_hldh_n[25] (mprj_io_hldh_n[25]),\
+.\mprj_io_hldh_n[26] (mprj_io_hldh_n[26]),\
+.\mprj_io_hldh_n[27] (mprj_io_hldh_n[27]),\
+.\mprj_io_hldh_n[28] (mprj_io_hldh_n[28]),\
+.\mprj_io_hldh_n[29] (mprj_io_hldh_n[29]),\
+.\mprj_io_hldh_n[30] (mprj_io_hldh_n[30]),\
+.\mprj_io_hldh_n[31] (mprj_io_hldh_n[31]),\
+.\mprj_io_hldh_n[32] (mprj_io_hldh_n[32]),\
+.\mprj_io_hldh_n[33] (mprj_io_hldh_n[33]),\
+.\mprj_io_hldh_n[34] (mprj_io_hldh_n[34]),\
+.\mprj_io_hldh_n[35] (mprj_io_hldh_n[35]),\
+.\mprj_io_hldh_n[36] (mprj_io_hldh_n[36]),\
+.\mprj_io_hldh_n[37] (mprj_io_hldh_n[37])
+
+`define MPRJ_IO_ENH \
+.\mprj_io_enh[0] (mprj_io_enh[0]),\
+.\mprj_io_enh[1] (mprj_io_enh[1]),\
+.\mprj_io_enh[2] (mprj_io_enh[2]),\
+.\mprj_io_enh[3] (mprj_io_enh[3]),\
+.\mprj_io_enh[4] (mprj_io_enh[4]),\
+.\mprj_io_enh[5] (mprj_io_enh[5]),\
+.\mprj_io_enh[6] (mprj_io_enh[6]),\
+.\mprj_io_enh[7] (mprj_io_enh[7]),\
+.\mprj_io_enh[8] (mprj_io_enh[8]),\
+.\mprj_io_enh[9] (mprj_io_enh[9]),\
+.\mprj_io_enh[10] (mprj_io_enh[10]),\
+.\mprj_io_enh[11] (mprj_io_enh[11]),\
+.\mprj_io_enh[12] (mprj_io_enh[12]),\
+.\mprj_io_enh[13] (mprj_io_enh[13]),\
+.\mprj_io_enh[14] (mprj_io_enh[14]),\
+.\mprj_io_enh[15] (mprj_io_enh[15]),\
+.\mprj_io_enh[16] (mprj_io_enh[16]),\
+.\mprj_io_enh[17] (mprj_io_enh[17]),\
+.\mprj_io_enh[18] (mprj_io_enh[18]),\
+.\mprj_io_enh[19] (mprj_io_enh[19]),\
+.\mprj_io_enh[20] (mprj_io_enh[20]),\
+.\mprj_io_enh[21] (mprj_io_enh[21]),\
+.\mprj_io_enh[22] (mprj_io_enh[22]),\
+.\mprj_io_enh[23] (mprj_io_enh[23]),\
+.\mprj_io_enh[24] (mprj_io_enh[24]),\
+.\mprj_io_enh[25] (mprj_io_enh[25]),\
+.\mprj_io_enh[26] (mprj_io_enh[26]),\
+.\mprj_io_enh[27] (mprj_io_enh[27]),\
+.\mprj_io_enh[28] (mprj_io_enh[28]),\
+.\mprj_io_enh[29] (mprj_io_enh[29]),\
+.\mprj_io_enh[30] (mprj_io_enh[30]),\
+.\mprj_io_enh[31] (mprj_io_enh[31]),\
+.\mprj_io_enh[32] (mprj_io_enh[32]),\
+.\mprj_io_enh[33] (mprj_io_enh[33]),\
+.\mprj_io_enh[34] (mprj_io_enh[34]),\
+.\mprj_io_enh[35] (mprj_io_enh[35]),\
+.\mprj_io_enh[36] (mprj_io_enh[36]),\
+.\mprj_io_enh[37] (mprj_io_enh[37])
+
+`define MPRJ_IO_INP_DIS \
+.\mprj_io_inp_dis[0] (mprj_io_inp_dis[0]),\
+.\mprj_io_inp_dis[1] (mprj_io_inp_dis[1]),\
+.\mprj_io_inp_dis[2] (mprj_io_inp_dis[2]),\
+.\mprj_io_inp_dis[3] (mprj_io_inp_dis[3]),\
+.\mprj_io_inp_dis[4] (mprj_io_inp_dis[4]),\
+.\mprj_io_inp_dis[5] (mprj_io_inp_dis[5]),\
+.\mprj_io_inp_dis[6] (mprj_io_inp_dis[6]),\
+.\mprj_io_inp_dis[7] (mprj_io_inp_dis[7]),\
+.\mprj_io_inp_dis[8] (mprj_io_inp_dis[8]),\
+.\mprj_io_inp_dis[9] (mprj_io_inp_dis[9]),\
+.\mprj_io_inp_dis[10] (mprj_io_inp_dis[10]),\
+.\mprj_io_inp_dis[11] (mprj_io_inp_dis[11]),\
+.\mprj_io_inp_dis[12] (mprj_io_inp_dis[12]),\
+.\mprj_io_inp_dis[13] (mprj_io_inp_dis[13]),\
+.\mprj_io_inp_dis[14] (mprj_io_inp_dis[14]),\
+.\mprj_io_inp_dis[15] (mprj_io_inp_dis[15]),\
+.\mprj_io_inp_dis[16] (mprj_io_inp_dis[16]),\
+.\mprj_io_inp_dis[17] (mprj_io_inp_dis[17]),\
+.\mprj_io_inp_dis[18] (mprj_io_inp_dis[18]),\
+.\mprj_io_inp_dis[19] (mprj_io_inp_dis[19]),\
+.\mprj_io_inp_dis[20] (mprj_io_inp_dis[20]),\
+.\mprj_io_inp_dis[21] (mprj_io_inp_dis[21]),\
+.\mprj_io_inp_dis[22] (mprj_io_inp_dis[22]),\
+.\mprj_io_inp_dis[23] (mprj_io_inp_dis[23]),\
+.\mprj_io_inp_dis[24] (mprj_io_inp_dis[24]),\
+.\mprj_io_inp_dis[25] (mprj_io_inp_dis[25]),\
+.\mprj_io_inp_dis[26] (mprj_io_inp_dis[26]),\
+.\mprj_io_inp_dis[27] (mprj_io_inp_dis[27]),\
+.\mprj_io_inp_dis[28] (mprj_io_inp_dis[28]),\
+.\mprj_io_inp_dis[29] (mprj_io_inp_dis[29]),\
+.\mprj_io_inp_dis[30] (mprj_io_inp_dis[30]),\
+.\mprj_io_inp_dis[31] (mprj_io_inp_dis[31]),\
+.\mprj_io_inp_dis[32] (mprj_io_inp_dis[32]),\
+.\mprj_io_inp_dis[33] (mprj_io_inp_dis[33]),\
+.\mprj_io_inp_dis[34] (mprj_io_inp_dis[34]),\
+.\mprj_io_inp_dis[35] (mprj_io_inp_dis[35]),\
+.\mprj_io_inp_dis[36] (mprj_io_inp_dis[36]),\
+.\mprj_io_inp_dis[37] (mprj_io_inp_dis[37])
+
+`define MPRJ_IO_IB_MODE_SEL \
+.\mprj_io_ib_mode_sel[0] (mprj_io_ib_mode_sel[0]),\
+.\mprj_io_ib_mode_sel[1] (mprj_io_ib_mode_sel[1]),\
+.\mprj_io_ib_mode_sel[2] (mprj_io_ib_mode_sel[2]),\
+.\mprj_io_ib_mode_sel[3] (mprj_io_ib_mode_sel[3]),\
+.\mprj_io_ib_mode_sel[4] (mprj_io_ib_mode_sel[4]),\
+.\mprj_io_ib_mode_sel[5] (mprj_io_ib_mode_sel[5]),\
+.\mprj_io_ib_mode_sel[6] (mprj_io_ib_mode_sel[6]),\
+.\mprj_io_ib_mode_sel[7] (mprj_io_ib_mode_sel[7]),\
+.\mprj_io_ib_mode_sel[8] (mprj_io_ib_mode_sel[8]),\
+.\mprj_io_ib_mode_sel[9] (mprj_io_ib_mode_sel[9]),\
+.\mprj_io_ib_mode_sel[10] (mprj_io_ib_mode_sel[10]),\
+.\mprj_io_ib_mode_sel[11] (mprj_io_ib_mode_sel[11]),\
+.\mprj_io_ib_mode_sel[12] (mprj_io_ib_mode_sel[12]),\
+.\mprj_io_ib_mode_sel[13] (mprj_io_ib_mode_sel[13]),\
+.\mprj_io_ib_mode_sel[14] (mprj_io_ib_mode_sel[14]),\
+.\mprj_io_ib_mode_sel[15] (mprj_io_ib_mode_sel[15]),\
+.\mprj_io_ib_mode_sel[16] (mprj_io_ib_mode_sel[16]),\
+.\mprj_io_ib_mode_sel[17] (mprj_io_ib_mode_sel[17]),\
+.\mprj_io_ib_mode_sel[18] (mprj_io_ib_mode_sel[18]),\
+.\mprj_io_ib_mode_sel[19] (mprj_io_ib_mode_sel[19]),\
+.\mprj_io_ib_mode_sel[20] (mprj_io_ib_mode_sel[20]),\
+.\mprj_io_ib_mode_sel[21] (mprj_io_ib_mode_sel[21]),\
+.\mprj_io_ib_mode_sel[22] (mprj_io_ib_mode_sel[22]),\
+.\mprj_io_ib_mode_sel[23] (mprj_io_ib_mode_sel[23]),\
+.\mprj_io_ib_mode_sel[24] (mprj_io_ib_mode_sel[24]),\
+.\mprj_io_ib_mode_sel[25] (mprj_io_ib_mode_sel[25]),\
+.\mprj_io_ib_mode_sel[26] (mprj_io_ib_mode_sel[26]),\
+.\mprj_io_ib_mode_sel[27] (mprj_io_ib_mode_sel[27]),\
+.\mprj_io_ib_mode_sel[28] (mprj_io_ib_mode_sel[28]),\
+.\mprj_io_ib_mode_sel[29] (mprj_io_ib_mode_sel[29]),\
+.\mprj_io_ib_mode_sel[30] (mprj_io_ib_mode_sel[30]),\
+.\mprj_io_ib_mode_sel[31] (mprj_io_ib_mode_sel[31]),\
+.\mprj_io_ib_mode_sel[32] (mprj_io_ib_mode_sel[32]),\
+.\mprj_io_ib_mode_sel[33] (mprj_io_ib_mode_sel[33]),\
+.\mprj_io_ib_mode_sel[34] (mprj_io_ib_mode_sel[34]),\
+.\mprj_io_ib_mode_sel[35] (mprj_io_ib_mode_sel[35]),\
+.\mprj_io_ib_mode_sel[36] (mprj_io_ib_mode_sel[36]),\
+.\mprj_io_ib_mode_sel[37] (mprj_io_ib_mode_sel[37])
+
+`define MPRJ_IO_VTRIP_SEL \
+.\mprj_io_vtrip_sel[0] (mprj_io_vtrip_sel[0]),\
+.\mprj_io_vtrip_sel[1] (mprj_io_vtrip_sel[1]),\
+.\mprj_io_vtrip_sel[2] (mprj_io_vtrip_sel[2]),\
+.\mprj_io_vtrip_sel[3] (mprj_io_vtrip_sel[3]),\
+.\mprj_io_vtrip_sel[4] (mprj_io_vtrip_sel[4]),\
+.\mprj_io_vtrip_sel[5] (mprj_io_vtrip_sel[5]),\
+.\mprj_io_vtrip_sel[6] (mprj_io_vtrip_sel[6]),\
+.\mprj_io_vtrip_sel[7] (mprj_io_vtrip_sel[7]),\
+.\mprj_io_vtrip_sel[8] (mprj_io_vtrip_sel[8]),\
+.\mprj_io_vtrip_sel[9] (mprj_io_vtrip_sel[9]),\
+.\mprj_io_vtrip_sel[10] (mprj_io_vtrip_sel[10]),\
+.\mprj_io_vtrip_sel[11] (mprj_io_vtrip_sel[11]),\
+.\mprj_io_vtrip_sel[12] (mprj_io_vtrip_sel[12]),\
+.\mprj_io_vtrip_sel[13] (mprj_io_vtrip_sel[13]),\
+.\mprj_io_vtrip_sel[14] (mprj_io_vtrip_sel[14]),\
+.\mprj_io_vtrip_sel[15] (mprj_io_vtrip_sel[15]),\
+.\mprj_io_vtrip_sel[16] (mprj_io_vtrip_sel[16]),\
+.\mprj_io_vtrip_sel[17] (mprj_io_vtrip_sel[17]),\
+.\mprj_io_vtrip_sel[18] (mprj_io_vtrip_sel[18]),\
+.\mprj_io_vtrip_sel[19] (mprj_io_vtrip_sel[19]),\
+.\mprj_io_vtrip_sel[20] (mprj_io_vtrip_sel[20]),\
+.\mprj_io_vtrip_sel[21] (mprj_io_vtrip_sel[21]),\
+.\mprj_io_vtrip_sel[22] (mprj_io_vtrip_sel[22]),\
+.\mprj_io_vtrip_sel[23] (mprj_io_vtrip_sel[23]),\
+.\mprj_io_vtrip_sel[24] (mprj_io_vtrip_sel[24]),\
+.\mprj_io_vtrip_sel[25] (mprj_io_vtrip_sel[25]),\
+.\mprj_io_vtrip_sel[26] (mprj_io_vtrip_sel[26]),\
+.\mprj_io_vtrip_sel[27] (mprj_io_vtrip_sel[27]),\
+.\mprj_io_vtrip_sel[28] (mprj_io_vtrip_sel[28]),\
+.\mprj_io_vtrip_sel[29] (mprj_io_vtrip_sel[29]),\
+.\mprj_io_vtrip_sel[30] (mprj_io_vtrip_sel[30]),\
+.\mprj_io_vtrip_sel[31] (mprj_io_vtrip_sel[31]),\
+.\mprj_io_vtrip_sel[32] (mprj_io_vtrip_sel[32]),\
+.\mprj_io_vtrip_sel[33] (mprj_io_vtrip_sel[33]),\
+.\mprj_io_vtrip_sel[34] (mprj_io_vtrip_sel[34]),\
+.\mprj_io_vtrip_sel[35] (mprj_io_vtrip_sel[35]),\
+.\mprj_io_vtrip_sel[36] (mprj_io_vtrip_sel[36]),\
+.\mprj_io_vtrip_sel[37] (mprj_io_vtrip_sel[37])
+
+
+`define MPRJ_IO_SLOW_SEL \
+.\mprj_io_slow_sel[0] (mprj_io_slow_sel[0]),\
+.\mprj_io_slow_sel[1] (mprj_io_slow_sel[1]),\
+.\mprj_io_slow_sel[2] (mprj_io_slow_sel[2]),\
+.\mprj_io_slow_sel[3] (mprj_io_slow_sel[3]),\
+.\mprj_io_slow_sel[4] (mprj_io_slow_sel[4]),\
+.\mprj_io_slow_sel[5] (mprj_io_slow_sel[5]),\
+.\mprj_io_slow_sel[6] (mprj_io_slow_sel[6]),\
+.\mprj_io_slow_sel[7] (mprj_io_slow_sel[7]),\
+.\mprj_io_slow_sel[8] (mprj_io_slow_sel[8]),\
+.\mprj_io_slow_sel[9] (mprj_io_slow_sel[9]),\
+.\mprj_io_slow_sel[10] (mprj_io_slow_sel[10]),\
+.\mprj_io_slow_sel[11] (mprj_io_slow_sel[11]),\
+.\mprj_io_slow_sel[12] (mprj_io_slow_sel[12]),\
+.\mprj_io_slow_sel[13] (mprj_io_slow_sel[13]),\
+.\mprj_io_slow_sel[14] (mprj_io_slow_sel[14]),\
+.\mprj_io_slow_sel[15] (mprj_io_slow_sel[15]),\
+.\mprj_io_slow_sel[16] (mprj_io_slow_sel[16]),\
+.\mprj_io_slow_sel[17] (mprj_io_slow_sel[17]),\
+.\mprj_io_slow_sel[18] (mprj_io_slow_sel[18]),\
+.\mprj_io_slow_sel[19] (mprj_io_slow_sel[19]),\
+.\mprj_io_slow_sel[20] (mprj_io_slow_sel[20]),\
+.\mprj_io_slow_sel[21] (mprj_io_slow_sel[21]),\
+.\mprj_io_slow_sel[22] (mprj_io_slow_sel[22]),\
+.\mprj_io_slow_sel[23] (mprj_io_slow_sel[23]),\
+.\mprj_io_slow_sel[24] (mprj_io_slow_sel[24]),\
+.\mprj_io_slow_sel[25] (mprj_io_slow_sel[25]),\
+.\mprj_io_slow_sel[26] (mprj_io_slow_sel[26]),\
+.\mprj_io_slow_sel[27] (mprj_io_slow_sel[27]),\
+.\mprj_io_slow_sel[28] (mprj_io_slow_sel[28]),\
+.\mprj_io_slow_sel[29] (mprj_io_slow_sel[29]),\
+.\mprj_io_slow_sel[30] (mprj_io_slow_sel[30]),\
+.\mprj_io_slow_sel[31] (mprj_io_slow_sel[31]),\
+.\mprj_io_slow_sel[32] (mprj_io_slow_sel[32]),\
+.\mprj_io_slow_sel[33] (mprj_io_slow_sel[33]),\
+.\mprj_io_slow_sel[34] (mprj_io_slow_sel[34]),\
+.\mprj_io_slow_sel[35] (mprj_io_slow_sel[35]),\
+.\mprj_io_slow_sel[36] (mprj_io_slow_sel[36]),\
+.\mprj_io_slow_sel[37] (mprj_io_slow_sel[37])
+
+
+`define MPRJ_IO_HOLDOVER \
+.\mprj_io_holdover[0] (mprj_io_holdover[0]),\
+.\mprj_io_holdover[1] (mprj_io_holdover[1]),\
+.\mprj_io_holdover[2] (mprj_io_holdover[2]),\
+.\mprj_io_holdover[3] (mprj_io_holdover[3]),\
+.\mprj_io_holdover[4] (mprj_io_holdover[4]),\
+.\mprj_io_holdover[5] (mprj_io_holdover[5]),\
+.\mprj_io_holdover[6] (mprj_io_holdover[6]),\
+.\mprj_io_holdover[7] (mprj_io_holdover[7]),\
+.\mprj_io_holdover[8] (mprj_io_holdover[8]),\
+.\mprj_io_holdover[9] (mprj_io_holdover[9]),\
+.\mprj_io_holdover[10] (mprj_io_holdover[10]),\
+.\mprj_io_holdover[11] (mprj_io_holdover[11]),\
+.\mprj_io_holdover[12] (mprj_io_holdover[12]),\
+.\mprj_io_holdover[13] (mprj_io_holdover[13]),\
+.\mprj_io_holdover[14] (mprj_io_holdover[14]),\
+.\mprj_io_holdover[15] (mprj_io_holdover[15]),\
+.\mprj_io_holdover[16] (mprj_io_holdover[16]),\
+.\mprj_io_holdover[17] (mprj_io_holdover[17]),\
+.\mprj_io_holdover[18] (mprj_io_holdover[18]),\
+.\mprj_io_holdover[19] (mprj_io_holdover[19]),\
+.\mprj_io_holdover[20] (mprj_io_holdover[20]),\
+.\mprj_io_holdover[21] (mprj_io_holdover[21]),\
+.\mprj_io_holdover[22] (mprj_io_holdover[22]),\
+.\mprj_io_holdover[23] (mprj_io_holdover[23]),\
+.\mprj_io_holdover[24] (mprj_io_holdover[24]),\
+.\mprj_io_holdover[25] (mprj_io_holdover[25]),\
+.\mprj_io_holdover[26] (mprj_io_holdover[26]),\
+.\mprj_io_holdover[27] (mprj_io_holdover[27]),\
+.\mprj_io_holdover[28] (mprj_io_holdover[28]),\
+.\mprj_io_holdover[29] (mprj_io_holdover[29]),\
+.\mprj_io_holdover[30] (mprj_io_holdover[30]),\
+.\mprj_io_holdover[31] (mprj_io_holdover[31]),\
+.\mprj_io_holdover[32] (mprj_io_holdover[32]),\
+.\mprj_io_holdover[33] (mprj_io_holdover[33]),\
+.\mprj_io_holdover[34] (mprj_io_holdover[34]),\
+.\mprj_io_holdover[35] (mprj_io_holdover[35]),\
+.\mprj_io_holdover[36] (mprj_io_holdover[36]),\
+.\mprj_io_holdover[37] (mprj_io_holdover[37])
+
+`define MPRJ_IO_ANALOG_EN \
+.\mprj_io_analog_en[0] (mprj_io_analog_en[0]),\
+.\mprj_io_analog_en[1] (mprj_io_analog_en[1]),\
+.\mprj_io_analog_en[2] (mprj_io_analog_en[2]),\
+.\mprj_io_analog_en[3] (mprj_io_analog_en[3]),\
+.\mprj_io_analog_en[4] (mprj_io_analog_en[4]),\
+.\mprj_io_analog_en[5] (mprj_io_analog_en[5]),\
+.\mprj_io_analog_en[6] (mprj_io_analog_en[6]),\
+.\mprj_io_analog_en[7] (mprj_io_analog_en[7]),\
+.\mprj_io_analog_en[8] (mprj_io_analog_en[8]),\
+.\mprj_io_analog_en[9] (mprj_io_analog_en[9]),\
+.\mprj_io_analog_en[10] (mprj_io_analog_en[10]),\
+.\mprj_io_analog_en[11] (mprj_io_analog_en[11]),\
+.\mprj_io_analog_en[12] (mprj_io_analog_en[12]),\
+.\mprj_io_analog_en[13] (mprj_io_analog_en[13]),\
+.\mprj_io_analog_en[14] (mprj_io_analog_en[14]),\
+.\mprj_io_analog_en[15] (mprj_io_analog_en[15]),\
+.\mprj_io_analog_en[16] (mprj_io_analog_en[16]),\
+.\mprj_io_analog_en[17] (mprj_io_analog_en[17]),\
+.\mprj_io_analog_en[18] (mprj_io_analog_en[18]),\
+.\mprj_io_analog_en[19] (mprj_io_analog_en[19]),\
+.\mprj_io_analog_en[20] (mprj_io_analog_en[20]),\
+.\mprj_io_analog_en[21] (mprj_io_analog_en[21]),\
+.\mprj_io_analog_en[22] (mprj_io_analog_en[22]),\
+.\mprj_io_analog_en[23] (mprj_io_analog_en[23]),\
+.\mprj_io_analog_en[24] (mprj_io_analog_en[24]),\
+.\mprj_io_analog_en[25] (mprj_io_analog_en[25]),\
+.\mprj_io_analog_en[26] (mprj_io_analog_en[26]),\
+.\mprj_io_analog_en[27] (mprj_io_analog_en[27]),\
+.\mprj_io_analog_en[28] (mprj_io_analog_en[28]),\
+.\mprj_io_analog_en[29] (mprj_io_analog_en[29]),\
+.\mprj_io_analog_en[30] (mprj_io_analog_en[30]),\
+.\mprj_io_analog_en[31] (mprj_io_analog_en[31]),\
+.\mprj_io_analog_en[32] (mprj_io_analog_en[32]),\
+.\mprj_io_analog_en[33] (mprj_io_analog_en[33]),\
+.\mprj_io_analog_en[34] (mprj_io_analog_en[34]),\
+.\mprj_io_analog_en[35] (mprj_io_analog_en[35]),\
+.\mprj_io_analog_en[36] (mprj_io_analog_en[36]),\
+.\mprj_io_analog_en[37] (mprj_io_analog_en[37])
+
+`define MPRJ_IO_ANALOG_SEL \
+.\mprj_io_analog_sel[0] (mprj_io_analog_sel[0]),\
+.\mprj_io_analog_sel[1] (mprj_io_analog_sel[1]),\
+.\mprj_io_analog_sel[2] (mprj_io_analog_sel[2]),\
+.\mprj_io_analog_sel[3] (mprj_io_analog_sel[3]),\
+.\mprj_io_analog_sel[4] (mprj_io_analog_sel[4]),\
+.\mprj_io_analog_sel[5] (mprj_io_analog_sel[5]),\
+.\mprj_io_analog_sel[6] (mprj_io_analog_sel[6]),\
+.\mprj_io_analog_sel[7] (mprj_io_analog_sel[7]),\
+.\mprj_io_analog_sel[8] (mprj_io_analog_sel[8]),\
+.\mprj_io_analog_sel[9] (mprj_io_analog_sel[9]),\
+.\mprj_io_analog_sel[10] (mprj_io_analog_sel[10]),\
+.\mprj_io_analog_sel[11] (mprj_io_analog_sel[11]),\
+.\mprj_io_analog_sel[12] (mprj_io_analog_sel[12]),\
+.\mprj_io_analog_sel[13] (mprj_io_analog_sel[13]),\
+.\mprj_io_analog_sel[14] (mprj_io_analog_sel[14]),\
+.\mprj_io_analog_sel[15] (mprj_io_analog_sel[15]),\
+.\mprj_io_analog_sel[16] (mprj_io_analog_sel[16]),\
+.\mprj_io_analog_sel[17] (mprj_io_analog_sel[17]),\
+.\mprj_io_analog_sel[18] (mprj_io_analog_sel[18]),\
+.\mprj_io_analog_sel[19] (mprj_io_analog_sel[19]),\
+.\mprj_io_analog_sel[20] (mprj_io_analog_sel[20]),\
+.\mprj_io_analog_sel[21] (mprj_io_analog_sel[21]),\
+.\mprj_io_analog_sel[22] (mprj_io_analog_sel[22]),\
+.\mprj_io_analog_sel[23] (mprj_io_analog_sel[23]),\
+.\mprj_io_analog_sel[24] (mprj_io_analog_sel[24]),\
+.\mprj_io_analog_sel[25] (mprj_io_analog_sel[25]),\
+.\mprj_io_analog_sel[26] (mprj_io_analog_sel[26]),\
+.\mprj_io_analog_sel[27] (mprj_io_analog_sel[27]),\
+.\mprj_io_analog_sel[28] (mprj_io_analog_sel[28]),\
+.\mprj_io_analog_sel[29] (mprj_io_analog_sel[29]),\
+.\mprj_io_analog_sel[30] (mprj_io_analog_sel[30]),\
+.\mprj_io_analog_sel[31] (mprj_io_analog_sel[31]),\
+.\mprj_io_analog_sel[32] (mprj_io_analog_sel[32]),\
+.\mprj_io_analog_sel[33] (mprj_io_analog_sel[33]),\
+.\mprj_io_analog_sel[34] (mprj_io_analog_sel[34]),\
+.\mprj_io_analog_sel[35] (mprj_io_analog_sel[35]),\
+.\mprj_io_analog_sel[36] (mprj_io_analog_sel[36]),\
+.\mprj_io_analog_sel[37] (mprj_io_analog_sel[37])
+
+
+`define MPRJ_IO_ANALOG_POL \
+.\mprj_io_analog_pol[0] (mprj_io_analog_pol[0]),\
+.\mprj_io_analog_pol[1] (mprj_io_analog_pol[1]),\
+.\mprj_io_analog_pol[2] (mprj_io_analog_pol[2]),\
+.\mprj_io_analog_pol[3] (mprj_io_analog_pol[3]),\
+.\mprj_io_analog_pol[4] (mprj_io_analog_pol[4]),\
+.\mprj_io_analog_pol[5] (mprj_io_analog_pol[5]),\
+.\mprj_io_analog_pol[6] (mprj_io_analog_pol[6]),\
+.\mprj_io_analog_pol[7] (mprj_io_analog_pol[7]),\
+.\mprj_io_analog_pol[8] (mprj_io_analog_pol[8]),\
+.\mprj_io_analog_pol[9] (mprj_io_analog_pol[9]),\
+.\mprj_io_analog_pol[10] (mprj_io_analog_pol[10]),\
+.\mprj_io_analog_pol[11] (mprj_io_analog_pol[11]),\
+.\mprj_io_analog_pol[12] (mprj_io_analog_pol[12]),\
+.\mprj_io_analog_pol[13] (mprj_io_analog_pol[13]),\
+.\mprj_io_analog_pol[14] (mprj_io_analog_pol[14]),\
+.\mprj_io_analog_pol[15] (mprj_io_analog_pol[15]),\
+.\mprj_io_analog_pol[16] (mprj_io_analog_pol[16]),\
+.\mprj_io_analog_pol[17] (mprj_io_analog_pol[17]),\
+.\mprj_io_analog_pol[18] (mprj_io_analog_pol[18]),\
+.\mprj_io_analog_pol[19] (mprj_io_analog_pol[19]),\
+.\mprj_io_analog_pol[20] (mprj_io_analog_pol[20]),\
+.\mprj_io_analog_pol[21] (mprj_io_analog_pol[21]),\
+.\mprj_io_analog_pol[22] (mprj_io_analog_pol[22]),\
+.\mprj_io_analog_pol[23] (mprj_io_analog_pol[23]),\
+.\mprj_io_analog_pol[24] (mprj_io_analog_pol[24]),\
+.\mprj_io_analog_pol[25] (mprj_io_analog_pol[25]),\
+.\mprj_io_analog_pol[26] (mprj_io_analog_pol[26]),\
+.\mprj_io_analog_pol[27] (mprj_io_analog_pol[27]),\
+.\mprj_io_analog_pol[28] (mprj_io_analog_pol[28]),\
+.\mprj_io_analog_pol[29] (mprj_io_analog_pol[29]),\
+.\mprj_io_analog_pol[30] (mprj_io_analog_pol[30]),\
+.\mprj_io_analog_pol[31] (mprj_io_analog_pol[31]),\
+.\mprj_io_analog_pol[32] (mprj_io_analog_pol[32]),\
+.\mprj_io_analog_pol[33] (mprj_io_analog_pol[33]),\
+.\mprj_io_analog_pol[34] (mprj_io_analog_pol[34]),\
+.\mprj_io_analog_pol[35] (mprj_io_analog_pol[35]),\
+.\mprj_io_analog_pol[36] (mprj_io_analog_pol[36]),\
+.\mprj_io_analog_pol[37] (mprj_io_analog_pol[37])
+
+`define MPRJ_IO_DM \
+.\mprj_io_dm[0] (mprj_io_dm[0]),\
+.\mprj_io_dm[1] (mprj_io_dm[1]),\
+.\mprj_io_dm[2] (mprj_io_dm[2]),\
+.\mprj_io_dm[3] (mprj_io_dm[3]),\
+.\mprj_io_dm[4] (mprj_io_dm[4]),\
+.\mprj_io_dm[5] (mprj_io_dm[5]),\
+.\mprj_io_dm[6] (mprj_io_dm[6]),\
+.\mprj_io_dm[7] (mprj_io_dm[7]),\
+.\mprj_io_dm[8] (mprj_io_dm[8]),\
+.\mprj_io_dm[9] (mprj_io_dm[9]),\
+.\mprj_io_dm[10] (mprj_io_dm[10]),\
+.\mprj_io_dm[11] (mprj_io_dm[11]),\
+.\mprj_io_dm[12] (mprj_io_dm[12]),\
+.\mprj_io_dm[13] (mprj_io_dm[13]),\
+.\mprj_io_dm[14] (mprj_io_dm[14]),\
+.\mprj_io_dm[15] (mprj_io_dm[15]),\
+.\mprj_io_dm[16] (mprj_io_dm[16]),\
+.\mprj_io_dm[17] (mprj_io_dm[17]),\
+.\mprj_io_dm[18] (mprj_io_dm[18]),\
+.\mprj_io_dm[19] (mprj_io_dm[19]),\
+.\mprj_io_dm[20] (mprj_io_dm[20]),\
+.\mprj_io_dm[21] (mprj_io_dm[21]),\
+.\mprj_io_dm[22] (mprj_io_dm[22]),\
+.\mprj_io_dm[23] (mprj_io_dm[23]),\
+.\mprj_io_dm[24] (mprj_io_dm[24]),\
+.\mprj_io_dm[25] (mprj_io_dm[25]),\
+.\mprj_io_dm[26] (mprj_io_dm[26]),\
+.\mprj_io_dm[27] (mprj_io_dm[27]),\
+.\mprj_io_dm[28] (mprj_io_dm[28]),\
+.\mprj_io_dm[29] (mprj_io_dm[29]),\
+.\mprj_io_dm[30] (mprj_io_dm[30]),\
+.\mprj_io_dm[31] (mprj_io_dm[31]),\
+.\mprj_io_dm[32] (mprj_io_dm[32]),\
+.\mprj_io_dm[33] (mprj_io_dm[33]),\
+.\mprj_io_dm[34] (mprj_io_dm[34]),\
+.\mprj_io_dm[35] (mprj_io_dm[35]),\
+.\mprj_io_dm[36] (mprj_io_dm[36]),\
+.\mprj_io_dm[37] (mprj_io_dm[37]),\
+.\mprj_io_dm[38] (mprj_io_dm[38]),\
+.\mprj_io_dm[39] (mprj_io_dm[39]),\
+.\mprj_io_dm[40] (mprj_io_dm[40]),\
+.\mprj_io_dm[41] (mprj_io_dm[41]),\
+.\mprj_io_dm[42] (mprj_io_dm[42]),\
+.\mprj_io_dm[43] (mprj_io_dm[43]),\
+.\mprj_io_dm[44] (mprj_io_dm[44]),\
+.\mprj_io_dm[45] (mprj_io_dm[45]),\
+.\mprj_io_dm[46] (mprj_io_dm[46]),\
+.\mprj_io_dm[47] (mprj_io_dm[47]),\
+.\mprj_io_dm[48] (mprj_io_dm[48]),\
+.\mprj_io_dm[49] (mprj_io_dm[49]),\
+.\mprj_io_dm[50] (mprj_io_dm[50]),\
+.\mprj_io_dm[51] (mprj_io_dm[51]),\
+.\mprj_io_dm[52] (mprj_io_dm[52]),\
+.\mprj_io_dm[53] (mprj_io_dm[53]),\
+.\mprj_io_dm[54] (mprj_io_dm[54]),\
+.\mprj_io_dm[55] (mprj_io_dm[55]),\
+.\mprj_io_dm[56] (mprj_io_dm[56]),\
+.\mprj_io_dm[57] (mprj_io_dm[57]),\
+.\mprj_io_dm[58] (mprj_io_dm[58]),\
+.\mprj_io_dm[59] (mprj_io_dm[59]),\
+.\mprj_io_dm[60] (mprj_io_dm[60]),\
+.\mprj_io_dm[61] (mprj_io_dm[61]),\
+.\mprj_io_dm[62] (mprj_io_dm[62]),\
+.\mprj_io_dm[63] (mprj_io_dm[63]),\
+.\mprj_io_dm[64] (mprj_io_dm[64]),\
+.\mprj_io_dm[65] (mprj_io_dm[65]),\
+.\mprj_io_dm[66] (mprj_io_dm[66]),\
+.\mprj_io_dm[67] (mprj_io_dm[67]),\
+.\mprj_io_dm[68] (mprj_io_dm[68]),\
+.\mprj_io_dm[69] (mprj_io_dm[69]),\
+.\mprj_io_dm[70] (mprj_io_dm[70]),\
+.\mprj_io_dm[71] (mprj_io_dm[71]),\
+.\mprj_io_dm[72] (mprj_io_dm[72]),\
+.\mprj_io_dm[73] (mprj_io_dm[73]),\
+.\mprj_io_dm[74] (mprj_io_dm[74]),\
+.\mprj_io_dm[75] (mprj_io_dm[75]),\
+.\mprj_io_dm[76] (mprj_io_dm[76]),\
+.\mprj_io_dm[77] (mprj_io_dm[77]),\
+.\mprj_io_dm[78] (mprj_io_dm[78]),\
+.\mprj_io_dm[79] (mprj_io_dm[79]),\
+.\mprj_io_dm[80] (mprj_io_dm[80]),\
+.\mprj_io_dm[81] (mprj_io_dm[81]),\
+.\mprj_io_dm[82] (mprj_io_dm[82]),\
+.\mprj_io_dm[83] (mprj_io_dm[83]),\
+.\mprj_io_dm[84] (mprj_io_dm[84]),\
+.\mprj_io_dm[85] (mprj_io_dm[85]),\
+.\mprj_io_dm[86] (mprj_io_dm[86]),\
+.\mprj_io_dm[87] (mprj_io_dm[87]),\
+.\mprj_io_dm[88] (mprj_io_dm[88]),\
+.\mprj_io_dm[89] (mprj_io_dm[89]),\
+.\mprj_io_dm[90] (mprj_io_dm[90]),\
+.\mprj_io_dm[91] (mprj_io_dm[91]),\
+.\mprj_io_dm[92] (mprj_io_dm[92]),\
+.\mprj_io_dm[93] (mprj_io_dm[93]),\
+.\mprj_io_dm[94] (mprj_io_dm[94]),\
+.\mprj_io_dm[95] (mprj_io_dm[95]),\
+.\mprj_io_dm[96] (mprj_io_dm[96]),\
+.\mprj_io_dm[97] (mprj_io_dm[97]),\
+.\mprj_io_dm[98] (mprj_io_dm[98]),\
+.\mprj_io_dm[99] (mprj_io_dm[99]),\
+.\mprj_io_dm[100] (mprj_io_dm[100]),\
+.\mprj_io_dm[101] (mprj_io_dm[101]),\
+.\mprj_io_dm[102] (mprj_io_dm[102]),\
+.\mprj_io_dm[103] (mprj_io_dm[103]),\
+.\mprj_io_dm[104] (mprj_io_dm[104]),\
+.\mprj_io_dm[105] (mprj_io_dm[105]),\
+.\mprj_io_dm[106] (mprj_io_dm[106]),\
+.\mprj_io_dm[107] (mprj_io_dm[107]),\
+.\mprj_io_dm[108] (mprj_io_dm[108]),\
+.\mprj_io_dm[109] (mprj_io_dm[109]),\
+.\mprj_io_dm[110] (mprj_io_dm[110]),\
+.\mprj_io_dm[111] (mprj_io_dm[111]),\
+.\mprj_io_dm[112] (mprj_io_dm[112]),\
+.\mprj_io_dm[113] (mprj_io_dm[113])
+
+`define MPRJ_IO_ANALOG \
+.\mprj_analog_io[0] (mprj_analog_io[0]),\
+.\mprj_analog_io[1] (mprj_analog_io[1]),\
+.\mprj_analog_io[2] (mprj_analog_io[2]),\
+.\mprj_analog_io[3] (mprj_analog_io[3]),\
+.\mprj_analog_io[4] (mprj_analog_io[4]),\
+.\mprj_analog_io[5] (mprj_analog_io[5]),\
+.\mprj_analog_io[6] (mprj_analog_io[6]),\
+.\mprj_analog_io[7] (mprj_analog_io[7]),\
+.\mprj_analog_io[8] (mprj_analog_io[8]),\
+.\mprj_analog_io[9] (mprj_analog_io[9]),\
+.\mprj_analog_io[10] (mprj_analog_io[10]),\
+.\mprj_analog_io[11] (mprj_analog_io[11]),\
+.\mprj_analog_io[12] (mprj_analog_io[12]),\
+.\mprj_analog_io[13] (mprj_analog_io[13]),\
+.\mprj_analog_io[14] (mprj_analog_io[14]),\
+.\mprj_analog_io[15] (mprj_analog_io[15]),\
+.\mprj_analog_io[16] (mprj_analog_io[16]),\
+.\mprj_analog_io[17] (mprj_analog_io[17]),\
+.\mprj_analog_io[18] (mprj_analog_io[18]),\
+.\mprj_analog_io[19] (mprj_analog_io[19]),\
+.\mprj_analog_io[20] (mprj_analog_io[20]),\
+.\mprj_analog_io[21] (mprj_analog_io[21]),\
+.\mprj_analog_io[22] (mprj_analog_io[22]),\
+.\mprj_analog_io[23] (mprj_analog_io[23]),\
+.\mprj_analog_io[24] (mprj_analog_io[24]),\
+.\mprj_analog_io[25] (mprj_analog_io[25]),\
+.\mprj_analog_io[26] (mprj_analog_io[26]),\
+.\mprj_analog_io[27] (mprj_analog_io[27]),\
+.\mprj_analog_io[28] (mprj_analog_io[28]),\
+.\mprj_analog_io[29] (mprj_analog_io[29]),\
+.\mprj_analog_io[30] (mprj_analog_io[30])
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/gpio_wb/Makefile b/verilog/dv/wb_utests/gpio_wb/Makefile
new file mode 100644
index 0000000..a42f609
--- /dev/null
+++ b/verilog/dv/wb_utests/gpio_wb/Makefile

@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = gpio_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
new file mode 100644
index 0000000..ea6c772
--- /dev/null
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v

@@ -0,0 +1,199 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "gpio_wb.v"
+
+module gpio_wb_tb;
+
+    reg wb_clk_i;
+    reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+    reg wb_we_i;
+    reg [3:0] wb_sel_i;
+
+    reg [31:0] wb_dat_i;
+    reg [31:0] wb_adr_i;
+    reg gpio_in_pad;
+
+    wire wb_ack_o;
+    wire [31:0] wb_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0;  
+        gpio_in_pad = 0;
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("gpio_wb_tb.vcd");
+        $dumpvars(0, gpio_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test GPIO Wishbone Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // GPIO Internal Register Addresses
+    wire [31:0] gpio_adr     = uut.BASE_ADR | uut.GPIO_DATA;
+    wire [31:0] gpio_oeb_adr = uut.BASE_ADR | uut.GPIO_ENA;
+    wire [31:0] gpio_pu_adr  = uut.BASE_ADR | uut.GPIO_PU;
+    wire [31:0] gpio_pd_adr  = uut.BASE_ADR | uut.GPIO_PD;
+
+    reg gpio_data;
+    reg gpio_pu; 
+    reg gpio_pd; 
+    reg gpio_oeb;  
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to gpio_data reg
+        gpio_in_pad = 1'b1;
+        gpio_data = 1'b1;
+        write(gpio_adr, gpio_data);
+       
+        #2;
+        // Read from gpio_data reg
+        read(gpio_adr);
+        if (wb_dat_o !== {30'd0, gpio_data, gpio_in_pad}) begin
+            $display("Monitor: Error reading from gpio reg");
+            $finish;
+        end
+        
+        #2;
+        // Write to pull-up reg
+        gpio_pu = 1'b1;
+        write(gpio_pu_adr, gpio_pu);
+        
+        #2;
+        // Read from pull-up reg
+        read(gpio_pu_adr);
+        if (wb_dat_o !== {31'd0, gpio_pu}) begin
+            $display("Monitor: Error reading from gpio pull-up reg");
+            $finish;
+        end
+
+        #2;
+        // Write to pull-down reg
+        gpio_pd = 1'b1;
+        write(gpio_pd_adr, gpio_pd);
+        
+        #2;
+        // Read from pull-down reg
+        read(gpio_pd_adr);
+        if (wb_dat_o !== {31'd0, gpio_pd}) begin
+            $display("Monitor: Error reading from gpio pull-down reg");
+            $finish;
+        end
+
+        #2;
+        // Write to gpio enable reg
+        gpio_oeb = 1'b1;
+        write(gpio_oeb_adr, gpio_oeb);
+        
+        #2;
+        // Read from gpio enable reg
+        read(gpio_oeb_adr);
+        if (wb_dat_o !== {31'd0, gpio_oeb}) begin
+            $display("Monitor: Error reading from gpio output enable reg");
+            $finish;
+        end
+        
+        #6;
+        $display("Monitor: GPIO WB Success!");
+        $display("Monitor: GPIO WB Passed!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+    
+    gpio_wb uut(
+        .wb_clk_i(wb_clk_i),
+	.wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	.wb_cyc_i(wb_cyc_i),
+	.wb_sel_i(wb_sel_i),
+	.wb_we_i(wb_we_i),
+	.wb_dat_i(wb_dat_i),
+	.wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	.wb_dat_o(wb_dat_o),
+        .gpio_in_pad(gpio_in_pad)
+    );
+    
+endmodule

diff --git a/verilog/dv/wb_utests/intercon_wb/Makefile b/verilog/dv/wb_utests/intercon_wb/Makefile
new file mode 100644
index 0000000..294cf17
--- /dev/null
+++ b/verilog/dv/wb_utests/intercon_wb/Makefile

@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = intercon_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../ -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
new file mode 100644
index 0000000..4f6fd38
--- /dev/null
+++ b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v

@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "wb_intercon.v"
+`include "dummy_slave.v"
+
+`define AW 32
+`define DW 32
+`define NS 6
+
+`define SLAVE_ADR { \
+    {8'h28, {24{1'b0}} }, \   
+    {8'h23, {24{1'b0}} }, \     
+    {8'h21, {24{1'b0}} }, \    
+    {8'h20, {24{1'b0}} }, \    
+    {8'h10, {24{1'b0}} }, \    
+    {8'h00, {24{1'b0}} }  \
+}\
+
+`define ADR_MASK { \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }, \
+    {8'hFF, {24{1'b0}} }  \
+}\
+
+module intercon_wb_tb;
+
+    localparam SEL = `DW / 8;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    // Master Interface
+    reg wbm_stb_i;
+    reg wbm_cyc_i;
+    reg wbm_we_i;
+    reg [SEL-1:0] wbm_sel_i;
+    reg [`AW-1:0] wbm_adr_i;
+    reg [`DW-1:0] wbm_dat_i;
+
+    wire [`DW-1:0] wbm_dat_o;
+    wire wbm_ack_o;
+
+    // Wishbone Slave Interface
+    wire [`NS-1:0] wbs_stb_i;
+    wire [`NS-1:0] wbs_ack_o;
+    wire [(`NS*`DW)-1:0] wbs_adr_i;
+    wire [(`NS*`AW)-1:0] wbs_dat_i;
+    wire [(`NS*`DW)-1:0] wbs_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wbm_adr_i = 0;  
+        wbm_dat_i = 0;  
+        wbm_sel_i = 0;   
+        wbm_we_i  = 0;    
+        wbm_cyc_i = 0;   
+        wbm_stb_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("intercon_wb_tb.vcd");
+        $dumpvars(0, intercon_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone Interconnect Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [`AW*`NS-1: 0] addr = `SLAVE_ADR;
+    reg [`DW:0] slave_data;
+    reg [`AW:0] slave_addr;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // W/R from all slaves
+        for (i=0; i<`NS; i=i+1) begin
+            slave_addr = addr[i*`AW +: `AW];
+            slave_data = $urandom_range(0, 2**32);
+            write(slave_addr, slave_data);
+            #2;
+            read(slave_addr);
+            if (wbm_dat_o !== slave_data) begin
+                $display("%c[1;31m",27);
+                $display ("Monitor: Reading from slave %0d failed", i);
+                $display("Monitor: Test Wishbone Interconnect failed");
+                $display("%c[0m",27);
+                $finish;
+            end
+        end
+        $display("Monitor: Test Wishbone Interconnect Success!");
+        $display("Monitor: Test Wishbone Interconnect Passed!");
+        $finish;
+    end
+    
+    task write;
+        input [`AW-1:0] addr;
+        input [`AW-1:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_sel_i = {SEL{1'b1}}; 
+                wbm_we_i = 1;    
+                wbm_adr_i = addr;
+                wbm_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wbm_ack_o == 1);
+            wait(wbm_ack_o == 0);
+            wbm_cyc_i = 0;
+            wbm_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [`AW-1:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wbm_stb_i = 1;
+                wbm_cyc_i = 1;
+                wbm_adr_i = addr;
+                wbm_we_i =  0;     
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wbm_ack_o == 1);
+            wait(wbm_ack_o == 0);
+            wbm_cyc_i = 0;
+            wbm_stb_i = 0;
+            $display("Read Cycle Ended.");
+        
+        end
+    endtask
+
+    wb_intercon #(
+        .AW(`AW),
+        .DW(`DW),
+        .NS(`NS),
+        .ADR_MASK(`ADR_MASK),
+        .SLAVE_ADR(`SLAVE_ADR)
+    ) uut(
+        // Master Interface
+        .wbm_adr_i(wbm_adr_i),
+        .wbm_stb_i(wbm_stb_i),
+        .wbm_dat_o(wbm_dat_o),
+        .wbm_ack_o(wbm_ack_o), 
+    
+        // Slave Interface
+        .wbs_stb_o(wbs_stb_i),
+        .wbs_dat_i(wbs_dat_o), 
+        .wbs_ack_i(wbs_ack_o)
+    );
+    
+    // Instantiate five dummy slaves for testing
+    dummy_slave dummy_slaves [`NS-1:0](
+        .wb_clk_i({`NS{wb_clk_i}}),
+        .wb_rst_i({`NS{wb_rst_i}}),
+        .wb_stb_i(wbs_stb_i),
+        .wb_cyc_i(wbm_cyc_i),
+        .wb_we_i(wbm_we_i),
+        .wb_sel_i(wbm_sel_i),
+        .wb_adr_i(wbm_adr_i),
+        .wb_dat_i(wbm_dat_i),
+        .wb_dat_o(wbs_dat_o),
+        .wb_ack_o(wbs_ack_o)
+    );
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/la_wb/Makefile b/verilog/dv/wb_utests/la_wb/Makefile
new file mode 100644
index 0000000..1b76d6b
--- /dev/null
+++ b/verilog/dv/wb_utests/la_wb/Makefile

@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = la_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
new file mode 100644
index 0000000..a1c10ab
--- /dev/null
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v

@@ -0,0 +1,271 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+`include "la_wb.v"
+
+module la_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+    wire [127:0] la_data; 
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+    
+    initial begin
+        $dumpfile("la_wb_tb.vcd");
+        $dumpvars(0, la_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone LA Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // LA Wishbone Internal Register Addresses
+    wire [31:0] la_data_adr_0   = uut.BASE_ADR | uut.LA_DATA_0;
+    wire [31:0] la_data_adr_1   = uut.BASE_ADR | uut.LA_DATA_1;
+    wire [31:0] la_data_adr_2   = uut.BASE_ADR | uut.LA_DATA_2;
+    wire [31:0] la_data_adr_3   = uut.BASE_ADR | uut.LA_DATA_3;
+    
+    wire [31:0] la_iena_adr_0 = uut.BASE_ADR | uut.LA_IENA_0;
+    wire [31:0] la_iena_adr_1 = uut.BASE_ADR | uut.LA_IENA_1;
+    wire [31:0] la_iena_adr_2 = uut.BASE_ADR | uut.LA_IENA_2;
+    wire [31:0] la_iena_adr_3 = uut.BASE_ADR | uut.LA_IENA_3;
+
+    wire [31:0] la_oenb_adr_0 = uut.BASE_ADR | uut.LA_OENB_0;
+    wire [31:0] la_oenb_adr_1 = uut.BASE_ADR | uut.LA_OENB_1;
+    wire [31:0] la_oenb_adr_2 = uut.BASE_ADR | uut.LA_OENB_2;
+    wire [31:0] la_oenb_adr_3 = uut.BASE_ADR | uut.LA_OENB_3;
+
+    reg [31:0] la_data_0;
+    reg [31:0] la_data_1; 
+    reg [31:0] la_data_2;
+    reg [31:0] la_data_3; 
+
+    reg [31:0] la_iena_0;
+    reg [31:0] la_iena_1; 
+    reg [31:0] la_iena_2;
+    reg [31:0] la_iena_3; 
+
+    reg [31:0] la_oenb_0;
+    reg [31:0] la_oenb_1; 
+    reg [31:0] la_oenb_2;
+    reg [31:0] la_oenb_3; 
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to la input enable registers
+        la_iena_0 = 32'hF0F0_F0F0;
+        la_iena_1 = 32'hA0A0_A0A0;
+        la_iena_2 = 32'hB0B0_B0B0;
+        la_iena_3 = 32'hC0C0_C0C0;
+
+        write(la_iena_adr_0, la_iena_0);
+        write(la_iena_adr_1, la_iena_1);
+        write(la_iena_adr_2, la_iena_2);
+        write(la_iena_adr_3, la_iena_3);
+
+        #2;
+        // Read from la input enable registers
+        read(la_iena_adr_0);
+        if (wb_dat_o !== la_iena_0) begin
+            $display("Monitor: Error reading from la_iena_0 reg");
+            $finish;
+        end
+        
+        read(la_iena_adr_1);
+        if (wb_dat_o !== la_iena_1) begin
+            $display("Monitor: Error reading from la_iena_1 reg");
+            $finish;
+        end
+        
+        read(la_iena_adr_2);
+        if (wb_dat_o !== la_iena_2) begin
+            $display("Monitor: Error reading from la_iena_2 reg");
+            $finish;
+        end
+
+        read(la_iena_adr_3);
+        if (wb_dat_o !== la_iena_3) begin
+            $display("Monitor: Error reading from la_iena_3 reg");
+            $finish;
+        end
+
+        // Write to la output enable registers
+        la_oenb_0 = 32'hC00C_0CC0;
+        la_oenb_1 = 32'hD00D_0DD0;
+        la_oenb_2 = 32'h0FF0_0FF0;
+        la_oenb_3 = 32'hA00A_A00A;
+
+        write(la_oenb_adr_0, la_oenb_0);
+        write(la_oenb_adr_1, la_oenb_1);
+        write(la_oenb_adr_2, la_oenb_2);
+        write(la_oenb_adr_3, la_oenb_3);
+
+        #2;
+        // Read from la output enable registers
+        read(la_oenb_adr_0);
+        if (wb_dat_o !== la_oenb_0) begin
+            $display("Monitor: Error reading from la_oenb_0 reg");
+            $finish;
+        end
+        
+        read(la_oenb_adr_1);
+        if (wb_dat_o !== la_oenb_1) begin
+            $display("Monitor: Error reading from la_oenb_1 reg");
+            $finish;
+        end
+        
+        read(la_oenb_adr_2);
+        if (wb_dat_o !== la_oenb_2) begin
+            $display("Monitor: Error reading from la_oenb_2 reg");
+            $finish;
+        end
+
+        read(la_oenb_adr_3);
+        if (wb_dat_o !== la_oenb_3) begin
+            $display("Monitor: Error reading from la_oenb_3 reg");
+            $finish;
+        end
+
+        // Write to la data registers
+        la_data_0 = $urandom_range(0, 2**30);
+        la_data_1 = $urandom_range(0, 2**30);
+        la_data_2 = $urandom_range(0, 2**30);
+        la_data_3 = $urandom_range(0, 2**30);
+
+        write(la_data_adr_0, la_data_0);
+        write(la_data_adr_1, la_data_1);
+        write(la_data_adr_2, la_data_2);
+        write(la_data_adr_3, la_data_3);
+
+        // #2;
+        // Read from la data registers
+        #25;  
+        if (la_data[31:0] !== la_data_0) begin
+            $display("Monitor: Error reading from la data_0 reg");
+            $finish;
+        end
+        
+        if (la_data[63:32] !== la_data_1) begin
+            $display("Monitor: Error reading from la data_1 reg");
+            $finish;
+        end
+        
+        if (la_data[95:64] !== la_data_2) begin
+            $display("Monitor: Error reading from la data_2 reg");
+            $finish;
+        end
+
+        if (la_data[127:96] !== la_data_3) begin
+            $display("Monitor: Error reading from la data_3 reg");
+            $finish;
+        end
+        #6;
+        $display("Monitor: Test LA Wishbone Success!");
+        $display("Monitor: Test LA Wishbone Passed!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+
+    la_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        .la_data(la_data)
+    );
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile
new file mode 100644
index 0000000..dc0ed9e
--- /dev/null
+++ b/verilog/dv/wb_utests/mem_wb/Makefile

@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mem_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
new file mode 100644
index 0000000..28f3e0c
--- /dev/null
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v

@@ -0,0 +1,190 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+    `include "gl/DFFRAM.v"
+`else 
+    `include "DFFRAMBB.v"
+    `include "DFFRAM.v"
+`endif
+
+`include "mem_wb.v"
+
+module mem_wb_tb;
+
+    reg wb_clk_i;
+    reg wb_rst_i;
+
+    reg [31:0] wb_adr_i;
+    reg [31:0] wb_dat_i;
+    reg [3:0]  wb_sel_i;
+    reg wb_we_i;
+    reg wb_cyc_i;
+    reg wb_stb_i;
+
+    wire wb_ack_o;
+    wire [31:0] wb_dat_o;
+    reg power1;
+
+    initial begin
+        wb_clk_i = 0;
+        wb_rst_i = 0;
+
+        wb_stb_i = 0;  // master select-signal for the slave
+        wb_we_i  = 0;  // R = 0 , W = 1
+        wb_cyc_i = 0;  // master is transferring
+        wb_adr_i = 0;  // input addr 32-bits
+        wb_dat_i = 0;  // input data 32-bits
+        wb_sel_i = 0;  // where data is available on data_i 4-bits
+    end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		#1;
+		power1 <= 1'b1;
+	end
+
+    wire VPWR;
+	wire VGND;
+	assign VGND = 1'b0;
+	assign VPWR = power1;
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("mem_wb_tb.vcd");
+        $dumpvars(0, mem_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Wishbone Memory Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [31:0] ref_data [255: 0];
+    reg [31: 0] read_data;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+
+        // Randomly Write to memory array
+        for ( i = 0; i < 1; i = i + 1) begin
+            ref_data[i] = $urandom_range(0, 2**30);
+            write(i, ref_data[i]);
+            #2;
+        end
+
+        #6;
+        for ( i = 0; i < 1; i = i + 1) begin
+            read(i);
+            if (wb_dat_o !== ref_data[i]) begin
+                $display("%c[1;31m",27);
+                $display("Expected %0b, but Got %0b ", ref_data[i], wb_dat_o);
+                $display("Monitor: Wishbone Memory Failed");
+                $display("%c[0m",27);
+                $finish;
+            end
+            #2;
+        end
+        #6;
+        $display("Success!");
+        $display ("Monitor: Test Wishbone Memory Passed");
+        $finish;
+    end
+
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF;
+                wb_we_i = 1;
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+
+    task read;
+        input [32:0] addr;
+        begin
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+
+    mem_wb uut(
+        `ifdef USE_POWER_PINS
+            .VPWR(VPWR),
+            .VGND(VGND),
+        `endif
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+
+        .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i),
+        .wb_sel_i(wb_sel_i),
+        .wb_we_i(wb_we_i),
+        .wb_cyc_i(wb_cyc_i),
+        .wb_stb_i(wb_stb_i),
+
+        .wb_ack_o(wb_ack_o),
+        .wb_dat_o(wb_dat_o)
+    );
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/mgmt_protect/Makefile b/verilog/dv/wb_utests/mgmt_protect/Makefile
new file mode 100644
index 0000000..7dd7866
--- /dev/null
+++ b/verilog/dv/wb_utests/mgmt_protect/Makefile

@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A 
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM ?= RTL
+
+.SUFFIXES:
+
+PATTERN = mgmt_protect
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+	rm -f *.vvp *.vcd
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
new file mode 100644
index 0000000..accae33
--- /dev/null
+++ b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v

@@ -0,0 +1,263 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS
+`define SIM_TIME 100_000
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+
+`include "defines.v"
+
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+    `include "gl/mprj_logic_high.v"
+    `include "gl/mprj2_logic_high.v"
+    `include "gl/mgmt_protect.v"
+    `include "gl/mgmt_protect_hv.v"
+`else
+    `include "mprj_logic_high.v"
+    `include "mprj2_logic_high.v"
+    `include "mgmt_protect.v"
+    `include "mgmt_protect_hv.v"
+`endif 
+
+module mgmt_protect_tb;
+
+    reg caravel_clk;
+    reg caravel_clk2;
+    reg caravel_rstn;
+
+    reg mprj_cyc_o_core;
+    reg mprj_stb_o_core;
+    reg mprj_we_o_core;
+    reg [31:0] mprj_adr_o_core;
+    reg [31:0] mprj_dat_o_core;
+    reg [3:0]  mprj_sel_o_core;
+
+    wire [127:0] la_data_in_mprj;
+    reg  [127:0] la_data_out_mprj;
+    reg  [127:0] la_oenb_mprj;
+    reg  [127:0] la_iena_mprj;
+
+    reg  [127:0] la_data_out_core;
+    wire [127:0] la_data_in_core;
+    wire [127:0] la_oenb_core;
+
+    wire 	  user_clock;
+    wire 	  user_clock2;
+    wire 	  user_reset;
+    wire 	  mprj_cyc_o_user;
+    wire 	  mprj_stb_o_user;
+    wire 	  mprj_we_o_user;
+    wire [3:0]  mprj_sel_o_user;
+    wire [31:0] mprj_adr_o_user;
+    wire [31:0] mprj_dat_o_user;
+    wire	  user1_vcc_powergood;
+    wire	  user2_vcc_powergood;
+    wire	  user1_vdd_powergood;
+    wire	  user2_vdd_powergood;
+
+    always #12.5 caravel_clk  <= (caravel_clk === 1'b0);
+	always #12.5 caravel_clk2 <= (caravel_clk2 === 1'b0);
+
+    initial begin
+        caravel_clk  = 0;
+        caravel_clk2 = 0;
+        caravel_rstn = 0;
+
+        mprj_cyc_o_core = 0;
+        mprj_stb_o_core = 0;
+        mprj_we_o_core  = 0;
+        mprj_adr_o_core = 0;
+        mprj_dat_o_core = 0;
+        mprj_sel_o_core = 0;
+
+        la_data_out_mprj = 0;
+        la_oenb_mprj      = 0;
+        la_data_out_core = 0;
+    end
+
+    reg USER_VDD3V3;
+    reg USER_VDD1V8;
+    reg VDD3V3;
+    reg VDD1V8;
+    
+    wire VCCD;      // Management/Common 1.8V power
+    wire VSSD;      // Common digital ground
+  
+    wire VCCD1;     // User area 1 1.8V power
+	wire VSSD1;     // User area 1 digital ground
+	wire VCCD2;     // User area 2 1.8V power
+	wire VSSD2;     // User area 2 digital ground
+
+	wire VDDA1;     // User area 1 3.3V power
+	wire VSSA1;     // User area 1 analog ground
+    wire VDDA2; 	// User area 2 3.3V power
+	wire VSSA2;     // User area 2 analog ground
+
+    assign VCCD = VDD1V8;
+	assign VSSD  = 1'b0;
+
+    assign VCCD1 = USER_VDD1V8;
+	assign VSSD1 = 1'b0;
+    
+    assign VCCD2 = USER_VDD1V8;
+	assign VSSD2 = 1'b0;
+
+    assign VDDA1 = USER_VDD3V3;
+	assign VSSA1 = 1'b0;
+
+    assign VDDA2 = USER_VDD3V3;
+	assign VSSA2 = 1'b0;
+
+	initial begin	// Power-up sequence
+        VDD1V8      <= 1'b0;
+		USER_VDD3V3 <= 1'b0;
+		USER_VDD1V8 <= 1'b0;
+		#200;
+		VDD1V8 <= 1'b1;
+		#200;
+        USER_VDD3V3 <= 1'b1;
+		#200;
+    	USER_VDD1V8 <= 1'b1;
+	end
+
+    initial begin
+        $dumpfile("mgmt_protect.vcd");
+        $dumpvars(0, mgmt_protect_tb);
+        #(`SIM_TIME);
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Management Protect Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    initial begin
+        caravel_rstn = 1'b1;
+        mprj_cyc_o_core = 1'b1;
+        mprj_stb_o_core = 1'b1;
+        mprj_we_o_core = 1'b1;
+        mprj_sel_o_core = 4'b1010;
+        mprj_adr_o_core = 32'hF0F0;
+        mprj_dat_o_core = 32'h0F0F;
+        la_data_out_mprj = 128'hFFFF_FFFF_FFFF_FFFF;
+        la_oenb_mprj = 128'h0000_0000_0000_0000;
+        la_data_out_core = 128'h0F0F_FFFF_F0F0_FFFF;
+        la_iena_mprj  = 128'hFFFF_FFFF_FFFF_FFFF;
+
+        wait(user1_vdd_powergood === 1'b1);
+        wait(user2_vdd_powergood === 1'b1);
+        wait(user1_vcc_powergood === 1'b1);
+        wait(user2_vcc_powergood === 1'b1);
+        #25;
+        if (user_reset !== ~caravel_rstn) begin 
+            $display("Monitor: Error on user_reset. "); $finish; 
+        end
+        if (mprj_cyc_o_user !== mprj_cyc_o_core) begin 
+            $display("Monitor: Error on mprj_cyc_o_user. "); $finish; 
+        end
+        if (mprj_stb_o_user !== mprj_stb_o_core) begin 
+            $display("Monitor: Error on mprj_stb_o_user. "); $finish; 
+        end
+        if (mprj_we_o_user !== mprj_we_o_core) begin 
+            $display("Monitor: Error on mprj_we_o_user. "); $finish;
+        end
+        if (mprj_sel_o_user !== mprj_sel_o_core) begin 
+            $display("Monitor: Error on mprj_sel_o_user. "); $finish; 
+        end
+        if (mprj_adr_o_user !== mprj_adr_o_core) begin 
+            $display("Monitor: Error on mprj_adr_o_user. "); $finish;
+        end
+        if (la_data_in_core !== la_data_out_mprj) begin 
+            $display("%0h", la_data_in_core);
+            $display("Monitor: Error on la_data_in_core. "); $finish;
+        end
+        if (la_oenb_core !== la_oenb_mprj) begin 
+            $display("Monitor: Error on la_oenb_core. "); $finish;
+        end
+        if (la_data_in_mprj !== la_data_out_core) begin 
+            $display("%0h , %0h", la_data_in_mprj, la_data_out_core);
+            $display("Monitor: Error on la_data_in_mprj. "); $finish;
+        end
+        $display ("Success!");
+        $display ("Monitor: Test Management Protect Passed");
+        $finish;
+    end
+
+    mgmt_protect uut (
+	`ifdef USE_POWER_PINS
+		.vccd(VCCD),
+		.vssd(VSSD),
+		.vccd1(VCCD1),
+		.vssd1(VSSD1),
+        .vccd2(VCCD2),
+		.vssd2(VSSD2),
+		.vdda1(VDDA1),
+		.vssa1(VSSA1),
+		.vdda2(VDDA2),
+		.vssa2(VSSA2),
+    `endif
+
+		.caravel_clk (caravel_clk),
+		.caravel_clk2(caravel_clk2),
+		.caravel_rstn(caravel_rstn),
+
+		.mprj_cyc_o_core(mprj_cyc_o_core),
+		.mprj_stb_o_core(mprj_stb_o_core),
+		.mprj_we_o_core (mprj_we_o_core),
+		.mprj_sel_o_core(mprj_sel_o_core),
+		.mprj_adr_o_core(mprj_adr_o_core),
+		.mprj_dat_o_core(mprj_dat_o_core),
+
+		.la_data_out_core(la_data_out_core),
+		.la_data_in_core (la_data_in_core),
+		.la_oenb_core(la_oenb_core),
+
+        .la_data_in_mprj(la_data_in_mprj),
+    	.la_data_out_mprj(la_data_out_mprj),
+    	.la_oenb_mprj(la_oenb_mprj),
+        .la_iena_mprj(la_iena_mprj),
+
+		.user_clock (user_clock),
+		.user_clock2(user_clock2),
+		.user_reset (user_reset),
+
+		.mprj_cyc_o_user(mprj_cyc_o_user),
+		.mprj_stb_o_user(mprj_stb_o_user),
+		.mprj_we_o_user (mprj_we_o_user),
+		.mprj_sel_o_user(mprj_sel_o_user),
+		.mprj_adr_o_user(mprj_adr_o_user),
+		.mprj_dat_o_user(mprj_dat_o_user),
+
+		.user1_vcc_powergood(user1_vcc_powergood),
+		.user2_vcc_powergood(user2_vcc_powergood),
+		.user1_vdd_powergood(user1_vdd_powergood),
+		.user2_vdd_powergood(user2_vdd_powergood)
+	);
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/mprj_ctrl/Makefile b/verilog/dv/wb_utests/mprj_ctrl/Makefile
new file mode 100644
index 0000000..f354018
--- /dev/null
+++ b/verilog/dv/wb_utests/mprj_ctrl/Makefile

@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = mprj_ctrl
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
new file mode 100644
index 0000000..fd9e5a2
--- /dev/null
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v

@@ -0,0 +1,159 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+`include "mprj_ctrl.v"
+
+module mprj_ctrl_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    // Mega Project Control Registers 
+    wire [31:0] mprj_ctrl = uut.BASE_ADR | uut.IOCONFIG;
+    wire [31:0] pwr_ctrl  = uut.BASE_ADR | uut.PWRDATA;
+
+    initial begin
+        $dumpfile("mprj_ctrl_tb.vcd");
+        $dumpvars(0, mprj_ctrl_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Mega-Project Control Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    reg [31:0] data;
+
+    initial begin   
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+
+        for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
+            data = $urandom_range(0, 2**(7));
+            write(mprj_ctrl+i*4, data);
+            #2;
+            read(mprj_ctrl+i*4);
+            if (wb_dat_o !== data) begin
+                $display("Monitor: R/W from IO-CTRL Failed.");
+                $finish;
+            end
+        end
+
+        data = $urandom_range(0, 2**(`MPRJ_PWR_PADS-2));
+        write(pwr_ctrl, data);
+        #2;
+        read(pwr_ctrl);
+        if (wb_dat_o !== data) begin
+            $display("Monitor: R/W from POWER-CTRL Failed.");
+            $finish;
+        end
+    
+        
+        $display("Success!");
+        $display ("Monitor: Test Mega-Project Control Passed");
+        $finish;
+    end
+
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+
+    mprj_ctrl_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o)
+    );
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile b/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
new file mode 100644
index 0000000..8bf03c7
--- /dev/null
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile

@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spi_sysctrl_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+

diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
new file mode 100644
index 0000000..99cb008
--- /dev/null
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v

@@ -0,0 +1,157 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simple_spi_master.v"
+
+module spi_sysctrl_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    reg [31:0] spi_cfg_data;
+    reg [31:0] spi_data;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    // SPI Control Register Addresses
+    wire [31:0] spi_cfg  = uut.BASE_ADR | uut.CONFIG; 
+    wire [31:0] spi_data_adr = uut.BASE_ADR | uut.DATA;
+
+    initial begin
+        $dumpfile("spi_sysctrl_wb_tb.vcd");
+        $dumpvars(0, spi_sysctrl_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test SPI System Control Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    initial begin   
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #10;
+
+        // Write to SPI_CFG
+        spi_cfg_data = {16'd0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0,
+            1'b0, 1'b0, 1'b0, 8'd2};
+        write(spi_cfg, spi_cfg_data);
+
+        #2;
+        // Read from SPI_CFG
+        read(spi_cfg);
+        if (wb_dat_o !== spi_cfg_data) begin
+            $display("Error reading spi_cfg reg");
+            $finish;
+        end
+
+        // Read default value of SPI_DATA
+        spi_data = 32'h00FF;
+        read(spi_data_adr);
+        if (wb_dat_o !== spi_data) begin
+            $display("Error reading data register reg");
+            $finish;
+        end
+        $display("Success!");
+        $display ("Monitor: Test SPI-SYSCTRL WB Passed");
+        $finish;
+    end
+
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Monitor: Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            wb_adr_i = 0;
+            $display("Monitor: Read Cycle Ended.");
+        end
+    endtask
+
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            wb_adr_i = 0;
+            wait(wb_ack_o == 0);
+            $display("Write Cycle Ended.");
+        end
+    endtask
+
+    simple_spi_master_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o)
+    );
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/spimemio_wb/Makefile b/verilog/dv/wb_utests/spimemio_wb/Makefile
new file mode 100644
index 0000000..d145f04
--- /dev/null
+++ b/verilog/dv/wb_utests/spimemio_wb/Makefile

@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = spimemio_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I ../ -I ../../  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+

diff --git a/verilog/dv/wb_utests/spimemio_wb/flash.hex b/verilog/dv/wb_utests/spimemio_wb/flash.hex
new file mode 100644
index 0000000..23bd76d
--- /dev/null
+++ b/verilog/dv/wb_utests/spimemio_wb/flash.hex

@@ -0,0 +1,6 @@
+@10000000
+a1
+b1
+c1
+d1
+f1
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
new file mode 100644
index 0000000..c474fd0
--- /dev/null
+++ b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v

@@ -0,0 +1,234 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`define FLASH_BASE  32'h 1000_000
+
+`include "spimemio.v"
+// `include "spiflash.v"
+
+module spimemio_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_flash_stb_i;
+	reg wb_cfg_stb_i;
+	reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0]  wb_sel_i;
+	reg [31:0] wb_adr_i;
+	reg [31:0] wb_dat_i;
+
+	wire wb_flash_ack_o;
+    wire wb_cfg_ack_o;
+	wire [31:0] wb_flash_dat_o;
+	wire [31:0] wb_cfg_dat_o;
+
+    wire flash_csb;
+    wire flash_clk;
+
+    wire flash_io0_oeb;
+    wire flash_io1_oeb;
+    wire flash_io2_oeb;
+    wire flash_io3_oeb;
+
+    wire flash_io0_di = 1'b 1;
+    wire flash_io1_di = 1'b 1;
+    wire flash_io2_di = 1'b 1;
+    wire flash_io3_di = 1'b 1;
+
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_flash_stb_i = 0;  
+        wb_cfg_stb_i = 0; 
+        wb_cyc_i = 0;   
+        wb_we_i  = 0;
+        wb_sel_i = 0;    
+        wb_adr_i = 0;  
+        wb_dat_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    spimemio_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        
+        .wb_flash_stb_i(wb_flash_stb_i),
+	    .wb_cfg_stb_i(wb_cfg_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+    	.wb_we_i(wb_we_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_adr_i(wb_adr_i), 
+	    .wb_dat_i(wb_dat_i),
+	    .wb_flash_ack_o(wb_flash_ack_o),
+        .wb_cfg_ack_o(wb_cfg_ack_o),
+	    .wb_flash_dat_o(wb_flash_dat_o),
+	    .wb_cfg_dat_o(wb_cfg_dat_o),
+
+        .flash_clk(flash_clk),
+        .flash_csb(flash_csb),
+
+        .flash_io0_oeb(flash_io0_oeb),
+        .flash_io1_oeb(flash_io1_oeb),
+        .flash_io2_oeb(flash_io2_oeb),
+        .flash_io3_oeb(flash_io3_oeb),
+
+        .flash_io0_di(flash_io0_di),
+        .flash_io1_di(flash_io1_di),
+	    .flash_io2_di(flash_io2_di),
+	    .flash_io3_di(flash_io3_di)       
+    );
+
+    initial begin
+        $dumpfile("spimemio_wb_tb.vcd");
+        $dumpvars(0, spimemio_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test spimmemio Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+        
+    wire [31:0] cfgreg_data;
+    assign cfgreg_data = {
+        1'b 1,
+        8'b 0,
+        3'b 111,
+        4'b 1010,
+        4'b 0,             // make sure is it tied to zero in the module itself
+        {~flash_io3_oeb, ~flash_io2_oeb, ~flash_io1_oeb, ~flash_io0_oeb},
+        2'b 0,
+        flash_csb,
+        flash_clk,
+        {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}
+    };
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Read from flash
+        for (i = `FLASH_BASE; i < `FLASH_BASE + 100 ; i = i + 4) begin
+            read(i, 1, 0);
+            if (wb_flash_dat_o !== 32'hFFFF_FFFF) begin
+                $display("%c[1;31m",27);
+                $display("Expected %0b, but Got %0b ",  32'hFFFF_FFFF, wb_flash_dat_o);
+                $display("Monitor: Wishbone spimemio Failed");
+            	$display("%c[0m",27);
+                $finish;
+            end
+            #2;
+        end 
+
+        #6;
+        // Write to Configuration register
+        write(cfgreg_data, 0);
+        #2;
+        read(0, 0, 1);
+        if (wb_cfg_dat_o !== cfgreg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ",  cfgreg_data, wb_cfg_dat_o);
+            $display("Monitor: Wishbone spimemio Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        
+        $display("Success!");
+        $display("Monitor: Wishbone spimemio Passed");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] data;
+        input [31:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_cfg_stb_i = 1'b 1;
+                wb_flash_stb_i = 1'b 0;
+                wb_cyc_i = 1'b 1;
+                wb_sel_i = 4'b 1111; // complete word
+                wb_we_i = 1'b 1;     // write enable
+                wb_adr_i = addr;
+                wb_dat_i = data;
+            end
+
+            wait_ack();
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        input flash_stb;
+        input cfg_stb;
+        begin 
+            wb_flash_stb_i = flash_stb;
+            wb_cfg_stb_i = cfg_stb;
+
+            wb_cyc_i = 1'b 1;
+            wb_adr_i = addr;
+            wb_dat_i = 24;
+            wb_sel_i = 4'b 1111; // complete word
+            wb_we_i = 1'b 0;     // read
+            $display("Initiated Read transaction...");
+            wait_ack();
+        end
+    endtask
+
+    task wait_ack;
+        // Wait for an ACK
+        if (wb_cfg_stb_i == 1) begin
+            @(posedge wb_cfg_ack_o) begin
+                #2;  // To end the transaction on the falling edge of ack 
+                wb_cyc_i = 1'b 0;
+                wb_cfg_stb_i = 1'b 0;
+                $display("Monitor: Received an ACK from slave");
+            end
+        end
+        else begin
+            @(posedge wb_flash_ack_o) begin
+                #2;  // To end the transaction on the falling edge of ack 
+                wb_cyc_i = 1'b 0;
+                wb_flash_stb_i = 1'b 0;
+                $display("Monitor: Received an ACK from slave");
+            end
+        end
+    endtask
+
+    // spiflash #(
+	// 	.FILENAME("flash.hex")
+	// ) spiflash (
+	// 	.csb(flash_csb),
+	// 	.clk(flash_clk),
+	// 	.io0(flash_io0),
+	// 	.io1(flash_io1),
+	// 	.io2(flash_io2),
+	// 	.io3(flash_io3)
+	// );
+    
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/storage_wb/Makefile b/verilog/dv/wb_utests/storage_wb/Makefile
new file mode 100644
index 0000000..6b04de9
--- /dev/null
+++ b/verilog/dv/wb_utests/storage_wb/Makefile

@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+PDK_PATH?=$(PDK_ROOT)/sky130A
+VERILOG_PATH = ../../../
+RTL_PATH = $(VERILOG_PATH)/rtl
+
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = storage_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+	iverilog -Ttyp -DFUNCTIONAL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+else
+	iverilog -Ttyp -DFUNCTIONAL -DGL -I $(PDK_PATH) -I $(VERILOG_PATH) -I .. -I $(RTL_PATH) \
+	$< -o $@
+endif
+
+%.vcd: %.vvp check-env
+	vvp $<
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
new file mode 100644
index 0000000..71a84df
--- /dev/null
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v

@@ -0,0 +1,257 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// `define DBG
+
+`define STORAGE_BASE_ADR  32'h0100_0000
+
+`define UNIT_DELAY #1
+`define USE_POWER_PINS 
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+
+`include "defines.v"
+`include "sram_1rw1r_32_256_8_sky130.v"
+
+`ifdef GL
+    `include "gl/storage.v"
+`else
+    `include "storage.v"
+`endif
+
+`include "storage_bridge_wb.v"
+
+module storage_tb;
+
+    localparam [(`RAM_BLOCKS*24)-1:0] STORAGE_RW_ADR = {
+        {24'h 10_0000},
+        {24'h 00_0000}
+    };
+
+    localparam [23:0] STORAGE_RO_ADR = {
+        {24'h 20_0000}
+    };
+
+    reg wb_clk_i;
+    reg wb_rst_i;
+
+    reg [31:0] wb_adr_i;
+    reg [31:0] wb_dat_i;
+    reg [3:0]  wb_sel_i;
+    reg wb_we_i;
+    reg wb_cyc_i;
+    reg  [1:0] wb_stb_i;
+    wire [1:0] wb_ack_o;
+    wire [31:0] wb_rw_dat_o;
+
+    // MGMT_AREA RO WB Interface  
+    wire [31:0] wb_ro_dat_o;
+
+    wire [`RAM_BLOCKS-1:0] mgmt_ena;
+    wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+    wire [`RAM_BLOCKS-1:0] mgmt_wen;
+    wire [31:0] mgmt_wdata;
+    wire [7:0] mgmt_addr;
+    wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+    wire ro_ena;
+    wire [7:0] ro_addr;
+    wire [31:0] ro_rdata;
+    reg power1;
+
+    initial begin
+        wb_clk_i = 0;
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+    end
+
+    initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		#1;
+		power1 <= 1'b1;
+	end
+
+    wire VPWR;
+	wire VGND;
+	assign VGND = 1'b0;
+	assign VPWR = power1;
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("storage.vcd");
+        $dumpvars(0, storage_tb);
+        repeat (100) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test Storage Area Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    reg [31:0] ref_data [255: 0];
+    reg [(24*`RAM_BLOCKS)-1:0] storage_rw_adr = STORAGE_RW_ADR;
+    reg [23:0] storage_ro_adr = STORAGE_RO_ADR;
+    reg [31:0] block_adr;
+
+    integer i,j;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+
+        // Test MGMT R/W port and user RO port
+        for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+            for ( j = 0; j < 100; j = j + 1) begin 
+                if (i == 0) begin
+                    ref_data[j] = $urandom_range(0, 2**30);
+                end
+                block_adr = (storage_rw_adr[24*i+:24] + (j << 2))  | `STORAGE_BASE_ADR;
+                write(block_adr, ref_data[j]);
+                #2;
+            end
+        end
+        
+        for (i = 0; i<`RAM_BLOCKS; i = i +1) begin
+            for ( j = 0; j < 100; j = j + 1) begin 
+                block_adr = (storage_rw_adr[24*i+:24] + (j << 2))  | `STORAGE_BASE_ADR;
+                read(block_adr, 0);
+                if (wb_rw_dat_o !== ref_data[j]) begin
+                    $display("Got %0h, Expected %0h from addr %0h: ",wb_rw_dat_o,ref_data[j], block_adr);
+                    $display("Monitor: MGMT R/W Operation Failed");
+                    $finish;
+                end
+                
+                if (i == 0) begin
+                    block_adr = (storage_ro_adr + (j << 2))  | `STORAGE_BASE_ADR;
+                    read(block_adr, 1);
+                    if (wb_ro_dat_o !== ref_data[j]) begin
+                        $display("Monitor: MGMT RO Operation Failed");
+                        $finish;
+                    end
+                end
+                #2;
+            end
+        end
+
+        $display("Success");
+        $display ("Monitor: Test Storage Area Passed");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i[0] = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o[0] == 1);
+            wait(wb_ack_o[0] == 0);
+            wb_cyc_i = 0;
+            wb_stb_i[0] = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        input integer interface;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i[interface] = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o[interface] == 1);
+            wait(wb_ack_o[interface] == 0);
+            wb_cyc_i = 0;
+            wb_stb_i[interface] = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+
+    storage_bridge_wb #(
+        .RW_BLOCKS_ADR(STORAGE_RW_ADR),
+        .RO_BLOCKS_ADR(STORAGE_RO_ADR)
+    ) wb_bridge (
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+
+        .wb_adr_i(wb_adr_i),
+        .wb_dat_i(wb_dat_i),
+        .wb_sel_i(wb_sel_i),
+        .wb_we_i(wb_we_i),
+        .wb_cyc_i(wb_cyc_i),
+        .wb_stb_i(wb_stb_i),
+        .wb_ack_o(wb_ack_o),
+        .wb_rw_dat_o(wb_rw_dat_o),
+
+    // MGMT_AREA RO WB Interface  
+        .wb_ro_dat_o(wb_ro_dat_o),
+
+    // MGMT Area native memory interface
+        .mgmt_ena(mgmt_ena), 
+        .mgmt_wen_mask(mgmt_wen_mask),
+        .mgmt_wen(mgmt_wen),
+        .mgmt_addr(mgmt_addr),
+        .mgmt_wdata(mgmt_wdata),
+        .mgmt_rdata(mgmt_rdata),
+    // MGMT_AREA RO Interface
+        .mgmt_ena_ro(ro_ena),
+        .mgmt_addr_ro(ro_addr),
+        .mgmt_rdata_ro(ro_rdata)
+    );
+
+    storage uut (
+        `ifdef USE_POWER_PINS
+            .VPWR(VPWR),
+            .VGND(VGND),
+        `endif
+        // Management R/W WB interface
+        .mgmt_clk(wb_clk_i),
+        .mgmt_ena(mgmt_ena),
+        .mgmt_wen(mgmt_wen),
+        .mgmt_wen_mask(mgmt_wen_mask),
+        .mgmt_addr(mgmt_addr),
+        .mgmt_wdata(mgmt_wdata),
+        .mgmt_rdata(mgmt_rdata),
+        // Management RO interface  
+        .mgmt_ena_ro(ro_ena),
+        .mgmt_addr_ro(ro_addr),
+        .mgmt_rdata_ro(ro_rdata)
+    );
+
+endmodule
\ No newline at end of file

diff --git a/verilog/dv/wb_utests/sysctrl_wb/Makefile b/verilog/dv/wb_utests/sysctrl_wb/Makefile
new file mode 100644
index 0000000..89aa77b
--- /dev/null
+++ b/verilog/dv/wb_utests/sysctrl_wb/Makefile

@@ -0,0 +1,34 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = sysctrl_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog  -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all
+

diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
new file mode 100644
index 0000000..77140c7
--- /dev/null
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v

@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "sysctrl.v"
+
+module sysctrl_wb_tb;
+
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+    reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_dat_i;
+	reg [31:0] wb_adr_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+    
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_cyc_i = 0;  
+        wb_sel_i = 0;  
+        wb_we_i  = 0;  
+        wb_dat_i = 0; 
+        wb_adr_i = 0; 
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+    
+    initial begin
+        $dumpfile("sysctrl_wb_tb.vcd");
+        $dumpvars(0, sysctrl_wb_tb);
+        repeat (50) begin
+            repeat (1000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display ("Monitor: Timeout, Test System Control Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+    
+    // System Control Default Register Addresses 
+    wire [31:0] clk_out_adr  = uut.BASE_ADR | uut.CLK_OUT;  
+    wire [31:0] trap_out_adr  = uut.BASE_ADR | uut.TRAP_OUT;
+    wire [31:0] irq_src_adr  = uut.BASE_ADR | uut.IRQ_SRC;
+
+    reg clk1_output_dest;
+    reg clk2_output_dest;
+    reg trap_output_dest;
+    reg irq_7_inputsrc;
+    reg irq_8_inputsrc;
+   
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0;
+        #2;
+        
+        clk1_output_dest   = 1'b1;
+        clk2_output_dest   = 1'b1;
+        trap_output_dest  = 1'b1;
+        irq_7_inputsrc    = 1'b1;
+        irq_8_inputsrc    = 1'b1;
+
+        // Write to System Control Registers
+        write(clk_out_adr, clk1_output_dest);
+        write(trap_out_adr, trap_output_dest);
+        write(irq_src_adr,  irq_7_inputsrc);
+        #2;
+        read(clk_out_adr);
+        if (wb_dat_o !== clk1_output_dest) begin
+            $display("Error reading CLK1 output destination register.");
+            $finish;
+        end
+
+        read(trap_out_adr);
+        if (wb_dat_o !== trap_output_dest) begin
+            $display("Error reading trap output destination register.");
+            $finish;
+        end
+
+        read(irq_src_adr);
+        if (wb_dat_o !== irq_7_inputsrc) begin
+            $display("Error reading IRQ7 input source register.");
+            $finish;
+        end
+
+        $display("Success!");
+        $display ("Monitor: Test System Control Passed!");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Monitor: Write Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Monitor: Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Monitor: Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Monitor: Read Cycle Ended.");
+        end
+    endtask
+
+    sysctrl_wb uut(
+        .wb_clk_i(wb_clk_i),
+	    .wb_rst_i(wb_rst_i),
+        .wb_stb_i(wb_stb_i),
+	    .wb_cyc_i(wb_cyc_i),
+	    .wb_sel_i(wb_sel_i),
+	    .wb_we_i(wb_we_i),
+	    .wb_dat_i(wb_dat_i),
+	    .wb_adr_i(wb_adr_i), 
+        .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o)
+    );
+    
+endmodule

diff --git a/verilog/dv/wb_utests/uart_wb/Makefile b/verilog/dv/wb_utests/uart_wb/Makefile
new file mode 100644
index 0000000..d1c587f
--- /dev/null
+++ b/verilog/dv/wb_utests/uart_wb/Makefile

@@ -0,0 +1,33 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+.SUFFIXES:
+
+PATTERN = uart_wb
+
+all:  ${PATTERN:=.vcd}
+
+%.vvp: %_tb.v
+	iverilog -I .. -I ../../ -I ../../../rtl \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+clean:
+	rm -f *.vvp *.vcd *.log
+
+.PHONY: clean all

diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
new file mode 100644
index 0000000..da48151
--- /dev/null
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v

@@ -0,0 +1,169 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+
+`timescale 1 ns / 1 ps
+
+`include "simpleuart.v"
+
+module uart_wb_tb;
+    
+    reg wb_clk_i;
+	reg wb_rst_i;
+
+    reg wb_stb_i;
+	reg wb_cyc_i;
+	reg wb_we_i;
+	reg [3:0] wb_sel_i;
+	reg [31:0] wb_adr_i;
+	reg [31:0] wb_dat_i;
+
+	wire wb_ack_o;
+	wire [31:0] wb_dat_o;
+
+    wire tbuart_rx;
+	wire ser_rx;
+  
+    initial begin
+        wb_clk_i = 0; 
+        wb_rst_i = 0;
+        wb_stb_i = 0; 
+        wb_we_i  = 0;  
+        wb_cyc_i = 0;  
+        wb_adr_i = 0; 
+        wb_dat_i = 0; 
+        wb_sel_i = 0;  
+    end
+
+    always #1 wb_clk_i = ~wb_clk_i;
+
+    initial begin
+        $dumpfile("uart_wb_tb.vcd");
+        $dumpvars(0, uart_wb_tb);
+        repeat (500) begin
+            repeat (10000) @(posedge wb_clk_i);
+        end
+        $display("%c[1;31m",27);
+        $display("Monitor: Timeout, Test UART Failed");
+        $display("%c[0m",27);
+        $finish;
+    end
+
+    integer i;
+
+    wire [31:0] div_reg_addr = uut.BASE_ADR | uut.CLK_DIV;
+    wire [31:0] div_reg_data = 32'h FFFF_FFFF;
+    
+    wire [31:0] dat_reg_addr = uut.BASE_ADR | uut.DATA;
+    wire [31:0] dat_reg_data = 32'h FFFF_FFFF;
+
+    initial begin
+        // Reset Operation
+        wb_rst_i = 1;
+        #2;
+        wb_rst_i = 0; 
+        #2;
+
+        // Write to div register
+        write(div_reg_addr, div_reg_data);
+        #2;
+        read(div_reg_addr);
+        if (wb_dat_o !== div_reg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ", div_reg_data, wb_dat_o);
+            $display("Monitor: Wishbone UART Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        #6;
+
+        // Write Operation: writes to data register
+        write(dat_reg_addr, dat_reg_data);
+        #2;
+        read(dat_reg_addr);
+        if (wb_dat_o !== dat_reg_data) begin
+            $display("%c[1;31m",27);
+            $display("Expected %0b, but Got %0b ", dat_reg_data, wb_dat_o);
+            $display("Monitor: Wishbone UART Failed");
+            $display("%c[0m",27);
+            $finish;
+        end
+        $display("Success!");
+        $display("Monitor: Wishbone UART Passed");
+        $finish;
+    end
+    
+    task write;
+        input [32:0] addr;
+        input [32:0] data;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_sel_i = 4'hF; 
+                wb_we_i = 1;     
+                wb_adr_i = addr;
+                wb_dat_i = data;
+                $display("Write Cycle Started.");
+            end
+            #2;
+            wb_we_i = 0;     
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Write Cycle Ended.");
+        end
+    endtask
+    
+    task read;
+        input [32:0] addr;
+        begin 
+            @(posedge wb_clk_i) begin
+                wb_stb_i = 1;
+                wb_cyc_i = 1;
+                wb_we_i = 0;
+                wb_adr_i = addr;
+                $display("Read Cycle Started.");
+            end
+            // Wait for an ACK
+            wait(wb_ack_o == 1);
+            #2;
+            // wait(wb_ack_o == 0);
+            wb_cyc_i = 0;
+            wb_stb_i = 0;
+            $display("Read Cycle Ended.");
+        end
+    endtask
+    
+    simpleuart_wb uut (
+		.wb_clk_i(wb_clk_i),
+		.wb_rst_i(wb_rst_i),
+    	.wb_stb_i(wb_stb_i),
+    	.wb_cyc_i(wb_cyc_i),
+    	.wb_sel_i(wb_sel_i),
+    	.wb_we_i(wb_we_i),
+        .wb_adr_i(wb_adr_i),      
+	    .wb_dat_i(wb_dat_i),
+	    .wb_ack_o(wb_ack_o),
+	    .wb_dat_o(wb_dat_o),
+        .ser_tx(tbuart_rx),
+		.ser_rx(ser_rx)
+	);
+
+endmodule