Add files via upload
diff --git "a/Simulations/pre_synthesis/Screenshot \050459\051.png" "b/Simulations/pre_synthesis/Screenshot \050459\051.png"
new file mode 100644
index 0000000..6b6d918
--- /dev/null
+++ "b/Simulations/pre_synthesis/Screenshot \050459\051.png"
Binary files differ
diff --git a/Simulations/pre_synthesis/add.vcd b/Simulations/pre_synthesis/add.vcd
new file mode 100644
index 0000000..2e02095
--- /dev/null
+++ b/Simulations/pre_synthesis/add.vcd
@@ -0,0 +1,1850 @@
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+ Tue Oct 19 09:16:28 2021
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+b1 0#
+b1 6#
+b1 H"
+b1 N"
+b0 O"
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+b0 V"
+b0 \"
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+b1 d"
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+b1 r"
+b1 x"
+b11 y"
+b11 !#
+b1111110011001111001 )
+b1100110000111 *
+b1 "#
+b1 (#
+b1 )"
+b1 i
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+b0 o
+b11 r
+b1 u
+b1 {
+b11 ~
+b1 #"
+1'"
+1g
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+1q
+1p
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+1|
+1!"
+1P
+12
+01
+04
+17
+1;
+0:
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+1C
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+1J
+b1 Q
+b1 0
+b1 3
+b0 6
+b11 9
+b1 <
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+b11 E
+b10 H
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+b1000110110111 &
+b11111010000 %
+b1000110110111 #
+b1000110110111 (
+b11111010000 "
+b11111010000 '
diff --git a/Simulations/pre_synthesis/adder.v b/Simulations/pre_synthesis/adder.v
new file mode 100644
index 0000000..d93bb11
--- /dev/null
+++ b/Simulations/pre_synthesis/adder.v
@@ -0,0 +1,120 @@
+
+module adder(p, q, mode, sum);
+
+parameter num = 18;
+
+output [num:0] sum;
+input [num-1:0] p,q;
+input mode;
+
+wire [num:0] temp, temp1;
+
+`ifdef DSPoperator
+wire [num:0] temp2, temp3;
+ assign temp2[num:0] = p[num-1] ? -{2'b0, p[num-2:0]}:{1'b0,p};
+ assign temp3[num:0] = q[num-1] ? -{2'b0, q[num-2:0]}:{1'b0,q};
+ assign temp[num:0] = mode ? temp2-temp3 : temp2+temp3;
+`else
+ wire [2*num+1:0] x [0:$clog2(num+1)];
+ wire [num:0] a1, b1, a, b;
+
+ assign a1 = {(num+1){p[num-1]}}^{2'b0, p[num-2:0]};
+ assign b1 = {(num+1){mode^q[num-1]}}^{2'b0, q[num-2:0]};
+ assign a[0] = a1[0];
+ assign b[0] = b1[0];
+ assign b[1] = p[num-1]&(q[num-1]^mode);
+ assign a[num] = a1[num]^b1[num];
+
+ assign x[0][1:0]={2{p[num-1]^q[num-1]^mode}}; // Input carry
+
+ genvar i, j;
+ generate
+ begin:ha_fa //halfadder
+ for(i=1; i<num; i=i+1) begin
+ halfadd t0({a1[i],b1[i]}, a[i], b[i+1]);
+ end
+ end
+
+ begin: kgp_gen // kgp generation
+ for (i=0; i<num; i=i+1) begin
+ kgp t(a[i], b[i], x[0][2*i+3:2*i+2]);
+ end
+ end
+ begin:recursiveStg //recursive
+ for (i=0; i<$clog2(num+1); i=i+1)
+ begin
+ assign x[i+1][(2**(i+1))-1:0]=x[i][(2**(i+1))-1:0];
+ for(j=(2**(i+1)); j<2*num+1; j=j+2)
+ begin
+ recursive_stage1 s(x[i][j+1-(2**(i+1)):j-(2**(i+1))],x[i][j+1:j],x[i+1][j+1:j]);
+ end
+ end
+ end
+ begin:addition // SUM Calculation
+ for(i=0; i<num+1; i=i+1) begin
+ assign temp[i] = a[i]^b[i]^x[$clog2(num)][2*i];
+ end
+ end
+ endgenerate
+`endif
+ assign temp1 = -temp;
+ assign sum = temp[num] ? ({temp[num], temp1[num-1:0]}) : (temp);
+
+endmodule
+
+`ifdef DSPoperator
+
+`else
+
+ module kgp(a,b,y);
+
+ input a,b; output [1:0] y;
+
+ assign y[0]=a | b;
+ assign y[1]=a & b;
+
+ endmodule
+
+
+
+ module recursive_stage1(a,b,y);
+
+ input [1:0] a,b; output [1:0] y;
+
+ wire [1:0] y;
+ wire b0;
+ not n1(b0,b[1]);
+ wire f,g0,g1;
+ and a1(f,b[0],b[1]);
+ and a2(g0,b0,b[0],a[0]);
+ and a3(g1,b0,b[0],a[1]);
+
+ or o1(y[0],f,g0);
+ or o2(y[1],f,g1);
+
+ endmodule
+
+ module halfadd(x, sum, carry);
+
+output sum,carry;
+input [1:0] x;
+
+ assign sum = x[1] ^ x[0];
+ assign carry = x[1] & x[0];
+
+endmodule
+
+
+
+module fulladd(x, sum, carry);
+
+output sum,carry;
+input [2:0] x;
+
+wire w;
+ assign w = x[2] ^ x[1];
+ assign sum = w ^ x[0];
+ assign carry = (x[2] & x[1])|(w & x[0]);
+endmodule
+`endif
+
diff --git a/Simulations/pre_synthesis/adder_tb.v b/Simulations/pre_synthesis/adder_tb.v
new file mode 100644
index 0000000..63aeb4b
--- /dev/null
+++ b/Simulations/pre_synthesis/adder_tb.v
@@ -0,0 +1,27 @@
+module adder_tb;
+reg [17:0] in1, in2;
+reg mode;
+wire [18:0] out;
+
+adder u1(
+in1,in2,mode,out
+);
+
+initial
+begin
+mode=0;
+ in1 = 10; in2 = 16;
+ #20; in1 = 50; in2 = 34;
+ #20; in1 = 110; in2 = 45;
+ #20; in1 = 2000; in2 = 4535;
+
+end
+
+initial
+begin
+ $dumpfile("add.vcd");
+ $dumpvars(0, adder_tb);
+ $monitor("time = %2d, in1 = %d, in2 = %d, out = %d", $time, in1, in2, out);
+end
+
+endmodule
\ No newline at end of file
