diff --git "a/Simulations/pre_synthesis/Screenshot \050459\051.png" "b/Simulations/pre_synthesis/Screenshot \050459\051.png"
new file mode 100644
index 0000000..6b6d918
--- /dev/null
+++ "b/Simulations/pre_synthesis/Screenshot \050459\051.png"
Binary files differ
diff --git a/Simulations/pre_synthesis/add.vcd b/Simulations/pre_synthesis/add.vcd
new file mode 100644
index 0000000..2e02095
--- /dev/null
+++ b/Simulations/pre_synthesis/add.vcd
@@ -0,0 +1,1850 @@
+$date
+	Tue Oct 19 09:16:28 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module adder_tb $end
+$var wire 19 ! out [18:0] $end
+$var reg 18 " in1 [17:0] $end
+$var reg 18 # in2 [17:0] $end
+$var reg 1 $ mode $end
+$scope module u1 $end
+$var wire 19 % a1 [18:0] $end
+$var wire 19 & b1 [18:0] $end
+$var wire 1 $ mode $end
+$var wire 18 ' p [17:0] $end
+$var wire 18 ( q [17:0] $end
+$var wire 19 ) temp1 [18:0] $end
+$var wire 19 * temp [18:0] $end
+$var wire 19 + sum [18:0] $end
+$var wire 19 , b [18:0] $end
+$var wire 19 - a [18:0] $end
+$scope begin addition $end
+$scope begin genblk9[0] $end
+$upscope $end
+$scope begin genblk9[1] $end
+$upscope $end
+$scope begin genblk9[2] $end
+$upscope $end
+$scope begin genblk9[3] $end
+$upscope $end
+$scope begin genblk9[4] $end
+$upscope $end
+$scope begin genblk9[5] $end
+$upscope $end
+$scope begin genblk9[6] $end
+$upscope $end
+$scope begin genblk9[7] $end
+$upscope $end
+$scope begin genblk9[8] $end
+$upscope $end
+$scope begin genblk9[9] $end
+$upscope $end
+$scope begin genblk9[10] $end
+$upscope $end
+$scope begin genblk9[11] $end
+$upscope $end
+$scope begin genblk9[12] $end
+$upscope $end
+$scope begin genblk9[13] $end
+$upscope $end
+$scope begin genblk9[14] $end
+$upscope $end
+$scope begin genblk9[15] $end
+$upscope $end
+$scope begin genblk9[16] $end
+$upscope $end
+$scope begin genblk9[17] $end
+$upscope $end
+$scope begin genblk9[18] $end
+$upscope $end
+$upscope $end
+$scope begin ha_fa $end
+$scope begin genblk2[1] $end
+$scope module t0 $end
+$var wire 1 . carry $end
+$var wire 1 / sum $end
+$var wire 2 0 x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[2] $end
+$scope module t0 $end
+$var wire 1 1 carry $end
+$var wire 1 2 sum $end
+$var wire 2 3 x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[3] $end
+$scope module t0 $end
+$var wire 1 4 carry $end
+$var wire 1 5 sum $end
+$var wire 2 6 x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[4] $end
+$scope module t0 $end
+$var wire 1 7 carry $end
+$var wire 1 8 sum $end
+$var wire 2 9 x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[5] $end
+$scope module t0 $end
+$var wire 1 : carry $end
+$var wire 1 ; sum $end
+$var wire 2 < x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[6] $end
+$scope module t0 $end
+$var wire 1 = carry $end
+$var wire 1 > sum $end
+$var wire 2 ? x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[7] $end
+$scope module t0 $end
+$var wire 1 @ carry $end
+$var wire 1 A sum $end
+$var wire 2 B x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[8] $end
+$scope module t0 $end
+$var wire 1 C carry $end
+$var wire 1 D sum $end
+$var wire 2 E x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[9] $end
+$scope module t0 $end
+$var wire 1 F carry $end
+$var wire 1 G sum $end
+$var wire 2 H x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[10] $end
+$scope module t0 $end
+$var wire 1 I carry $end
+$var wire 1 J sum $end
+$var wire 2 K x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[11] $end
+$scope module t0 $end
+$var wire 1 L carry $end
+$var wire 1 M sum $end
+$var wire 2 N x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[12] $end
+$scope module t0 $end
+$var wire 1 O carry $end
+$var wire 1 P sum $end
+$var wire 2 Q x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[13] $end
+$scope module t0 $end
+$var wire 1 R carry $end
+$var wire 1 S sum $end
+$var wire 2 T x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[14] $end
+$scope module t0 $end
+$var wire 1 U carry $end
+$var wire 1 V sum $end
+$var wire 2 W x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[15] $end
+$scope module t0 $end
+$var wire 1 X carry $end
+$var wire 1 Y sum $end
+$var wire 2 Z x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[16] $end
+$scope module t0 $end
+$var wire 1 [ carry $end
+$var wire 1 \ sum $end
+$var wire 2 ] x [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk2[17] $end
+$scope module t0 $end
+$var wire 1 ^ carry $end
+$var wire 1 _ sum $end
+$var wire 2 ` x [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin kgp_gen $end
+$scope begin genblk4[0] $end
+$scope module t $end
+$var wire 1 a a $end
+$var wire 1 b b $end
+$var wire 2 c y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[1] $end
+$scope module t $end
+$var wire 1 d a $end
+$var wire 1 e b $end
+$var wire 2 f y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[2] $end
+$scope module t $end
+$var wire 1 g a $end
+$var wire 1 h b $end
+$var wire 2 i y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[3] $end
+$scope module t $end
+$var wire 1 j a $end
+$var wire 1 k b $end
+$var wire 2 l y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[4] $end
+$scope module t $end
+$var wire 1 m a $end
+$var wire 1 n b $end
+$var wire 2 o y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[5] $end
+$scope module t $end
+$var wire 1 p a $end
+$var wire 1 q b $end
+$var wire 2 r y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[6] $end
+$scope module t $end
+$var wire 1 s a $end
+$var wire 1 t b $end
+$var wire 2 u y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[7] $end
+$scope module t $end
+$var wire 1 v a $end
+$var wire 1 w b $end
+$var wire 2 x y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[8] $end
+$scope module t $end
+$var wire 1 y a $end
+$var wire 1 z b $end
+$var wire 2 { y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[9] $end
+$scope module t $end
+$var wire 1 | a $end
+$var wire 1 } b $end
+$var wire 2 ~ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[10] $end
+$scope module t $end
+$var wire 1 !" a $end
+$var wire 1 "" b $end
+$var wire 2 #" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[11] $end
+$scope module t $end
+$var wire 1 $" a $end
+$var wire 1 %" b $end
+$var wire 2 &" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[12] $end
+$scope module t $end
+$var wire 1 '" a $end
+$var wire 1 (" b $end
+$var wire 2 )" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[13] $end
+$scope module t $end
+$var wire 1 *" a $end
+$var wire 1 +" b $end
+$var wire 2 ," y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[14] $end
+$scope module t $end
+$var wire 1 -" a $end
+$var wire 1 ." b $end
+$var wire 2 /" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[15] $end
+$scope module t $end
+$var wire 1 0" a $end
+$var wire 1 1" b $end
+$var wire 2 2" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[16] $end
+$scope module t $end
+$var wire 1 3" a $end
+$var wire 1 4" b $end
+$var wire 2 5" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk4[17] $end
+$scope module t $end
+$var wire 1 6" a $end
+$var wire 1 7" b $end
+$var wire 2 8" y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin recursiveStg $end
+$scope begin genblk6[0] $end
+$scope begin genblk7[2] $end
+$scope module s $end
+$var wire 2 9" a [1:0] $end
+$var wire 2 :" b [1:0] $end
+$var wire 1 ;" b0 $end
+$var wire 1 <" f $end
+$var wire 1 =" g0 $end
+$var wire 1 >" g1 $end
+$var wire 2 ?" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[4] $end
+$scope module s $end
+$var wire 2 @" a [1:0] $end
+$var wire 2 A" b [1:0] $end
+$var wire 1 B" b0 $end
+$var wire 1 C" f $end
+$var wire 1 D" g0 $end
+$var wire 1 E" g1 $end
+$var wire 2 F" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[6] $end
+$scope module s $end
+$var wire 2 G" a [1:0] $end
+$var wire 2 H" b [1:0] $end
+$var wire 1 I" b0 $end
+$var wire 1 J" f $end
+$var wire 1 K" g0 $end
+$var wire 1 L" g1 $end
+$var wire 2 M" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[8] $end
+$scope module s $end
+$var wire 2 N" a [1:0] $end
+$var wire 2 O" b [1:0] $end
+$var wire 1 P" b0 $end
+$var wire 1 Q" f $end
+$var wire 1 R" g0 $end
+$var wire 1 S" g1 $end
+$var wire 2 T" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[10] $end
+$scope module s $end
+$var wire 2 U" a [1:0] $end
+$var wire 2 V" b [1:0] $end
+$var wire 1 W" b0 $end
+$var wire 1 X" f $end
+$var wire 1 Y" g0 $end
+$var wire 1 Z" g1 $end
+$var wire 2 [" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[12] $end
+$scope module s $end
+$var wire 2 \" a [1:0] $end
+$var wire 2 ]" b [1:0] $end
+$var wire 1 ^" b0 $end
+$var wire 1 _" f $end
+$var wire 1 `" g0 $end
+$var wire 1 a" g1 $end
+$var wire 2 b" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[14] $end
+$scope module s $end
+$var wire 2 c" a [1:0] $end
+$var wire 2 d" b [1:0] $end
+$var wire 1 e" b0 $end
+$var wire 1 f" f $end
+$var wire 1 g" g0 $end
+$var wire 1 h" g1 $end
+$var wire 2 i" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[16] $end
+$scope module s $end
+$var wire 2 j" a [1:0] $end
+$var wire 2 k" b [1:0] $end
+$var wire 1 l" b0 $end
+$var wire 1 m" f $end
+$var wire 1 n" g0 $end
+$var wire 1 o" g1 $end
+$var wire 2 p" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[18] $end
+$scope module s $end
+$var wire 2 q" a [1:0] $end
+$var wire 2 r" b [1:0] $end
+$var wire 1 s" b0 $end
+$var wire 1 t" f $end
+$var wire 1 u" g0 $end
+$var wire 1 v" g1 $end
+$var wire 2 w" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[20] $end
+$scope module s $end
+$var wire 2 x" a [1:0] $end
+$var wire 2 y" b [1:0] $end
+$var wire 1 z" b0 $end
+$var wire 1 {" f $end
+$var wire 1 |" g0 $end
+$var wire 1 }" g1 $end
+$var wire 2 ~" y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[22] $end
+$scope module s $end
+$var wire 2 !# a [1:0] $end
+$var wire 2 "# b [1:0] $end
+$var wire 1 ## b0 $end
+$var wire 1 $# f $end
+$var wire 1 %# g0 $end
+$var wire 1 &# g1 $end
+$var wire 2 '# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[24] $end
+$scope module s $end
+$var wire 2 (# a [1:0] $end
+$var wire 2 )# b [1:0] $end
+$var wire 1 *# b0 $end
+$var wire 1 +# f $end
+$var wire 1 ,# g0 $end
+$var wire 1 -# g1 $end
+$var wire 2 .# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[26] $end
+$scope module s $end
+$var wire 2 /# a [1:0] $end
+$var wire 2 0# b [1:0] $end
+$var wire 1 1# b0 $end
+$var wire 1 2# f $end
+$var wire 1 3# g0 $end
+$var wire 1 4# g1 $end
+$var wire 2 5# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[28] $end
+$scope module s $end
+$var wire 2 6# a [1:0] $end
+$var wire 2 7# b [1:0] $end
+$var wire 1 8# b0 $end
+$var wire 1 9# f $end
+$var wire 1 :# g0 $end
+$var wire 1 ;# g1 $end
+$var wire 2 <# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[30] $end
+$scope module s $end
+$var wire 2 =# a [1:0] $end
+$var wire 2 ># b [1:0] $end
+$var wire 1 ?# b0 $end
+$var wire 1 @# f $end
+$var wire 1 A# g0 $end
+$var wire 1 B# g1 $end
+$var wire 2 C# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[32] $end
+$scope module s $end
+$var wire 2 D# a [1:0] $end
+$var wire 2 E# b [1:0] $end
+$var wire 1 F# b0 $end
+$var wire 1 G# f $end
+$var wire 1 H# g0 $end
+$var wire 1 I# g1 $end
+$var wire 2 J# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[34] $end
+$scope module s $end
+$var wire 2 K# a [1:0] $end
+$var wire 2 L# b [1:0] $end
+$var wire 1 M# b0 $end
+$var wire 1 N# f $end
+$var wire 1 O# g0 $end
+$var wire 1 P# g1 $end
+$var wire 2 Q# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[36] $end
+$scope module s $end
+$var wire 2 R# a [1:0] $end
+$var wire 2 S# b [1:0] $end
+$var wire 1 T# b0 $end
+$var wire 1 U# f $end
+$var wire 1 V# g0 $end
+$var wire 1 W# g1 $end
+$var wire 2 X# y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk6[1] $end
+$scope begin genblk7[4] $end
+$scope module s $end
+$var wire 2 Y# a [1:0] $end
+$var wire 2 Z# b [1:0] $end
+$var wire 1 [# b0 $end
+$var wire 1 \# f $end
+$var wire 1 ]# g0 $end
+$var wire 1 ^# g1 $end
+$var wire 2 _# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[6] $end
+$scope module s $end
+$var wire 2 `# a [1:0] $end
+$var wire 2 a# b [1:0] $end
+$var wire 1 b# b0 $end
+$var wire 1 c# f $end
+$var wire 1 d# g0 $end
+$var wire 1 e# g1 $end
+$var wire 2 f# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[8] $end
+$scope module s $end
+$var wire 2 g# a [1:0] $end
+$var wire 2 h# b [1:0] $end
+$var wire 1 i# b0 $end
+$var wire 1 j# f $end
+$var wire 1 k# g0 $end
+$var wire 1 l# g1 $end
+$var wire 2 m# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[10] $end
+$scope module s $end
+$var wire 2 n# a [1:0] $end
+$var wire 2 o# b [1:0] $end
+$var wire 1 p# b0 $end
+$var wire 1 q# f $end
+$var wire 1 r# g0 $end
+$var wire 1 s# g1 $end
+$var wire 2 t# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[12] $end
+$scope module s $end
+$var wire 2 u# a [1:0] $end
+$var wire 2 v# b [1:0] $end
+$var wire 1 w# b0 $end
+$var wire 1 x# f $end
+$var wire 1 y# g0 $end
+$var wire 1 z# g1 $end
+$var wire 2 {# y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[14] $end
+$scope module s $end
+$var wire 2 |# a [1:0] $end
+$var wire 2 }# b [1:0] $end
+$var wire 1 ~# b0 $end
+$var wire 1 !$ f $end
+$var wire 1 "$ g0 $end
+$var wire 1 #$ g1 $end
+$var wire 2 $$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[16] $end
+$scope module s $end
+$var wire 2 %$ a [1:0] $end
+$var wire 2 &$ b [1:0] $end
+$var wire 1 '$ b0 $end
+$var wire 1 ($ f $end
+$var wire 1 )$ g0 $end
+$var wire 1 *$ g1 $end
+$var wire 2 +$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[18] $end
+$scope module s $end
+$var wire 2 ,$ a [1:0] $end
+$var wire 2 -$ b [1:0] $end
+$var wire 1 .$ b0 $end
+$var wire 1 /$ f $end
+$var wire 1 0$ g0 $end
+$var wire 1 1$ g1 $end
+$var wire 2 2$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[20] $end
+$scope module s $end
+$var wire 2 3$ a [1:0] $end
+$var wire 2 4$ b [1:0] $end
+$var wire 1 5$ b0 $end
+$var wire 1 6$ f $end
+$var wire 1 7$ g0 $end
+$var wire 1 8$ g1 $end
+$var wire 2 9$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[22] $end
+$scope module s $end
+$var wire 2 :$ a [1:0] $end
+$var wire 2 ;$ b [1:0] $end
+$var wire 1 <$ b0 $end
+$var wire 1 =$ f $end
+$var wire 1 >$ g0 $end
+$var wire 1 ?$ g1 $end
+$var wire 2 @$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[24] $end
+$scope module s $end
+$var wire 2 A$ a [1:0] $end
+$var wire 2 B$ b [1:0] $end
+$var wire 1 C$ b0 $end
+$var wire 1 D$ f $end
+$var wire 1 E$ g0 $end
+$var wire 1 F$ g1 $end
+$var wire 2 G$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[26] $end
+$scope module s $end
+$var wire 2 H$ a [1:0] $end
+$var wire 2 I$ b [1:0] $end
+$var wire 1 J$ b0 $end
+$var wire 1 K$ f $end
+$var wire 1 L$ g0 $end
+$var wire 1 M$ g1 $end
+$var wire 2 N$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[28] $end
+$scope module s $end
+$var wire 2 O$ a [1:0] $end
+$var wire 2 P$ b [1:0] $end
+$var wire 1 Q$ b0 $end
+$var wire 1 R$ f $end
+$var wire 1 S$ g0 $end
+$var wire 1 T$ g1 $end
+$var wire 2 U$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[30] $end
+$scope module s $end
+$var wire 2 V$ a [1:0] $end
+$var wire 2 W$ b [1:0] $end
+$var wire 1 X$ b0 $end
+$var wire 1 Y$ f $end
+$var wire 1 Z$ g0 $end
+$var wire 1 [$ g1 $end
+$var wire 2 \$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[32] $end
+$scope module s $end
+$var wire 2 ]$ a [1:0] $end
+$var wire 2 ^$ b [1:0] $end
+$var wire 1 _$ b0 $end
+$var wire 1 `$ f $end
+$var wire 1 a$ g0 $end
+$var wire 1 b$ g1 $end
+$var wire 2 c$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[34] $end
+$scope module s $end
+$var wire 2 d$ a [1:0] $end
+$var wire 2 e$ b [1:0] $end
+$var wire 1 f$ b0 $end
+$var wire 1 g$ f $end
+$var wire 1 h$ g0 $end
+$var wire 1 i$ g1 $end
+$var wire 2 j$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[36] $end
+$scope module s $end
+$var wire 2 k$ a [1:0] $end
+$var wire 2 l$ b [1:0] $end
+$var wire 1 m$ b0 $end
+$var wire 1 n$ f $end
+$var wire 1 o$ g0 $end
+$var wire 1 p$ g1 $end
+$var wire 2 q$ y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk6[2] $end
+$scope begin genblk7[8] $end
+$scope module s $end
+$var wire 2 r$ a [1:0] $end
+$var wire 2 s$ b [1:0] $end
+$var wire 1 t$ b0 $end
+$var wire 1 u$ f $end
+$var wire 1 v$ g0 $end
+$var wire 1 w$ g1 $end
+$var wire 2 x$ y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[10] $end
+$scope module s $end
+$var wire 2 y$ a [1:0] $end
+$var wire 2 z$ b [1:0] $end
+$var wire 1 {$ b0 $end
+$var wire 1 |$ f $end
+$var wire 1 }$ g0 $end
+$var wire 1 ~$ g1 $end
+$var wire 2 !% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[12] $end
+$scope module s $end
+$var wire 2 "% a [1:0] $end
+$var wire 2 #% b [1:0] $end
+$var wire 1 $% b0 $end
+$var wire 1 %% f $end
+$var wire 1 &% g0 $end
+$var wire 1 '% g1 $end
+$var wire 2 (% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[14] $end
+$scope module s $end
+$var wire 2 )% a [1:0] $end
+$var wire 2 *% b [1:0] $end
+$var wire 1 +% b0 $end
+$var wire 1 ,% f $end
+$var wire 1 -% g0 $end
+$var wire 1 .% g1 $end
+$var wire 2 /% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[16] $end
+$scope module s $end
+$var wire 2 0% a [1:0] $end
+$var wire 2 1% b [1:0] $end
+$var wire 1 2% b0 $end
+$var wire 1 3% f $end
+$var wire 1 4% g0 $end
+$var wire 1 5% g1 $end
+$var wire 2 6% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[18] $end
+$scope module s $end
+$var wire 2 7% a [1:0] $end
+$var wire 2 8% b [1:0] $end
+$var wire 1 9% b0 $end
+$var wire 1 :% f $end
+$var wire 1 ;% g0 $end
+$var wire 1 <% g1 $end
+$var wire 2 =% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[20] $end
+$scope module s $end
+$var wire 2 >% a [1:0] $end
+$var wire 2 ?% b [1:0] $end
+$var wire 1 @% b0 $end
+$var wire 1 A% f $end
+$var wire 1 B% g0 $end
+$var wire 1 C% g1 $end
+$var wire 2 D% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[22] $end
+$scope module s $end
+$var wire 2 E% a [1:0] $end
+$var wire 2 F% b [1:0] $end
+$var wire 1 G% b0 $end
+$var wire 1 H% f $end
+$var wire 1 I% g0 $end
+$var wire 1 J% g1 $end
+$var wire 2 K% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[24] $end
+$scope module s $end
+$var wire 2 L% a [1:0] $end
+$var wire 2 M% b [1:0] $end
+$var wire 1 N% b0 $end
+$var wire 1 O% f $end
+$var wire 1 P% g0 $end
+$var wire 1 Q% g1 $end
+$var wire 2 R% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[26] $end
+$scope module s $end
+$var wire 2 S% a [1:0] $end
+$var wire 2 T% b [1:0] $end
+$var wire 1 U% b0 $end
+$var wire 1 V% f $end
+$var wire 1 W% g0 $end
+$var wire 1 X% g1 $end
+$var wire 2 Y% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[28] $end
+$scope module s $end
+$var wire 2 Z% a [1:0] $end
+$var wire 2 [% b [1:0] $end
+$var wire 1 \% b0 $end
+$var wire 1 ]% f $end
+$var wire 1 ^% g0 $end
+$var wire 1 _% g1 $end
+$var wire 2 `% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[30] $end
+$scope module s $end
+$var wire 2 a% a [1:0] $end
+$var wire 2 b% b [1:0] $end
+$var wire 1 c% b0 $end
+$var wire 1 d% f $end
+$var wire 1 e% g0 $end
+$var wire 1 f% g1 $end
+$var wire 2 g% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[32] $end
+$scope module s $end
+$var wire 2 h% a [1:0] $end
+$var wire 2 i% b [1:0] $end
+$var wire 1 j% b0 $end
+$var wire 1 k% f $end
+$var wire 1 l% g0 $end
+$var wire 1 m% g1 $end
+$var wire 2 n% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[34] $end
+$scope module s $end
+$var wire 2 o% a [1:0] $end
+$var wire 2 p% b [1:0] $end
+$var wire 1 q% b0 $end
+$var wire 1 r% f $end
+$var wire 1 s% g0 $end
+$var wire 1 t% g1 $end
+$var wire 2 u% y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[36] $end
+$scope module s $end
+$var wire 2 v% a [1:0] $end
+$var wire 2 w% b [1:0] $end
+$var wire 1 x% b0 $end
+$var wire 1 y% f $end
+$var wire 1 z% g0 $end
+$var wire 1 {% g1 $end
+$var wire 2 |% y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk6[3] $end
+$scope begin genblk7[16] $end
+$scope module s $end
+$var wire 2 }% a [1:0] $end
+$var wire 2 ~% b [1:0] $end
+$var wire 1 !& b0 $end
+$var wire 1 "& f $end
+$var wire 1 #& g0 $end
+$var wire 1 $& g1 $end
+$var wire 2 %& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[18] $end
+$scope module s $end
+$var wire 2 && a [1:0] $end
+$var wire 2 '& b [1:0] $end
+$var wire 1 (& b0 $end
+$var wire 1 )& f $end
+$var wire 1 *& g0 $end
+$var wire 1 +& g1 $end
+$var wire 2 ,& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[20] $end
+$scope module s $end
+$var wire 2 -& a [1:0] $end
+$var wire 2 .& b [1:0] $end
+$var wire 1 /& b0 $end
+$var wire 1 0& f $end
+$var wire 1 1& g0 $end
+$var wire 1 2& g1 $end
+$var wire 2 3& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[22] $end
+$scope module s $end
+$var wire 2 4& a [1:0] $end
+$var wire 2 5& b [1:0] $end
+$var wire 1 6& b0 $end
+$var wire 1 7& f $end
+$var wire 1 8& g0 $end
+$var wire 1 9& g1 $end
+$var wire 2 :& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[24] $end
+$scope module s $end
+$var wire 2 ;& a [1:0] $end
+$var wire 2 <& b [1:0] $end
+$var wire 1 =& b0 $end
+$var wire 1 >& f $end
+$var wire 1 ?& g0 $end
+$var wire 1 @& g1 $end
+$var wire 2 A& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[26] $end
+$scope module s $end
+$var wire 2 B& a [1:0] $end
+$var wire 2 C& b [1:0] $end
+$var wire 1 D& b0 $end
+$var wire 1 E& f $end
+$var wire 1 F& g0 $end
+$var wire 1 G& g1 $end
+$var wire 2 H& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[28] $end
+$scope module s $end
+$var wire 2 I& a [1:0] $end
+$var wire 2 J& b [1:0] $end
+$var wire 1 K& b0 $end
+$var wire 1 L& f $end
+$var wire 1 M& g0 $end
+$var wire 1 N& g1 $end
+$var wire 2 O& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[30] $end
+$scope module s $end
+$var wire 2 P& a [1:0] $end
+$var wire 2 Q& b [1:0] $end
+$var wire 1 R& b0 $end
+$var wire 1 S& f $end
+$var wire 1 T& g0 $end
+$var wire 1 U& g1 $end
+$var wire 2 V& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[32] $end
+$scope module s $end
+$var wire 2 W& a [1:0] $end
+$var wire 2 X& b [1:0] $end
+$var wire 1 Y& b0 $end
+$var wire 1 Z& f $end
+$var wire 1 [& g0 $end
+$var wire 1 \& g1 $end
+$var wire 2 ]& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[34] $end
+$scope module s $end
+$var wire 2 ^& a [1:0] $end
+$var wire 2 _& b [1:0] $end
+$var wire 1 `& b0 $end
+$var wire 1 a& f $end
+$var wire 1 b& g0 $end
+$var wire 1 c& g1 $end
+$var wire 2 d& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[36] $end
+$scope module s $end
+$var wire 2 e& a [1:0] $end
+$var wire 2 f& b [1:0] $end
+$var wire 1 g& b0 $end
+$var wire 1 h& f $end
+$var wire 1 i& g0 $end
+$var wire 1 j& g1 $end
+$var wire 2 k& y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin genblk6[4] $end
+$scope begin genblk7[32] $end
+$scope module s $end
+$var wire 2 l& a [1:0] $end
+$var wire 2 m& b [1:0] $end
+$var wire 1 n& b0 $end
+$var wire 1 o& f $end
+$var wire 1 p& g0 $end
+$var wire 1 q& g1 $end
+$var wire 2 r& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[34] $end
+$scope module s $end
+$var wire 2 s& a [1:0] $end
+$var wire 2 t& b [1:0] $end
+$var wire 1 u& b0 $end
+$var wire 1 v& f $end
+$var wire 1 w& g0 $end
+$var wire 1 x& g1 $end
+$var wire 2 y& y [1:0] $end
+$upscope $end
+$upscope $end
+$scope begin genblk7[36] $end
+$scope module s $end
+$var wire 2 z& a [1:0] $end
+$var wire 2 {& b [1:0] $end
+$var wire 1 |& b0 $end
+$var wire 1 }& f $end
+$var wire 1 ~& g0 $end
+$var wire 1 !' g1 $end
+$var wire 2 "' y [1:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 "'
+0!'
+0~&
+0}&
+1|&
+b0 {&
+b0 z&
+b0 y&
+0x&
+0w&
+0v&
+1u&
+b0 t&
+b0 s&
+b0 r&
+0q&
+0p&
+0o&
+1n&
+b0 m&
+b0 l&
+b0 k&
+0j&
+0i&
+0h&
+1g&
+b0 f&
+b0 e&
+b0 d&
+0c&
+0b&
+0a&
+1`&
+b0 _&
+b0 ^&
+b0 ]&
+0\&
+0[&
+0Z&
+1Y&
+b0 X&
+b0 W&
+b0 V&
+0U&
+0T&
+0S&
+1R&
+b0 Q&
+b0 P&
+b0 O&
+0N&
+0M&
+0L&
+1K&
+b0 J&
+b0 I&
+b0 H&
+0G&
+0F&
+0E&
+1D&
+b0 C&
+b0 B&
+b0 A&
+0@&
+0?&
+0>&
+1=&
+b0 <&
+b0 ;&
+b0 :&
+09&
+08&
+07&
+16&
+b0 5&
+b0 4&
+b0 3&
+02&
+01&
+00&
+1/&
+b0 .&
+b0 -&
+b0 ,&
+0+&
+0*&
+0)&
+1(&
+b0 '&
+b0 &&
+b0 %&
+0$&
+0#&
+0"&
+1!&
+b0 ~%
+b0 }%
+b0 |%
+0{%
+0z%
+0y%
+1x%
+b0 w%
+b0 v%
+b0 u%
+0t%
+0s%
+0r%
+1q%
+b0 p%
+b0 o%
+b0 n%
+0m%
+0l%
+0k%
+1j%
+b0 i%
+b0 h%
+b0 g%
+0f%
+0e%
+0d%
+1c%
+b0 b%
+b0 a%
+b0 `%
+0_%
+0^%
+0]%
+1\%
+b0 [%
+b0 Z%
+b0 Y%
+0X%
+0W%
+0V%
+1U%
+b0 T%
+b0 S%
+b0 R%
+0Q%
+0P%
+0O%
+1N%
+b0 M%
+b0 L%
+b0 K%
+0J%
+0I%
+0H%
+1G%
+b0 F%
+b0 E%
+b0 D%
+0C%
+0B%
+0A%
+1@%
+b0 ?%
+b0 >%
+b0 =%
+0<%
+0;%
+0:%
+19%
+b0 8%
+b0 7%
+b0 6%
+05%
+04%
+03%
+12%
+b0 1%
+b0 0%
+b0 /%
+0.%
+0-%
+0,%
+1+%
+b0 *%
+b0 )%
+b0 (%
+0'%
+0&%
+0%%
+1$%
+b0 #%
+b0 "%
+b0 !%
+0~$
+0}$
+0|$
+1{$
+b0 z$
+b0 y$
+b0 x$
+0w$
+0v$
+0u$
+1t$
+b0 s$
+b0 r$
+b0 q$
+0p$
+0o$
+0n$
+1m$
+b0 l$
+b0 k$
+b0 j$
+0i$
+0h$
+0g$
+1f$
+b0 e$
+b0 d$
+b0 c$
+0b$
+0a$
+0`$
+1_$
+b0 ^$
+b0 ]$
+b0 \$
+0[$
+0Z$
+0Y$
+1X$
+b0 W$
+b0 V$
+b0 U$
+0T$
+0S$
+0R$
+1Q$
+b0 P$
+b0 O$
+b0 N$
+0M$
+0L$
+0K$
+1J$
+b0 I$
+b0 H$
+b0 G$
+0F$
+0E$
+0D$
+1C$
+b0 B$
+b0 A$
+b0 @$
+0?$
+0>$
+0=$
+1<$
+b0 ;$
+b0 :$
+b0 9$
+08$
+07$
+06$
+15$
+b0 4$
+b0 3$
+b0 2$
+01$
+00$
+0/$
+1.$
+b0 -$
+b0 ,$
+b0 +$
+0*$
+0)$
+0($
+1'$
+b0 &$
+b0 %$
+b0 $$
+0#$
+0"$
+0!$
+1~#
+b0 }#
+b1 |#
+b0 {#
+0z#
+0y#
+0x#
+1w#
+b0 v#
+b0 u#
+b0 t#
+0s#
+0r#
+0q#
+1p#
+b1 o#
+b0 n#
+b0 m#
+0l#
+0k#
+0j#
+1i#
+b0 h#
+b0 g#
+b0 f#
+0e#
+0d#
+0c#
+1b#
+b0 a#
+b0 `#
+b0 _#
+0^#
+0]#
+0\#
+1[#
+b0 Z#
+b0 Y#
+b0 X#
+0W#
+0V#
+0U#
+1T#
+b0 S#
+b0 R#
+b0 Q#
+0P#
+0O#
+0N#
+1M#
+b0 L#
+b0 K#
+b0 J#
+0I#
+0H#
+0G#
+1F#
+b0 E#
+b0 D#
+b0 C#
+0B#
+0A#
+0@#
+1?#
+b0 >#
+b0 =#
+b0 <#
+0;#
+0:#
+09#
+18#
+b0 7#
+b0 6#
+b0 5#
+04#
+03#
+02#
+11#
+b0 0#
+b0 /#
+b0 .#
+0-#
+0,#
+0+#
+1*#
+b0 )#
+b0 (#
+b0 '#
+0&#
+0%#
+0$#
+1##
+b0 "#
+b0 !#
+b0 ~"
+0}"
+0|"
+0{"
+1z"
+b0 y"
+b0 x"
+b0 w"
+0v"
+0u"
+0t"
+1s"
+b0 r"
+b0 q"
+b0 p"
+0o"
+0n"
+0m"
+1l"
+b0 k"
+b0 j"
+b0 i"
+0h"
+0g"
+0f"
+1e"
+b0 d"
+b0 c"
+b0 b"
+0a"
+0`"
+0_"
+1^"
+b0 ]"
+b1 \"
+b1 ["
+0Z"
+1Y"
+0X"
+1W"
+b1 V"
+b1 U"
+b0 T"
+0S"
+0R"
+0Q"
+1P"
+b1 O"
+b0 N"
+b0 M"
+0L"
+0K"
+0J"
+1I"
+b0 H"
+b1 G"
+b0 F"
+0E"
+0D"
+0C"
+1B"
+b1 A"
+b0 @"
+b0 ?"
+0>"
+0="
+0<"
+1;"
+b0 :"
+b0 9"
+b0 8"
+07"
+06"
+b0 5"
+04"
+03"
+b0 2"
+01"
+00"
+b0 /"
+0."
+0-"
+b0 ,"
+0+"
+0*"
+b0 )"
+0("
+0'"
+b0 &"
+0%"
+0$"
+b0 #"
+0""
+0!"
+b0 ~
+0}
+0|
+b0 {
+0z
+0y
+b0 x
+0w
+0v
+b0 u
+0t
+0s
+b0 r
+0q
+0p
+b1 o
+0n
+1m
+b1 l
+0k
+1j
+b0 i
+0h
+0g
+b1 f
+0e
+1d
+b0 c
+0b
+0a
+b0 `
+0_
+0^
+b0 ]
+0\
+0[
+b0 Z
+0Y
+0X
+b0 W
+0V
+0U
+b0 T
+0S
+0R
+b0 Q
+0P
+0O
+b0 N
+0M
+0L
+b0 K
+0J
+0I
+b0 H
+0G
+0F
+b0 E
+0D
+0C
+b0 B
+0A
+0@
+b0 ?
+0>
+0=
+b0 <
+0;
+0:
+b1 9
+18
+07
+b10 6
+15
+04
+b0 3
+02
+01
+b10 0
+1/
+0.
+b11010 -
+b0 ,
+b11010 +
+b11010 *
+b1111111111111100110 )
+b10000 (
+b1010 '
+b10000 &
+b1010 %
+0$
+b10000 #
+b1010 "
+b11010 !
+$end
+#20
+b0 o#
+b0 |#
+b0 ["
+0Y"
+b1010100 !
+b1010100 +
+b0 A"
+b0 G"
+b1 H"
+b1 N"
+b0 O"
+b0 U"
+b1111111111110101100 )
+b1010100 *
+b1 d"
+b1 j"
+b0 f
+b1 i
+b0 l
+b1 u
+0d
+1h
+0j
+1t
+0/
+1.
+b10000 -
+05
+b1000100 ,
+1:
+b11 0
+b0 6
+b10 9
+b11 <
+b100010 &
+b110010 %
+b100010 #
+b100010 (
+b110010 "
+b110010 '
+#40
+b11 P&
+b11 /%
+0+%
+1,%
+b11 *%
+b11 E%
+b11 $$
+0~#
+1!$
+0"$
+b1 Z#
+b1 g#
+b1 o#
+b1 |#
+b11 }#
+b11 ,$
+b1 F"
+b1 ["
+b11 i"
+1D"
+1Y"
+0e"
+1f"
+b1 A"
+b1 G"
+b0 H"
+b0 N"
+b1 O"
+b1 U"
+b11 d"
+b11 j"
+b1 f
+b0 i
+b10011011 !
+b10011011 +
+b1 l
+b11 u
+1d
+0h
+b1111111111101100101 )
+b10011011 *
+b1 :"
+b1 @"
+1k
+1n
+0m
+1s
+1/
+0.
+b1 c
+11
+14
+08
+b1000010 -
+1>
+1b
+b10 0
+b1011001 ,
+b11 3
+b11 6
+b0 9
+b10 ?
+b101101 &
+b1101110 %
+b101101 #
+b101101 (
+b1101110 "
+b1101110 '
+#60
+b11 3&
+b11 :&
+0/&
+10&
+06&
+17&
+b11 I&
+b11 .&
+b11 e&
+b11 5&
+b11 (%
+b11 D%
+b11 K%
+0$%
+1%%
+0@%
+1A%
+0B%
+0C%
+0G%
+1H%
+0I%
+0J%
+b11 #%
+b11 >%
+b11 ?%
+b11 Z%
+b11 F%
+b11 a%
+b11 {#
+b11 9$
+b11 @$
+0w#
+1x#
+05$
+16$
+0<$
+1=$
+b1 a#
+b1 n#
+b0 o#
+b0 |#
+b11 v#
+b11 %$
+b11 4$
+b11 A$
+b11 ;$
+b11 H$
+b1 M"
+b0 ["
+b11 b"
+b11 ~"
+b11 '#
+1K"
+0Y"
+0^"
+1_"
+1g"
+1h"
+1e"
+0f"
+0z"
+1{"
+0|"
+1%#
+1&#
+b1100110000111 !
+b1100110000111 +
+b1 0#
+b1 6#
+b1 H"
+b1 N"
+b0 O"
+b0 U"
+b0 V"
+b0 \"
+b11 ]"
+b11 c"
+b1 d"
+b1 j"
+b1 r"
+b1 x"
+b11 y"
+b11 !#
+b1111110011001111001 )
+b1100110000111 *
+b1 "#
+b1 (#
+b1 )"
+b1 i
+b0 l
+b0 o
+b11 r
+b1 u
+b1 {
+b11 ~
+b1 #"
+1'"
+1g
+0k
+0n
+1q
+1p
+0t
+1z
+1}
+1|
+1!"
+1P
+12
+01
+04
+17
+1;
+0:
+1@
+b1100100001 ,
+1C
+1G
+b1011001100110 -
+1J
+b1 Q
+b1 0
+b1 3
+b0 6
+b11 9
+b1 <
+b11 B
+b11 E
+b10 H
+b10 K
+b1000110110111 &
+b11111010000 %
+b1000110110111 #
+b1000110110111 (
+b11111010000 "
+b11111010000 '
diff --git a/Simulations/pre_synthesis/adder.v b/Simulations/pre_synthesis/adder.v
new file mode 100644
index 0000000..d93bb11
--- /dev/null
+++ b/Simulations/pre_synthesis/adder.v
@@ -0,0 +1,120 @@
+
+module adder(p, q, mode, sum);
+
+parameter num = 18;
+
+output [num:0] sum;
+input [num-1:0] p,q;
+input mode;
+
+wire [num:0] temp, temp1;
+
+`ifdef DSPoperator
+wire [num:0] temp2, temp3;
+    assign temp2[num:0] = p[num-1] ? -{2'b0, p[num-2:0]}:{1'b0,p};
+    assign temp3[num:0] = q[num-1] ? -{2'b0, q[num-2:0]}:{1'b0,q};
+    assign temp[num:0] = mode ? temp2-temp3 : temp2+temp3;
+`else
+    wire [2*num+1:0] x [0:$clog2(num+1)];
+    wire [num:0] a1, b1, a, b;
+
+    assign a1 = {(num+1){p[num-1]}}^{2'b0, p[num-2:0]};
+    assign b1 = {(num+1){mode^q[num-1]}}^{2'b0, q[num-2:0]};
+    assign a[0] = a1[0];
+    assign b[0] = b1[0];
+    assign b[1] = p[num-1]&(q[num-1]^mode);
+    assign a[num] = a1[num]^b1[num];
+
+    assign x[0][1:0]={2{p[num-1]^q[num-1]^mode}};  					// Input carry
+
+    genvar i, j;
+    generate
+    begin:ha_fa			//halfadder
+        for(i=1; i<num; i=i+1) begin
+        halfadd t0({a1[i],b1[i]}, a[i], b[i+1]);
+        end
+    end
+
+    begin: kgp_gen		// kgp generation
+        for (i=0; i<num; i=i+1) begin
+        kgp t(a[i], b[i], x[0][2*i+3:2*i+2]);
+        end
+    end
+    begin:recursiveStg	//recursive
+        for (i=0; i<$clog2(num+1); i=i+1)
+        begin
+        assign x[i+1][(2**(i+1))-1:0]=x[i][(2**(i+1))-1:0];
+            for(j=(2**(i+1)); j<2*num+1; j=j+2)
+            begin
+            recursive_stage1 s(x[i][j+1-(2**(i+1)):j-(2**(i+1))],x[i][j+1:j],x[i+1][j+1:j]);		
+            end
+        end
+    end
+    begin:addition		// SUM Calculation
+        for(i=0; i<num+1; i=i+1) begin
+        assign temp[i] = a[i]^b[i]^x[$clog2(num)][2*i];
+        end
+    end
+    endgenerate
+`endif
+    assign temp1 = -temp;
+    assign sum = temp[num] ? ({temp[num], temp1[num-1:0]}) : (temp);
+
+endmodule
+
+`ifdef DSPoperator
+
+`else
+
+    module kgp(a,b,y);
+
+    input a,b;						output [1:0] y;
+
+    assign y[0]=a | b;
+    assign y[1]=a & b;
+
+    endmodule
+
+
+
+    module recursive_stage1(a,b,y);
+
+    input [1:0] a,b;				output [1:0] y;
+
+    wire [1:0] y;
+    wire b0;
+    not n1(b0,b[1]);
+    wire f,g0,g1;
+    and a1(f,b[0],b[1]);
+    and a2(g0,b0,b[0],a[0]);
+    and a3(g1,b0,b[0],a[1]);
+
+    or o1(y[0],f,g0);
+    or o2(y[1],f,g1);
+
+    endmodule
+
+    module halfadd(x, sum, carry);
+
+output sum,carry;
+input [1:0] x;
+
+	assign	 sum = x[1] ^ x[0];
+	assign 	 carry = x[1] & x[0];
+	
+endmodule
+
+
+
+module fulladd(x, sum, carry);
+
+output sum,carry;
+input [2:0] x;
+
+wire w;	
+	assign 	 w = x[2] ^ x[1];
+        assign	 sum = w ^ x[0];
+	assign 	 carry = (x[2] & x[1])|(w & x[0]);
+endmodule
+`endif
+
diff --git a/Simulations/pre_synthesis/adder_tb.v b/Simulations/pre_synthesis/adder_tb.v
new file mode 100644
index 0000000..63aeb4b
--- /dev/null
+++ b/Simulations/pre_synthesis/adder_tb.v
@@ -0,0 +1,27 @@
+module adder_tb;
+reg [17:0] in1, in2;
+reg mode;
+wire [18:0] out;
+
+adder u1(
+in1,in2,mode,out
+);
+
+initial
+begin
+mode=0;
+	     in1 = 10; in2 = 16;
+	#20; in1 = 50; in2 = 34; 
+	#20; in1 = 110; in2 = 45;
+	#20; in1 = 2000; in2 = 4535;
+
+end
+
+initial 
+begin
+	$dumpfile("add.vcd");
+	$dumpvars(0, adder_tb);
+	$monitor("time = %2d, in1 = %d, in2 = %d, out = %d", $time, in1, in2, out);
+end
+
+endmodule
\ No newline at end of file