commit: 16df4119d4d05f3abfa5deb2f3ba007ad187f574
[log] [tgz]
author: Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com>
Wed Oct 20 13:28:35 2021 +0530
committer: GitHub <noreply@github.com>
Wed Oct 20 13:28:35 2021 +0530
tree: 93a85c1c1b60b7e59c8a27f5227825a7ef04f835
parent: 956742f5c85380d303480c91d702cff707f80280 [diff]

Add files via upload

caravel/verilog/gl/DFFRAM.v[Added - diff]
caravel/verilog/gl/__user_analog_project_wrapper.v[Added - diff]
caravel/verilog/gl/__user_project_wrapper.v[Added - diff]
caravel/verilog/gl/caravan.v[Added - diff]
caravel/verilog/gl/caravel.v[Added - diff]
caravel/verilog/gl/chip_io.v[Added - diff]
caravel/verilog/gl/chip_io_alt.v[Added - diff]
caravel/verilog/gl/digital_pll.v[Added - diff]
caravel/verilog/gl/gpio_control_block.v[Added - diff]
caravel/verilog/gl/gpio_logic_high.v[Added - diff]
caravel/verilog/gl/mgmt_core.v[Added - diff]
caravel/verilog/gl/mgmt_protect.v[Added - diff]
caravel/verilog/gl/mgmt_protect_hv.v[Added - diff]
caravel/verilog/gl/mprj2_logic_high.v[Added - diff]
caravel/verilog/gl/mprj_logic_high.v[Added - diff]
caravel/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v[Added - diff]
caravel/verilog/gl/storage.v[Added - diff]
caravel/verilog/gl/user_id_programming.v[Added - diff]

18 files changed

tree: 93a85c1c1b60b7e59c8a27f5227825a7ef04f835

README.md

Caravel User Project

18 bit Adder