commit: 956742f5c85380d303480c91d702cff707f80280
[log]
author: Dhayalakumar <61288836+dhayalakumarm@users.noreply.github.com>
Wed Oct 20 13:21:56 2021 +0530
committer: GitHub <noreply@github.com>
Wed Oct 20 13:21:56 2021 +0530
tree: 4f841de1fb748b2cb692d7b076ae196d680002ed
parent: 06ba91dc1c7f2694dfe2f392fa85ea0afe106f5b [diff]

Add files via upload

caravel/verilog/rtl/DFFRAM.v[Added - diff]
caravel/verilog/rtl/DFFRAMBB.v[Added - diff]
caravel/verilog/rtl/README[Added - diff]
caravel/verilog/rtl/__uprj_analog_netlists.v[Added - diff]
caravel/verilog/rtl/__uprj_netlists.v[Added - diff]
caravel/verilog/rtl/__user_analog_project_wrapper.v[Added - diff]
caravel/verilog/rtl/__user_project_wrapper.v[Added - diff]
caravel/verilog/rtl/caravan.v[Added - diff]
caravel/verilog/rtl/caravan_netlists.v[Added - diff]
caravel/verilog/rtl/caravel.v[Added - diff]
caravel/verilog/rtl/caravel_clocking.v[Added - diff]
caravel/verilog/rtl/caravel_netlists.v[Added - diff]
caravel/verilog/rtl/chip_io.v[Added - diff]
caravel/verilog/rtl/chip_io_alt.v[Added - diff]
caravel/verilog/rtl/clock_div.v[Added - diff]
caravel/verilog/rtl/convert_gpio_sigs.v[Added - diff]
caravel/verilog/rtl/counter_timer_high.v[Added - diff]
caravel/verilog/rtl/counter_timer_low.v[Added - diff]
caravel/verilog/rtl/defines.v[Added - diff]
caravel/verilog/rtl/digital_pll.v[Added - diff]
caravel/verilog/rtl/digital_pll_controller.v[Added - diff]
caravel/verilog/rtl/gpio_control_block.v[Added - diff]
caravel/verilog/rtl/gpio_logic_high.v[Added - diff]
caravel/verilog/rtl/gpio_wb.v[Added - diff]
caravel/verilog/rtl/housekeeping_spi.v[Added - diff]
caravel/verilog/rtl/la_wb.v[Added - diff]
caravel/verilog/rtl/mem_wb.v[Added - diff]
caravel/verilog/rtl/mgmt_core.v[Added - diff]
caravel/verilog/rtl/mgmt_protect.v[Added - diff]
caravel/verilog/rtl/mgmt_protect_hv.v[Added - diff]
caravel/verilog/rtl/mgmt_soc.v[Added - diff]
caravel/verilog/rtl/mprj2_logic_high.v[Added - diff]
caravel/verilog/rtl/mprj_ctrl.v[Added - diff]
caravel/verilog/rtl/mprj_io.v[Added - diff]
caravel/verilog/rtl/mprj_logic_high.v[Added - diff]
caravel/verilog/rtl/pads.v[Added - diff]
caravel/verilog/rtl/picorv32.v[Added - diff]
caravel/verilog/rtl/ring_osc2x13.v[Added - diff]
caravel/verilog/rtl/simple_por.v[Added - diff]
caravel/verilog/rtl/simple_spi_master.v[Added - diff]
caravel/verilog/rtl/simpleuart.v[Added - diff]
caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v[Added - diff]
caravel/verilog/rtl/spimemio.v[Added - diff]
caravel/verilog/rtl/sram_1rw1r_32_256_8_sky130.v[Added - diff]
caravel/verilog/rtl/storage.v[Added - diff]
caravel/verilog/rtl/storage_bridge_wb.v[Added - diff]
caravel/verilog/rtl/sysctrl.v[Added - diff]
caravel/verilog/rtl/user_id_programming.v[Added - diff]
caravel/verilog/rtl/wb_intercon.v[Added - diff]

49 files changed

tree: 4f841de1fb748b2cb692d7b076ae196d680002ed

README.md

Caravel User Project

18 bit Adder