instantiate comparator behavioural model
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v index a4a8c1a..e3065b6 100644 --- a/verilog/rtl/user_analog_project_wrapper.v +++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -122,58 +122,21 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_analog_proj_example mprj ( +wire vout; + +assign gpio_analog[17] = vout; +assign io_out[24] = vout + +comparator comp_0 ( `ifdef USE_POWER_PINS - .vdda1(vdda1), // User area 1 3.3V power - .vdda2(vdda2), // User area 2 3.3V power - .vssa1(vssa1), // User area 1 analog ground - .vssa2(vssa2), // User area 2 analog ground - .vccd1(vccd1), // User area 1 1.8V power - .vccd2(vccd2), // User area 2 1.8V power - .vssd1(vssd1), // User area 1 digital ground - .vssd2(vssd2), // User area 2 digital ground + .vdd3v3 (vdda2), // User area 2 3.3V power + .vdd1v8 (vccd2), // User area 2 1.8V power + .vss (vssd2), // User area 2 digital ground `endif - - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - .io_in (io_in), - .io_in_3v3 (io_in_3v3), - .io_out(io_out), - .io_oeb(io_oeb), - - // GPIO-analog - .gpio_analog(gpio_analog), - .gpio_noesd(gpio_noesd), - - // Dedicated analog - .io_analog(io_analog), - .io_clamp_high(io_clamp_high), - .io_clamp_low(io_clamp_low), - - // Clock - .user_clock2(user_clock2), - - // IRQ - .irq(user_irq) + .vout (vout), + .vp (gpio_analog[14]), + .vn (gpio_analog[15]), + .biasn (gpio_analog[16]) ); endmodule // user_analog_project_wrapper