commit | 38ab6891c7a56cb0c0b9870bdae56caa40f4dddc | [log] [tgz] |
---|---|---|
author | H-S-S-11 <harry@snell.org.uk> | Fri Oct 08 16:04:57 2021 +0100 |
committer | H-S-S-11 <harry@snell.org.uk> | Fri Oct 08 16:04:57 2021 +0100 |
tree | 7b44546bb071573ad6e2a311dd919f5af257f002 | |
parent | 10b25e4997c89c98f9cb62fd69ffca7b5a92eaf5 [diff] |
make comparator verilog model
Collection of analog and mixed signal test circuits.
Basic goal: a comparator based on the circuit in “CMOS Design” (Jacob Baker).
Extra goals:
Refer to README for the sample project documentation.