commit eb5a605e11b9d31b9450f4e84830732ad781c409
author mrg <mrg@ucsc.edu> Thu Jun 17 11:52:38 2021 -0700
committer mrg <mrg@ucsc.edu> Thu Jun 17 11:52:38 2021 -0700
tree f94106246b556c12ac3cc077804280dff202d500
parent 8bde8f85b6c4b247c9657a1599751366bef362f3
parent d617e93156c0e08af3f4da9ee3b3925994ceb63d

Merge branch 'main' of github.com:AmoghLonkar/openram_testchip into main

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9885f23..2d92416 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -105,7 +105,7 @@
    // Only io_out[21] is output
    assign io_oeb = ~(1'b1 << 21);
    // Assign other outputs to 0
-   assign io_out[`MPRJ_IO_PADS:22] = 0;
+   assign io_out[`MPRJ_IO_PADS-1:22] = 0;
    wire     gpio_out;
    assign io_out[21] = gpio_out;
    assign io_out[20:0] = 0;