final gds oasis
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/gds.info b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/gds.info
new file mode 100644
index 0000000..d5cf800
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: b1a54329abec9ddabd4ced34b12620986a98ae1a
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/git.info b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/git.info
new file mode 100644
index 0000000..0923b31
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino.git
+Branch: master
+Commit: cb2d94c54d1906072380d2d58384c95d538c3a7a
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.log
new file mode 100644
index 0000000..b7f587b
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+    Elapsed: 0.160s  Memory: 829.00M
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+    Elapsed: 0.100s  Memory: 829.00M
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+DRC section
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+START: 67/44 (mcon)
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+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_beol_check.xml ..
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diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.log
new file mode 100644
index 0000000..db8ee22
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.log
@@ -0,0 +1,728 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 103.570s  Memory: 1611.00M
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..3932fb8
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.log
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+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 74.380s  Memory: 1273.00M
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..cbaa2bd
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.log
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+"ongrid" in: offgrid.lydrc:189
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 2026.00M
+"output" in: offgrid.lydrc:189
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:190
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:190
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:191
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 2026.00M
+"output" in: offgrid.lydrc:191
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:192
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:192
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:193
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 2026.00M
+"output" in: offgrid.lydrc:193
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:194
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:194
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:195
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.220s  Memory: 2026.00M
+"output" in: offgrid.lydrc:195
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:196
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:196
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:197
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.220s  Memory: 2026.00M
+"output" in: offgrid.lydrc:197
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:198
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:198
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:199
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 2026.00M
+"output" in: offgrid.lydrc:199
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:200
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:200
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:201
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.220s  Memory: 2026.00M
+"output" in: offgrid.lydrc:201
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"with_angle" in: offgrid.lydrc:202
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"output" in: offgrid.lydrc:202
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+"ongrid" in: offgrid.lydrc:203
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 2026.00M
+"output" in: offgrid.lydrc:203
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2026.00M
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 174.770s  Memory: 1947.00M
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..ad5f1b7
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 2330288 kB
+VmHWM:	 1019360 kB
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..1d95935
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper_no_zero_areas.gds
+VmPeak:	 1472780 kB
+VmHWM:	 1134072 kB
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.log
new file mode 100644
index 0000000..f19cd53
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.log
@@ -0,0 +1,550 @@
+
+Magic 8.3 revision 241 - Compiled on Fri Dec 17 23:56:38 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Skipping bad "port" line: port 64 nsew default
+Skipping bad "port" line: port 65 nsew default
+Skipping bad "port" line: port 66 nsew default
+Skipping bad "port" line: port 67 nsew default
+Skipping bad "port" line: port 68 nsew default
+Skipping bad "port" line: port 69 nsew default
+Skipping bad "port" line: port 70 nsew default
+Skipping bad "port" line: port 71 nsew default
+Skipping bad "port" line: port 72 nsew default
+Skipping bad "port" line: port 73 nsew default
+Skipping bad "port" line: port 74 nsew default
+Skipping bad "port" line: port 75 nsew default
+Skipping bad "port" line: port 76 nsew default
+Skipping bad "port" line: port 77 nsew default
+Skipping bad "port" line: port 78 nsew default
+Skipping bad "port" line: port 79 nsew default
+Skipping bad "port" line: port 80 nsew default
+Skipping bad "port" line: port 81 nsew default
+Skipping bad "port" line: port 82 nsew default
+Skipping bad "port" line: port 83 nsew default
+Skipping bad "port" line: port 84 nsew default
+Skipping bad "port" line: port 85 nsew default
+Skipping bad "port" line: port 86 nsew default
+Skipping bad "port" line: port 87 nsew default
+Skipping bad "port" line: port 88 nsew default
+Skipping bad "port" line: port 89 nsew default
+Skipping bad "port" line: port 90 nsew default
+Skipping bad "port" line: port 91 nsew default
+Skipping bad "port" line: port 92 nsew default
+Skipping bad "port" line: port 93 nsew default
+Skipping bad "port" line: port 94 nsew default
+Skipping bad "port" line: port 95 nsew default
+Skipping bad "port" line: port 96 nsew default
+Skipping bad "port" line: port 97 nsew default
+Skipping bad "port" line: port 98 nsew default
+Skipping bad "port" line: port 99 nsew default
+Skipping bad "port" line: port 100 nsew default
+Skipping bad "port" line: port 101 nsew default
+Skipping bad "port" line: port 102 nsew default
+Skipping bad "port" line: port 103 nsew default
+Skipping bad "port" line: port 104 nsew default
+Skipping bad "port" line: port 105 nsew default
+Skipping bad "port" line: port 106 nsew default
+Skipping bad "port" line: port 107 nsew default
+Skipping bad "port" line: port 108 nsew default
+Skipping bad "port" line: port 109 nsew default
+Skipping bad "port" line: port 110 nsew default
+Skipping bad "port" line: port 111 nsew default
+Skipping bad "port" line: port 112 nsew default
+Skipping bad "port" line: port 113 nsew default
+Skipping bad "port" line: port 114 nsew default
+Skipping bad "port" line: port 115 nsew default
+Skipping bad "port" line: port 116 nsew default
+Skipping bad "port" line: port 117 nsew default
+Skipping bad "port" line: port 118 nsew default
+Skipping bad "port" line: port 119 nsew default
+Skipping bad "port" line: port 120 nsew default
+Skipping bad "port" line: port 121 nsew default
+Skipping bad "port" line: port 122 nsew default
+Skipping bad "port" line: port 123 nsew default
+Ignoring unknown "port" use: powerIgnoring unknown "port" use: powerIgnoring unknown "port" use: powerIgnoring unknown "port" use: powerIgnoring unknown "port" use: groundIgnoring unknown "port" use: groundIgnoring unknown "port" use: groundIgnoring unknown "port" use: groundWarning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__a2111o_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__clkinvlp_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "scr1_top_wb".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "mbist_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "pinmux".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/pdks.info b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/pdks.info
new file mode 100644
index 0000000..81cfbcc
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 13207762cf4eb2e2943be51bf1605f2bb2bac41d
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/precheck.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/precheck.log
new file mode 100644
index 0000000..5e3bd7b
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/precheck.log
@@ -0,0 +1,88 @@
+2021-12-22 08:04:49 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino.git | Branch: master | Commit: cb2d94c54d1906072380d2d58384c95d538c3a7a
+2021-12-22 08:04:49 - [INFO] - {{INSTALLING CARAVEL}} Running `Make Install` in riscduino
+2021-12-22 08:04:49 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: riscduino
+2021-12-22 08:04:55 - [INFO] - {{Project GDS Info}} user_project_wrapper: b1a54329abec9ddabd4ced34b12620986a98ae1a
+2021-12-22 08:04:55 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.241
+2021-12-22 08:04:55 - [INFO] - {{PDKs Info}} Open PDKs: 13207762cf4eb2e2943be51bf1605f2bb2bac41d | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2021-12-22 08:04:55 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs'
+2021-12-22 08:04:55 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
+2021-12-22 08:04:55 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2021-12-22 08:04:56 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino.
+2021-12-22 08:04:56 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2021-12-22 08:04:57 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino.
+2021-12-22 08:04:57 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v): 'utf-8' codec can't decode byte 0x91 in position 5970: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv): 'utf-8' codec can't decode byte 0xa9 in position 4875: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh): 'utf-8' codec can't decode byte 0xa9 in position 4377: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
+2021-12-22 08:04:58 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 294 non-compliant file(s) with the SPDX Standard.
+2021-12-22 08:04:58 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino/run_regress', 'riscduino/Makefile', 'riscduino/sta/base.sdc', 'riscduino/sta/Makefile', 'riscduino/sta/run_sta', 'riscduino/sta/scripts/or_write_verilog.tcl', 'riscduino/sta/scripts/sta.tcl', 'riscduino/sta/scripts/caravel_timing.tcl', 'riscduino/sta/sdc/caravel.sdc', 'riscduino/verilog/dv/Makefile', 'riscduino/verilog/dv/risc_boot/risc_boot.c', 'riscduino/verilog/dv/risc_boot/risc_boot_tb.v', 'riscduino/verilog/dv/risc_boot/Makefile', 'riscduino/verilog/dv/risc_boot/user_uart.c', 'riscduino/verilog/dv/risc_boot/run_iverilog']
+2021-12-22 08:04:58 - [INFO] - For the full SPDX compliance report check: riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/spdx_compliance_report.log
+2021-12-22 08:04:58 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2021-12-22 08:04:58 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2021-12-22 08:04:58 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2021-12-22 08:04:58 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2021-12-22 08:05:01 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2021-12-22 08:05:01 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2021-12-22 08:05:01 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2021-12-22 08:05:01 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2021-12-22 08:05:01 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/__user_project_wrapper.v
+2021-12-22 08:05:02 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/__user_project_wrapper.v
+2021-12-22 08:05:02 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/defines.v
+2021-12-22 08:05:02 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/defines.v
+2021-12-22 08:05:08 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
+2021-12-22 08:05:08 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
+2021-12-22 08:05:08 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
+2021-12-22 08:05:08 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
+2021-12-22 08:05:08 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2021-12-22 08:05:08 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2021-12-22 08:05:08 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2021-12-22 08:05:08 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (13 instances). 
+2021-12-22 08:05:08 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2021-12-22 08:05:08 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2021-12-22 08:05:08 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2021-12-22 08:05:08 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2021-12-22 08:05:08 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2021-12-22 08:05:09 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2021-12-22 08:05:09 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2021-12-22 08:05:09 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/gds/user_project_wrapper_empty.gds.gz
+2021-12-22 08:05:09 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/gds/user_project_wrapper_empty.gds.gz
+2021-12-22 08:07:30 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.xor.gds
+2021-12-22 08:07:30 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2021-12-22 08:07:30 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2021-12-22 08:23:42 - [INFO] - 0 DRC violations
+2021-12-22 08:23:42 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:23:42 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2021-12-22 08:25:09 - [INFO] - No DRC Violations found
+2021-12-22 08:25:09 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:25:09 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2021-12-22 08:41:45 - [INFO] - No DRC Violations found
+2021-12-22 08:41:45 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:41:45 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2021-12-22 08:44:41 - [INFO] - No DRC Violations found
+2021-12-22 08:44:41 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:44:41 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2021-12-22 08:45:57 - [INFO] - No DRC Violations found
+2021-12-22 08:45:57 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:45:57 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2021-12-22 08:46:29 - [INFO] - No DRC Violations found
+2021-12-22 08:46:29 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:46:29 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2021-12-22 08:46:41 - [INFO] - No DRC Violations found
+2021-12-22 08:46:41 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2021-12-22 08:46:41 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs'
+2021-12-22 08:46:41 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/spdx_compliance_report.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..0238520
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/spdx_compliance_report.log
@@ -0,0 +1,294 @@
+/root/riscduino/run_regress
+/root/riscduino/Makefile
+/root/riscduino/sta/base.sdc
+/root/riscduino/sta/Makefile
+/root/riscduino/sta/run_sta
+/root/riscduino/sta/scripts/or_write_verilog.tcl
+/root/riscduino/sta/scripts/sta.tcl
+/root/riscduino/sta/scripts/caravel_timing.tcl
+/root/riscduino/sta/sdc/caravel.sdc
+/root/riscduino/verilog/dv/Makefile
+/root/riscduino/verilog/dv/risc_boot/risc_boot.c
+/root/riscduino/verilog/dv/risc_boot/risc_boot_tb.v
+/root/riscduino/verilog/dv/risc_boot/Makefile
+/root/riscduino/verilog/dv/risc_boot/user_uart.c
+/root/riscduino/verilog/dv/risc_boot/run_iverilog
+/root/riscduino/verilog/dv/vpi/system/system.c
+/root/riscduino/verilog/dv/user_spi/Makefile
+/root/riscduino/verilog/dv/user_spi/user_spi_tb.v
+/root/riscduino/verilog/dv/user_spi/user_risc_boot.c
+/root/riscduino/verilog/dv/user_spi/run_iverilog
+/root/riscduino/verilog/dv/riscv_regress/user_risc_regress_tb.v
+/root/riscduino/verilog/dv/riscv_regress/riscv_runtests.sv
+/root/riscduino/verilog/dv/riscv_regress/Makefile
+/root/riscduino/verilog/dv/riscv_regress/uprj_netlists.v
+/root/riscduino/verilog/dv/agents/uart_agent.v
+/root/riscduino/verilog/dv/user_i2cm/Makefile
+/root/riscduino/verilog/dv/user_i2cm/user_i2cm_tb.v
+/root/riscduino/verilog/dv/user_i2cm/user_uart.c
+/root/riscduino/verilog/dv/user_i2cm/run_iverilog
+/root/riscduino/verilog/dv/model/s25fl256s.sv
+/root/riscduino/verilog/dv/model/i2c_slave_model.v
+/root/riscduino/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+/root/riscduino/verilog/dv/user_mbist_test1/Makefile
+/root/riscduino/verilog/dv/user_mbist_test1/run_iverilog
+/root/riscduino/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+/root/riscduino/verilog/dv/user_risc_boot/Makefile
+/root/riscduino/verilog/dv/user_risc_boot/user_uart.c
+/root/riscduino/verilog/dv/user_risc_boot/user_risc_boot.c
+/root/riscduino/verilog/dv/user_risc_boot/run_iverilog
+/root/riscduino/verilog/dv/user_basic/user_basic_tb.v
+/root/riscduino/verilog/dv/user_basic/Makefile
+/root/riscduino/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
+/root/riscduino/verilog/dv/user_risc_soft_boot/Makefile
+/root/riscduino/verilog/dv/user_risc_soft_boot/user_risc_boot.c
+/root/riscduino/verilog/dv/user_risc_soft_boot/run_iverilog
+/root/riscduino/verilog/dv/wb_port/wb_port_tb.v
+/root/riscduino/verilog/dv/wb_port/Makefile
+/root/riscduino/verilog/dv/wb_port/run_verilog
+/root/riscduino/verilog/dv/wb_port/wb_port.c
+/root/riscduino/verilog/dv/user_uart/Makefile
+/root/riscduino/verilog/dv/user_uart/user_uart_tb.v
+/root/riscduino/verilog/dv/user_uart/user_uart.c
+/root/riscduino/verilog/dv/user_uart/run_iverilog
+/root/riscduino/verilog/rtl/uprj_netlists.v
+/root/riscduino/verilog/rtl/user_proj_example.v
+/root/riscduino/verilog/rtl/user_project_wrapper.v
+/root/riscduino/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv
+/root/riscduino/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+/root/riscduino/verilog/rtl/wb_interconnect/src/wb_arb.sv
+/root/riscduino/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino/verilog/rtl/wb_host/src/wb_host.sv
+/root/riscduino/verilog/rtl/usb1_host/src/filelist.f
+/root/riscduino/verilog/rtl/usb1_host/src/top/usb1_host.sv
+/root/riscduino/verilog/rtl/usb1_host/src/phy/usb_transceiver.v
+/root/riscduino/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
+/root/riscduino/verilog/rtl/usb1_host/src/includes/usbh_host_defs.v
+/root/riscduino/verilog/rtl/usb1_host/src/core/usbh_sie.sv
+/root/riscduino/verilog/rtl/usb1_host/src/core/usbh_crc5.sv
+/root/riscduino/verilog/rtl/usb1_host/src/core/usbh_core.sv
+/root/riscduino/verilog/rtl/usb1_host/src/core/usbh_crc16.sv
+/root/riscduino/verilog/rtl/usb1_host/src/core/usbh_fifo.sv
+/root/riscduino/verilog/rtl/mbist/run_verilator
+/root/riscduino/verilog/rtl/mbist/run_iverilog
+/root/riscduino/verilog/rtl/mbist/include/mbist_def.svh
+/root/riscduino/verilog/rtl/mbist/src/top/mbist_top2.sv
+/root/riscduino/verilog/rtl/mbist/src/top/mbist_top1.sv
+/root/riscduino/verilog/rtl/mbist/src/top/mbist_top.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_sti_sel.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_fsm.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_pat_sel.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_data_cmp.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_mux.sv
+/root/riscduino/verilog/rtl/mbist/src/core/mbist_op_sel.sv
+/root/riscduino/verilog/rtl/uart_i2c/src/uart_i2c_top.sv
+/root/riscduino/verilog/rtl/sar_adc/DAC_8BIT.v
+/root/riscduino/verilog/rtl/sar_adc/adc_reg.sv
+/root/riscduino/verilog/rtl/sar_adc/ACMP.sv
+/root/riscduino/verilog/rtl/sar_adc/SAR.sv
+/root/riscduino/verilog/rtl/sar_adc/sar_adc.sv
+/root/riscduino/verilog/rtl/sar_adc/ACMP_HVL.v
+/root/riscduino/verilog/rtl/sspim/src/filelist_spi.f
+/root/riscduino/verilog/rtl/sspim/src/sspim_if.sv
+/root/riscduino/verilog/rtl/sspim/src/sspim_ctl.sv
+/root/riscduino/verilog/rtl/sspim/src/sspim_top.sv
+/root/riscduino/verilog/rtl/sspim/src/sspim_cfg.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_fifo.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_top.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_tx.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_rx.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_clkgen.sv
+/root/riscduino/verilog/rtl/qspim/src/filelist.f
+/root/riscduino/verilog/rtl/qspim/src/qspim_ctrl.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_regs.sv
+/root/riscduino/verilog/rtl/qspim/src/qspim_if.sv
+/root/riscduino/verilog/rtl/uart/src/uart_cfg.sv
+/root/riscduino/verilog/rtl/uart/src/uart_core.sv
+/root/riscduino/verilog/rtl/uart/src/uart_txfsm.sv
+/root/riscduino/verilog/rtl/uart/src/uart_rxfsm.sv
+/root/riscduino/verilog/rtl/i2cm/src/includes/i2cm_defines.v
+/root/riscduino/verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+/root/riscduino/verilog/rtl/i2cm/src/core/i2cm_top.v
+/root/riscduino/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+/root/riscduino/verilog/rtl/digital_core/run_modelsim
+/root/riscduino/verilog/rtl/digital_core/filelist_rtl.f
+/root/riscduino/verilog/rtl/digital_core/src/digital_core.sv
+/root/riscduino/verilog/rtl/digital_core/src/glbl_cfg.sv
+/root/riscduino/verilog/rtl/sdram_ctrl/src/run_modelsim
+/root/riscduino/verilog/rtl/sdram_ctrl/src/filelist_rtl.f
+/root/riscduino/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v
+/root/riscduino/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v
+/root/riscduino/verilog/rtl/syntacore/scr1/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h
+/root/riscduino/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h
+/root/riscduino/verilog/rtl/syntacore/scr1/synth/synth.tcl
+/root/riscduino/verilog/rtl/syntacore/scr1/synth/base.sdc
+/root/riscduino/verilog/rtl/syntacore/scr1/synth/run_synth
+/root/riscduino/verilog/rtl/syntacore/scr1/synth/sta.tcl
+/root/riscduino/verilog/rtl/syntacore/scr1/synth/Makefile
+/root/riscduino/verilog/rtl/syntacore/scr1/src/run_modemsim
+/root/riscduino/verilog/rtl/syntacore/scr1/src/wb_top.files
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core.files
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh
+/root/riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh
+/root/riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv
+/root/riscduino/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
+/root/riscduino/verilog/rtl/pinmux/src/pinmux.sv
+/root/riscduino/verilog/rtl/pinmux/src/gpio_control.sv
+/root/riscduino/verilog/rtl/pinmux/src/pwm.sv
+/root/riscduino/verilog/rtl/pinmux/src/pinmux_reg.sv
+/root/riscduino/verilog/rtl/pinmux/src/gpio_intr.sv
+/root/riscduino/verilog/rtl/clk_skew_adjust/synth/synth.tcl
+/root/riscduino/verilog/rtl/clk_skew_adjust/synth/Makefile
+/root/riscduino/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
+/root/riscduino/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
+/root/riscduino/verilog/rtl/lib/pulse_gen_type1.sv
+/root/riscduino/verilog/rtl/lib/async_fifo.sv
+/root/riscduino/verilog/rtl/lib/ctech_cells.sv
+/root/riscduino/verilog/rtl/lib/wb_interface.v
+/root/riscduino/verilog/rtl/lib/reset_sync.sv
+/root/riscduino/verilog/rtl/lib/ser_inf_32b.sv
+/root/riscduino/verilog/rtl/lib/clk_buf.v
+/root/riscduino/verilog/rtl/lib/pulse_gen_type2.sv
+/root/riscduino/verilog/rtl/lib/ser_shift.sv
+/root/riscduino/verilog/rtl/lib/registers.v
+/root/riscduino/verilog/rtl/lib/sync_fifo.sv
+/root/riscduino/verilog/rtl/lib/async_fifo_th.sv
+/root/riscduino/verilog/rtl/lib/wb_stagging.sv
+/root/riscduino/verilog/rtl/lib/double_sync_low.v
+/root/riscduino/verilog/rtl/lib/async_wb.sv
+/root/riscduino/verilog/rtl/lib/double_sync_high.v
+/root/riscduino/verilog/rtl/lib/clk_ctl.v
+/root/riscduino/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+/root/riscduino/gds/.magicrc
+/root/riscduino/openlane/Makefile
+/root/riscduino/openlane/wb_interconnect/pdn.tcl
+/root/riscduino/openlane/wb_interconnect/base.sdc
+/root/riscduino/openlane/wb_interconnect/sta.tcl
+/root/riscduino/openlane/wb_interconnect/config.tcl
+/root/riscduino/openlane/wb_interconnect/interactive.tcl
+/root/riscduino/openlane/mbist1/base.sdc
+/root/riscduino/openlane/mbist1/sta.tcl
+/root/riscduino/openlane/mbist1/config.tcl
+/root/riscduino/openlane/mbist1/interactive.tcl
+/root/riscduino/openlane/wb_host/base.sdc
+/root/riscduino/openlane/wb_host/config.tcl
+/root/riscduino/openlane/wb_host/interactive.tcl
+/root/riscduino/openlane/mbist/base.sdc
+/root/riscduino/openlane/mbist/sta.tcl
+/root/riscduino/openlane/mbist/config.tcl
+/root/riscduino/openlane/mbist/interactive.tcl
+/root/riscduino/openlane/sar_adc/pdn.tcl
+/root/riscduino/openlane/sar_adc/config.tcl
+/root/riscduino/openlane/sar_adc/interactive.tcl
+/root/riscduino/openlane/qspim/pdn.tcl
+/root/riscduino/openlane/qspim/base.sdc
+/root/riscduino/openlane/qspim/sta.tcl
+/root/riscduino/openlane/qspim/config.tcl
+/root/riscduino/openlane/qspim/interactive.tcl
+/root/riscduino/openlane/uart_i2cm_usb_spi/pdn.tcl
+/root/riscduino/openlane/uart_i2cm_usb_spi/base.sdc
+/root/riscduino/openlane/uart_i2cm_usb_spi/sta.tcl
+/root/riscduino/openlane/uart_i2cm_usb_spi/config.tcl
+/root/riscduino/openlane/uart_i2cm_usb_spi/interactive.tcl
+/root/riscduino/openlane/syntacore/pdn.tcl
+/root/riscduino/openlane/syntacore/base.sdc
+/root/riscduino/openlane/syntacore/sta.tcl
+/root/riscduino/openlane/syntacore/config.tcl
+/root/riscduino/openlane/syntacore/interactive.tcl
+/root/riscduino/openlane/pinmux/base.sdc
+/root/riscduino/openlane/pinmux/config.tcl
+/root/riscduino/openlane/pinmux/interactive.tcl
+/root/riscduino/openlane/clk_skew_adjust/config.tcl
+/root/riscduino/openlane/user_project_wrapper/pdn.tcl
+/root/riscduino/openlane/user_project_wrapper/base.sdc
+/root/riscduino/openlane/user_project_wrapper/sta.tcl
+/root/riscduino/openlane/user_project_wrapper/config.tcl
+/root/riscduino/openlane/user_project_wrapper/gen_pdn.tcl
+/root/riscduino/openlane/user_project_wrapper/mod.tcl
+/root/riscduino/openlane/user_project_wrapper/interactive.tcl
+/root/riscduino/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino/spef/qspim_top.spef
+/root/riscduino/spef/user_project_wrapper.spef
+/root/riscduino/spef/scr1_top_wb.spef
+/root/riscduino/spef/wb_host.spef
+/root/riscduino/spef/pinmux.spef
+/root/riscduino/spef/uart_i2c_usb_spi_top.spef
+/root/riscduino/spef/wb_interconnect.spef
+/root/riscduino/spef/mbist_top.spef
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/tools.info b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/tools.info
new file mode 100644
index 0000000..f3795cd
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.5
+Magic: 8.3.241
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.log b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.log
new file mode 100644
index 0000000..233ba02
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.log
@@ -0,0 +1,640 @@
+Reading file /root/riscduino/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 241 - Compiled on Fri Dec 17 23:56:38 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__a2111o_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__clkinvlp_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "scr1_top_wb".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "mbist_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "pinmux".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.88 x 3520.00  (-42.88,  0.00 ), (  0.00,  3520.00)  150937.59 
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.50 x 3520.00  ( 2920.00,  0.00 ), ( 2962.50,  3520.00)  149600.00 
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.53   (-42.88, -37.53), ( 2962.50,  0.00 )  112791.91 
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.21   (-42.88,  3520.00), ( 2962.50,  3557.21)  111830.19 
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 241 - Compiled on Fri Dec 17 23:56:38 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.88 x 3520.00  (-42.88,  0.00 ), (  0.00,  3520.00)  150937.59 
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.50 x 3520.00  ( 2920.00,  0.00 ), ( 2962.50,  3520.00)  149600.00 
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.53   (-42.88, -37.53), ( 2962.50,  0.00 )  112791.91 
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.21   (-42.88,  3520.00), ( 2962.50,  3557.21)  111830.19 
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u5295_dinesha/design/riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.150s  Memory: 523.00M
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.total b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/__user_project_wrapper.v b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/__user_project_wrapper.v
new file mode 100644
index 0000000..98ff3a8
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/__user_project_wrapper.v
@@ -0,0 +1,90 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper.  The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+    parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+// Dummy assignments so that we can take it through the openlane flow
+`ifdef SIM
+// Needed for running GL simulation
+assign io_out = 0;
+assign io_oeb = 0;
+`else
+assign io_out = io_in;
+`endif
+
+endmodule	// user_project_wrapper
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/defines.v b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/defines.v
new file mode 100644
index 0000000..6213b6c
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/defines.v
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19	/* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19	/* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2	/* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2	/* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 1
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO control default mode and enable for most I/Os
+// Most I/Os set to be user input pins on startup.
+// NOTE:  To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
+`define MGMT_INIT 1'b0
+`define OENB_INIT 1'b0
+`define DM_INIT 3'b001
+
+`endif // __GLOBAL_DEFINE_H
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_beol_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_feol_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d3b973b
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,333 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be mnually merge if less : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_met_min_ca_density_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_offgrid_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..fa00f7c
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/offgrid.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..037e5d5
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_zeroarea_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.drc.report b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.rdb b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tcl b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tcl
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tr b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.tr
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.xml b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.filtered.v b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..ea5cc74
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,5324 @@
+module user_project_wrapper (user_clock2,
+    vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
+    vssd1,
+    vssd2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \bist_correct[0] ;
+ wire \bist_correct[1] ;
+ wire \bist_correct[2] ;
+ wire \bist_correct[3] ;
+ wire \bist_correct_rp[0] ;
+ wire \bist_correct_rp[1] ;
+ wire \bist_correct_rp[2] ;
+ wire \bist_correct_rp[3] ;
+ wire bist_done;
+ wire bist_done_rp;
+ wire bist_en;
+ wire bist_en_rp;
+ wire \bist_error[0] ;
+ wire \bist_error[1] ;
+ wire \bist_error[2] ;
+ wire \bist_error[3] ;
+ wire \bist_error_cnt0[0] ;
+ wire \bist_error_cnt0[1] ;
+ wire \bist_error_cnt0[2] ;
+ wire \bist_error_cnt0[3] ;
+ wire \bist_error_cnt0_rp[0] ;
+ wire \bist_error_cnt0_rp[1] ;
+ wire \bist_error_cnt0_rp[2] ;
+ wire \bist_error_cnt0_rp[3] ;
+ wire \bist_error_cnt1[0] ;
+ wire \bist_error_cnt1[1] ;
+ wire \bist_error_cnt1[2] ;
+ wire \bist_error_cnt1[3] ;
+ wire \bist_error_cnt1_rp[0] ;
+ wire \bist_error_cnt1_rp[1] ;
+ wire \bist_error_cnt1_rp[2] ;
+ wire \bist_error_cnt1_rp[3] ;
+ wire \bist_error_cnt2[0] ;
+ wire \bist_error_cnt2[1] ;
+ wire \bist_error_cnt2[2] ;
+ wire \bist_error_cnt2[3] ;
+ wire \bist_error_cnt2_rp[0] ;
+ wire \bist_error_cnt2_rp[1] ;
+ wire \bist_error_cnt2_rp[2] ;
+ wire \bist_error_cnt2_rp[3] ;
+ wire \bist_error_cnt3[0] ;
+ wire \bist_error_cnt3[1] ;
+ wire \bist_error_cnt3[2] ;
+ wire \bist_error_cnt3[3] ;
+ wire \bist_error_cnt3_rp[0] ;
+ wire \bist_error_cnt3_rp[1] ;
+ wire \bist_error_cnt3_rp[2] ;
+ wire \bist_error_cnt3_rp[3] ;
+ wire \bist_error_rp[0] ;
+ wire \bist_error_rp[1] ;
+ wire \bist_error_rp[2] ;
+ wire \bist_error_rp[3] ;
+ wire bist_load;
+ wire bist_load_rp;
+ wire bist_rst_n;
+ wire bist_run;
+ wire bist_run_rp;
+ wire bist_sdi;
+ wire bist_sdi_rp;
+ wire bist_sdo;
+ wire bist_sdo_rp;
+ wire bist_shift;
+ wire bist_shift_rp;
+ wire \boot_remap[0] ;
+ wire \boot_remap[1] ;
+ wire \boot_remap[2] ;
+ wire \boot_remap[3] ;
+ wire \cfg_clk_ctrl1[0] ;
+ wire \cfg_clk_ctrl1[10] ;
+ wire \cfg_clk_ctrl1[11] ;
+ wire \cfg_clk_ctrl1[12] ;
+ wire \cfg_clk_ctrl1[13] ;
+ wire \cfg_clk_ctrl1[14] ;
+ wire \cfg_clk_ctrl1[15] ;
+ wire \cfg_clk_ctrl1[16] ;
+ wire \cfg_clk_ctrl1[17] ;
+ wire \cfg_clk_ctrl1[18] ;
+ wire \cfg_clk_ctrl1[19] ;
+ wire \cfg_clk_ctrl1[1] ;
+ wire \cfg_clk_ctrl1[20] ;
+ wire \cfg_clk_ctrl1[21] ;
+ wire \cfg_clk_ctrl1[22] ;
+ wire \cfg_clk_ctrl1[23] ;
+ wire \cfg_clk_ctrl1[24] ;
+ wire \cfg_clk_ctrl1[25] ;
+ wire \cfg_clk_ctrl1[26] ;
+ wire \cfg_clk_ctrl1[27] ;
+ wire \cfg_clk_ctrl1[28] ;
+ wire \cfg_clk_ctrl1[29] ;
+ wire \cfg_clk_ctrl1[2] ;
+ wire \cfg_clk_ctrl1[30] ;
+ wire \cfg_clk_ctrl1[31] ;
+ wire \cfg_clk_ctrl1[3] ;
+ wire \cfg_clk_ctrl1[4] ;
+ wire \cfg_clk_ctrl1[5] ;
+ wire \cfg_clk_ctrl1[6] ;
+ wire \cfg_clk_ctrl1[7] ;
+ wire \cfg_clk_ctrl1[8] ;
+ wire \cfg_clk_ctrl1[9] ;
+ wire \cfg_clk_ctrl2[0] ;
+ wire \cfg_clk_ctrl2[10] ;
+ wire \cfg_clk_ctrl2[11] ;
+ wire \cfg_clk_ctrl2[12] ;
+ wire \cfg_clk_ctrl2[13] ;
+ wire \cfg_clk_ctrl2[14] ;
+ wire \cfg_clk_ctrl2[15] ;
+ wire \cfg_clk_ctrl2[16] ;
+ wire \cfg_clk_ctrl2[17] ;
+ wire \cfg_clk_ctrl2[18] ;
+ wire \cfg_clk_ctrl2[19] ;
+ wire \cfg_clk_ctrl2[1] ;
+ wire \cfg_clk_ctrl2[20] ;
+ wire \cfg_clk_ctrl2[21] ;
+ wire \cfg_clk_ctrl2[22] ;
+ wire \cfg_clk_ctrl2[23] ;
+ wire \cfg_clk_ctrl2[24] ;
+ wire \cfg_clk_ctrl2[25] ;
+ wire \cfg_clk_ctrl2[26] ;
+ wire \cfg_clk_ctrl2[27] ;
+ wire \cfg_clk_ctrl2[2] ;
+ wire \cfg_clk_ctrl2[3] ;
+ wire \cfg_clk_ctrl2[4] ;
+ wire \cfg_clk_ctrl2[5] ;
+ wire \cfg_clk_ctrl2[6] ;
+ wire \cfg_clk_ctrl2[7] ;
+ wire \cfg_clk_ctrl2[8] ;
+ wire \cfg_clk_ctrl2[9] ;
+ wire \cfg_cska_mbist1_rp[0] ;
+ wire \cfg_cska_mbist1_rp[1] ;
+ wire \cfg_cska_mbist1_rp[2] ;
+ wire \cfg_cska_mbist1_rp[3] ;
+ wire \cfg_cska_mbist2_rp[0] ;
+ wire \cfg_cska_mbist2_rp[1] ;
+ wire \cfg_cska_mbist2_rp[2] ;
+ wire \cfg_cska_mbist2_rp[3] ;
+ wire \cfg_cska_mbist3_rp[0] ;
+ wire \cfg_cska_mbist3_rp[1] ;
+ wire \cfg_cska_mbist3_rp[2] ;
+ wire \cfg_cska_mbist3_rp[3] ;
+ wire \cfg_cska_mbist4_rp[0] ;
+ wire \cfg_cska_mbist4_rp[1] ;
+ wire \cfg_cska_mbist4_rp[2] ;
+ wire \cfg_cska_mbist4_rp[3] ;
+ wire \cfg_cska_pinmux_rp[0] ;
+ wire \cfg_cska_pinmux_rp[1] ;
+ wire \cfg_cska_pinmux_rp[2] ;
+ wire \cfg_cska_pinmux_rp[3] ;
+ wire \cfg_cska_qspi_co_rp[0] ;
+ wire \cfg_cska_qspi_co_rp[1] ;
+ wire \cfg_cska_qspi_co_rp[2] ;
+ wire \cfg_cska_qspi_co_rp[3] ;
+ wire \cfg_cska_qspi_rp[0] ;
+ wire \cfg_cska_qspi_rp[1] ;
+ wire \cfg_cska_qspi_rp[2] ;
+ wire \cfg_cska_qspi_rp[3] ;
+ wire \cfg_cska_riscv_rp[0] ;
+ wire \cfg_cska_riscv_rp[1] ;
+ wire \cfg_cska_riscv_rp[2] ;
+ wire \cfg_cska_riscv_rp[3] ;
+ wire \cfg_cska_uart_rp[0] ;
+ wire \cfg_cska_uart_rp[1] ;
+ wire \cfg_cska_uart_rp[2] ;
+ wire \cfg_cska_uart_rp[3] ;
+ wire cpu_clk;
+ wire cpu_rst_n;
+ wire \fuse_mhartid[0] ;
+ wire \fuse_mhartid[10] ;
+ wire \fuse_mhartid[11] ;
+ wire \fuse_mhartid[12] ;
+ wire \fuse_mhartid[13] ;
+ wire \fuse_mhartid[14] ;
+ wire \fuse_mhartid[15] ;
+ wire \fuse_mhartid[16] ;
+ wire \fuse_mhartid[17] ;
+ wire \fuse_mhartid[18] ;
+ wire \fuse_mhartid[19] ;
+ wire \fuse_mhartid[1] ;
+ wire \fuse_mhartid[20] ;
+ wire \fuse_mhartid[21] ;
+ wire \fuse_mhartid[22] ;
+ wire \fuse_mhartid[23] ;
+ wire \fuse_mhartid[24] ;
+ wire \fuse_mhartid[25] ;
+ wire \fuse_mhartid[26] ;
+ wire \fuse_mhartid[27] ;
+ wire \fuse_mhartid[28] ;
+ wire \fuse_mhartid[29] ;
+ wire \fuse_mhartid[2] ;
+ wire \fuse_mhartid[30] ;
+ wire \fuse_mhartid[31] ;
+ wire \fuse_mhartid[3] ;
+ wire \fuse_mhartid[4] ;
+ wire \fuse_mhartid[5] ;
+ wire \fuse_mhartid[6] ;
+ wire \fuse_mhartid[7] ;
+ wire \fuse_mhartid[8] ;
+ wire \fuse_mhartid[9] ;
+ wire \fuse_mhartid_rp[0] ;
+ wire \fuse_mhartid_rp[10] ;
+ wire \fuse_mhartid_rp[11] ;
+ wire \fuse_mhartid_rp[12] ;
+ wire \fuse_mhartid_rp[13] ;
+ wire \fuse_mhartid_rp[14] ;
+ wire \fuse_mhartid_rp[15] ;
+ wire \fuse_mhartid_rp[16] ;
+ wire \fuse_mhartid_rp[17] ;
+ wire \fuse_mhartid_rp[18] ;
+ wire \fuse_mhartid_rp[19] ;
+ wire \fuse_mhartid_rp[1] ;
+ wire \fuse_mhartid_rp[20] ;
+ wire \fuse_mhartid_rp[21] ;
+ wire \fuse_mhartid_rp[22] ;
+ wire \fuse_mhartid_rp[23] ;
+ wire \fuse_mhartid_rp[24] ;
+ wire \fuse_mhartid_rp[25] ;
+ wire \fuse_mhartid_rp[26] ;
+ wire \fuse_mhartid_rp[27] ;
+ wire \fuse_mhartid_rp[28] ;
+ wire \fuse_mhartid_rp[29] ;
+ wire \fuse_mhartid_rp[2] ;
+ wire \fuse_mhartid_rp[30] ;
+ wire \fuse_mhartid_rp[31] ;
+ wire \fuse_mhartid_rp[3] ;
+ wire \fuse_mhartid_rp[4] ;
+ wire \fuse_mhartid_rp[5] ;
+ wire \fuse_mhartid_rp[6] ;
+ wire \fuse_mhartid_rp[7] ;
+ wire \fuse_mhartid_rp[8] ;
+ wire \fuse_mhartid_rp[9] ;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire \irq_lines_rp[0] ;
+ wire \irq_lines_rp[10] ;
+ wire \irq_lines_rp[11] ;
+ wire \irq_lines_rp[12] ;
+ wire \irq_lines_rp[13] ;
+ wire \irq_lines_rp[14] ;
+ wire \irq_lines_rp[15] ;
+ wire \irq_lines_rp[1] ;
+ wire \irq_lines_rp[2] ;
+ wire \irq_lines_rp[3] ;
+ wire \irq_lines_rp[4] ;
+ wire \irq_lines_rp[5] ;
+ wire \irq_lines_rp[6] ;
+ wire \irq_lines_rp[7] ;
+ wire \irq_lines_rp[8] ;
+ wire \irq_lines_rp[9] ;
+ wire \mem0_addr_a[10] ;
+ wire \mem0_addr_a[2] ;
+ wire \mem0_addr_a[3] ;
+ wire \mem0_addr_a[4] ;
+ wire \mem0_addr_a[5] ;
+ wire \mem0_addr_a[6] ;
+ wire \mem0_addr_a[7] ;
+ wire \mem0_addr_a[8] ;
+ wire \mem0_addr_a[9] ;
+ wire \mem0_addr_b[10] ;
+ wire \mem0_addr_b[2] ;
+ wire \mem0_addr_b[3] ;
+ wire \mem0_addr_b[4] ;
+ wire \mem0_addr_b[5] ;
+ wire \mem0_addr_b[6] ;
+ wire \mem0_addr_b[7] ;
+ wire \mem0_addr_b[8] ;
+ wire \mem0_addr_b[9] ;
+ wire \mem0_din_a[0] ;
+ wire \mem0_din_a[10] ;
+ wire \mem0_din_a[11] ;
+ wire \mem0_din_a[12] ;
+ wire \mem0_din_a[13] ;
+ wire \mem0_din_a[14] ;
+ wire \mem0_din_a[15] ;
+ wire \mem0_din_a[16] ;
+ wire \mem0_din_a[17] ;
+ wire \mem0_din_a[18] ;
+ wire \mem0_din_a[19] ;
+ wire \mem0_din_a[1] ;
+ wire \mem0_din_a[20] ;
+ wire \mem0_din_a[21] ;
+ wire \mem0_din_a[22] ;
+ wire \mem0_din_a[23] ;
+ wire \mem0_din_a[24] ;
+ wire \mem0_din_a[25] ;
+ wire \mem0_din_a[26] ;
+ wire \mem0_din_a[27] ;
+ wire \mem0_din_a[28] ;
+ wire \mem0_din_a[29] ;
+ wire \mem0_din_a[2] ;
+ wire \mem0_din_a[30] ;
+ wire \mem0_din_a[31] ;
+ wire \mem0_din_a[3] ;
+ wire \mem0_din_a[4] ;
+ wire \mem0_din_a[5] ;
+ wire \mem0_din_a[6] ;
+ wire \mem0_din_a[7] ;
+ wire \mem0_din_a[8] ;
+ wire \mem0_din_a[9] ;
+ wire \mem0_dout_a[0] ;
+ wire \mem0_dout_a[10] ;
+ wire \mem0_dout_a[11] ;
+ wire \mem0_dout_a[12] ;
+ wire \mem0_dout_a[13] ;
+ wire \mem0_dout_a[14] ;
+ wire \mem0_dout_a[15] ;
+ wire \mem0_dout_a[16] ;
+ wire \mem0_dout_a[17] ;
+ wire \mem0_dout_a[18] ;
+ wire \mem0_dout_a[19] ;
+ wire \mem0_dout_a[1] ;
+ wire \mem0_dout_a[20] ;
+ wire \mem0_dout_a[21] ;
+ wire \mem0_dout_a[22] ;
+ wire \mem0_dout_a[23] ;
+ wire \mem0_dout_a[24] ;
+ wire \mem0_dout_a[25] ;
+ wire \mem0_dout_a[26] ;
+ wire \mem0_dout_a[27] ;
+ wire \mem0_dout_a[28] ;
+ wire \mem0_dout_a[29] ;
+ wire \mem0_dout_a[2] ;
+ wire \mem0_dout_a[30] ;
+ wire \mem0_dout_a[31] ;
+ wire \mem0_dout_a[3] ;
+ wire \mem0_dout_a[4] ;
+ wire \mem0_dout_a[5] ;
+ wire \mem0_dout_a[6] ;
+ wire \mem0_dout_a[7] ;
+ wire \mem0_dout_a[8] ;
+ wire \mem0_dout_a[9] ;
+ wire \mem0_mask_a[0] ;
+ wire \mem0_mask_a[1] ;
+ wire \mem0_mask_a[2] ;
+ wire \mem0_mask_a[3] ;
+ wire \mem1_addr_a[10] ;
+ wire \mem1_addr_a[2] ;
+ wire \mem1_addr_a[3] ;
+ wire \mem1_addr_a[4] ;
+ wire \mem1_addr_a[5] ;
+ wire \mem1_addr_a[6] ;
+ wire \mem1_addr_a[7] ;
+ wire \mem1_addr_a[8] ;
+ wire \mem1_addr_a[9] ;
+ wire \mem1_addr_b[10] ;
+ wire \mem1_addr_b[2] ;
+ wire \mem1_addr_b[3] ;
+ wire \mem1_addr_b[4] ;
+ wire \mem1_addr_b[5] ;
+ wire \mem1_addr_b[6] ;
+ wire \mem1_addr_b[7] ;
+ wire \mem1_addr_b[8] ;
+ wire \mem1_addr_b[9] ;
+ wire \mem1_din_a[0] ;
+ wire \mem1_din_a[10] ;
+ wire \mem1_din_a[11] ;
+ wire \mem1_din_a[12] ;
+ wire \mem1_din_a[13] ;
+ wire \mem1_din_a[14] ;
+ wire \mem1_din_a[15] ;
+ wire \mem1_din_a[16] ;
+ wire \mem1_din_a[17] ;
+ wire \mem1_din_a[18] ;
+ wire \mem1_din_a[19] ;
+ wire \mem1_din_a[1] ;
+ wire \mem1_din_a[20] ;
+ wire \mem1_din_a[21] ;
+ wire \mem1_din_a[22] ;
+ wire \mem1_din_a[23] ;
+ wire \mem1_din_a[24] ;
+ wire \mem1_din_a[25] ;
+ wire \mem1_din_a[26] ;
+ wire \mem1_din_a[27] ;
+ wire \mem1_din_a[28] ;
+ wire \mem1_din_a[29] ;
+ wire \mem1_din_a[2] ;
+ wire \mem1_din_a[30] ;
+ wire \mem1_din_a[31] ;
+ wire \mem1_din_a[3] ;
+ wire \mem1_din_a[4] ;
+ wire \mem1_din_a[5] ;
+ wire \mem1_din_a[6] ;
+ wire \mem1_din_a[7] ;
+ wire \mem1_din_a[8] ;
+ wire \mem1_din_a[9] ;
+ wire \mem1_dout_a[0] ;
+ wire \mem1_dout_a[10] ;
+ wire \mem1_dout_a[11] ;
+ wire \mem1_dout_a[12] ;
+ wire \mem1_dout_a[13] ;
+ wire \mem1_dout_a[14] ;
+ wire \mem1_dout_a[15] ;
+ wire \mem1_dout_a[16] ;
+ wire \mem1_dout_a[17] ;
+ wire \mem1_dout_a[18] ;
+ wire \mem1_dout_a[19] ;
+ wire \mem1_dout_a[1] ;
+ wire \mem1_dout_a[20] ;
+ wire \mem1_dout_a[21] ;
+ wire \mem1_dout_a[22] ;
+ wire \mem1_dout_a[23] ;
+ wire \mem1_dout_a[24] ;
+ wire \mem1_dout_a[25] ;
+ wire \mem1_dout_a[26] ;
+ wire \mem1_dout_a[27] ;
+ wire \mem1_dout_a[28] ;
+ wire \mem1_dout_a[29] ;
+ wire \mem1_dout_a[2] ;
+ wire \mem1_dout_a[30] ;
+ wire \mem1_dout_a[31] ;
+ wire \mem1_dout_a[3] ;
+ wire \mem1_dout_a[4] ;
+ wire \mem1_dout_a[5] ;
+ wire \mem1_dout_a[6] ;
+ wire \mem1_dout_a[7] ;
+ wire \mem1_dout_a[8] ;
+ wire \mem1_dout_a[9] ;
+ wire \mem1_mask_a[0] ;
+ wire \mem1_mask_a[1] ;
+ wire \mem1_mask_a[2] ;
+ wire \mem1_mask_a[3] ;
+ wire \mem2_addr_a[10] ;
+ wire \mem2_addr_a[2] ;
+ wire \mem2_addr_a[3] ;
+ wire \mem2_addr_a[4] ;
+ wire \mem2_addr_a[5] ;
+ wire \mem2_addr_a[6] ;
+ wire \mem2_addr_a[7] ;
+ wire \mem2_addr_a[8] ;
+ wire \mem2_addr_a[9] ;
+ wire \mem2_addr_b[10] ;
+ wire \mem2_addr_b[2] ;
+ wire \mem2_addr_b[3] ;
+ wire \mem2_addr_b[4] ;
+ wire \mem2_addr_b[5] ;
+ wire \mem2_addr_b[6] ;
+ wire \mem2_addr_b[7] ;
+ wire \mem2_addr_b[8] ;
+ wire \mem2_addr_b[9] ;
+ wire \mem2_din_a[0] ;
+ wire \mem2_din_a[10] ;
+ wire \mem2_din_a[11] ;
+ wire \mem2_din_a[12] ;
+ wire \mem2_din_a[13] ;
+ wire \mem2_din_a[14] ;
+ wire \mem2_din_a[15] ;
+ wire \mem2_din_a[16] ;
+ wire \mem2_din_a[17] ;
+ wire \mem2_din_a[18] ;
+ wire \mem2_din_a[19] ;
+ wire \mem2_din_a[1] ;
+ wire \mem2_din_a[20] ;
+ wire \mem2_din_a[21] ;
+ wire \mem2_din_a[22] ;
+ wire \mem2_din_a[23] ;
+ wire \mem2_din_a[24] ;
+ wire \mem2_din_a[25] ;
+ wire \mem2_din_a[26] ;
+ wire \mem2_din_a[27] ;
+ wire \mem2_din_a[28] ;
+ wire \mem2_din_a[29] ;
+ wire \mem2_din_a[2] ;
+ wire \mem2_din_a[30] ;
+ wire \mem2_din_a[31] ;
+ wire \mem2_din_a[3] ;
+ wire \mem2_din_a[4] ;
+ wire \mem2_din_a[5] ;
+ wire \mem2_din_a[6] ;
+ wire \mem2_din_a[7] ;
+ wire \mem2_din_a[8] ;
+ wire \mem2_din_a[9] ;
+ wire \mem2_dout_a[0] ;
+ wire \mem2_dout_a[10] ;
+ wire \mem2_dout_a[11] ;
+ wire \mem2_dout_a[12] ;
+ wire \mem2_dout_a[13] ;
+ wire \mem2_dout_a[14] ;
+ wire \mem2_dout_a[15] ;
+ wire \mem2_dout_a[16] ;
+ wire \mem2_dout_a[17] ;
+ wire \mem2_dout_a[18] ;
+ wire \mem2_dout_a[19] ;
+ wire \mem2_dout_a[1] ;
+ wire \mem2_dout_a[20] ;
+ wire \mem2_dout_a[21] ;
+ wire \mem2_dout_a[22] ;
+ wire \mem2_dout_a[23] ;
+ wire \mem2_dout_a[24] ;
+ wire \mem2_dout_a[25] ;
+ wire \mem2_dout_a[26] ;
+ wire \mem2_dout_a[27] ;
+ wire \mem2_dout_a[28] ;
+ wire \mem2_dout_a[29] ;
+ wire \mem2_dout_a[2] ;
+ wire \mem2_dout_a[30] ;
+ wire \mem2_dout_a[31] ;
+ wire \mem2_dout_a[3] ;
+ wire \mem2_dout_a[4] ;
+ wire \mem2_dout_a[5] ;
+ wire \mem2_dout_a[6] ;
+ wire \mem2_dout_a[7] ;
+ wire \mem2_dout_a[8] ;
+ wire \mem2_dout_a[9] ;
+ wire \mem2_mask_a[0] ;
+ wire \mem2_mask_a[1] ;
+ wire \mem2_mask_a[2] ;
+ wire \mem2_mask_a[3] ;
+ wire \mem3_addr_a[10] ;
+ wire \mem3_addr_a[2] ;
+ wire \mem3_addr_a[3] ;
+ wire \mem3_addr_a[4] ;
+ wire \mem3_addr_a[5] ;
+ wire \mem3_addr_a[6] ;
+ wire \mem3_addr_a[7] ;
+ wire \mem3_addr_a[8] ;
+ wire \mem3_addr_a[9] ;
+ wire \mem3_addr_b[10] ;
+ wire \mem3_addr_b[2] ;
+ wire \mem3_addr_b[3] ;
+ wire \mem3_addr_b[4] ;
+ wire \mem3_addr_b[5] ;
+ wire \mem3_addr_b[6] ;
+ wire \mem3_addr_b[7] ;
+ wire \mem3_addr_b[8] ;
+ wire \mem3_addr_b[9] ;
+ wire \mem3_din_a[0] ;
+ wire \mem3_din_a[10] ;
+ wire \mem3_din_a[11] ;
+ wire \mem3_din_a[12] ;
+ wire \mem3_din_a[13] ;
+ wire \mem3_din_a[14] ;
+ wire \mem3_din_a[15] ;
+ wire \mem3_din_a[16] ;
+ wire \mem3_din_a[17] ;
+ wire \mem3_din_a[18] ;
+ wire \mem3_din_a[19] ;
+ wire \mem3_din_a[1] ;
+ wire \mem3_din_a[20] ;
+ wire \mem3_din_a[21] ;
+ wire \mem3_din_a[22] ;
+ wire \mem3_din_a[23] ;
+ wire \mem3_din_a[24] ;
+ wire \mem3_din_a[25] ;
+ wire \mem3_din_a[26] ;
+ wire \mem3_din_a[27] ;
+ wire \mem3_din_a[28] ;
+ wire \mem3_din_a[29] ;
+ wire \mem3_din_a[2] ;
+ wire \mem3_din_a[30] ;
+ wire \mem3_din_a[31] ;
+ wire \mem3_din_a[3] ;
+ wire \mem3_din_a[4] ;
+ wire \mem3_din_a[5] ;
+ wire \mem3_din_a[6] ;
+ wire \mem3_din_a[7] ;
+ wire \mem3_din_a[8] ;
+ wire \mem3_din_a[9] ;
+ wire \mem3_dout_a[0] ;
+ wire \mem3_dout_a[10] ;
+ wire \mem3_dout_a[11] ;
+ wire \mem3_dout_a[12] ;
+ wire \mem3_dout_a[13] ;
+ wire \mem3_dout_a[14] ;
+ wire \mem3_dout_a[15] ;
+ wire \mem3_dout_a[16] ;
+ wire \mem3_dout_a[17] ;
+ wire \mem3_dout_a[18] ;
+ wire \mem3_dout_a[19] ;
+ wire \mem3_dout_a[1] ;
+ wire \mem3_dout_a[20] ;
+ wire \mem3_dout_a[21] ;
+ wire \mem3_dout_a[22] ;
+ wire \mem3_dout_a[23] ;
+ wire \mem3_dout_a[24] ;
+ wire \mem3_dout_a[25] ;
+ wire \mem3_dout_a[26] ;
+ wire \mem3_dout_a[27] ;
+ wire \mem3_dout_a[28] ;
+ wire \mem3_dout_a[29] ;
+ wire \mem3_dout_a[2] ;
+ wire \mem3_dout_a[30] ;
+ wire \mem3_dout_a[31] ;
+ wire \mem3_dout_a[3] ;
+ wire \mem3_dout_a[4] ;
+ wire \mem3_dout_a[5] ;
+ wire \mem3_dout_a[6] ;
+ wire \mem3_dout_a[7] ;
+ wire \mem3_dout_a[8] ;
+ wire \mem3_dout_a[9] ;
+ wire \mem3_mask_a[0] ;
+ wire \mem3_mask_a[1] ;
+ wire \mem3_mask_a[2] ;
+ wire \mem3_mask_a[3] ;
+ wire \mem_cen_a[0] ;
+ wire \mem_cen_a[1] ;
+ wire \mem_cen_a[2] ;
+ wire \mem_cen_a[3] ;
+ wire \mem_cen_b[0] ;
+ wire \mem_cen_b[1] ;
+ wire \mem_cen_b[2] ;
+ wire \mem_cen_b[3] ;
+ wire \mem_clk_a[0] ;
+ wire \mem_clk_a[1] ;
+ wire \mem_clk_a[2] ;
+ wire \mem_clk_a[3] ;
+ wire \mem_clk_b[0] ;
+ wire \mem_clk_b[1] ;
+ wire \mem_clk_b[2] ;
+ wire \mem_clk_b[3] ;
+ wire \mem_web_a[0] ;
+ wire \mem_web_a[1] ;
+ wire \mem_web_a[2] ;
+ wire \mem_web_a[3] ;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire rtc_clk;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire sflash_ss;
+ wire soft_irq;
+ wire soft_irq_rp;
+ wire \sram0_addr0[0] ;
+ wire \sram0_addr0[1] ;
+ wire \sram0_addr0[2] ;
+ wire \sram0_addr0[3] ;
+ wire \sram0_addr0[4] ;
+ wire \sram0_addr0[5] ;
+ wire \sram0_addr0[6] ;
+ wire \sram0_addr0[7] ;
+ wire \sram0_addr0[8] ;
+ wire \sram0_addr1[0] ;
+ wire \sram0_addr1[1] ;
+ wire \sram0_addr1[2] ;
+ wire \sram0_addr1[3] ;
+ wire \sram0_addr1[4] ;
+ wire \sram0_addr1[5] ;
+ wire \sram0_addr1[6] ;
+ wire \sram0_addr1[7] ;
+ wire \sram0_addr1[8] ;
+ wire sram0_clk0;
+ wire sram0_clk1;
+ wire sram0_csb0;
+ wire sram0_csb1;
+ wire \sram0_din0[0] ;
+ wire \sram0_din0[10] ;
+ wire \sram0_din0[11] ;
+ wire \sram0_din0[12] ;
+ wire \sram0_din0[13] ;
+ wire \sram0_din0[14] ;
+ wire \sram0_din0[15] ;
+ wire \sram0_din0[16] ;
+ wire \sram0_din0[17] ;
+ wire \sram0_din0[18] ;
+ wire \sram0_din0[19] ;
+ wire \sram0_din0[1] ;
+ wire \sram0_din0[20] ;
+ wire \sram0_din0[21] ;
+ wire \sram0_din0[22] ;
+ wire \sram0_din0[23] ;
+ wire \sram0_din0[24] ;
+ wire \sram0_din0[25] ;
+ wire \sram0_din0[26] ;
+ wire \sram0_din0[27] ;
+ wire \sram0_din0[28] ;
+ wire \sram0_din0[29] ;
+ wire \sram0_din0[2] ;
+ wire \sram0_din0[30] ;
+ wire \sram0_din0[31] ;
+ wire \sram0_din0[3] ;
+ wire \sram0_din0[4] ;
+ wire \sram0_din0[5] ;
+ wire \sram0_din0[6] ;
+ wire \sram0_din0[7] ;
+ wire \sram0_din0[8] ;
+ wire \sram0_din0[9] ;
+ wire \sram0_dout0[0] ;
+ wire \sram0_dout0[10] ;
+ wire \sram0_dout0[11] ;
+ wire \sram0_dout0[12] ;
+ wire \sram0_dout0[13] ;
+ wire \sram0_dout0[14] ;
+ wire \sram0_dout0[15] ;
+ wire \sram0_dout0[16] ;
+ wire \sram0_dout0[17] ;
+ wire \sram0_dout0[18] ;
+ wire \sram0_dout0[19] ;
+ wire \sram0_dout0[1] ;
+ wire \sram0_dout0[20] ;
+ wire \sram0_dout0[21] ;
+ wire \sram0_dout0[22] ;
+ wire \sram0_dout0[23] ;
+ wire \sram0_dout0[24] ;
+ wire \sram0_dout0[25] ;
+ wire \sram0_dout0[26] ;
+ wire \sram0_dout0[27] ;
+ wire \sram0_dout0[28] ;
+ wire \sram0_dout0[29] ;
+ wire \sram0_dout0[2] ;
+ wire \sram0_dout0[30] ;
+ wire \sram0_dout0[31] ;
+ wire \sram0_dout0[3] ;
+ wire \sram0_dout0[4] ;
+ wire \sram0_dout0[5] ;
+ wire \sram0_dout0[6] ;
+ wire \sram0_dout0[7] ;
+ wire \sram0_dout0[8] ;
+ wire \sram0_dout0[9] ;
+ wire \sram0_dout1[0] ;
+ wire \sram0_dout1[10] ;
+ wire \sram0_dout1[11] ;
+ wire \sram0_dout1[12] ;
+ wire \sram0_dout1[13] ;
+ wire \sram0_dout1[14] ;
+ wire \sram0_dout1[15] ;
+ wire \sram0_dout1[16] ;
+ wire \sram0_dout1[17] ;
+ wire \sram0_dout1[18] ;
+ wire \sram0_dout1[19] ;
+ wire \sram0_dout1[1] ;
+ wire \sram0_dout1[20] ;
+ wire \sram0_dout1[21] ;
+ wire \sram0_dout1[22] ;
+ wire \sram0_dout1[23] ;
+ wire \sram0_dout1[24] ;
+ wire \sram0_dout1[25] ;
+ wire \sram0_dout1[26] ;
+ wire \sram0_dout1[27] ;
+ wire \sram0_dout1[28] ;
+ wire \sram0_dout1[29] ;
+ wire \sram0_dout1[2] ;
+ wire \sram0_dout1[30] ;
+ wire \sram0_dout1[31] ;
+ wire \sram0_dout1[3] ;
+ wire \sram0_dout1[4] ;
+ wire \sram0_dout1[5] ;
+ wire \sram0_dout1[6] ;
+ wire \sram0_dout1[7] ;
+ wire \sram0_dout1[8] ;
+ wire \sram0_dout1[9] ;
+ wire sram0_web0;
+ wire \sram0_wmask0[0] ;
+ wire \sram0_wmask0[1] ;
+ wire \sram0_wmask0[2] ;
+ wire \sram0_wmask0[3] ;
+ wire \sram1_addr0[0] ;
+ wire \sram1_addr0[1] ;
+ wire \sram1_addr0[2] ;
+ wire \sram1_addr0[3] ;
+ wire \sram1_addr0[4] ;
+ wire \sram1_addr0[5] ;
+ wire \sram1_addr0[6] ;
+ wire \sram1_addr0[7] ;
+ wire \sram1_addr0[8] ;
+ wire \sram1_addr1[0] ;
+ wire \sram1_addr1[1] ;
+ wire \sram1_addr1[2] ;
+ wire \sram1_addr1[3] ;
+ wire \sram1_addr1[4] ;
+ wire \sram1_addr1[5] ;
+ wire \sram1_addr1[6] ;
+ wire \sram1_addr1[7] ;
+ wire \sram1_addr1[8] ;
+ wire sram1_clk0;
+ wire sram1_clk1;
+ wire sram1_csb0;
+ wire sram1_csb1;
+ wire \sram1_din0[0] ;
+ wire \sram1_din0[10] ;
+ wire \sram1_din0[11] ;
+ wire \sram1_din0[12] ;
+ wire \sram1_din0[13] ;
+ wire \sram1_din0[14] ;
+ wire \sram1_din0[15] ;
+ wire \sram1_din0[16] ;
+ wire \sram1_din0[17] ;
+ wire \sram1_din0[18] ;
+ wire \sram1_din0[19] ;
+ wire \sram1_din0[1] ;
+ wire \sram1_din0[20] ;
+ wire \sram1_din0[21] ;
+ wire \sram1_din0[22] ;
+ wire \sram1_din0[23] ;
+ wire \sram1_din0[24] ;
+ wire \sram1_din0[25] ;
+ wire \sram1_din0[26] ;
+ wire \sram1_din0[27] ;
+ wire \sram1_din0[28] ;
+ wire \sram1_din0[29] ;
+ wire \sram1_din0[2] ;
+ wire \sram1_din0[30] ;
+ wire \sram1_din0[31] ;
+ wire \sram1_din0[3] ;
+ wire \sram1_din0[4] ;
+ wire \sram1_din0[5] ;
+ wire \sram1_din0[6] ;
+ wire \sram1_din0[7] ;
+ wire \sram1_din0[8] ;
+ wire \sram1_din0[9] ;
+ wire \sram1_dout0[0] ;
+ wire \sram1_dout0[10] ;
+ wire \sram1_dout0[11] ;
+ wire \sram1_dout0[12] ;
+ wire \sram1_dout0[13] ;
+ wire \sram1_dout0[14] ;
+ wire \sram1_dout0[15] ;
+ wire \sram1_dout0[16] ;
+ wire \sram1_dout0[17] ;
+ wire \sram1_dout0[18] ;
+ wire \sram1_dout0[19] ;
+ wire \sram1_dout0[1] ;
+ wire \sram1_dout0[20] ;
+ wire \sram1_dout0[21] ;
+ wire \sram1_dout0[22] ;
+ wire \sram1_dout0[23] ;
+ wire \sram1_dout0[24] ;
+ wire \sram1_dout0[25] ;
+ wire \sram1_dout0[26] ;
+ wire \sram1_dout0[27] ;
+ wire \sram1_dout0[28] ;
+ wire \sram1_dout0[29] ;
+ wire \sram1_dout0[2] ;
+ wire \sram1_dout0[30] ;
+ wire \sram1_dout0[31] ;
+ wire \sram1_dout0[3] ;
+ wire \sram1_dout0[4] ;
+ wire \sram1_dout0[5] ;
+ wire \sram1_dout0[6] ;
+ wire \sram1_dout0[7] ;
+ wire \sram1_dout0[8] ;
+ wire \sram1_dout0[9] ;
+ wire \sram1_dout1[0] ;
+ wire \sram1_dout1[10] ;
+ wire \sram1_dout1[11] ;
+ wire \sram1_dout1[12] ;
+ wire \sram1_dout1[13] ;
+ wire \sram1_dout1[14] ;
+ wire \sram1_dout1[15] ;
+ wire \sram1_dout1[16] ;
+ wire \sram1_dout1[17] ;
+ wire \sram1_dout1[18] ;
+ wire \sram1_dout1[19] ;
+ wire \sram1_dout1[1] ;
+ wire \sram1_dout1[20] ;
+ wire \sram1_dout1[21] ;
+ wire \sram1_dout1[22] ;
+ wire \sram1_dout1[23] ;
+ wire \sram1_dout1[24] ;
+ wire \sram1_dout1[25] ;
+ wire \sram1_dout1[26] ;
+ wire \sram1_dout1[27] ;
+ wire \sram1_dout1[28] ;
+ wire \sram1_dout1[29] ;
+ wire \sram1_dout1[2] ;
+ wire \sram1_dout1[30] ;
+ wire \sram1_dout1[31] ;
+ wire \sram1_dout1[3] ;
+ wire \sram1_dout1[4] ;
+ wire \sram1_dout1[5] ;
+ wire \sram1_dout1[6] ;
+ wire \sram1_dout1[7] ;
+ wire \sram1_dout1[8] ;
+ wire \sram1_dout1[9] ;
+ wire sram1_web0;
+ wire \sram1_wmask0[0] ;
+ wire \sram1_wmask0[1] ;
+ wire \sram1_wmask0[2] ;
+ wire \sram1_wmask0[3] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire sspim_ssn;
+ wire uart_rst_n;
+ wire uart_rxd;
+ wire uart_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_mbist1_rp;
+ wire wbd_clk_mbist2_rp;
+ wire wbd_clk_mbist3_rp;
+ wire wbd_clk_mbist4_rp;
+ wire wbd_clk_mbist_skew;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_risc_rp;
+ wire wbd_clk_riscv_skew;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire wbd_int_rst_n;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_mbist_ack_i;
+ wire \wbd_mbist_adr_o[0] ;
+ wire \wbd_mbist_adr_o[10] ;
+ wire \wbd_mbist_adr_o[11] ;
+ wire \wbd_mbist_adr_o[12] ;
+ wire \wbd_mbist_adr_o[1] ;
+ wire \wbd_mbist_adr_o[2] ;
+ wire \wbd_mbist_adr_o[3] ;
+ wire \wbd_mbist_adr_o[4] ;
+ wire \wbd_mbist_adr_o[5] ;
+ wire \wbd_mbist_adr_o[6] ;
+ wire \wbd_mbist_adr_o[7] ;
+ wire \wbd_mbist_adr_o[8] ;
+ wire \wbd_mbist_adr_o[9] ;
+ wire wbd_mbist_cyc_o;
+ wire \wbd_mbist_dat_i[0] ;
+ wire \wbd_mbist_dat_i[10] ;
+ wire \wbd_mbist_dat_i[11] ;
+ wire \wbd_mbist_dat_i[12] ;
+ wire \wbd_mbist_dat_i[13] ;
+ wire \wbd_mbist_dat_i[14] ;
+ wire \wbd_mbist_dat_i[15] ;
+ wire \wbd_mbist_dat_i[16] ;
+ wire \wbd_mbist_dat_i[17] ;
+ wire \wbd_mbist_dat_i[18] ;
+ wire \wbd_mbist_dat_i[19] ;
+ wire \wbd_mbist_dat_i[1] ;
+ wire \wbd_mbist_dat_i[20] ;
+ wire \wbd_mbist_dat_i[21] ;
+ wire \wbd_mbist_dat_i[22] ;
+ wire \wbd_mbist_dat_i[23] ;
+ wire \wbd_mbist_dat_i[24] ;
+ wire \wbd_mbist_dat_i[25] ;
+ wire \wbd_mbist_dat_i[26] ;
+ wire \wbd_mbist_dat_i[27] ;
+ wire \wbd_mbist_dat_i[28] ;
+ wire \wbd_mbist_dat_i[29] ;
+ wire \wbd_mbist_dat_i[2] ;
+ wire \wbd_mbist_dat_i[30] ;
+ wire \wbd_mbist_dat_i[31] ;
+ wire \wbd_mbist_dat_i[3] ;
+ wire \wbd_mbist_dat_i[4] ;
+ wire \wbd_mbist_dat_i[5] ;
+ wire \wbd_mbist_dat_i[6] ;
+ wire \wbd_mbist_dat_i[7] ;
+ wire \wbd_mbist_dat_i[8] ;
+ wire \wbd_mbist_dat_i[9] ;
+ wire \wbd_mbist_dat_o[0] ;
+ wire \wbd_mbist_dat_o[10] ;
+ wire \wbd_mbist_dat_o[11] ;
+ wire \wbd_mbist_dat_o[12] ;
+ wire \wbd_mbist_dat_o[13] ;
+ wire \wbd_mbist_dat_o[14] ;
+ wire \wbd_mbist_dat_o[15] ;
+ wire \wbd_mbist_dat_o[16] ;
+ wire \wbd_mbist_dat_o[17] ;
+ wire \wbd_mbist_dat_o[18] ;
+ wire \wbd_mbist_dat_o[19] ;
+ wire \wbd_mbist_dat_o[1] ;
+ wire \wbd_mbist_dat_o[20] ;
+ wire \wbd_mbist_dat_o[21] ;
+ wire \wbd_mbist_dat_o[22] ;
+ wire \wbd_mbist_dat_o[23] ;
+ wire \wbd_mbist_dat_o[24] ;
+ wire \wbd_mbist_dat_o[25] ;
+ wire \wbd_mbist_dat_o[26] ;
+ wire \wbd_mbist_dat_o[27] ;
+ wire \wbd_mbist_dat_o[28] ;
+ wire \wbd_mbist_dat_o[29] ;
+ wire \wbd_mbist_dat_o[2] ;
+ wire \wbd_mbist_dat_o[30] ;
+ wire \wbd_mbist_dat_o[31] ;
+ wire \wbd_mbist_dat_o[3] ;
+ wire \wbd_mbist_dat_o[4] ;
+ wire \wbd_mbist_dat_o[5] ;
+ wire \wbd_mbist_dat_o[6] ;
+ wire \wbd_mbist_dat_o[7] ;
+ wire \wbd_mbist_dat_o[8] ;
+ wire \wbd_mbist_dat_o[9] ;
+ wire \wbd_mbist_sel_o[0] ;
+ wire \wbd_mbist_sel_o[1] ;
+ wire \wbd_mbist_sel_o[2] ;
+ wire \wbd_mbist_sel_o[3] ;
+ wire wbd_mbist_stb_o;
+ wire wbd_mbist_we_o;
+ wire wbd_riscv_dmem_ack_o;
+ wire \wbd_riscv_dmem_adr_i[0] ;
+ wire \wbd_riscv_dmem_adr_i[10] ;
+ wire \wbd_riscv_dmem_adr_i[11] ;
+ wire \wbd_riscv_dmem_adr_i[12] ;
+ wire \wbd_riscv_dmem_adr_i[13] ;
+ wire \wbd_riscv_dmem_adr_i[14] ;
+ wire \wbd_riscv_dmem_adr_i[15] ;
+ wire \wbd_riscv_dmem_adr_i[16] ;
+ wire \wbd_riscv_dmem_adr_i[17] ;
+ wire \wbd_riscv_dmem_adr_i[18] ;
+ wire \wbd_riscv_dmem_adr_i[19] ;
+ wire \wbd_riscv_dmem_adr_i[1] ;
+ wire \wbd_riscv_dmem_adr_i[20] ;
+ wire \wbd_riscv_dmem_adr_i[21] ;
+ wire \wbd_riscv_dmem_adr_i[22] ;
+ wire \wbd_riscv_dmem_adr_i[23] ;
+ wire \wbd_riscv_dmem_adr_i[24] ;
+ wire \wbd_riscv_dmem_adr_i[25] ;
+ wire \wbd_riscv_dmem_adr_i[26] ;
+ wire \wbd_riscv_dmem_adr_i[27] ;
+ wire \wbd_riscv_dmem_adr_i[28] ;
+ wire \wbd_riscv_dmem_adr_i[29] ;
+ wire \wbd_riscv_dmem_adr_i[2] ;
+ wire \wbd_riscv_dmem_adr_i[30] ;
+ wire \wbd_riscv_dmem_adr_i[31] ;
+ wire \wbd_riscv_dmem_adr_i[3] ;
+ wire \wbd_riscv_dmem_adr_i[4] ;
+ wire \wbd_riscv_dmem_adr_i[5] ;
+ wire \wbd_riscv_dmem_adr_i[6] ;
+ wire \wbd_riscv_dmem_adr_i[7] ;
+ wire \wbd_riscv_dmem_adr_i[8] ;
+ wire \wbd_riscv_dmem_adr_i[9] ;
+ wire \wbd_riscv_dmem_dat_i[0] ;
+ wire \wbd_riscv_dmem_dat_i[10] ;
+ wire \wbd_riscv_dmem_dat_i[11] ;
+ wire \wbd_riscv_dmem_dat_i[12] ;
+ wire \wbd_riscv_dmem_dat_i[13] ;
+ wire \wbd_riscv_dmem_dat_i[14] ;
+ wire \wbd_riscv_dmem_dat_i[15] ;
+ wire \wbd_riscv_dmem_dat_i[16] ;
+ wire \wbd_riscv_dmem_dat_i[17] ;
+ wire \wbd_riscv_dmem_dat_i[18] ;
+ wire \wbd_riscv_dmem_dat_i[19] ;
+ wire \wbd_riscv_dmem_dat_i[1] ;
+ wire \wbd_riscv_dmem_dat_i[20] ;
+ wire \wbd_riscv_dmem_dat_i[21] ;
+ wire \wbd_riscv_dmem_dat_i[22] ;
+ wire \wbd_riscv_dmem_dat_i[23] ;
+ wire \wbd_riscv_dmem_dat_i[24] ;
+ wire \wbd_riscv_dmem_dat_i[25] ;
+ wire \wbd_riscv_dmem_dat_i[26] ;
+ wire \wbd_riscv_dmem_dat_i[27] ;
+ wire \wbd_riscv_dmem_dat_i[28] ;
+ wire \wbd_riscv_dmem_dat_i[29] ;
+ wire \wbd_riscv_dmem_dat_i[2] ;
+ wire \wbd_riscv_dmem_dat_i[30] ;
+ wire \wbd_riscv_dmem_dat_i[31] ;
+ wire \wbd_riscv_dmem_dat_i[3] ;
+ wire \wbd_riscv_dmem_dat_i[4] ;
+ wire \wbd_riscv_dmem_dat_i[5] ;
+ wire \wbd_riscv_dmem_dat_i[6] ;
+ wire \wbd_riscv_dmem_dat_i[7] ;
+ wire \wbd_riscv_dmem_dat_i[8] ;
+ wire \wbd_riscv_dmem_dat_i[9] ;
+ wire \wbd_riscv_dmem_dat_o[0] ;
+ wire \wbd_riscv_dmem_dat_o[10] ;
+ wire \wbd_riscv_dmem_dat_o[11] ;
+ wire \wbd_riscv_dmem_dat_o[12] ;
+ wire \wbd_riscv_dmem_dat_o[13] ;
+ wire \wbd_riscv_dmem_dat_o[14] ;
+ wire \wbd_riscv_dmem_dat_o[15] ;
+ wire \wbd_riscv_dmem_dat_o[16] ;
+ wire \wbd_riscv_dmem_dat_o[17] ;
+ wire \wbd_riscv_dmem_dat_o[18] ;
+ wire \wbd_riscv_dmem_dat_o[19] ;
+ wire \wbd_riscv_dmem_dat_o[1] ;
+ wire \wbd_riscv_dmem_dat_o[20] ;
+ wire \wbd_riscv_dmem_dat_o[21] ;
+ wire \wbd_riscv_dmem_dat_o[22] ;
+ wire \wbd_riscv_dmem_dat_o[23] ;
+ wire \wbd_riscv_dmem_dat_o[24] ;
+ wire \wbd_riscv_dmem_dat_o[25] ;
+ wire \wbd_riscv_dmem_dat_o[26] ;
+ wire \wbd_riscv_dmem_dat_o[27] ;
+ wire \wbd_riscv_dmem_dat_o[28] ;
+ wire \wbd_riscv_dmem_dat_o[29] ;
+ wire \wbd_riscv_dmem_dat_o[2] ;
+ wire \wbd_riscv_dmem_dat_o[30] ;
+ wire \wbd_riscv_dmem_dat_o[31] ;
+ wire \wbd_riscv_dmem_dat_o[3] ;
+ wire \wbd_riscv_dmem_dat_o[4] ;
+ wire \wbd_riscv_dmem_dat_o[5] ;
+ wire \wbd_riscv_dmem_dat_o[6] ;
+ wire \wbd_riscv_dmem_dat_o[7] ;
+ wire \wbd_riscv_dmem_dat_o[8] ;
+ wire \wbd_riscv_dmem_dat_o[9] ;
+ wire wbd_riscv_dmem_err_o;
+ wire \wbd_riscv_dmem_sel_i[0] ;
+ wire \wbd_riscv_dmem_sel_i[1] ;
+ wire \wbd_riscv_dmem_sel_i[2] ;
+ wire \wbd_riscv_dmem_sel_i[3] ;
+ wire wbd_riscv_dmem_stb_i;
+ wire wbd_riscv_dmem_we_i;
+ wire wbd_riscv_imem_ack_o;
+ wire \wbd_riscv_imem_adr_i[0] ;
+ wire \wbd_riscv_imem_adr_i[10] ;
+ wire \wbd_riscv_imem_adr_i[11] ;
+ wire \wbd_riscv_imem_adr_i[12] ;
+ wire \wbd_riscv_imem_adr_i[13] ;
+ wire \wbd_riscv_imem_adr_i[14] ;
+ wire \wbd_riscv_imem_adr_i[15] ;
+ wire \wbd_riscv_imem_adr_i[16] ;
+ wire \wbd_riscv_imem_adr_i[17] ;
+ wire \wbd_riscv_imem_adr_i[18] ;
+ wire \wbd_riscv_imem_adr_i[19] ;
+ wire \wbd_riscv_imem_adr_i[1] ;
+ wire \wbd_riscv_imem_adr_i[20] ;
+ wire \wbd_riscv_imem_adr_i[21] ;
+ wire \wbd_riscv_imem_adr_i[22] ;
+ wire \wbd_riscv_imem_adr_i[23] ;
+ wire \wbd_riscv_imem_adr_i[24] ;
+ wire \wbd_riscv_imem_adr_i[25] ;
+ wire \wbd_riscv_imem_adr_i[26] ;
+ wire \wbd_riscv_imem_adr_i[27] ;
+ wire \wbd_riscv_imem_adr_i[28] ;
+ wire \wbd_riscv_imem_adr_i[29] ;
+ wire \wbd_riscv_imem_adr_i[2] ;
+ wire \wbd_riscv_imem_adr_i[30] ;
+ wire \wbd_riscv_imem_adr_i[31] ;
+ wire \wbd_riscv_imem_adr_i[3] ;
+ wire \wbd_riscv_imem_adr_i[4] ;
+ wire \wbd_riscv_imem_adr_i[5] ;
+ wire \wbd_riscv_imem_adr_i[6] ;
+ wire \wbd_riscv_imem_adr_i[7] ;
+ wire \wbd_riscv_imem_adr_i[8] ;
+ wire \wbd_riscv_imem_adr_i[9] ;
+ wire \wbd_riscv_imem_dat_i[0] ;
+ wire \wbd_riscv_imem_dat_i[10] ;
+ wire \wbd_riscv_imem_dat_i[11] ;
+ wire \wbd_riscv_imem_dat_i[12] ;
+ wire \wbd_riscv_imem_dat_i[13] ;
+ wire \wbd_riscv_imem_dat_i[14] ;
+ wire \wbd_riscv_imem_dat_i[15] ;
+ wire \wbd_riscv_imem_dat_i[16] ;
+ wire \wbd_riscv_imem_dat_i[17] ;
+ wire \wbd_riscv_imem_dat_i[18] ;
+ wire \wbd_riscv_imem_dat_i[19] ;
+ wire \wbd_riscv_imem_dat_i[1] ;
+ wire \wbd_riscv_imem_dat_i[20] ;
+ wire \wbd_riscv_imem_dat_i[21] ;
+ wire \wbd_riscv_imem_dat_i[22] ;
+ wire \wbd_riscv_imem_dat_i[23] ;
+ wire \wbd_riscv_imem_dat_i[24] ;
+ wire \wbd_riscv_imem_dat_i[25] ;
+ wire \wbd_riscv_imem_dat_i[26] ;
+ wire \wbd_riscv_imem_dat_i[27] ;
+ wire \wbd_riscv_imem_dat_i[28] ;
+ wire \wbd_riscv_imem_dat_i[29] ;
+ wire \wbd_riscv_imem_dat_i[2] ;
+ wire \wbd_riscv_imem_dat_i[30] ;
+ wire \wbd_riscv_imem_dat_i[31] ;
+ wire \wbd_riscv_imem_dat_i[3] ;
+ wire \wbd_riscv_imem_dat_i[4] ;
+ wire \wbd_riscv_imem_dat_i[5] ;
+ wire \wbd_riscv_imem_dat_i[6] ;
+ wire \wbd_riscv_imem_dat_i[7] ;
+ wire \wbd_riscv_imem_dat_i[8] ;
+ wire \wbd_riscv_imem_dat_i[9] ;
+ wire \wbd_riscv_imem_dat_o[0] ;
+ wire \wbd_riscv_imem_dat_o[10] ;
+ wire \wbd_riscv_imem_dat_o[11] ;
+ wire \wbd_riscv_imem_dat_o[12] ;
+ wire \wbd_riscv_imem_dat_o[13] ;
+ wire \wbd_riscv_imem_dat_o[14] ;
+ wire \wbd_riscv_imem_dat_o[15] ;
+ wire \wbd_riscv_imem_dat_o[16] ;
+ wire \wbd_riscv_imem_dat_o[17] ;
+ wire \wbd_riscv_imem_dat_o[18] ;
+ wire \wbd_riscv_imem_dat_o[19] ;
+ wire \wbd_riscv_imem_dat_o[1] ;
+ wire \wbd_riscv_imem_dat_o[20] ;
+ wire \wbd_riscv_imem_dat_o[21] ;
+ wire \wbd_riscv_imem_dat_o[22] ;
+ wire \wbd_riscv_imem_dat_o[23] ;
+ wire \wbd_riscv_imem_dat_o[24] ;
+ wire \wbd_riscv_imem_dat_o[25] ;
+ wire \wbd_riscv_imem_dat_o[26] ;
+ wire \wbd_riscv_imem_dat_o[27] ;
+ wire \wbd_riscv_imem_dat_o[28] ;
+ wire \wbd_riscv_imem_dat_o[29] ;
+ wire \wbd_riscv_imem_dat_o[2] ;
+ wire \wbd_riscv_imem_dat_o[30] ;
+ wire \wbd_riscv_imem_dat_o[31] ;
+ wire \wbd_riscv_imem_dat_o[3] ;
+ wire \wbd_riscv_imem_dat_o[4] ;
+ wire \wbd_riscv_imem_dat_o[5] ;
+ wire \wbd_riscv_imem_dat_o[6] ;
+ wire \wbd_riscv_imem_dat_o[7] ;
+ wire \wbd_riscv_imem_dat_o[8] ;
+ wire \wbd_riscv_imem_dat_o[9] ;
+ wire wbd_riscv_imem_err_o;
+ wire \wbd_riscv_imem_sel_i[0] ;
+ wire \wbd_riscv_imem_sel_i[1] ;
+ wire \wbd_riscv_imem_sel_i[2] ;
+ wire \wbd_riscv_imem_sel_i[3] ;
+ wire wbd_riscv_imem_stb_i;
+ wire wbd_riscv_imem_we_i;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+    .m0_wbd_ack_o(wbd_int_ack_o),
+    .m0_wbd_cyc_i(wbd_int_cyc_i),
+    .m0_wbd_err_o(wbd_int_err_o),
+    .m0_wbd_stb_i(wbd_int_stb_i),
+    .m0_wbd_we_i(wbd_int_we_i),
+    .m1_wbd_ack_o(wbd_riscv_imem_ack_o),
+    .m1_wbd_cyc_i(wbd_riscv_imem_stb_i),
+    .m1_wbd_err_o(wbd_riscv_imem_err_o),
+    .m1_wbd_stb_i(wbd_riscv_imem_stb_i),
+    .m1_wbd_we_i(wbd_riscv_imem_we_i),
+    .m2_wbd_ack_o(wbd_riscv_dmem_ack_o),
+    .m2_wbd_cyc_i(wbd_riscv_dmem_stb_i),
+    .m2_wbd_err_o(wbd_riscv_dmem_err_o),
+    .m2_wbd_stb_i(wbd_riscv_dmem_stb_i),
+    .m2_wbd_we_i(wbd_riscv_dmem_we_i),
+    .rst_n(wbd_int_rst_n),
+    .s0_wbd_ack_i(wbd_spim_ack_i),
+    .s0_wbd_cyc_o(wbd_spim_cyc_o),
+    .s0_wbd_stb_o(wbd_spim_stb_o),
+    .s0_wbd_we_o(wbd_spim_we_o),
+    .s1_wbd_ack_i(wbd_uart_ack_i),
+    .s1_wbd_cyc_o(wbd_uart_cyc_o),
+    .s1_wbd_stb_o(wbd_uart_stb_o),
+    .s1_wbd_we_o(wbd_uart_we_o),
+    .s2_wbd_ack_i(wbd_glbl_ack_i),
+    .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+    .s2_wbd_stb_o(wbd_glbl_stb_o),
+    .s2_wbd_we_o(wbd_glbl_we_o),
+    .s3_wbd_ack_i(wbd_mbist_ack_i),
+    .s3_wbd_cyc_o(wbd_mbist_cyc_o),
+    .s3_wbd_stb_o(wbd_mbist_stb_o),
+    .s3_wbd_we_o(wbd_mbist_we_o),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wi(wbd_clk_wi_skew),
+    .boot_remap({\boot_remap[3] ,
+    \boot_remap[2] ,
+    \boot_remap[1] ,
+    \boot_remap[0] }),
+    .cfg_cska_wi({\cfg_clk_ctrl1[3] ,
+    \cfg_clk_ctrl1[2] ,
+    \cfg_clk_ctrl1[1] ,
+    \cfg_clk_ctrl1[0] }),
+    .ch_clk_in({wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int}),
+    .ch_clk_out({wbd_clk_mbist4_rp,
+    wbd_clk_mbist3_rp,
+    wbd_clk_mbist2_rp,
+    wbd_clk_mbist1_rp,
+    wbd_clk_pinmux_rp,
+    wbd_clk_uart_rp,
+    wbd_clk_qspi_rp,
+    wbd_clk_risc_rp}),
+    .ch_data_in({\bist_error_cnt3[3] ,
+    \bist_error_cnt3[2] ,
+    \bist_error_cnt3[1] ,
+    \bist_error_cnt3[0] ,
+    \bist_correct[3] ,
+    \bist_error[3] ,
+    \bist_error_cnt2[3] ,
+    \bist_error_cnt2[2] ,
+    \bist_error_cnt2[1] ,
+    \bist_error_cnt2[0] ,
+    \bist_correct[2] ,
+    \bist_error[2] ,
+    \bist_error_cnt1[3] ,
+    \bist_error_cnt1[2] ,
+    \bist_error_cnt1[1] ,
+    \bist_error_cnt1[0] ,
+    \bist_correct[1] ,
+    \bist_error[1] ,
+    \bist_error_cnt0[3] ,
+    \bist_error_cnt0[2] ,
+    \bist_error_cnt0[1] ,
+    \bist_error_cnt0[0] ,
+    \bist_correct[0] ,
+    \bist_error[0] ,
+    bist_done,
+    bist_sdo,
+    bist_shift,
+    bist_sdi,
+    bist_load,
+    bist_run,
+    bist_en,
+    soft_irq,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] ,
+    \fuse_mhartid[31] ,
+    \fuse_mhartid[30] ,
+    \fuse_mhartid[29] ,
+    \fuse_mhartid[28] ,
+    \fuse_mhartid[27] ,
+    \fuse_mhartid[26] ,
+    \fuse_mhartid[25] ,
+    \fuse_mhartid[24] ,
+    \fuse_mhartid[23] ,
+    \fuse_mhartid[22] ,
+    \fuse_mhartid[21] ,
+    \fuse_mhartid[20] ,
+    \fuse_mhartid[19] ,
+    \fuse_mhartid[18] ,
+    \fuse_mhartid[17] ,
+    \fuse_mhartid[16] ,
+    \fuse_mhartid[15] ,
+    \fuse_mhartid[14] ,
+    \fuse_mhartid[13] ,
+    \fuse_mhartid[12] ,
+    \fuse_mhartid[11] ,
+    \fuse_mhartid[10] ,
+    \fuse_mhartid[9] ,
+    \fuse_mhartid[8] ,
+    \fuse_mhartid[7] ,
+    \fuse_mhartid[6] ,
+    \fuse_mhartid[5] ,
+    \fuse_mhartid[4] ,
+    \fuse_mhartid[3] ,
+    \fuse_mhartid[2] ,
+    \fuse_mhartid[1] ,
+    \fuse_mhartid[0] ,
+    \cfg_clk_ctrl2[15] ,
+    \cfg_clk_ctrl2[14] ,
+    \cfg_clk_ctrl2[13] ,
+    \cfg_clk_ctrl2[12] ,
+    \cfg_clk_ctrl2[11] ,
+    \cfg_clk_ctrl2[10] ,
+    \cfg_clk_ctrl2[9] ,
+    \cfg_clk_ctrl2[8] ,
+    \cfg_clk_ctrl2[7] ,
+    \cfg_clk_ctrl2[6] ,
+    \cfg_clk_ctrl2[5] ,
+    \cfg_clk_ctrl2[4] ,
+    \cfg_clk_ctrl2[3] ,
+    \cfg_clk_ctrl2[2] ,
+    \cfg_clk_ctrl2[1] ,
+    \cfg_clk_ctrl2[0] ,
+    \cfg_clk_ctrl1[27] ,
+    \cfg_clk_ctrl1[26] ,
+    \cfg_clk_ctrl1[25] ,
+    \cfg_clk_ctrl1[24] ,
+    \cfg_clk_ctrl1[23] ,
+    \cfg_clk_ctrl1[22] ,
+    \cfg_clk_ctrl1[21] ,
+    \cfg_clk_ctrl1[20] ,
+    \cfg_clk_ctrl1[19] ,
+    \cfg_clk_ctrl1[18] ,
+    \cfg_clk_ctrl1[17] ,
+    \cfg_clk_ctrl1[16] ,
+    \cfg_clk_ctrl1[15] ,
+    \cfg_clk_ctrl1[14] ,
+    \cfg_clk_ctrl1[13] ,
+    \cfg_clk_ctrl1[12] ,
+    \cfg_clk_ctrl1[11] ,
+    \cfg_clk_ctrl1[10] ,
+    \cfg_clk_ctrl1[9] ,
+    \cfg_clk_ctrl1[8] }),
+    .ch_data_out({\bist_error_cnt3_rp[3] ,
+    \bist_error_cnt3_rp[2] ,
+    \bist_error_cnt3_rp[1] ,
+    \bist_error_cnt3_rp[0] ,
+    \bist_correct_rp[3] ,
+    \bist_error_rp[3] ,
+    \bist_error_cnt2_rp[3] ,
+    \bist_error_cnt2_rp[2] ,
+    \bist_error_cnt2_rp[1] ,
+    \bist_error_cnt2_rp[0] ,
+    \bist_correct_rp[2] ,
+    \bist_error_rp[2] ,
+    \bist_error_cnt1_rp[3] ,
+    \bist_error_cnt1_rp[2] ,
+    \bist_error_cnt1_rp[1] ,
+    \bist_error_cnt1_rp[0] ,
+    \bist_correct_rp[1] ,
+    \bist_error_rp[1] ,
+    \bist_error_cnt0_rp[3] ,
+    \bist_error_cnt0_rp[2] ,
+    \bist_error_cnt0_rp[1] ,
+    \bist_error_cnt0_rp[0] ,
+    \bist_correct_rp[0] ,
+    \bist_error_rp[0] ,
+    bist_done_rp,
+    bist_sdo_rp,
+    bist_shift_rp,
+    bist_sdi_rp,
+    bist_load_rp,
+    bist_run_rp,
+    bist_en_rp,
+    soft_irq_rp,
+    \irq_lines_rp[15] ,
+    \irq_lines_rp[14] ,
+    \irq_lines_rp[13] ,
+    \irq_lines_rp[12] ,
+    \irq_lines_rp[11] ,
+    \irq_lines_rp[10] ,
+    \irq_lines_rp[9] ,
+    \irq_lines_rp[8] ,
+    \irq_lines_rp[7] ,
+    \irq_lines_rp[6] ,
+    \irq_lines_rp[5] ,
+    \irq_lines_rp[4] ,
+    \irq_lines_rp[3] ,
+    \irq_lines_rp[2] ,
+    \irq_lines_rp[1] ,
+    \irq_lines_rp[0] ,
+    \fuse_mhartid_rp[31] ,
+    \fuse_mhartid_rp[30] ,
+    \fuse_mhartid_rp[29] ,
+    \fuse_mhartid_rp[28] ,
+    \fuse_mhartid_rp[27] ,
+    \fuse_mhartid_rp[26] ,
+    \fuse_mhartid_rp[25] ,
+    \fuse_mhartid_rp[24] ,
+    \fuse_mhartid_rp[23] ,
+    \fuse_mhartid_rp[22] ,
+    \fuse_mhartid_rp[21] ,
+    \fuse_mhartid_rp[20] ,
+    \fuse_mhartid_rp[19] ,
+    \fuse_mhartid_rp[18] ,
+    \fuse_mhartid_rp[17] ,
+    \fuse_mhartid_rp[16] ,
+    \fuse_mhartid_rp[15] ,
+    \fuse_mhartid_rp[14] ,
+    \fuse_mhartid_rp[13] ,
+    \fuse_mhartid_rp[12] ,
+    \fuse_mhartid_rp[11] ,
+    \fuse_mhartid_rp[10] ,
+    \fuse_mhartid_rp[9] ,
+    \fuse_mhartid_rp[8] ,
+    \fuse_mhartid_rp[7] ,
+    \fuse_mhartid_rp[6] ,
+    \fuse_mhartid_rp[5] ,
+    \fuse_mhartid_rp[4] ,
+    \fuse_mhartid_rp[3] ,
+    \fuse_mhartid_rp[2] ,
+    \fuse_mhartid_rp[1] ,
+    \fuse_mhartid_rp[0] ,
+    \cfg_cska_mbist4_rp[3] ,
+    \cfg_cska_mbist4_rp[2] ,
+    \cfg_cska_mbist4_rp[1] ,
+    \cfg_cska_mbist4_rp[0] ,
+    \cfg_cska_mbist3_rp[3] ,
+    \cfg_cska_mbist3_rp[2] ,
+    \cfg_cska_mbist3_rp[1] ,
+    \cfg_cska_mbist3_rp[0] ,
+    \cfg_cska_mbist2_rp[3] ,
+    \cfg_cska_mbist2_rp[2] ,
+    \cfg_cska_mbist2_rp[1] ,
+    \cfg_cska_mbist2_rp[0] ,
+    \cfg_cska_mbist1_rp[3] ,
+    \cfg_cska_mbist1_rp[2] ,
+    \cfg_cska_mbist1_rp[1] ,
+    \cfg_cska_mbist1_rp[0] ,
+    \cfg_cska_qspi_co_rp[3] ,
+    \cfg_cska_qspi_co_rp[2] ,
+    \cfg_cska_qspi_co_rp[1] ,
+    \cfg_cska_qspi_co_rp[0] ,
+    \cfg_cska_pinmux_rp[3] ,
+    \cfg_cska_pinmux_rp[2] ,
+    \cfg_cska_pinmux_rp[1] ,
+    \cfg_cska_pinmux_rp[0] ,
+    \cfg_cska_uart_rp[3] ,
+    \cfg_cska_uart_rp[2] ,
+    \cfg_cska_uart_rp[1] ,
+    \cfg_cska_uart_rp[0] ,
+    \cfg_cska_qspi_rp[3] ,
+    \cfg_cska_qspi_rp[2] ,
+    \cfg_cska_qspi_rp[1] ,
+    \cfg_cska_qspi_rp[0] ,
+    \cfg_cska_riscv_rp[3] ,
+    \cfg_cska_riscv_rp[2] ,
+    \cfg_cska_riscv_rp[1] ,
+    \cfg_cska_riscv_rp[0] }),
+    .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }),
+    .m1_wbd_adr_i({\wbd_riscv_imem_adr_i[31] ,
+    \wbd_riscv_imem_adr_i[30] ,
+    \wbd_riscv_imem_adr_i[29] ,
+    \wbd_riscv_imem_adr_i[28] ,
+    \wbd_riscv_imem_adr_i[27] ,
+    \wbd_riscv_imem_adr_i[26] ,
+    \wbd_riscv_imem_adr_i[25] ,
+    \wbd_riscv_imem_adr_i[24] ,
+    \wbd_riscv_imem_adr_i[23] ,
+    \wbd_riscv_imem_adr_i[22] ,
+    \wbd_riscv_imem_adr_i[21] ,
+    \wbd_riscv_imem_adr_i[20] ,
+    \wbd_riscv_imem_adr_i[19] ,
+    \wbd_riscv_imem_adr_i[18] ,
+    \wbd_riscv_imem_adr_i[17] ,
+    \wbd_riscv_imem_adr_i[16] ,
+    \wbd_riscv_imem_adr_i[15] ,
+    \wbd_riscv_imem_adr_i[14] ,
+    \wbd_riscv_imem_adr_i[13] ,
+    \wbd_riscv_imem_adr_i[12] ,
+    \wbd_riscv_imem_adr_i[11] ,
+    \wbd_riscv_imem_adr_i[10] ,
+    \wbd_riscv_imem_adr_i[9] ,
+    \wbd_riscv_imem_adr_i[8] ,
+    \wbd_riscv_imem_adr_i[7] ,
+    \wbd_riscv_imem_adr_i[6] ,
+    \wbd_riscv_imem_adr_i[5] ,
+    \wbd_riscv_imem_adr_i[4] ,
+    \wbd_riscv_imem_adr_i[3] ,
+    \wbd_riscv_imem_adr_i[2] ,
+    \wbd_riscv_imem_adr_i[1] ,
+    \wbd_riscv_imem_adr_i[0] }),
+    .m1_wbd_dat_i({\wbd_riscv_imem_dat_i[31] ,
+    \wbd_riscv_imem_dat_i[30] ,
+    \wbd_riscv_imem_dat_i[29] ,
+    \wbd_riscv_imem_dat_i[28] ,
+    \wbd_riscv_imem_dat_i[27] ,
+    \wbd_riscv_imem_dat_i[26] ,
+    \wbd_riscv_imem_dat_i[25] ,
+    \wbd_riscv_imem_dat_i[24] ,
+    \wbd_riscv_imem_dat_i[23] ,
+    \wbd_riscv_imem_dat_i[22] ,
+    \wbd_riscv_imem_dat_i[21] ,
+    \wbd_riscv_imem_dat_i[20] ,
+    \wbd_riscv_imem_dat_i[19] ,
+    \wbd_riscv_imem_dat_i[18] ,
+    \wbd_riscv_imem_dat_i[17] ,
+    \wbd_riscv_imem_dat_i[16] ,
+    \wbd_riscv_imem_dat_i[15] ,
+    \wbd_riscv_imem_dat_i[14] ,
+    \wbd_riscv_imem_dat_i[13] ,
+    \wbd_riscv_imem_dat_i[12] ,
+    \wbd_riscv_imem_dat_i[11] ,
+    \wbd_riscv_imem_dat_i[10] ,
+    \wbd_riscv_imem_dat_i[9] ,
+    \wbd_riscv_imem_dat_i[8] ,
+    \wbd_riscv_imem_dat_i[7] ,
+    \wbd_riscv_imem_dat_i[6] ,
+    \wbd_riscv_imem_dat_i[5] ,
+    \wbd_riscv_imem_dat_i[4] ,
+    \wbd_riscv_imem_dat_i[3] ,
+    \wbd_riscv_imem_dat_i[2] ,
+    \wbd_riscv_imem_dat_i[1] ,
+    \wbd_riscv_imem_dat_i[0] }),
+    .m1_wbd_dat_o({\wbd_riscv_imem_dat_o[31] ,
+    \wbd_riscv_imem_dat_o[30] ,
+    \wbd_riscv_imem_dat_o[29] ,
+    \wbd_riscv_imem_dat_o[28] ,
+    \wbd_riscv_imem_dat_o[27] ,
+    \wbd_riscv_imem_dat_o[26] ,
+    \wbd_riscv_imem_dat_o[25] ,
+    \wbd_riscv_imem_dat_o[24] ,
+    \wbd_riscv_imem_dat_o[23] ,
+    \wbd_riscv_imem_dat_o[22] ,
+    \wbd_riscv_imem_dat_o[21] ,
+    \wbd_riscv_imem_dat_o[20] ,
+    \wbd_riscv_imem_dat_o[19] ,
+    \wbd_riscv_imem_dat_o[18] ,
+    \wbd_riscv_imem_dat_o[17] ,
+    \wbd_riscv_imem_dat_o[16] ,
+    \wbd_riscv_imem_dat_o[15] ,
+    \wbd_riscv_imem_dat_o[14] ,
+    \wbd_riscv_imem_dat_o[13] ,
+    \wbd_riscv_imem_dat_o[12] ,
+    \wbd_riscv_imem_dat_o[11] ,
+    \wbd_riscv_imem_dat_o[10] ,
+    \wbd_riscv_imem_dat_o[9] ,
+    \wbd_riscv_imem_dat_o[8] ,
+    \wbd_riscv_imem_dat_o[7] ,
+    \wbd_riscv_imem_dat_o[6] ,
+    \wbd_riscv_imem_dat_o[5] ,
+    \wbd_riscv_imem_dat_o[4] ,
+    \wbd_riscv_imem_dat_o[3] ,
+    \wbd_riscv_imem_dat_o[2] ,
+    \wbd_riscv_imem_dat_o[1] ,
+    \wbd_riscv_imem_dat_o[0] }),
+    .m1_wbd_sel_i({\wbd_riscv_imem_sel_i[3] ,
+    \wbd_riscv_imem_sel_i[2] ,
+    \wbd_riscv_imem_sel_i[1] ,
+    \wbd_riscv_imem_sel_i[0] }),
+    .m2_wbd_adr_i({\wbd_riscv_dmem_adr_i[31] ,
+    \wbd_riscv_dmem_adr_i[30] ,
+    \wbd_riscv_dmem_adr_i[29] ,
+    \wbd_riscv_dmem_adr_i[28] ,
+    \wbd_riscv_dmem_adr_i[27] ,
+    \wbd_riscv_dmem_adr_i[26] ,
+    \wbd_riscv_dmem_adr_i[25] ,
+    \wbd_riscv_dmem_adr_i[24] ,
+    \wbd_riscv_dmem_adr_i[23] ,
+    \wbd_riscv_dmem_adr_i[22] ,
+    \wbd_riscv_dmem_adr_i[21] ,
+    \wbd_riscv_dmem_adr_i[20] ,
+    \wbd_riscv_dmem_adr_i[19] ,
+    \wbd_riscv_dmem_adr_i[18] ,
+    \wbd_riscv_dmem_adr_i[17] ,
+    \wbd_riscv_dmem_adr_i[16] ,
+    \wbd_riscv_dmem_adr_i[15] ,
+    \wbd_riscv_dmem_adr_i[14] ,
+    \wbd_riscv_dmem_adr_i[13] ,
+    \wbd_riscv_dmem_adr_i[12] ,
+    \wbd_riscv_dmem_adr_i[11] ,
+    \wbd_riscv_dmem_adr_i[10] ,
+    \wbd_riscv_dmem_adr_i[9] ,
+    \wbd_riscv_dmem_adr_i[8] ,
+    \wbd_riscv_dmem_adr_i[7] ,
+    \wbd_riscv_dmem_adr_i[6] ,
+    \wbd_riscv_dmem_adr_i[5] ,
+    \wbd_riscv_dmem_adr_i[4] ,
+    \wbd_riscv_dmem_adr_i[3] ,
+    \wbd_riscv_dmem_adr_i[2] ,
+    \wbd_riscv_dmem_adr_i[1] ,
+    \wbd_riscv_dmem_adr_i[0] }),
+    .m2_wbd_dat_i({\wbd_riscv_dmem_dat_i[31] ,
+    \wbd_riscv_dmem_dat_i[30] ,
+    \wbd_riscv_dmem_dat_i[29] ,
+    \wbd_riscv_dmem_dat_i[28] ,
+    \wbd_riscv_dmem_dat_i[27] ,
+    \wbd_riscv_dmem_dat_i[26] ,
+    \wbd_riscv_dmem_dat_i[25] ,
+    \wbd_riscv_dmem_dat_i[24] ,
+    \wbd_riscv_dmem_dat_i[23] ,
+    \wbd_riscv_dmem_dat_i[22] ,
+    \wbd_riscv_dmem_dat_i[21] ,
+    \wbd_riscv_dmem_dat_i[20] ,
+    \wbd_riscv_dmem_dat_i[19] ,
+    \wbd_riscv_dmem_dat_i[18] ,
+    \wbd_riscv_dmem_dat_i[17] ,
+    \wbd_riscv_dmem_dat_i[16] ,
+    \wbd_riscv_dmem_dat_i[15] ,
+    \wbd_riscv_dmem_dat_i[14] ,
+    \wbd_riscv_dmem_dat_i[13] ,
+    \wbd_riscv_dmem_dat_i[12] ,
+    \wbd_riscv_dmem_dat_i[11] ,
+    \wbd_riscv_dmem_dat_i[10] ,
+    \wbd_riscv_dmem_dat_i[9] ,
+    \wbd_riscv_dmem_dat_i[8] ,
+    \wbd_riscv_dmem_dat_i[7] ,
+    \wbd_riscv_dmem_dat_i[6] ,
+    \wbd_riscv_dmem_dat_i[5] ,
+    \wbd_riscv_dmem_dat_i[4] ,
+    \wbd_riscv_dmem_dat_i[3] ,
+    \wbd_riscv_dmem_dat_i[2] ,
+    \wbd_riscv_dmem_dat_i[1] ,
+    \wbd_riscv_dmem_dat_i[0] }),
+    .m2_wbd_dat_o({\wbd_riscv_dmem_dat_o[31] ,
+    \wbd_riscv_dmem_dat_o[30] ,
+    \wbd_riscv_dmem_dat_o[29] ,
+    \wbd_riscv_dmem_dat_o[28] ,
+    \wbd_riscv_dmem_dat_o[27] ,
+    \wbd_riscv_dmem_dat_o[26] ,
+    \wbd_riscv_dmem_dat_o[25] ,
+    \wbd_riscv_dmem_dat_o[24] ,
+    \wbd_riscv_dmem_dat_o[23] ,
+    \wbd_riscv_dmem_dat_o[22] ,
+    \wbd_riscv_dmem_dat_o[21] ,
+    \wbd_riscv_dmem_dat_o[20] ,
+    \wbd_riscv_dmem_dat_o[19] ,
+    \wbd_riscv_dmem_dat_o[18] ,
+    \wbd_riscv_dmem_dat_o[17] ,
+    \wbd_riscv_dmem_dat_o[16] ,
+    \wbd_riscv_dmem_dat_o[15] ,
+    \wbd_riscv_dmem_dat_o[14] ,
+    \wbd_riscv_dmem_dat_o[13] ,
+    \wbd_riscv_dmem_dat_o[12] ,
+    \wbd_riscv_dmem_dat_o[11] ,
+    \wbd_riscv_dmem_dat_o[10] ,
+    \wbd_riscv_dmem_dat_o[9] ,
+    \wbd_riscv_dmem_dat_o[8] ,
+    \wbd_riscv_dmem_dat_o[7] ,
+    \wbd_riscv_dmem_dat_o[6] ,
+    \wbd_riscv_dmem_dat_o[5] ,
+    \wbd_riscv_dmem_dat_o[4] ,
+    \wbd_riscv_dmem_dat_o[3] ,
+    \wbd_riscv_dmem_dat_o[2] ,
+    \wbd_riscv_dmem_dat_o[1] ,
+    \wbd_riscv_dmem_dat_o[0] }),
+    .m2_wbd_sel_i({\wbd_riscv_dmem_sel_i[3] ,
+    \wbd_riscv_dmem_sel_i[2] ,
+    \wbd_riscv_dmem_sel_i[1] ,
+    \wbd_riscv_dmem_sel_i[0] }),
+    .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }),
+    .s1_wbd_adr_o({\wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .s2_wbd_adr_o({\wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .s3_wbd_adr_o({\wbd_mbist_adr_o[12] ,
+    \wbd_mbist_adr_o[11] ,
+    \wbd_mbist_adr_o[10] ,
+    \wbd_mbist_adr_o[9] ,
+    \wbd_mbist_adr_o[8] ,
+    \wbd_mbist_adr_o[7] ,
+    \wbd_mbist_adr_o[6] ,
+    \wbd_mbist_adr_o[5] ,
+    \wbd_mbist_adr_o[4] ,
+    \wbd_mbist_adr_o[3] ,
+    \wbd_mbist_adr_o[2] ,
+    \wbd_mbist_adr_o[1] ,
+    \wbd_mbist_adr_o[0] }),
+    .s3_wbd_dat_i({\wbd_mbist_dat_i[31] ,
+    \wbd_mbist_dat_i[30] ,
+    \wbd_mbist_dat_i[29] ,
+    \wbd_mbist_dat_i[28] ,
+    \wbd_mbist_dat_i[27] ,
+    \wbd_mbist_dat_i[26] ,
+    \wbd_mbist_dat_i[25] ,
+    \wbd_mbist_dat_i[24] ,
+    \wbd_mbist_dat_i[23] ,
+    \wbd_mbist_dat_i[22] ,
+    \wbd_mbist_dat_i[21] ,
+    \wbd_mbist_dat_i[20] ,
+    \wbd_mbist_dat_i[19] ,
+    \wbd_mbist_dat_i[18] ,
+    \wbd_mbist_dat_i[17] ,
+    \wbd_mbist_dat_i[16] ,
+    \wbd_mbist_dat_i[15] ,
+    \wbd_mbist_dat_i[14] ,
+    \wbd_mbist_dat_i[13] ,
+    \wbd_mbist_dat_i[12] ,
+    \wbd_mbist_dat_i[11] ,
+    \wbd_mbist_dat_i[10] ,
+    \wbd_mbist_dat_i[9] ,
+    \wbd_mbist_dat_i[8] ,
+    \wbd_mbist_dat_i[7] ,
+    \wbd_mbist_dat_i[6] ,
+    \wbd_mbist_dat_i[5] ,
+    \wbd_mbist_dat_i[4] ,
+    \wbd_mbist_dat_i[3] ,
+    \wbd_mbist_dat_i[2] ,
+    \wbd_mbist_dat_i[1] ,
+    \wbd_mbist_dat_i[0] }),
+    .s3_wbd_dat_o({\wbd_mbist_dat_o[31] ,
+    \wbd_mbist_dat_o[30] ,
+    \wbd_mbist_dat_o[29] ,
+    \wbd_mbist_dat_o[28] ,
+    \wbd_mbist_dat_o[27] ,
+    \wbd_mbist_dat_o[26] ,
+    \wbd_mbist_dat_o[25] ,
+    \wbd_mbist_dat_o[24] ,
+    \wbd_mbist_dat_o[23] ,
+    \wbd_mbist_dat_o[22] ,
+    \wbd_mbist_dat_o[21] ,
+    \wbd_mbist_dat_o[20] ,
+    \wbd_mbist_dat_o[19] ,
+    \wbd_mbist_dat_o[18] ,
+    \wbd_mbist_dat_o[17] ,
+    \wbd_mbist_dat_o[16] ,
+    \wbd_mbist_dat_o[15] ,
+    \wbd_mbist_dat_o[14] ,
+    \wbd_mbist_dat_o[13] ,
+    \wbd_mbist_dat_o[12] ,
+    \wbd_mbist_dat_o[11] ,
+    \wbd_mbist_dat_o[10] ,
+    \wbd_mbist_dat_o[9] ,
+    \wbd_mbist_dat_o[8] ,
+    \wbd_mbist_dat_o[7] ,
+    \wbd_mbist_dat_o[6] ,
+    \wbd_mbist_dat_o[5] ,
+    \wbd_mbist_dat_o[4] ,
+    \wbd_mbist_dat_o[3] ,
+    \wbd_mbist_dat_o[2] ,
+    \wbd_mbist_dat_o[1] ,
+    \wbd_mbist_dat_o[0] }),
+    .s3_wbd_sel_o({\wbd_mbist_sel_o[3] ,
+    \wbd_mbist_sel_o[2] ,
+    \wbd_mbist_sel_o[1] ,
+    \wbd_mbist_sel_o[0] }));
+ mbist_top u_mbist (.bist_done(bist_done),
+    .bist_en(bist_en_rp),
+    .bist_load(bist_load_rp),
+    .bist_run(bist_run_rp),
+    .bist_sdi(bist_sdi_rp),
+    .bist_sdo(bist_sdo),
+    .bist_shift(bist_shift_rp),
+    .rst_n(bist_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_ack_o(wbd_mbist_ack_i),
+    .wb_clk2_i(wbd_clk_mbist_skew),
+    .wb_clk_i(wbd_clk_mbist_skew),
+    .wb_cyc_i(wbd_mbist_cyc_o),
+    .wb_stb_i(wbd_mbist_stb_o),
+    .wb_we_i(wbd_mbist_we_o),
+    .wbd_clk_int(wbd_clk_mbist1_rp),
+    .wbd_clk_mbist(wbd_clk_mbist_skew),
+    .bist_correct({\bist_correct[3] ,
+    \bist_correct[2] ,
+    \bist_correct[1] ,
+    \bist_correct[0] }),
+    .bist_error({\bist_error[3] ,
+    \bist_error[2] ,
+    \bist_error[1] ,
+    \bist_error[0] }),
+    .bist_error_cnt0({\bist_error_cnt0[3] ,
+    \bist_error_cnt0[2] ,
+    \bist_error_cnt0[1] ,
+    \bist_error_cnt0[0] }),
+    .bist_error_cnt1({\bist_error_cnt1[3] ,
+    \bist_error_cnt1[2] ,
+    \bist_error_cnt1[1] ,
+    \bist_error_cnt1[0] }),
+    .bist_error_cnt2({\bist_error_cnt2[3] ,
+    \bist_error_cnt2[2] ,
+    \bist_error_cnt2[1] ,
+    \bist_error_cnt2[0] }),
+    .bist_error_cnt3({\bist_error_cnt3[3] ,
+    \bist_error_cnt3[2] ,
+    \bist_error_cnt3[1] ,
+    \bist_error_cnt3[0] }),
+    .cfg_cska_mbist({\cfg_cska_mbist1_rp[3] ,
+    \cfg_cska_mbist1_rp[2] ,
+    \cfg_cska_mbist1_rp[1] ,
+    \cfg_cska_mbist1_rp[0] }),
+    .mem_addr_a0({\mem0_addr_a[10] ,
+    \mem0_addr_a[9] ,
+    \mem0_addr_a[8] ,
+    \mem0_addr_a[7] ,
+    \mem0_addr_a[6] ,
+    \mem0_addr_a[5] ,
+    \mem0_addr_a[4] ,
+    \mem0_addr_a[3] ,
+    \mem0_addr_a[2] }),
+    .mem_addr_a1({\mem1_addr_a[10] ,
+    \mem1_addr_a[9] ,
+    \mem1_addr_a[8] ,
+    \mem1_addr_a[7] ,
+    \mem1_addr_a[6] ,
+    \mem1_addr_a[5] ,
+    \mem1_addr_a[4] ,
+    \mem1_addr_a[3] ,
+    \mem1_addr_a[2] }),
+    .mem_addr_a2({\mem2_addr_a[10] ,
+    \mem2_addr_a[9] ,
+    \mem2_addr_a[8] ,
+    \mem2_addr_a[7] ,
+    \mem2_addr_a[6] ,
+    \mem2_addr_a[5] ,
+    \mem2_addr_a[4] ,
+    \mem2_addr_a[3] ,
+    \mem2_addr_a[2] }),
+    .mem_addr_a3({\mem3_addr_a[10] ,
+    \mem3_addr_a[9] ,
+    \mem3_addr_a[8] ,
+    \mem3_addr_a[7] ,
+    \mem3_addr_a[6] ,
+    \mem3_addr_a[5] ,
+    \mem3_addr_a[4] ,
+    \mem3_addr_a[3] ,
+    \mem3_addr_a[2] }),
+    .mem_addr_b0({\mem0_addr_b[10] ,
+    \mem0_addr_b[9] ,
+    \mem0_addr_b[8] ,
+    \mem0_addr_b[7] ,
+    \mem0_addr_b[6] ,
+    \mem0_addr_b[5] ,
+    \mem0_addr_b[4] ,
+    \mem0_addr_b[3] ,
+    \mem0_addr_b[2] }),
+    .mem_addr_b1({\mem1_addr_b[10] ,
+    \mem1_addr_b[9] ,
+    \mem1_addr_b[8] ,
+    \mem1_addr_b[7] ,
+    \mem1_addr_b[6] ,
+    \mem1_addr_b[5] ,
+    \mem1_addr_b[4] ,
+    \mem1_addr_b[3] ,
+    \mem1_addr_b[2] }),
+    .mem_addr_b2({\mem2_addr_b[10] ,
+    \mem2_addr_b[9] ,
+    \mem2_addr_b[8] ,
+    \mem2_addr_b[7] ,
+    \mem2_addr_b[6] ,
+    \mem2_addr_b[5] ,
+    \mem2_addr_b[4] ,
+    \mem2_addr_b[3] ,
+    \mem2_addr_b[2] }),
+    .mem_addr_b3({\mem3_addr_b[10] ,
+    \mem3_addr_b[9] ,
+    \mem3_addr_b[8] ,
+    \mem3_addr_b[7] ,
+    \mem3_addr_b[6] ,
+    \mem3_addr_b[5] ,
+    \mem3_addr_b[4] ,
+    \mem3_addr_b[3] ,
+    \mem3_addr_b[2] }),
+    .mem_cen_a({\mem_cen_a[3] ,
+    \mem_cen_a[2] ,
+    \mem_cen_a[1] ,
+    \mem_cen_a[0] }),
+    .mem_cen_b({\mem_cen_b[3] ,
+    \mem_cen_b[2] ,
+    \mem_cen_b[1] ,
+    \mem_cen_b[0] }),
+    .mem_clk_a({\mem_clk_a[3] ,
+    \mem_clk_a[2] ,
+    \mem_clk_a[1] ,
+    \mem_clk_a[0] }),
+    .mem_clk_b({\mem_clk_b[3] ,
+    \mem_clk_b[2] ,
+    \mem_clk_b[1] ,
+    \mem_clk_b[0] }),
+    .mem_din_a0({\mem0_din_a[31] ,
+    \mem0_din_a[30] ,
+    \mem0_din_a[29] ,
+    \mem0_din_a[28] ,
+    \mem0_din_a[27] ,
+    \mem0_din_a[26] ,
+    \mem0_din_a[25] ,
+    \mem0_din_a[24] ,
+    \mem0_din_a[23] ,
+    \mem0_din_a[22] ,
+    \mem0_din_a[21] ,
+    \mem0_din_a[20] ,
+    \mem0_din_a[19] ,
+    \mem0_din_a[18] ,
+    \mem0_din_a[17] ,
+    \mem0_din_a[16] ,
+    \mem0_din_a[15] ,
+    \mem0_din_a[14] ,
+    \mem0_din_a[13] ,
+    \mem0_din_a[12] ,
+    \mem0_din_a[11] ,
+    \mem0_din_a[10] ,
+    \mem0_din_a[9] ,
+    \mem0_din_a[8] ,
+    \mem0_din_a[7] ,
+    \mem0_din_a[6] ,
+    \mem0_din_a[5] ,
+    \mem0_din_a[4] ,
+    \mem0_din_a[3] ,
+    \mem0_din_a[2] ,
+    \mem0_din_a[1] ,
+    \mem0_din_a[0] }),
+    .mem_din_a1({\mem1_din_a[31] ,
+    \mem1_din_a[30] ,
+    \mem1_din_a[29] ,
+    \mem1_din_a[28] ,
+    \mem1_din_a[27] ,
+    \mem1_din_a[26] ,
+    \mem1_din_a[25] ,
+    \mem1_din_a[24] ,
+    \mem1_din_a[23] ,
+    \mem1_din_a[22] ,
+    \mem1_din_a[21] ,
+    \mem1_din_a[20] ,
+    \mem1_din_a[19] ,
+    \mem1_din_a[18] ,
+    \mem1_din_a[17] ,
+    \mem1_din_a[16] ,
+    \mem1_din_a[15] ,
+    \mem1_din_a[14] ,
+    \mem1_din_a[13] ,
+    \mem1_din_a[12] ,
+    \mem1_din_a[11] ,
+    \mem1_din_a[10] ,
+    \mem1_din_a[9] ,
+    \mem1_din_a[8] ,
+    \mem1_din_a[7] ,
+    \mem1_din_a[6] ,
+    \mem1_din_a[5] ,
+    \mem1_din_a[4] ,
+    \mem1_din_a[3] ,
+    \mem1_din_a[2] ,
+    \mem1_din_a[1] ,
+    \mem1_din_a[0] }),
+    .mem_din_a2({\mem2_din_a[31] ,
+    \mem2_din_a[30] ,
+    \mem2_din_a[29] ,
+    \mem2_din_a[28] ,
+    \mem2_din_a[27] ,
+    \mem2_din_a[26] ,
+    \mem2_din_a[25] ,
+    \mem2_din_a[24] ,
+    \mem2_din_a[23] ,
+    \mem2_din_a[22] ,
+    \mem2_din_a[21] ,
+    \mem2_din_a[20] ,
+    \mem2_din_a[19] ,
+    \mem2_din_a[18] ,
+    \mem2_din_a[17] ,
+    \mem2_din_a[16] ,
+    \mem2_din_a[15] ,
+    \mem2_din_a[14] ,
+    \mem2_din_a[13] ,
+    \mem2_din_a[12] ,
+    \mem2_din_a[11] ,
+    \mem2_din_a[10] ,
+    \mem2_din_a[9] ,
+    \mem2_din_a[8] ,
+    \mem2_din_a[7] ,
+    \mem2_din_a[6] ,
+    \mem2_din_a[5] ,
+    \mem2_din_a[4] ,
+    \mem2_din_a[3] ,
+    \mem2_din_a[2] ,
+    \mem2_din_a[1] ,
+    \mem2_din_a[0] }),
+    .mem_din_a3({\mem3_din_a[31] ,
+    \mem3_din_a[30] ,
+    \mem3_din_a[29] ,
+    \mem3_din_a[28] ,
+    \mem3_din_a[27] ,
+    \mem3_din_a[26] ,
+    \mem3_din_a[25] ,
+    \mem3_din_a[24] ,
+    \mem3_din_a[23] ,
+    \mem3_din_a[22] ,
+    \mem3_din_a[21] ,
+    \mem3_din_a[20] ,
+    \mem3_din_a[19] ,
+    \mem3_din_a[18] ,
+    \mem3_din_a[17] ,
+    \mem3_din_a[16] ,
+    \mem3_din_a[15] ,
+    \mem3_din_a[14] ,
+    \mem3_din_a[13] ,
+    \mem3_din_a[12] ,
+    \mem3_din_a[11] ,
+    \mem3_din_a[10] ,
+    \mem3_din_a[9] ,
+    \mem3_din_a[8] ,
+    \mem3_din_a[7] ,
+    \mem3_din_a[6] ,
+    \mem3_din_a[5] ,
+    \mem3_din_a[4] ,
+    \mem3_din_a[3] ,
+    \mem3_din_a[2] ,
+    \mem3_din_a[1] ,
+    \mem3_din_a[0] }),
+    .mem_dout_a0({\mem0_dout_a[31] ,
+    \mem0_dout_a[30] ,
+    \mem0_dout_a[29] ,
+    \mem0_dout_a[28] ,
+    \mem0_dout_a[27] ,
+    \mem0_dout_a[26] ,
+    \mem0_dout_a[25] ,
+    \mem0_dout_a[24] ,
+    \mem0_dout_a[23] ,
+    \mem0_dout_a[22] ,
+    \mem0_dout_a[21] ,
+    \mem0_dout_a[20] ,
+    \mem0_dout_a[19] ,
+    \mem0_dout_a[18] ,
+    \mem0_dout_a[17] ,
+    \mem0_dout_a[16] ,
+    \mem0_dout_a[15] ,
+    \mem0_dout_a[14] ,
+    \mem0_dout_a[13] ,
+    \mem0_dout_a[12] ,
+    \mem0_dout_a[11] ,
+    \mem0_dout_a[10] ,
+    \mem0_dout_a[9] ,
+    \mem0_dout_a[8] ,
+    \mem0_dout_a[7] ,
+    \mem0_dout_a[6] ,
+    \mem0_dout_a[5] ,
+    \mem0_dout_a[4] ,
+    \mem0_dout_a[3] ,
+    \mem0_dout_a[2] ,
+    \mem0_dout_a[1] ,
+    \mem0_dout_a[0] }),
+    .mem_dout_a1({\mem1_dout_a[31] ,
+    \mem1_dout_a[30] ,
+    \mem1_dout_a[29] ,
+    \mem1_dout_a[28] ,
+    \mem1_dout_a[27] ,
+    \mem1_dout_a[26] ,
+    \mem1_dout_a[25] ,
+    \mem1_dout_a[24] ,
+    \mem1_dout_a[23] ,
+    \mem1_dout_a[22] ,
+    \mem1_dout_a[21] ,
+    \mem1_dout_a[20] ,
+    \mem1_dout_a[19] ,
+    \mem1_dout_a[18] ,
+    \mem1_dout_a[17] ,
+    \mem1_dout_a[16] ,
+    \mem1_dout_a[15] ,
+    \mem1_dout_a[14] ,
+    \mem1_dout_a[13] ,
+    \mem1_dout_a[12] ,
+    \mem1_dout_a[11] ,
+    \mem1_dout_a[10] ,
+    \mem1_dout_a[9] ,
+    \mem1_dout_a[8] ,
+    \mem1_dout_a[7] ,
+    \mem1_dout_a[6] ,
+    \mem1_dout_a[5] ,
+    \mem1_dout_a[4] ,
+    \mem1_dout_a[3] ,
+    \mem1_dout_a[2] ,
+    \mem1_dout_a[1] ,
+    \mem1_dout_a[0] }),
+    .mem_dout_a2({\mem2_dout_a[31] ,
+    \mem2_dout_a[30] ,
+    \mem2_dout_a[29] ,
+    \mem2_dout_a[28] ,
+    \mem2_dout_a[27] ,
+    \mem2_dout_a[26] ,
+    \mem2_dout_a[25] ,
+    \mem2_dout_a[24] ,
+    \mem2_dout_a[23] ,
+    \mem2_dout_a[22] ,
+    \mem2_dout_a[21] ,
+    \mem2_dout_a[20] ,
+    \mem2_dout_a[19] ,
+    \mem2_dout_a[18] ,
+    \mem2_dout_a[17] ,
+    \mem2_dout_a[16] ,
+    \mem2_dout_a[15] ,
+    \mem2_dout_a[14] ,
+    \mem2_dout_a[13] ,
+    \mem2_dout_a[12] ,
+    \mem2_dout_a[11] ,
+    \mem2_dout_a[10] ,
+    \mem2_dout_a[9] ,
+    \mem2_dout_a[8] ,
+    \mem2_dout_a[7] ,
+    \mem2_dout_a[6] ,
+    \mem2_dout_a[5] ,
+    \mem2_dout_a[4] ,
+    \mem2_dout_a[3] ,
+    \mem2_dout_a[2] ,
+    \mem2_dout_a[1] ,
+    \mem2_dout_a[0] }),
+    .mem_dout_a3({\mem3_dout_a[31] ,
+    \mem3_dout_a[30] ,
+    \mem3_dout_a[29] ,
+    \mem3_dout_a[28] ,
+    \mem3_dout_a[27] ,
+    \mem3_dout_a[26] ,
+    \mem3_dout_a[25] ,
+    \mem3_dout_a[24] ,
+    \mem3_dout_a[23] ,
+    \mem3_dout_a[22] ,
+    \mem3_dout_a[21] ,
+    \mem3_dout_a[20] ,
+    \mem3_dout_a[19] ,
+    \mem3_dout_a[18] ,
+    \mem3_dout_a[17] ,
+    \mem3_dout_a[16] ,
+    \mem3_dout_a[15] ,
+    \mem3_dout_a[14] ,
+    \mem3_dout_a[13] ,
+    \mem3_dout_a[12] ,
+    \mem3_dout_a[11] ,
+    \mem3_dout_a[10] ,
+    \mem3_dout_a[9] ,
+    \mem3_dout_a[8] ,
+    \mem3_dout_a[7] ,
+    \mem3_dout_a[6] ,
+    \mem3_dout_a[5] ,
+    \mem3_dout_a[4] ,
+    \mem3_dout_a[3] ,
+    \mem3_dout_a[2] ,
+    \mem3_dout_a[1] ,
+    \mem3_dout_a[0] }),
+    .mem_mask_a0({\mem0_mask_a[3] ,
+    \mem0_mask_a[2] ,
+    \mem0_mask_a[1] ,
+    \mem0_mask_a[0] }),
+    .mem_mask_a1({\mem1_mask_a[3] ,
+    \mem1_mask_a[2] ,
+    \mem1_mask_a[1] ,
+    \mem1_mask_a[0] }),
+    .mem_mask_a2({\mem2_mask_a[3] ,
+    \mem2_mask_a[2] ,
+    \mem2_mask_a[1] ,
+    \mem2_mask_a[0] }),
+    .mem_mask_a3({\mem3_mask_a[3] ,
+    \mem3_mask_a[2] ,
+    \mem3_mask_a[1] ,
+    \mem3_mask_a[0] }),
+    .mem_web_a({\mem_web_a[3] ,
+    \mem_web_a[2] ,
+    \mem_web_a[1] ,
+    \mem_web_a[0] }),
+    .wb_adr_i({\wbd_mbist_adr_o[10] ,
+    \wbd_mbist_adr_o[9] ,
+    \wbd_mbist_adr_o[8] ,
+    \wbd_mbist_adr_o[7] ,
+    \wbd_mbist_adr_o[6] ,
+    \wbd_mbist_adr_o[5] ,
+    \wbd_mbist_adr_o[4] ,
+    \wbd_mbist_adr_o[3] ,
+    \wbd_mbist_adr_o[2] }),
+    .wb_cs_i({\wbd_mbist_adr_o[12] ,
+    \wbd_mbist_adr_o[11] }),
+    .wb_dat_i({\wbd_mbist_dat_o[31] ,
+    \wbd_mbist_dat_o[30] ,
+    \wbd_mbist_dat_o[29] ,
+    \wbd_mbist_dat_o[28] ,
+    \wbd_mbist_dat_o[27] ,
+    \wbd_mbist_dat_o[26] ,
+    \wbd_mbist_dat_o[25] ,
+    \wbd_mbist_dat_o[24] ,
+    \wbd_mbist_dat_o[23] ,
+    \wbd_mbist_dat_o[22] ,
+    \wbd_mbist_dat_o[21] ,
+    \wbd_mbist_dat_o[20] ,
+    \wbd_mbist_dat_o[19] ,
+    \wbd_mbist_dat_o[18] ,
+    \wbd_mbist_dat_o[17] ,
+    \wbd_mbist_dat_o[16] ,
+    \wbd_mbist_dat_o[15] ,
+    \wbd_mbist_dat_o[14] ,
+    \wbd_mbist_dat_o[13] ,
+    \wbd_mbist_dat_o[12] ,
+    \wbd_mbist_dat_o[11] ,
+    \wbd_mbist_dat_o[10] ,
+    \wbd_mbist_dat_o[9] ,
+    \wbd_mbist_dat_o[8] ,
+    \wbd_mbist_dat_o[7] ,
+    \wbd_mbist_dat_o[6] ,
+    \wbd_mbist_dat_o[5] ,
+    \wbd_mbist_dat_o[4] ,
+    \wbd_mbist_dat_o[3] ,
+    \wbd_mbist_dat_o[2] ,
+    \wbd_mbist_dat_o[1] ,
+    \wbd_mbist_dat_o[0] }),
+    .wb_dat_o({\wbd_mbist_dat_i[31] ,
+    \wbd_mbist_dat_i[30] ,
+    \wbd_mbist_dat_i[29] ,
+    \wbd_mbist_dat_i[28] ,
+    \wbd_mbist_dat_i[27] ,
+    \wbd_mbist_dat_i[26] ,
+    \wbd_mbist_dat_i[25] ,
+    \wbd_mbist_dat_i[24] ,
+    \wbd_mbist_dat_i[23] ,
+    \wbd_mbist_dat_i[22] ,
+    \wbd_mbist_dat_i[21] ,
+    \wbd_mbist_dat_i[20] ,
+    \wbd_mbist_dat_i[19] ,
+    \wbd_mbist_dat_i[18] ,
+    \wbd_mbist_dat_i[17] ,
+    \wbd_mbist_dat_i[16] ,
+    \wbd_mbist_dat_i[15] ,
+    \wbd_mbist_dat_i[14] ,
+    \wbd_mbist_dat_i[13] ,
+    \wbd_mbist_dat_i[12] ,
+    \wbd_mbist_dat_i[11] ,
+    \wbd_mbist_dat_i[10] ,
+    \wbd_mbist_dat_i[9] ,
+    \wbd_mbist_dat_i[8] ,
+    \wbd_mbist_dat_i[7] ,
+    \wbd_mbist_dat_i[6] ,
+    \wbd_mbist_dat_i[5] ,
+    \wbd_mbist_dat_i[4] ,
+    \wbd_mbist_dat_i[3] ,
+    \wbd_mbist_dat_i[2] ,
+    \wbd_mbist_dat_i[1] ,
+    \wbd_mbist_dat_i[0] }),
+    .wb_sel_i({\wbd_mbist_sel_o[3] ,
+    \wbd_mbist_sel_o[2] ,
+    \wbd_mbist_sel_o[1] ,
+    \wbd_mbist_sel_o[0] }));
+ pinmux u_pinmux (.bist_done(bist_done_rp),
+    .bist_en(bist_en),
+    .bist_load(bist_load),
+    .bist_run(bist_run),
+    .bist_sdi(bist_sdi),
+    .bist_sdo(bist_sdo_rp),
+    .bist_shift(bist_shift),
+    .h_reset_n(wbd_int_rst_n),
+    .i2cm_clk_i(i2cm_clk_i),
+    .i2cm_clk_o(i2cm_clk_o),
+    .i2cm_clk_oen(i2cm_clk_oen),
+    .i2cm_data_i(i2cm_data_i),
+    .i2cm_data_o(i2cm_data_o),
+    .i2cm_data_oen(i2cm_data_oen),
+    .i2cm_intr(i2cm_intr_o),
+    .mclk(wbd_clk_pinmux_skew),
+    .pulse1m_mclk(pulse1m_mclk),
+    .reg_ack(wbd_glbl_ack_i),
+    .reg_cs(wbd_glbl_stb_o),
+    .reg_wr(wbd_glbl_we_o),
+    .sflash_sck(sflash_sck),
+    .sflash_ss(sflash_ss),
+    .soft_irq(soft_irq),
+    .spim_miso(sspim_so),
+    .spim_mosi(sspim_si),
+    .spim_sck(sspim_sck),
+    .spim_ss(sspim_ssn),
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+    .usb_dn_i(usb_dn_i),
+    .usb_dn_o(usb_dn_o),
+    .usb_dp_i(usb_dp_i),
+    .usb_dp_o(usb_dp_o),
+    .usb_intr(usb_intr_o),
+    .usb_oen(usb_oen),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_pinmux_rp),
+    .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+    .bist_correct({\bist_correct_rp[3] ,
+    \bist_correct_rp[2] ,
+    \bist_correct_rp[1] ,
+    \bist_correct_rp[0] }),
+    .bist_error({\bist_error_rp[3] ,
+    \bist_error_rp[2] ,
+    \bist_error_rp[1] ,
+    \bist_error_rp[0] }),
+    .bist_error_cnt0({\bist_error_cnt0_rp[3] ,
+    \bist_error_cnt0_rp[2] ,
+    \bist_error_cnt0_rp[1] ,
+    \bist_error_cnt0_rp[0] }),
+    .bist_error_cnt1({\bist_error_cnt1_rp[3] ,
+    \bist_error_cnt1_rp[2] ,
+    \bist_error_cnt1_rp[1] ,
+    \bist_error_cnt1_rp[0] }),
+    .bist_error_cnt2({\bist_error_cnt2_rp[3] ,
+    \bist_error_cnt2_rp[2] ,
+    \bist_error_cnt2_rp[1] ,
+    \bist_error_cnt2_rp[0] }),
+    .bist_error_cnt3({\bist_error_cnt3_rp[3] ,
+    \bist_error_cnt3_rp[2] ,
+    \bist_error_cnt3_rp[1] ,
+    \bist_error_cnt3_rp[0] }),
+    .cfg_cska_pinmux({\cfg_cska_pinmux_rp[3] ,
+    \cfg_cska_pinmux_rp[2] ,
+    \cfg_cska_pinmux_rp[1] ,
+    \cfg_cska_pinmux_rp[0] }),
+    .digital_io_in({io_in[37],
+    io_in[36],
+    io_in[35],
+    io_in[34],
+    io_in[33],
+    io_in[32],
+    io_in[31],
+    io_in[30],
+    io_in[29],
+    io_in[28],
+    io_in[27],
+    io_in[26],
+    io_in[25],
+    io_in[24],
+    io_in[23],
+    io_in[22],
+    io_in[21],
+    io_in[20],
+    io_in[19],
+    io_in[18],
+    io_in[17],
+    io_in[16],
+    io_in[15],
+    io_in[14],
+    io_in[13],
+    io_in[12],
+    io_in[11],
+    io_in[10],
+    io_in[9],
+    io_in[8],
+    io_in[7],
+    io_in[6],
+    io_in[5],
+    io_in[4],
+    io_in[3],
+    io_in[2],
+    io_in[1],
+    io_in[0]}),
+    .digital_io_oen({io_oeb[37],
+    io_oeb[36],
+    io_oeb[35],
+    io_oeb[34],
+    io_oeb[33],
+    io_oeb[32],
+    io_oeb[31],
+    io_oeb[30],
+    io_oeb[29],
+    io_oeb[28],
+    io_oeb[27],
+    io_oeb[26],
+    io_oeb[25],
+    io_oeb[24],
+    io_oeb[23],
+    io_oeb[22],
+    io_oeb[21],
+    io_oeb[20],
+    io_oeb[19],
+    io_oeb[18],
+    io_oeb[17],
+    io_oeb[16],
+    io_oeb[15],
+    io_oeb[14],
+    io_oeb[13],
+    io_oeb[12],
+    io_oeb[11],
+    io_oeb[10],
+    io_oeb[9],
+    io_oeb[8],
+    io_oeb[7],
+    io_oeb[6],
+    io_oeb[5],
+    io_oeb[4],
+    io_oeb[3],
+    io_oeb[2],
+    io_oeb[1],
+    io_oeb[0]}),
+    .digital_io_out({io_out[37],
+    io_out[36],
+    io_out[35],
+    io_out[34],
+    io_out[33],
+    io_out[32],
+    io_out[31],
+    io_out[30],
+    io_out[29],
+    io_out[28],
+    io_out[27],
+    io_out[26],
+    io_out[25],
+    io_out[24],
+    io_out[23],
+    io_out[22],
+    io_out[21],
+    io_out[20],
+    io_out[19],
+    io_out[18],
+    io_out[17],
+    io_out[16],
+    io_out[15],
+    io_out[14],
+    io_out[13],
+    io_out[12],
+    io_out[11],
+    io_out[10],
+    io_out[9],
+    io_out[8],
+    io_out[7],
+    io_out[6],
+    io_out[5],
+    io_out[4],
+    io_out[3],
+    io_out[2],
+    io_out[1],
+    io_out[0]}),
+    .fuse_mhartid({\fuse_mhartid[31] ,
+    \fuse_mhartid[30] ,
+    \fuse_mhartid[29] ,
+    \fuse_mhartid[28] ,
+    \fuse_mhartid[27] ,
+    \fuse_mhartid[26] ,
+    \fuse_mhartid[25] ,
+    \fuse_mhartid[24] ,
+    \fuse_mhartid[23] ,
+    \fuse_mhartid[22] ,
+    \fuse_mhartid[21] ,
+    \fuse_mhartid[20] ,
+    \fuse_mhartid[19] ,
+    \fuse_mhartid[18] ,
+    \fuse_mhartid[17] ,
+    \fuse_mhartid[16] ,
+    \fuse_mhartid[15] ,
+    \fuse_mhartid[14] ,
+    \fuse_mhartid[13] ,
+    \fuse_mhartid[12] ,
+    \fuse_mhartid[11] ,
+    \fuse_mhartid[10] ,
+    \fuse_mhartid[9] ,
+    \fuse_mhartid[8] ,
+    \fuse_mhartid[7] ,
+    \fuse_mhartid[6] ,
+    \fuse_mhartid[5] ,
+    \fuse_mhartid[4] ,
+    \fuse_mhartid[3] ,
+    \fuse_mhartid[2] ,
+    \fuse_mhartid[1] ,
+    \fuse_mhartid[0] }),
+    .irq_lines({\irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] }),
+    .pinmux_debug({la_data_out[127],
+    la_data_out[126],
+    la_data_out[125],
+    la_data_out[124],
+    la_data_out[123],
+    la_data_out[122],
+    la_data_out[121],
+    la_data_out[120],
+    la_data_out[119],
+    la_data_out[118],
+    la_data_out[117],
+    la_data_out[116],
+    la_data_out[115],
+    la_data_out[114],
+    la_data_out[113],
+    la_data_out[112],
+    la_data_out[111],
+    la_data_out[110],
+    la_data_out[109],
+    la_data_out[108],
+    la_data_out[107],
+    la_data_out[106],
+    la_data_out[105],
+    la_data_out[104],
+    la_data_out[103],
+    la_data_out[102],
+    la_data_out[101],
+    la_data_out[100],
+    la_data_out[99],
+    la_data_out[98],
+    la_data_out[97],
+    la_data_out[96]}),
+    .reg_addr({\wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .reg_be({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .reg_rdata({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .reg_wdata({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .sflash_di({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .sflash_do({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .sflash_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}));
+ qspim_top u_qspi_master (.mclk(wbd_clk_spi),
+    .rst_n(qspim_rst_n),
+    .spi_clk(sflash_sck),
+    .spi_csn0(sflash_ss),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_ack_o(wbd_spim_ack_i),
+    .wbd_clk_int(wbd_clk_qspi_rp),
+    .wbd_clk_spi(wbd_clk_spi),
+    .wbd_err_o(wbd_spim_err_i),
+    .wbd_stb_i(wbd_spim_stb_o),
+    .wbd_we_i(wbd_spim_we_o),
+    .cfg_cska_sp_co({\cfg_cska_qspi_co_rp[3] ,
+    \cfg_cska_qspi_co_rp[2] ,
+    \cfg_cska_qspi_co_rp[1] ,
+    \cfg_cska_qspi_co_rp[0] }),
+    .cfg_cska_spi({\cfg_cska_qspi_rp[3] ,
+    \cfg_cska_qspi_rp[2] ,
+    \cfg_cska_qspi_rp[1] ,
+    \cfg_cska_qspi_rp[0] }),
+    .spi_debug({la_data_out[95],
+    la_data_out[94],
+    la_data_out[93],
+    la_data_out[92],
+    la_data_out[91],
+    la_data_out[90],
+    la_data_out[89],
+    la_data_out[88],
+    la_data_out[87],
+    la_data_out[86],
+    la_data_out[85],
+    la_data_out[84],
+    la_data_out[83],
+    la_data_out[82],
+    la_data_out[81],
+    la_data_out[80],
+    la_data_out[79],
+    la_data_out[78],
+    la_data_out[77],
+    la_data_out[76],
+    la_data_out[75],
+    la_data_out[74],
+    la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64]}),
+    .spi_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .spi_sdi({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .spi_sdo({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .wbd_adr_i({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .wbd_dat_i({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .wbd_dat_o({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .wbd_sel_i({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }));
+ scr1_top_wb u_riscv_top (.core_clk(cpu_clk),
+    .cpu_rst_n(cpu_rst_n),
+    .pwrup_rst_n(wbd_int_rst_n),
+    .rst_n(wbd_int_rst_n),
+    .rtc_clk(rtc_clk),
+    .soft_irq(soft_irq_rp),
+    .sram0_clk0(sram0_clk0),
+    .sram0_clk1(sram0_clk1),
+    .sram0_csb0(sram0_csb0),
+    .sram0_csb1(sram0_csb1),
+    .sram0_web0(sram0_web0),
+    .sram1_clk0(sram1_clk0),
+    .sram1_clk1(sram1_clk1),
+    .sram1_csb0(sram1_csb0),
+    .sram1_csb1(sram1_csb1),
+    .sram1_web0(sram1_web0),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_clk(wbd_clk_riscv_skew),
+    .wb_rst_n(wbd_int_rst_n),
+    .wbd_clk_int(wbd_clk_risc_rp),
+    .wbd_clk_riscv(wbd_clk_riscv_skew),
+    .wbd_dmem_ack_i(wbd_riscv_dmem_ack_o),
+    .wbd_dmem_err_i(wbd_riscv_dmem_err_o),
+    .wbd_dmem_stb_o(wbd_riscv_dmem_stb_i),
+    .wbd_dmem_we_o(wbd_riscv_dmem_we_i),
+    .wbd_imem_ack_i(wbd_riscv_imem_ack_o),
+    .wbd_imem_err_i(wbd_riscv_imem_err_o),
+    .wbd_imem_stb_o(wbd_riscv_imem_stb_i),
+    .wbd_imem_we_o(wbd_riscv_imem_we_i),
+    .cfg_cska_riscv({\cfg_cska_riscv_rp[3] ,
+    \cfg_cska_riscv_rp[2] ,
+    \cfg_cska_riscv_rp[1] ,
+    \cfg_cska_riscv_rp[0] }),
+    .fuse_mhartid({\fuse_mhartid_rp[31] ,
+    \fuse_mhartid_rp[30] ,
+    \fuse_mhartid_rp[29] ,
+    \fuse_mhartid_rp[28] ,
+    \fuse_mhartid_rp[27] ,
+    \fuse_mhartid_rp[26] ,
+    \fuse_mhartid_rp[25] ,
+    \fuse_mhartid_rp[24] ,
+    \fuse_mhartid_rp[23] ,
+    \fuse_mhartid_rp[22] ,
+    \fuse_mhartid_rp[21] ,
+    \fuse_mhartid_rp[20] ,
+    \fuse_mhartid_rp[19] ,
+    \fuse_mhartid_rp[18] ,
+    \fuse_mhartid_rp[17] ,
+    \fuse_mhartid_rp[16] ,
+    \fuse_mhartid_rp[15] ,
+    \fuse_mhartid_rp[14] ,
+    \fuse_mhartid_rp[13] ,
+    \fuse_mhartid_rp[12] ,
+    \fuse_mhartid_rp[11] ,
+    \fuse_mhartid_rp[10] ,
+    \fuse_mhartid_rp[9] ,
+    \fuse_mhartid_rp[8] ,
+    \fuse_mhartid_rp[7] ,
+    \fuse_mhartid_rp[6] ,
+    \fuse_mhartid_rp[5] ,
+    \fuse_mhartid_rp[4] ,
+    \fuse_mhartid_rp[3] ,
+    \fuse_mhartid_rp[2] ,
+    \fuse_mhartid_rp[1] ,
+    \fuse_mhartid_rp[0] }),
+    .irq_lines({\irq_lines_rp[15] ,
+    \irq_lines_rp[14] ,
+    \irq_lines_rp[13] ,
+    \irq_lines_rp[12] ,
+    \irq_lines_rp[11] ,
+    \irq_lines_rp[10] ,
+    \irq_lines_rp[9] ,
+    \irq_lines_rp[8] ,
+    \irq_lines_rp[7] ,
+    \irq_lines_rp[6] ,
+    \irq_lines_rp[5] ,
+    \irq_lines_rp[4] ,
+    \irq_lines_rp[3] ,
+    \irq_lines_rp[2] ,
+    \irq_lines_rp[1] ,
+    \irq_lines_rp[0] }),
+    .riscv_debug({la_data_out[63],
+    la_data_out[62],
+    la_data_out[61],
+    la_data_out[60],
+    la_data_out[59],
+    la_data_out[58],
+    la_data_out[57],
+    la_data_out[56],
+    la_data_out[55],
+    la_data_out[54],
+    la_data_out[53],
+    la_data_out[52],
+    la_data_out[51],
+    la_data_out[50],
+    la_data_out[49],
+    la_data_out[48],
+    la_data_out[47],
+    la_data_out[46],
+    la_data_out[45],
+    la_data_out[44],
+    la_data_out[43],
+    la_data_out[42],
+    la_data_out[41],
+    la_data_out[40],
+    la_data_out[39],
+    la_data_out[38],
+    la_data_out[37],
+    la_data_out[36],
+    la_data_out[35],
+    la_data_out[34],
+    la_data_out[33],
+    la_data_out[32],
+    la_data_out[31],
+    la_data_out[30],
+    la_data_out[29],
+    la_data_out[28],
+    la_data_out[27],
+    la_data_out[26],
+    la_data_out[25],
+    la_data_out[24],
+    la_data_out[23],
+    la_data_out[22],
+    la_data_out[21],
+    la_data_out[20],
+    la_data_out[19],
+    la_data_out[18],
+    la_data_out[17],
+    la_data_out[16],
+    la_data_out[15],
+    la_data_out[14],
+    la_data_out[13],
+    la_data_out[12],
+    la_data_out[11],
+    la_data_out[10],
+    la_data_out[9],
+    la_data_out[8],
+    la_data_out[7],
+    la_data_out[6],
+    la_data_out[5],
+    la_data_out[4],
+    la_data_out[3],
+    la_data_out[2],
+    la_data_out[1],
+    la_data_out[0]}),
+    .sram0_addr0({\sram0_addr0[8] ,
+    \sram0_addr0[7] ,
+    \sram0_addr0[6] ,
+    \sram0_addr0[5] ,
+    \sram0_addr0[4] ,
+    \sram0_addr0[3] ,
+    \sram0_addr0[2] ,
+    \sram0_addr0[1] ,
+    \sram0_addr0[0] }),
+    .sram0_addr1({\sram0_addr1[8] ,
+    \sram0_addr1[7] ,
+    \sram0_addr1[6] ,
+    \sram0_addr1[5] ,
+    \sram0_addr1[4] ,
+    \sram0_addr1[3] ,
+    \sram0_addr1[2] ,
+    \sram0_addr1[1] ,
+    \sram0_addr1[0] }),
+    .sram0_din0({\sram0_din0[31] ,
+    \sram0_din0[30] ,
+    \sram0_din0[29] ,
+    \sram0_din0[28] ,
+    \sram0_din0[27] ,
+    \sram0_din0[26] ,
+    \sram0_din0[25] ,
+    \sram0_din0[24] ,
+    \sram0_din0[23] ,
+    \sram0_din0[22] ,
+    \sram0_din0[21] ,
+    \sram0_din0[20] ,
+    \sram0_din0[19] ,
+    \sram0_din0[18] ,
+    \sram0_din0[17] ,
+    \sram0_din0[16] ,
+    \sram0_din0[15] ,
+    \sram0_din0[14] ,
+    \sram0_din0[13] ,
+    \sram0_din0[12] ,
+    \sram0_din0[11] ,
+    \sram0_din0[10] ,
+    \sram0_din0[9] ,
+    \sram0_din0[8] ,
+    \sram0_din0[7] ,
+    \sram0_din0[6] ,
+    \sram0_din0[5] ,
+    \sram0_din0[4] ,
+    \sram0_din0[3] ,
+    \sram0_din0[2] ,
+    \sram0_din0[1] ,
+    \sram0_din0[0] }),
+    .sram0_dout0({\sram0_dout0[31] ,
+    \sram0_dout0[30] ,
+    \sram0_dout0[29] ,
+    \sram0_dout0[28] ,
+    \sram0_dout0[27] ,
+    \sram0_dout0[26] ,
+    \sram0_dout0[25] ,
+    \sram0_dout0[24] ,
+    \sram0_dout0[23] ,
+    \sram0_dout0[22] ,
+    \sram0_dout0[21] ,
+    \sram0_dout0[20] ,
+    \sram0_dout0[19] ,
+    \sram0_dout0[18] ,
+    \sram0_dout0[17] ,
+    \sram0_dout0[16] ,
+    \sram0_dout0[15] ,
+    \sram0_dout0[14] ,
+    \sram0_dout0[13] ,
+    \sram0_dout0[12] ,
+    \sram0_dout0[11] ,
+    \sram0_dout0[10] ,
+    \sram0_dout0[9] ,
+    \sram0_dout0[8] ,
+    \sram0_dout0[7] ,
+    \sram0_dout0[6] ,
+    \sram0_dout0[5] ,
+    \sram0_dout0[4] ,
+    \sram0_dout0[3] ,
+    \sram0_dout0[2] ,
+    \sram0_dout0[1] ,
+    \sram0_dout0[0] }),
+    .sram0_dout1({\sram0_dout1[31] ,
+    \sram0_dout1[30] ,
+    \sram0_dout1[29] ,
+    \sram0_dout1[28] ,
+    \sram0_dout1[27] ,
+    \sram0_dout1[26] ,
+    \sram0_dout1[25] ,
+    \sram0_dout1[24] ,
+    \sram0_dout1[23] ,
+    \sram0_dout1[22] ,
+    \sram0_dout1[21] ,
+    \sram0_dout1[20] ,
+    \sram0_dout1[19] ,
+    \sram0_dout1[18] ,
+    \sram0_dout1[17] ,
+    \sram0_dout1[16] ,
+    \sram0_dout1[15] ,
+    \sram0_dout1[14] ,
+    \sram0_dout1[13] ,
+    \sram0_dout1[12] ,
+    \sram0_dout1[11] ,
+    \sram0_dout1[10] ,
+    \sram0_dout1[9] ,
+    \sram0_dout1[8] ,
+    \sram0_dout1[7] ,
+    \sram0_dout1[6] ,
+    \sram0_dout1[5] ,
+    \sram0_dout1[4] ,
+    \sram0_dout1[3] ,
+    \sram0_dout1[2] ,
+    \sram0_dout1[1] ,
+    \sram0_dout1[0] }),
+    .sram0_wmask0({\sram0_wmask0[3] ,
+    \sram0_wmask0[2] ,
+    \sram0_wmask0[1] ,
+    \sram0_wmask0[0] }),
+    .sram1_addr0({\sram1_addr0[8] ,
+    \sram1_addr0[7] ,
+    \sram1_addr0[6] ,
+    \sram1_addr0[5] ,
+    \sram1_addr0[4] ,
+    \sram1_addr0[3] ,
+    \sram1_addr0[2] ,
+    \sram1_addr0[1] ,
+    \sram1_addr0[0] }),
+    .sram1_addr1({\sram1_addr1[8] ,
+    \sram1_addr1[7] ,
+    \sram1_addr1[6] ,
+    \sram1_addr1[5] ,
+    \sram1_addr1[4] ,
+    \sram1_addr1[3] ,
+    \sram1_addr1[2] ,
+    \sram1_addr1[1] ,
+    \sram1_addr1[0] }),
+    .sram1_din0({\sram1_din0[31] ,
+    \sram1_din0[30] ,
+    \sram1_din0[29] ,
+    \sram1_din0[28] ,
+    \sram1_din0[27] ,
+    \sram1_din0[26] ,
+    \sram1_din0[25] ,
+    \sram1_din0[24] ,
+    \sram1_din0[23] ,
+    \sram1_din0[22] ,
+    \sram1_din0[21] ,
+    \sram1_din0[20] ,
+    \sram1_din0[19] ,
+    \sram1_din0[18] ,
+    \sram1_din0[17] ,
+    \sram1_din0[16] ,
+    \sram1_din0[15] ,
+    \sram1_din0[14] ,
+    \sram1_din0[13] ,
+    \sram1_din0[12] ,
+    \sram1_din0[11] ,
+    \sram1_din0[10] ,
+    \sram1_din0[9] ,
+    \sram1_din0[8] ,
+    \sram1_din0[7] ,
+    \sram1_din0[6] ,
+    \sram1_din0[5] ,
+    \sram1_din0[4] ,
+    \sram1_din0[3] ,
+    \sram1_din0[2] ,
+    \sram1_din0[1] ,
+    \sram1_din0[0] }),
+    .sram1_dout0({\sram1_dout0[31] ,
+    \sram1_dout0[30] ,
+    \sram1_dout0[29] ,
+    \sram1_dout0[28] ,
+    \sram1_dout0[27] ,
+    \sram1_dout0[26] ,
+    \sram1_dout0[25] ,
+    \sram1_dout0[24] ,
+    \sram1_dout0[23] ,
+    \sram1_dout0[22] ,
+    \sram1_dout0[21] ,
+    \sram1_dout0[20] ,
+    \sram1_dout0[19] ,
+    \sram1_dout0[18] ,
+    \sram1_dout0[17] ,
+    \sram1_dout0[16] ,
+    \sram1_dout0[15] ,
+    \sram1_dout0[14] ,
+    \sram1_dout0[13] ,
+    \sram1_dout0[12] ,
+    \sram1_dout0[11] ,
+    \sram1_dout0[10] ,
+    \sram1_dout0[9] ,
+    \sram1_dout0[8] ,
+    \sram1_dout0[7] ,
+    \sram1_dout0[6] ,
+    \sram1_dout0[5] ,
+    \sram1_dout0[4] ,
+    \sram1_dout0[3] ,
+    \sram1_dout0[2] ,
+    \sram1_dout0[1] ,
+    \sram1_dout0[0] }),
+    .sram1_dout1({\sram1_dout1[31] ,
+    \sram1_dout1[30] ,
+    \sram1_dout1[29] ,
+    \sram1_dout1[28] ,
+    \sram1_dout1[27] ,
+    \sram1_dout1[26] ,
+    \sram1_dout1[25] ,
+    \sram1_dout1[24] ,
+    \sram1_dout1[23] ,
+    \sram1_dout1[22] ,
+    \sram1_dout1[21] ,
+    \sram1_dout1[20] ,
+    \sram1_dout1[19] ,
+    \sram1_dout1[18] ,
+    \sram1_dout1[17] ,
+    \sram1_dout1[16] ,
+    \sram1_dout1[15] ,
+    \sram1_dout1[14] ,
+    \sram1_dout1[13] ,
+    \sram1_dout1[12] ,
+    \sram1_dout1[11] ,
+    \sram1_dout1[10] ,
+    \sram1_dout1[9] ,
+    \sram1_dout1[8] ,
+    \sram1_dout1[7] ,
+    \sram1_dout1[6] ,
+    \sram1_dout1[5] ,
+    \sram1_dout1[4] ,
+    \sram1_dout1[3] ,
+    \sram1_dout1[2] ,
+    \sram1_dout1[1] ,
+    \sram1_dout1[0] }),
+    .sram1_wmask0({\sram1_wmask0[3] ,
+    \sram1_wmask0[2] ,
+    \sram1_wmask0[1] ,
+    \sram1_wmask0[0] }),
+    .wbd_dmem_adr_o({\wbd_riscv_dmem_adr_i[31] ,
+    \wbd_riscv_dmem_adr_i[30] ,
+    \wbd_riscv_dmem_adr_i[29] ,
+    \wbd_riscv_dmem_adr_i[28] ,
+    \wbd_riscv_dmem_adr_i[27] ,
+    \wbd_riscv_dmem_adr_i[26] ,
+    \wbd_riscv_dmem_adr_i[25] ,
+    \wbd_riscv_dmem_adr_i[24] ,
+    \wbd_riscv_dmem_adr_i[23] ,
+    \wbd_riscv_dmem_adr_i[22] ,
+    \wbd_riscv_dmem_adr_i[21] ,
+    \wbd_riscv_dmem_adr_i[20] ,
+    \wbd_riscv_dmem_adr_i[19] ,
+    \wbd_riscv_dmem_adr_i[18] ,
+    \wbd_riscv_dmem_adr_i[17] ,
+    \wbd_riscv_dmem_adr_i[16] ,
+    \wbd_riscv_dmem_adr_i[15] ,
+    \wbd_riscv_dmem_adr_i[14] ,
+    \wbd_riscv_dmem_adr_i[13] ,
+    \wbd_riscv_dmem_adr_i[12] ,
+    \wbd_riscv_dmem_adr_i[11] ,
+    \wbd_riscv_dmem_adr_i[10] ,
+    \wbd_riscv_dmem_adr_i[9] ,
+    \wbd_riscv_dmem_adr_i[8] ,
+    \wbd_riscv_dmem_adr_i[7] ,
+    \wbd_riscv_dmem_adr_i[6] ,
+    \wbd_riscv_dmem_adr_i[5] ,
+    \wbd_riscv_dmem_adr_i[4] ,
+    \wbd_riscv_dmem_adr_i[3] ,
+    \wbd_riscv_dmem_adr_i[2] ,
+    \wbd_riscv_dmem_adr_i[1] ,
+    \wbd_riscv_dmem_adr_i[0] }),
+    .wbd_dmem_dat_i({\wbd_riscv_dmem_dat_o[31] ,
+    \wbd_riscv_dmem_dat_o[30] ,
+    \wbd_riscv_dmem_dat_o[29] ,
+    \wbd_riscv_dmem_dat_o[28] ,
+    \wbd_riscv_dmem_dat_o[27] ,
+    \wbd_riscv_dmem_dat_o[26] ,
+    \wbd_riscv_dmem_dat_o[25] ,
+    \wbd_riscv_dmem_dat_o[24] ,
+    \wbd_riscv_dmem_dat_o[23] ,
+    \wbd_riscv_dmem_dat_o[22] ,
+    \wbd_riscv_dmem_dat_o[21] ,
+    \wbd_riscv_dmem_dat_o[20] ,
+    \wbd_riscv_dmem_dat_o[19] ,
+    \wbd_riscv_dmem_dat_o[18] ,
+    \wbd_riscv_dmem_dat_o[17] ,
+    \wbd_riscv_dmem_dat_o[16] ,
+    \wbd_riscv_dmem_dat_o[15] ,
+    \wbd_riscv_dmem_dat_o[14] ,
+    \wbd_riscv_dmem_dat_o[13] ,
+    \wbd_riscv_dmem_dat_o[12] ,
+    \wbd_riscv_dmem_dat_o[11] ,
+    \wbd_riscv_dmem_dat_o[10] ,
+    \wbd_riscv_dmem_dat_o[9] ,
+    \wbd_riscv_dmem_dat_o[8] ,
+    \wbd_riscv_dmem_dat_o[7] ,
+    \wbd_riscv_dmem_dat_o[6] ,
+    \wbd_riscv_dmem_dat_o[5] ,
+    \wbd_riscv_dmem_dat_o[4] ,
+    \wbd_riscv_dmem_dat_o[3] ,
+    \wbd_riscv_dmem_dat_o[2] ,
+    \wbd_riscv_dmem_dat_o[1] ,
+    \wbd_riscv_dmem_dat_o[0] }),
+    .wbd_dmem_dat_o({\wbd_riscv_dmem_dat_i[31] ,
+    \wbd_riscv_dmem_dat_i[30] ,
+    \wbd_riscv_dmem_dat_i[29] ,
+    \wbd_riscv_dmem_dat_i[28] ,
+    \wbd_riscv_dmem_dat_i[27] ,
+    \wbd_riscv_dmem_dat_i[26] ,
+    \wbd_riscv_dmem_dat_i[25] ,
+    \wbd_riscv_dmem_dat_i[24] ,
+    \wbd_riscv_dmem_dat_i[23] ,
+    \wbd_riscv_dmem_dat_i[22] ,
+    \wbd_riscv_dmem_dat_i[21] ,
+    \wbd_riscv_dmem_dat_i[20] ,
+    \wbd_riscv_dmem_dat_i[19] ,
+    \wbd_riscv_dmem_dat_i[18] ,
+    \wbd_riscv_dmem_dat_i[17] ,
+    \wbd_riscv_dmem_dat_i[16] ,
+    \wbd_riscv_dmem_dat_i[15] ,
+    \wbd_riscv_dmem_dat_i[14] ,
+    \wbd_riscv_dmem_dat_i[13] ,
+    \wbd_riscv_dmem_dat_i[12] ,
+    \wbd_riscv_dmem_dat_i[11] ,
+    \wbd_riscv_dmem_dat_i[10] ,
+    \wbd_riscv_dmem_dat_i[9] ,
+    \wbd_riscv_dmem_dat_i[8] ,
+    \wbd_riscv_dmem_dat_i[7] ,
+    \wbd_riscv_dmem_dat_i[6] ,
+    \wbd_riscv_dmem_dat_i[5] ,
+    \wbd_riscv_dmem_dat_i[4] ,
+    \wbd_riscv_dmem_dat_i[3] ,
+    \wbd_riscv_dmem_dat_i[2] ,
+    \wbd_riscv_dmem_dat_i[1] ,
+    \wbd_riscv_dmem_dat_i[0] }),
+    .wbd_dmem_sel_o({\wbd_riscv_dmem_sel_i[3] ,
+    \wbd_riscv_dmem_sel_i[2] ,
+    \wbd_riscv_dmem_sel_i[1] ,
+    \wbd_riscv_dmem_sel_i[0] }),
+    .wbd_imem_adr_o({\wbd_riscv_imem_adr_i[31] ,
+    \wbd_riscv_imem_adr_i[30] ,
+    \wbd_riscv_imem_adr_i[29] ,
+    \wbd_riscv_imem_adr_i[28] ,
+    \wbd_riscv_imem_adr_i[27] ,
+    \wbd_riscv_imem_adr_i[26] ,
+    \wbd_riscv_imem_adr_i[25] ,
+    \wbd_riscv_imem_adr_i[24] ,
+    \wbd_riscv_imem_adr_i[23] ,
+    \wbd_riscv_imem_adr_i[22] ,
+    \wbd_riscv_imem_adr_i[21] ,
+    \wbd_riscv_imem_adr_i[20] ,
+    \wbd_riscv_imem_adr_i[19] ,
+    \wbd_riscv_imem_adr_i[18] ,
+    \wbd_riscv_imem_adr_i[17] ,
+    \wbd_riscv_imem_adr_i[16] ,
+    \wbd_riscv_imem_adr_i[15] ,
+    \wbd_riscv_imem_adr_i[14] ,
+    \wbd_riscv_imem_adr_i[13] ,
+    \wbd_riscv_imem_adr_i[12] ,
+    \wbd_riscv_imem_adr_i[11] ,
+    \wbd_riscv_imem_adr_i[10] ,
+    \wbd_riscv_imem_adr_i[9] ,
+    \wbd_riscv_imem_adr_i[8] ,
+    \wbd_riscv_imem_adr_i[7] ,
+    \wbd_riscv_imem_adr_i[6] ,
+    \wbd_riscv_imem_adr_i[5] ,
+    \wbd_riscv_imem_adr_i[4] ,
+    \wbd_riscv_imem_adr_i[3] ,
+    \wbd_riscv_imem_adr_i[2] ,
+    \wbd_riscv_imem_adr_i[1] ,
+    \wbd_riscv_imem_adr_i[0] }),
+    .wbd_imem_dat_i({\wbd_riscv_imem_dat_o[31] ,
+    \wbd_riscv_imem_dat_o[30] ,
+    \wbd_riscv_imem_dat_o[29] ,
+    \wbd_riscv_imem_dat_o[28] ,
+    \wbd_riscv_imem_dat_o[27] ,
+    \wbd_riscv_imem_dat_o[26] ,
+    \wbd_riscv_imem_dat_o[25] ,
+    \wbd_riscv_imem_dat_o[24] ,
+    \wbd_riscv_imem_dat_o[23] ,
+    \wbd_riscv_imem_dat_o[22] ,
+    \wbd_riscv_imem_dat_o[21] ,
+    \wbd_riscv_imem_dat_o[20] ,
+    \wbd_riscv_imem_dat_o[19] ,
+    \wbd_riscv_imem_dat_o[18] ,
+    \wbd_riscv_imem_dat_o[17] ,
+    \wbd_riscv_imem_dat_o[16] ,
+    \wbd_riscv_imem_dat_o[15] ,
+    \wbd_riscv_imem_dat_o[14] ,
+    \wbd_riscv_imem_dat_o[13] ,
+    \wbd_riscv_imem_dat_o[12] ,
+    \wbd_riscv_imem_dat_o[11] ,
+    \wbd_riscv_imem_dat_o[10] ,
+    \wbd_riscv_imem_dat_o[9] ,
+    \wbd_riscv_imem_dat_o[8] ,
+    \wbd_riscv_imem_dat_o[7] ,
+    \wbd_riscv_imem_dat_o[6] ,
+    \wbd_riscv_imem_dat_o[5] ,
+    \wbd_riscv_imem_dat_o[4] ,
+    \wbd_riscv_imem_dat_o[3] ,
+    \wbd_riscv_imem_dat_o[2] ,
+    \wbd_riscv_imem_dat_o[1] ,
+    \wbd_riscv_imem_dat_o[0] }),
+    .wbd_imem_dat_o({\wbd_riscv_imem_dat_i[31] ,
+    \wbd_riscv_imem_dat_i[30] ,
+    \wbd_riscv_imem_dat_i[29] ,
+    \wbd_riscv_imem_dat_i[28] ,
+    \wbd_riscv_imem_dat_i[27] ,
+    \wbd_riscv_imem_dat_i[26] ,
+    \wbd_riscv_imem_dat_i[25] ,
+    \wbd_riscv_imem_dat_i[24] ,
+    \wbd_riscv_imem_dat_i[23] ,
+    \wbd_riscv_imem_dat_i[22] ,
+    \wbd_riscv_imem_dat_i[21] ,
+    \wbd_riscv_imem_dat_i[20] ,
+    \wbd_riscv_imem_dat_i[19] ,
+    \wbd_riscv_imem_dat_i[18] ,
+    \wbd_riscv_imem_dat_i[17] ,
+    \wbd_riscv_imem_dat_i[16] ,
+    \wbd_riscv_imem_dat_i[15] ,
+    \wbd_riscv_imem_dat_i[14] ,
+    \wbd_riscv_imem_dat_i[13] ,
+    \wbd_riscv_imem_dat_i[12] ,
+    \wbd_riscv_imem_dat_i[11] ,
+    \wbd_riscv_imem_dat_i[10] ,
+    \wbd_riscv_imem_dat_i[9] ,
+    \wbd_riscv_imem_dat_i[8] ,
+    \wbd_riscv_imem_dat_i[7] ,
+    \wbd_riscv_imem_dat_i[6] ,
+    \wbd_riscv_imem_dat_i[5] ,
+    \wbd_riscv_imem_dat_i[4] ,
+    \wbd_riscv_imem_dat_i[3] ,
+    \wbd_riscv_imem_dat_i[2] ,
+    \wbd_riscv_imem_dat_i[1] ,
+    \wbd_riscv_imem_dat_i[0] }),
+    .wbd_imem_sel_o({\wbd_riscv_imem_sel_i[3] ,
+    \wbd_riscv_imem_sel_i[2] ,
+    \wbd_riscv_imem_sel_i[1] ,
+    \wbd_riscv_imem_sel_i[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb (.csb0(\mem_cen_a[0] ),
+    .csb1(\mem_cen_b[0] ),
+    .web0(\mem_web_a[0] ),
+    .clk0(\mem_clk_a[0] ),
+    .clk1(\mem_clk_b[0] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\mem0_addr_a[10] ,
+    \mem0_addr_a[9] ,
+    \mem0_addr_a[8] ,
+    \mem0_addr_a[7] ,
+    \mem0_addr_a[6] ,
+    \mem0_addr_a[5] ,
+    \mem0_addr_a[4] ,
+    \mem0_addr_a[3] ,
+    \mem0_addr_a[2] }),
+    .addr1({\mem0_addr_b[10] ,
+    \mem0_addr_b[9] ,
+    \mem0_addr_b[8] ,
+    \mem0_addr_b[7] ,
+    \mem0_addr_b[6] ,
+    \mem0_addr_b[5] ,
+    \mem0_addr_b[4] ,
+    \mem0_addr_b[3] ,
+    \mem0_addr_b[2] }),
+    .din0({\mem0_din_a[31] ,
+    \mem0_din_a[30] ,
+    \mem0_din_a[29] ,
+    \mem0_din_a[28] ,
+    \mem0_din_a[27] ,
+    \mem0_din_a[26] ,
+    \mem0_din_a[25] ,
+    \mem0_din_a[24] ,
+    \mem0_din_a[23] ,
+    \mem0_din_a[22] ,
+    \mem0_din_a[21] ,
+    \mem0_din_a[20] ,
+    \mem0_din_a[19] ,
+    \mem0_din_a[18] ,
+    \mem0_din_a[17] ,
+    \mem0_din_a[16] ,
+    \mem0_din_a[15] ,
+    \mem0_din_a[14] ,
+    \mem0_din_a[13] ,
+    \mem0_din_a[12] ,
+    \mem0_din_a[11] ,
+    \mem0_din_a[10] ,
+    \mem0_din_a[9] ,
+    \mem0_din_a[8] ,
+    \mem0_din_a[7] ,
+    \mem0_din_a[6] ,
+    \mem0_din_a[5] ,
+    \mem0_din_a[4] ,
+    \mem0_din_a[3] ,
+    \mem0_din_a[2] ,
+    \mem0_din_a[1] ,
+    \mem0_din_a[0] }),
+    .dout0({\mem0_dout_a[31] ,
+    \mem0_dout_a[30] ,
+    \mem0_dout_a[29] ,
+    \mem0_dout_a[28] ,
+    \mem0_dout_a[27] ,
+    \mem0_dout_a[26] ,
+    \mem0_dout_a[25] ,
+    \mem0_dout_a[24] ,
+    \mem0_dout_a[23] ,
+    \mem0_dout_a[22] ,
+    \mem0_dout_a[21] ,
+    \mem0_dout_a[20] ,
+    \mem0_dout_a[19] ,
+    \mem0_dout_a[18] ,
+    \mem0_dout_a[17] ,
+    \mem0_dout_a[16] ,
+    \mem0_dout_a[15] ,
+    \mem0_dout_a[14] ,
+    \mem0_dout_a[13] ,
+    \mem0_dout_a[12] ,
+    \mem0_dout_a[11] ,
+    \mem0_dout_a[10] ,
+    \mem0_dout_a[9] ,
+    \mem0_dout_a[8] ,
+    \mem0_dout_a[7] ,
+    \mem0_dout_a[6] ,
+    \mem0_dout_a[5] ,
+    \mem0_dout_a[4] ,
+    \mem0_dout_a[3] ,
+    \mem0_dout_a[2] ,
+    \mem0_dout_a[1] ,
+    \mem0_dout_a[0] }),
+    .dout1({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9,
+    _NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32}),
+    .wmask0({\mem0_mask_a[3] ,
+    \mem0_mask_a[2] ,
+    \mem0_mask_a[1] ,
+    \mem0_mask_a[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb (.csb0(\mem_cen_a[1] ),
+    .csb1(\mem_cen_b[1] ),
+    .web0(\mem_web_a[1] ),
+    .clk0(\mem_clk_a[1] ),
+    .clk1(\mem_clk_b[1] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\mem1_addr_a[10] ,
+    \mem1_addr_a[9] ,
+    \mem1_addr_a[8] ,
+    \mem1_addr_a[7] ,
+    \mem1_addr_a[6] ,
+    \mem1_addr_a[5] ,
+    \mem1_addr_a[4] ,
+    \mem1_addr_a[3] ,
+    \mem1_addr_a[2] }),
+    .addr1({\mem1_addr_b[10] ,
+    \mem1_addr_b[9] ,
+    \mem1_addr_b[8] ,
+    \mem1_addr_b[7] ,
+    \mem1_addr_b[6] ,
+    \mem1_addr_b[5] ,
+    \mem1_addr_b[4] ,
+    \mem1_addr_b[3] ,
+    \mem1_addr_b[2] }),
+    .din0({\mem1_din_a[31] ,
+    \mem1_din_a[30] ,
+    \mem1_din_a[29] ,
+    \mem1_din_a[28] ,
+    \mem1_din_a[27] ,
+    \mem1_din_a[26] ,
+    \mem1_din_a[25] ,
+    \mem1_din_a[24] ,
+    \mem1_din_a[23] ,
+    \mem1_din_a[22] ,
+    \mem1_din_a[21] ,
+    \mem1_din_a[20] ,
+    \mem1_din_a[19] ,
+    \mem1_din_a[18] ,
+    \mem1_din_a[17] ,
+    \mem1_din_a[16] ,
+    \mem1_din_a[15] ,
+    \mem1_din_a[14] ,
+    \mem1_din_a[13] ,
+    \mem1_din_a[12] ,
+    \mem1_din_a[11] ,
+    \mem1_din_a[10] ,
+    \mem1_din_a[9] ,
+    \mem1_din_a[8] ,
+    \mem1_din_a[7] ,
+    \mem1_din_a[6] ,
+    \mem1_din_a[5] ,
+    \mem1_din_a[4] ,
+    \mem1_din_a[3] ,
+    \mem1_din_a[2] ,
+    \mem1_din_a[1] ,
+    \mem1_din_a[0] }),
+    .dout0({\mem1_dout_a[31] ,
+    \mem1_dout_a[30] ,
+    \mem1_dout_a[29] ,
+    \mem1_dout_a[28] ,
+    \mem1_dout_a[27] ,
+    \mem1_dout_a[26] ,
+    \mem1_dout_a[25] ,
+    \mem1_dout_a[24] ,
+    \mem1_dout_a[23] ,
+    \mem1_dout_a[22] ,
+    \mem1_dout_a[21] ,
+    \mem1_dout_a[20] ,
+    \mem1_dout_a[19] ,
+    \mem1_dout_a[18] ,
+    \mem1_dout_a[17] ,
+    \mem1_dout_a[16] ,
+    \mem1_dout_a[15] ,
+    \mem1_dout_a[14] ,
+    \mem1_dout_a[13] ,
+    \mem1_dout_a[12] ,
+    \mem1_dout_a[11] ,
+    \mem1_dout_a[10] ,
+    \mem1_dout_a[9] ,
+    \mem1_dout_a[8] ,
+    \mem1_dout_a[7] ,
+    \mem1_dout_a[6] ,
+    \mem1_dout_a[5] ,
+    \mem1_dout_a[4] ,
+    \mem1_dout_a[3] ,
+    \mem1_dout_a[2] ,
+    \mem1_dout_a[1] ,
+    \mem1_dout_a[0] }),
+    .dout1({_NC33,
+    _NC34,
+    _NC35,
+    _NC36,
+    _NC37,
+    _NC38,
+    _NC39,
+    _NC40,
+    _NC41,
+    _NC42,
+    _NC43,
+    _NC44,
+    _NC45,
+    _NC46,
+    _NC47,
+    _NC48,
+    _NC49,
+    _NC50,
+    _NC51,
+    _NC52,
+    _NC53,
+    _NC54,
+    _NC55,
+    _NC56,
+    _NC57,
+    _NC58,
+    _NC59,
+    _NC60,
+    _NC61,
+    _NC62,
+    _NC63,
+    _NC64}),
+    .wmask0({\mem1_mask_a[3] ,
+    \mem1_mask_a[2] ,
+    \mem1_mask_a[1] ,
+    \mem1_mask_a[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb (.csb0(\mem_cen_a[2] ),
+    .csb1(\mem_cen_b[2] ),
+    .web0(\mem_web_a[2] ),
+    .clk0(\mem_clk_a[2] ),
+    .clk1(\mem_clk_b[2] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\mem2_addr_a[10] ,
+    \mem2_addr_a[9] ,
+    \mem2_addr_a[8] ,
+    \mem2_addr_a[7] ,
+    \mem2_addr_a[6] ,
+    \mem2_addr_a[5] ,
+    \mem2_addr_a[4] ,
+    \mem2_addr_a[3] ,
+    \mem2_addr_a[2] }),
+    .addr1({\mem2_addr_b[10] ,
+    \mem2_addr_b[9] ,
+    \mem2_addr_b[8] ,
+    \mem2_addr_b[7] ,
+    \mem2_addr_b[6] ,
+    \mem2_addr_b[5] ,
+    \mem2_addr_b[4] ,
+    \mem2_addr_b[3] ,
+    \mem2_addr_b[2] }),
+    .din0({\mem2_din_a[31] ,
+    \mem2_din_a[30] ,
+    \mem2_din_a[29] ,
+    \mem2_din_a[28] ,
+    \mem2_din_a[27] ,
+    \mem2_din_a[26] ,
+    \mem2_din_a[25] ,
+    \mem2_din_a[24] ,
+    \mem2_din_a[23] ,
+    \mem2_din_a[22] ,
+    \mem2_din_a[21] ,
+    \mem2_din_a[20] ,
+    \mem2_din_a[19] ,
+    \mem2_din_a[18] ,
+    \mem2_din_a[17] ,
+    \mem2_din_a[16] ,
+    \mem2_din_a[15] ,
+    \mem2_din_a[14] ,
+    \mem2_din_a[13] ,
+    \mem2_din_a[12] ,
+    \mem2_din_a[11] ,
+    \mem2_din_a[10] ,
+    \mem2_din_a[9] ,
+    \mem2_din_a[8] ,
+    \mem2_din_a[7] ,
+    \mem2_din_a[6] ,
+    \mem2_din_a[5] ,
+    \mem2_din_a[4] ,
+    \mem2_din_a[3] ,
+    \mem2_din_a[2] ,
+    \mem2_din_a[1] ,
+    \mem2_din_a[0] }),
+    .dout0({\mem2_dout_a[31] ,
+    \mem2_dout_a[30] ,
+    \mem2_dout_a[29] ,
+    \mem2_dout_a[28] ,
+    \mem2_dout_a[27] ,
+    \mem2_dout_a[26] ,
+    \mem2_dout_a[25] ,
+    \mem2_dout_a[24] ,
+    \mem2_dout_a[23] ,
+    \mem2_dout_a[22] ,
+    \mem2_dout_a[21] ,
+    \mem2_dout_a[20] ,
+    \mem2_dout_a[19] ,
+    \mem2_dout_a[18] ,
+    \mem2_dout_a[17] ,
+    \mem2_dout_a[16] ,
+    \mem2_dout_a[15] ,
+    \mem2_dout_a[14] ,
+    \mem2_dout_a[13] ,
+    \mem2_dout_a[12] ,
+    \mem2_dout_a[11] ,
+    \mem2_dout_a[10] ,
+    \mem2_dout_a[9] ,
+    \mem2_dout_a[8] ,
+    \mem2_dout_a[7] ,
+    \mem2_dout_a[6] ,
+    \mem2_dout_a[5] ,
+    \mem2_dout_a[4] ,
+    \mem2_dout_a[3] ,
+    \mem2_dout_a[2] ,
+    \mem2_dout_a[1] ,
+    \mem2_dout_a[0] }),
+    .dout1({_NC65,
+    _NC66,
+    _NC67,
+    _NC68,
+    _NC69,
+    _NC70,
+    _NC71,
+    _NC72,
+    _NC73,
+    _NC74,
+    _NC75,
+    _NC76,
+    _NC77,
+    _NC78,
+    _NC79,
+    _NC80,
+    _NC81,
+    _NC82,
+    _NC83,
+    _NC84,
+    _NC85,
+    _NC86,
+    _NC87,
+    _NC88,
+    _NC89,
+    _NC90,
+    _NC91,
+    _NC92,
+    _NC93,
+    _NC94,
+    _NC95,
+    _NC96}),
+    .wmask0({\mem2_mask_a[3] ,
+    \mem2_mask_a[2] ,
+    \mem2_mask_a[1] ,
+    \mem2_mask_a[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb (.csb0(\mem_cen_a[3] ),
+    .csb1(\mem_cen_b[3] ),
+    .web0(\mem_web_a[3] ),
+    .clk0(\mem_clk_a[3] ),
+    .clk1(\mem_clk_b[3] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\mem3_addr_a[10] ,
+    \mem3_addr_a[9] ,
+    \mem3_addr_a[8] ,
+    \mem3_addr_a[7] ,
+    \mem3_addr_a[6] ,
+    \mem3_addr_a[5] ,
+    \mem3_addr_a[4] ,
+    \mem3_addr_a[3] ,
+    \mem3_addr_a[2] }),
+    .addr1({\mem3_addr_b[10] ,
+    \mem3_addr_b[9] ,
+    \mem3_addr_b[8] ,
+    \mem3_addr_b[7] ,
+    \mem3_addr_b[6] ,
+    \mem3_addr_b[5] ,
+    \mem3_addr_b[4] ,
+    \mem3_addr_b[3] ,
+    \mem3_addr_b[2] }),
+    .din0({\mem3_din_a[31] ,
+    \mem3_din_a[30] ,
+    \mem3_din_a[29] ,
+    \mem3_din_a[28] ,
+    \mem3_din_a[27] ,
+    \mem3_din_a[26] ,
+    \mem3_din_a[25] ,
+    \mem3_din_a[24] ,
+    \mem3_din_a[23] ,
+    \mem3_din_a[22] ,
+    \mem3_din_a[21] ,
+    \mem3_din_a[20] ,
+    \mem3_din_a[19] ,
+    \mem3_din_a[18] ,
+    \mem3_din_a[17] ,
+    \mem3_din_a[16] ,
+    \mem3_din_a[15] ,
+    \mem3_din_a[14] ,
+    \mem3_din_a[13] ,
+    \mem3_din_a[12] ,
+    \mem3_din_a[11] ,
+    \mem3_din_a[10] ,
+    \mem3_din_a[9] ,
+    \mem3_din_a[8] ,
+    \mem3_din_a[7] ,
+    \mem3_din_a[6] ,
+    \mem3_din_a[5] ,
+    \mem3_din_a[4] ,
+    \mem3_din_a[3] ,
+    \mem3_din_a[2] ,
+    \mem3_din_a[1] ,
+    \mem3_din_a[0] }),
+    .dout0({\mem3_dout_a[31] ,
+    \mem3_dout_a[30] ,
+    \mem3_dout_a[29] ,
+    \mem3_dout_a[28] ,
+    \mem3_dout_a[27] ,
+    \mem3_dout_a[26] ,
+    \mem3_dout_a[25] ,
+    \mem3_dout_a[24] ,
+    \mem3_dout_a[23] ,
+    \mem3_dout_a[22] ,
+    \mem3_dout_a[21] ,
+    \mem3_dout_a[20] ,
+    \mem3_dout_a[19] ,
+    \mem3_dout_a[18] ,
+    \mem3_dout_a[17] ,
+    \mem3_dout_a[16] ,
+    \mem3_dout_a[15] ,
+    \mem3_dout_a[14] ,
+    \mem3_dout_a[13] ,
+    \mem3_dout_a[12] ,
+    \mem3_dout_a[11] ,
+    \mem3_dout_a[10] ,
+    \mem3_dout_a[9] ,
+    \mem3_dout_a[8] ,
+    \mem3_dout_a[7] ,
+    \mem3_dout_a[6] ,
+    \mem3_dout_a[5] ,
+    \mem3_dout_a[4] ,
+    \mem3_dout_a[3] ,
+    \mem3_dout_a[2] ,
+    \mem3_dout_a[1] ,
+    \mem3_dout_a[0] }),
+    .dout1({_NC97,
+    _NC98,
+    _NC99,
+    _NC100,
+    _NC101,
+    _NC102,
+    _NC103,
+    _NC104,
+    _NC105,
+    _NC106,
+    _NC107,
+    _NC108,
+    _NC109,
+    _NC110,
+    _NC111,
+    _NC112,
+    _NC113,
+    _NC114,
+    _NC115,
+    _NC116,
+    _NC117,
+    _NC118,
+    _NC119,
+    _NC120,
+    _NC121,
+    _NC122,
+    _NC123,
+    _NC124,
+    _NC125,
+    _NC126,
+    _NC127,
+    _NC128}),
+    .wmask0({\mem3_mask_a[3] ,
+    \mem3_mask_a[2] ,
+    \mem3_mask_a[1] ,
+    \mem3_mask_a[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(sram0_csb0),
+    .csb1(sram0_csb1),
+    .web0(sram0_web0),
+    .clk0(sram0_clk0),
+    .clk1(sram0_clk1),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\sram0_addr0[8] ,
+    \sram0_addr0[7] ,
+    \sram0_addr0[6] ,
+    \sram0_addr0[5] ,
+    \sram0_addr0[4] ,
+    \sram0_addr0[3] ,
+    \sram0_addr0[2] ,
+    \sram0_addr0[1] ,
+    \sram0_addr0[0] }),
+    .addr1({\sram0_addr1[8] ,
+    \sram0_addr1[7] ,
+    \sram0_addr1[6] ,
+    \sram0_addr1[5] ,
+    \sram0_addr1[4] ,
+    \sram0_addr1[3] ,
+    \sram0_addr1[2] ,
+    \sram0_addr1[1] ,
+    \sram0_addr1[0] }),
+    .din0({\sram0_din0[31] ,
+    \sram0_din0[30] ,
+    \sram0_din0[29] ,
+    \sram0_din0[28] ,
+    \sram0_din0[27] ,
+    \sram0_din0[26] ,
+    \sram0_din0[25] ,
+    \sram0_din0[24] ,
+    \sram0_din0[23] ,
+    \sram0_din0[22] ,
+    \sram0_din0[21] ,
+    \sram0_din0[20] ,
+    \sram0_din0[19] ,
+    \sram0_din0[18] ,
+    \sram0_din0[17] ,
+    \sram0_din0[16] ,
+    \sram0_din0[15] ,
+    \sram0_din0[14] ,
+    \sram0_din0[13] ,
+    \sram0_din0[12] ,
+    \sram0_din0[11] ,
+    \sram0_din0[10] ,
+    \sram0_din0[9] ,
+    \sram0_din0[8] ,
+    \sram0_din0[7] ,
+    \sram0_din0[6] ,
+    \sram0_din0[5] ,
+    \sram0_din0[4] ,
+    \sram0_din0[3] ,
+    \sram0_din0[2] ,
+    \sram0_din0[1] ,
+    \sram0_din0[0] }),
+    .dout0({\sram0_dout0[31] ,
+    \sram0_dout0[30] ,
+    \sram0_dout0[29] ,
+    \sram0_dout0[28] ,
+    \sram0_dout0[27] ,
+    \sram0_dout0[26] ,
+    \sram0_dout0[25] ,
+    \sram0_dout0[24] ,
+    \sram0_dout0[23] ,
+    \sram0_dout0[22] ,
+    \sram0_dout0[21] ,
+    \sram0_dout0[20] ,
+    \sram0_dout0[19] ,
+    \sram0_dout0[18] ,
+    \sram0_dout0[17] ,
+    \sram0_dout0[16] ,
+    \sram0_dout0[15] ,
+    \sram0_dout0[14] ,
+    \sram0_dout0[13] ,
+    \sram0_dout0[12] ,
+    \sram0_dout0[11] ,
+    \sram0_dout0[10] ,
+    \sram0_dout0[9] ,
+    \sram0_dout0[8] ,
+    \sram0_dout0[7] ,
+    \sram0_dout0[6] ,
+    \sram0_dout0[5] ,
+    \sram0_dout0[4] ,
+    \sram0_dout0[3] ,
+    \sram0_dout0[2] ,
+    \sram0_dout0[1] ,
+    \sram0_dout0[0] }),
+    .dout1({\sram0_dout1[31] ,
+    \sram0_dout1[30] ,
+    \sram0_dout1[29] ,
+    \sram0_dout1[28] ,
+    \sram0_dout1[27] ,
+    \sram0_dout1[26] ,
+    \sram0_dout1[25] ,
+    \sram0_dout1[24] ,
+    \sram0_dout1[23] ,
+    \sram0_dout1[22] ,
+    \sram0_dout1[21] ,
+    \sram0_dout1[20] ,
+    \sram0_dout1[19] ,
+    \sram0_dout1[18] ,
+    \sram0_dout1[17] ,
+    \sram0_dout1[16] ,
+    \sram0_dout1[15] ,
+    \sram0_dout1[14] ,
+    \sram0_dout1[13] ,
+    \sram0_dout1[12] ,
+    \sram0_dout1[11] ,
+    \sram0_dout1[10] ,
+    \sram0_dout1[9] ,
+    \sram0_dout1[8] ,
+    \sram0_dout1[7] ,
+    \sram0_dout1[6] ,
+    \sram0_dout1[5] ,
+    \sram0_dout1[4] ,
+    \sram0_dout1[3] ,
+    \sram0_dout1[2] ,
+    \sram0_dout1[1] ,
+    \sram0_dout1[0] }),
+    .wmask0({\sram0_wmask0[3] ,
+    \sram0_wmask0[2] ,
+    \sram0_wmask0[1] ,
+    \sram0_wmask0[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb (.csb0(sram1_csb0),
+    .csb1(sram1_csb1),
+    .web0(sram1_web0),
+    .clk0(sram1_clk0),
+    .clk1(sram1_clk1),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\sram1_addr0[8] ,
+    \sram1_addr0[7] ,
+    \sram1_addr0[6] ,
+    \sram1_addr0[5] ,
+    \sram1_addr0[4] ,
+    \sram1_addr0[3] ,
+    \sram1_addr0[2] ,
+    \sram1_addr0[1] ,
+    \sram1_addr0[0] }),
+    .addr1({\sram1_addr1[8] ,
+    \sram1_addr1[7] ,
+    \sram1_addr1[6] ,
+    \sram1_addr1[5] ,
+    \sram1_addr1[4] ,
+    \sram1_addr1[3] ,
+    \sram1_addr1[2] ,
+    \sram1_addr1[1] ,
+    \sram1_addr1[0] }),
+    .din0({\sram1_din0[31] ,
+    \sram1_din0[30] ,
+    \sram1_din0[29] ,
+    \sram1_din0[28] ,
+    \sram1_din0[27] ,
+    \sram1_din0[26] ,
+    \sram1_din0[25] ,
+    \sram1_din0[24] ,
+    \sram1_din0[23] ,
+    \sram1_din0[22] ,
+    \sram1_din0[21] ,
+    \sram1_din0[20] ,
+    \sram1_din0[19] ,
+    \sram1_din0[18] ,
+    \sram1_din0[17] ,
+    \sram1_din0[16] ,
+    \sram1_din0[15] ,
+    \sram1_din0[14] ,
+    \sram1_din0[13] ,
+    \sram1_din0[12] ,
+    \sram1_din0[11] ,
+    \sram1_din0[10] ,
+    \sram1_din0[9] ,
+    \sram1_din0[8] ,
+    \sram1_din0[7] ,
+    \sram1_din0[6] ,
+    \sram1_din0[5] ,
+    \sram1_din0[4] ,
+    \sram1_din0[3] ,
+    \sram1_din0[2] ,
+    \sram1_din0[1] ,
+    \sram1_din0[0] }),
+    .dout0({\sram1_dout0[31] ,
+    \sram1_dout0[30] ,
+    \sram1_dout0[29] ,
+    \sram1_dout0[28] ,
+    \sram1_dout0[27] ,
+    \sram1_dout0[26] ,
+    \sram1_dout0[25] ,
+    \sram1_dout0[24] ,
+    \sram1_dout0[23] ,
+    \sram1_dout0[22] ,
+    \sram1_dout0[21] ,
+    \sram1_dout0[20] ,
+    \sram1_dout0[19] ,
+    \sram1_dout0[18] ,
+    \sram1_dout0[17] ,
+    \sram1_dout0[16] ,
+    \sram1_dout0[15] ,
+    \sram1_dout0[14] ,
+    \sram1_dout0[13] ,
+    \sram1_dout0[12] ,
+    \sram1_dout0[11] ,
+    \sram1_dout0[10] ,
+    \sram1_dout0[9] ,
+    \sram1_dout0[8] ,
+    \sram1_dout0[7] ,
+    \sram1_dout0[6] ,
+    \sram1_dout0[5] ,
+    \sram1_dout0[4] ,
+    \sram1_dout0[3] ,
+    \sram1_dout0[2] ,
+    \sram1_dout0[1] ,
+    \sram1_dout0[0] }),
+    .dout1({\sram1_dout1[31] ,
+    \sram1_dout1[30] ,
+    \sram1_dout1[29] ,
+    \sram1_dout1[28] ,
+    \sram1_dout1[27] ,
+    \sram1_dout1[26] ,
+    \sram1_dout1[25] ,
+    \sram1_dout1[24] ,
+    \sram1_dout1[23] ,
+    \sram1_dout1[22] ,
+    \sram1_dout1[21] ,
+    \sram1_dout1[20] ,
+    \sram1_dout1[19] ,
+    \sram1_dout1[18] ,
+    \sram1_dout1[17] ,
+    \sram1_dout1[16] ,
+    \sram1_dout1[15] ,
+    \sram1_dout1[14] ,
+    \sram1_dout1[13] ,
+    \sram1_dout1[12] ,
+    \sram1_dout1[11] ,
+    \sram1_dout1[10] ,
+    \sram1_dout1[9] ,
+    \sram1_dout1[8] ,
+    \sram1_dout1[7] ,
+    \sram1_dout1[6] ,
+    \sram1_dout1[5] ,
+    \sram1_dout1[4] ,
+    \sram1_dout1[3] ,
+    \sram1_dout1[2] ,
+    \sram1_dout1[1] ,
+    \sram1_dout1[0] }),
+    .wmask0({\sram1_wmask0[3] ,
+    \sram1_wmask0[2] ,
+    \sram1_wmask0[1] ,
+    \sram1_wmask0[0] }));
+ uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew),
+    .i2c_rstn(i2c_rst_n),
+    .i2cm_intr_o(i2cm_intr_o),
+    .reg_ack(wbd_uart_ack_i),
+    .reg_cs(wbd_uart_stb_o),
+    .reg_wr(wbd_uart_we_o),
+    .scl_pad_i(i2cm_clk_i),
+    .scl_pad_o(i2cm_clk_o),
+    .scl_pad_oen_o(i2cm_clk_oen),
+    .sda_pad_i(i2cm_data_i),
+    .sda_pad_o(i2cm_data_o),
+    .sda_padoen_o(i2cm_data_oen),
+    .spi_rstn(sspim_rst_n),
+    .sspim_sck(sspim_sck),
+    .sspim_si(sspim_si),
+    .sspim_so(sspim_so),
+    .sspim_ssn(sspim_ssn),
+    .uart_rstn(uart_rst_n),
+    .uart_rxd(uart_rxd),
+    .uart_txd(uart_txd),
+    .usb_clk(usb_clk),
+    .usb_in_dn(usb_dn_i),
+    .usb_in_dp(usb_dp_i),
+    .usb_intr_o(usb_intr_o),
+    .usb_out_dn(usb_dn_o),
+    .usb_out_dp(usb_dp_o),
+    .usb_out_tx_oen(usb_oen),
+    .usb_rstn(usb_rst_n),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_uart_rp),
+    .wbd_clk_uart(wbd_clk_uart_skew),
+    .cfg_cska_uart({\cfg_cska_uart_rp[3] ,
+    \cfg_cska_uart_rp[2] ,
+    \cfg_cska_uart_rp[1] ,
+    \cfg_cska_uart_rp[0] }),
+    .reg_addr({\wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .reg_be({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .reg_rdata({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .reg_wdata({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }));
+ wb_host u_wb_host (.bist_rst_n(bist_rst_n),
+    .cpu_clk(cpu_clk),
+    .cpu_rst_n(cpu_rst_n),
+    .i2cm_rst_n(i2c_rst_n),
+    .qspim_rst_n(qspim_rst_n),
+    .rtc_clk(rtc_clk),
+    .sspim_rst_n(sspim_rst_n),
+    .uart_rst_n(uart_rst_n),
+    .usb_clk(usb_clk),
+    .usb_rst_n(usb_rst_n),
+    .user_clock1(wb_clk_i),
+    .user_clock2(user_clock2),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wh(wbd_clk_wh),
+    .wbd_int_rst_n(wbd_int_rst_n),
+    .wbm_ack_o(wbs_ack_o),
+    .wbm_clk_i(wb_clk_i),
+    .wbm_cyc_i(wbs_cyc_i),
+    .wbm_rst_i(wb_rst_i),
+    .wbm_stb_i(wbs_stb_i),
+    .wbm_we_i(wbs_we_i),
+    .wbs_ack_i(wbd_int_ack_o),
+    .wbs_clk_i(wbd_clk_wh),
+    .wbs_clk_out(wbd_clk_int),
+    .wbs_cyc_o(wbd_int_cyc_i),
+    .wbs_err_i(wbd_int_err_o),
+    .wbs_stb_o(wbd_int_stb_i),
+    .wbs_we_o(wbd_int_we_i),
+    .cfg_clk_ctrl1({\cfg_clk_ctrl1[31] ,
+    \cfg_clk_ctrl1[30] ,
+    \cfg_clk_ctrl1[29] ,
+    \cfg_clk_ctrl1[28] ,
+    \cfg_clk_ctrl1[27] ,
+    \cfg_clk_ctrl1[26] ,
+    \cfg_clk_ctrl1[25] ,
+    \cfg_clk_ctrl1[24] ,
+    \cfg_clk_ctrl1[23] ,
+    \cfg_clk_ctrl1[22] ,
+    \cfg_clk_ctrl1[21] ,
+    \cfg_clk_ctrl1[20] ,
+    \cfg_clk_ctrl1[19] ,
+    \cfg_clk_ctrl1[18] ,
+    \cfg_clk_ctrl1[17] ,
+    \cfg_clk_ctrl1[16] ,
+    \cfg_clk_ctrl1[15] ,
+    \cfg_clk_ctrl1[14] ,
+    \cfg_clk_ctrl1[13] ,
+    \cfg_clk_ctrl1[12] ,
+    \cfg_clk_ctrl1[11] ,
+    \cfg_clk_ctrl1[10] ,
+    \cfg_clk_ctrl1[9] ,
+    \cfg_clk_ctrl1[8] ,
+    \cfg_clk_ctrl1[7] ,
+    \cfg_clk_ctrl1[6] ,
+    \cfg_clk_ctrl1[5] ,
+    \cfg_clk_ctrl1[4] ,
+    \cfg_clk_ctrl1[3] ,
+    \cfg_clk_ctrl1[2] ,
+    \cfg_clk_ctrl1[1] ,
+    \cfg_clk_ctrl1[0] }),
+    .cfg_clk_ctrl2({\boot_remap[3] ,
+    \boot_remap[2] ,
+    \boot_remap[1] ,
+    \boot_remap[0] ,
+    \cfg_clk_ctrl2[27] ,
+    \cfg_clk_ctrl2[26] ,
+    \cfg_clk_ctrl2[25] ,
+    \cfg_clk_ctrl2[24] ,
+    \cfg_clk_ctrl2[23] ,
+    \cfg_clk_ctrl2[22] ,
+    \cfg_clk_ctrl2[21] ,
+    \cfg_clk_ctrl2[20] ,
+    \cfg_clk_ctrl2[19] ,
+    \cfg_clk_ctrl2[18] ,
+    \cfg_clk_ctrl2[17] ,
+    \cfg_clk_ctrl2[16] ,
+    \cfg_clk_ctrl2[15] ,
+    \cfg_clk_ctrl2[14] ,
+    \cfg_clk_ctrl2[13] ,
+    \cfg_clk_ctrl2[12] ,
+    \cfg_clk_ctrl2[11] ,
+    \cfg_clk_ctrl2[10] ,
+    \cfg_clk_ctrl2[9] ,
+    \cfg_clk_ctrl2[8] ,
+    \cfg_clk_ctrl2[7] ,
+    \cfg_clk_ctrl2[6] ,
+    \cfg_clk_ctrl2[5] ,
+    \cfg_clk_ctrl2[4] ,
+    \cfg_clk_ctrl2[3] ,
+    \cfg_clk_ctrl2[2] ,
+    \cfg_clk_ctrl2[1] ,
+    \cfg_clk_ctrl2[0] }),
+    .cfg_cska_wh({\cfg_clk_ctrl1[7] ,
+    \cfg_clk_ctrl1[6] ,
+    \cfg_clk_ctrl1[5] ,
+    \cfg_clk_ctrl1[4] }),
+    .wbm_adr_i({wbs_adr_i[31],
+    wbs_adr_i[30],
+    wbs_adr_i[29],
+    wbs_adr_i[28],
+    wbs_adr_i[27],
+    wbs_adr_i[26],
+    wbs_adr_i[25],
+    wbs_adr_i[24],
+    wbs_adr_i[23],
+    wbs_adr_i[22],
+    wbs_adr_i[21],
+    wbs_adr_i[20],
+    wbs_adr_i[19],
+    wbs_adr_i[18],
+    wbs_adr_i[17],
+    wbs_adr_i[16],
+    wbs_adr_i[15],
+    wbs_adr_i[14],
+    wbs_adr_i[13],
+    wbs_adr_i[12],
+    wbs_adr_i[11],
+    wbs_adr_i[10],
+    wbs_adr_i[9],
+    wbs_adr_i[8],
+    wbs_adr_i[7],
+    wbs_adr_i[6],
+    wbs_adr_i[5],
+    wbs_adr_i[4],
+    wbs_adr_i[3],
+    wbs_adr_i[2],
+    wbs_adr_i[1],
+    wbs_adr_i[0]}),
+    .wbm_dat_i({wbs_dat_i[31],
+    wbs_dat_i[30],
+    wbs_dat_i[29],
+    wbs_dat_i[28],
+    wbs_dat_i[27],
+    wbs_dat_i[26],
+    wbs_dat_i[25],
+    wbs_dat_i[24],
+    wbs_dat_i[23],
+    wbs_dat_i[22],
+    wbs_dat_i[21],
+    wbs_dat_i[20],
+    wbs_dat_i[19],
+    wbs_dat_i[18],
+    wbs_dat_i[17],
+    wbs_dat_i[16],
+    wbs_dat_i[15],
+    wbs_dat_i[14],
+    wbs_dat_i[13],
+    wbs_dat_i[12],
+    wbs_dat_i[11],
+    wbs_dat_i[10],
+    wbs_dat_i[9],
+    wbs_dat_i[8],
+    wbs_dat_i[7],
+    wbs_dat_i[6],
+    wbs_dat_i[5],
+    wbs_dat_i[4],
+    wbs_dat_i[3],
+    wbs_dat_i[2],
+    wbs_dat_i[1],
+    wbs_dat_i[0]}),
+    .wbm_dat_o({wbs_dat_o[31],
+    wbs_dat_o[30],
+    wbs_dat_o[29],
+    wbs_dat_o[28],
+    wbs_dat_o[27],
+    wbs_dat_o[26],
+    wbs_dat_o[25],
+    wbs_dat_o[24],
+    wbs_dat_o[23],
+    wbs_dat_o[22],
+    wbs_dat_o[21],
+    wbs_dat_o[20],
+    wbs_dat_o[19],
+    wbs_dat_o[18],
+    wbs_dat_o[17],
+    wbs_dat_o[16],
+    wbs_dat_o[15],
+    wbs_dat_o[14],
+    wbs_dat_o[13],
+    wbs_dat_o[12],
+    wbs_dat_o[11],
+    wbs_dat_o[10],
+    wbs_dat_o[9],
+    wbs_dat_o[8],
+    wbs_dat_o[7],
+    wbs_dat_o[6],
+    wbs_dat_o[5],
+    wbs_dat_o[4],
+    wbs_dat_o[3],
+    wbs_dat_o[2],
+    wbs_dat_o[1],
+    wbs_dat_o[0]}),
+    .wbm_sel_i({wbs_sel_i[3],
+    wbs_sel_i[2],
+    wbs_sel_i[1],
+    wbs_sel_i[0]}),
+    .wbs_adr_o({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .wbs_dat_i({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .wbs_dat_o({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .wbs_sel_o({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }));
+endmodule
diff --git a/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.magic.drc.mag b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..2725f64
--- /dev/null
+++ b/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,96536 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1640161422
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< locali >>
+rect 320833 665227 320867 665329
+rect 77953 577031 77987 577473
+rect 255513 577167 255547 577405
+rect 219449 576963 219483 577065
+rect 255697 576895 255731 577133
+rect 79333 543031 79367 543541
+rect 80345 542759 80379 543065
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