jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/precheck.log

2021-12-22 08:04:49 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino.git | Branch: master | Commit: cb2d94c54d1906072380d2d58384c95d538c3a7a
2021-12-22 08:04:49 - [INFO] - {{INSTALLING CARAVEL}} Running `Make Install` in riscduino
2021-12-22 08:04:49 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: riscduino
2021-12-22 08:04:55 - [INFO] - {{Project GDS Info}} user_project_wrapper: b1a54329abec9ddabd4ced34b12620986a98ae1a
2021-12-22 08:04:55 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.241
2021-12-22 08:04:55 - [INFO] - {{PDKs Info}} Open PDKs: 13207762cf4eb2e2943be51bf1605f2bb2bac41d | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-12-22 08:04:55 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs'
2021-12-22 08:04:55 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-12-22 08:04:55 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2021-12-22 08:04:56 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino.
2021-12-22 08:04:56 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-12-22 08:04:57 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino.
2021-12-22 08:04:57 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v): 'utf-8' codec can't decode byte 0x91 in position 5970: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv): 'utf-8' codec can't decode byte 0xa9 in position 4875: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh): 'utf-8' codec can't decode byte 0xa9 in position 4377: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:57 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
2021-12-22 08:04:58 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 294 non-compliant file(s) with the SPDX Standard.
2021-12-22 08:04:58 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino/run_regress', 'riscduino/Makefile', 'riscduino/sta/base.sdc', 'riscduino/sta/Makefile', 'riscduino/sta/run_sta', 'riscduino/sta/scripts/or_write_verilog.tcl', 'riscduino/sta/scripts/sta.tcl', 'riscduino/sta/scripts/caravel_timing.tcl', 'riscduino/sta/sdc/caravel.sdc', 'riscduino/verilog/dv/Makefile', 'riscduino/verilog/dv/risc_boot/risc_boot.c', 'riscduino/verilog/dv/risc_boot/risc_boot_tb.v', 'riscduino/verilog/dv/risc_boot/Makefile', 'riscduino/verilog/dv/risc_boot/user_uart.c', 'riscduino/verilog/dv/risc_boot/run_iverilog']
2021-12-22 08:04:58 - [INFO] - For the full SPDX compliance report check: riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs/spdx_compliance_report.log
2021-12-22 08:04:58 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2021-12-22 08:04:58 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-12-22 08:04:58 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2021-12-22 08:04:58 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-12-22 08:05:01 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-12-22 08:05:01 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2021-12-22 08:05:01 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-12-22 08:05:01 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2021-12-22 08:05:01 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/__user_project_wrapper.v
2021-12-22 08:05:02 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/__user_project_wrapper.v
2021-12-22 08:05:02 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/defines.v
2021-12-22 08:05:02 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/verilog/rtl/defines.v
2021-12-22 08:05:08 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2021-12-22 08:05:08 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
2021-12-22 08:05:08 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2021-12-22 08:05:08 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2021-12-22 08:05:08 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2021-12-22 08:05:08 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2021-12-22 08:05:08 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2021-12-22 08:05:08 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (13 instances). 
2021-12-22 08:05:08 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2021-12-22 08:05:08 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2021-12-22 08:05:08 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2021-12-22 08:05:08 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2021-12-22 08:05:08 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2021-12-22 08:05:09 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-12-22 08:05:09 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2021-12-22 08:05:09 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/gds/user_project_wrapper_empty.gds.gz
2021-12-22 08:05:09 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/dd71e938ce85d7e877b8213d5405457f2ea15ae9/gds/user_project_wrapper_empty.gds.gz
2021-12-22 08:07:30 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/outputs/user_project_wrapper.xor.gds
2021-12-22 08:07:30 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-12-22 08:07:30 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2021-12-22 08:23:42 - [INFO] - 0 DRC violations
2021-12-22 08:23:42 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:23:42 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2021-12-22 08:25:09 - [INFO] - No DRC Violations found
2021-12-22 08:25:09 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:25:09 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2021-12-22 08:41:45 - [INFO] - No DRC Violations found
2021-12-22 08:41:45 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:41:45 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2021-12-22 08:44:41 - [INFO] - No DRC Violations found
2021-12-22 08:44:41 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:44:41 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2021-12-22 08:45:57 - [INFO] - No DRC Violations found
2021-12-22 08:45:57 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:45:57 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2021-12-22 08:46:29 - [INFO] - No DRC Violations found
2021-12-22 08:46:29 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:46:29 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2021-12-22 08:46:41 - [INFO] - No DRC Violations found
2021-12-22 08:46:41 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-22 08:46:41 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino/jobs/mpw_precheck/3c5aca82-8365-464d-9f8d-f7ce189a6095/logs'
2021-12-22 08:46:41 - [INFO] - {{SUCCESS}} All Checks Passed !!!