| /* |
| |
| Copyright (c) 2014-2018 Alex Forencich |
| |
| Permission is hereby granted, free of charge, to any person obtaining a copy |
| of this software and associated documentation files (the "Software"), to deal |
| in the Software without restriction, including without limitation the rights |
| to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| copies of the Software, and to permit persons to whom the Software is |
| furnished to do so, subject to the following conditions: |
| |
| The above copyright notice and this permission notice shall be included in |
| all copies or substantial portions of the Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY |
| FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| THE SOFTWARE. |
| |
| */ |
| |
| // Language: Verilog 2001 |
| |
| `timescale 1ns / 1ps |
| |
| /* |
| * FPGA core logic |
| */ |
| module ethernet_100m |
| ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| /* |
| * Clock: 125MHz |
| * Synchronous reset |
| */ |
| input wire clk, |
| input wire rst, |
| |
| /* |
| * Ethernet: 100BASE-T MII |
| */ |
| input wire phy_rx_clk, |
| input wire [3:0] phy_rxd, |
| input wire phy_rx_dv, |
| input wire phy_rx_er, |
| input wire phy_tx_clk, |
| output wire [3:0] phy_txd, |
| output wire phy_tx_en |
| ); |
| |
| wire [7:0] rx_udp_payload_axis_tdata; |
| wire rx_udp_payload_axis_tvalid; |
| wire rx_udp_payload_axis_tready; |
| wire rx_udp_payload_axis_tlast; |
| |
| wire [7:0] tx_udp_payload_axis_tdata; |
| wire tx_udp_payload_axis_tvalid; |
| wire tx_udp_payload_axis_tready; |
| wire tx_udp_payload_axis_tlast; |
| |
| ethernet_core #( |
| .TARGET("GENERIC"), |
| .LOCAL_MAC(48'h02_00_00_00_00_00), |
| .LOCAL_IP({8'd192, 8'd168, 8'd1, 8'd128}), |
| .GATEWAY_IP({8'd192, 8'd168, 8'd1, 8'd1}), |
| .SUBNET_MASK({8'd255, 8'd255, 8'd255, 8'd0}) |
| ) |
| core ( |
| .clk(clk), |
| .rst(rst), |
| .phy_rx_clk(phy_rx_clk), |
| .phy_rxd(phy_rxd), |
| .phy_rx_dv(phy_rx_dv), |
| .phy_rx_er(phy_rx_er), |
| .phy_tx_clk(phy_tx_clk), |
| .phy_txd(phy_txd), |
| .phy_tx_en(phy_tx_en), |
| .phy_reset_n(), |
| .rx_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), |
| .rx_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), |
| .rx_udp_payload_axis_tready(rx_udp_payload_axis_tready), |
| .rx_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), |
| .rx_udp_payload_axis_tuser(), |
| .tx_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), |
| .tx_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), |
| .tx_udp_payload_axis_tready(tx_udp_payload_axis_tready), |
| .tx_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), |
| .tx_udp_payload_axis_tuser(0) |
| ); |
| |
| axis_fifo #( |
| .DEPTH(512), |
| .DATA_WIDTH(8), |
| .KEEP_ENABLE(0), |
| .ID_ENABLE(0), |
| .DEST_ENABLE(0), |
| .USER_ENABLE(1), |
| .USER_WIDTH(1), |
| .FRAME_FIFO(0) |
| ) |
| udp_payload_fifo ( |
| .clk(clk), |
| .rst(rst), |
| .s_axis_tdata(rx_udp_payload_axis_tdata), |
| .s_axis_tkeep(0), |
| .s_axis_tvalid(rx_udp_payload_axis_tvalid), |
| .s_axis_tready(rx_udp_payload_axis_tready), |
| .s_axis_tlast(rx_udp_payload_axis_tlast), |
| .s_axis_tid(0), |
| .s_axis_tdest(0), |
| .s_axis_tuser(0), |
| .m_axis_tdata(tx_udp_payload_axis_tdata), |
| .m_axis_tkeep(), |
| .m_axis_tvalid(tx_udp_payload_axis_tvalid), |
| .m_axis_tready(tx_udp_payload_axis_tready), |
| .m_axis_tlast(tx_udp_payload_axis_tlast), |
| .m_axis_tid(), |
| .m_axis_tdest(), |
| .m_axis_tuser(), |
| .status_overflow(), |
| .status_bad_frame(), |
| .status_good_frame() |
| ); |
| endmodule |