final gds oasis
90 files changed
tree: 5fa75b210234df19561d1b3149a997dfc41029fa
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. jobs/
  6. lef/
  7. mag/
  8. maglef/
  9. oas/
  10. openlane/
  11. signoff/
  12. spi/
  13. verilog/
  14. .gitignore
  15. .gitmodules
  16. info.yaml
  18. Makefile

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note


YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.


export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
export CARAVEL_ROOT=$(pwd)/caravel
make install

Running Simulation


  • This test is meant to verify that we can send and receive data from YONGA-100M Ethernet through GPIO pins. The firmware sends a UDP frame to YONGA-100M Ethernet, then receives a response from YONGA-100M Ethernet.

To run RTL simulation,

make verify-ethernet_100m

Hardening the User Project Macro using OpenLANE

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order <>__
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <>__
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck <>

List of Contributors

In alphabetical order:

  • Abdullah Yildiz
  • Burak Yakup Cakar