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foss-eda-tools / third_party / shuttle / sky130 / mpw-003 / slot-008 / refs/heads/main
commit1f769e4c62c0535faac80fe203ac5076be388a51[log] [tgz]
authorJeff DiCorpo <jeffdi@efabless.com>Wed Dec 29 01:56:51 2021 -0800
committerJeff DiCorpo <jeffdi@efabless.com>Wed Dec 29 01:56:51 2021 -0800
tree5fa75b210234df19561d1b3149a997dfc41029fa
parentb9a4a249b433e7732dbe24fc0a9ae12d9e25a0ff [diff]
final gds oasis
90 files changed
tree: 5fa75b210234df19561d1b3149a997dfc41029fa
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. jobs/
  6. lef/
  7. mag/
  8. maglef/
  9. oas/
  10. openlane/
  11. signoff/
  12. spi/
  13. verilog/
  14. caravel
  15. .gitignore
  16. .gitmodules
  17. info.yaml
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Overview

YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.

Setup

export PDK_ROOT=<pdk-installation-path>
export OPENLANE_ROOT=<openlane-installation-path>
cd $UPRJ_ROOT
export CARAVEL_ROOT=$(pwd)/caravel
make install

Running Simulation

GPIO Test

  • This test is meant to verify that we can send and receive data from YONGA-100M Ethernet through GPIO pins. The firmware sends a UDP frame to YONGA-100M Ethernet, then receives a response from YONGA-100M Ethernet.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-ethernet_100m

Hardening the User Project Macro using OpenLANE

# Run openlane to harden user_proj_example
make user_proj_example
# Run openlane to harden user_project_wrapper
make user_project_wrapper

Checklist for Open-MPW Submission

  • ✔️ The project repo adheres to the same directory structure in this repo.
  • ✔️ The project repo contain info.yaml at the project root.
  • ✔️ Top level macro is named user_project_wrapper.
  • ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
  • ✔️ The hardened Macros are LVS and DRC clean
  • ✔️ The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
  • ✔️ The hardened user_project_wrapper adheres to the same pin order specified at pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>__
  • ✔️ The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>__
  • ✔️ XOR check passes with zero total difference.
  • ✔️ Openlane summary reports are retained under ./signoff/
  • ✔️ The design passes the mpw-precheck <https://github.com/efabless/mpw_precheck>

List of Contributors

In alphabetical order:

  • Abdullah Yildiz
  • Burak Yakup Cakar