missing files
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 43444d0..542f66b 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h3m59s,0h1m34s,0.19458281444582815,10.2784,0.09729140722291407,-1,504.96,1,0,0,0,0,0,0,0,0,0,-1,-1,1381577,2003,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,40141.04,1.23,4.2,0.57,0.6,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h3m2s,0h1m15s,3.1133250311332503,10.2784,1.5566625155666252,-1,599.84,16,0,0,0,0,0,0,0,0,0,-1,-1,2694902,14465,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,10005.48,33.33,15.62,16.75,3.79,-1,37,965,37,965,0,0,0,16,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.7,sky130_fd_sc_hd,4,0
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 342dfe5..35c21b2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -35,10 +35,16 @@
module user_project_wrapper #(
parameter BITS = 32
)(
- `ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
- `endif
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
@@ -75,6 +81,7 @@
output [2:0] user_irq
);
+
// generate active wires
wire [31: 0] active;
assign active = la_data_in[31:0];
@@ -110,7 +117,7 @@
.io_oeb (io_oeb[37:0])
);
- wrapped_rgb_mixer wrapped_rgb_mixer_1(
+ wrapped_frequency_counter wrapped_frequency_counter_1(
`ifdef USE_POWER_PINS
.vccd1 (vccd1),
.vssd1 (vssd1),
@@ -125,6 +132,216 @@
.io_oeb (io_oeb[37:0])
);
+ wrapped_vga_clock wrapped_vga_clock_2(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[2]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_rgb_mixer wrapped_rgb_mixer_3(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[3]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_frequency_counter wrapped_frequency_counter_4(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[4]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_vga_clock wrapped_vga_clock_5(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[5]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_rgb_mixer wrapped_rgb_mixer_6(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[6]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_frequency_counter wrapped_frequency_counter_7(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[7]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_vga_clock wrapped_vga_clock_8(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[8]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_rgb_mixer wrapped_rgb_mixer_9(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[9]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_frequency_counter wrapped_frequency_counter_10(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[10]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_vga_clock wrapped_vga_clock_11(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[11]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_rgb_mixer wrapped_rgb_mixer_12(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[12]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_frequency_counter wrapped_frequency_counter_13(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[13]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_vga_clock wrapped_vga_clock_14(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[14]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
+ wrapped_rgb_mixer wrapped_rgb_mixer_15(
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+ `endif
+ .wb_clk_i (wb_clk_i),
+ .active (active[15]),
+ .la1_data_in (la1_data_in[31:0]),
+ .la1_data_out (la1_data_out[31:0]),
+ .la1_oenb (la1_oenb[31:0]),
+ .io_in (io_in[37:0]),
+ .io_out (io_out[37:0]),
+ .io_oeb (io_oeb[37:0])
+ );
+
// end of module instantiation
endmodule // user_project_wrapper
