Update index.rst
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 2dce7c4..6b8efef 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -34,6 +34,7 @@
- `Verilog Integration <#verilog-integration>`__
- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
- `Checklist for Open-MPW
Submission <#checklist-for-open-mpw-submission>`__
@@ -160,6 +161,13 @@
The verilog test-benches are under this directory
`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+Analog Design Flow
+===================
+
+> :construction: Under construction :construction:
+
+
Running Open-MPW Precheck Locally
=================================
