Google Git Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-037/HEAD
  1. 092781b Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 3 years, 10 months ago main
  2. 2bf65fc final gds & signoff results by Jeff DiCorpo · 4 years, 10 months ago
  3. 97b9d15 final gds oasis by Jeff DiCorpo · 4 years, 10 months ago
  4. 2a83f43 final gds & signoff results by Jeff DiCorpo · 4 years, 10 months ago
  5. f88d6b6 final gds oasis by Jeff DiCorpo · 4 years, 10 months ago
  6. aebfd3c final gds & signoff results by Jeff DiCorpo · 5 years ago
  7. 660680b final gds oasis by Jeff DiCorpo · 5 years ago
  8. 7af2ec9 final gds & signoff results by Jeff DiCorpo · 5 years ago
  9. 411eb1d final gds oasis by Jeff DiCorpo · 5 years ago
  10. 5680cc4 final gds & signoff results by Jeff DiCorpo · 5 years ago
  11. 86642a9 final gds oasis by Jeff DiCorpo · 5 years ago
  12. 38c00f1 final gds & signoff results by Jeff DiCorpo · 5 years ago
  13. 7664128 final gds oasis by Jeff DiCorpo · 5 years ago
  14. 3dd5532 tapeout.log by Jeff DiCorpo · 5 years ago
  15. 0354c14 final gds oasis by Jeff DiCorpo · 5 years ago
  16. 48500a6 final gds & signoff results by Jeff DiCorpo · 5 years ago
  17. d657cf5 final gds oasis by Jeff DiCorpo · 5 years ago
  18. bc66ceb more DRC updates by Barry Muldrey · 5 years ago
  19. 9e82528 DRC work by Barry Muldrey · 5 years ago
  20. 9ec92fe refreshed after Magic update (v8.3.196) by Barry Muldrey · 5 years ago
  21. dcc9b34 refresh from commit b44a04804145badb05bbec9b7e9f9a8d55f4cfba by Barry Muldrey · 5 years ago
  22. 5a031a0 update to current cell PDK by Barry Muldrey · 5 years ago
  23. a713521 updated by Barry Muldrey · 5 years ago
  24. 5f0ed72 Refreshed GDS, Magic, and Verilog files by pwhardy · 5 years ago
  25. 5a1fcb0 Added all files, ran precheck, added caravel submodule for precheck. All GDS files got compressed during precheck by pwhardy · 5 years ago
  26. 33067d6 Added newly refreshed files by pwhardy · 5 years ago
  27. 209f087 copying entire /mag/ /gds/ and /verilog/ from PDK by pwhardy · 5 years ago
  28. 6e5bebf no more submodules by pwhardy · 5 years ago
  29. 33c9465 remove example by pwhardy · 5 years ago
  30. c3ce084 submodule and symlink by pwhardy · 5 years ago
  31. 1c7e64b delete example by pwhardy · 5 years ago
  32. ee93a49 mirroring upstream (efabless) by pwhardy · 5 years ago
  33. 8b004e7 remove spice by pwhardy · 5 years ago
  34. 0ea36b6 restore caravel by pwhardy · 5 years ago
  35. 4f519bb Update info.yaml file by pwhardy · 5 years ago
  36. 435eb3e Cleaning mpw2 repo for upload: by pwhardy · 5 years ago
  37. b16d7fa Added GDS and all supporting files. Updated info.yaml, added copyright to files, and copied license. .gitignore added to ignore PDK libraries for precheck. by pwhardy · 5 years ago
  38. 84eba62 Added GDS of final design, updated info.yaml, added copyright and license. Updated magic files, passes pre-check aside from default config checks by pwhardy · 5 years ago
  39. 23e46c6 Updated magic and schematic files by pwhardy · 5 years ago
  40. afb8cb4 Added new LICENSE, updated info.yaml by pwhardy · 5 years ago
  41. 0f92e43 Corrected signal names in user_analog_project_wrapper by pwhardy · 5 years ago
  42. e35fe2e Added all files for TopLevelTestStructure and supporting cells, added verilog module and added an instance into user_analog_project_wrapper by pwhardy · 5 years ago
  43. 0b0d2d3 Replaced TopLevelTestStructure with TopLevleProtectStructure files by pwhardy · 5 years ago
  44. 85e4631 Added the magic, gds, and verilog modules for the test structure. Still need to put the verilog instance into the wrapper and assign pin connections by pwhardy · 5 years ago
  45. 517439c fix check_default missing ENV variables by Jeff DiCorpo · 5 years ago
  46. 67640ef Auto updated submodule references by Git bot · 5 years ago
  47. c68f39e Updated the documentation to include a description of the power-on-reset by Tim Edwards · 5 years ago
  48. 13f142e Update index.rst by Manar · 5 years ago
  49. 520ff4a Update index.rst by Manar · 5 years ago
  50. a119592 Update index.rst by Manar · 5 years ago
  51. dd3d811 Doc updates by manarabdelaty · 5 years ago
  52. 55c9fff Merge branch 'main' of https://github.com/efabless/caravel_analog_user into main by manarabdelaty · 5 years ago
  53. 9e46db5 Auto updated submodule references by Git bot · 5 years ago
  54. f9e592b Update submodule reference to caravel-lite by manarabdelaty · 5 years ago
  55. 3f75a89 Update Makefile by manarabdelaty · 5 years ago
  56. 206bfb5 Update run-xor.sh by manarabdelaty · 5 years ago
  57. b7fad20 [CI] update run-xor by manarabdelaty · 5 years ago
  58. 9b861b2 Add pattern to dv Makefile and drop obselete openlane wrapper dir by manarabdelaty · 5 years ago
  59. b07e408 Update README.md by Manar · 5 years ago
  60. 7b7b2f6 Update index.rst by Manar · 5 years ago
  61. 722391b Merge branch 'main' of github.com:efabless/caravel_user_project_analog into main by Tim Edwards · 5 years ago
  62. e982ef8 Update README.md by Manar · 5 years ago
  63. 9422266 Modified the wrapper to extend the analog pins out 4um like the rest of by Tim Edwards · 5 years ago
  64. 1f15094 [CI] Add github workflows for running the precheck/dv/caravan_build by manarabdelaty · 5 years ago
  65. a1553af Add docs dir by manarabdelaty · 5 years ago
  66. 892f0d2 Update Makefile by manarabdelaty · 5 years ago
  67. ff42add Update info.yaml to have the user_level_netlist point to the rtl netlist by manarabdelaty · 5 years ago
  68. 35111e9 Corrected ngspice testbenches for change in the name of the parameter by Tim Edwards · 6 years ago
  69. dba051e Modifications to the wrapper testbench schematic (not quite working by Tim Edwards · 6 years ago
  70. 5cc020d Added xschem schematic and symbol for the analog project wrapper, and a by Tim Edwards · 6 years ago
  71. a26abdd Redid the layout for the example analog project based on the updated by Tim Edwards · 6 years ago
  72. 60e4dcb Update Makefile by manarabdelaty · 6 years ago
  73. 8a1d5f2 Corrected the info.yaml file to point to the caravan.v file as the by Tim Edwards · 6 years ago
  74. 6bb2165 Added layout for the user_analog_project_wrapper example. by Tim Edwards · 6 years ago
  75. 5ea70cb Changed the schematics so that the resistor does not set a W by Tim Edwards · 6 years ago
  76. 796099e Corrected the schematic for the proper orientation of the topmost by Tim Edwards · 6 years ago
  77. dfc24ad Added xschem schematic of the POR and testbench simulations and results. by Tim Edwards · 6 years ago
  78. fb13001 Simple layout, unwired (needs modifications to the project wrapper) by Tim Edwards · 6 years ago
  79. a44a60b Preliminary work on the analog user project example. Added verilog RTL and by Tim Edwards · 6 years ago
  80. 6af7408 Initial commit by manarabdelaty · 6 years ago