- 092781b Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 1 year, 11 months ago main
- 2bf65fc final gds & signoff results by Jeff DiCorpo · 2 years, 11 months ago
- 97b9d15 final gds oasis by Jeff DiCorpo · 2 years, 11 months ago
- 2a83f43 final gds & signoff results by Jeff DiCorpo · 2 years, 11 months ago
- f88d6b6 final gds oasis by Jeff DiCorpo · 2 years, 11 months ago
- aebfd3c final gds & signoff results by Jeff DiCorpo · 3 years ago
- 660680b final gds oasis by Jeff DiCorpo · 3 years ago
- 7af2ec9 final gds & signoff results by Jeff DiCorpo · 3 years ago
- 411eb1d final gds oasis by Jeff DiCorpo · 3 years ago
- 5680cc4 final gds & signoff results by Jeff DiCorpo · 3 years ago
- 86642a9 final gds oasis by Jeff DiCorpo · 3 years ago
- 38c00f1 final gds & signoff results by Jeff DiCorpo · 3 years ago
- 7664128 final gds oasis by Jeff DiCorpo · 3 years ago
- 3dd5532 tapeout.log by Jeff DiCorpo · 3 years ago
- 0354c14 final gds oasis by Jeff DiCorpo · 3 years ago
- 48500a6 final gds & signoff results by Jeff DiCorpo · 3 years, 3 months ago
- d657cf5 final gds oasis by Jeff DiCorpo · 3 years, 3 months ago
- bc66ceb more DRC updates by Barry Muldrey · 3 years, 3 months ago
- 9e82528 DRC work by Barry Muldrey · 3 years, 3 months ago
- 9ec92fe refreshed after Magic update (v8.3.196) by Barry Muldrey · 3 years, 3 months ago
- dcc9b34 refresh from commit b44a04804145badb05bbec9b7e9f9a8d55f4cfba by Barry Muldrey · 3 years, 3 months ago
- 5a031a0 update to current cell PDK by Barry Muldrey · 3 years, 4 months ago
- a713521 updated by Barry Muldrey · 3 years, 4 months ago
- 5f0ed72 Refreshed GDS, Magic, and Verilog files by pwhardy · 3 years, 4 months ago
- 5a1fcb0 Added all files, ran precheck, added caravel submodule for precheck. All GDS files got compressed during precheck by pwhardy · 3 years, 4 months ago
- 33067d6 Added newly refreshed files by pwhardy · 3 years, 4 months ago
- 209f087 copying entire /mag/ /gds/ and /verilog/ from PDK by pwhardy · 3 years, 4 months ago
- 6e5bebf no more submodules by pwhardy · 3 years, 4 months ago
- 33c9465 remove example by pwhardy · 3 years, 4 months ago
- c3ce084 submodule and symlink by pwhardy · 3 years, 4 months ago
- 1c7e64b delete example by pwhardy · 3 years, 4 months ago
- ee93a49 mirroring upstream (efabless) by pwhardy · 3 years, 4 months ago
- 8b004e7 remove spice by pwhardy · 3 years, 4 months ago
- 0ea36b6 restore caravel by pwhardy · 3 years, 4 months ago
- 4f519bb Update info.yaml file by pwhardy · 3 years, 4 months ago
- 435eb3e Cleaning mpw2 repo for upload: by pwhardy · 3 years, 4 months ago
- b16d7fa Added GDS and all supporting files. Updated info.yaml, added copyright to files, and copied license. .gitignore added to ignore PDK libraries for precheck. by pwhardy · 3 years, 4 months ago
- 84eba62 Added GDS of final design, updated info.yaml, added copyright and license. Updated magic files, passes pre-check aside from default config checks by pwhardy · 3 years, 4 months ago
- 23e46c6 Updated magic and schematic files by pwhardy · 3 years, 4 months ago
- afb8cb4 Added new LICENSE, updated info.yaml by pwhardy · 3 years, 4 months ago
- 0f92e43 Corrected signal names in user_analog_project_wrapper by pwhardy · 3 years, 4 months ago
- e35fe2e Added all files for TopLevelTestStructure and supporting cells, added verilog module and added an instance into user_analog_project_wrapper by pwhardy · 3 years, 4 months ago
- 0b0d2d3 Replaced TopLevelTestStructure with TopLevleProtectStructure files by pwhardy · 3 years, 4 months ago
- 85e4631 Added the magic, gds, and verilog modules for the test structure. Still need to put the verilog instance into the wrapper and assign pin connections by pwhardy · 3 years, 4 months ago
- 517439c fix check_default missing ENV variables by Jeff DiCorpo · 3 years, 5 months ago
- 67640ef Auto updated submodule references by Git bot · 3 years, 7 months ago
- c68f39e Updated the documentation to include a description of the power-on-reset by Tim Edwards · 3 years, 7 months ago
- 13f142e Update index.rst by Manar · 3 years, 7 months ago
- 520ff4a Update index.rst by Manar · 3 years, 7 months ago
- a119592 Update index.rst by Manar · 3 years, 7 months ago
- dd3d811 Doc updates by manarabdelaty · 3 years, 7 months ago
- 55c9fff Merge branch 'main' of https://github.com/efabless/caravel_analog_user into main by manarabdelaty · 3 years, 7 months ago
- 9e46db5 Auto updated submodule references by Git bot · 3 years, 7 months ago
- f9e592b Update submodule reference to caravel-lite by manarabdelaty · 3 years, 7 months ago
- 3f75a89 Update Makefile by manarabdelaty · 3 years, 7 months ago
- 206bfb5 Update run-xor.sh by manarabdelaty · 3 years, 7 months ago
- b7fad20 [CI] update run-xor by manarabdelaty · 3 years, 7 months ago
- 9b861b2 Add pattern to dv Makefile and drop obselete openlane wrapper dir by manarabdelaty · 3 years, 7 months ago
- b07e408 Update README.md by Manar · 3 years, 7 months ago
- 7b7b2f6 Update index.rst by Manar · 3 years, 7 months ago
- 722391b Merge branch 'main' of github.com:efabless/caravel_user_project_analog into main by Tim Edwards · 3 years, 7 months ago
- e982ef8 Update README.md by Manar · 3 years, 7 months ago
- 9422266 Modified the wrapper to extend the analog pins out 4um like the rest of by Tim Edwards · 3 years, 7 months ago
- 1f15094 [CI] Add github workflows for running the precheck/dv/caravan_build by manarabdelaty · 3 years, 7 months ago
- a1553af Add docs dir by manarabdelaty · 3 years, 7 months ago
- 892f0d2 Update Makefile by manarabdelaty · 3 years, 7 months ago
- ff42add Update info.yaml to have the user_level_netlist point to the rtl netlist by manarabdelaty · 3 years, 7 months ago
- 35111e9 Corrected ngspice testbenches for change in the name of the parameter by Tim Edwards · 3 years, 7 months ago
- dba051e Modifications to the wrapper testbench schematic (not quite working by Tim Edwards · 3 years, 7 months ago
- 5cc020d Added xschem schematic and symbol for the analog project wrapper, and a by Tim Edwards · 3 years, 7 months ago
- a26abdd Redid the layout for the example analog project based on the updated by Tim Edwards · 3 years, 7 months ago
- 60e4dcb Update Makefile by manarabdelaty · 3 years, 7 months ago
- 8a1d5f2 Corrected the info.yaml file to point to the caravan.v file as the by Tim Edwards · 3 years, 7 months ago
- 6bb2165 Added layout for the user_analog_project_wrapper example. by Tim Edwards · 3 years, 7 months ago
- 5ea70cb Changed the schematics so that the resistor does not set a W by Tim Edwards · 3 years, 7 months ago
- 796099e Corrected the schematic for the proper orientation of the topmost by Tim Edwards · 3 years, 7 months ago
- dfc24ad Added xschem schematic of the POR and testbench simulations and results. by Tim Edwards · 3 years, 7 months ago
- fb13001 Simple layout, unwired (needs modifications to the project wrapper) by Tim Edwards · 3 years, 7 months ago
- a44a60b Preliminary work on the analog user project example. Added verilog RTL and by Tim Edwards · 3 years, 7 months ago
- 6af7408 Initial commit by manarabdelaty · 3 years, 7 months ago
